SML2108 SUMMIT | Alldatasheet
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1Characteristics subject to change without notice 2053 2.2 11/07/00 SML2108SUMMIT MICROELECTRONICS, Inc. ©SUMMIT MICROELECTRONICS, Inc., 2000 • 300 Orchard City Dr., Suite 131 Campbell, CA 95008 Phone 408-378-6461 FAX 408-378-6586 www.summitmicro.com PRELIMINARY !!!!! Integrated Bias Current Monitor """"" Monitors & Measures Laser Temperature Directly """"" Eliminates Need for External Thermistor & Thermal Coupling Issues """"" Alarm Output on Over-temperature Condition !!!!! Adaptive Modulation Control (AMC) """"" Adjusts Modulation Current as a Function of the Laser Temperature """"" 256 Independent Compensation Values """"" Integrated 8-Bit Modulation Control DAC !!!!! Flexible Biasing Architecture """"" Bias Control and Modulation Control: 0 to 10mA / 0 to 100 mA Source, 0 to 100mA Sink !!!!! Automatic Power Control (APC) with Integrated 10-Bit Programmable Offset """"" Automatic Initial Bias Optimization !!!!! Electronic Calibration Through 2-wire Interface Laser Diode Adaptive Power Controller SIMPLIFIED APPLICATION DIAGRAM
FEATURES
The SML2108 is an adaptive power controller for laser diodes. It is the industry's first integrated device that can directly monitor and measure a laser diode's temperature, and provide a variable modulation current. The SML2108's integrated active feedback loop is used to calibrate and control the mean and modulation power of high speed, high power laser diodes. Inherent manufacturing tolerances introduce variations of performance in laser diodes. These variations, combined with parametric changes over the laser’s extreme tem- perature range and laser ageing, call for an efficient temperature compensation scheme. Using an internal digital control loop and a programmable nonvolatile com- pensation lookup table, the SML2108 provides the most optimum adaptive power control with a minimum number of external components. The SML2108 removes the need for any manual calibra- tion of the laser control circuit, which is currently the industry standard practice. All calibration values are programmed through the 2-wire communication interface, which can be controlled by most production ATE equip- ment. Programming of configuration, control and calibration values by the user can be simplified with the interface adapter and Windows GUI software obtainable from Sum- mit Microelectronics. The SML2108 is available in 48 lead TQFP.
DESCRIPTION
2053 SAD 1.0 MODSET IN+ IMOD SML2108 LASER DIODE MONITOR DIODE Interface VDD VDD IN–
2053 2.2 11/07/00 SUMMIT MICROELECTRONICS, Inc. PRELIMINARY FUNCTIONAL BLOCK DIAGRAM SCL CE# SDA VSS VDD 6AUTOMON DETECT 10-Bit DAC 10-Bit NV Reg 10-Bit DAC Reg Config NV POR 8-Bit ADC NV Look-up Table NV Scaling & Offset ADC Read & Alarm Reg POR Reg 8-Bit DAC MOD P MOD N BIAS P BIAS N RDY VSS A ALERT# CAP1 CAP2 11 10 2053 BD 2.1 EXT TEMP5 VSS D14 VCC (All Rs 100kΩ )
2053 2.2 11/07/00 SML2108 SUMMIT MICROELECTRONICS, Inc. PRELIMINARY PIN CONFIGURATION PIN DESCRIPTIONS DETECT (12) This is the analog input from the laser monitor photodiode for the integrator circuit. There is an on-board resistance of 2MΩ between the DETECT input and CAP1 pin. CAP1 and CAP2 (11 & 10) Capacitor inputs for an external capacitor in the feedback loop of the Mean Power Control Integrator. There is an on- board capacitance of 500pF. AUTOMON (6) Active high input used to enable the internal auto-monitor function, which provides automatic adjustments to the modulation output currents (MODP and MODN) based on the internal A/D output and the values stored in the nonvolatile lookup table. This pin has an internal 100kΩ pullup. ALERT# (8) Active low, open-drain output. This pin is driven low whenever the bias current increases beyond a predefined nonvolatile threshold. This can be used to predict laser failure. SDA, SCL (4 & 5) Data and Clock lines, respectively, whose function and use are based on the industry standard I 2C interface. Lookup table values, configuration data, and D/A and A/D registers may all be accessed via these two pins of the SML2108. These pins have internal 100kΩ pullups. Address Pins for the interface provided to allow multiple devices on a single bus. These pins have internal 100kΩ pullups. RDY# (7) Active low, open-drain output. This pin is driven low whenever the internal A/D is performing a conversion, or while the on-board EEPROM is being programmed. EXT TEMP (9) Temperature input (or no connection). This pin can be programmed as an input to the ADC and can interface a temperature sensor. The EXT TEMP pin is multiplexed with the bias current to provide a means of configuring the input to the ADC. When EXT TEMP is programmed as the SDA SCL AUTOMON RDY# ALERT# EXT TEMP CAP2 CAP1 DETECT MODN MODN BIASN BIASN V SS VSS VSS VSS BIASN BIASN MODN MODN 48-Pin TQFP 2053 PCon 2.0 VSS A VSS D VDD VDD BIASP BIASP MODP MODP V DD VDD VSS VSS CE# V DD VDD BIASP BIASP MODP MODP V DD VDD VSS VSS
2053 2.2 11/07/00 SUMMIT MICROELECTRONICS, Inc. PRELIMINARY input to the ADC using bit 5 of Register 1, the converted value of the current entering this pin is used as the address of the EEPROM lookup table. In this configuration the modulation current can be controlled by temperature rather than the bias current. Refer to the application example on using the EXT TEMP pin. If this option is not used the pin should be left floating. V SS A, VSS D (13 & 14) Analog and digital low-side supplies for on-board circuitry. Must be at same potential as all other VSS pins. High-side supply for the Bias and Modulation currents and power supply input for the chip. CE# (48) The chip enable input is active low and provides an additional method of enabling the serial interface. The state of this pin has no effect on the auto-monitor function. This pin has an internal 100kΩ pullup. BIASP (17, 18, 43, & 44) High-side mean bias control current. Current source output range is programmable, with the optional ranges of 0 to 100mA or 0 to 10mA. BIASN (27, 28, 33, & 34) Low-side mean bias control current. Current sink input range is 0 to 100mA. High-side modulation control current. Current source output range is programmable, with optional ranges of 0 to 100mA or 0 to 10mA. Low-side modulation control current. Current sink input range is 0 to 100mA.
2053 2.2 11/07/00 SML2108 SUMMIT MICROELECTRONICS, Inc. PRELIMINARY *COMMENT Stresses listed under Absolute Maximum Ratings may cause perma- nent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. ELECTRICAL TABLES ABSOLUTE MAXIMUM RATINGS* (Over Recommended Operating Conditions; Voltages are relative to GND) lobmySr etemaraPs noitidnoC. niM. pyT. xaMs tinU ecnamrofrePCDAlacipyT N/So itaresioNotlangiST A Cº52=0 7B d DHTn oitrotsidcinomrahlatoT0 8– Bd noitaludomretnicinomrahkaeP noitrotsid redrOdn20 8– Bd redrOdr30 8– Bd ycaruccACD noituloseR8 s tiB gnissimonhcihwrofnoituloeR deetnaraugerasedoc 8s tiB ycaruccaevitaleR ½±B SL LND 1±B SL rorreelacsllufevitisoP2 ±B SL rorretesfforalopinU V SS V5=2 ±B SL V SS otV7.2= V6.3 2±B SL
2053 Elect Table A
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2053 2.2 11/07/00 SUMMIT MICROELECTRONICS, Inc. PRELIMINARY
2053 Elect Table B
lobmySr etemaraPs noitidnoC. niM. pyT. xaMs tinU V DD egatlovylppuS noitaludomdnasaibmumixaM tnerruc 35 .5V ID tnerrucylppuS -tuotnerrucnoitaludomdnasaiB nepostup 2A m IOL tnerrucegakaeltupnIV NI VotV0= DD 1A µ IIL tnerrucegakaeltuptuOV TUO VotV0= DD 01A µ V LO egatlovwoltuptuOI LO Am2=4 .0V V HO egatlovhgihtuptuO V DD I,V5= LO Aµ004–=4 .2V V DD I,V5.4< LO Aµ001–=V DD 2.0– V V LI egatlovwoltupnI1 .0– 3.0 × V DD V V HI egatlovhgihtupnI7 .0 × V DD 5.0V f TNI poolrotargetnI ycneuqerf 1z Hk t SUP noitazilibatspurewoP emit sselsitnatsnocemitrotargetnI sm01naht 01s m stupnIgolanA TCETEDC DAottupniTCETED0 5 .1V I PMETTXE tupnitnerrucelacslluF 6.093A µ stuptuOgolanA I NDOM noitaludomlennahc-N tnerruc 00 01– Am I PDOM noitaludomlennahc-P tnerruc 00 01A m I NSAIB tnerrucsaiblennahc-N0 0 01– Am I PSAIB tnerrucsaiblennahc-P0 0 01A m V CAD tuptuoCADtiB-010 5 .1V stuptuOlatigiD TRELAt uptuoTRELA situptuoTRELAniardnepO evitca 5A m
SUMMIT MICROELECTRONICS, Inc. ances introduce variations of performance in laser diodes. laser diode characteristics at two different temperatures.
- The ratio of light power of its on state divided by
ratio indicates that data may possibly be lost. ratio of the laser driver module. Figure 1. Laser Current Increase Caused by Temperature Increase, Constant Light Power Out
2053 Fig01
2053 2.2 11/07/00 SUMMIT MICROELECTRONICS, Inc. Figure 2. Output Block 1: Mean Power Control Figure 3. Output Block 2: IMOD The built-in integration time constant is nominally 1ms. decreased to less than 100us. effect on the contents of the nonvolatile register.
2053 Fig02
2053 Fig03
2053 2.2 11/07/00 SML2108 SUMMIT MICROELECTRONICS, Inc. PRELIMINARY the data is first placed in the volatile register. At the conclusion of the write command an internal nonvolatile write sequence initiates the storage of the volatile contents into the NV register. Note that when modifying the 10-Bit DAC output, the mean power control loop will become temporarily disrupted. It may be several milliseconds before the bias current has settled to its steady state value. Until then its value will be undefined. Modulation Current — Auto-Monitor Control The laser bias current, which relates directly to laser temperature, can be monitored using an on-board, cur- rent-sensing A/D converter. In the auto-monitor mode the 8-Bit output of the converter is used as an address to the EEPROM lookup table. The subsequent 8-Bit data output from the lookup table becomes the input for the compen- sation DAC. The 8-Bit compensation DAC output is a current in the range of 0 to 100mA and is used to control the modulation current MODP and MODN. The output block of the modulation current control is shown in Figure The lookup table provides an arbitrary mapping from bias current to modulation current. The input range to the ADC may be scaled and/or offset to provide maximum resolu- tion within the appropriate conversion space. The sample interval is programmable from 10µs to 1s. Refer to the ADC section for further details about configuring the A/D. The interface is used to program the configuration regis- ters as well as lookup table values. Lookup Table A 2k-Bit (256 x 8) memory array of on-board EEPROM comprises the internal lookup table. This array is ac- cessed via the 2-wire serial interface using a slave ad- dress of 1010 BIN. (Note: 1010BIN is the default, however this may be set to 1110BIN, depending upon the contents of Configuration Register 2.) Refer to the Bus Interface section for details on programming and reading data from the device. In the auto-monitor mode the content of the array repre- sents the transfer function between the A/D output and the final value of modulation current. Using a lookup table to implement this function allows arbitrary functions, and even nonlinear relations, to be easily realized. Also, the use of a lookup table allows each device to be customized to normalize overall module operation. Although the memory may normally be read and written as a standard memory, a security feature exists in the con- figuration settings that will prevent any external access to the array. Additionally, if the auto-monitor feature is not used, then the modulation output current may be pro- grammed to a fixed value, and the array may be used as a standard memory to store device settings, board identi- fication values, production dates, etc. 8-Bit Current Output D/A The 8-Bit D/A defines the modulation output current. Associated with this DAC are an 8-Bit volatile register and an 8-Bit nonvolatile (NV) register. The content of the volatile register determines the DAC output current. The DAC output current is given by the following relation: XOC 100mA256=× where X = the 8-Bit data stored in the volatile register. On device power-up the volatile register may be loaded with all zeroes or it may be loaded from the contents of the 8- Bit nonvolatile register. Access to the 8-Bit volatile register is obtained via the 2- wire interface at slave address 1001 BIN, word address 4. Refer to Figures 8 and 11 for details on programming and reading data from the 8-Bit register. When writing to the volatile register, the new DAC output will become valid immediately at the end of the write command. Reading the volatile register has no effect on the DAC output. Reading or writing the volatile register has no effect on the contents of the nonvolatile register. The 8-Bit NV register can only be accessed indirectly through the volatile register. The command sequence to communicate with the NV register is the same as that of the volatile register, except word address 6 is used instead of 4. When reading the NV register the data is first transferred into the volatile register where it may be accessed by the serial interface. Note that upon this transfer the DAC output will change immediately to reflect the new data. Similarly, when writing to the NV register, the data is first placed in the volatile register. At the conclusion of the write command, an internal nonvolatile write sequence initiates the storage of the volatile contents into the NV register.
2053 2.2 11/07/00 SUMMIT MICROELECTRONICS, Inc. Figure 5. Half Scale (code 10BIN) with OffsetFigure 4. Full Scale (code 11BIN) with Offset Figure 6. Quarter Scale (code 01BIN) with Offset Figure 7. Tenth Scale (code 00BIN) with Offset maximize the resolution of the ADC. current and the ADC input current.
2053 Fig04
2053 Fig05
2053 Fig06
2053 Fig07
2053 2.2 11/07/00 SML2108 SUMMIT MICROELECTRONICS, Inc. PRELIMINARY REGISTERS Register 0 2053 Reg0 1.0 REGISTER BIT MAPS The SML2108 has three user programmable, nonvolatile configuration registers. Register 0 This register is used to configure the 8-Bit ADC that monitors the bias current. Bit 7 enables the ADC alert to be latched, which will hold the ALERT pin low until the alert is reset. Bits 6, 5, and 4 are used to set the sample interval of the ADC. The input to the ADC can be scaled and offset to provide maximum resolution over the bias current. Bits 3 and 2 are used to set the full scale range of the ADC, while bits 1 and 0 are used to set the ADC offset. See the Table. Register 1 This register controls multiple functions. Bit 7 disables the alert during a manual analog-to-digital conversion of the bias current. Bit 6 selects the action that will reset an alert from the ADC. When this bit is set to a 0 any device read or write will reset the alert. When set to a 1 the alert will be reset by a low AUTOMON signal. Bit 5 is used to toggle the source of the ADC input between the I BIAS current and the EXT TEMP signal. Bit 2 initializes the input of the 10 bit DAC to either zero or a stored value from a nonvolatile register when the device is powered up. Bit 1 initializes the input of the 8 bit DAC to either zero or a stored value from a nonvolatile register when the device is powered up. Bit 0 sets the maximum P-channel bias current (I BIASP ) and modulation current (IMODP ) to either 10mA or 100mA. Register 2 This register controls several functions related to the bus interface. Bits 7 and 6 control the read and write access to the configuration registers. It is imperative that register 2 be programmed properly to prevent an inadvertent lockout. Bit 5 determines whether the memory array is available or locked. Bit 4 selects the device type address for accessing the memory array, while bit 3 determines whether the device must receive a bus address that corresponds to the biasing of the address pins. Bit 2 is used to enable an alert condition on the ADC to shut down the bias current. Bits 1 & 0 are unused. 76543210 noitcnuFCDA trelA lavretnIelpmaSCDAe gnaRCDAt esffOCDA 0 xxx xx xx dehctaltontrelA 1 dehctaltrelA x 000 lavretnielpmassµ5 001 sµ02" " 01 0 sµ061" " 011 ""sm82.1 100 sm52.6" " 10 1 sm52" " 110 sm002" " 111 s6.1" " xxx 00 tnerrucsaibelacslluf01/1 01 tnerrucsaibelacslluf4/1 10 tnerrucsaibelacslluf2/1 11 tnerrucsaibelacslluF xx 00 tesffooN 01 tesffotnerrucsaibelacslluffo4/1 10 tesffotnerrucsaibelacslluffo2/1 11 tesffotnerrucsaibelacslluffo4/3
2053 2.2 11/07/00 SUMMIT MICROELECTRONICS, Inc. PRELIMINARY Register 2 Register 1 2053 Reg1 1.0 2053 Reg2 1.0 76 5 4 32 1 0 noitcnuF sseccAretsigeR yromeM sseccA eciveD sserddA niP sserddA trelA noitcA desunU x x x x xx etirWrodaeRon;dekcolsretsigeRllA 01 etirWon;sretsigeRlladaeR 10 daeRon;sretsigeRllaetirW 11 sretsigeRllaetirWdnadaeR xx 0 elbaliavaMORPEE 1 dekcolMORPEE x 0 0101sisserdAepyTeciveD NIB 1 0111sisserdAepyTeciveD NIB x 0 desaibnipsserddaotsdnopseR ylnosserdda 1 sserddasubynaotsdnopseR x 0 trelaybdetceffanutnerrucsaiB noitidnoc 1 tnerrucsaibnwodstuhsnoitidnoctrelA 76543210 noitcnuFtrelA trelA teseR CDA tupnI desunU tiB-01 CAD tiB-8 CAD I PSAIB 0 x x xx x x x noisrevnoclaunamgniruddewollatontrelA 1 noisrevnoclaunamgniruddewollatrelA x 0 etirWrodaeRybtesertrelA 1 nipNOMOTUAnowoLybtesertrelA x
0 I NSAIB Iro PSAIB CDAottupnitnerruc
1 CDAottupninipPMETTXE
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1 I:Am001sitnerrucxaM PSAIB I, PDOM
SUMMIT MICROELECTRONICS, Inc. rate, and some support the alternative 400kHz clock. Figure 8. I2C Data Timing remain stable when the Clock is high. Table 1. I
2053 Fig08
2053 2.2 11/07/00 SUMMIT MICROELECTRONICS, Inc. Figure 9. I Figure 10. Acknowledge Timing a Stop on the clock pulse following the NACK. internal non-volatile write cycle. recognizing a Start condition and its DTI. further data transmission. See Figure 12. Figure 11. Typical Master Address Byte Transmission
2053 Fig09
2053 Fig10
2053 Fig11
SUMMIT MICROELECTRONICS, Inc. Figure 12. Read Figure 13. Write continues to output data for each Acknowledge received. memory will continue to output data. the lookup table are illustrated in Figures 14 through 24.
2053 Fig13
2053 Fig12
2053 2.2 11/07/00 SUMMIT MICROELECTRONICS, Inc. Figure 14. Look-up Table Page/Byte Write Figure 15. Look-up Table Random Address Read with Dummy Write Figure 16. Look-up Table Sequential Read with Dummy Write
2053 Fig14
2053 Fig15
SUMMIT MICROELECTRONICS, Inc. Figure 18. 8-Bit DAC Volatile Register Read with Dummy Write Figure 17. 8-Bit DAC Volatile Register Write Figure 20. 8-Bit DAC Non-volatile Register Read with Dummy Write Figure 19. 8-Bit DAC Non-volatile Register Write
2053 Fig17
2053 Fig19
2053 Fig20
2053 Fig18
2053 2.2 11/07/00 SUMMIT MICROELECTRONICS, Inc.
2053 Fig22
Figure 21. 10-Bit DAC Volatile Register Write Figure 22. 10-Bit DAC Nonvolatile Register Write Figure 23. 10-Bit DAC Volatile Register Read with Dummy Write Figure 24. 10-Bit DAC Nonvolatile Register Read with Dummy Write
2053 Fig21
2053 Fig23
2053 Fig24
2053 2.2 11/07/00 SML2108 SUMMIT MICROELECTRONICS, Inc. PRELIMINARY APPLICATION EXAMPLE USING EXTERNAL TEM- PERATURE INPUT The EXT TEMP pin of the SML2108 allows the input of the internal ADC to be driven from an external device, rather than a mirrored version of the bias current. Figure 25 shows an example using a National Semiconductor LM334 to deliver a current into the SML2108 that is proportional to absolute temperature. The scale and offset features of the ADC input can be used to center this current and maximize the full range of the look-up table. For this application the current I SET coming out of the LM334 and into the EXT TEMP pin of the SML2108 is given by the following equation: I SET = 227µV / oK / RSET For example, using a value of 210Ω for RSET yields a current of 295µA at 0oC and 387µA at 85oC. Next select scale and offset values of the ADC input that will optimize the current range of the LM334. Nominal full- scale input current of the ADC is 390.6µA (= 100mA/256). By setting the input offset to ¾ scale (293µA) and the full- scale range to ¼ scale (97.6µA), then the zero scale of the internal ADC becomes 293µA, and the full-scale is 390.6µA. This represents a temperature range of approxi- mately –2 oC to 88oC using a 210Ω resistor in the configu- ration shown. (These settings correspond to configuration Register 0, Bits 3 - 0 set to 7 HEX .) Figure 25. Example of an External Temperature
APPLICATIONS
2053 Fig25
210Ω ±1% ISET
2053 2.2 11/07/00 SUMMIT MICROELECTRONICS, Inc. PRELIMINARY
ORDERING INFORMATION
48 PIN TQFP PACKAGE
0.50 BSC
DETAIL "A" 1 ref DETAIL "B"A B 1.60 max 1.35 – 1.45 0.22 8.975 – 9.025 0.353 – 0.355 6.5 – 7.1 0.271 – 0.280 6.5 – 7.1 0.271 – 0.280 8.975 – 9.025 0.353 – 0.355 0.02 0.063 0.053 – 0.057 0.10 – 0.20 0.004 – 0.008 0.45 – 0.75 0.018 – 0.030 0.076 0.003 0.009 mm. in. 20xx Pckg 1.0 SML2108 F Base Part Number Package F = 48 Pin TQFP
2053 2.2 11/07/00 SML2108 SUMMIT MICROELECTRONICS, Inc. PRELIMINARY NOTICE SUMMIT Microelectronics, Inc. reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. SUMMIT Microelectronics, Inc. assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained herein reflect representative operating parameters, and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked, SUMMIT Microelectronics, Inc. shall not be liable for any damages arising as a result of any error or omission. SUMMIT Microelectronics, Inc. does not recommend the use of any of its products in life support or aviation applications where the failure or malfunction of the product can reasonably be expected to cause any failure of either system or to significantly affect their safety or effectiveness. Products are not authorized for use in such applications unless SUMMIT Microelectronics, Inc. receives written assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and (c) potential liability of SUMMIT Microelectronics, Inc. is adequately protected under the circumstances. © Copyright 2000 SUMMIT Microelectronics, Inc. I2C is a trademark of Philips Corporation.