SMJ44400

SMJ44400 MICROSS | Alldatasheet

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Technical content

Rev. 2.2 01/10 Micross Components reserves the right to change products or specifi cations without notice.

FEATURES

• Organized 1,048,576 x 4 OPTIONS MARKING
• Timing 80ns access -80 100ns access -10 120ns access -12
• Package(s) Ceramic DIP (400mils) JD No. 113 Ceramic Flatpack HR No. 308
• Operating Temperature Ranges Military (-55 oC to +125oC) M PIN ASSIGNMENT (Top View) AVAILABLE AS MILITARY SPECIFICATIONS
• SMD 5962-90847
• MIL-STD-883 20-Pin DIP (JD) 20-Pin Flatpack (HR) (400 MIL) GENERAL DESCRIPTION The SMJ44400 is a series of 4,194,304-bit dynamic random-access memories (DRAMs), organized as 1,048,576 words of four bits each. This series employs state-of-the-art technology for high performance, reliability, and low-power operation. The SMJ44400 features maximum row access times of 80ns, 100ns, and 120ns. Maximum power dissipation is as low as 360mW operating and 22mW standby. All inputs and outputs, including clocks, are compatible with Series 54 TTL. All addressses and data-in lines are latched on- chip to simplify system design. Data out is unlatched to allow greater system fl exibility. 1M x 4 DRAM DYNAMIC RANDOM-ACCESS MEMORY For more products and information please visit our web site at www.micross.com
• Single +5V ±10% power supply
• Enhanced Page-Mode operation for faster memory access

3 Higher data bandwidth than conventional page-mode

3 Random Single-Bit Access within a row with a column

• CAS\\-Before-RAS\\ (CBR) Refresh
• Long Refresh period: 1024-cycle Refresh in 16ms (Max)
• 3-State unlatched Output
• Low Power Dissipation
• All Inputs/Outputs and Clocks are TTL Compatible
• Processing to MIL-STD-883, Class B available DQ1 DQ2 RAS\\ Vcc Vss DQ4 DQ3 CAS\\ OE\\ The SMJ44400 is offered in a 400-mil, 20-pin ceramic side- brazed dual-in-line package (JD suffi x) and a 20-pin ceramic fl atpack (HR suffi x) that are characterized for operation from -55°C to +125°C. OPERATION Enhanced Page Mode Enhanced page-mode operation allows faster memory ac- cess by keeping the same row address while selecting random column addresses. The time for row-address setup and hold and address multiplex is eliminated. The maximum number of columns that can be accessed is determined by the maximum RAS\\ low time and the CAS\\ page cycle time used. With minimum CAS\\ page cycle time, all 1024 columns speci fi ed by column addresses A0 through A9 can be accessed without intervening RAS\\ cycles. Unlike conventional page-mode DRAMs, the col- umn address buffers in this device are activated on the (continued) Pin Name Function A0 - A9 Address Inputs CAS\\ Column-Address Strobe DQ1 - DQ4 Data Inputs/Outputs OE\\ Output Enable RAS\\ Row-Address Strobe W\\ Write Enable Vcc 5V Supply Vss Ground

Rev. 2.2 01/10 Micross Components reserves the right to change products or specifi cations without notice. Enhanced Paga Mode (continued) falling edge of RAS\\. The buffers act as transparent or fl ow- through latches while CAS\\ is high. The falling edge of CAS\\ latches the column addresses. This feature allows the SMJ44400 to operate at a higher data bandwidth then con- ventional page-mode parts, since data retrieval begins as soon as column address is valid rather than when CAS\\ goes low. This performance improvement is referred to as enhanced page mode. Valid column address can be presented immediately after row address hold time has been satisfi ed, usually well in advance of the maximum (access time from column address) has been satisfi ed. In the event that column addresses for the next cycle are valid at the time CAS\\ goes high, access time for the next cycle is determined by the later occurrence of t CAC or tCPA (access time form rising edge of CAS\\). Address (A0-A9) Twenty address bits are required to decode 1 of 1,048,576 storage cell locations. Ten row-address bits are set up on in- puts A0 through A9 and latched onto the chip by RAS\\. The ten column-address bits are set up on pins A0 through A9 and latched onto the chip by CAS\\. All addresses must be stable on or before the falling edges of RAS\\ and CAS\\. RAS\\ is similar to a chip enable in that it activates the sense amplifi ers as well as the row decoder. CAS\\ is used as a chip select, activat- ing the output buffer as well as latching the address bits into the column-address buffer. Write Enable (W\\) The read or write mode is selected through W\\. A logic high on the W\\ input selects the read mode and a logic low se- lects the write mode. The write-enable terminal can be driven from standard TTL circuits without a pullup resistor. The data input is disabled when the read mode is selected. When W\\ goes low prior to CAS\\ (early write), data out reamins in the high-impedance state for the entire cycle permitting a write operation independent of the state of OE\\. This permits early- write operation to be completed with OE\\ grounded. Data In/Out (DQ1 - DQ4) The high-impedance output buffer provides direct TTL compatibility (no pullup resistor required) with a fanout of two Series 54 TTL loads. Data out is the same polarity as data in. The output is in the high-impedance ( fl oating) state until CAS\\ and OE\\ are brought low. In a read cycle the output becomes valid after all access times are satis fi ed. The output remains valid while CAS\\ and OE\\ are low. CAS\\ or OE\\ going high returns it to the high-impedance state. Output Enable (OE\\) OE\\ controls the impedance of the output buffers. When OE\\ is high, the buffers remain in the high-impedance state. Bringing OE\\ low during a normal cycle activates the output buffers, putting them in the low-impedance state. It is neces- sary for both RAS\\ and CAS\\ to be brought low for the output buffers to go into the low-impedance state. Once in the low- ompedance state, they remain in the low-impedance state until either OE\\ or CAS\\ is brought high. Refresh A refresh operation must be performed at least once every 16ms to retain data. This can be achieved by strobing each of the 1024 rows (A0-A9). A normal read or write cycle refreshes all bits in each row that is selected. A RAS\\-only operation can be used by holding CAS\\ at the high (inactive) level, conserving power as the output buffer remains in the high-impedance state. Externally generated addresses must be used for a RAS\\-only refresh. Hidden refresh can be per- formed while maintaining valid data at teh output pin. This is accomplished by holding CAS\\ at V IL after a read operation and cycling RAS\\ after a speci fi ed precharge period, similar to a RAS\\-only refresh cycle. The external address is ignored during the hidden refresh cycles. CAS\\-before-RAS\\ (CBR) and hidden refresh CBR refresh is utilized by bringing CAS\\ low earlier than RAS\\ (see parameter t CSR) and holding it low after RAS\\ falls (see parameter tCSR). For successive CBR refresh cycles, CAS\\ can remain low while cycling RAS\\. The external address is ignored and the refresh address is generated internally. During CBR refresh cycles the outputs remain in the high- impedance state. Hidden refresh can be performed while maintaining valid data at the output pins. Thsi is accomplished by holding CAS\\ at VIL after a read operation. RAS\\ is cycled after the speci fi ed read cycle parameters are met. Hidden refresh can also be used in conjuction with an early-write cycle. CAS\\ is maintained at VIL while RAS\\ is cycled, once all the specifi ed early-write parameters are met. Externally generated addresses must be used to specify the location to be accessed during the initial RAS\\ cycle of a hidden refresh operation. Subsequent RAS\\ cycles (refresh cycles) use the internally-generated addresses and the external address is ignored. Power Up To achieve proper device operation, an initial pause of 200μs followed by a minimum of eight initialization cycles is (continued)

Rev. 2.2 01/10 Micross Components reserves the right to change products or specifi cations without notice. Power Up (continued) required after full Vcc level is achieved. These eight initializa- tion cycles need to include at least one refresh (RAS\\-only or CBR) cycle. Test Mode An industry standard Design For Test (DFT) mode is incorporated in the SMJ44400. A CBR with W\\ low (WCBR) cycle is used to enter test mode. In the test mode, data is written into and read from eight sections of the array in parallel. All data is written into the array through DQ1. Data is com- parted upon reading and if all bits are equal, all DQ pins go high. If any one bit is different, all the DQ pins go low. Any combination read, write, read-write, or page-mode can be used in the test mode. The test mode function reduces test times by enabling the 1M x 4-bit DRAM to be tested as if it were a 512K DRAM where column address 0 is not used. A RAS\\-only or CBR refresh cycle is used to exit the DFT mode. LOGIC SYMBOL1 RAM 1024K x 4 RAS\\ CAS\\ OE\\ DQ1 DQ2 DQ3 DQ4 23,21D G25 20D10/21D0 20D19/21D9 C20[Row] G23/[Refresh Row] 24[Power Down] C21[Column] G24 23C22 24,25EN A 0 1 048 575 A, 22D A, Z26 1. This symbol is in accordance with ANSI/IEEE Std. 91-1984 and IEC Publication 617-12. The pinouts illustrated are for the JD package.

Rev. 2.2 01/10 Micross Components reserves the right to change products or specifi cations without notice. FUNCTIONAL BLOCK DIAGRAM RAS\\ CAS\\ W\\ OE\\ Timeing and Control Column Address Buffers Row Address Buffers R O W D E C O D E R Column Decode Sense Amplifiers 128K Array 128K Array 128K Array 128K Array 128K Array 128K Array 16 16 I/O Buffers 4 of 16 Selection Data In Reg. Data Out Reg. ABSOLUTE MAXIMUM RATINGS* *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional opera- tion of the device at these or any other conditions above those indicated in the operation section of this specifi ca- tion is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. ** Junction temperature depends upon package type, cycle time, loading, ambient temperature and airfl ow. RECOMMENDED OPERATING CONDITIONS SYM DESCRIPTION MIN NOM MAX UNIT VCC Supply Voltage 4.5 5 5.5 V VIH High-Level Input Voltage 2.4 6.5 V VIL Low-Level Input Voltage1 -1 0.8 V TA Minimum Operating Temperature -55 °C TC Maximum Operating Case Temperature 125 °C 1. The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only.

Rev. 2.2 01/10 Micross Components reserves the right to change products or specifi cations without notice. SYM PARAMETER TEST CONDITIONS MIN MAX MIN MAX MIN MAX UNIT VOH High-level output voltage IOH = -5mA 2.4 2.4 2.4 V VOL Low-level output voltage IOL = 4.2mA 0.4 0.4 0.4 V II Input current (leakage) VCC = 5.5V, VI = 0V to 6.5V, All other pins = 0V to VCC ±10 ±10 ±10 μA IO Output current (leakage) VCC = 5.5V, VO = 0V to VCC, CAS\\ High ±10 ±10 ±10 μA ICC1 Read - or write-cycle current1 VCC = 5.5V, Minimum cycle 85 80 70 mA ICC2 Standby current After 1 memory cycle, RAS\\ and CAS\\ High, VIH = 2.4V 444 m A ICC3 Average refresh current (RAS\\ only, or CBR\\)1 VCC = 5.5V, Minimum cycle, RAS\\ cycling, CAS\\ High (RAS\\ only), RAS\\ Low after CAS\\ Low (CBR) 85 75 65 mA I CC4 Average page current2 VCC = 5.5V, tPC = minimum, RAS\\ Low, CAS\\ cycling 50 40 35 mA -8 -10 -12 ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS (-55oC<TA<125oC or -40oC to +85oC; Vcc = 5V +10%) NOTES: 1. Measured with a maximum of one address change while RAS\\ = VIL. 2. Measured with a maximum of one address change while CAS\\ = VIH. 3. VCC = 5V ±0.5V and the bias on the pins under test is 0V . Capacitance is sampled only at initial design and after any major change. 4. tOFF and tOEZ are specifi ed when the output is no longer driven. The outputs are disabled by bringing either OE\\ or CAS\\ High. CAPACITANCE (f = 1MHz)3 SYM PARAMETER MAX UNIT Ci(A) Input capacitance, address inputs 7 pF Ci(RC) Input capacitance, strobe inputs 10 pF Ci(W) Input capacitance, write-enable inputs 10 pF CO Output capacitance 10 pF SWITCHING CHARACTERISTICS (-55oC<TA<125oC or -40oC to +85oC; Vcc = 5V +10%) -8 -10 -12 SYM PARAMETERS MAX MAX MAX UNIT tAA Access time from column address 40 45 55 ns tCAC Access time from CAS\\ low 20 25 30 ns tCPA Access time from column precharge 45 50 55 ns tRAC Access time from RAS\\ low 80 100 120 ns tOEA Access time from OE\\ low 20 25 30 ns tOFF Output disable time after CAS\\ High4 20 25 30 ns tOEZ Output disable tiem after OE\\ High4 20 25 30 ns

Rev. 2.2 01/10 Micross Components reserves the right to change products or specifi cations without notice. TIMING REQUIREMENTS (-55oC<TA<125oC or -40oC to +85oC; Vcc = 5V +10%) SYM PARAMETER MIN MAX MIN MAX MIN MAX UNIT tRC Cycle time, random read or write1 150 180 210 ns tRWC Cycle time, read-write 205 245 285 ns tPC Cycle time, page-mode read or write2 50 60 65 ns tPRWC Cycle time, page-mode read-write 100 120 135 ns tRASP Pulse duration, page mode, RAS\\ low3 80 100000 100 100000 120 100000 ns tRAS Pulse duration, nonpage mode, RAS\\ low3 80 10000 100 10000 120 10000 ns tCAS Pulse duration, CAS\\ low4 20 10000 25 10000 30 10000 ns tCP Pulse duration, CAS\\ High 10 10 15 ns tRP Pulse duration, RAS\\ High (precharge) 60 70 80 ns tWP Pulse duration, write 15 20 25 ns tASC Setup time, column address before CAS\\ low 0 0 0 ns tASR Setup time, row address before RAS\\ low 0 0 0 ns tDS Setup time, data5 000 n s tRCS Setup time, read before CAS\\ low 0 0 0 ns tCWL Setup time, W\\ low before CAS\\ high 20 25 30 ns tRWL Setup time, W\\ low before RAS\\ high 20 25 30 ns tWCS Setup time, W\\ low before CAS\\ low (early-write operation only) 000 n s tWSR Setup time, W\\ High (CBR refresh only) 10 10 10 ns tCAH Hold time, column address after CAS\\ low 15 20 20 ns tDHR Hold time, data after RAS\\ low 60 75 90 ns tDH Hold time, data5 15 20 25 ns tAR Hold time, column address after CAS\\ low4 60 75 90 ns tRAH Hold time, row address after RAS\\ low 10 15 15 ns tRCH Hold time, read after CAS\\ High6 000 n s tRRH Hold time, read after RAS\\ High6 000 n s tWCH Hold time, write after CAS\\ low (early-write operation only) 15 20 25 ns tWCR Hold time, write after RAS\\ low4 60 75 90 ns tWHR Hold time, W\\ High (CBR refresh only) 10 10 10 ns tOEH Hold time, OE\\ command 20 25 30 ns tROH Hold time, RAS\\ referenced to OE\\ 20 25 30 ns tAWD Delay time, column address to W\\ low (read-write operation only) 70 80 90 ns tCHR Delay time, RAS\\ low to CAS\\ High (CBR refresh only) 20 20 25 ns tCRP Delay time, CAS\\ High to RAS\\ low 0 0 0 ns tCSH Delay time, RAS\\ low to CAS\\ High 80 100 120 ns tCSR Delay time, CAS\\ low to RAS\\ low (CBR refresh only) 10 10 10 ns tCWD Delay time, CAS\\ low to W\\ low (read-write operation only) 50 60 70 ns -8 -10 -12 NOTES: 1. All cycle times assume tT = 5ns. 2. To assure tPC min, tASC should be > tCP. 3. In a read-write cycle, tRWD and tRWL must be observed. 4. In a read-write cycle, tCWD and tCWL must be observed. 5. Referenced to the later of CAS\\ or W\\ in write operations. 6. Either tRRH or tRCH must be satisfi ed for a read cycle.

Micross Components reserves the right to change products or specifi cations without notice.

1. Maximum value specifi ed only to assure access time.
2. Valid data is presented at the outputs after all access times are satisfi ed but can go from the high-impedance state to an invalid-data state prior to the specifi ed access times as the outputs are driven when
3. Transition times (rise and fall) for RAS\\ and CAS\\ are to be a minimum of 3ns and a maximum of 50ns.

Figure 1. Load Circuit for Timing Parameters

1. CL includes probe and fi xture capacitance.

Rev. 2.2 01/10 Micross Components reserves the right to change products or specifi cations without notice. READ-CYCLE TIMING NOTES: 1. Valid data is presented at the outputs after all access times are satisfi ed but can go from the high-impedance state to an invalid-data state prior to the specifi ed access tiems as the outputs are driven when CAS\\ and OE\\ are low.

Rev. 2.2 01/10 Micross Components reserves the right to change products or specifi cations without notice. EARLY-WRITE-CYCLE TIMING

Rev. 2.2 01/10 Micross Components reserves the right to change products or specifi cations without notice. WRITE-CYCLE TIMING

Rev. 2.2 01/10 Micross Components reserves the right to change products or specifi cations without notice. READ-WRITE CYCLE TIMING NOTES: 1. Valid data is presented at the outputs after all access times are satisfi ed but can go from the high-impedance state to an invalid-data state prior to the specifi ed access tiems as the outputs are driven when CAS\\ and OE\\ are low. (1)

Rev. 2.2 01/10 Micross Components reserves the right to change products or specifi cations without notice. ENHANCED-PAGE-MODE READ-CYCLE TIMING NOTES: 1. Valid data is presented at the outputs after all access times are satisfi ed but can go from the high-impedance state to an invalid-data state prior to the specifi ed access tiems as the outputs are driven when CAS\\ and OE\\ are low. 2. Access time is tCPA or tAA dependent. (1) (2) (2)

Rev. 2.2 01/10 Micross Components reserves the right to change products or specifi cations without notice. ENHANCED-PAGE-MODE WRITE-CYCLE TIMING2 NOTES: 1. Referenced to CAS\\ or W\\, whichever occurs last. 2. A read cycle or a read-write cycle can be intermixed with write cycles as long as read and read-write timing specifi cations are not violated. (1) (1)

Rev. 2.2 01/10 Micross Components reserves the right to change products or specifi cations without notice. ENHANCED-PAGE-MODE READ-WRITE-CYCLE TIMING2 NOTES: 1. Valid data is presented at the outputs after all access times are satisfi ed but can go from the high-impedance state to an invalid-data state prior to the specifi ed access times as the outputs are driven when CAS\\ and OE\\ are low. 2. A read or write cycle can be intermixed with read-write cycles as long as the read and write timing specifi cations are not violated. (1) (1)

Rev. 2.2 01/10 Micross Components reserves the right to change products or specifi cations without notice. RAS\\-ONLY REFRESH TIMING

Rev. 2.2 01/10 Micross Components reserves the right to change products or specifi cations without notice. AUTOMATIC-CBR-REFRESH-CYCLE TIMING

Rev. 2.2 01/10 Micross Components reserves the right to change products or specifi cations without notice. HIDDEN-REFRESH-CYCLE (READ) TIMING NOTES: 1. Valid data is presented at the outputs after all access times are satisfi ed but can go from the high-impedance state to an invalid-data state prior to the specifi ed access times as the outputs are driven when CAS\\ and OE\\ are low. (1)

Rev. 2.2 01/10 Micross Components reserves the right to change products or specifi cations without notice. MECHANICAL DEFINITIONS* Micross Case #113 (Package Designator JD) SMD 5962-90847, Case Outline U NOTE: These dimensions are per the SMD. Micross’ package dimensional limits may differ, but they will be within the SMD limits. * All measurements are in inches. eA c A Q L e bb2S1 D E Pin 1 MIN MAX A --- 0.175 b 0.015 0.021 b2 0.045 0.065 c 0.008 0.014 D 0.980 1.030 D1 0.890 0.910 E 0.380 0.410 eA 0.385 0.420 e Q 0.015 0.060 L 0.125 0.200 S1 --- 0.070 SYMBOL SMD Specifications

0.100 BSC

Rev. 2.2 01/10 Micross Components reserves the right to change products or specifi cations without notice. MECHANICAL DEFINITIONS* Micross Case #308 (Package Designator HR) SMD 5962-90847, Case Outline X NOTE: These dimensions are per the SMD. Micross’ package dimensional limits may differ, but they will be within the SMD limits. * All measurements are in inches. D EL e b S cA Q MIN MAX A 0.080 0.100 b 0.015 0.021 c 0.004 0.010 D 0.690 0.710 E 0.483 0.497 e L 0.340 0.370 Q 0.025 0.035 S 0.101 0.133 SYMBOL SMD Specifications

0.050 TYP

Rev. 2.2 01/10 Micross Components reserves the right to change products or specifi cations without notice. *AVAILABLE PROCESSES M = Extended Temperature Range -55 oC to +125oC

ORDERING INFORMATION

EXAMPLE: SMJ44400-12JDM Device Number Speed ns Package Type Process SMJ44400 -80 JD /* SMJ44400 -10 JD /* SMJ44400 -12 JD /* EXAMPLE: SMJ44400-80HRM Device Number Speed ns Package Type Process SMJ44400 -80 HR /* SMJ44400 -10 HR /* SMJ44400 -12 HR /*

Rev. 2.2 01/10 Micross Components reserves the right to change products or specifi cations without notice. MICROSS TO DSCC PART NUMBER CROSS REFERENCE* Micross Package Designator JD TI Part #** SMD Part # SMJ44400-12/JDM 5962-9084701MUA SMJ44400-10/JDM 5962-9084702MUA SMJ44400-80/JDM 5962-9084703MUA *Micross part number is for reference only. Orders received referencing the SMD part number will be processed per the SMD. Parts are listed on SMD under the old Texas Instruments part number. Micross purchased this product line in November of 1999. Micross Package Designator HR TI Part # SMD Part # SMJ44400-12/HRM 5962-9084701MXA SMJ44400-10/HRM 5962-9084702MXA SMJ44400-80/HRM 5962-9084703MXA