SMH4042ASAHM

SMH4042A SUMMIT | Alldatasheet

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1Characteristics subject to change without notice 2070 9.1 5/27/03 SMH4042ASUMMIT MICROELECTRONICS, Inc. ©SUMMIT MICROELECTRONICS, Inc., 2003 • 1717 Fox Drive, San Jose, CA 95131  Phone 408-436-9890  FAX 408-436-9897  www.summitmicro.com Preliminary /G6CFull Voltage Control for Hot Swap Applications /G7715V High Side Driver Generation Allows use of Low On Resistance N-Channel FETs /G77Under-Voltage Lockout /G77Electronic Circuit Breakers /G77Card Insertion Detection /G77Host VCC Detection /G77Card Voltage Sequencing Distributed Power Hot-Swap Controller for CompactPCI FUNCTIONAL BLOCK DIAGRAM

FEATURES

/G6CFlexible Reset Control /G77Low Voltage Resets /G77Host Reset Filtering /G77Soft Reset /G6CAdjustable Power On Slew Rate /G6CSuppoprts Mixed Voltage Cards /G6CTwo Wire I2C Serial Data Interface /G774k-Bit E2PROM Memory SCL SDA EEPROM Memory Array PWR_EN PCI_RST# VSEL –CBI_324 CBI_5 HST_3V_MON CARD_3V_MON

25 CARD_5V_MON

1.25V VCC LOCAL_PCI_RST 20 LOCAL_PCI_RST# 9

3 ISLEW

SGNL_VLD# HEALTHY# 15 DRVREN# 2 FAULT# 4 27VGATE5 VGATE3 1VREF GND 12BD_SEL2# BD_SEL1# CONTROL ASSOCIATE MEMBER

2070 9.1 5/27/03 SUMMIT MICROELECTRONICS, Inc. PIN CONFIGURATION The SMH4042A is a fully integrated hot swap controller that provides complete power control for add-in cards ranging in use for basic hot swap systems to high availability CompactPCI systems. It detects proper insertion of the card and senses valid supply voltage levels at the backplane. Utilizing external low on-resistance N-channel MOSFETs, card power is ramped by two high-side driver outputs that are slew-rate limited at 250V/s. The SMH4042A continuously monitors the host supplies, the add-in card supplies and the add-in card current. If the SMH4042A detects the current is higher than the programmed value it will shut down the MOSFETs and issue a fault status back to the host.

DESCRIPTION

The internal 512 × 8 E2PROM can be used as configuration memory for the individual card or as general purpose memory. The proprietary Data Download mode provides a more direct interface to the E 2PROM, simplifying access by the add-in card’s controller or ASIC. Programming of configuration, control and calibration values by the user can be simplified with the interface adapter and Windows GUI software obtainable from Summit Microelectronics. CBI_5 DRVREN# ISLEW FAULT# 1VREF VSEL PWR_EN LOCAL_PCI_RST# BD_SEL2# BD_SEL1# GND VCC VGATE5 nc CARD_5V_MON CBI_3 HST_3V_MON VGATE3 CARD_3V_MON LOCAL_PCI_RST SCL SDA PCI_RST# SGNL_VLD# HEALTHY#

2070 PCon

2070 9.1 5/27/03 SMH4042A SUMMIT MICROELECTRONICS, Inc. 3 A0 (8) Address 0 is not used by the memory array. It can be connected to ground or left floating. It must not be connected V CC. A1, A2 (10, 11) Address inputs 1 and 2 are used to set the two-bit device address of the memory array. The state of these inputs will determine the device address for the memory if it is on a two-wire bus with multiple memories with the same device type identifier. SCL (19) The SCL input is used to clock data into and out of the memory array. In the write mode, data must remain stable while SCL is HIGH. In the read mode, data is clocked out on the falling edge of SCL. SDA (18) The SDA pin is a bidirectional pin used to transfer data into and out of the memory array. Data changing from one state to the other may occur only when SCL is LOW, except when generating START or STOP conditions. SDA is an open-drain output and may be wire-ORed with any number of open-drain outputs. CARD_3V_MON (21) This input monitors the card-side 3.3V supply. If the input falls below V TRIP then the HEALTHY# and SGNL_VLD# outputs are de-asserted and the reset outputs are driven active. CARD_5V_MON (25) This input monitors the card-side 5V supply. If the input falls below V TRIP then the HEALTHY# and SGNL_VLD# outputs are de-asserted and the reset outputs are driven active. CBI_3 (24) CBI_3 is the circuit breaker input for the low supply. With a series resistor placed in the supply path between VCC3 and CBI_3, the circuit breaker will trip whenever the voltage across the resistor exceeds 50mV. CBI_5 (1) CBI_5 is the circuit breaker input for the supply voltage. With a series resistor placed in the supply path between the 5V early power and CBI_5, the circuit breaker will trip whenever the voltage across the resistor exceeds 50mV. PIN DESCRIPTIONS HST_3V_MON (23) This input monitors the host 3.3V supply and it is used as a reference for the circuit breaker comparator. If VCC3 falls below V TRIP then SGNL_VLD# is de-asserted, the high side drivers are disabled, and LOCAL_PCI_RST# is asserted. ISLEW (3) A Diode-connected NFET input. It may be used to adjust the 250V/s default slew rate of the high-side driver outputs. PCI_RST# (17) A TTL level reset input signal from the host interface. A high to low transition (held low longer than 40ns) will initiate a reset sequence. The LOCAL_PCI_RST# and LOCAL_PCI_RST outputs will be driven active for a minimum period of t PURST. If the PCI_RST# input is still held low after t PURST times out the reset outputs will continue to be driven until PCI_RST# is released. PWR_EN (7) A TTL level input that allows the host to enable or disable the power to the individual card. During initial power up this signal would start in a low state, and then be driven high during software initialization. If this signal is driven low then the power supply control outputs will be driven into the inactive state and the reset signals asserted. In a “non-High Availability” system this input can be tied high. The PWR_EN input is also used to reset the SMH4042A circuit breakers. After an over-current condi- tion is detected the VGATE outputs can be turned back on by first taking PWR_EN low then returning it high. VSEL (6) A TTL level input used to determine which of the host power supply inputs will be monitored for valid voltage and reset generation. This is a static input and the pin should be tied to V CC or ground through a resistor. VSEL is high for 3.3V power. VSEL is low for 5V or mixed mode power. VCC (28) The power supply input. It is monitored for power integrity. If it falls below the 5V sense threshold (V TRIP) and the VSEL input is low then the SGNL_VLD# and HEALTHY# signals are de-asserted, the high side drivers disabled, and reset outputs asserted. On a CompactPCI board this must be connected to early power.

2070 9.1 5/27/03 SUMMIT MICROELECTRONICS, Inc. GND (14) Power supply return line. Ground should be applied at the same time as early power. BD_SEL1#, BD_SEL2# (13, 12) These are active low TTL level inputs with internal pull- ups to V CC. When pulled low they indicate full board insertion. On the host side the signals should be directly tied to ground. In a “High Availability” application these inputs can be the last pins to mate with the backplane. Alternatively, they can be actively driven by the host, or be connected to switches interfaced to the board ejectors, or any combination. Regardless, both inputs must be low before the SMH4042A will begin to turn on the backend voltage. DRVREN# (2) An open-drain, active-low output that indicates the status of the 3 volt and 5 volt high side driver outputs (VGATE5 and VGATE3). This signal may also be used as a switching signal for the 12 volt supply. FAULT# (4) An open-drain, active-low output. It will be driven low whenever an over-current condition is detected. It will be reset at the same time that the VGATE outputs are turned back on after a reset from the host on the PWR_EN signal. HEALTHY# (15) An open-drain, active-low output indicating card side power inputs are above their reset trip levels. LOCAL_PCI_RST# (9) An open-drain active-low output. It is used to reset the backend circuitry on the add-in card. It is active whenever the card-side monitor inputs are below their respective V TRIP levels. It may also be driven low by a low input on the PCI_RST# pin. LOCAL_PCI_RST (20) An open-drain (PFET) active-high output. It operates in parallel with LOCAL_PCI_RST#, providing an active high reset signal which is required by many 8051 style MCUs. It is active whenever the card-side monitor inputs are below their respective V TRIP levels. It may also be driven active by a low input on the PCI_RST# pin. SGNL_VLD# (16) An open-drain, active-low output that indicates card side power is valid and the internal card side PCI_RST# timer has timed out. VGATE3 (22) A slew rate limited high side driver output for the 3.3V external power FET gate. The output-voltage is generated by an on-board charge pump. VGATE5 (27) A slew rate limited high side driver output for the 5V external power FET gate. The output voltage is generated by an on-board charge pump. REF (5) This output provides a 1V reference for pre-charging the bus signal pins. Implementing a simple unity-gain ampli- fier circuit will allow pre-charging a large number of pins. ABSOLUTE MAXIMUM RATINGS* RECOMMENDED OPERATING CONDITIONS* Terminal Voltage with Respect to GND: CARD_3V_MON, CARD_5V_MON, HST_3V_MON, SGNL_VLD#, HEALTHY#, Package Thermal Resistance (θ JA) Moisture Classification Level 1 (MSL 1) per J-STD- 020 RELIABILITY CHARACTERISTICS Note * - The device is not guaranteed to function outside its operating rating. Stresses listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.

2070 9.1 5/27/03 SMH4042A SUMMIT MICROELECTRONICS, Inc. 5 DC OPERATING CHARACTERISTICS (Over Recommended Operating Conditions; Voltages are relative to GND ) Notes: (1) The SMH4042A will drive the Reset outputs and voltage control signals throughout the operating range of 1V to 5.5V. The balance of the logic will not be guaranteed operational unless V CC is greater than 2.7V. (2) A, B,G, H, K. L, M, & N refer to the Part Number Suffix. (3) For TA = –10ºC to 85ºC. 2037 Elect Table 2.0 lobmySr etemaraPs noitidnoC )2( .niM. pyT. xaMs tinU V CC egatlovylppuS) 1(1 V I 1CC tnerruCylppuSrewoP gnitarepO0 05A µ I 2CC gnitirW3 A m V PIRT )2(s leveLdlohserhT V CC 5 A 052.45 73.40 05.4V V CC 5 B 005.45 26.40 57.4V NOM_V3_TSH G 75.25 6.22 7.2V NOM_V3_TSH H 27.20 8.27 8.2V NOM_V3_TSH K 78.25 9.20 0.3V NOM_V3_TSH L 00.30 1.37 1.3V NOM_V5_DRAC M V CC Vm05+5V NOM_V5_DRAC N V CC Vm05–5V NOM_V3_DRAC M +NOM_V3_TSH Vm05 V NOM_V3_DRAC N –NOM_V3_TSH Vm05 V V TSYHRT siseretsyHtnioPpirT 7V m I IL tnerruCegakaeLtupnI 2A µ I OL tnerruCegakaeLtuptuO 01A µ VLI egatloVwoLtupnI 1.0–8 .0V VHI egatloVhgiHtupnI 2V CC V1+V V LO egatloVwoLtuptuO V CC I,V0.5= LO Am1.2=4 .0V V HO egatloVhgiHtuptuO V CC I,V0.5= HO Aµ004–=4 .2V V SRLO woL#TSR_ICP_LACOL I LO Am2.3=4 .0V V SRHO hgiHTESER I HO Aµ008–=V CC V57.0–V V 3GVHO hgiH3ETAGV I HO Aµ5=2 13 15 1V V 5GVHO hgiH5ETAGV I HO Aµ5=3 14 15 1V V FER egatloVtuptuOecnerefeRd aoLoN5 9.00 0.15 0.1V V BC egatloVpirTrekaerBtiucriC) 3(0 40 50 6V m

2070 9.1 5/27/03 SUMMIT MICROELECTRONICS, Inc. Power-Up Sequence The SMH4042A is an integrated power controller for any hot swappable add-in card. It provides all the signals and control functions to be compatible with CompactPCI Hot Swap requirements for basic hot swap systems, full hot swap boards, and high availability systems. Insertion Process As the add-in board is inserted into the backplane, physical connections are made with the chassis in order to properly discharge any voltage potentials to ground. The board will first contact the long pins on the backplane that provide early power (5V, 3.3V and ground). Depend- ing upon the board configuration, early power should be routed to the V CC pin of the SMH4042A. As soon as power is applied the SMH4042A will assert the reset outputs to the backend circuits, turn off the VGATE3 and VGATE5 outputs (disabling the external power FETs) and assert 1VREF. This signal can be used to pre-charge the I/O pins before they begin to mate with the bus signals. The open collector HEALTHY# output will be de-asserted. It should be actively pulled high by an external pull-up resistor (minimum 10k Ω). The next pins to mate are the I/Os, and the balance of the power pins if they are not already mated. The I/Os will have been pre-charged by the 1VREF output. The BD_SEL# pins are the last inputs to be driven to their true state. In most systems these will most likely be driven to ground when the short pins are mated. This would indicate the card is fully inserted and the power-up sequence can begin. If, however, the design is based on high availability requirements, the two pins can be ac- tively driven by the host or combined with a switch input indicating the ejector handles are fully engaged. Sequencing Once the proper card insertion has been assured the SMH4042A will check the status of the Power Enable signal from the host. This input can be used to power down individual cards on the bus via software control. It must by held high in order for the SMH4042A to enable power sequencing to the card. When these conditions have been met, the SMH4042A will drive the VGATE3 and VGATE5 outputs to turn on the external 3 volt and 5 volt power FETs. The slew rate of these outputs is controlled to a slew rate of 250V/s. Different slew rates can be accommodated by either adding an additional capacitor between the MOSFET gate DEVICE OPERATION and ground or by injecting current into the ISLEW input. All circuitry on the card is held in a reset condition until the 5V (or 3.3V) supply is stable and the reset interval timer has timed out the 150ms reset time. At this point, the reset signals are de-asserted, and proper operation of the card commences. See Figure 1, Table 1, and Flow Chart 1. The SMH4042A will monitor the card’s backend voltages. Once they are at or above the card V TRIP levels the SMH4042A will drive the HEALTHY# output. Card Removal Process The card removal process operates in the opposite sequence. For non-high-availability cards the action of card removal disconnects the BD_SEL# (short pins) from ground and the SMH4042A will instantly shutdown the VGATE outputs, change the HEALTHY# status, and assert the LOCAL_PCI_RST# output. Because connectors to the host backplane employ stag- gered pins, power will still be applied to the SMH4042A and the I/O interface circuits. The LOCAL_PCI_RST# signal will place the interface circuits into a high impedance condition. The pre-charge voltage will be applied to the I/Os enabling a graceful disengagement from the active bus. Once the I/O pins are free of the backplane, power can be removed from the SMH4042A and other early power devices by releasing the long pins. The removal process is slightly different for a high- availability system. As the ejector handle is rotated the ejector switch will open, causing a change of state that will activate the ENUM# signal to the host. In response to this notification the host will de-assert a hardware controlled BD_SEL# signal. This action will turn on an indicator LED on the card, notifying the operator it is now safe to proceed with the removal of the card. The sequence will then follow that outlined for the non-high-availability removal pro- cess. Power Configurations The SMH4042A can be used in 5V-only, 3.3V-only and mixed voltage systems. For systems with a single power supply, connect V CC and HST_3V_MON together to the bus power line. Also connect CARD_3V_MON and CARD_5V_MON together to the card side power. Now the state of VSEL determines the reset level that will be used to signal valid power. For 3.3V systems tie VSEL to V CC, for 5V systems tie VSEL to ground.

Figure 1. Card Insertion Timing Diagram Table 1. Card Insertion Timing

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2070 9.1 5/27/03 SUMMIT MICROELECTRONICS, Inc. Flow Chart 1. Sequence Diagram

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VCC ≥ 1V Assert Outputs LOCAL_PCI_RST & LOCAL_PCI_RST# Shut Off Signals DRVREN#, HEALTHY#, SGNL_VLD#, VGATE3 & VGATE5 Monitor BD_SEL1# & BD_SEL2# For Insertion YES HIGH LOW NO HIGH LOW Monitor VSEL Input Level Monitor HOST_3V_MON Input Level Monitor VCC & HOST_3V_MON Input Level Turn On Signals DRVREN#, VGATE3 & VGATE5 Monitor CARD_3V_MON & CARD_3V_MON: ≥ VTRIP? LOW OK LOW OK Turn On SGNL_VLD Turn On HEALTHY# Start Timer tPURST tPURST Timeout? NO YES PCI_RST Released? NO YES Release Resets

Figure 2. Loss-of-Voltage Timing Sequence Figure 3. Circuit Breaker Timing Sequence the backend logic will not proceed. source to the backend logic. based on the host power supply falling out of spec.

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2070 9.1 5/27/03 SUMMIT MICROELECTRONICS, Inc. Figure 4. Host-Initiated Reset Timing greater than 50mV for more than 16µs. the SMH4042A employs two different sampling schemes. down. This provides an effective response time of 4µs. providing an effective response time of 16µs. the reset cycle will be determined by the PCI_RST# input.

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rate, and some support the alternative 400kHz clock. Figure 5. I Table 2. I2C AC Operating Characteristics

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2070 9.1 5/27/03 SUMMIT MICROELECTRONICS, Inc. Stop condition. See Figure 6. issue a Stop on the clock pulse following the NACK. internal non-volatile write cycle. devices on the bus. The next bit is the block select bit. ing a Start condition and its DTI. further data transmission. See Figure 9. generated by the Master. See Figure 10. Figure 6. I Figure 7. Acknowledge Timing Figure 8. Typical Master Address Byte Transmission

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Write) followed by the address of the word it is to read. and reverts to its standby power mode. address byte Read or random address byte Read). memory will continue to output data. Figure 9. Basic Read Figure 10. Basic Write

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2070 9.1 5/27/03 SUMMIT MICROELECTRONICS, Inc. WRITE OPERATIONS The SMH4042A allows two types of Write operations to its a 512 x 8 array: byte Write and page Write. A byte Write operation writes a single byte during the nonvolatile Write period (t WR). The page Write operation allows up to 16 bytes in the same page to be written during t WR. Byte Write After the slave address is sent (to identify the slave device, and a Read or Write operation), a second byte is transmitted which contains the 8 bit address of any one of the 512 words in the array. Upon receipt of the word address the SMH4042A responds with an Acknowledge. After receiving the next byte of data, it again responds with an Acknowledge. The master then terminates the transfer by generating a Stop condition, at which time the SMH4042A begins the internal write cycle. The SMH4042A inputs are disabled while the internal write cycle is in progress, and the device will not respond to any requests from the Master. Page Write The SMH4042A is capable of a 16-byte page Write opera- tion. It is initiated in the same manner as the byte-Write operation, but, instead of terminating the Write cycle after the first data word, the Master can transmit up to 15 more bytes of data. After the receipt of each byte the SMH4042A will respond with an Acknowledge. The SMH4042A automatically increments the address for subsequent data words. After the receipt of each word the low order address bits are internally incremented by one. The high order bits of the address byte remain constant. Should the Master transmit more than 16 bytes, prior to generating the Stop condition, the address counter will roll over and the previously written data will be overwritten. As with the byte-Write operation, all inputs are disabled during the internal write cycle. Refer to Figure 5 for the address, Acknowledge and data transfer sequence. Acknowledge Polling When the SMH4042A is performing an internal Write operation it will ignore any new Start conditions. Since the device will only return an acknowledge after it accepts the Start, the part can be continuously queried until an acknowledge is issued, indicating that the internal write cycle is complete. See Flow Chart 2 for the proper sequence of operations for polling. READ OPERATIONS There are two different read options: 1. Current Address Byte Read 2. Random Address Byte Read Current Address Read The SMH4042A contains an internal address counter which maintains the address of the last word accessed, incremented by one. If the last address accessed (either a Read or Write) was to address location n, the next Read operation would access data from address location n+1 and increment the current address pointer. When the SMH4042A receives the Slave address field with the R/W MEMORY OPERATION Flow Chart 2. Polling Next Operation a Write? ACK Returned Issue Address Proceed With Write Await Next Command Issue Stop Issue Slave Address and R/W = 0 Issue Stop Write Cycle In Progress Ye s No Issue Start

2070 Flow02

2070 9.1 5/27/03 SMH4042A SUMMIT MICROELECTRONICS, Inc. 15 bit set to “1” it issues an acknowledge and transmits the 8- Bit word stored at address location n+1. The current address byte Read operation only accesses a single byte of data. The Master holds the SDA line high (NACK) and generates a Stop condition. At this point the SMH4042A discontinues data transmission. Random Address Read Random address Read operations allow the Master to access any memory location in a random fashion. This operation involves a two-step process. First, the Master issues a Write command which includes the Start condi- tion and the Slave address field (with the R/W bit set to Write) followed by the address of the word it is to read. This procedure sets the internal address counter of the SMH4042A to the desired address. After the word address acknowledge is received by the Master, the Master immediately reissues a Start condition followed by an- other Slave address field with the R/W bit set to Read. The SMH4042A will respond with an Acknowledge and then transmit the 8 data bits stored at the addressed location. At this point the Master issues a NACK and generates the Stop condition. The SMH4042A discontinues data trans- mission and reverts to its standby power mode. Sequential Read Sequential Reads can be initiated as either a current address Read or a random access Read. The first word is transmitted as with the other byte Read modes (current address byte Read or random address byte Read); however, the Master now responds with an Acknowledge, indicating that it requires additional data from the SMH4042A. The SMH4042A continues to output data for each Acknowledge received. The Master terminates the sequential Read operation with a NACK and a Stop. During a sequential Read operation the internal address counter is automatically incremented with each Acknowl- edge signal. For Read operations all address bits are incremented, allowing the entire array to be read using a single Read command. After a count of the last memory address the address counter will roll over and the memory will continue to output data. Data Download The SMH4042A supports a proprietary mode of operation specifically for the Hot Swap environment. After a power on reset the internal address pointer is reset to 00. The host or ASIC then only needs to issue a Read command and then sequentially clock out data starting at address 00.

2070 9.1 5/27/03 SUMMIT MICROELECTRONICS, Inc.

APPLICATIONS

DESIGN CONSIDERATIONS FOR A COMPACTPCI BOARD Figure 11 is a generic representation of a CompactPCI board and it illustrates how the SMH4042A is the key component in the board insertion/removal process. The illustrations that follow show in more detail how the various blocks interface to the SMH4042A. Power Busses It is important in the design of the board to ensure the backend logic is isolated from the power control circuits and other early power circuits such as FPGAs and the I/ O interface circuits. In Figure 12 the early power busses for 5V and 3V have series current limiting resistors. These values should be calculated so as to limit the in- rush current that will initially charge the capacitive load of the early power circuits. As the card is inserted further, the medium length pins engage and short out the current limiting resistors. Note the placement of the sense (shunt) resistors. They are in series with the power FETs and no voltage drop will be detected across the resistor until VGATE is applied to the power FETs. The sense resistor values are determined by dividing 50mV by the current specification for that supply. It should be noted that there is an inherent delay from VGATE5 turning on to VGATE3 turning on. The typical delay is illustrated in Figure 13. Figure 11. Diagram of Typical

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Figure 12. Power Control and Power Plane Isolation Figure 13. Typical Delay: VGATE5 to VGATE3

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2070 9.1 5/27/03 SUMMIT MICROELECTRONICS, Inc. Figure 14. Four Power Switching Implementations

required for the external pull-up resistors. Instruments and Pericom Semiconductor. Figure 15. Bus Buffers with External Pull-ups Figure 16. Bus Buffers with Integrated Pull-ups

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2070 9.1 5/27/03 SUMMIT MICROELECTRONICS, Inc. switch is redundant and realistically can be grounded. Hot Swap specification states the following. is a typical implementation utilizing a common op amp. Figure 17. I/O Pre-charge Circuit the BD_SEL pull-up resistor. dependent upon the interface operating levels.

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 The medium length pins contact. Figure 18. Full Hot Swap Board/Host Interface SMH4042A before it will begin the power-on sequence.

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2070 9.1 5/27/03 SUMMIT MICROELECTRONICS, Inc. Figure 19. Using DRVREN# to switch 12V and –12V to the Backend Logic

Figure 20. Typical CompactPCI Power On Sequence for a Non-High Availability System

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2070 9.1 5/27/03 SUMMIT MICROELECTRONICS, Inc. Figure 21. Typical CompactPCI Power On Sequence for a Full Hot Swap Board Using the S39421

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for controlling the slot voltages. Figure 22. Diagram for a PCI Hot Plug Slot Implementation

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2070 9.1 5/27/03 SUMMIT MICROELECTRONICS, Inc. PACKAGES

28 PIN SOIC PACKAGE

28 PIN SSOP PACKAGE

0.291 - 0.299 0.013 - 0.020 (0.33 - 0.51) 0.004 - 0.012 (0.10 - 0.30) 0.697 - 0.713 (17.70 - 18.10) 0.394 - 0.419 (10.00 - 10.65) 0.093 - 0.104 (2.35 - 2.65) 0.016 - 0.050 (0.23 - 0.32) 0.010 - 0.029 (0.25 - 0.75) (7.40 - 7.60)

28 Pin SOIC

´45º 0.016 - 0.050 0.05 Ref. JEDEC MS-013 Inches (Millimeters) 0º to 8º max. 0.007 - 0.010 (0.18 - 0.25) 0.150 - 0.157 (3.81 - 3.99) 0.025 (0.635) 0.016 - 0.050 (0.20 - 0.31) 0.386 - 0.394 (9.80 - 10.00) 0.228 - 0.244 (5.79 - 6.20) Pin 1 0º to 8º max. 0.004 - 0.010 (0.10 - 0.25) 0.059 (1.50) 0.053 - 0.069 (1.35 - 1.75) MAX

28 Pin SSOP

Ref. JEDEC MO-137

2070 9.1 5/27/03 SMH4042A SUMMIT MICROELECTRONICS, Inc. 27

ORDERING INFORMATION

Date Code (YYW W) Lot tracking code (Summit use) Drawing not to scale xx Status Tracking Code (Blank, MS, ES, 01, 02,...) (Summit Use) Package Designator G=28 Lead SSOP Summit Part Number A VTRIP VCC 5 S=28 Lead SOIC A=4.375V B=4.625V G VTRIP HST_3V_MON G=2.65V H=2.80V K=2.95V L=3.10V M VTRIP OFFSET M=+50mV N=-50mV

2070 9.1 5/27/03 SUMMIT MICROELECTRONICS, Inc. NOTICE SUMMIT Microelectronics, Inc. reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. SUMMIT Microelectronics, Inc. assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained herein reflect representative operating parameters, and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked, SUMMIT Microelectronics, Inc. shall not be liable for any damages arising as a result of any error or omission. SUMMIT Microelectronics, Inc. does not recommend the use of any of its products in life support or aviation applications where the failure or malfunction of the product can reasonably be expected to cause any failure of either system or to significantly affect their safety or effectiveness. Products are not authorized for use in such applications unless SUMMIT Microelectronics, Inc. receives written assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and (c) potential liability of SUMMIT Microelectronics, Inc. is adequately protected under the circumstances. This document supersedes all previous versions. © Copyright 2003 SUMMIT Microelectronics, Inc. I2C is a trademark of Philips Corporation. PICMG & CompactPCI are trademarks of the PCI Industrial Computer Manufacturer's Group.