SMD1102

SMD1103 SUMMIT | Alldatasheet

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1Characteristics subject to change without notice 2033 8.1 10/04/01 SMD1102 / 1103 / 1113SUMMIT MICROELECTRONICS, Inc. ©SUMMIT MICROELECTRONICS, Inc., 2001 • 300 Orchard City Dr., Suite 131 • Campbell, CA 95008 • Phone 408-378-6461 • FAX 408-378- 6586 • www.summitmicro.com Preliminary !!!!! Complete Data Acquisition System """"" 10-Bit A/D Converter Resolution """"" 75µs Acquisition plus Conversion Time """"" Alarm Limits for Each Input Channel """"" Auto-Increment of Input Channels """"" Two Wire I2C Serial Data Interface """"" System Management Bus (SMBus) Compat- ible """"" Auto-Monitor with SMBALERT Output """"" Low Quiescent Current of 50µA """"" Wide Supply Voltage Range: 2.7V to 5.5V 10-Bit Data Acquisition System for Autonomous Environmental Monitoring FUNCTIONAL BLOCK DIAGRAM

FEATURES

""""" 2-Channel Analog Input """"" External Voltage Reference Input Provided for Absolute Measurements """"" 3-Channel Analog Input """"" Reference Voltage Input for the A/D Converter is Connected to VDD for Ratiometric Measure- ments """"" Extended I2C Operation """"" 3-Channel Analog Input """"" External Voltage Reference Input Provided for Absolute Measurements GND VDD CONVERTER CLOCK SCL SDA 2033 BD 7.0 CONTROL LOGIC 2-WIRE SERIAL INTERFACE ANALOG MULTIPLEXER 10-BIT A/D CONVERTER E2PROM ALARM LIMIT REGISTERS SAMPLE AND HOLD SMB ALERT # A IN2 X A IN1 A IN0 (1103, 1113) REF IN (1102, 1113) X CE# (1113) (1113) (1113) (1113) Note: See Pin Configuration drawings for pinouts

2033 8.1 10/04/01 SUMMIT MICROELECTRONICS, Inc. PIN CONFIGURATION The SMD1102, SMD1103 and SMD1113 each contain a 10-Bit data acquisition system (DAS) with dedicated EE- PROM alarm limit storage. The three devices communi- cate with the host µP via a standard two-wire I 2C serial interface. After initialization the SMD1102/1103/1113 can INTRODUCTION PIN NAMES automatically monitor one or more analog input channels. If any input signal moves beyond its user-programmed limits the host is notified by the SMB ALERT# output, enabling fault prediction in telecom line card applications, as an example. 1102 A IN0, AIN1 Analog channel inputs GND Power supply return REFIN Reference input SCL Serial Clock SDA Serial Data SMB ALERT# Interrupt output VDD Power Supply 1103 AIN0, AIN1, AIN2 Analog channel inputs GND Power supply return SCL Serial Clock SDA Serial Data SMB ALERT# Interrupt output VDD Power Supply 1113 CE# Chip Enable A2, A1, A0 I 2C Address select inputs AIN0, AIN1, AIN2 Analog channel inputs GND Power supply return REF IN Reference input SCL Serial Clock SDA Serial Data SMB ALERT# Interrupt output VDD Power Supply A IN2 A IN1 A IN0 GND VDD CE# REF IN NC SMB ALERT # SCL SDA 2033 14 PCon 14-Pin SOIC SMD1113 2033 8 PCon-2 REF IN A IN1 A IN0 GND VDD SMB ALERT # SCL SDA 8-Pin SOIC SMD1102 A IN2 A IN1 A IN0 GND VDD SMB ALERT # SCL SDA 8-Pin SOIC SMD1103 2033 8 PCon-3

32033 8.1 10/04/01 SMD1102 / 1103 / 1113 SUMMIT MICROELECTRONICS, Inc. *COMMENT Stresses listed under Absolute Maximum Ratings may cause perma- nent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. Terminal Voltage with Respect to GND: DC OPERATING CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS* (Over Recommended Operating Conditions; Voltages are relative to GND)

2033 Elect Table

RECOMMENDED OPERATING CONDITIONS Temperature –40 ºC to 85ºC. Voltage 2.7V to 5.5V lobmySr etemaraPs noitidnoC )1etoN( .niM. pyT. xaMs tinU V CC egatloVylppuS7 .25 .5V ICC tnerruCylppuSn epostuptuollA3 A m IBS tnerruCybdnatS ,eldiCDA,nepostuptuollA ssecorpnietirwyromemon 05A µ IIL tnerrucegakaeltupnIV NI VotV0= CC 2A µ IOL tuOt nerrucegakaeltupV TUO VotV0= CC 01A µ V LO egatlovwoltuptuO V CC I,V5= LO Am1.2=4 .0 V V CC I,V5.4< LO Am1=2 .0 V HO egatlovhgihtuptuO V CC I,V5= LO Aµ004–= 4.2 V V CC I,V5.4< LO Aµ001–=V CC 2.0– V LI egatlovwoltupnI1 .0– 3.0 × V CC V V HI egatlovhgihtupnI7 .0 × V CC V CC 7.0+V stupnIgolanA V NIFER V FER egatlovtupni1 V CC V V NI AnoegatlovtupnI NI 0 Ahguorht NI 2 05 .5V

2033 8.1 10/04/01 SUMMIT MICROELECTRONICS, Inc. PIN DESCRIPTIONS Serial Clock (SCL) The SCL input is used to clock data into and out of the device. In the WRITE mode data must remain stable while SCL is HIGH. In the READ mode data is clocked out on the falling edge of SCL. Serial Data (SDA) The SDA pin is a bidirectional pin used to transfer data into and out of the device. Data may change only when SCL is LOW, except during START and STOP conditions. It is an open-drain output and may be wire-ORed with any number of open-drain or open-collector outputs. SMB ALERT# This interrupt output pin signals the host when an out-of- limit condition is detected by one of the EEPROM limit registers. The SMB ALERT open-drain output is active low. REFIN Voltage reference input for 10-Bit A/D converter. This signal is only on the SMD1102 and SMD1113. AIN0, AIN1, AIN2 Multiplexer input pins for channels 0, 1, and 2, respec- tively. A IN2 is only available on the SMD1103 and SMD1113. These pins may be left unconnected if they are not used. However, the Alert Regions must be set accordingly (see the section "Alert Conditions"). A0, A1, A2 The address inputs are only available on the SMD1113. Multiple SMD1113s can be used on a single bus by setting different device addresses. A2 has a 50k Ω pull-up resistor, and A1 and A0 have 50kΩ pull-down resistors. Do not set the address to all zeroes because it would cause a conflict with the SMB Alert Response. CE# Chip Enable/disable input must be held low to enable I communications. It has a 50kΩ pull-down resistor and is only available on the SMD1113. VDD Power supply input. GND Power supply return.

SUMMIT MICROELECTRONICS, Inc. inputs move outside these limits. autonomous conversions of the same or all channels. hold capacitor as a sample of the signal. Figure 1. Sample/Hold and SAR logic one the EEPROM limit register will be addressed. wrap around to channel 0. See Table 1B. of the EEPROM/Conversion bit. See Table 1C.

1 MORPEEsserddA

2033 Table01A

• Denotes SMD 1102 & SMD1103. Ax bits are for the SMD1113.

2033 Table01B

• Denotes SMD 1102 & SMD1103. Ax bits are for the SMD1113.

2033 8.1 10/04/01 SUMMIT MICROELECTRONICS, Inc. Single Channel Conversions This command sequence is composed of: the Device Type Identifier, followed by the E/C bit set to zero, then the channel select bits set to the desired value, and the R/M bit set to logic one. After the R/M bit is clocked in the host releases the SDA line and monitors the SDA line for an acknowledge bit (ACK) from the SMD1102/1103/1113. The device will drive the SDA line low indicating it received the command and that it has initiated the acquisition and conversion on the selected channel. The clock source for the acquisition and conversion is an internal clock. After the ACK the SMD1102/1103/1113 will output four dummy zeros on SDA followed by an echo of the channel’s 2 address bits. The remaining bits in this first byte are the two MSBs of the conversion. Refer to Figure 2 for a detailed illustration of this sequence, and for that of retrieving the remaining conversion byte. The host can issue a stop condition after retrieving the conversion data and place the SMD1102/1103/1113 in a low power standby mode. Successive Single Channel Conversions If the host does not issue a stop command after receiving the last bit of the previous conversion, but instead issues an ACK and continues clocking, then the SMD1102/1103/ 1113 will begin another acquisition and conversion pro- cess on the same channel. Auto-Increment In the auto-increment mode, the DAS starts a conversion and then automatically advances to the next channel. The auto-increment mode always starts at channel 0 and switches the channel input in the sequence 0, 1, 2, 0, 1, 2, etc. after each successive conversion. The SMD1102, SMD1103, and SMD1113 independently repeat this pro- cess so long as the host continues clocking the device, supplies ACK bits at the appropriate clock interval, and issues no stop conditions. Refer to Figure 4 for a detailed illustration of the sequence. Programming the Limit Registers Programming the nonvolatile limit registers of the SMD1102/1103/1113 for use with the auto-monitor func- tion is straightforward. Associated with each channel is an 11-bit lower limit register and an 11-bit upper limit register. Ten bits correspond to the 10-bit data, and the MSB represents the monitor option bit. The monitor option bits of the upper and lower limit combine to define the alert region for each channel (described more fully in the section labeled Alert Conditions). Each limit register must be programmed separately with a three byte com- mand sequence. To program the limit register the host first issues a start condition, followed by the device type identifier, the EEPROM/Conversion (E/C) bit (set to one), the channel select bits, and the Read/Monitor bit (set to zero). The second byte consists of four zeroes followed by the limit select bit (zero = lower limit, one = upper limit), the monitor option bit, and the two most significant bits of the limit data. The third byte consists of the remaining eight bits of limit data. After receiving a stop condition, the SMD1102/1103/1113 initiates its internal program sequence. Refer to Figure 5 for details. Six such sequences are required to set the upper and lower limits for all three channels. However, once programmed the data remains stored in EEPROM until reprogrammed. For example, when a device has both V DD and VREF at 5.00V, and an alert must be generated if the voltage on any channel is ≤2.00V or >3.00V, then the monitor option bits are set to 10 BIN, the upper limit is set to 266HEX, and the lower limit is set to 199HEX. Reading the Limit Registers The timing diagram for reading the limit register data of a particular channel is shown in Figure 6. The five byte sequence commences with a start condition, followed by the device type identifier, the EEPROM/Conversion bit (set to one), the channel select bits, and the Read/Monitor bit (set to one). After acknowledging the slave byte the device outputs a one, followed by an echo of the channel select bits, a zero, another zero (representing the lower limit data), the monitor option bit and the two most significant bits of the limit data. The third byte consists of the remaining eight bits of the lower limit data. The fourth byte of the output sequence is the same as the second byte except the fifth bit is a one (to indicate upper

2033 Table01C

Table 1C. Address Byte — Read/Monitor * Denotes SMD 1102 & SMD1103. Ax bits are for the SMD1113. 7BD6 BD5 BD4 BD0 BD noitcnuFreifitnedIepyTeciveDM /R ro ro ro rotinom-otuaelbanE MORPEEetirwro C/E(retsigertimil )etats -nocD/AdaeR MORPEEronoisrev C/E(retsigertimil )etats

SUMMIT MICROELECTRONICS, Inc. Figure 4. Auto-Increment Continuous Read Sequence Figure 5. Programming the Auto-Monitor Limit Registers Figure 6. Reading the Auto-Monitor Limit Registers

2033 Fig05

Figure 2. Single Channel Read Sequence Figure 3. Single Channel Continuous Read Sequence

2033 Fig02

2033 Fig06

1 CH1 CH0 0

2033 Fig04

2033 8.1 10/04/01 SUMMIT MICROELECTRONICS, Inc. stored with the upper and lower limits in the NV registers. lower limit above the upper limit. with the lowest address to be serviced first. not be set with A2, A1 and A0 all equal to zero. Figure 7. Begin Auto-Monitor Command

10 CH1 CH0 0

2033 Fig07

remaining eight bits of the upper limit data. channel select bits, and the Read/Monitor bit set to zero. channel that prompted the alert. Auto-Monitor function will not return valid data.

SUMMIT MICROELECTRONICS, Inc. Figure 10. Resetting SMBALERT# Figure 8. Four Alert Conditions Figure 9. SMBALERT# Response Sequence

0 CH1 CH0

2033 Fig10

SMBALERT# will not return valid data.

2033 Fig08

2033 Fig09

2033 8.1 10/04/01 SUMMIT MICROELECTRONICS, Inc. Table 2. Register Read/Write AC Operating Characteristics rate, and some support the alternative 400kHz clock.

2033 Table02

Figure 11. Interface Bus Timing Note (1) These values are guaranteed by design.

2033 Fig11

SUMMIT MICROELECTRONICS, Inc. a Stop on the clock pulse following the NACK. internal nonvolatile write cycle. bits illustrated in Table 1. terminate further data transmission. Figure 12. Start and Stop Conditions Figure 13. Acknowledge Timing

2033 8.1 10/04/01 SUMMIT MICROELECTRONICS, Inc. PACKAGES .228 (5.80) .035 (.90) .020 (.50) .010 (.25) x45° .0192 (.49) .0138 (.35) .061 (1.75) .053 (1.35) .0098 (.25) .004 (.127) .05 (1.27) TYP. .275 (6.99) TYP. .030 (.762) TYP.

8 Places

.050 (1.27) TYP. .050 (1.270) TYP. .157 (4.00) .150 (3.80) .196 (5.00)1 .189 (4.80) FOOTPRINT 8pn JEDEC SOIC ILL.2

8 Pin SOIC (Type S) Package JEDEC (150 mil body width)

132033 8.1 10/04/01 SMD1102 / 1103 / 1113 SUMMIT MICROELECTRONICS, Inc.

14 PIN SOIC PACKAGE

0.150 - 0.157 0.013 - 0.020 (0.33 - 0.51) 0.004 - 0.01 (0.10 - 0.25) 0.337 - 0.344 (8.55 - 8.75) 0.228 - 0.244 (5.80 - 6.20) 0.053 - 0.069 (1.35 - 1.75) 0.016 - 0.050 (0.19 - 0.25) 0.01 - 0.02 (0.25 - 0.50) (3.80 - 4.00)

14 Pin SOIC

×45º 0.016 - 0.050 0.05 0 to 8 typ Ref. JEDEC MS-012 Inches (Millimeters)

ORDERING INFORMATION

2 = REFIN 3 = AIN2 S = SOIC

2033 Tree 8

S = SOIC

2033 Tree 14

2033 8.1 10/04/01 SUMMIT MICROELECTRONICS, Inc. NOTICE SUMMIT Microelectronics, Inc. reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. SUMMIT Microelectronics, Inc. assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained herein reflect representative operating parameters, and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked, SUMMIT Microelectronics, Inc. shall not be liable for any damages arising as a result of any error or omission. SUMMIT Microelectronics, Inc. does not recommend the use of any of its products in life support or aviation applications where the failure or malfunction of the product can reasonably be expected to cause any failure of either system or to significantly affect their safety or effectiveness. Products are not authorized for use in such applications unless SUMMIT Microelectronics, Inc. receives written assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and (c) potential liability of SUMMIT Microelectronics, Inc. is adequately protected under the circumstances. Power Management for Communications™ This document supersedes all previous versions. © Copyright 2001 SUMMIT Microelectronics, Inc. I2C is a trademark of Philips Corporation. PART MARKING SUMMIT SMD1113S L YY WW Package type - SOIC (S) L = Lot number YY = Y ear WW = Work Week SMD1113 /KCA SUMMIT SMD1103 S L YY WW Package type - SOIC (S) L = Lot number YY = Y ear WW = Work Week SUMMIT SMD1103 S L YY WW SMD1102 SMD1103 /KCA /KCA