SLE95250

SLE95250 INFINEON | Alldatasheet

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OPTIGATM Trust B Authentication IC OPTIGA TM Trust Product Authenication Family Brief Databook Revision 2.01, 2021-03-02

The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Edition 2021-03-02 Published by Infineon Technologies AG

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Revision History

Page or Item Subjects (major changes since previous revision) Minor typo and update Added the UTAC package drawing <Revision 1.01>,2016-12-15 Updated Electrical Specification <Revision 0.91>, 2016-06-15 Updated Life span counter operation <Revision 0.9>, 2016-04-15 Initial Release <Revision 2.01>, 2021-03-02 Revision 2.01, 2021-03-02

Revision 2.01, 2021-03-02

Revision 2.01, 2021-03-02

1 Preface

This document describes on the operation and interface characteristics of the OPTIGATM Trust B design.

1.1 Abstract

This document is the device specification for OPTIGATM Trust B design.

1.2 Document definitions

This document describes the architecture and behavior of the OPTIGATM Trust B design.

1.3 Disclaimer

Infineon is as diligent as possible in compiling and updating the information on this databook. However, Infineon does not guarantee the correctness and completeness of the info rmation provided. Equally, Infineon does not guarantee that this information is up to date. For questions concerning our products, their specifications and their utilization please contact Infineon for the latest specification. Features and spec values may be changed without notice.

1.4 Textual Convention

This document uses the following textual conventions:

• Functional units o f subsystems are given in plain UPPER CASE. For example: “The SSC can be used to communicate with shift registers.”.
• Pins using negative logic are i ndicated by a N postfix. For example: “A reset input pin, RESETN, is provided for the hardware reset.”.
• Bit fields and bits in registers are generally referenced as “Register name.Bit field” or “Register name.Bit”. Most of the register names contain a module name prefix (for example, “SSCCON”, where “SSC” is the module name prefix, and “CON” is the actual register name). In chapters describing peripheral modules, the actual register name is referenced also as the kernel register name.
• Variables used to de scribe sets of processing units or registers appear in mixed-case type. For example, the register name “CC6xR” refers to multiple “CC6xR” registers with the variable x (x = 0, 1, 2). The bounds of the variables are always given where the register expression is first used (for example, “x = 2 - 0”), and is repeated as needed in the rest of the text.
• The default radix is decimal. H exadecimal constants have a suffix with the subscript letter “H”, as in 100H. Binary constants have a suffix with the subscript letter “B”, as in: 111B.
• When the extent of register fields, groups of signals, or grou ps of pins are collectively named in the body of the document, they are given as “NAME[A:B]”, which defines a range for the named group from B to A. Individual bits, signals, or pins are given as “NAME[C]” where the range of the variable C is given in the text. For example: CFG[2:0] and TOS[0]. Units are abbreviated as follows:
• kByte = 1024 bytes of memory
• MHz = Megahertz
• Byte = 8-bit quantity
• MByte = 1,048,576 bytes of memory
• kBaud, kBit = 1000 characters/bits per second
• MBaud, MBit = 1,000,000 c haracters/bits per second
• μs = Microsecond Revision 2.01, 2021-03-02

1.5 Abbreviations and Acronyms

°C Degree Celsius mA milli ampere mS milli second mV milli volt µA micro ampere µS micro second µV micro volt IC Integrated Circuit PMU Power Management Unit TSNP Thin Small Non Leaded Package CGU Clock Generation Unit OEM Original Equipment Manufacturer ODM Original Design Manufacturer ECC Elliptic Curve Cryptography ODC OPTIGA TM Digital Certificate MAC Message Authentication Code UID Unique IDentifier LSB Least Significant Bit MSB Most Significant Bit GPIO General Purpose I/O MCU Microcontroller Unit Revision 2.01, 2021-03-02

Infineon Technologies’ novel OPTIGA TM Trust B Authentication chip offe rs a robust cryptographic solu tion, that assists OEMs and system manufactu rers to safeguard the authenti city and safety of their original products, and protection of their investments against unauthorized after-market replacements. It leverages Infineon’s market leading security know-how into t he battery and accessory authentication markets. With its innovative asymmetric cryptography approach, it signif icantly reduces system cost whilst making a leap up in security.

2.1 Application Field

The main area of application is authentication leading to incre ased safety, functionality and reliability of the accessories, replacement parts and disposables with a special focus on batteries. The OPTIGATM Trust B Authentication IC lends itself for use in multiple application domains which use its safety and highly reliable authentication features. These protect the systems from unauthorized accessories, replacement parts and disposables.

• Low and high density batteries – Mobile Phones – Computing Devices – Digital Imaging – Power Tools
• Adaptor
• Miscellenous Accessories – Earphones – Speakers – Docking Stations – Game Controller
• Water Filter Replacement Parts Revision 2.01, 2021-03-02

2.2 Features

The features of OPTIGATM Trust B Authentication IC are listed as follows:

• Security – 131 bits Elliptic Curve Cryptography (ECC) Engine – 163 bits OPTIGATM Trust B Digital Certificate (ODC) – Message Authentication Code (MAC) Function – Host Challenge by Software(Host → Slave) – Security Library Concept for easy host side integration – Kill-Feature
• Customizable Non-Volatile Memories – 64-bits protected NVM read-only space for customer specified information – 512-bits unprotected NVM memories for user mode area – Endurance of 100,000 programming cycle (at 25 Deg C ambient temperature)
• Single Wire Interface – Single-Wire Interfaces (SWI) I/O interface – up to 500kbit/s transmission speed – Device ID search scheme and address management for multiple device capabilities – 96 bits Unique Chip Identification number – Communication library concept for easy host side integration – Multiple device capabilities in direct powered mode – Powered directly or Indirect Power via Single-wire interface – Device ID search and management scheme – Power-up detection capability – Programmable Device Address capability
• Power Management – Direct powered / Indirect powered application solution – Power Up and Down Control Via SWI interface – Power Down Control Via Power Down Command – Wide Operating Range Single Supply Voltage Support (From 2.0V to 5.5V)
• Lifespan Indicator – The counter value can only be read by the host, and is protected from being reprogrammed – Counter value is decrement on command – Up to 32 bit Life Span Counter Feature
• Small Package – PG-TSNP-6-9 Package – Package Width of 1.10mm is suitable for slim Printed Circuit Board (PCB) design – Package Height of 0.4mm(Max) is suitable for low height form factor profile design – Package Size: 1.5mm X 1.1mm –P i t c h : 0 . 5 m m – Comply with RoHS Standard – Comply with IPC/J-STD-020 MSL-1 Standard
• ESD – JESD22-A114 ESD HBM Standard 2kV Standard – JESD-C101 ESD CDM 500V Standard Revision 2.01, 2021-03-02

3 Functional Overview

OPTIGATM Trust B is designed to be used as a companion authentication d evice. This authentication device reside away from the HOSTsystem such that the host system is ab le to check if it is communicating with an authenticated original product. The SWI communication link is the basis for the OPTIGATM Trust B to communicates with the HOST controller. It is designed to conform to the Infineon SWI Bus Interface specification

3.1 Typical Application

OPTIGATM Trust B can be integrated to any system with very low hardware requirement. In a typical setup, only a pull-up resistor, RSWI, is required for open-drain GPIO. OPTIGATM Trust B provides a combination of secured authentication function and user read/write storage space via a single serial serial interface(SWI). SWI is able to perform bidirectional communication on multiple devices on the bus without extra hardware. Communication on the SWI is half-duplex transmission in which master and slave can transmit and received commands only one at a time. In SWI a rchitecture, SWI master initiates and controls all the SWI operations. The SWI bus operates in a command and r esponse sequence. An additional feature of SWI interface is the ability of interrupt-based processing which allows for concurrent processing. Figure 3-1 shows an example of a Host system connection to an OPTIGATM Trust B device Figure 3-1 Application Diagram of OPTIGA TM Trust B based on Direct Power Revision 2.01, 2021-03-02 HOST ISWI OPTIGATM VDD GND SWI SLAVE BOARD SWI MASTER BOARD GND VCC RSWI VCC GND SWIGPIO1 1) GPIO configured as open drain output with drive capability of > 2mA – 10mA 2) RSWI can be connected to the same VCC voltage or other system voltage lower than VCC GND VCC CVDD CVCC 2.2nF

Revision 2.01, 2021-03-02 HOST ISWI OPTIGATM VSWI VDD GND SWI SLAVE BOARD SWI MASTER BOARD GND VCC RSWI CVCC VCC GND SWI IVDDP + Charge ICha rge I VDDP IOD GPIO1 1) GPIO configured as open drain output with drive capability of > 2mA – 10mA D VCC GND VCC CVDD 2.2nF In certain scenario where minimum number of wire connection are desired, OPTIGATM Trust B can be configured with a total of two wires using some external circuit components. Figure 3-2 shows a setup example of the system where OPTIGA TM Trust B is powered using the co mmunication line. The resistor, RSWI, maintains the power supply with a voltage drop of RSWI multiplied by ISWI. The voltage is fed to the OPTIGA’s single wire interface port and its power supply through a diode. Using the following setup, the VCC connection is not required. Figure 3-2 Application Diagram of OPTIGA TM Trust B based on Indirect Power

3.2 Support Mode of Operation

Various mode of operations supported in OPTIGATM Trust B is tabulated in Table 3-1. Table 3-1 Mode of Operation Mode of Operation Description Power Down • All systems are disabled, lowest current consumption mode Active - Idle • Communication Ready

• System is not active
• NVM is not active
• Authentication is not active Active - Communication
• Communication Ready
• System is active
• NVM is not active
• Authentication is not active Active - Authentication
• Communication Ready
• System is active
• NVM is active
• Authentication is active Active - NVM • Communication Ready
• System is active
• NVM is active
• Authentication is not active Revision 2.01, 2021-03-02

Signals Description for PG-TSNP-6-9 Package DataBook 14 System Description

4 Signals Description for PG-TSNP-6-9 Package

This chapter provides: 1. Pin Configuration (PG-TSNP-6-9 Package) 2. Abbreviations for signals des cription (Pin Type and Buffer Type) 3. Pin Description (PG-TSNP-6-9 Package)

4.1 Pin Configuration (PG-TSNP-6-9 Package)

The Pin configuration diagram for OPTIGATM Trust B PG-TSNP-6-9 Package Figure 4-1 Pin Configuration (PG- TSNP-6-9 Package) - Top View Revision 2.01, 2021-03-02 6 1 Pin 1 Marking VSS VDD VSS SWI VCC5VSS Top View

Signals Description for PG-TSNP-6-9 Package DataBook 15 System Description

4.2 Abbreviations

The Standard abbreviations for I/O are shown in Table 4-1 and Table 4-2. Note: Any changes and extensions must be negotiated first. Table 4-1 Abbreviations for Pin Type Abbreviations Description I Standard input-only pin. Digital levels. O Output. Digital levels. I/O I/O is a bidirectional input/output signal. AI Input. Analog levels. AO Output. Analog levels. AI/O Input or Output. Analog levels. PWR Power GND Ground MCL Must be connected to Low (JEDEC Standard) MCH Must be connected to High (JEDEC Standard) NU Not Usable (JEDEC Standard) NC Not Connected (JEDEC Standard) Table 4-2 Abbreviations for Buffer Type Abbreviations Description Z High impedance PU1 Pull up, 10 kΩ PD1 Pull down, 10 kΩ PD2 Pull down, 20 kΩ TS Tristate capab ility: The corresponding pin has 3 operational states: Low, high and high- impedance. OD Open Drain. The corresponding p in has 2 operational states, active low and tristate, and allows multiple devices to share as a wire-OR. An external pull-up is required to sustain the inactive state until another agent drives it, and must be provided by the central resource. OC Open Collector PP Push-Pull. The corresponding pin has 2 operational states: Ac tive-low and active-high (identical to output with no type attribute). OD/PP Open-Drain or Push-Pull. The corresponding pin can be conf igured either as an output with the OD attribute or as an output with the PP attribute. ST Schmitt-Trigger characteristics TTL TTL characteristics Revision 2.01, 2021-03-02

Signals Description for PG-TSNP-6-9 Package DataBook 16 System Description

4.3 Pin Description (PG-TSNP-6-9 Package)

Pin description for OPTIGATM Trust B PG-TSNP-6-9 Package is shown below.

4.4 Package

4.4.1 Package Outl ine: PG-TSNP-6-9

Table 4-6 shows the PG-TSNP-6-9 package dimension for OPTIGATM Trust. Figure 4-2 shows the PG-TSNP-6-9 package outline for OPTIGATM Trust. Table 4-3 I/O Signals Pin No. Name Pin Type Buffer Type Function 1S W II / O O D Single Wire Interface Table 4-4 Power Supply Pin No. Name Pin Type Buffer Type Function

2 VCC PWR – Supply

Positive Power Input for OPTIGATM Trust B. Connect 0.1μF capacitor.

6 VDD PWR – Digital Power Supply

Internal Digital Power Supply of OPTIGATM Trust B. Connect 2.2nF capacitor. Table 4-5 Ground Pins Pin No. Name Pin Type Buffer Type Function 4, 3, 5 VSS PWR – GND Pin (Pin 4 is the main VSS) This is the common ground of the IC. Table 4-6 PG-TSNP-6-9 Package Dimensions Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. A 1.05 1.1 1.15 mm Package Width B 1.45 1.5 1.55 mm Package Length C 0.35 0.375 0.40 mm Package Height D 0.25 0.30 0.35 mm Solder Pad Width E 0.25 0.30 0.35 mm Solder Pad Length F 0.50 mm Solder Pad Pitch Revision 2.01, 2021-03-02

Signals Description for PG-TSNP-6-9 Package DataBook 17 System Description Figure 4-2 PG-TSNP-6-9 Package The packages with a triangle and circle laser marking on the Pi n 1 location are identical packages produced at different fabrication sites. Revision 2.01, 2021-03-02 F D E C

Electrical Characteristics

5 Electrical Characteristics

5.1 Absolute Maximum Ratings

Stresses above the max. values listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit.

5.2 Operating Conditions

Within the operational range, the IC operates as explained prod uct description.Typical Values: VCC = 3.8V, TAMB = 25 °C Table 5-1 Absolute Maximum Ratings Parameter Symbol Values Un it Note / Test Condition Min. Typ. Max. VCC Supply Voltage VCC -0.3 – 6.0 V VDD Supply Voltage VDD -0.3 – 1.60 V I/O VI/O -0.3 – 6.0 V ESD robustness HBM VESD,HBM 2000.0 V According to EIA/JESD22-A114 ESD robustness CDM VESD,CDM 500.0 V According to EIA/JESD22-C101 Latch up ILU 100.0 mA According to EIA/ JESD78 Junction temperature range TJ -40.0 85.0 °C Storage Temperature TSTORE -55.0 150.0 °C Table 5-2 Operating Conditions Parameter Symbol Values Un it Note / Test Condition Min. Typ. Max. VCC Supply Voltage Range VCC 2.0 3.8 5.5 V Measurement is at the VCC pin.VCC VDD Supply Voltage Range VDD 1.35 1.45 1.6 V Measurement is at the VDD pin. Need to connect 2.2nF Capacitor.Ramp up of VDD shall be slower than 1µSec. SWI Voltage Range VSWI -0.3 5.5 V Revision 2.01, 2021-03-02

5.3 SWI I/O Characteristics

Current Consumption, Active Idle Mode IVCC, Active-Idle 0.5 mA Idle Function Mode Ave over Active Idle Current Consumption, Active Mode, Authentication Operation IVCC, Active- ECC 1.0 mA Authentication Mode Ave over Authentication Current Consumption, Power-Down Mode IVCC,PD 1.0 3.0 μA SWI is set at 0V Maximum Value condition is set at VCC = 4.35V @ 85 Deg C Ambient Temperature TAMB -40 25 85 °C Table 5-3 SWI I/O Characteristics Parameter Symbol Values Un it Note / Test Condition Min. Typ. Max. SWI Input High Voltage VSWI,IH 1.2 5.5 V SWI Input Low Voltage VSWI,IL -0.30 0.80 V SWI Output High Voltage VSWI,OH 1.30 5.5 V No remote powering, measured at 1.0µA. For Master Only SWI Output Low Voltage VSWI,OL 0.10 V Measured at 1mA SWI Bus Load CSWI,L 250 pF SWI Wake up Voltage VSWI,WK 0.8 1.0 1.2 V SWI Wake up Filter tSWI,WK 72 0 2 8 µ s Table 5-2 Operating Conditions (cont’d) Parameter Symbol Values Un it Note / Test Condition Min. Typ. Max. Revision 2.01, 2021-03-02

5.4 SWI Timing Characteristics

5.5 EEPROM

Table 5-4 SWI Timing Characteristics Parameter Symbol Values Un it Note / Test Condition Min. Typ. Max. Basic Timing Parameters Time Base tSWI 1.0 50 µs Bus Frequency fSWI 10.0 500.0 kHz 50% Zero, 50% One Peak Data Rate 500 kBits/ s Transmit Timing Parameters Duration for 0B tTO 0.75 1.25 t SWI Duration for 1B tT1 2.75 3.25 t SWI Duration for STOP tTS 4.75 t SWI Receive Timing Parameters Duration for 0B tRO 0.5 1.5 t SWI Duration for 1B tR1 2.5 3.5 t SWI Duration for STOP tRS 4.5 t SWI Interrupt Timing Parameters Interrupt Arming Time tARM 4.75 t SWI Interrupt Active Time tINT 0.75 1 1.25 t SWI Drive period for all Slaves Interrupt Trailing Time tTRAIL 3.25 t SWI Drive period for all Slaves Bus Time-Out Parameters Bus Time-Out Period tTOUT 10.0 t SWI Power and Reset Control Timing Parameters Power Down Low Time tPDL 196.0 µs Slave Power Up Delay tPUP 10.0 ms Slave Soft Reset Delay tSRD 1.0 ms Table 5-5 EEPROM Parameter Symbol Values Un it Note / Test Condition Min. Typ. Max. EEPROM Endurance NCYC 105 Cycle 25 Deg C EEPROM Retention Tretent 10 years 25 Deg C EEPROM Programming Time t PROG 5.1 ms Revision 2.01, 2021-03-02

5.6 Authentication Res ponse Computation Time

Table 5-6 Authentication Response Computation Time Parameter Symbol Values Un it Note / Test Condition Min. Typ. Max. Response Computation Time ECCE- 131 TECCE131 34.0 ms Revision 2.01, 2021-03-02

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