SLB9670VQ1.2 INFINEON | Alldatasheet
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SLB 9670 TCG Rev. 116 SLB 9670VQ1.2 SLB 9670XQ1.2 Chip Card and Security Data Sheet Revision 1.0, 2015-11-05
Data Sheet 2 Revision 1.0 2015-11-05 SLB 9670 TPM1.2 Trusted Platform Module
Revision History
Page or Item Subjects (major changes since previous revision) Revision 1.0, 2015-11-05 Initial version.
SLB 9670 TPM1.2 Trusted Platform Module Table of Contents Data Sheet 3 Revision 1.0 2015-11-05 Table of Contents
SLB 9670 TPM1.2 Trusted Platform Module List of Tables Data Sheet 5 Revision 1.0 2015-11-05 List of Tables
Data Sheet 6 Revision 1.0 2015-11-05 SLB 9670 TPM1.2 Trusted Platform Module Overview
1 Overview
The SLB 9670 is a Trusted Platform Module and is based on advanced hardware security technology. This TPM implementation has achieved CC EA L4+ certification and serves as a basis for other TPM products and firmware upgrades. It is available in PG-VQFN-32-13 package. It supports an SPI interface with a transfer rate of up to 43 MHz. The SLB 9670 is a TPM based on TCG family 1.2 specifications (see [1] and [2]).
- Compliant to TPM Main Specif ication, Version 1.2, Rev. 116
- S P I i n t e r f a c e
- Approved for Google Chromebook / Chromebox
- Standard (-20..+80°C) and Enhanc ed temperature range (-40..+85°C)
- PG-VQFN-32-13 package
- Optimized for battery operated devices: low standby power consumption (typ. 110µA)
- 24 PCRs
- 6 kByte free NV memory
- Up to 10 concurrent sessions
- Up to eight 2048-bit keys can be loaded into volatile storage
- 16 slots for keys of up to 2048-bit
- 8 monotonic counters
- 1280 Byte I/O buffer
- Built-in support by Linux Kernel
1.1 Power Management
In the SLB 9670, power management is handled intern ally; no explicit power-down or standby mode is available. The device automatically enters a low- power state after each su ccessful command/response transaction. If a transaction is started on the SPI bus from the host platform, the device will wake immediately and will return to the low-power mode after the transaction has been finished.
2 Device Types / Ordering Information
The SLB 9670 product family features devices using a VQFN package. Table 2-1 shows the different versions. Table 2-1 Device Configuration Device Name Package Remarks SLB 9670VQ1.2 PG-VQFN-32-13 Standard temperature range SLB 9670XQ1.2 PG-VQFN-32-13 En hanced temperature range
Data Sheet 7 Revision 1.0 2015-11-05 SLB 9670 TPM1.2 Trusted Platform Module Pin Description
3 Pin Description
Figure 3-1 Pinout of the SLB 9670VQ1.2 and SLB 9670XQ1.2 (PG-VQFN-32-13 Package, Top View) Table 3-1 Buffer Types Buffer Type Description TS Tri-State pin ST Schmitt-Trigger pin OD Open-Drain pin Table 3-2 I/O Signals Pin Number Name Pin Type Buffer Type Function PG-VQFN-32-13
20 CS# I ST Chip Select
The SPI chip select signal (active low).
19 SCLK I ST SPI Clock
The SPI clock signal. Only SPI mode 0 is supported by the device.
21 MOSI I ST Master Out Slave In (SPI Data)
SPI data which is received from the master.
24 MISO O TS Master In Slave Out (SPI Data)
SPI data which is sent to the SPI bus master.
18 PIRQ# O OD Interrupt Request
Interrupt request signal to the host. The pin has no internal pull-up resistor. The interrupt is active low. GND NCI NCI NCI NCI NCI/VDD NCI NCI/GND MISO GND NCI NC NC NCI NCI NCI NCI TPM SLB 9670 VQ1.2 PG-VQFN-32-13 10 15 2630 Pinning_VQFN-32-13_SLB9670.vsd GND VDD MOSI CS# SCLK PIRQ # RST# NCI/VDD GND NCI NCI NCI GPIO PP VDD
Data Sheet 8 Revision 1.0 2015-11-05 SLB 9670 TPM1.2 Trusted Platform Module Pin Description
17 RST# I ST Reset
External reset signal. Asserting this pin unconditionally resets the device. The signal is active low and is typically connected to the PCIRST# signal of the host. This pin has a weak internal pull-up resistor. 6G P I O I / O T S GPIO-Express-00 Signal This pin is a general purpose I/O pin. It is defined as GPIO-Express-00, please refer to [2] and the PCISIG ECN “Trusted Configuration Space for PCI Express”. This pin may be left unconnected; it has an internal pull- up resistor. 7P P I S T Physical Presence This pin should be connected to a jumper. The standard position of the jumper should connect the pin to GND. If the pin is connected to VDD, some special commands are enabled (for instance, the command TPM_ForceClear, also refer to [1]). This pin may be left unconnected; it has an internal pull- down resistor. Table 3-3 Power Supply Pin Number Name Pin Type Buffer Type Function PG-VQFN-32-13 8, 22 VDD PWR — Power Supply All VDD pins must be connected externally and should be bypassed to GND via 100 nF capacitors. 2, 9, 23, 32 GND GND — Ground All GND pins must be connected externally. Table 3-4 Not Connected Pin Number Name Pin Type Buffer Type Function PG-VQFN-32-13 29, 30 NC NU — No Connect All pins must not be connected externally (must be left floating). 25 - 28, 31 NCI — — Not Connected Internally All pins are not connected internally (can be connected externally). Table 3-2 I/O Signals (continued) Pin Number Name Pin Type Buffer Type Function PG-VQFN-32-13
Data Sheet 9 Revision 1.0 2015-11-05 SLB 9670 TPM1.2 Trusted Platform Module Pin Description
3.1 Typical Schematic
Figure 3-2 shows the typical schematic fo r the SLB 9670. The power supply pi ns should be bypassed to GND with capacitors located close to th e device. The physical presence input may be connected to a jumper as shown in the schematic; or it may be driven by other devices (this is application- or platform-dependent). Figure 3-2 Typical Schematic 1, 14 NCI/VDD — — Not Connected Internally/VDD All pins are not connected internally (can be connected externally). Note that pins 1 and 14 are defined as VDD in the TCG specification [5]. To be compliant, VDD can be connected to these pins.
16 NCI/GND — — Not Connected Internally/GND
This pin is not connected internally (can be connected externally). Note that pin 16 is defined as GND in the TCG specification [5]. To be compliant, GND can be connected to this pins. Table 3-4 Not Connected (continued) Pin Number Name Pin Type Buffer Type Function PG-VQFN-32-13 SLB 9670 SCLK CS# MISO MOSI PIRQ# TPM _CS# PIRQ# VDD GND 3. 3V(1. 8V ) 2x 100 nF (pla ce clos e to device VDD/GND pins ) PP J1GPIO NC/NCI GPIO MISO MOSI Schematic_SLB9670.vsd SCLK 1 µF 3.3V ( 1.8V) RST#RESET #
Data Sheet 10 Revision 1.0 2015-11-05 SLB 9670 TPM1.2 Trusted Platform Module
Electrical Characteristics
4 Electrical Characteristics
This chapter lists the maximum and operating ranges for various electrical and timing parameters.
4.1 Absolute Maximum Ratings
Attention: Stresses above the max. values listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit.
4.2 Functional Operating Range
Table 4-1 Absolute Maximum Ratings Parameter Symbol Values Unit Note or Test Condition Min. Typ. Max. Supply Voltage VDD -0.3 – 7.0 V – Voltage on any pin Vmax -0.3 – V DD+0.3 V – -0.5 – V DD+0.5 V V DD = 3.3V ± 10%; pins MISO, MOSI, SCLK and CS# Ambient temperature TA -20 – 85 °C Standard temperature devices Ambient temperature TA -40 – 85 °C Enhanced temperature devices Storage temperature TS -40 – 125 °C – ESD robustness HBM: 1.5 kΩ, 100 pF VESD,HBM – – 2000 V According to EIA/JESD22-A114-B ESD robustness VESD,CDM – – 500 V According to ESD Association Standard STM5.3.1 - 1999 Latchup immunity I latch 100 mA According to EIA/JESD78 Table 4-2 Functional Operating Range Parameter Symbol Values Unit Note or Test Condition Min. Typ. Max. Supply Voltage VDD 3.0 3.3 3.6 V – 1.65 1.8 1.95 V – Ambient temperature TA -20 – 85 °C Standard temperature devices Ambient temperature TA -40 – 85 °C Enhanced temperature devices Useful lifetime1) 1) The useful lifetime of the device is 5 (five) years with a duty cycle (that means, a power-on time) of 100%. A useful lifetime of 7 (seven) years can be guaranteed for a duty cycle of 70%. For both scenarios, it is assumed that the device will be used for calculations for approximately 5% of the maximum useful lifetime. ––5 y Operating lifetime1) ––5 y Average TA over lifetime – 55 – °C
Data Sheet 11 Revision 1.0 2015-11-05 SLB 9670 TPM1.2 Trusted Platform Module
4.3 DC Characteristics
Note: Current consumption does not include any curren ts flowing through resistive loads on output pins! Table 4-3 Current Consumption Parameter Symbol Values Unit Note or Test Condition Min. Typ. Max. Current Consumption in Active Mode IVDD_Active 25 mA Current Consumption in Sleep Mode IVDD_Sleep 110 µA Pin PP = GND, pins GPIO, RST# and PIRQ# = VDD, CS# inactive (=VDD), MOSI, MISO and SCLK don't care Table 4-4 DC Characteristics of SPI Interface Pins (SCLK, CS#, MISO, MOSI, RST#, PIRQ#) Parameter Symbol Values Unit Note or Test Condition Min. Typ. Max. Input voltage high V IH 0.7 VDD VDD+0.5 V V DD,typ = 3.3V, only pins SCLK, MISO, MOSI and CS# 0.7 VDD VDD+0.3 V V DD,typ = 3.3V, pin RST# 0.7 VDD VDD+0.3 V V DD,typ = 1.8V Input voltage low V IL -0.5 0.3 V DD VV DD,typ = 3.3V, only pins SCLK, MISO, MOSI and CS# -0.3 0.3 V DD VV DD,typ = 3.3V, pin RST# -0.3 0.3 V DD VV DD,typ = 1.8V Input leakage current I LEAK -20 20 µA 0V < V IN < VDD -150 150 µA Pins SCLK, CS#, MISO, MOSI -0.5V < VIN < VDD+0.5V VDD,typ = 3.3V -150 150 µA Pin RST# -0.5V < VIN < VDD+0.3V VDD,typ = 3.3V -150 150 µA -0.3V < V IN < VDD+0.3V VDD,typ = 1.8V Output high voltage V OH 0.9 VDD VI OH = -100µA Output low voltage V OL 0.1 VDD VI OL = 1.5mA Pad input capacitance C IN 10 pF Output load capacitance C LOAD 40 pF
Data Sheet 12 Revision 1.0 2015-11-05 SLB 9670 TPM1.2 Trusted Platform Module
4.4 AC Characteristics
Table 4-5 DC Characteristics of GPIO and PP Pins Parameter Symbol Values Unit Note or Test Condition Min. Typ. Max. Input voltage high V IH 0.7 VDD VDD+0.3 V Pins GPIO and PP Input voltage low V IL -0.3 0.2 V DD VP i n s G P I O a n d P P Input leakage current I LEAK -20 20 µA 0V < V IN < VDD -150 150 µA -0.3V < V IN < VDD + 0.3V Output high voltage V OH 0.7 VDD VI OH = -1mA, pin GPIO Output low voltage V OL 0.3 V I OL < 1mA, pin GPIO Pad input capacitance C IN 10 pF Pins GPIO and PP Table 4-6 Device Reset Parameter Symbol Values Unit Note or Test Condition Min. Typ. Max. Reset Pulse Width t RST 80 µs Cold (power-on) reset Reset Pulse Width t RST 2µ s W a r m r e s e t Table 4-7 AC Characteristics of SPI Interface Parameter Symbol Values Unit Note or Test Condition Min. Typ. Max. SCLK frequency f CLK 43 MHz V DD,typ = 3.3V 22.5 MHz V DD,typ = 1.8V SCLK period t CLK 1/fCLK - 1/fCLK 1/fCLK + µs Rising edge to rising edge, measured at VIN = 0.5 VDD SCLK low time t CLKL 0.45 tCLK µs Falling edge to rising edge, measured at VIN = 0.5 VDD SCLK high time t CLKL 0.45 tCLK µs Rising edge to falling edge, measured at VIN = 0.5 VDD SCLK slew rate (rising/falling) t SLEW 1 4 V/ns between 0.2 V DD and 0.6 VDD CS# high time t CS 50 ns Rising edge to falling edge CS# setup time t CSS 5 ns CS# falling edge to SCLK rising edge CS# hold time t CSH 5n s S C L K f a l l i n g e d g e t o C S # r i s i n g edge
Data Sheet 13 Revision 1.0 2015-11-05 SLB 9670 TPM1.2 Trusted Platform Module
4.5 Timing
Some pads are disabled after deassertion of the reset signal for up to 500 µs. MOSI setup time t SU 2 ns Data setup time to SCLK rising edge MOSI hold time t H 3 ns Data hold time from SCLK rising edge MISO hold time t HO 0 ns Output hold time from SCLK falling edge MISO valid delay time t V 00 . 7 t CLKL ns Output valid delay from SCLK falling edge Table 4-7 AC Characteristics of SPI Interface (continued) Parameter Symbol Values Unit Note or Test Condition Min. Typ. Max.
Data Sheet 14 Revision 1.0 2015-11-05 SLB 9670 TPM1.2 Trusted Platform Module Package Dimensions (VQFN)
5 Package Dimensions (VQFN)
All dimensions are given in millimeters (mm) unless otherwise noted. The pack ages are “green” and RoHS compliant. Figure 5-1 Package Dimensions PG-VQFN-32-13
5.1 Packing Type
PG-VQFN-32-13: Tape & Reel (reel diameter 330mm), 5000 pcs. per reel Figure 5-2 Tape & Reel Dimensions PG-VQFN-32-13
5.2 Recommended Footprint
Figure 5-3 shows the recommended footpr int for the PG-VQFN-32-13 pack age. The exposed pad of the package is internally connected to GND. It shall be connected to GND externally as well. Figure 5-3 Recommended Footprint PG-VQFN-32-13 32x 0.9 MAX. (0.2)SEATING PLANE C 0.05 MAX. 0.05 C 0.1 C 7 x 0.5 = 3.5 0.5 0.4±0.05 (4.2) 0.1 32x BM AC
0.05 M C
-0.07 +0.050.25 2417 ±0.13.6 ±0.13.6 Index Marking B Index Marking A
0.1 A 2x
0.1 B 2x
5.25 5.25 8 0.3 1.1Index Marking PG-VQFN-32-13-TP V01 PG-VQFN-32-13-FP V01 Package outline 5 x 53.6 3.6 4.1 4.1 0.5 0.25 0.7
Data Sheet 15 Revision 1.0 2015-11-05 SLB 9670 TPM1.2 Trusted Platform Module Package Dimensions (VQFN)
5.3 Chip Marking
Line 1: SLB9670 Line 2: VQ12 yy or XQ12 yy (see Table 2-1), the <yy> is an internal FW indication (only at manufacturing due to field upgrade option) Line 3: <Lot number> H <datecode> Figure 5-4 Chip Marking PG-VQFN-32-13 For details and recommendations regarding asse mbly of packages on PCBs, please refer to http://www.infineon.com/cms/en/product/technology/packages/ 1234567 Infineon Lot Code Softwarecode Chip Markin g_VQFN.vs d XXH VQ12 YY
Data Sheet 16 Revision 1.0 2015-11-05 SLB 9670 TPM1.2 Trusted Platform Module References References [1] —, “TPM Main Specificat ion”, Version 1.2, Rev. 116, 2011-03-01, TCG (parts 1-3) [2] —, “TCG PC Client TPM Interface Specif ication (TIS)”, Version 1.3, 2013-03-21, TCG [3] —, “PC Client Implementation Spec ification”, Version 1.2, 2005-07-13, TCG [4] —, “TCG Software Stack Specificat ion (TSS)”, Version 1.2, 2005-11-02, TCG [5] —, “TCG PC Client Platform TPM Profile (PTP) Specification”, Rev. 00.43, 2014-08-04, TCG
Data Sheet 17 Revision 1.0 2015-11-05 SLB 9670 TPM1.2 Trusted Platform Module Terminology Terminology ESW Embedded Software HMAC Hashed Message Authentication Code LPC Low Pin Count (bus) PCR Platform Configuration Register PUBEK Public Endorsement Key SPI Serial Peripheral Interface (bus) TCG Trusted Computing Group TPM Trusted Platform Module TSS TCG Software Stack
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