SLB9645

SLB9645 INFINEON | Alldatasheet

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Chip Card & Security ICs Data Sheet Hardware Description Rev. 1.1, 2014-02-12 TPM Trusted Platform Module SLB9645 TCG Rev. 116 SLB9645VQ1.2 SLB9645TT1.2 SLB9645XT1.2 SLB9645XQ1.2

81726 Munich, Germany

© 2014 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

Data Sheet 3 Rev. 1.1, 2014-02-12 Hardware Description Trademarks of Infineon Technologies AG AURIX™, BlueMoon™, C166™, Ca nPAK™, CIPOS™, CIPURSE™, COMN EON™, EconoPACK™, CoolMOS™, CoolSET™, CORECONTROL™, CROSSAVE™, DAVE™, EasyPIM™, EconoBRI DGE™, EconoDUAL™, EconoPIM™, EiceDRIVER™, eupec™, FCOS™, HITFE T™, HybridPACK™, I²RF™, ISOFACE™, IsoPACK™, MIPAQ™, ModSTACK™, my-d™, NovalithIC™, OmniTune™, OptiMOS™, ORIGA™, PRIMARION™, PrimePACK™, PrimeSTACK™, PR O-SIL™, PROFET™, RASIC™, Re verSave™, SatRIC™, SIEGET™, SINDRION™, SIPMOS™, SMARTi™, SmartLEW IS™, SOLID FLASH™, TEMPFET™, thinQ!™, TRENCHSTOP™, TriCore™, X-GO LD™, X-PMU™, XMM™, XPOSYS™. Other Trademarks Advance Design System™ (ADS) of Agilent Te chnologies, AMBA™, ARM™, MULTI-ICE™, KEIL™, PRIMECELL™, REALVIEW™, THUMB™, µVision™ of ARM Limited, UK. AUTOSAR™ is licensed by AUTOSAR development partnership. Bluetooth™ of Bluetooth SIG Inc. CAT-iq™ of DECT Forum. COLOSSUS™, FirstGPS™ of Trimble Navigation Ltd. EMV™ of EMVC o, LLC (Visa Holdings In c.). EPCOS™ of Epcos AG. FLEXGO™ of Microsoft Corp oration. FlexRay™ is licensed by FlexRay Consortium. HYPERTERMINAL™ of Hilgraeve Incorporated. IEC™ of Commission Electrot echnique Internationale. IrDA™ of Infrared Data Association Corporation. ISO™ of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLAB™ of MathWorks, Inc. MAXIM™ of Maxim Integrated Products, Inc. MICROTEC™, NUCLEUS™ of Mentor Graphics of MURATA MANUFACTURING CO., MICROWAVE OFFI CE™ (MWO) of Applied Wave Research Inc., OmniVision™ of OmniVision Technologies, Inc. Open wave™ Openwave Systems Inc. RED HAT™ Red Hat, Inc. RFMD™ RF Micro Devices, Inc. SIRIUS™ of Sirius Sate llite Radio Inc. SOLARIS™ of Sun Microsystems, Inc. SPANSION™ of Spansion LLC Ltd. Symbian™ of Sy mbian Software Limited. TAIYO YUDEN™ of Taiyo Yuden Co. TEAKLITE™ of CEVA, Inc. T EKTRONIX™ of Tektroni x Inc. TOKO™ of TOKO KABUSHIKI KAISHA TA. UNIX™ of X/Open Company Limited. VERILOG™, PALLADIUM™ of Cadence Design Systems, Inc. VLYNQ™ of Texas Instruments Incorporated. VXWORKS™, WIND RIVER™ of WIND RIVER SYSTEMS, INC. ZETEX™ of Diodes Zetex Limited. Last Trademarks Update 2010-10-26

Revision History

Page or Item Subjects (major changes since previous revision) Rev. 1.1, 2014-02-12 Fixed typos, document references, added note to Table 8 Rev 1.0, 2013-09-17 Initial version

Data Sheet 4 Rev. 1.1, 2014-02-12 Hardware Description Table of Contents

Data Sheet 6 Rev. 1.1, 2014-02-12 Hardware Description List of Tables

Data Sheet 7 Rev. 1.1, 2014-02-12 Hardware Description 1O v e r v i e w The SLB9645 is a Trusted Platform Module. It is available in different packages, see Table 1 below. It only supports the I2C interface and featur es a dedicated interrupt pin which incr eases performance (since no polling on the I2C bus is necessary). The I2C interface is compliant to both standard mode operation (up to 100 kHz) and fast mode operation (up to 400 kHz); for details regarding the characteristics in these modes, please refer to Section 4.5.

Features

• Compliant to TPM Main Specific ation, Version 1.2, Rev. 116
• I2C compatible interface up to 400 kbps
• Approved for Google Chromebook/Chromebox
• Standard (-20..+85°C) and wide temperature range (-40..+85°C)
• TSSOP-28 and VQ FN-32 package
• Optimized for battery operated devices: low standby power consumption (typ.150 µA)
• 24 PCRs
• 6 kBytes free NV memory
• Up to 10 concurrent sessions
• Up to eight 2048-bit keys can be loaded into volatile storage
• 16 slots for keys of up to 2048-bit
• 8 monotonic counters
• 1280 Bytes IO buffer
• Built-in support by Linux™ ke rnel version 3.10 and higher

2 Device Types / Ordering Information

The SLB9645 product family features devices with different packages and different temperature ranges. Table 1 shows the available versions. Table 1 Device Types Device Name Package Remarks SLB9645TT1.2 PG-TSSOP-28-2 Standard temperature range SLB9645XT1.2 PG-TSSOP-28-2 Enhanced temperature range SLB9645VQ1.2 PG-VQFN-32-13 Standard temperature range SLB9645XQ1.2 PG-VQFN-32-13 Enhanced temperature range

Data Sheet 8 Rev. 1.1, 2014-02-12 Hardware Description

3 Pin Description

Figure 1 Pinout of the SLB9645TT1.2 (PG-TSSOP-28-2 Package, Top View) Figure 2 Pinout of the SLB9645VQ1.2 (PG-VQFN-32-13 Package, Top View) SDA SCL NC GND VDD DAVINT# PP NC RESET# VDD GND NC NC NC NC NC NC GND NC NC NC NC NC NC GND NC NC NC TPM SLB 9645 TT 1.2 PG-TSSOP-28-2 14 8 1 4 15182228 Pinning_TSSO P-28-2_S LB9645.vsd VDD VDD NC NC NC NC NC GND NC GND PP SCL SDA NC NC GND NC TPM SLB 9645 VQ 1.2 PG-VQFN-32-13 10 15 2630 Pinning_VQFN-32-13_SLB 9645. vsd NC NC NC NC NC NC NC VDD DAVINT# NC NC NC NC NC RESET#

Data Sheet 9 Rev. 1.1, 2014-02-12 Hardware Description Table 2 Buffer Types Buffer Type Description TS Tri-State pin ST Schmitt-Trigger pin OD Open-Drain pin Table 3 I/O Signals Pin Number Name Pin Type Buffer Type Function PG-TSSOP- 28-2 PG-VQFN- 32-13 12 9 S D A I / O O D I2C Bus Data Signal The data line of the I2C bus. 23 0 S C L I / O O D I2C Bus Clock Signal The clock signal of the I2C bus. 9 8 RESET# I ST Reset External reset signal. Asserting this pin unconditionally resets the device. The signal is active low. 6 2 DAVINT# I/O ST Data Available Interrupt This pin can be connected to the host interrupt controller to allow interrupt driven reads of the response data instead of polling of the TPM_STS_x.dataAvail bit. The signal remains inactive (high) as long as TPM_STS_x.dataAvail is 0. As soon as a response is available, the signal is asserted (low) and remains active until the complete response is read by the host. 73 1 P P I S T Physical Presence This pin should be connected to a jumper. The standard position of the jumper should connect the pin to GND. If the pin is connected to VDD, some special commands are enabled (for instance, the command TPM_ForceClear, also refer to [1]). Table 4 Power Supply Pin Number Name Pin Type Buffer Type Function PG-TSSOP- 28-2 PG-VQFN- 32-13 5, 10 1, 9, 10 VDD PWR — Power Supply All VDD pins must be connected externally and should be bypassed to GND via 100 nF capacitors. 4, 11, 18, 25 16, 26, 32 GND GND — Ground All GND pins must be connected externally.

Data Sheet 10 Rev. 1.1, 2014-02-12 Hardware Description

3.1 Typical Schematic

Figure 3 shows the typical schematic for the SLB9645. The power supply pins should be bypassed to GND with capacitors located close to the devi ce. The physical presence input may be connected to a jumper as shown in the schematic; or it may be driven by other devices (this is application- or platform-dependent). Note that pull-up resistors are needed on the I2C clock and data signals, these are not shown in the schematic. Figure 3 Typical Schematic Table 5 Not Connected Pin Number Name Pin Type Buffer Type Function PG-TSSOP- 28-2 PG-VQFN- 32-13 3, 8, 12 - 17, 19 - 24, 26 - 3 - 7, 11 - 15, 17 - 25, 27, 28 NC NU — Not Connected All NC pins must not be connected externally (must be left floating). SLB 9645 SDA RESET# SDA VDD GND VDD 2x 100 nF (place close to device VDD/GND pins) PP VDD DAVINT# NC Schematic _SLB 9645 .vsd 1 µF SCLSCL 4k7 Physical Presence HW Switch DAVINT# RESET#

Electrical Characteristics

Data Sheet 11 Rev. 1.1, 2014-02-12 Hardware Description

4 Electrical Characteristics

This chapter lists the maximum and operating ranges for various electrical and timing parameters.

4.1 Absolute Maximum Ratings

Attention: Stresses above the max. values listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit.

4.2 Functional Operating Range

Table 6 Absolute Maximum Ratings Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Supply Voltage VDD -0.3 – 7 V – Voltage on any pin Vmax -0.3 – V DD+0.3 V – Ambient temperature TA -40 – 85 °C – Storage temperature TS -40 – 125 °C – ESD robustness HBM: 1.5 kΩ, 100 pF VESD,HBM – – 2000 V According to EIA/JESD22-A114-B ESD robustness VESD,CDM – – 500 V According to ESD Association Standard STM5.3.1 - 1999 Latchup immunity I latch 100 mA According to EIA/JESD78 Table 7 Functional Operating Range Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Supply Voltage VDD 3.0 3.3 3.6 V 3.3 V system environment Supply Voltage VDD 1.62 1.8 1.98 V 1.8 V system environment Ambient temperature TA -20 – 85 °C Standard temperature range devices Ambient temperature TA -40 – 85 °C Enhanced temperature range devices Useful lifetime1) 1) The useful lifetime of the device is 5 (five) years with a duty cycle (that means, a power-on time) of 100%. An useful lifetime of 7 (seven) years can be guaranteed for a duty cycle of 70%. For both scenarios, it is assumed that the device will be used for calculations for approximately 5% of the maximum useful lifetime. ––5 y Operating lifetime1) ––5 y Average TA over lifetime – 55 – °C

Data Sheet 12 Rev. 1.1, 2014-02-12 Hardware Description

4.3 DC Characteristics

TA = 25°C, VDD = 3.3V ± 0.3V or 1.8V ± 0.18V unless otherwise noted Note: Current consumption does not include any currents flowing through resistive loads on output pins! Note: Device sleep mode will be entered after 30 seconds of inactivity after the last TPM command was executed. Table 8 Current Consumption Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Current Consumption in Active Mode IVDD_Active 3.0 25 mA V DD = 3.3V ± 0.3V Device is active and is operating internally. Note that since the device is mostly in an internal sleep state in a “typical” application, the typical average current consumption is far less than the maximum value. It is assumed that in a normal environment, the device is in an internal sleep state for approximately 90% of the operating time of the platform. Current Consumption in Sleep Mode IVDD_Sleep 0.9 mA V DD = 3.3V ± 0.3V, pins SDA and RESET# = VDD Device is active, SCL is toggling but no ongoing internal TPM operation. The device is in an internal sleep state. Current Consumption in Sleep Mode with Stopped Clock IVDD_Sleep_CS 150 µA V DD = 3.3V ± 0.3V, pins SDA, SCL and RESET# = VDD Device is active, SCL is not toggling and no ongoing internal TPM operation. The device is in an internal sleep state. Table 9 DC Characteristics Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Input voltage high VIH 0.7 VDD VDD+0.3 V All pins except RESET# Input voltage low VIL -0.3 0.3 V DD V All pins except RESET# Input voltage high VIH 0.8 VDD VDD V Pin RESET# Input voltage low VIL 0 0.2 V DD V Pin RESET# Input high leakage current IIH -15 15 µA V IN = VDD Input low leakage current IIL -15 15 µA V IN = 0V Output high voltage VOH VDD-0.3 V I OH = 1mA Output low voltage VOL 0.3 V I OL = 1mA

Data Sheet 13 Rev. 1.1, 2014-02-12 Hardware Description

4.4 AC Characteristics

TA = 25°C, VDD = 3.3V ± 0.3V or 1.8V ± 0.18V unless otherwise noted

4.5 I2C Standard/Fast Mode Interface Characteristics

The electrical characteristics are compliant to the NXP I²C bus specification [5] and [6] for “standard-mode” (fSCL ≤ 100 kHz) and “fast-mode” (fSCL ≤ 400 kHz), with certain deviations stated in Table 11 and Table 12 below. For printed circuit board design the reduced output fall time tOF compared to the NXP I²C bus specification needs to be considered! TA = 25°C, VDD = 3.3V ± 0.3V unless otherwise noted Table 10 Device Reset Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Reset Pulse Width tRST 80 — — µs Cold (power-on) reset Reset Pulse Width tRST 10 — — µs Warm reset Table 11 I2C Standard Mode Interface Characteristics Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. SCL clock frequency fSCL 0— 1 0 0 k H z — Output fall time from VIHmin to VILmax (at device pin) tOF — — 75 ns 10 pF ≤ Cb ≤ 400 pF SCL fall time (bus line, output) tfSCL ——2 5n s — Table 12 I2C Fast Mode Interface Characteristics Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. SCL clock frequency fSCL 0— 4 0 0 k H z — Hysteresis of input stage VHYS 0.05 — — V — Output fall time from VIHmin to VILmax (at device pin) tOF 0.4 — 75 ns 10 pF ≤ Cb ≤ 400 pF Spikes suppressed by input filter tSP — 20 — ns Input filter implemented for SCL, not for SDA SCL fall time (bus line, output) tfSCL ——2 5n s — Input current (SCL, SDA) II -10 — 10 µA V IN between 10% and 90% of the supply voltage VDD; the condition “If VDD is switched off, I/O pins of fast-mode devices must not obstruct the SDA and SCL lines” is not fulfilled.

Package Dimensions (TSSOP) Data Sheet 14 Rev. 1.1, 2014-02-12 Hardware Description

5 Package Dimensions (TSSOP)

All dimensions are given in millimeters (mm) unless ot herwise noted. The packa ges are “green” and RoHS compliant. Figure 4 Package Dimens ions PG-TSSOP-28-2

5.1 Packing Type

PG-TSSOP-28-2: Tape & Reel (reel diameter 330mm), 3000 pcs. per reel Figure 5 Tape & Reel Dimensions PG-TSSOP-28-2

5.2 Recommended Footprint

Controlling dimension is millimeters (mm). Figure 6 Recommended Footprint PG-TSSOP-28-2 2) Does not include dambar protrusion of 0.08 max. per side 1) Does not include plastic or metal protrusion of 0.15 max. per side Index Marking GPS09034 1)±0.19.7 ±0.10.6 A

0.13 M 28xAC

0.65 0.22 2) -0.03 +0.08

0.25 M 28xB

0.1±0.05 ±0.05 C 0.1 1.1 MAX. 0.9 -0.035 B 0.125 +0.075 ±0.14.4 1) ...8˚0˚ 6.4 10.2 6.8 16 ±0.3 1.6 1.2 0.3 L B A e

Package Dimensions (TSSOP) Data Sheet 15 Rev. 1.1, 2014-02-12 Hardware Description

5.3 Chip Marking

Line 1: SLB9645TT12 or SLB9645XT12 (see Table 1) Line 2: G <datecode> KMC, <K> indicates assembly site code, <MC> indicates mold compound code Line 3: 00 <Lot number>, the 00 is an internal FW indication (only at manufacturing due to field upgrade option) Figure 7 Chip Marking PG-TSSOP-28-2 Table 13 Recommended Footprint Dimensions (PG-TSSOP-28-2) e 0.65 mm 25.6 mil A 6.10 mm 240 mil L 1.30 mm 51 mil B 0.40 mm 16 mil 12345678901 12XXXXXXXXXXX G KMC Mold Compound Code Lot CodeSoftwarecode Assembly Site Code ChipMarking.vsd

Package Dimensions (VQFN) Data Sheet 16 Rev. 1.1, 2014-02-12 Hardware Description

6 Package Dimensions (VQFN)

All dimensions are given in millimeters (mm) unless ot herwise noted. The packa ges are “green” and RoHS compliant. Figure 8 Package Dimensions PG-VQFN-32-13

6.1 Packing Type

PG-VQFN-32-13: Tape & Reel (reel diameter 330mm), 5000 pcs. per reel Figure 9 Tape & Reel Dimensions PG-VQFN-32-13

6.2 Recommended Footprint

Figure 10 shows the recommended footprint for the PG-VQFN-32-13 package. Figure 10 Recommended Footprint PG-VQFN-32-13 32x 0.9 MAX. (0.2)SEATING PLANE C 0.05 MAX. 0.05 C 0.1 C 7 x 0.5 = 3.5 0.5 0.4±0.05 (4.2) 0.1 32x BM AC

0.05 M C

-0.07 +0.050.25 2417 ±0.13.6 ±0.13.6 Index Marking B Index Marking A

0.1 A 2x

0.1 B 2x

5.25 5.25 8 0.3 1.1Index Marking PG-VQFN-32-13-TP V01 PG-VQFN-32-13-FP V01 Package outline 5 x 53.6 3.6 4.1 4.1 0.5 0.25 0.7

Package Dimensions (VQFN) Data Sheet 17 Rev. 1.1, 2014-02-12 Hardware Description

6.3 Chip Marking

Line 1: SLB9645 Line 2: VQ12 yy or XQ12_yy (see Table 1), the <yy> is an internal FW indication Line 3: <Lot number> H <datecode> Figure 11 Chip Marking PG-VQFN-32-13 1234567 Infineon Lot Code Softwarecode ChipMarking_VQFN.vsd XXH VQ12 YY

Data Sheet 18 Rev. 1.1, 2014-02-12 Hardware Description References [1] —, “TPM Main Specification”, Version 1.2, Rev. 116, 2011-03-01, TCG (parts 1-3) [2] —, “TCG PC Client TPM Interface Specific ation (TIS)”, Version 1.21, 2011-04-28, TCG [3] —, “PC Client Implementation Specific ation”, Version 1.2, 2005-07-13, TCG [4] —, “TCG Software Stack Specification (TSS)”, Version 1.2, 2005-11-02, TCG [5] —, “NXP I²C bus specification, Rev. 03”, 19 June 2007 [6] —, “NXP I²C bus specification, Rev. 4”, 13 February 2012

Data Sheet 19 Rev. 1.1, 2014-02-12 Hardware Description Terminology I2C Inter-Integrated Circuit PCR Platform Config uration Register TCG Trusted Computing Group TPM Trusted Platform Module TSS TCG Software Stack

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