SLB0586

SLB0586 SIEMENS | Alldatasheet

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‘© Sensor operation - no mechanically moved switching elements ? @ Operation is also possible from several extensions i > i | by means of sensors or push buttons © Can replace electromechanical wall switches in conventional light installations wro0so2s © Brightness control with a physiologically P-DIP-8 approximated linear characteristic —$___—_— @ Very high interference immunity, also against a a ripple control signals @ Very few peripheral components ‘@ Programming input permits selection of three different functions (MODE A/B/C) ae © *Soft" turn-ON with MODE A and C vesosi2 P-DSO-8-1 Type Ordering Code Package - SLB 0586A — Q67000-H8721 _—P-DIP-8 & SLB 0586 G | Q67000-H8720 | P-DSO-8-1 (SMD) The SLB 0586 A and SLB 0586 G are integrated circuits in CMOS technology that permit the design of digital electronic dimmers. A single sensor or an equivalent extension input are used to turn the dimmer ON and OFF and to set the required brightness. Semiconductor Group 301 9.92

SLB 0586 A SLB 0586 G | | CI Yool]1 8[] az Yop Ot 8p az

1 PROG C12

1 prog []2 71) Ms 7) Mss c op 6HOIN «(3 {JIN 1SYNC C4 spor sen | rsync [4 S[]IseNn 1£P00093 | Term: Pin Configurations (top view) Pin Definitions and Functions PinNo. [Symbol _| Function 2 [1PROG | Programming input

3 C: integrator

5 | SEN Sensor input

6 IN Extension input

7 Supply voltage

8 Trigger pulse output

hi : : e3< 2F8 KD oe Bee Bsé | "I | aso Bs FEF aso Zo Block Diagram Semiconductor Group 303

The SLB 0586 A permits the design of fully electronic dimmers for light bulbs (resistive loads) which are operated via a single sensor. The integrated circuit replaces mechanical wall switches in conventional light circuit installations. All functions can be selected from several switching points (extensions). The brightness is set by phase control. Its digital logic is synchronized with the line frequency (see Block Diagram). It is possible to supply the IC via a two-wire connection, as the angle of current flow is limited to a maximum of 152 ‘C of the half wave. Operation The integrated circuit can distinguish the instruction “ON/OFF" and "Dimming" by the duration for which control input is operated i.e. the sensor is touched (refer to figure 1). Turning ON/OFF Short touching (50 to 400 ms) of the sensor area turns the lamp ON or OFF, depending on its preceding state. The switching process is activated as soon as the sensor is released. Setting of the Brightness (Dimming) If the sensor is touched for a longer period (> 400 ms), the angle of current flow will be varied continuously. It runs across its control loop in approximately 7.6 s (e.g. bright-dark- bright) and continues this sequence until the sensor is released. Easy operation, even in the lower brightness range, is enabled by the following procedure: the phase control angle is controlled such that the lamp brightness varies physiologically-linear with the operating time and pauses for a short period when the minimum brightness is reached. Using Re and Cs in the application circuit the angle of current flow can be controlled between 40° and 148°. Control Behavior The three operating MODES A, B, C, differ in their control behavior. The required MODE is set with the programming input. MODE A With turn-ON, the maximum brightness level is set; with dimming, control starts from the minimum brightness level. With repeated dimming, control is carried out in the same direction (e.g. "brighter’). MODE B_ With turn-OFF, the selected brightness is stored and set again when the switch is turned on. Dimming starts at this stored value and the control direction is reversed with repeated dimming. MODE C With turn-ON, the maximum brightness is set; with dimming, contro! is started from the minimum brightness. The control direction is reversed with repeated dimming. Semiconductor Group 304

Programming of the MODES. MODE A: Ve = Vss (L) MODE B: Ve = open (tristate) MODE C: Vie = Voo (H) Ve = Level at pin 2 © s TT 180° nig | we | Ot 150° St ToT Mime | a [J [Tt hn Of 150° a mas co a fo) ° ain | Yo © 180° ST ee Ymos Mey [pe [| y20 0 1 2 3 6 5 6 7 BF HM BH BH — serseasy a Angle of current fiow S Control signal: S Sensor touched ¥, Lamp voltage {<0.4s,-> 04s) S Sensor not touched Figure 1 Control Behavior of Operating MODES (schematic) MODES A and C permit “soft” turn-ON; i.e. brightness is increased from 0 to maximum within 380 ms. Semiconductor Group 305,

Pin5,6 Pin 2 ? g ZX AX - 8002 8002 sso} | Fp 2 ZX ZX i i Pin 3 Pin & r---4 ? 9 oto | 1 ZX XK | js I ' | 8002 8002 ! 1 3 bo | af p { | ' ! 180K ZK KR | ! ‘Limitation of t ISubstrat Current | ba — 4 IES 00095, | Pin8 Pind = Pin? ; Vos | : IF Figure 2 7 _ 7 Internal Wiring of Pins Semiconductor Group 306

® | al] | TT | dae doe] foto | AY rx i a aa l pop Hoe) Loe | rm = © esone | w50Vee Quow sersor Eitenson ne Figure 3 Application Circuit The suggested circuit design of the SLB 0586 A performs the following functions: @ Current supply for the circuit (Rs, C2, D1, D2, Cs) @ Filtered signal for synchronization of the internal time base (PLL circuit) with line frequency (R 2, Cs). For specific applications Ca can be increased up to 33 nF, so that the lamp gets darker (refer to figure 3). @ Integration unit for internal PLL circuit (Cs, Ro) ‘© Protection of the user (Re, Rs) @ Sensitivity setting of the sensor (R7) @ Current limitation in the case of reverse polarity of the extension (Rs, Rs). Both resistors can be omitted, if no extension is connected. In this case pin 6 must be interconnected with Vss (pin 7). @ D3: Reduction of positive voltages which may arise during the triggered state at the gate of some triacs to values below Voo + 0.3 V by diode forward voltage. If suitable triacs are used, diode D3 can be omitted. ‘@ Dr: The choke and the capacitor C; are used for EMI suppression. Depending on the application, the EMI suppression is to be dimensioned in acc. with VDE 0875/part 1 (general) VDE 0550/part 6 (chokes) or corresponding to national regulations Semiconductor Group 307

@ The components Cs 10...100 nF ceramic C7 33...68 nF Ds Ge or Schottky diode Rv: 33.68 2 serve to improve interference immunity under special conditions like for example: — high-frequency line interferences — long extension lines with high earth capacitances — supply line resistances in the load circuit and can therefore be dropped for normal operating conditions. @ At 110 V/60 Hz line: C2: 150 nF/160 Vac Re: 680 kar Application Notes 1.Synchronization Interference of the synchronization can be suppressed by setting the C: filter capacitor at the sync input between 3.3 and 33nF. By increasing the Cs value the range of the controllable conduction angles goes to less minimum brightness. At the same time, the immunity against superimposed interference from the line improves, so that, for example, with Cs =33nF an interference amplitude of 30V does not cause any synchronization errors in the range of 150 to 1500 Hz. Cs (nF) Conduction angle (°) Interference amplitude (V) 3.3 151 to 43 20 6.8 148 to 40 10.0 147 to 39 15.0 144 to 36 33.0 136 to 28 30 2. PLL Circuit The PLL circuit at pin 3 can be varied to reach a minimum of flickering and a maximum of noise immunity. The PLL circuit is adjusted to a capacitor value of 100 nF. Rw can be varied in the range of 22 ka to 680 k2 (figure 5). Here higher resistances speed up the response of the PLL. circuit. Hence it is possible to reduce the jitter of the trigger pulse to below 0.5 ms by a low- resistance Rio at low interference frequencies (< 400 Hz) and a high-resistance Rio at high interference frequencies. This will greatly reduce brightness modulations through interferences. Semiconductor Group 308

1. Dependence of Cs and Angle of Current Flow (Figure 4) 1 160} | : ooo : Angle of Current Flow Range: we een aaa Ay - ft AMSLLA GS pee te - i - a foe 0 10 20 30 nF 40 Go 4. Range of Value of the RC-Component at Pin 3 for Stationary PLL-Operation (Figure 5) 1000 repos T T KQ - eet COLLCETVLELL LL ai | Stationary PLL Range | | | woL er ee a i) 100 200 300 nF 400 Semiconductor Group 309

1. Extensions All switching and contro! functions can also be performed from extensions which are connected to the extension input. The main sensor input and the extension inputs have equal priority. Electronic sensor switches or mechanical pushbutton switches can be connected to the extensions. During operation "H" potential must be applied to the extension input for both half cycles. Note The extension input must be connected to Vss, if this input is not required. Operation of the Control Inputs Input potential during both half waves of the line phase: Function : Line Half Wave Sensor Input Extension Input positive L H Operated — $$$ negative 0 H Not operated L Wireless Remote Control The connection of a wireless remote control to the extension is very easy. All functions of the SLB 0586 A can be performed with the aid of a single transmission channel. 6. interference Immunity A digitally determined immunity period of approximately 50 ms ensures a high interference immunity against electrical variations on the control inputs and additionally allows almost delay-free operation. Due to the special logic of the extension input, even large ground capacitances of the contro! line will not lead to interference. In case of power failure the set switching state with the recommended external circuitry remains stored. After prolonged power failure (Vss > — 3.6 V) the circuit turns into OFF- state. The control characteristic of the synchronous oscillator (PLL circuit) is designed such that interference due to ripple control signals may cause slight variations in brightness. However, they will not lead to a malfunction of the dimmer. Semiconductor Group 310

1. General Information All time specifications refer to a line frequency of 50 Hz. In case of a line frequency of 60 Hz, the times are reduced accordingly. 8. Functional Description of Evaluation Logic for Sensor and Extension Inputs The logic status at the sensor and extension inputs are sampled by latches L1 and L2 using the time slot pattern shown in the timing diagram (figure 6). For operation (ON/OFF or DIMMING) "1" must be present at the D input of FF1 for two consecutive rising edges of the 50 Hz clock pulse of the internal PLL. The flipflops FF1 and FF2, are reset by two logic zeros occurring at the same time at latch outputs L1 and L2. For operation via the extension input five consecutive sampling values must be "1". The minimum immunity time is therefore approx. 24 ms. Due to the different sampling rates, two sampling values of "1" must follow at the sensor input for an operation to be recognized. In this case the minimum immunity time is approx. 39 ms. Semiconductor Group 3

SEN Lf (—al'| —o operation. | 4 | 0 att, ON/OFF | Fe Yc Dimming | Strobe_ SEN EN R R JL 39ps ['t EXT ° oO Q 12 PLL_SOHz. Strobe_ EXT EN 1ES00682 | ML ssys Figure 6 Schematic Circuit Diagram of Evaluation Logic for Sensor and Extension Inputs a oe toms ‘SOHz Mains 0.68ms PLL_SOKz

50 Hz Clock of

Strobe_EXT. ‘Sampling Point for Extension Input 09ms 20ms _ ‘Strobe_SEN: Sampling Point for Sensor Input ‘eran Figure 7 Timing Diagram of Evaluation Logic for Sensor and Extension Inputs Semiconductor Group 32

| nN ZX 0 n | Input Comparator | AK ZK ZK 02 Figure 8 6 Schematic Circuit Diagram at Synchronous Input Functional Description Diodes D1 and D2 have characteristics similar to Z-diodes and start conducting at about 25V. In spite of the line voltage at the triac it is ensured - by using Re - that the voltages present at the synchronous input of SLB 0586 A remain within the supply voltage level. To obtain a highly stable trigger point for the phase comparator, T1 becomes conductive only after recognizing the synchronization edge. Semiconductor Group 313

Program O— — > | Input L, | a ‘Sampling Values charge a = Sampling Clock 1 Pulse 1 — Sampling Clock 2 | 1es00679 | Figure 9 Schematic Circuit Diagram at Programming Input (Pin 2) Functional Description of Pin 2 (Programming Input) The SLB 0586 A provides the possibility of differentiating between types A, B, and C by appropriate connection of pin 2. Depending on the charge pulses shown in figure 9 transistors T3 and T4 alternate in becoming conductive. The currents flowing during the conductive phase of the transistors are sufficient for a charge reversal of the load capacitance of 7 pF max. present at pin 2. It is important that no major discharge of the capacitance present at pin 2 occurs from the time of charge reversal until the sampling of the voltage level by the two sampling clocks. Semiconductor Group 314

‘approx. 20ns i I [ | Charge Pulse 1 | Charge Pulse 2 | “Date Acceptance Sampling Clock 2 | Type | i AO 0 0 ° Boo 1 0 1 Sampling Values C4 1 1 1 e106 Figure 10 Internal Timing for Differentiating between the three Possible Modes A, B, and C Semiconductor Group 315

Voo = OV Parameter Symbol Limit Values Unit min, [max Supp woe lie |[-75 03 WV input voage [ve-08 03 Input urent ti )-05 0s [mA Storage temperature Te = 55 [725 |C Total power dissipation (Ta = 25 ‘C) i [10 | mw Thermal Resistance System-air P-DSO-8 Rosa 231 KW Operating Range Supply voltages Vs j-se [-45 |v Line frequency _ _\\f ATs 63 Hz Ambient temperature _ _ Ta jo 80 Cc Characteristics Ta = 25 C; Vas = —5 V (Voo = 0V) Parameter Symbol “Limit Values —_—_—| Unit | Test Condition min. typ. max. . _ Quiescent current | (Pint) Joo 7 0.45 | MA__ fare = 50H2 Sensor Input (pin 5) H-input voltage V2Veset | lv - L-input voltage wevestt Vo | Input current In 33 37 wA | 220Vat sensor input and series resistor HL transition time | mw line sine ({rigger transition) wave | LH transition time | rma i Frequency with t 50/60 Hz | synchronized active signal with 50/60Hz | clock at sync _ _| input Semiconductor Group 316

Characteristics (cont'd) Ts = 25 "C; Vss =- 5 V (Voo = 0 V) Parameter Symbol Limit Values Unit | Test Condition min. typ. max. Extensions (pin 6) H-input voltage Vii 1/2 Vase1.t | — _ L-input voltage 4/2 Ves-1.1 Input current Tus -4 0 vi=0V Te 0 1 Vi= Vss Sync Input (pin 4) Gi H-input voltage Vn 1/2 Vss418 v__ [with series L-input voltage Vi 1/2. Ves-18 |V | resistor 1.5 Ma Input current Tis 207 ee nA | from 220 Viine*! HL transition time — | re supply (trigger transition) sine LH transition time mut wave _ Frequency f 50/60 Hz Programming Input (pin 2) Load capacitance [C. ] 7 —|pF OT through board with tristate Integrator (pin 3) Application circuit | Cs 68 100 | 330 nF Rio 22 100 680 ka Output (pin 8) Coutputcurrent [fo [25 mA | Va=-3V L-pulse width to 39.0 us | 50Hz supply 32.6 us | 60Hz supply Hc transition time | wo 5 us LH transition time 1uH0, L 5 us *) see Application Circuit Semiconductor Group 317