SH88F6161

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Document overview

• Manufacturer or author: Jason
• PDF pages: 205

Technical content

Enhanced 8051 Microcontroller 1 V2.2 1. Features  8 bits micro -controller with Pipe-line structured 8051 compatible instruction set  Flash ROM: 64K Bytes  ISP ROM: 1K Bytes  RAM: internal 256 Bytes, external 2816 Bytes  EEPROM-Like:bulid-in 2048 Bytes  5 Bytes MCU identification number to be readable  The highest CPU frequency up to 24M  Operation Voltage: VDD = 2.0V - 5.5V  Oscillator (code option): - High frequency Crystal oscillator: 2MHZ-12MHZ - low frequency Crystal oscillator: 32.768kHz - internal frequency Ceramic oscillator: 12MHz - Internal low frequency RC oscillator: 128KHz - PLL oscillator: four times  61 CMOS bi-directional I/O pins  Built-in pull-up resistor for input pin  Two 16-bit timer/counters T2 and T3  Four PCA, of which the PCA0 , PCA2, PCA3 each containing two comparison/capture moudles, PCA1 has three comparative/capture moudles  10 External interrupt sources  Powerful interrupt sources: - Timer2, 3, PCA0, 1, 2, 3 - INT2, 3 INT40-47 - ADC, DAC, SCM, LPD - EUART0, EUART1, TWI, SPI, USB  LCD driver: - 4 X 40dots (1/4 duty 1/3 bias) - 5 X 39 dots (1/5 duty 1/3 bias) - 6 X 38 dots (1/6 duty 1/3 bias)  LED driver: 10 X 8dots  Two Enhanced UART (EUART) with own baud rate generator  Built-in regulator - Output: 3.3V  12-bit 1M spsSAR Analog Digital Converter - built-in 1.5V/2.5V reference voltage - 12 external analog inputs  12-bit voltage type DAC digital-to-analog converters - 12-bit Accuracy - 1 channel  The Universal Serial Bus (USB) - Compatible with USB2.0 (Full speed 12Mbps) - Support control, interrupt and buck data transfer - Support 3 endpoints: (EP0, EP1, EP2)  Built-in operational Amplifier (OP)  SPI (Master/slave Mode)  TWI (I2C Interface)  Built-in low voltage Reset (LVR) function (code option) - LVR Voltage: 2.1v - LVR Voltage: 2.7v - LVR Voltage: 3.7v - LVR Voltage: 4.1v  CPU Machine period: 1 oscillator clock  Built-in Watch Dog Timer (WDT) (code option)  Built-in oscillator Warm-up timer  Support Low power operation modes: - Idle Mode - Power-Down Mode  Flash Type  Package: LQFP64, TQFP48 2. General Description The SH88F6161/SH88F6162 is a high performance 8051 compatible micro-controller, regard to its build-in Pipe-line instruction fetch structure, that helps the SH88F6161/SH88F6162 can perform more fast operation speed and higher calculation performance, comparing with standard 8051 at same clock speed. The SH88F6161/SH88F6162 retains most features of the standard 8051. These features include internal 256 bytes RAM and Two 16-bit timer/counters,In addition, the SH88F6161/SH88F6162 provides external 2816 bytes RAM, It also contains 64 K bytes Flash memory block both for program and data. In addition to 2K EEPROM -Like integrated,used to save the data after system power down. SH88F6161/SH88F6162 includes: 61 CMOS bi-directional I/O pins, 4 PCA, Two Enhanced UART (EUART) with own baud rate generaor、LCD driver、LED driver、DAC、ADC、USB (not in SH88F6161)、operational Amplifier、SPI、TWI. For high reliability and low cost issues, the SH88F6161/SH88F6162 builds in Watchdog Timer, Low Voltage Reset function. And SH88F6161/SH88F6162 also supports two power saving modes to reduce power consumption.

1. Block Diagram 64K Bytes Flash ROM XTAL2 XTAL1 VDD Power Internal 256 Bytes External 2816 Bytes Data RAM Timer2 (16bit) Timer3 (16bit) 1K Bytes ISP ROM External Interrupt EUART*2 12-Bit ADC Internal RC Oscillator1 Pipelined 8051 architecture Reset circuit Watch Dog Port 0 Configuration IO Port 1 Configuration IO Port 2 Configuration IO Port 3 Configuration IO Port 4 Configuration IO Port 5 Configuration IO Port 6 Configuration IO Port 7 Configuration IO P0.0 - P0.7 P1.0 - P1.7 P2.0 - P2.7 P3.0 - P3.7 P4.0 - P4.7 P5.0 - P5.7 P6.0 - P6.7 P7.0 - P7.4 /Reset USB TWI SPI 12-Bit DAC LCD/LED ITAG Port (for Debug) OP Regulator 2K Bytes EEPROM PCA0 PCA1 PCA2 PCA3 Oscillator2XTALX1 XTALX2

1. Pin Configration

4.1 LQFP64 Package

XTAL2/P7.2 SEG19/INT42/P5.2 SEG20/INT43/P5.3 P4.6/SEG15/TXD1 P4.7/SEG16/RXD1 P5.0/INT40/SEG17 ADC6/LED_C10/SEG35/P0.6 ADC7/LED_C9/SEG36/P0.7 P5.1/INT41/SEG18 ADC8/LED_C8/SEG37/P1.0 ADC9/LED_C7/SEG38/P1.1 ADC10/LED_C6/COM6/SEG39/P1.2 ADC11/LED_C5/COM5/SEG40/P1.3 P2.5/OPP1 P1.5/COM3/LED_C3/CREF P1.6/COM2/LED_C2/DACO MISO/ADC3/SEG32/P0.3 MOSI/ADC2/SEG31/P0.2 SS/ADC1/P0.1 SCK/ADC0/P0.0 P2.0/OPN2 P2.1/OPN1/TCK P2.2/OPN0/TDI P2.3/OPO/TMS P2.4/OPP0/TDO P2.7/D+ XTAL1/P7.1 XTALX2/P7.4 P0CEX0/SEG26/INT2/P6.1 P0CEX1/SEG25/P6.0 SEG21/INT44/P5.4 SEG22/INT45/P5.5 GND VDD VDDR SCL/P6.6 SDA/P6.7 XTALX1/P7.3 SEG23/INT46/P5.6 SEG24/INT47/P5.7 RXD/SEG30/P6.5 P3.0/SEG1/LED_S1 P3.1/SEG2/LED_S2 P3.2/SEG3/LED_S3/ECI1 P3.3/SEG4/LED_S4/P1CEX0 P3.4/SEG5/LED_S5/P1CEX1 P3.5/SEG6/LED_S6/P1CEX2 P3.6/SEG7/LED_S7/ECI2 P3.7/SEG8/LED_S8/P2CEX0 P4.0/SEG9/P2CEX1 P4.1/SEG10/ECI3 P4.2/SEG11/P3CEX0 P4.3/SEG12/P3CEX1 P4.4/SEG13/T2EX P4.5/SEG14/T2 T3/SEG28/P6.3 ECI0/SEG27/INT3/P6.2 TXD/SEG29/P6.4 RESET/P7.0 SH88F6162 38 37 36 35 34 3339404142434445464748 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VREF/LED_C4/COM4/P1.4 ADC4/SEG33/P0.4 ADC5/SEG34/P0.5 P2.6/D- P1.7/COM1/LED_C1 SH88F6162 Pin Configuration Diagram

XTAL2/P7.2 SEG19/INT42/P5.2 SEG20/INT43/P5.3 P4.6/SEG15/TXD1 P4.7/SEG16/RXD1 P5.0/INT40/SEG17 ADC6/LED_C10/SEG35/P0.6 ADC7/LED_C9/SEG36/P0.7 P5.1/INT41/SEG18 ADC8/LED_C8/SEG37/P1.0 ADC9/LED_C7/SEG38/P1.1 ADC10/LED_C6/COM6/SEG39/P1.2 ADC11/LED_C5/COM5/SEG40/P1.3 P2.5/OPP1 P1.5/COM3/LED_C3/CREF P1.6/COM2/LED_C2/DACO MISO/ADC3/SEG32/P0.3 MOSI/ADC2/SEG31/P0.2 SS/ADC1/P0.1 SCK/ADC0/P0.0 P2.0/OPN2 P2.1/OPN1/TCK P2.2/OPN0/TDI P2.3/OPO/TMS P2.4/OPP0/TDO XTAL1/P7.1 XTALX2/P7.4 P0CEX0/SEG26/INT2/P6.1 P0CEX1/SEG25/P6.0 SEG21/INT44/P5.4 SEG22/INT45/P5.5 GND VDD NC SCL/P6.6 SDA/P6.7 XTALX1/P7.3 SEG23/INT46/P5.6 SEG24/INT47/P5.7 RXD/SEG30/P6.5 P3.0/SEG1/LED_S1 P3.1/SEG2/LED_S2 P3.2/SEG3/LED_S3/ECI1 P3.3/SEG4/LED_S4/P1CEX0 P3.4/SEG5/LED_S5/P1CEX1 P3.5/SEG6/LED_S6/P1CEX2 P3.6/SEG7/LED_S7/ECI2 P3.7/SEG8/LED_S8/P2CEX0 P4.0/SEG9/P2CEX1 P4.1/SEG10/ECI3 P4.2/SEG11/P3CEX0 P4.3/SEG12/P3CEX1 P4.4/SEG13/T2EX P4.5/SEG14/T2 T3/SEG28/P6.3 ECI0/SEG27/INT3/P6.2 TXD/SEG29/P6.4 RESET/P7.0 SH88F6161 38 37 36 35 34 3339404142434445464748 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VREF/LED_C4/COM4/P1.4 ADC4/SEG33/P0.4 ADC5/SEG34/P0.5 P1.7/COM1/LED_C1 P2.7 P2.6 SH88F6161 Pin Configuration Diagram

4.2 TQFP48 Package

1 2 3 4 5 6 7 8 9 10 11 12 XTAL2/P7.2 ADC6/LED_C10/SEG35/P0.6 ADC7/LED_C9/SEG36/P0.7 ADC8/LED_C8/SEG37/P1.0 ADC9/LED_C7/SEG38/P1.1 ADC10/LED_C6/COM6/SEG39/P1.2 ADC11/LED_C5/COM5/SEG40/P1.3 XTALX2/P7.4 XTALX1/P7.3 VREF/LED_C4/COM4/P1.4 ADC4/SEG33/P0.4 ADC5/SEG34/P0.5 P1.5/COM3/LED_C3/CREF P1.6/COM2/LED_C2/DACO P2.1/OPN1/TCK P2.2/OPN0/TDI P2.3/OPO/TMS P2.4/OPP0/TDO GND VDD VDDR P3.0/SEG1/LED_S1 P3.1/SEG2/LED_S2 P1.7/COM1/LED_C1 SEG17/INT40/P5.0 SEG18/INT41/P5.1 P3.2/SEG3/LED_S3/ECI1 P3.3/SEG4/LED_S4/P1CEX0 P3.4/SEG5/LED_S5/P1CEX1 P3.5/SEG6/LED_S6/P1CEX2 P3.6/SEG7/LED_S7/ECI2 P3.7/SEG8/LED_S8/P2CEX0 P4.0/SEG9/P2CEX1 P4.1/SEG10/ECI3 P4.2/SEG11/P3CEX0 P4.3/SEG12/P3CEX1 SEG19/INT42/P5.2 SEG20/INT43/P5.3 XTAL1/P7.1 P0CEX0/SEG26/INT2/P6.1 P0CEX1/SEG25/P6.0 RXD/SEG30/P6.5 T3/SEG28/P6.3 ECI0/SEG27/INT3/P6.2 TXD/SEG29/P6.4 RESET/P7.0 P2.7/D+ P2.6/D- SH88F6162 Pin Configuration Diagram

1 2 3 4 5 6 7 8 9 10 11 12 XTAL2/P7.2 ADC6/LED_C10/SEG35/P0.6 ADC7/LED_C9/SEG36/P0.7 ADC8/LED_C8/SEG37/P1.0 ADC9/LED_C7/SEG38/P1.1 ADC10/LED_C6/COM6/SEG39/P1.2 ADC11/LED_C5/COM5/SEG40/P1.3 XTALX2/P7.4 XTALX1/P7.3 VREF/LED_C4/COM4/P1.4 ADC4/SEG33/P0.4 ADC5/SEG34/P0.5 P1.5/COM3/LED_C3/CREF P1.6/COM2/LED_C2/DACO P2.1/OPN1/TCK P2.2/OPN0/TDI P2.3/OPO/TMS P2.4/OPP0/TDO GND VDD NC P3.0/SEG1/LED_S1 P3.1/SEG2/LED_S2 P1.7/COM1/LED_C1 SEG17/INT40/P5.0 SEG18/INT41/P5.1 P3.2/SEG3/LED_S3/ECI1 P3.3/SEG4/LED_S4/P1CEX0 P3.4/SEG5/LED_S5/P1CEX1 P3.5/SEG6/LED_S6/P1CEX2 P3.6/SEG7/LED_S7/ECI2 P3.7/SEG8/LED_S8/P2CEX0 P4.0/SEG9/P2CEX1 P4.1/SEG10/ECI3 P4.2/SEG11/P3CEX0 P4.3/SEG12/P3CEX1 SEG19/INT42/P5.2 SEG20/INT43/P5.3 XTAL1/P7.1 P0CEX0/SEG26/INT2/P6.1 P0CEX1/SEG25/P6.0 RXD/SEG30/P6.5 T3/SEG28/P6.3 ECI0/SEG27/INT3/P6.2 TXD/SEG29/P6.4 RESET/P7.0 P2.7 P2.6 SH88F6161 Pin Configuration Diagram Note: The out most pin function has the highest priority, and the inner most pin function has the lowest priority. This means when one pin is occupied by a higher priority function (if enabled) cannot be used as the lower priority functional pin, even when the lower priority function is also enabled. Until the higher priority function is closed by software, can the corresponding pin be released for the lower priority function use.

Table 4.1 Pin Function Pin No. LQFP64 Pin Name Type Function description 1 XTAL2/P7.2 O I/O XTAL2: external crystals output pin P7.2: bi-directional I/O port Default function: P7.2 2 XTALX1/P7.3 I I/O XTALX1: external crystals input pin P7.3: bi-directional I/O port Default function: P7.3 3 XTALX2/P7.4 O I/O XTALX2: external crystals output pin P7.4: bi-directional I/O port Default function: P7.4 4 SCK/ADC0/P0.0 I/O I I/O SCK: SPI the bus clock pin ADC0: ADC input channel0 P0.0: bi-directional I/O port Default function: P0.0 5 SS/ADC1/P0.1 I/O I I/O SS: SPI chip select signal ADC1: ADC input channel1 P0.1: bi-directional I/O port Default function: P0.1 6 MOSI/ADC2/SEG31/P0.2 I/O I O I/O MOSI: SPI Data pin ADC2: ADC input channel2 SEG31: signal output for LCD display P0.2: bi-directional I/O port Default function: P0.2 7 MISO/ADC3/SEG32/P0.3 I/O I O I/O MISO: SPI Data pin ADC3: ADC input channel3 SEG32: signal output for LCD display P0.3: bi-directional I/O port Default function: P0.3 8 ADC4/SEG33/P0.4 I O I/O ADC4: ADC input channel4 SEG33: signal output for LCD display P0.4: bi-directional I/O port Default function: P0.4 9 ADC5/SEG34/P0.5 I O I/O ADC5: ADC input channel5 SEG34: signal output for LCD display P0.5: bi-directional I/O port Default function: P0.5 10 ADC6/LED_C10/SEG35/P0.6 I O O I/O ADC6: ADC input channel6 LEC_C10: LED output signal SEC35: signal output for LCD display P0.6: bi-directional I/O port Default function: P0.6 11 ADC7/LED_C9/SEG36/P0.7 I O O I/O ADC7: ADC input channel7 LED_C9: LED output signal SEG36: signal output for LCD display P0.7: bi-directional I/O port Default function: P0.7 (to be continued)

(continue) Pin No. LQFP64 Pin Name Type Function description 12 ADC8/LED_C8/SEG37/P1.0 I O O I/O ADC8: ADC input channel8 LED_C8: LED output signal SEG37: signal output for LCD display P1.0: bi-directional I/O port Default function: P1.0 13 ADC9/LED_C7/SEG38/P1.1 I O O I/O ADC9: ADC input channel9 LED_C7: LED output signal SEG38: signal output for LCD display P1.1: bi-directional I/O port Default function: P1.1

14 ADC10/LED_C6/COM6/

SEG39/P1.2 I O O O I/O ADC10: ADC input channel10 SEG39: signal output for LCD display LED_C6: LED output signal COM6: signal output for LCD display P1.2: bi-directional I/O port Default function: P1.2

15 ADC11/LED_C5/COM5/

SEG40/P1.3 I O O O I/O ADC11: ADC input channel11 LED_C5: LED output signal SEG40: signal output for LCD display COM5: signal output for LCD display P1.3: bi-directional I/O port Default function: P1.3 16 VREF/LED_C4/COM4/P1.4 I O O I/O VREF: the external reference voltage pin for ADC/DAC LED_C4: LED output signal COM4: signal output for LCD display P1.4: bi-directional I/O port Default function: P1.4 17 CREF/LED_C3/COM3/P1.5 O O O I/O CREF: the external capacitor pin of ADC/DAC reference voltage LED_C3: LED output signal COM3: signal output for LCD display P1.5: bi-directional I/O port Default function: P1.5 18 DACO/LED_C2/COM2 /P1.6 O O O I/O DACO: DAC output pin LED_C2: LED output signal COM2: signal output for LCD display P1.6: bi-directional I/O port Default function: P1.6 19 LED_C1/COM1/P1.7 O O I/O LED_C1: LED output signal COM1: signal output for LCD display P1.7: bi-directional I/O port Default function: P1.7

20 GND P Ground

21 VDD P Power supply

22 VDDR O Regulator external capacitor pin

(to be continued)

(continue) Pin No. LQFP64 Pin Name Type Function description 23 OPN2/P2.0 I I/O OPN2: OP negative phase input pin P2.0: bi-directional I/O port Default function: P2.0 24 TCK/OPN1/P2.1 I I I/O TCK: programmer clock pin OPN1: OP negative phase input P2.1: bi-directional I/O port Default function: P2.1 25 TDI/OPN0/P2.2 I I I/O TDI: programmer data pin OPN0: OP negative phase input P2.2: bi-directional I/O port Default function: P2.2 26 TMS/OPO/P2.3 I O I/O TMS: programmer mode selection pin OPO: OP output P2.3: bi-directional I/O port、 Default function: P2.3 27 TDO/OPP0/P2.4 O I I/O TDO: programmer data input pin OPP0: OP positive phase input P2.4: bi-directional I/O port Default function: P2.4 28 OPP1/P2.5 I I/O OPP0: OP positive phase input P2.5: bi-directional I/O port Default function: P2.5 29 D-/P2.6 I/O I/O D-: USB Data pin P2.6: bi-directional I/O port Default function: P2.6 30 D+/P2.7 I/O I/O D+: USB Data pin P2.7: bi-directional I/O port Default function: P2.7 31 LED_S1/SEG1/P3.0 O O I/O LED_S1: LED output signal SEG1: signal output for LCD display P3.0: bi-directional I/O port Default function: P3.0 32 LED_S2/SEG2/P3.1 O O I/O LED_S2: LED output signal SEG2: signal output for LCD display P3.1: bi-directional I/O port Default function: P3.1 33 ECI1/LED_S3/SEG3/P3.2 I O O I/O ECI1: PCA1 external clock input pin LED_S3: LED output signal SEG3: signal output for LCD display P3.2: bi-directional I/O port Default function: P3.2 34 P1CEX0/LED_S4/SEG4/P3.3 I/O O O I/O P1CEX0: PCA1 module 0 capture/compare output pin LED_S4: LED output signal SEG4: signal output for LCD display P3.3: bi-directional I/O port Default function: P3.3 (to be continued)

(continue) Pin No. LQFP64 Pin Name Type Function description 35 P1CEX1/LED_S5/SEG5/P3.4 I/O O O I/O P1CEX1: PCA1 module 1 capture/compare output pin LED_S5: LED output signal SEG5: signal output for LCD display P3.4: bi-directional I/O port Default function: P3.4 36 P1CEX2/LED_S6/SEG6/P3.5 I/O O O I/O P1CEX2: PCA1 module 2 capture/compare output pin LED_S6: LED output signal SEG6: signal output for LCD display P3.5: bi-directional I/O port Default function: P3.5 37 ECI2/LED_S7/SEG7/P3.6 I O O I/O ECI2: the PCA2 external clock input pin LED_S7: LED output signal SEG7: signal output for LCD display P3.6: bi-directional I/O port Default function: P3.6 38 P2CEX0/LED_S8/SEG8/P3.7 I/O O O I/O P2CEX0: PCA2 module 0 capture/compare output pin LED_S8: LCD output signal SEG8: signal output for LCD display P3.7: bi-directional I/O port Default function: P3.7 39 P2CEX1/SEG9/P4.0 I/O O I/O P2CEX1: PCA2 module 1 capture/compare output pin SEG9: signal output for LCD display P4.0: bi-directional I/O port Default function: P4.0 40 ECI3/SEG10/P4.1 I O I/O ECI3: PCA3 clock input pin SEG10: signal output for LCD display P4.1: bi-directional I/O port Default function: P4.1 41 P3CEX0/SEG11/P4.2 I/O O I/O P3CEX0: PCA3 module 0 capture/compare output pin SEG11: signal output for LCD display P4.2: bi-directional I/O port Default function: P4.2 42 P3CEX1/SEG12/P4.3 I/O O I/O P3CEX1: PCA3 module 1 capture/compare the output pin SEG12: signal output for LCD display P4.2: bi-directional I/O port Default function: P4.3 43 T2EX/SEG13/P4.4 I O I/O T2EX: Timer2 external trigger pin SEG13: signal output for LCD display P4.4: bi-directional I/O port Default function: P4.4 44 T2/SEG14/P4.5 O O I/O T2: Timer2 waveform output SEG14: signal output for LCD display P4.5: bi-directional I/O port Default function: P4.5 (to be continued)

(continue) Pin No. LQFP64 Pin Name Type Function description 45 TXD1/SEG15/P4.6 O O I/O TXD1: UART1 sent pin SEG15: signal output for LCD display P4.6: bi-directional I/O port Default function: P4.6 46 RXD1/SEG16/P4.7 I O I/O RXD1: UART1 receive pin SEG16: signal output for LCD display P4.7: bi-directional I/O port Default function: P4.7 47 SEG17/INT40/P5.0 O I I/O SEG17: signal output for LCD display INT40: External interrupt40 P5.0: bi-directional I/O port Default function: P5.0 48 SEG18/INT41/P5.1 O I I/O SEG18: signal output for LCD display INT41: External interrupt41 P5.1: bi-directional I/O port Default function: P5.1 49 SEG19/INT42/P5.2 O I I/O SEG19: signal output for LCD display INT42: External interrupt42 P5.2: bi-directional I/O port Default function: P5.2 50 SEG20/INT43/P5.3 O I I/O SEG20: signal output for LCD display INT43: External interrupt43 P5.3: bi-directional I/O port Default function: P5.3 51 SEG21/INT44/P5.4 O I I/O SEG21: signal output for LCD display INT44: External interrupt44 P5.4: bi-directional I/O port Default function: P5.4 52 SEG22/INT45/P5.5 O I I/O SEG22: signal output for LCD display INT45: External interrupt45 P5.5: bi-directional I/O port Default function: P5.5 53 SEG23/INT46/P5.6 O I I/O SEG23: signal output for LCD display INT46: External interrupt46 P5.6: bi-directional I/O port Default function: P5.6 54 SEG24/INT47/P5.7 O I I/O SEG24: signal output for LCD display INT47: External interrupt47 P5.7: bi-directional I/O port Default function: P5.7 55 P0CEX1/SEG25/P6.0 I/O O I/O P0CEX1: PCA0 module1 capture/compare output pin SEG25: signal output for LCD display P6.0: bi-directional I/O port Default function: P6.0 (to be continued)

(continue) Pin No. LQFP64 Pin Name Type Function description 56 P0CEX0/ SEG26/INT2/P6.1 I/O O I I/O P0CEX0: PCA0 module0 capture/compare output pin SEG26: signal output for LCD display INT2: External interrupt2 input pin P6.1: bi-directional I/O port Default function: P6.1 57 ECI0/ SEG27/INT3/P6.2 I O I I/O ECI0: PCA0 clock input pin SEG27: signal output for LCD display INT3: External interrupt3 input pin P6.2: bi-directional I/O port Default function: P6.2 58 T3/SEG28/P6.3 O O I/O T3: Timer3 waveform output pin SEG28: signal output for LCD display P6.3: bi-directional I/O port Default function: P6.3 59 TXD/SEG29/P6.4 O O I/O TXD: UART0 data sent pin SEG29: signal output for LCD display P6.4: bi-directional I/O port Default function: P6.4 60 RXD/SEG30/P6.5 I O I/O RXD: UART0 data receive pin SEG30: signal output for LCD display P6.5: bi-directional I/O port Default function: P6.5 61 SCL/P6.6 I/O I/O SCL: TWI clock pin P6.6: bi-directional I/O port Default function: P6.6 62 SDA/P6.7 I/O I/O SDA: TWI Data pin P6.7: bi-directional I/O port Default function: P6.7 63 RESET/P7.0 I I/O RESET: system reset pin P7.0: bi-directional I/O port Default function: controlled by the code option 64 XTAL1/P7.1 I I/O XTAL1: external crystals input pin P7.1: bi-directional I/O port Default function: P7.1

1. Pin Description Pin No. Type Description I/O PORT P0.0 - P0.7 I/O 8-bit bi-directional I/O port P1.0 - P1.7 I/O 8-bit bi-directional I/O port P2.0 - P2.7 I/O 8-bit bi-directional I/O port P3.0 - P3.7 I/O 8-bit bi-directional I/O port P4.0 - P4.7 I/O 8-bit bi-directional I/O port P5.0 - P5.7 I/O 8-bit bi-directional I/O port P6.0 - P6.7 I/O 8-bit bi-directional I/O port P7.0 - P7.4 I/O 6-bit bi-directional I/O port Timer/Counter T2 I/O Timer2 T3 I Timer3 T2EX I The external input pin for timer 2 PCA Controller P0CEX0 I/O Input /output pin for PCA0 module 0 P0CEX1 I/O Input /output pin for PCA0 module 1 P1CEX0 I/O Input /output pin for PCA1 module 0 P1CEX1 I/O Input /output pin for PCA1module 1 P1CEX2 I/O Input /output pin for PCA1 module 2 P2CEX0 I/O Input /output pin for PCA2 module 0 P2CEX1 I/O Input /output pin for PCA2 module 1 P3CEX0 I/O Input /output pin for PCA3 module 0 P3CEX1 I/O Input /output pin for PCA3 module1 ECI0 I The external clock input for PCA0 ECI1 I The external clock input for PCA1 ECI2 I The external clock input for PCA2 ECI3 I The external clock input for PCA3 EUART RXD I EUART0 data input TXD O EUART0 data output RXD1 I EUART1 data input TXD1 O EUART1 data output ADC CREF O ADC/DAC bulit-in 1.5v/2.5v reference voltage external capacitance pin VREF O ADC/DAC external analog reference voltage pin ADC0- ADC11 I No.12 ADC input pin DAC DACO O DAC conversion output pin (to be continued)

(continue) TWI SCL I/O TW CLK pin SDA I/O TWI data input/output pin LCD/LED COM1 - COM6 O Common signal output for LCDdisplay LED_C1 - LED_C10 O Common signal output for LCDdisplay LED_S1 - LED_S8 O LED Segment signal output SEG1 - SEG40 O LCD Segment signal output USB D+ I/O USB data input/output D- I/O USB data input/output pin SPI MOSI I/O SPI master output slave input MISO I/O SPI master input slave output SCK I/O SPI serial clock SS I SPI slave select OP OPP0 I OP positive input pin OPP1 I OP positive input pin OPN0 I OP negative input pin OPN1 I OP negative input pin OPN2 I OP negative input pin OPO O OP output pin Interrupt & Reset & Clock & Power INT2、INT3 I External interrupt 2,3 input source INT40 - INT47 I External interrupt 40-47 input source RESET I The device will be reset by A low voltage on this pin longer than 10us, an internal resistor about 30kΩ to VDD, So using only an external capacitor to GND can cause a PIN reset. XTAL1 I 32.768kHz/high-frequency external oscillator input XTAL2 O 32.768kHz/high-frequency external oscillator output XTALX1 I high frequency external oscillatorX input XTALX2 O high frequency external oscillator X output GND P Ground VDD P Power source(2.0 - 5.5V) VDDR P Power regulator output (3.3V),connect 1μF capacitor to GND Programmer TDO O Debug interface: Test data out TMS I Debug interface: Test mode select TDI I Debug interface: Test data in TCK I Debug interface: Test clock in

1. Product Information SH88F6161/SH88F6162: LQFP64, TQFP48 Part Num RAM (byte) Flash (byte) (byte) EUARTx LED OP ADC (12bit) DAC (12bit) PCAx (16bit) Timerx ExINT USB RC IO SPI LCD Package SH88F6161 2816 64K 2048 0,1 10*8 1 12 1 0,1,2,3 2,3 2+8 No ±1% 61 1

4 X 40

5 X 39

6 X 38

SH88F6161 2816 64K 2048 0 10*8 1 8 1 0,1,2,3 3 2+8 No ±1% 45 No

4 X 30

5 X 29

6 X 28

SH88F6162 2816 64K 2048 0,1 10*8 1 12 1 0,1,2,3 2,3 2+8 2.0 ±1% 61 1 SH88F6162 2816 64K 2048 0 10*8 1 8 1 0,1,2,3 3 2+8 2.0 ±1% 45 No

1. SFR Mapping The SFR of the SH88F6161/SH88F6162 fall into the following categories: CPU Core Registers: ACC, B, PSW, SP, DPL, DPH Enhanced CPU Core Registers: AUXC, DPL1, DPH1, INSCON, XPAGE Power and Clock Control Registers: PCON, SUSLO, LPDCON Flash Registers: IB_OFFSET, IB_DATA, IB_CON1, IB_CON2,IB_CON3, IB_CON4, IB_CON5, FLASHCON Data Memory Register: XPAGE Hardware Watchdog Timer Registers: RSTSTAT System Clock Control Registers: CLKCON, CLKLO, CLKRC0, CLKRC1 PLL Registers: PLLCON Interrupt System Registers: IEN0, IEN1, IENC, IPH0, IPL0, IPH1, IPL1, EXF0, EXF1, EXCON I/O Port Registers: P0, P1, P2, P3, P4, P5, P6, P7, P0CR, P1CR, P2CR, P3CR, P4CR, P5CR, P6CR, P7CR, P0PCR, P1PCR, P2PCR, P3PCR, P4PCR, P5PCR, P6PCR, P7PCR, P6OS Timer Registers: T2CON, T2MOD, TH2, TL2, RCAP2L, RCAP2H, T3CON, TL3, TH3 PCARegisters: PCACON, P0TOPL, P0TOPH, P0CMD,P0CF, P0CPM0, P0CPM1, P0CPL0, P0CPH0, P0CPL1, P0CPH1, P1TOPL, P1TOPH, P1CMD, P1CF, P1CPM0, P1CPM1, P1CPM2, P1CPL0, P1CPH0, P1CPL1, P1CPH1, P1CPL2, P1CPH2, P2TOPL, P2TOPH, P2CMD, P2CF, P2CPM0, P2CPM1, P2CPL0, P2CPH0, P2CPL1, P2CPH1, P3TOPL, P3TOPH, P3CMD, P3CF, P3CPM0, P3CPM1, P3CPL0, P3CPH0, P3CPL1, P3CPH1, P0FORCE, P1FORCE, P2FORCE, P3FORCE LCD Registers: DISPCON, DISPCON1, P1SS, P2SS, P3SS, P4SS, P5SS, P6SS, P7SS EUART Registers: SCON, SBUF, SADEN, SADDR, PCON, SBRTL, SBRTH, SFINE, SCON1, SBUF1, SADEN1, SADDR1, PCON1, SBRTL1, SBRTH1, SFINE1 Regulator Register: REGCON OP Register: OPCON,OPIOS ADC Register: ADCON1, ADCON2, ADT, SCHCON1, SCHCON2, SCHCON3, ADCL, ADCH, ADCGTL, ADCGTH, ADCLTL, ADCLTH SPI Register: SPCON, SPSTA, SPDAT DAC Register: DACCON0, DACCON1, DACCAL, DACH, DACL USB Register: USBCON, USBIF1, USBIF2, USBIE1, USBIE2, USBADDR, EP0CON, EP1CON, EP2CON, IEP0CNT, IEP1CNT, IEP2CNT, OEP0CNT, OEP1CNT, OEP2CNT TWI Register: TWICON, TWISTA, TWTOUT, TWIBR, TWIADR, TWIDAT, TWIAMR, TWTFREE

Table 7.1 C51 Core SFRs Mnem Add Name POR/WDT/LVR/ PIN Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PSW D0H Program Status Word 00000000 CY AC F0 RS1 RS0 OV F1 P INSCON 86H Data pointer select -0--00-0 - BKS0 - - DIV MUL - DPS Table 7.2 Power and Clock control SFRs Mnem Add Name POR/WDT/LVR/ PIN Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PCON 87H Power Control 00--0000 SMOD SSTAT - - GF1 GF0 PD IDL LPDCON B3H Low voltage testing 0u000000 LPDEN - LPDMD LPDIF LPDS3 LPDS2 LPDS1 LPDS0 Table 7.3 Flash control SFRs Mnem Add Name POR/WDT/LVR/ PIN Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 IB_OFF SET FBH Offset Register for Programming 00000000 IB_OFF SET.7 IB_OFF SET.6 IB_OFF SET.5 IB_OFF SET.4 IB_OFF SET.3 IB_OFF SET.2 IB_OFF SET.1 IB_OFF SET.0 IB_CON2 F3H Flash Memory Control Register 2 ----0000 - - - - IB_CON2.3 IB_CON2.2 IB_CON2.1 IB_CON2.0 IB_CON3 F4H Flash Memory Control Register 3 ----0000 - - - - IB_CON3.3 IB_CON3.2 IB_CON3.1 IB_CON3.0 IB_CON4 F5H Flash Memory Control Register 4 ----0000 - - - - IB_CON4.3 IB_CON4.2 IB_CON4.1 IB_CON4.0 IB_CON5 F6H Flash Memory Control Register 5 ----0000 - - - - IB_CON5.3 IB_CON5.2 IB_CON5.1 IB_CON5.0

Table 7.4 WDT SFR Mnem Add Name POR/WDT/LVR/ PIN Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 RSTSTAT B1H Watchdog Timer Control *-***000 WDOF - PORF LVRF CLRF WDT.2 WDT.1 WDT.0 Note: * : RSTSTAT initial value is determined by different RESET. Table 7.5 CLKCON SFRs Mnem Add Name POR/WDT/LVR/ PIN Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 CLKCON B2H System Clock Control Register 111000-- 32k_SPDUP CLKS1 CLKS0 SCMIF OSC2ON FS - - CLKLO BDH Internal RC adjust Contro Register 0---0000 CLKRCEN - - - CLKLO.3 CLKLO.2 CLKLO.1 CLKLO.0 Table 7.6 Interrupt SFRs Mnem Add Name POR/WDT/LVR/ PIN Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 IEN0 A8H Interrupt Enable Control 0 00000000 EA EADC ET2 ES0 EPCA3 EPCA2 EPCA1 EPCA0 IEN1 A9H Interrupt Enable Control 1 00000000 ESCM/ELPD ES1 EUSB/ETWI ET3 EX4 EX3 EX2/EDAC ESPI IPH0 B4H Interrupt Priority Control High 0 -0000000 - PADCH PT2H PS0H PPCA3H PPCA2H PPCA1H PPCA0H IPL0 B8H Interrupt Priority Control Low 0 -0000000 - PADCL PT2L PS0L PPCA3L PPCA2L PPCA1L PPCA0L IPH1 B5H Interrupt Priority Control High 1 00000000 PSCM/LPDH PS1H PUSB/TWIH PT3H PX4H PX3H PX2DACH PSPIH IPL1 B9H Interrupt Priority Control Low 1 00000000 PSCM/LPDL PS1L PUSB/TWIL PT3L PX4L PX3L PX2DACL PSPIL EXF1 E8H External interrupt Control 1 00000000 IF47 IF46 IF45 IF44 IF43 IF42 IF41 IF40 IENC C3H Interrupt 4channel enable control 00000000 EXS47 EXS46 EXS45 EXS44 EXS43 EXS42 EXS41 EXS40

Table 7.7 Port SFRs Mnem Add Name POR/WDT/LVR/ PIN Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Table 7.8 Timer SFRs Mnem Add Name POR/WDT/LVR/ PIN Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 T2CON C8H Timer/Counter20 Control 00--0000 TF2 EXF2 - - EXEN2 TR2 C/ T2 ——— CP/RL2 ———— T2MOD C9H Timer/Counter2 Mode 0-----00 TCLKP2 - - - - - T2OE DCEN RCAP2L CAH Timer/Counter20 Reload RCAP2H CBH Timer/Counter20 Reload T3CON BBH Timer/Counter3 Control 0-00-000 TF3 - T3PS.1 T3PS.0 - TR3 T3CLKS.1 T3CLKS.0 Table 7.9 PCA SFRs Mnem Add Name POR/WDT/LVR/PI N Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 P0CF 98H PCA0 Flag register 0-----00 CF0 - - - - - P0CCF1 P0CCF0 P0CMD 99H PCA0 Mode register 00---000 ECF0 P0SDEN - - - P0CPS2 P0CPS1 P0CPS0 P0CPM0 9AH PCA0 Capture/Compare Module 0 register 00000000 P0SMP0 P0SMN0 P0FSP0 P0FSN0 P0ECOM0 P0TCP0 P0MAT0 P0ECCF0 P0CPM1 9BH PCA0 Capture/Compare Module 1 register 00000000 P0SMP1 P0SMN1 P0FSP1 P0FSN1 P0ECOM1 P0TCP1 P0MAT1 P0ECCF1 P1CF C8H PCA1 flag register 0-----000 CF1 - - - - P1CCF2 P1CCF1 P1CCF0 P1CMD C9H PCA1 mode register 00---000 ECF1 P1SDEN - - P1CPS2 P1CPS1 P1CPS0 P1CPM0 CAH PCA1 Capture/Compare Module 0 register 00000000 P1SMP0 P1SMN0 P1FSP0 P1FSN0 P1ECOM0 P1TCP0 P1MAT0 P1ECCF0 P1CPM1 CBH PCA1 Capture/Compare Module 1 register 00000000 P1SMP1 P1SMN1 P1FSP1 P1FSN1 P1ECOM1 P1TCP1 P1MAT1 P1ECCF1 P1CPM2 D1H PCA1 Capture/Compare Module 2 register 00000000 P1SMP2 P1SMN2 P1FSP2 P1FSN2 P1ECOM2 P1TCP2 P1MAT2 P1ECCF2 (to be continued)

(continue) P2CF E8H PCA2 flag register 0-----00 CF2 - - - - - P2CCF1 P2CCF0 P2CMD E9H PCA2 mode register 00---000 ECF2 P2SDEN - - - P2CPS2 P2CPS1 P2CPS0 P2CPM0 EAH PCA2 Capture/Compare Module 0 register 00000000 P2SMP0 P2SMN0 P2FSP0 P2FN0 P2ECOM0 P2TCP0 P2MAT0 P2ECCF0 P2CPM1 EBH PCA2 Capture/Compare Module 1 register 00000000 P2SMP1 P2SMN1 P2FSP1 P2FSN1 P2ECOM1 P2TCP1 P2MAT1 P2ECCF1 P3CF F8H PCA3 fiag register 0-----00 CF3 - - - - - P3CCF1 P3CCF0 P3CMD F9H PCA3 mode register 00---000 ECF3 P3SDEN - - - P3CPS2 P3CPS1 P3CPS0 P3CPM0 FAH PCA3 Capture/Compare Module 0 register 00000000 P3SMP0 P3SMN0 P3FSP0 P3FSN0 P3ECOM0 P3TCP0 P3MAT0 P3ECCF0 P3CPM1 F2H PCA3 Capture/Compare Module 1 register 00000000 P3SMP1 P3SMN1 P3FSP1 P3FSN1 P3ECOM1 P3TCP1 P3MAT1 P3ECCF1 PCACON D8H PCA enable register ----0000 - - - - PR3 PR2 PR1 PR0 P0FORCE DCH PCA0 forced output control register --00--00 - - P0OSC1 P0OSC0 - - P0FCO1 P0FCO0 P1FORCE DDH PCA1 forced output control register -000-000 - P1OSC2 P1OSC1 P1OSC0 - P1FCO2 P1FCO1 P1FCO0 P2FORCE DEH PCA2 forced output control register --00--00 - - P2OSC1 P2OSC0 - - P2FCO1 P2FCO0 P3FORCE DFH PCA3 forced output control register --00--00 - - P3OSC1 P3OSC0 - - P3FCO1 P3FCO0

Table 7.10 Regulator SFR Mnem Add Name POR/WDT/LVR/ PIN Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Table 7.11 USB SFRs Mnem Add Name POR/WDT/LVR/ PIN Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 USBCON B1H USB Control 00000000 ENUSB SW1CON SWRST DPSTA DMSTA SW2CON WKUP GOSUSP USBIF1 B0H USB Interrupt Vector1 00000000 PUPIF OVERIF OW SETUPIF SOFIF RESMIF SUSPIF USBRSTIF USBIF2 88H USB Interrupt Vector2 -000-000 - OEP2IF OEP1IF OEP0IF - IEP2IF IEP1IF IEP0IF USBIE1 B2H USB Interrupt Enable1 00-00000 PUPIE OVERIE - SETUPIE SOFIE RESMIE SUSPIE PBRSTIE USBIE2 B3H USB Interrupt Enable2 -000-000 - OEP2IE OEP1IE OEP0IE - IEP2IE IEP1IE IEP0IE USBADDR BEH USB Device Address -0000000 - USBADDR6 USBADDR5 USBADDR4 USBADDR3 USBADDR2 USBADDR1 USBADDR0 EP0CON BH Endpoint0 Control 00--0000 IEP0DTG OEP0DTG - - IEP0STL IEP0RDY OEP0STL OEP0RDY EP1CON AAH Endpoint1 Control 00000000 IEP1DTG OEP1DTG - - IEP1STL IEP1RDY OEP1STL OEP1RDY EP2CON ABH Endpoint2 Control 00000000 IEP2DTG OEP2DTG - - IEP2STL IEP2RDY OEP2STL OEP2RDY IEP0CNT ACH USB Endpoint0 input data buffer ----0000 - - - - IEP0CNT3 IEP0CNT2 IEP0CNT1 IEP0CNT0 IEP1CNT ADH USB Endpoint1 input data buffer ---00000 - - - IEP1CNT4 IEP1CNT3 IEP1CNT2 IEP1CNT1 IEP1CNT0 IEP2CNT AEH USB Endpoint2 input data buffer -0000000 - IEP2CNT6 IEP2CNT5 IEP2CNT4 IEP2CNT3 IEP2CNT2 IEP2CNT1 IEP2CNT0 OEP0CNT AFH USB Endpoint0 output data buffer ----0000 - - - - OEP0CNT3 OEP0CNT2 OEP0CNT1 OEP0CNT0 OEP1CNT B6H USB Endpoint1 output data buffer ---00000 - - - OEP1CNT4 OEP1CNT3 OEP1CNT2 OEP1CNT1 OEP1CNT0 OEP2CNT B7H USB Endpoint2 output data buffer -0000000 - OEP2CNT6 OEP2CNT5 OEP2CNT4 OEP2CNT3 OEP2CNT2 OEP2CNT1 OEP2CNT0 Table 7.12 SPI SFRs Mnem Add Name POR/WDT/LVR/ PIN Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SPCON F9H SPI Control 00000000 DIR MSTR CPHA CPOL SSDIS SPR2 SPR1 SPR0 SPSTA F8H SPI Status 00000--- SPEN SPIF MODF WCOL RXOV - - -

Table 7.13 OP SFRs Mnem Add Name POR/WDT/LVR/ PIN Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 OPCON A1H OP Control 0---0000 OPEN - - - OPPSEL.1 OPPSEL.0 OPNSEL.1 OPNSEL.0 OPIOS A2H OP port configuration register ---00000 - - - OPN2IO OPN1IO OPN0IO OPP1IO OPP0IO Table 7.14 LCD SFRs Mnem Add Name POR/WDT/LVR/ PIN Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 DISPCON C4H LCD Control register 00000000 DISPSEL DISPON DUTY1 DUTY0 VOL3 VOL2 VOL1 VOL0 DISPCON1 C5H LCD Control register1 ---00000 - - - RLCD FCCTL1 FCCTL0 MOD1 MOD0 P1SS C6H LCD port selection register1 00000000 P1S7 P1S6 P1S5 P1S4 P1S3 P1S2 P1S1 P1S0 P2SS C7H LCD port selection register2 00000000 P2S7 P2S6 P2S5 P2S4 P2S3 P2S2 P2S1 P2S0 P3SS CEH LCD port selection register3 00000000 P3S7 P3S6 P3S5 P3S4 P3S3 P3S2 P3S1 P3S0 P4SS CFH LCD port selection register4 00000000 P4S7 P4S6 P4S5 P4S4 P4S3 P4S2 P4S1 P4S0 P5SS DFH LCD port selection register5 00000000 P5S7 P5S6 P5S5 P5S4 P5S3 P5S2 P5S1 P5S0 P6SS E7H LCD port selection register6 00000000 P6S7 P6S6 P6S5 P6S4 P6S3 P6S2 P6S1 P6S0 Table 7.15 TWI SFRs Mnem Add Name POR/WDT/LVR/ PIN Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TWICON C0H TWI Control register 00000000 TOUT ENTWI STA STO TWINT AA TFREE EFREE TWTFREE C6H Timeout For Bus High level TWITOUT C7H Timeout For Bus Low level

Table 7.16 EUART SFRs Mnem Add Name POR/WDT/LVR/ PIN Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SCON 98H Serial Control 00000000 SM0/FE SM1/RXOV SM2/TXCOL REN TB8 RB8 TI RI PCON 87H Power & serial Control 00--0000 SMOD SSTAT - - GF1 GF0 PD IDL SFINE 9EH Baudrate Generator ----0000 - - - - SFINE.3 SFINE.2 SFINE.1 SFINE.0 SCON1 D8H Serial Control 00000000 SM10/FE1 SM11/RXOV1 SM12/TXCOL1 REN1 TB81 RB81 TI1 RI1 SFINE1 DEH Baudrate Generator ----0000 - - - - SFINE1.3 SFINE1.2 SFINE1.1 SFINE1.0 Table 7.17 DAC SFRs Mnem Add Name POR/WDT/LVR/ PIN Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 DACCON0 8BH DAC Control 0 00000000 DACEN DACOSEL.1 DACOSEL.0 DACLSEL.1 DACLSEL.0 DACDF DACIO DACIF DACCON1 9FH DAC Control 1 00-00000 DACCALON OFFSETSW - VREFS REFSEL REFON DACSREF.1 DACSREF.0 DACCAL A4H DAC self –calibration control register 0-000000 OFFSET SIGN - OFFSET DATA.5 OFFSET DATA.4 OFFSET DATA.3 OFFSET DATA.2 OFFSET DATA.1 OFFSET DATA.0 DACH 8DH DAC Data High Byte ----0000 - - - - DAC.11 DAC.10 DAC.9 DAC.8

Table 7.18 ADC SFRs Mnem Add Name POR/WDT/LVR/ PIN Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ADCON1 91H ADC Control1 00000000 ADON ADCIF EC TRE TRS2 TRS1 TRS0 GO/D ----- O ---- N ---- E ---- ADCON2 8DH ADC Control2 0—0000- ADCIE - - ACLIE ACGIE ACLIF ACGIF - ADT 89H ADC Time Configuration -0000000 - TADC2 TADC1 TADC0 TS3 TS2 TS1 TS0 SCHCON1 8AH ADC Channel1 000-0000 VREF1 VREF0 ALR - SCH3 SCH2 SCH1 SCH0 SCHCON2 8BH ADC Channel2 00000000 ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 SCHCON3 8CH ADC Channel3 ----0000 - - - - ADC11 ADC10 ADC9 ADC8 ADCL 92H low byte of the ADC results 00000000 A7 A6 A5 A4 A3 A2 A1 A0 ADCH 93H high byte of the ADC results 00000000 A15 A14 A13 A12 A11 A10 A9 A8 ADCGTL 94H ADC Greater Compare register (low byte) 00000000 GT7 GT6 GT5 GT4 GT3 GT2 GT1 GT0 ADCGTH 95H ADC Greater Compare register (high byte) ----0000 - - - - GT11 GT10 GT9 GT8 ADCLTL 96H ADC less Compare register (low byte) 00000000 LT7 LT6 LT5 LT4 LT3 LT2 LT1 LT0 ADCLTH 97H ADC less Compare register (high byte) ----0000 - - - - LT11 LT10 LT9 LT8 Note: - reserved bits.

addressable Non Bit addressable F8H SPSTA SPCON SPDAT IB_OFFSET IB_DATA - - (Reserved) FFH F0H B AUXC IB_CON1 IB_CON2 IB_CON3 IB_CON4 IB_CON5 XPAGE F7H E8H EXF1 P0PCR P1PCR P2PCR P3PCR P4PCR - P7SS EFH E0H ACC P0CR P1CR P2CR P3CR P4CR - P6SS E7H D8H SCON1 SBUF1 SADDR1 SADEN1 SBRTL1 SBRTH1 SFINE1 P5SS DFH D0H PSW PCON1 - - - - - - D7H C8H T2CON T2MOD RCAP2L RCAP2H TL2 TH2 P3SS P4SS CFH C0H P4 - EXCON IENC DISPCON DISPCON1 P1SS P2SS C7H B8H IPL0 IPL1 - T3CON PLLCON CLKLO CLKRC0 CLKRC1 BFH B0H P3 RSTSTAT CLKCON LPDCON IPH0 IPH1 - - B7H A8H IEN0 IEN1 - - - - - - AFH A0H P2 OPCON OPIOS - DACCAL ISPLO ISPCON FLASHCON A7H 98H SCON SBUF SADDR SADEN SBRTL SBRTH SFINE DACCON1 9FH 88H EXF0 TL3 TH3 DACCON0 DACL DACH SUSLO REGCON 8FH 80H P0 SP DPL DPH DPL1 DPH1 INSCON PCON 87H Bank1 Bit addressable Non Bit addressable F8H P3CF P3CMD P3CPM0 - - P3TOPL P3TOPH (Reserved for) Testing FFH F0H B AUXC P3CPM1 P3CPL0 P3CPH0 P3CPL1 P3CPH1 XPAGE F7H E8H P2CF P2CMD P2CPM0 P2CPM1 - - P2TOPL P2TOPH EFH E0H ACC P5PCR P6PCR P7PCR P2CPL0 P2CPH0 P2CPL1 P2CPH1 E7H D8H PCACON P5CR P6CR P7CR - - - - DFH D0H PSW P1CPM2 P1CPL0 P1CPH0 P1CPL1 P1CPH1 P1CPL2 P1CPH2 D7H C8H P1CF P1CMD P1CPM0 P1CPM1 - - P1TOPL P1TOPH CFH C0H TWICON TWISTA TWIBR TWIADR TWIDAT TWIAMR TWTOUT TWTFREE C7H B8H IPL0 IPL1 - - - - USBADDR EP0CON BFH B0H USBIF1 USBCON USBIE1 USBIE2 IPH0 IPH1 OEP1CNT OEP2CNT B7H A8H IEN0 IEN1 EP1CON EP2CON IEP0CNT IEP1CNT IEP2CNT OEP0CNT AFH A0H P7 P6OS - - P0CPL0 P0CPH0 P0CPL1 P0CPH1 A7H 98H P0CF P0CMD P0CPM0 P0CPM1 - - P0TOPL P0TOPH 9FH 90H P6 ADCON1 ADCL ADCH ADCGTL ADCGTH ADCLTL ADCLTH 97H 88H USBIF2 ADT SCHCON1 SCHCON2 SCHCON3 ADCON2 SUSLO - 8FH 80H P5 SP DPL DPH DPL1 DPH1 INSCON PCON 87H Note: (1) The unused addresses of SFR are not available. (2) The BKS1 and BKS0 bits in INSCON register is used to choose the bank0 or bank1. For more detail description please refers to the table 8.2 Data Pointer Select Register.

1. Normal Function

8.1 CPU

8.1.1 CPU Feature

 CPU core registers: ACC, B, PSW, SP, DPL, DPH Accumulator ACC is the Accumulator register. The mnemonics for accumulator-specific instructions, however, refer to the Accumulator simply as A. B Register The B register is used during multiply and divide operations. For other instructions it can be treated as another scratch pad register. Stack Pointer (SP) The Stack Pointer Register is 8 bits wide, It is incremented before data is stored during PUSH, CALL executions and it is decremented after data is out of stack during POP, RET, RETI executions. The stack may reside anywhere in on-chip internal RAM (00H-FFH). On reset, the Stack Pointer is initialized to 07H causing the stack to begin at location 08H. Program Status Word Register (PSW) The PSW register contains program status information. Table 8.1 PSW Register D0H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PSW CY AC F0 RS1 RS0 OV F1 P R/W R/W R/W R/W R/W R/W R/W R/W R Reset Value (POR/WDT/LVR/PIN) 0 0 0 0 0 0 0 0 Bit Number Bit Mnemonic Description 7 CY Carry flag bit 0: no carry or borrow in an arithmetic or logic operation 1: a carry or borrow in an arithmetic or logic operation 6 AC Auxiliary Carry flag bit 0: an auxiliary carry or borrow in an arithmetic or logic operation 1: an auxiliary carry or borrow in an arithmetic or logic operation

5 F0 F0 flag bit

Available to the user for general purposes 4-3 RS[1:0] R0-R7 Register bank select bits 00: Bank0 (Address to 00H-07H) 01: Bank1 (Address to 08H-0FH) 10: Bank2 (Address to 10H-17H) 11: Bank3 (Address to 18H-1FH) 2 OV Overflow flag bit 0: no overflow happen 1: an overflow happen

1 F1 F1 flag bit

Available to the user for general purposes 0 P Parity flag bit 0: an even number of “one” bits in the Accumulator 1: an odd number of “one” bits in the Accumulator

8.1.2 Enhanced CPU core SFRs

 Extended 'MUL' and 'DIV' instructions: 16bits X 8bits, 16bits/8bits  Dual Data Pointer  Enhanced CPU core registers: AUXC, DPL1, DPH1, INSCON The SH88F6161/SH88F6162 has modified 'MUL' and 'DIV' instructions. These instructions support 16 bits operand. A new register - the register is applied to hold the upper part of the operand/result. The AUXC register is used during 16 bits operand multiply and divide operations. For other instructions it can be treated as another scratch pad register. After reset, the CPU is in standard mode, which means that the 'MUL' and 'DIV' instructions are operating like the standard 8051 instructions. To enable the 16 bits mode operation, the corresponding enable bit in the INSCON register must be set. Operation Result A B AUXC MUL INSCON.2 = 0; 8 bit mode (A)*(B) Low Byte High Byte --- INSCON.2 = 1; 16 bit mode (AUXC A)*(B) Low Byte Middle Byte High Byte DIV INSCON.3 = 0; 8 bit mode (A)/(B) Quotient Low Byte Remainder --- INSCON.3 = 1; 16 bit mode (AUXC A)/(B) Quotient Low Byte Remainder Quotient High Byte Dual Data Pointer Using two data pointers can accelerate data memory moves. The standard data pointer is called DPTR and the new data pointer is called DPTR1. DPTR1 is the same with DPTR, which consists of a high byte (DPH1) and a low byte (DPL1). Its intended function is to hold a 16-bit address, but it may be manipulated as a 16-bit register or as two independent 8-bit registers. The DPS bit in INSCON register is used to choose the active pointer. The user can switch data pointers by toggling the DPS bit. And all DPTR-related instructions will use the currently selected data pointer.

8.1.3 Registers

Table 8.2 Data Pointer Select Register 86H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 INSCON BKS1 BKS0 - - DIV MUL - DPS R/W R/W R/W - - R/W R/W - R/W Reset Value (POR/WDT/LVR/PIN) 0 0 - - 0 0 - 0 Bit Number Bit Mnemonic Description 7-6 BKS[1:0] SFR Bank Selection Bit 00: SFR Bank0 selected 01: SFR Bank1 selected 1x: reserved

3 DIV

16-bit/8-bit Divide Selection Bit 0: 8-bit Divide 1: 16-bit Divide

2 MUL

16-bit/8-bit Multiply Selection Bit 0: 8-bit Multiply 1: 16-bit Multiply

0 DPS

Data Pointer Selection Bit 0: Data pointer 1: Data pointer1

8.2 RAM

8.2.1 Feature

SH88F6161/SH88F6162 provides both internal RAM 256bytes and external RAM 256bytes for random data storage. The internal data memory is mapped into four separated segments:  The Lower 128 bytes of RAM (addresses 00H to 7FH) are directly and indirectly addressable.  The Upper 128 bytes of RAM (addresses 80H to FFH) are indirectly addressable only.  The Special Function Registers (SFR, addresses 80H to FFH) are directly addressable only.  The external 2816 bytes of RAM(addresses 00H to AFFH) are indirectly accessed by MOVX instructions.  The external 40 bytes of RAM(addresses B00H to B27H) are indirectly accessed by MOVX instructions.  The external 256 bytes of RAM(addresses B28H to C27H) are indirectly accessed by MOVX instructions. The Upper 128 bytes occupy the same address space as SFR, but they are physically separate from SFR space. When an instruction accesses an internal location above address 7FH, the CPU can distinguish whether to access the upper 128 bytes data RAM or to access SFR by different addressing mode of the instruction. Note: the unused address is unavailable in SFR. 0B00H Upper 128 bytes Internal Ram indirect accesses Lower 128 bytes Internal Ram direct or indirect accesses Extenal RAM 0AFFH Special Function Register direct accesses LCD RAM 0B27H 00H 0B28H USB RAM 0C27H 0000H 7FH 80H FFH FFH 80H The SH88F6161/SH88F6162 provides traditional method for accessing of external RAM. Use MOVXA, @Ri or MOVX @Ri, A; to access external low 256 bytes RAM; MOVX A, @DPTR or MOVX @DPTR, A also to access external 3112 bytes RAM. In SH88F6161/SH88F6162 the user can also use XPAGE register to access external RAM only with MOVX A, @Ri or MOVX @Ri, A instructions. The user can use XPAGE to represent the high byte address of RAM above 256 Bytes. In Flash SSP mode, the XPAGE can also be used as sector selector (Refer to SSP Function).

8.2.2 Register

Table 8.3 Data Memory Page Register F7H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) 0 0 0 0 0 0 0 0 Bit Number Bit Mnemonic Description 7-4 XPAGE[7:4] RAM Page Selector no significance 3-0 XPAGE[3:0] RAM Page Selecto

8.3 Flash Program Memory

8.3.1 Feature

 The program memory consists 64 X 1KB sectors, total 64KB  Programming and erasing can be done over the full operation voltage range  Write, read and erase operation are all supported by In-Circuit Programming (ICP)  Fast mass/sector erase and programming  Minimum program/erase cycles: Main program memory: 10,000 EEPROM like memory: 100,000  Minimum years data retention: 10  Low power consumption EEPROM Like Data Block (2K bytes) 0000H0000H Information Block 07FFH FFFFH Program Rom (64K) Program Memory Block BootRom Block BootRom Block FC00H The SH88F6161/SH88F6162 embeds 64K flash program memory for program code. The flash program memory provides electrical erasure and programming and supports In-Circuit Programming (ICP) mode and Self -Sector Programming (SSP) mode. The SH88F6161/SH88F6162 also embeds 2048 bytes EEPROM-like for program data with 256bytes per sector.and total 8 sectors. SH88F6161/SH88F6162 has a boot sector with 1024 bytes, for in system programming. Flash operation definition: In-Circuit Programming (ICP) mode: Erase, read and write to flash memory by the Flash Programmer Self-Sector Programming (SSP) mode: Erase, read and write to flash memory by the user code in program memory. In system progromming(ISP)mode: the user code running in the BootRom, can erase,write and read flash memory. At present, the BootRom program has been rooted by factory, which can cooperate with the corresponding PC software to download the program through the UART port. Flash memory supports the following operations: (1) Code-Protect Control mode Programming SH88F6161/SH88F6162 implements code-protect function to offer high safeguard for customer code. Two modes are available for each sector. Code-protect control mode 0: Used to enable/disable the write/read operation (except mass erase) from any programmer. Code-protect control mode 1: Used to enable/disable the read operation through MOVC instruction from other sectors; or the sector erase/write operation through SSP Function. The user must use the following two ways to complete code protection control mode Settings: 1. Flash programmer in ICP mode is set to corresponding protection bit to enter the protected mode. 2. The SSP mode does not support code protection control mode programming. (2) Mass Erase The mass erase operation will erase all the contents of program code, code option, code protect bit and customer code ID , regardless the status of code-protect control mode. (The Flash Programmer supplies customer code ID setting function for customer to distinguish their product.) Mass erase is only available in Flash Programmer.

(3) Sector Erase The sector erase operation will erase the contents of program code of selected sector . This operation can be done by Flash Programmer or the user’s program. If done by the Flash Programmer, the code-protect control mode 0 of the selected sector must be disabled. (4) EEPROM-Like Erase The EEPROM-Like erase operation will erase the contents of program code of EEPROM-Like. This operation can be done by Flash Programmer or the user’s program. (5) Write/Read Code The Write/Read Code operation will write the customer code into the Flash Programming Memory or read the customer code from the Flash Programming Memory. This operation can be done by Flash Programmer or the user’s program. If done by the user’s program, the code-protect control mode 1 of the selected sector must be disabled. But the program can read/write its own sector regardless of its security bit. If done by the Flash Programmer, the code-protect control mode 0 of the selected sector must be disabled. (6) Write/Read EEPROM-Like The Write/Read EEPROM-Like operation will write the customer data into the EEPROM-Like or read the customer data from the EEPROM-Like. This operation can be done by Flash Programmer or the user’s program. Flash Memory operation Operation ICP SSP Code Protection Yes No Sector Erase Yes (without security bit) Yes (without security bit) Mass Erase Yes No EEPROM-like Erase Yes Yes Write/Read Yes (without security bit) Yes (without security bit or its own sector) EEPROM-like Write/Read Yes Yes

8.3.2 Flash Operation in ICP Mode

ICP mode is performed without removing the micro-controller from the system. In ICP mode, the user system must be power-off, and the programmer can refresh the program memory through ICP programming interface. The ICP programming interface consists of 6 wires (VDD, GND, TCK, TDI, TMS, TDO). At first the four JTAG pins (TDO, TDI, TCK, TMS) are used to enter the programming mode. Only after the three pins are inputted the specified waveform, the CPU will enter the programming mode. For more detail description please refers to the FLASH Programmer’s user guide. In ICP mode,all the flash operations are completed by the programmer through 6 -wire interface. Since the program timing is very sensitive, five jumpers are needed (VDD, TDO, TDI, TCK, TMS) to separate the program pins from the application circuit as the following diagram. MCU TCK TDI TDO GN D To Application Circuit Jumper Flash Programmer VDD TMS The recommended steps are as following: (1) The jumpers must be open to separate the programming pins from the application circuit before programming. (2) Connect the programming interface with programmer and begin programming. (3) Disconnect programmer and short these jumpers after programming is complete.

8.4 SSP Function

The SH88F6161/SH88F6162 provides SSP (Self Sector Programming) function, each sector can be sector e rased or programmed by the user’s code if the selected sector is not be protected. But once sector has been programmed, it cannot be reprogrammed before sector erase. The SH88F6161/SH88F6162 builds in a complex control flow to prevent the code from carelessly modification. If the dedicated conditions are not met (IB_CON1-5), the SSP will be terminated.

8.4.1 SSP Registers

(1) Memory Page Register for Programming Table 8.4 Memory Page Register for Programming F7H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) 0 0 0 0 0 0 0 0 Bit Number Bit Mnemonic Description 7-2 XPAGE[7:2] Sector of the flash memory to be programmed, 000000---means sector 0, and so on 1-0 XPAGE[1:0] High Address of Offset of the flash memory sector to be programmed Table 8.5 Offset of Flash Memory for Programming FBH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 IB_OFFSET IB_OFF SET.7 IB_OFF SET.6 IB_OFF SET.5 IB_OFF SET.4 IB_OFF SET.3 IB_OFF SET.2 IB_OFF SET.1 IB_OFF SET.0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) 0 0 0 0 0 0 0 0 Bit Number Bit Mnemonic Description 7-0 IB_OFFSET[7:0] Low Address of Offset of the flash memory sector to be programmed XPAGE[1:0] and IB_OFFSET[7:0] are total 10 bits, stored all sectors within the 1024 bytes offset. For EEPROM-like memory, one sector is 256 bytes, total 8 sectors, register defined as below: Table 8.6 Offset Register for Programming F7H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) 0 0 0 0 0 0 0 0 Bit Number Bit Mnemonic Description 7-3 XPAGE[7:3] Reserved 2-0 XPAGE[2:0] Sector of the flash memory to be programmed, 000: sector0 001: sector1 010: sector2 011: sector3 100: sector4 101: sector5 110: sector6 111: sector7 EEPROM-like area can be accessed by the instruction “MOVC A, @A+DPTR” or “MOVC A, @A+PC”, note: need to set FAC bit in FLASHCON register.

Table 8.7 Offset of Flash Memory for Programming FBH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 IB_OFFSET IB_OFF SET.7 IB_OFF SET.6 IB_OFF SET.5 IB_OFF SET.4 IB_OFF SET.3 IB_OFF SET.2 IB_OFF SET.1 IB_OFF SET.0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) 0 0 0 0 0 0 0 0 Bit Number Bit Mnemonic Description 7-0 IB_OFFSET[7:0] Address of Offset of the flash memory sector to be programmed IB_OFFSET[7:0]are total 8 bits, stored all EEPROM-like sectors within the 256 bytes offset. (2) Data Register for Programming Table 8.8 Data Register for Programming FCH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) 0 0 0 0 0 0 0 0 Bit Number Bit Mnemonic Description 7-0 IB_DATA[7:0] Data to be programmed (3) Operation Mode Selection Register Table 8.9 SSP Type select Register F2H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) 0 0 0 0 0 0 0 0 Bit Number Bit Mnemonic Description 7-0 IB_CON1[7:0] SSP Type select 0xE6: Sector Erase 0x6E: Sector Programming (4) SSP Flow Control Register Table 8.10 SSP Flow Control Register1 F3H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 IB_CON2 - - - - IB_CON2.3 IB_CON2.2 IB_CON2.1 IB_CON2.0 R/W - - - - R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) - - - - 0 0 0 0 Bit Number Bit Mnemonic Description 3-0 IB_CON2[3:0] Must be 05H, else Flash Programming will terminate

Table 8.11 SSP Flow Control Register2 F4H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 IB_CON3 - - - - IB_CON3.3 IB_CON3.2 IB_CON3.1 IB_CON3.0 R/W - - - - R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) - - - - 0 0 0 0 Bit Number Bit Mnemonic Description 3-0 IB_CON3[3:0] Must be 0AH else Flash Programming will terminate Table 8.12 SSP Flow Control Register3 F5H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 IB_CON4 - - - - IB_CON4.3 IB_CON4.2 IB_CON4.1 IB_CON4.0 R/W - - - - R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) - - - - 0 0 0 0 Bit Number Bit Mnemonic Description 3-0 IB_CON4[3:0] Must be 09H, else Flash Programming will terminate Table 8.13 SSP Flow Control Register4 F6H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 IB_CON5 - - - - IB_CON5.3 IB_CON5.2 IB_CON5.1 IB_CON5.0 R/W - - - - R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) - - - - 0 0 0 0 Bit Number Bit Mnemonic Description 3-0 IB_CON5[3:0] Must be 06H, else Flash Programming will terminate

8.4.2 Flash Control Flow

IB_CON1=E6H &IB_CON2[3:0]=5H &IB_CON3=AH &IB_CON4=9H &IB_CON5=6H IB_CON1=6EH &IB_CON2[3:0]=5H &IB_CON3=AH &IB_CON4=9H &IB_CON5=6H Programming Set IB_OFFSET Set XPAGE Set IB_DATA Set IB_CON1 IB_CON2≠5H IB_CON2[3:0]≠5H Set IB_CON2[3:0]=5H IB_CON3≠AH Set IB_CON3=AH IB_CON3≠AH Set IB_CON4=9H IB_CON4≠9H Set IB_CON5=6H IB_CON2≠5H ELSE Sector Erase Reset IB_CON1-5

8.4.3 SSP Programming Note

To successfully complete SSP programming, the user’s software must following the steps below: (1) For Code/Data Programming 1. Disable interrupt; 2. Fill in the XPAGE, IB_OFFSET for the corresponding address; 3. Fill in IB_DATA if programming is wanted; 4. Fill in IB_CON1-5 sequentially; 5. Add 4 nops for more stable operation; 6. Code/Data programming, CPU will be in IDLE mode; 7. Go to Step 3 if more data are to be programmed; 8. Clear XPAGE; enable interrupt if necessary. (2) For Sector Erase 1. Disable interrupt; 2. Fill in the XPAGE for the corresponding sector; 3. Fill in IB_CON1-5 sequentially; 4. Add 4 NOPs for more stable operation; 5. Sector Erase, CPU will be in IDLE mode; 6. Go to step 2 if more sectors are to be erased; 7. Clear XPAGE; enable interrupt if necessary. (3) For Code Reading Just Use “MOVC A, @A+DPTR” or “MOVC A, @A+PC”. (4) For EEPROM-Like Steps is same as code programming,the diffenrences are: 1. Set FAC bit in FLASHCON register before programming or erase EEPROM-Like. 2. One sector of EEPROM-Like is 256 bytes.

8.4.4 In System Programming (ISP)

In system programming model is that the code running in the boot sector (BootRom Block), excutes erase or read or write operations on the Flash memory. SH88F6161/SH88F6162 to support ISP mode with built -in 1K bytes of the boot sector, located in FC00H - FFFFH. Erase, burning and write operations on program memory and customer information block excuted by the code running in program memory area is the same as the operation in is the same as operation excuted by the code running in the boot sector (see sector self programming (SSP) section). Customer information block correspond to the block that XPGAE[3:0] is defined as 1000. When erasing and writing the customer block, XPGAE[3:0] should be set to 1000. Customer information block can be accessed by the command "MOVC A, @A+DPTR". Note: FAC bits (FLASHCON.0) need to be set to 1. If customers enable the ISP funct ion (options OP_ISP 0 code, see the code options section), the last sector address of the program memory area (FC00H - FFFFH) will be mapped as a boot sector address, not as a program memory area to use; if customers disable the ISP function (OP_ISP is set to 1, see the code option section), the last sector of the program memory (FC00H - FFFFH) can be used as a program storage area. ISP can erase and program ISP can not erase or program Program Memory Block 0000H BootRom Block FC00H FFFFH Program Memory Block BootRom Block No Use After the reset by power on or reset pin, if ISP function is disable, the code will run from 0000H; if ISP function is disable, there are two possibilities as follow: (1) If OP_ISPPIN = 0, the code in boot sector will be run,and wii run from FC00H. (2) If OP_ISPPIN = 1, the code will run from FC00H when the chip is reset with P3.4 and P3.5 all held low for 100 µs, otherwise, the code will run from 0000H. When ISP is enable and ISPCON[7:0] = 0AH, the code run in program area can be jumped to the boot sector. And if ISPCON[7:0] is not equal to 0AH, jumping boot sector will result OVL event. The special condition should be meet when setting ISPCON. When ISP is disable, boot sector no exists. Then FC00H-FFFFH area as program memory can be accessed freely.

Table 8.14 ISP Auxiliary Register A5H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) 0 0 0 0 0 0 0 0 Bit Number Bit Mnemonic Description 7-0 ISPLO[7:0] ISP auxiliary register 55H:allows the software to programe ISPCON register other:prohibit the software to programe ISPCON register Table 8.15 Software reset flag and instruction access control register A7H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 FLASHCON SWRF - - - - - - FAC R/W R/W - - - - - - R/W Reset Value (POR/WDT/LVR/PIN) 0 - - - - - - 0 Bit Number Bit Mnemonic Description

7 SWRF

only be set by hardware after software reset； cleared by software or other reset

0 FAC

Executive area select bit (see SSP section ) note: when the code running in the boot sector, FAC should be cleared, Boot sector can be accessed by MOVC instruction Table 8.16 ISP control register A6H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) 0 0 0 0 0 0 0 0 Bit Number Bit Mnemonic Description 7-0 ISPCON[7:0] ISP control bit When the program running in the boot sector, setting ISPCON to 5AH will result software reset, and setting ISPCON to other values will make ISPCON change to 0AH. When the program running in the program area, setting ISPCON to 0AH will make the pc jump from program area to boot sector, and setting ISPCON to other values will make ISPCON change to 00H Note: The software reset function is set for pc in order to jump from boot sector to program area. When the code in program is updated by the code running in the boot sector, the pc can be set to 0000H by executing software reset. Then the program will run from 0000H. When the code run in the boot sector, the modification of encryption control byte take effect immediately .

The software reset will cause the follow operations: (1) The modified Code Operation is effective. (2) Jump to program area and execute the code,Then jumpping to boot sector is not permitted. (3) The initial value of SFR is the same as the value after POR. Note: (1) ISPLO should be set to 55H firstly, and then ISPCON can be set; between the modification of ISPLO and ISPCON, other instruction can not be inserted. otherwisely, ISPLO will be cleared and ISPCON will be kept; When ISPCON has been set, ISPLO will be cleared. (2) If the value written to ISPLO register is not equal to 55H, ISPLO will be cleared and ISPCON keep not be changed. Burning the chip Using the Serial Port The BootRom program has been rooted by factory.When enable ISP function by setting OP_ISP to 0,the code wil be updated by cooperating with PC software through the UART port(TXD(P6.4) and RXD(P6.5)). The PC software can be download from www.sinowealth.com

8.4.5 Readable identificantion Code

A 5-Byte readable identificantion code is burned in the chip after produced, Every byte is between 0 and 255. they can not be erased, and can be read by program and program tool. When want to read the 5-Byte number, FAC should be set to one. And then write 127B - 127F to DPTR with clearing register A. Thus the identificantion code can be read by “MOVC A, @A+DPTR” instruction. Note: after reading the identificantion code, the FAC must be clear ed. Otherwise it will affect the user program to read code area. FLASHCON Register is described as follow: Table 8.17 Flash Access Control Register A7H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 FLASHCON - - - - - - - FAC Reset Value (POR/WDT/LVR/PIN) - - - - - - - 0 Bit Number Bit Mnemonic Description FAC: Flash access control 0: access Main Block area by MOVC instruction or SSP function 1: access EEPROM-like by MOVC instruction or SSP function

8.5 System Clock and Oscillator

8.5.1 Features

 Four oscillator types: 32.768kHz crystal, crystal oscillator, ceramic oscillator, 12MHz internal RC and PLL  Built-in 12MHz Internal RC  Built-in 32.768kHz speed up circuit  Built-in system clock prescaler

8.5.2 Clock Definition

The SH88F6161/SH88F6162 have several internal clocks defined as below: 32KCRYCLK: the oscillator clock from XTAL 32.768kHz crystal oscillator. f 32KCRY is defined as the 32KCRYCLK fr equency. t32KCRY is defined as the 32KCRYCLK period. CRYCLK: the oscillator clock from XTAL or XTALX 2M -12MHz crystal oscillator, ceramic oscillato. f CRY is defined as theCRYCLK frequency. tCRY is defined as the CRYCLK period. HRCCLK: the oscillator clock from internal 12MHz RC. f HRC is defined as the HRCCLK frequency. t HRC is defined as the HRCCLK period. LRCCLK: the oscillator clock from internal 128K Hz RC. f FLC is defined as the LRC CLK frequency. t FLC is defined as the LRCCLK period. PLLCLK: the oscillator clock from PLL. fPLL is defined as the PLLCLK frequency. tPLL is defined as the PLLCLK period. WDTCLK: the internal WDT RC clock. fWDT is defined as the WDTCLK frequency. tWDT is defined as the WDTCLK period. SCMCLK: the oscillator clock from internal 32kHz monitor RC. fSCM is defined as the SCMCLK frequency. tSCM is defined as the SCMCLK period. OSC1CLK: Selected from 2 types of low frequency clock source (input 32.767K from external pin, the internal 128K RC). OSC2CLK: Selected from 2 types of high frequency clock source (input 2 - 12M from external pin, the internal 12M RC). OSCSCLK: Selected from two types of high frequency clock source (OSC2CLK, (PLLclock frequency)/2). SYSCLK: system clock, the output of system clock prescaler. It is the CPU instruct ion clock. fSYS is defined as the SYSCLK frequency. tSYS is defined as the SYSCLK period. 32.768k/ 2M~12M 12MHz RC 4 times PLL 2K RC m u x /1 /12 cpu peripheral device SYSCLK 32KCRYCLK/C RYCLK PLLCLK HRCCLK CRYCLK WDT WDTCLK OP_OSC[3:0] CLKS[1:0] SCMIF LRCCLK XTAL1 XTAL2 XTALX1 XTALX2 USB 2M~12M 128KHzRC PLLFS 32K SCMCLK FS m u x OSC1CLK OSC2CLK DAC 48M m u x OSCSCLK

8.5.3 Description

SH88F6161/SH88F6162 has four oscillator types: 32.768kHz crystal oscillator, 2M~12MHz crystal/ceramic oscillator, PLL and internal RC (12MHz /128KHz), which is selected by code option OP_OSC (Refer to code option section for details). SH88F6161/SH88F6162 have 4 Oscillator pins (XTAL1, XTAL2, XTALX1, XTALX2) and can generates one or two clock sources from four oscillator types. It is selected by code option OP_OSC (Refer to code option section for details). The oscillator generates the basic clock pulse that provides the system clock to supply CPU and on-chip peripherals. clock sources can be switched mutually,and how to select will be introduced in the follow sections. when using USB moudle, external 12M or internal 12MRC oscillator should be choosed as the OSC2CLK. When CLKRCEN bit in the CLKLO register is 0, the internal 12MRC will be corrected by chip factory, as a fixed value; when CLKRCEN = 1, the Internal 12MRC corrected by facture can be modified by user software: through modifying the CLKRC0 register to adjust RC oscillation frequency . CLKRC1 is the value that has been corrected by factory, when the RC oscillation frequency offset has been adjusted which is too large, the initial value corrected can be gained by reading CLKRC1 register.

8.5.4 Registers

Table 8.18 System Clock Control Register B2H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 CLKCON 32k_SPDUP CLKS1 CLKS0 SCMIF OSC2ON FS - - R/W R/W R/W R/W R R/W R/W - - Reset Value (POR/WDT/LVR/PIN) 1 1 1 0 0 0 - - Bit Number Bit Mnemonic Description 7 32k_SPDUP 32.768kHz oscillator speed up mode control bit 0: 32.768kHz oscillator normal mode, cleared by software. 1: 32.768kHz oscillator speed up mode, set by hardware or software. This control bit is set by hardware automatically in all kinds of RESET such as Power on reset, watch dog reset etc. to speed up the 32.768kHz Oscillator oscillating, shorten the 32.768kHz oscillator start-oscillating time. And this bit also can be set or cleared by software if necessary. Such as set before entering Power-down mode and cleared when Power-down mode wakes up. It should be noted that turning off 32.768kHz oscillator speed up (clear this bit) could reduce the system power consumption. Only when code option OP_OSC is 1010 or 1101, this bit is valid. (32.768kHz oscillator is selected, Refer to code option section for details) 6-5 CLKS[1: 0] SYSCLK Prescaler Register 00: fSYS = fOSCS 01: fSYS = fOSCS/2 10: fSYS = fOSCS/4 11: fSYS = fOSCS/12 If 32.768kHz oscillator is selected as OSCSCLK, these control bits is invalid.

3 OSC2ON

OSC2CLK On control Register 0: Cleared to turn off OSC2CLK 1: Set to turn on OSC2CLK 2 FS Frequency Select Register 0: OSC1CLK is selected as OSCSCLK 1: OSC2CLK is selected as OSCSCLK

Table 8.19 PLL Clock Control Register BCH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PLLCON - - - - - PLLSTA PLLON PLLFS R/W - - - - - R R/W R/W Reset Value (POR/WDT/LVR/PIN) - - - - - 0 0 0 Bit Number Bit Mnemonic Description

2 PLLSTA

0: PLL has not lock phase 1: PLL lock phase Stable clock can be output after PLL lock phase

1 PLLON

0: PLL off 1: PLL on Only when OSC2ON = 1, this bit is valid

0 PLLFS

PLL system clock select Register 0: PLL is not selected as OSC2CLK 1: 1/2 Prescaler frequency of PLL used as OSCSCLK PLL input clock must be greater than 5M Table 8.20 Internal RC adjust control register BDH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 CLKLO CLKRCEN - - - CLKLO.3 CLKLO.2 CLKLO.1 CLKLO.0 R/W R/W - - - R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) 0 - - - 0 0 0 0 Bit Number Bit Mnemonic Description

7 CLKRCEN

Internal RC software adjust control register 0: software adjust disable, adjust by hardware 1: software adjust enable, and CLKRC0 is valid 3-0 CLKLO[3:0] Internal RC software adjust lock register Only when CLKLO = 0x8A, CLKRC0 could be modified Table 8.21 Internal RC adjust register BEH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) u u u u u u u u Bit Number Bit Mnemonic Description 7-0 CLKRC0[7:0] Internal RC adjust register Only when CLKLO = 0x8A, CLKRC0 could be modified. When CLKLO = 0x8A,followed by CLKRC0 be written, Then the value written to CLKRC0 will be valid. By setting this register,the internal RC oscillation frequency can be adjusted. Every adjusting range is about 0.25% (0 is the lowerest, and 256 is the highest. The range between 0 and 127 is used to adjust small frequency, and the range between 128 and 256 is used to adjust large frequency) The value of this register after POR is the data of internal RC corrected by factory.

Table 8.22 Internal RC initial adjust value register BFH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 R/W R R R R R R R R Reset Value (POR/WDT/LVR/PIN) u u u u u u u u Bit Number Bit Mnemonic Description 7-0 CLKRC1[7:0] Internal RC initial adjust value register This register is read-only. The data is factory correction values of 12MHz RC

8.5.5 System Clock Select example

(1) Clock switched from low frequency clock to high frequency clock. Low frequency clock: external 32.768KHZ crystal oscillator clock or internal 128KHZ RC oscillator clock. High frequency clock: external 2M - 12M crystal oscillator clock or internal 12MRC oscillator clock or PLLclock. a. Firstly, set OSC2ON to 1 to open the OSC2CLK; b. Wait for the oscillator to warmup (see oscillator warmup sections), if switch to PLL, the time for PLL input oscillator warmup should be waited; if not to PLL, jump to “f” to execute; c. If switch to PLL, need to set PLLON to 1 to open the PLL; d. If PLL is opened, Wait at least 2ms, to ensure PLLSTA = 1 (output stabilized frequency); e. If switch to PLL, set PLLFS =1 to select PLLCLK as OSCSCLK; f. Set FS = 1 to select OSCSCLK as SYSCLK. (2) Clock switched from high frequency clock to low frequency clock: a. Set FS = 0 to select OSC1CLK as SYSCLK; b. If switch from PLL to OSC1CLK, and USB is not enable, PLL should be turned off (PLLON = 0) to reduce the power consumption of the system; c. set OSC2ON = 0 to turn off OSC2CLK, which can reduce the power consumptionof the system. Note: when switch to high frequency clock, the clock need to be switched should be open firstly, then start to convert after the warmup of oscillator.

8.5.6 Oscillator Type

(1) OP_OSC[3:0] = 0011:OSC1CLK is interna128K RC Oscillator, OSC2CLK is interna12M RC Oscillator. XTAL and XTALX are shared with IO XTALX1 XTALX2 XTAL1 XTAL2 (2) OP_OSC[3:0] = 1010: the OSC1CLK is 32.768kHz Crystal Oscillator input from XTAL, OSC2CLK is interna12M RC Oscillator XTALX shared with I/O XTALX1 XTALX2 XTAL1 XTAL2 32.768kHz (3) OP_OSC[3:0] = 1101: the OSC1CLK is 32.768kHz Crystal Oscillator input from XTAL, The OSC2CLK is 2M - 12M Crystal/Ceramic Oscillator input from XTALX. XTALX1 XTALX2 XTAL1 XTAL2 32.768kHz Crystal (4) OP_OSC[3:0] = 0110: the OSC1CLK is internal 128K RC,the OSC2CLK is 2M- 12M Crystal/Ceramic Oscillator input from XTAL. XTALX1 XTALX2 XTAL1 XTAL2 Crystal

8.5.7 Capacitor Selection for Oscillator

Ceramitor Oscillator Remarks Frequency C1 C2 2MHz 21 - 39pF 21 - 39pF no bulit-in ceramic resonator load capacitance 4MHz 21 - 39pF 21 - 39pF Different parameters under model 12 - 18pF 12 - 18pF 15pF 15pF 6MHz 21 - 39pF 21 - 39pF Different parameters under model 12 - 18pF 12 - 18pF 15pF 15pF 8MHz 21 - 39pF 21 - 39pF Different parameters under model 7 - 13pF 7 - 13pF 12 - 18pF 12 - 18pF 7.5 - 12.5pF 7.5 - 12.5pF 15pF 15pF 10MHz 7 - 13pF 7 - 13pF Different parameters under model 15pF 15pF 12MHz 7 - 13pF 7 - 13pF Different parameters under model 7.5 - 12.5pF 7.5 - 12.5pF XTAL Capacitor Selection for Oscillator Crystal Oscillator Remarks Frequency C1 C2 32.768kHz 15pF 15pF no 4MHz 8 - 15pF 8 - 15pF no 8MHz 8 - 15pF 8 - 15pF no 10MHz 8 - 15pF 8 - 15pF no 12MHz 8 - 15pF 8 - 15pF no Note: (1) Capacitor values are used for design guidance only! (2) Be careful for the stray capacitance on PCB board, the user should test the performance of the oscillator over the expected VDD and the temperature range for the application. Before selecting crystal/ceramic, the user should consult the crystal/ceramic manufacturer for appropriate value of external component to get best performance.

8.6 System Clock Monitor (SCM)

In order to enhance the system reliability, SH88F6161/SH88F6162 contains a system clock monitor (SCM) module. If the system clock fails (for example the oscillator stops oscillating), the built -in SCM will switch the OSCCLK to the internal 32k WDTCLK and set system clock monitor bit (SCMIF) to 1. An d the SCM interrupt will be generated when EA and ESCM is enabled. If the OSCCLK comes back, SCM will switch the OSCCLK back to the oscillator and clears the SCMIF automatically. Notes: The SCMIF is read only register; it can be clear to 0 or set to 1 by hardware only. If SCMIF is cleared, the SCM switches the system clock to the state before system clock fail automatically. If Internal RC is selected as OSCCLK by code option (Refer to code option section for detail), the SCM can not work. Table 8.23 System Clock Control Register B2H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 CLKCON - - - SCMIF - - - - Reset Value (POR/WDT/LVR/PIN) - - - 0 - - - - Bit Number Bit Mnemonic Description

4 SCMIF

0: Clear by hardware to indicate system clock is normal 1: Set by hardware to indicate system clock fails

8.7 I/O Port

8.7.1 Features

 61 bi-directional I/O ports  Share with alternative functions The SH88F6161/SH88F6162 has 61 bi-directional I/O ports. The PORT data is put in Px register. The PORT control register (PxCRy) controls the PORT as input or output. Each I/O port has an internal pull-high resistor, which is controlled by PxPCRy when the PORT is used as input (x = 0-7, y = 0-7). For SH88F6161/SH88F6162, some I/O pins can share with alternative functions. There exists a priority rule in CPU to avoid these functions be conflict when all the functions are enabled. (Refer to Port Share Section for details).

8.7.2 Registers

Table 8.24 Port Control Register E1H - E5H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) 0 0 0 0 0 0 0 0 Bit Number Bit Mnemonic Description 7-0 PxCRy x = 0-7, y = 0-7 Port input/output direction control Register 0: input mode 1: output mode Table 8.25 Port Pull up Resistor Control Register E9H - EDH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) 0 0 0 0 0 0 0 0 Bit Number Bit Mnemonic Description 7-0 PxPCRy x = 0-7, y = 0-7 Input Port internal pull-high resistor enable/disable control 0: internal pull-high resistor disabled 1: internal pull-high resistor enabled

Table 8.26 Port Data Register 80H, 90H, A0H, B0H, C0H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) 0 0 0 0 0 0 0 0 Bit Number Bit Mnemonic Description 7-0 Px.y x = 0-7, y = 0-7 Port Data Register Table 8.27 Port output Mode select register A1H (Bank1) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 P6OS P6OS.7 P6OS.6 - - - - - - R/W R/W R/W - - - - - - Reset Value (POR/WDT/LVR/PIN) 0 0 - - - - - - Bit Number Bit Mnemonic Description 7-6 P6OS.x x = 7-6 Port output mode select 0:act as a CMOS push-pull output 1: act as a open drain output of N channel

8.7.3 Port Diagram

Read Data Register/Pad Selection Read PxPCRy Output Mode I/O Pad 0: From Pad 1: From data register SFEN Second Function Input Mode Read Port Data Register (Pull-up) 0 = ON 1 = OFF VDD VDD 0 = OFF 1 = ON Port Diagram Note: (1) The input source of reading input port operation is from the input pin directly. (2) The input source of reading output port operation has two paths, one is from the port data Register, and the other is from the output pin directly. The read Instruction distinguishes which path i s selected: The read- modify-write instruction is for the reading of the data register in output mode, and the other instructions are for reading of the output pin directly. (3) The destination of writing port operation is the data register regardless the port shared as the second function or not. (4) In power-down mode:The reserve pins of LQFP64 package must be set to output or input with pull -high to avoid leakage current.

8.7.4 Port Share

The 61 bi-directional I/O ports can also share second or third s pecial function. But the share priority should obey the Outer Most Inner Lest rule: The out most pin function in Pin Configuration has the highest priority, and the inner most pin function has the lowest priority. This means when one pin is occupied by a higher priority function (if enabled), it cannot be used as the lower priority functional pin, even the lower priority function is also enabled. Only until the higher priority function is closed by hardware or software, can the corresponding pin be release d for the lower priority function use. Also the function that need pull up resister is also controlled by the same rule. When port share function is enabled, the user can modify PxCR, PxPCR (x = 0-8), but these operations will have no effect on the port status until the second function was disabled. When port share function is enabled, any read or write operation to port will only affect the data register while the port pin keeps unchanged until all the share functions are disabled. PORT0: - SCK/ADC0(P0.0): SPI clock port/ADC channel0 - SS/ADC1(P0.1): SPI Master or Slave select/ADC channel1 - MOSI/ADC2/SEG31(P0.2): SPI data port/ADC channel0/LCD SEG31 - MISO/ADC3/SEG32(P0.3): SPI data port/ADCchannel3/LCD SEG32 - ADC4/SEG33(P0.4): ADC channel4/LCD SEG33 - ADC5/SEG34(P0.5): ADC channel5/LCD SEG34 - ADC6/LED_C10/SEG35(P0.6): ADC channel6/LED COM10/LCD SEG35 - ADC7/LED_C9/SEG36(P0.7): ADC channel7/LED COM9/LCD SEG35 Table 8.28 PORT0 Share function Table Pin No. Priority Function Enable bit LQFP64 TQFP48 4 -

1 SCK Set SPEN bit in SPSTA register

2 ADC0 SCH[3:0] in SCHCON1 register is 0000 and the bit0 of SCHCON2 register is set to

3 P0.0 above condition is not met 5 -

1 SS set SPEN bit in SPSTA register, and clear SSDIS bit in SPCON register

2 ADC1 SCH[3:0] bit in SCHCON1 register is 0001 and the bit1 in SCHCON2 registers is

3 P0.1 above condition is not met 6 -

1 MOSI set SPEN bit in SPSTA register

2 ADC2 SCH[3:0] bit in SCHCON1 register is 0010 and the bit2 in SCHCON2 register is set

3 SEG31 Clear DISPSEL bit in DISPCON register and set P4S6 bit in P4SS register

4 P0.2 above condition is not met 7 -

1 MISO set SPEN bit in SPSTA register

2 ADC3 SCH[3:0] bit in SCHCON1 register is 0011 and the bit3 in SCHCON2 registers is

3 SEG32 Clear DISPSEL bit in DISPCON register and set P4S7 bit in P4SS register

4 P0.3 above condition is not met 8 4

1 ADC4 SCH[3:0] bit in SCHCON1 register is 0100 and the bit4 in SCHCON2 register is set

2 SEG33 Clear DISPSEL bit in DISPCON register and set P5S0 bit in P5SS register

3 P0.4 above condition is not met 9 5

1 ADC5 SCH[3:0] bit in SCHCON1 register is 0101 and the bit5 in SCHCON2 register is set

2 SEG34 Clear DISPSEL bit in DISPCON registe and set P5S1 bit in P5SS register

3 P0.5 above condition is not met (to be continued)

(continue) 10 6

1 ADC6 SCH[3:0] bit in SCHCON1 register is 0110 and the bit6 in SCHCON2 register is set

2 LED_C10 Set DISPSEL bit in DISPCON register and set P7S1 bit in P7SS register

3 SEG35 Clear DISPSEL bit in DISPCON register and set P5S2 bit in P5SS register

4 P0.6 above condition is not met 11 7

1 ADC7 SCH[3:0] bit in SCHCON1 register is 0111 and the bit7 in SCHCON2 register is set

2 LED_C9 Set DISPSEL bit in DISPCON register and set P7S0 bit in P7SS register

3 SEG36 Clear DISPSEL bit in DISPCON register and set P5S3 bit in P5SS register

4 P0.7 above condition is not met PORT1: - ADC8/LED_C8 /SEG37(P1.0): ADCchannel8/LED COM8 /LCD SEG37 - ADC9/LED_C7 /SEG38(P1.1):ADCchannel9/LED COM7/LCD SEG38 - ADC10/LED_C6/COM6/SEG39(P1.2):ADCchannel10/LED COM6/LCD COM6/LCD SEG39 - ADC11/LED_C5/COM5/SEG40(P1.3):ADCchannel11/LED COM5/LCD COM5/LCD SEG40 - Vref/LED_C4/COM4(P1.4):ADC reference voltage input/LED COM4/LED COM4 - Cref/LED_C3/COM3(P1.5):built-in reference voltage output/LED COM3/LCD COM3 - DACO/LED_C2/COM2(P1.6):D/A output /LED COM2/LCD COM2 - LED_C1/COM1(P1.7):LED COM1/LCD COM1 Table 8.29 PORT1 Share function Table Pin No. Priority Function Enable bit LQFP64 TQFP48 12 8

1 ADC8 SCH[3:0] bit in SCHCON1 register is1000 and the bit0 of SCHCON3 register is set

2 LED_C8 Set DISPSEL bit in DISPCON register and set P6S7 bit in P6SS register

3 SEG37 Clear DISPSEL bit in DISPCON register and set P5S4 bit in P5SS register

4 P1.0 above condition is not met 13 9

1 ADC9 SCH[3:0] bit in SCHCON1 register is 1001 and the bit1 of SCHCON3 register is set

2 LED_C7 Set DISPSEL bit in DISPCON register and set P6S6 bit in P6SS register

3 SEG38 Clear DISPSEL bit in DISPCON register and set P5S5 bit in P5SS register

4 P1.1 above condition is not met 14 10

1 ADC10 SCH[3:0] bit in SCHCON1 register is 1010 and the bit2 of the SCHCON3 register is

2 LED_C6 Set DISPSEL bit in DISPCON register and set P6S5 bit in P6SS register

3 COM6 DISPSEL bit in DISPCON register is cleared, DUTY[1:0] bit is 10 and the P5S6 bit

in P5SS register is set to one

4 SEG39 The DISPSEL bit in DISPCON register is cleared, the DUTY[1:0] bit is 00 or 01 and

the P5S6 bit in P5SS register is set to 1 5 P1.2 above condition is not met 15 11

1 ADC11 SCH[3:0] bit in SCHCON1 register is 1011 and the bit3 in SCHCON3 register is set

2 LED_C5 Set DISPSEL bit in DISPCON register and set P6S4 bit in P6SS register

3 COM5 The DISPSEL bit in DISPCON register is cleared, the DUTY[1:0] bit is 01 or 10 and

the P5S7 bit in P5SS register is set to 1

4 SEG40 DISPSEL bit in DISPCON register is cleared, DUTY[1:0] bit is 00 and the P5S7 bit

in P5SS register is set to 1 5 P1.3 above condition is not met (to be continued)

(continue) 16 12

1 Vref set VREFS bit in DACCON1 register to one

2 LED_C4 Set DISPSEL bit in DISPCON register and set P6S3 bit in P6SS register

3 COM4 Clear DISPSEL bit in DISPCON register and set P6S3 bit in P6SS register

4 P1.4 above condition is not met 17 13

1 Cref set REFON bit in DACCON1 register

2 LED_C3 Set DISPSEL bit in DISPCON register and set P6S2 bit in P6SS register

3 COM3 Clear DISPSEL bit in DISPCON register and set P6S2 bit in P6SS register

4 P1.5 above condition is not met 18 14

1 DACO set DACIO bit in DACCON1 register

2 LED_C2 Set DISPSEL bit in DISPCON register and set P6S1 bit in P6SS register

3 COM2 Clear DISPSEL bit in DISPCON register and set P6S1 bit in P6SS register

4 P1.6 above condition is not met 19 15

1 LED_C1 Set DISPSEL bit in DISPCON register and set P6S0 bit in P6SS register

2 COM1 Clear DISPSEL bit in DISPCON register and set P6S0 bit in P6SS register

3 P1.7 above condition is not met PORT2: - OPN2(P2.0): Negative OP input2 - TCK/OPN1(P2.1): testing clock input/Negative OP input1 - TDI/OPN0(P2.2): testing data input/Negative OP input0 - TMS/OPO(P2.3): testing mode select/OP output pin - TDO/OPP0(P2.4): testing data out put/Positive OP input0 - OPP1(P2.5): Positive OP input1 - D+(P2.6): Positive data USB - D-(P2.7): Negative data USB Table 8.30 PORT2 share function table Pin No. Priority Function Enable bit LQFP64 TQFP48 23 -

1 OPN2 set OPN2IO bit in OPIOS register

2 P2.0 above condition is not met 24 19

1 TCK debug interface

2 OPN1 set OPN1IO bit in OPIOS register

3 P2.1 above condition is not met 25 20

1 TDI debug interface

2 OPN0 set OPN1IO bit in OPIOS register

3 P2.2 above condition is not met 26 21

1 TMS debug interface

2 OPO set OPEN bit in OPCON register

3 P2.3 above condition is not met 27 22

1 TDO debug interface

2 OPP0 set OPP0IO bit in OPIOS register

3 P2.4 above condition is not met (to be continued)

(continue) 28 -

1 OPP1 set OPP1IO bit in OPIOS register

2 P2.5 above condition is not met 29 -

1 D- set ENUSB bit in USBCON register

2 P2.6 above condition is not met 30 -

1 D+ set ENUSB bit in USBCON register

2 P2.7 above condition is not met PORT3: - LED_S1/SEG1(P3.0): LED SEG1/LCD SEG1 - LED_S2/SEG2(P3.1): LED SEG2/LCD SEG2 - ECI1/LED_S3/SEG3(P3.2): PCA1 clock input/LEDportSEG3/LCDportSEG3 - P1CEX0/LED_S4/SEG4(P3.3): PCA1compare/capture 0/LED SEG4/LCD SEG4 - P1CEX1/LED_S5/SEG5(P3.4): PCA1 compare/capture 1/LED SEG5/LCD SEG5 - P1CEX2/LED_S6/SEG6(P3.5): PCA1 compare/capture 2/LED SEG6/LCD SEG6 - ECI2/LED_S7/SEG7(P3.6): PCA2 clock input/LED SEG7/LCD SEG7 - P2CEX0/LED_S8/SEG8(P3.7): PCA2 compare/capture 0/LED SEG8/LCD SEG8 Table 8.31 PORT3 share function table Pin No. Priority Function Enable bit LQFP64 TQFP48 31 23

1 LED_S1 Set DISPSEL bit in DISPCON register and set P1S0 bit in P1SS register

2 SEG1 Clear DISPSEL bit in DISPCON register and set P1S0 bit in P1SS register

3 P3.0 above condition is not met 32 24

1 LED_S2 Set DISPSEL bit in DISPCON register and set P1S1 bit in P1SS register

2 SEG2 Clear DISPSEL bit in DISPCON register and set P1S1bit in P1SS register

3 P3.1 above condition is not met 33 25

1 ECI1 Set PR1 bit in PCACON register and P1CPS[2:0] bit in P1CMD register is 110

2 LED_S3 Set DISPSEL bit in DISPCON register and set P1S2 bit in P1SS register

3 SEG3 Clear DISPSEL bit in DISPCON register and set P1S2 bit in P1SS register

4 P3.2 above condition is not met 34 26

1 P1CEX0 P1SMP0:P1SMN0 = 01: set P1ECOM0 bit in P1CPM0 register and set P1TCP0 bit;

P1SMP0:P1SMN0 = others: set P1TCP0 bit

2 LED_S4 Set DISPSEL bit in DISPCON register and set P1S3 bit in P1SS register

3 SEG4 Clear DISPSEL bit in DISPCON register and set P1S3 bit in P1SS register

4 P3.3 above condition is not met 35 27

1 P1CEX1 P1SMP1:P1SMN1 = 01: set P1ECOM1 bit and P1TCP1 bit in P1CPM1 register;

P1SMP1:P1SMN1 = others: set P1ECOM1 bit in P1CPM1

2 LED_S5 Set DISPSEL bit in DISPCON register and set P1S4 bit in P1SS register

3 SEG5 Clear DISPSEL bit in DISPCON register and set P1S4 bit in P1SS register

4 P3.4 above condition is not met (to be continued)

(continue) 36 28

1 P1CEX2 P1SMP2:P1SMN2 = 01: Set P1ECOM2 bit and P1TCP2 bit in P1CPM2 register;

P1SMP2:P1SMN2 = others: Set P1ECOM2 bit in P1CPM2 resgister

2 LED_S6 Set DISPSEL bit in DISPCON register and set P1S5 bit in P1SS register

3 SEG6 Clear DISPSEL bit in DISPCON register and set P1S5 bit in P1SS register

4 P3.5 above condition is not met 37 29

1 ECI2 Set PR2 bit in PCACON register and set P2CPS[2:0] bit in P2CMD register to110

2 LED_S7 Set DISPSEL bit in DISPCON register and set P1S6 bit in P1SS register

3 SEG7 Clear DISPSEL bit in DISPCON register and set P1S6 bit in P1SS register

4 P3.6 above condition is not met 38 30

1 P2CEX0 P2SMP0:P2SMN0 = 01: Set P2ECOM0 bit and P2TCP0 bit in P2CPM0 register;

P1SMP1:P1SMN1 = others: Set P2ECOM0 bit in P2CPM0 register

2 LED_S8 Set DISPSEL bit in DISPCON register and set P1S7 bit in P1SS register

3 SEG8 Clear DISPSEL bit in DISPCON register and set P1S7 bit in P1SS register

4 P3.7 above condition is not met PORT4: - P2CEX1/SEG9(P4.0): PCA2 compare/capture 1/LCD SEG9 - ECI3/SEG10(P4.1): PCA3 clock input/LCD SEG10 - P3CEX0/SEG11(P4.2): PCA3 compare/capture 0/LCD SEG11 - P3CEX1/SEG12(P4.3): PCA3 compare/capture 1/LCD SEG12 - T2EX/SEG13(P4.4): TIMER2 capture input/LCD SEG13 - T2/SEG14(P4.5): TIMER2 internal clock input/LCD SEG14 - TXD1/SEG15(P4.6): EUART1 sent pin/LCD SEG15 - RXD1/SEG16(P4.7): EUART1 receive pin/LCD SEG16 Table 8.32 PORT4 share function table Pin No. Priority Function Enable bit LQFP64 TQFP48 39 31

1 P2CEX1 P2SMP1:P2SMN1 = 01: set P2ECOM1 bit and P2TCP1 bit in P2CPM1 register;

P1SMP1:P1SMN1 = others: set P2ECOM1 bit in P2CPM1 register

2 SEG9 Clear DISPSEL bit in DISPCON register and set P2S0 bit in P2SS register

3 P4.0 above condition is not met 40 32

1 ECI3 set PR3 bit in PCACON register and set P3CPS[2:0] bit in P3CMD register to 110

2 SEG10 Clear DISPSEL bit in DISPCON register and set P2S1 bit in P2SS register

3 P4.1 above condition is not met 41 33

1 P3CEX0 P3SMP0:P3SMN0 = 01: set P3ECOM0 bit and P3TCP0 bit in P3CPM0 register;

P3SMP0:P3SMN0 = others: set P3ECOM0 bit in P3CPM0 register

2 SEG11 Clear DISPSEL bit in DISPCON register and set P2S2 bit in P2SS register

3 P4.2 above condition is not met 42 34

1 P3CEX1 P3SMP1:P3SMN1 = 01: set P3ECOM1bit and P3TCP1 bit in P3CPM1 register；

P3SMP1:P3SMN1 = others: set P3ECOM1 bit in P3CPM1 register

2 SEG12 Clear DISPSEL bit in DISPCON register and set P2S3 bit in P2SS register

3 P4.3 above condition is not met (to be continued)

(continue) 43 -

1 T2EX

In mode 2, 3, set EXEN2 bit in T2CON register; In mode 1, set DCEN bit in T2CON register, or clear DCEN bit and set EXEN2 bit (Auto pull up)

2 SEG13 Clear DISPSEL bit in DISPCON register and set P2S4 bit in P2SS register

3 P4.4 above condition is not met 44 -

1 T2 set TR2 bit and C/T

---- ---- bit in T2CON register or clear C/T ---- ---- bit with T2OE bit be set in T2MOD register

2 SEG14 Clear DISPSEL bit in DISPCON register and set P2S5 bit in P2SS register

3 P4.5 above condition is not met 45 -

1 TXD1 Write SBUF1 register

2 SEG15 Clear DISPSEL bit in DISPCON register and set P2S6 bit in P2SS register

3 P4.6 above condition is not met 46 -

1 RXD1 set REN1 bit in SCON1 register

2 SEG16 Clear DISPSEL bit in DISPCON register and set P2S7 bit in P2SS register

3 P4.7 above condition is not met PORT5: - SEG17/INT40(P5.0): LCD SEG17/External interrupt40 - SEG18/INT41(P5.1): LCD SEG18/External interrupt41 - SEG19/INT42(P5.2): LCD SEG19/External interrupt42 - SEG20/INT43(P5.3): LCD SEG20/External interrupt43 - SEG21/INT44(P5.4): LCD SEG21/External interrupt44 - SEG22/INT45(P5.5): LCD SEG22/External interrupt45 - SEG23/INT46(P5.6): LCD SEG23/External interrupt46 - SEG24/INT47(P5.7): LCD SEG24/External interrupt47 Table 8.33 PORT5 share function table Pin No. Priority Function Enable bit LQFP64 TQFP48 47 35

1 SEG17 Clear DISPSEL bit in DISPCON register and set P3S0 bit in P3SS register

2 INT40 EX4 bit in IEN1 register is set to one, EXS40 bit in the IENC register is set to one

and P5.0 work in input mode (pull-high mode can be set by software) 3 P5.0 above condition is not met 48 36

1 SEG18 Clear DISPSEL bit in DISPCON register and set P3S1 bit in P3SS register

2 INT41 EX4 bit in IEN1 register is set to one, EXS41 bit in the IENC register is set to one

and P5.1 work in input mode (pull-high mode can be set by software) 3 P5.1 above condition is not met 49 37

1 SEG19 Clear DISPSEL bit in DISPCON register and set P3S2 bit in P3SS register

2 INT42 EX4 bit in IEN1 register is set to one, EXS42 bit in IENC register is set to one, and

P5.2 work in input mode (pull-high mode can be set by software) 3 P5.2 above condition is not met 50 38

1 SEG20 Clear DISPSEL bit in DISPCON register and set P3S3 bit in P3SS register

2 INT43 EX4 bit in IEN1 register is set to one, EXS43 bit in the IENC register is set to one,

and P5.3 work in input mode (pull-high mode can be set by software) 3 P5.3 above condition is not met (to be continued)

(continue) 51 -

1 SEG21 Clear DISPSEL bit in DISPCON register and set P3S4 bit in P3SS register

2 INT44 EX4 bit in IEN1 register is set to one, EXS44 bit in the IENC register is set to one,

and P5.4 work in input mode (pull-high mode can be set by software) 3 P5.4 above condition is not met 52 -

1 SEG22 Clear DISPSEL bit in DISPCON register and set P3S5 bit in P3SS register

2 INT45 EX4 bit in IEN1 register is set to one, EXS45 bit in the IENC register is set to one,

and P5.5 work in input mode (pull-high mode can be set by software) 3 P5.5 above condition is not met 53 -

1 SEG23 Clear DISPSEL bit in DISPCON register and set P3S6 bit in P3SS register

2 INT46 EX4 bit in IEN1 register is set to one, EXS46 bit in the IENC register is set to one,

and P5.6 work in input mode (pull-high mode can be set by software) 3 P5.6 above condition is not met 54 -

1 SEG24 Clear DISPSEL bit in DISPCON register and set P3S7 bit in P3SS register

2 INT47 EX4 bit in IEN1 register is set to one, EXS47 bit in the IENC register is set to one,

and P5.7 work in input mode (pull-high mode can be set by software) 3 P5.7 above condition is not met PORT6: - P0CEX1/SEG25(P6.0): PCA0 compare/capture1/LCD SEG25 - P0CEX0/SEG26/INT2(P6.1): PCA0 compare/capture 0/LCD SEG26/External interrupt2 input - ECI0/SEG27/INT3(P6.2): PCA0 clock input/LCD SEG27/External interrupt3 intput - T3/SEG28(P6.3): TIMER3 clock intput/LCD SEG28 - TXD/SEG29(P6.4): EUART sent pin/LCD SEG29 - RXD/SEG30(P6.5): EUARTreceive pin/LCD SEG30 - SDA(P6.6): TWI data port - SCL(P6.7): TWI clock port Table 8.34 PORT6 share function table Pin No. Priority Function Enable bit LQFP64 TQFP48 55 39

1 P0CEX1 P0SMP1:P0SMN1 = 01: set P0ECOM1 bit and P0TCP1 bit in P0CPM1 register

P0SMP1:P0SMN1 = other: set P0ECOM1 bit

2 SEG25 Clear DISPSEL bit in DISPCON register and set P4S0 bit in P4SS register

3 P6.0 above condition is not met 56 40

1 P0CEX0 P0SMP0:P0SMN0 = 01: set P0ECOM0 bit and P0TCP0 bit in P0CPM0 register

P0SMP1:P0SMN1 = other: set P0ECOM0 bit

2 SEG26 Clear DISPSEL bit in DISPCON register and set P4S1 bit in P4SS register

3 INT2 set EX2 bit in IEN0 register and port 6.1 work in input mode 4 P6.1 above condition is not met 57 41

1 ECI0 Set PR0 bit in PCACON register and P0CPS[2:0] bit in P0CMD register is 110

2 SEG27 Clear DISPSEL bit in DISPCON register and set P4S2 bit in P4SS register

3 INT3 set EX3 bit in IEN0 register and port 6.2 work in input mode 4 P6.2 above condition is not met (to be continued)

(continue) 58 42

1 T3 Set TR3 bit in T3CON register and T3CLKS[1:0] = 01 (Auto pull up)

2 SEG28 Clear DISPSEL bit in DISPCON register and set P4S3 bit in P4SS register

3 P6.3 above condition is not met 59 43

1 TXD Write SBUF register

2 SEG29 Clear DISPSEL bit in DISPCON register and set P4S4 bit in P4SS register

3 P6.4 above condition is not met 60 44

1 RXD set REN bit in SCON register

2 SEG30 Clear DISPSEL bit in DISPCON register and set P4S5 bit in P4SS register

3 P6.5 above condition is not met 61 45

1 SCL When ENTWI bit in the TWICON register is 1, take action to theTWIDAT

2 P6.6 above condition is not met 62 46

1 SDA When ENTWI bit in the TWICON register is 1, take action to theTWIDAT

2 P6.7 above condition is not met PORT7: - RESET(P7.0): reset pin - XTAL1(P7.1): External low frequency/high frequency input oscillator - XTAL2(P7.2): External low frequency/high frequency output oscillator - XTALX1(P7.3): External high frequency input oscillator - XTALX2(P7.4): External high frequency output oscillator Table 8.35 PORT7 share function table Pin No. Priority Function Enable bit LQFP64 TQFP48 63 47

1 RESET Code Option OP_RST = 0 (enable hardware reset)

2 P7.0 above condition is not met 64 48

1 XTAL1 OP_OSC[3:0] = 1010/1100/0110

(32.768K crystal oscillator/crystal oscillator、ceramic oscillator) 2 P7.1 above condition is not met 1 1

1 XTAL2 OP_OSC[3:0] = 1010/1100/0110

(32.768K crystal oscillator/crystal oscillator、ceramic oscillator) 2 P7.2 above condition is not met 2 2

1 XTALX1 OP_OSC[3:0] = 1101 (crystal oscillator、ceramic oscillator)

2 P7.3 above condition is not met 3 3

1 XTALX2 OP_OSC[3:0] = 1101 (crystal oscillator、ceramic oscillator)

2 P7.4 above condition is not met

8.8 Timer

8.8.1 Features

 The SH88F6161/SH88F6162 has TWO timers (Timer2, 3)  Timer2 is compatible with the standard 8052 and can realize the 2 Road 8 bit from overloading the timer function  Timer2 is compatible with the standard 8052 and has up or down counting and programmable clock output function  Timer3 is a 16-bit auto-reload timer and can operate even in Power-Down mode

8.8.2 Timer2

The Timer 2 is implemented as a 16-bit register accessed as two cascaded data registers: TH2 and TL2. It is controlled by the register T2CON and T2MOD. The Timer2 interrupt can be enabled by setting the ET2 bit in the IEN0 register. (Refer to Interrupt Section for details) C/T2 ——— selects system clock (timer operation) or external pin T2 (counter operation) as the timer clock input. Setting TR2 allows Timer 2/Counter 2 Data Register to increment by the selected input. System clock or system clock devided by 12 can be selected as the clock source of timer2 by setting TCLKP2 bit in T2MOD register. Timer2 Modes Timer2 has 3 operating modes: Capture/Reload, Auto -reload mode with up or down counter, Baud Rate Generator and Programmable clock-output. Mode select C/T2 ——— T2OE DCEN TR2 CP/RL2 Mode X 0 X 1 1 0 16-bit capture X 0 0 1 0 1 16-bit auto-reload timer X 0 1 1 0 0 1 X 1 X 2 Programmable clock 1 1 X 1 X Not recommed to use X X X 0 X X Timer 2 stop to work, still allows the T2EX path way Mode0: 16-bit Capture In the capture mode, two options are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer2 is a 16-bit timer or counter which will set TF2 on overflow to generate an interrupt if ET2 is enabled. If EXEN2 = 1, Timer2 performs the same operation, but a 1-to-0 transition at external input T2EX also causes the current value in TH2 and TL2 to be captured into RCAP2H and RCAP2L respectively, In addition, a 1-to-0 transition at T2EX causes bit EXF2 in T2CON to be set. The EXF2 bit, like TF2, can also generate an interrupt if ET2 is enabled. 0:Switch Off 1:Switch On Block Diagram of 16 bit Capcture mode (Mode 0) of Timer2 Overflow flag RCAP2HRCAP2L TL2 TH2 TF2 EXF 0:Switch Off 1:Switch On External falling edge flag Increment Mode C/T2 Interrupt Request TR2 EXEN2 CP / RL2 T2EX System clock TCLKP2

Mode1: 16-bit auto-reload Timer Timer2 can be programmed to count up or down when configured in its 16-bit auto-reload mode. This feature is invoked by the DCEN (Down Counter Enable) bit in T2MOD. After reset, the DCEN bit is set to 0 so that Timer2 will default to count up. When DCEN is set, Timer2 can count up or down, depending on the value of the T2EX pin. When DCEN = 0, two options are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer2 counts up to 0FFFFH and then sets the TF2 bit upon overflow. The overflow also causes the timer registers to be reloaded with the 16-bit value in RCAP2H and RCAP2L, which are pressed by software. If EXEN2 = 1, a 16-bit reload can be triggered either by an overflow or by a 1-to -0 transition at external input T2EX. This transition also sets the EXF2 bit. Both the TF2 and EXF2 bits can generate an interrupt if ET2 is enabled. TF2C/T2 The Block Diagram of Auto Relode Mode (Mode 1)of Timer2 (DCEN=0) RCAP2L RCAP2H EXF 0:Switch Off 1:Switch On Increment Mode 0:Switch Off 1:Switch On External Falling Edge flag TL2 TH2 T2EX Interrupt Request Overflow Flag TR2 EXEN2 System clock TCLKP2 ADC/ DAC At this point, TIMER2 overflow can trigger ADC (TRS[2:0] = 100) or DAC (IDACLSEL[2:0] = 001) began to convert data. Setting the DCEN bit enables Timer2 to count up or down. When DCEN = 1, the T2EX pin controls the direction of the count, and EXEN2’s control is invalid. A logical “1” at T2EX makes Timer2 count up. The timer will overflow at 0FFFFH and set the TF2 bit. This overflow also causes the 16-bit value in RCAP2H and RCAP2L to be reloaded into the timer registers, TH2 and TL2, respectively. A logical “0” at T2EX makes Timer2 count down. The timer underflows when TH2 and TL2 equal the values stored in RCAP2H and RCAP2L. The underflow sets the TF2 bit and causes 0FFFFH to be reloaded into the timer registers. The EXF2 bit toggles whenever Timer2 overflows or underflows and can be used as a 17th bit of resolution. In this operating mode, EXF2 does not flag an interrupt. TF2 TR2 C/T2 The Block Diagram of Auto-Reload Mode ( Mode 1) of Timer2 (DCEN=1) T2EX EXF2 Toggle 1.T2EX=1， Timer2 is up counter 2.T2EX=0， Timer2 is down counter TL2 TH2 RCAP2L RCAP2H FFH FFH 0:Switch Off 1:Switch On Overflow Flag Interrupt Request System clock TCLKP2 Note: in this mode and DCEN = 0, timer 2 count overflow can trigger ADC/DAC to begin the conversion, see the specific ADC/DAC.

Mode2:Programmable Clock Output To configure the Timer2 as a clock generator, bit C/T2 ——— must be cleared and bit T2OE must be set. Bit TR2 starts and stops the timer. In this mode T2 will output a 50% duty period clock: RCAP2L][RCAP2H,65536 SYSf 1FrequencyOutClock Timer2 overflow will not generate an interrupt, so it is possible to use Timer2 as a baud-rate generator and a clock output simultaneously with the same frequency. TR2 The Block Diagram of Programmable Clock output ( Mode 2 ) of Timer2 T2OE TL2 TH2 RCAP2L RCAP2H EXEN2 EXF2 0:Switch Off 1:Switch OnT2EX C/ T2 C/ T2 0:Switch Off 1:Switch On Timer2 Interrupt Request 0:Switch Off 1:Switch On System clock TCLKP2 Note: (1) Both TF2 and EXF2 can cause timer2 interrupt request, and they have the same vector address. (2) TF2 and EXF2 are set as 1 by hardware while event occurs. But they can also be set by software at any time. Only the software and the hardware reset will be able to clear TF2 & EXF2 to 0. (3) When EA = 1 & ET2 = 1, setting TF2 or EXF2 as 1 will cause a timer2 interrupt.

Table 8.36 Timer2 Control Register C8H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 T2CON TF2 EXF2 - - EXEN2 TR2 C/T ---- ---- CP/RL2 R/W R/W R/W - - R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) 0 0 - - 0 0 0 0 Bit Number Bit Mnemonic Description

7 TF2

0: No overflow (Must be cleared by software) 1: Overflow (Set by hardware)

6 EXF2

External event input (falling edge) from T2EX pin detected flag bit 0: No external event input (Must be cleared by software) 1: Detected external event input (Set by hardware if EXEN2 = 1)

3 EXEN2

External event input (falling edge) from T2EX pin used as Reload /Capture trigger enable/disable control bit 0: Ignore events on T2EX pin 1: Cause a capture or reload when a negative edge on T2EX pin is detected, when Timer 2 is not used to clock the EUART (T2EX always has a pull up resistor)

2 TR2

Timer2 start/stop control bit 0: Stop Timer2 1: Start Timer2

1 C/T2

——— Timer2 Timer/Counter mode selected bit 0: Timer Mode, T2 pin is used as I/O port 1: Counter Mode, the internal pull-up resister is turned on

0 CP/RL2

———— Capture/Reload mode selected bit 0: 16-bits timer/counter with reload function 1: 16-bits timer/counter with capture function Table 8.37 Timer2 Mode Control Register C9H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 T2MOD TCLKP2 - - - - - T2OE DCEN R/W R/W - - - - - R/W R/W Reset Value (POR/WDT/LVR/PIN) 0 - - - - - 0 0 Bit Number Bit Mnemonic Description

7 TCLKP2

0:Timer2 source is 1/12 prescale of system clock 1: Timer2 source is system clock

1 T2OE

0: Set P4.5/T2 as clock input or I/O port 1: Set P4.5/T2 as clock output (Baud-Rate generator mode)

0 DCEN

0: Disable Timer2 as up/down counter, Timer2 is an up counter 1: Enable Timer2 as up/down counter

Table 8.38 Timer2 Reload/Capture & Data Registers CAH-CDH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) 0 0 0 0 0 0 0 0 Bit Number Bit Mnemonic Description 7-0 RCAP2L[7:0] Timer2 Reload/Capturer Data RCAP2H[7:0] 7-0 TL2[7:0] Timer2 Low & High byte counter TH2[7:0]

8.8.3 Timer3

Timer3 is a 16-bit auto-reload timer. It is implemented as a 16-bit register accessed as two cascaded Data Registers: TH3 and TL3. It is controlled by the T3CON register. The Timer3 interrupt can be enabled by setting ET3 bit in IEN 1 register (Refer to Interrupt Section for details). Timer3 has only one operating mode: 16-bit Counter/Timer with auto-reload. Timer3 also supports the following features: selectable pre-scaler setting and Operation during CPU Power-Down mode. Timer3 consists of a 16-bit counter/reload register (TH3, TL3). When writing to TH3 and TL3, they are used as timer load register. When reading from TH3 and TL3, they are used as timer counter register. Setting the TR3 bit enables Timer 3 to count up. The Timer will overflow from 0xFFFF to 0x0000 and set the TF3 bit. This overflow also causes the 16-bit value written in timer load register to be reloaded into the timer counter register. Writing to TH3 also can cause the 16-bit value written in timer load register to be reloaded into the timer counter register. Read or write operation to TH3 and TL3 should follow these steps: Write operation: Low nibble first, High nibble to update the counter Read operation: High nibble first, Low nibble followed. TF3 The Block Diagram of Timer3 TL3 TH3 Increment Mode 0:Switch Off 1:Switch On 16-bit Counter Interrupt Request Overflow Flag TR3 System Clock Prescaler 1,8,64,256 T3PS[1:0] T3CLKS[1:0] Crystal 32.768kHz / RC 128KHz ADC/DAC If T3CLKS[1:0] is 00, Timer 3 can’t work in Power Down mode. If T3CLKS[1:0] is 01, Timer3 can work in Power Down mode. Even close all oscillator, Timer 3 can count. If T3CLKS[1:0] is 10, Timer3 can work in Power Down mode If low frequency oscillator is off, then Timer3 can not count. It can be described in the following table. T3CLKS[1:0] Oscillator status Can work in normal mode Can work in Power Down mode 00 - YES NO 01 - YES YES low frequency off in power-down YES NO low frequency on in power-down YES YES TIMER3 overflow can trigger ADC (TRS[2:0] = 110) or DAC (IDACLSEL[2:0] = 010) began to transform data. Note: (1) When TH3 and TL3 read or written, must make sure TR3 = 0. (2) When T3 is selected as Timer3 clock source and TR3 changes from 0 to 1, the first T3 down edge will be ignored. (3) Timer3 count overflow can trigger ADC/DAC to begin the conversion, see the specific ADC/DAC.

Table 8.39 Timer3 Control Register BBH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 T3CON TF3 - T3PS.1 T3PS.0 - TR3 T3CLKS.1 T3CLKS.0 R/W R/W - R/W R/W - R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) 0 - 0 0 - 0 0 0 Bit Number Bit Mnemonic Description

7 TF3

0: No overflow (cleared by hardware) 1: Overflow (Set by hardware) 5-4 T3PS[1:0] Timer3 input clock Prescaler Select bits 00: 1/1 01: 1/8 10: 1/64 11: 1/256

2 TR3

Timer3 start/stop control bit 0: Stop Timer3 1: Start Timer3 1-0 T3CLKS[1:0] Timer3 Clock Source select bits 00: System clock, T3 pin is used as I/O port 01: External clock from pin T3, auto pull-up 10: 32.768kHz from external Crystal or RC 128kHz (see code operation:OP_OSC) 11: reserved Table 8.40 Timer3 Reload/Counter Data Registers 89H-8AH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) 0 0 0 0 0 0 0 0 Bit Number Bit Mnemonic Description 7-0 TL3.x Timer3 Low & High byte counter, x = 0 - 7 TH3.x

8.9 Programmable counter array (PCAx (x = 0, 1, 2, 3))

8.9.1 Features

 PCA is a general purpose 16-bit Timer/Counter module, with two or three independent Output Compare Units, and with PWM support. PCA0, 2, 3 has two independent Output Compare Units, PCA1 has three independent Output Compare Units  Phase Correct PWM Mode  Phase frequency Correct PWM Mode Note: (1) A lower case“x” replaces PCA number, such as PCAx (x = 0, 1, 2, 3). The definitions are also used extensively throughout the document. (2) A lower case “n” replaces Compare Units number, such as P0CEXn (n = 0, 1, 2). The definitions are also used extensively throughout the document. The Programmable Counter Array (PCAx) provides enhanced timer functionality while requiring less CPU intervention than the standard 8051 counter/timers. The PCAx consists of a dedicated 16-bit counter/timer and two 16-bit capture/compare modules (PCA1 has three compare/capture modules), The PCA block diagram is shown in Figure8.9-1, Each capture/compare module has its own associated I/O line (PxCEXn (n = 0, 1, 2)). The counter/timer is driven by a programmable timebase that can select between eight sources: system clock, system clock divided by 4, system clock divided by 12, system clock divided by 32, the external oscillator clock source divided by 8, timer 2 overflow, an external clock signal on the ECI input pin or 32.768Khz crystal/built-in128kHzRC, The PxCPS2-PxCPS0 bits in the PxCMD register select the timebase for the counter/timer as shown in followingTable. PxCPS2 PxCPS1 PxCPS0 Clock Source 0 0 0 System clock 0 0 1 System clock divided by 4 0 1 0 System clock divided by 12 0 1 1 System clock divided by 32 1 0 0 Timer 2 overflow 1 0 1 The external oscillator clock source divided by 8 1 1 0 High-to-low transitions on ECI (max rate = system clock divided by 4 1 1 1 32.768Khz/built-in 128kHzRC Note: (1) External oscillator source divided by 8 is synchronized with the system clock. (2) Max rate value of timebse is System clock divided by 4 (except sytem clock as basetime), otherwise PCAx will not work well. (3) only when OP_OSC[3:0] = 1010 or 1101, can select external 32.768Khz crystal oscillator as timebase, when OP_OSC[3:0] = 0011 or 0110, can select built-in128Khz as timebase.

16 Bit Counter

Capture/Compare Cell 2 is only used by PCA1 Clock Select Sysclk Sysclk/12 Sysclk/4 TIMER2 ECIx Crystal/8 PxCPS2~0 PRx 32.768k/128k Sysclk/32 Capture/Compare Cell 1 Capture/Compare Cell 2 Overflow Figure 8.9-1 the schematic diagram of PCAx

Mode PxSDEN PxSMPn PxSMNn PxFSPn PxFSNn Function Mode0 0 0 0

0 X Capture triggered by positive edge (single slope)

1 0 Capture triggered by negative edge on (single slope) 1 1 Capture triggered by transition (single slope) Mode1 0 0 1

0 X Continuous software timer (single slope)

1 X Single software timer (single slope)

Mode2 0 1 0 X X frequency output (single slope) Mode3 1 1 0 0 8 bit PWM (single slope) 0 1 16 bit PWM (single slope) 1 1 0 16 bit phase correction PWM (dual ramp) 1 1 1 Phase frequency correction PWM (dual ramp) Others PCAx Counter correctly, but the compare/capture module does not work. X: Don’t Care; When PCAx Counter model work by its sigle-slope or dual -slope operation, Output Compare Units must be configured the same slope operation, otherwise Output Compare Units will not work. Note (used Output Compare Units): (1) To change the value of PxTOP must ensure that the new PxTOP value not less than the values of all the comparison register. (2) When compare/capture module work as 8-Bit Pulse Width Modulator, or 16-Bit Pulse Width Modulator, setting the PxCPHn equal to 0x00 or PxTOP will result in a constant high or low output (depending on the polarity of output set by the bit PxTCPn) (3) ALL Output Compare Units of PCAx must work in the same slope operation (example: PCA0 compare/capture module0 and compare/capture module1 can only work in the same slope mode). Table 8.41 summarizes the bit settings in the PxCPMn registers used to select the PCA capture/compare module’s operating modes, Setting the Px ECCFn bit in a PxCPMn register enables the module's PxCCFn interrupt. Note: PCAx interrupts must be globally enabled before individual PxCCFn interrupts are recognized. PCAx interrupts are globally enabled by setting the EA bit and the EPCAx bit to logic 1. See Figure 8.9-3. for details on the PCAx interrupt configuration. Capture/Compare Cell 0 PxCCF0 PxECCF0 PxECCF1 PCAx Counter Overflow CFx ECFx EPCAx EA Interrupt Request Capture/Compare Cell 1 PxCCF0 Capture/Compare Cell 2 PxCCF0 PxECCF2 Capture/Compare Cell 2 is only used by PCA1 Figure 8.9-3 PCAx Interrupt Block Diagram

8.9.2 Mode0: Edge-triggered Capture Mode

In this mode, a valid transition on the PxCEXn pin causes the PCAx to capture the value of the PCA counter/timer and load it into the corresponding module's 16-bit capture/compare register ( PxCPLn and PxCPHn ). The PxFSPn and PxFSNn bits in thePCAxCPMn register are used to select the type of transition that triggers the capture: low -to-high transition (positive edge trigger PxFSPn:PxFSNn = 0X ), high-to -low transition (negative edge trigger PxFSPn:PxFSNn = 10), or either transition (positive or negative edge trigger PxFSPn:PxFSNn = 11 ). When a capture occurs, the Capture/Compare Flag ( PxCCFn) in PCAxCF is set to logic 1 and an i nterrupt request is generated if PxCCFn interrupts are enabled. The PxCCFn bit is not automatically cleared by hardware when the CPU vectors to the interrupt service routine, and must be cleared by software. If both PxFSPn and PxFSNn bits are set to logic 1, then the state of the Port pin associated with PxTCPn can be read directly to determine whether a rising-edge or falling-edge caused the capture. PxCPHn PxCPLn PxCEXn PxFSPn PxFSNn PxCCFn PxSMPn PxSMNn PxECOMn PHx PLx Overflow Flag Interrupt Request CFx PxTOPH PxTOPL 16Bit Compare Clear Clock Select Sysclk Sysclk/12 Sysclk/4 TIMER2 ECIx Crystal/8 PxCPS2~0 PRx 32.768k Sysclk/32 Overflow Capture ADC PxTCPn Figure 8.9-4 PCAx Capture Mode Diagram Note: (1) ThePxCEXn input signal must remain high or low for at least 4 system clock periods to be recognized by the hardware. (2) The PCA1 compare/capture module 0 work in Edge-triggered Capture Mode ( positive edge trigger), you can start ADC conversion data(DACLSEL[2:0] = 111).

8.9.3 Mode1: Software Timer Mode

In Software Timer mode (PxSMPn: PxSMNn = 01, PxFSPn: PxFSNn = 0x), the PCA counter/timer value is compared to the module's 16-bit capture/compare register (PxCPHn and PxCPLn). When a match occurs, the Capture/Compare Flag (PxCCFn) in PCAxCF is set to logic 1 and an interrupt request is generated if PxCCFn interrupts are enabled. When PxTCPn = 1, the state of PxCEXn port pin can be changed. The PxCCFn bit is not automatically cleared by hardware when the CPU vectors to the interrupt service routine, and must be cleared by software. PxCPHn PxCPLn 16Bit Compare PxCCFn PxMATn PxCEXn Enable PxSMPn PxSMNn PxECOMn PxTCPn ADC PHx PLx Overflow Flag Interrupt Request CFx PxTOPH PxTOPL 16Bit Compare Clear Clock Select Sysclk Sysclk/12 Sysclk/4 TIMER2 ECIx Crystal/8 PxCPS2~0 PRx 32.768k Sysclk/32 Match Overflow Figure 8.9-5 Software Timer Mode Diagram PCA0 Set CFx flag bit, the nweTOP value and PxCPn value is loaded PxCEXn Set PxCCFn flag bit Figure 8.9-6 Software Timer Mode Principle Diagram Note: (1) The PCA0 compare/capture module 0 work in soft time MODE (TRS[2:0] = 011), a match occurs can Start ADC converstion Data (For detailed information refer to ADC Module.) (2) The PCA1 compare/capture module 1 work in soft time MODE (TRS[2:0] = 101), a match occurs can Start ADC converstion Data (For detailed information refer to ADC Module.) When PxFSPn: PxFSNn = 1x, compar e/capture module work in single trigger mode, by setting bit PxOSCn in PxFORCE register to generate single rising or falling edge. In addition, when compare/capture module work in soft time MODE, the match output of the comparator can beforced by writing the bit PxFCOn in PxFORCE register, Forcing compare match will not set the PxCCFn Flag or affect the register, but the state of PxCCFn pin will be changed as if a real compare match had occurred, when Forcing compare match occurred, the bit PxFCOn will be cleared by hardware.

8.9.4 Mode2: Frequency Output Mode

Frequency Output Mode produces a programmable-frequency square wave on the module’s associated PxCEXn pin. The capture/compare module high byte holds the number of PCA clocks to count before the output is toggled. The square wave frequency FPxCEXn = FPCAx/(2 X PxCPHn) Note: A value of 0x00 in the PxCPHn register is equal to 256 for this equation. Where FPCAx is the frequency of the clock selected by the CPS2-0 bits in the PCAx register The following figure 8 .9-7, The lower byte of the capture/compare module is compared to the PCA counter low byte; on a match, PxCEXn pin is toggled and the offset held in the high byte (PxCPHn) is added to the matched value in PxCPLn.In this mode, PxTOPL value is fixed 0Xff, but PxTOPH can be configured. PxCPLn 8Bit Compare 8Bit Adder PxCPHn PxCEXnMatch Enable Enable PxSMPn PxSMNn PxECOMn PLx PxTOPL 8Bit Compare Clear Clock Select Sysclk Sysclk/12 Sysclk/4 TIMER2 ECIx Crystal/8 PxCPS2~0 PRx 32.768k Sysclk/32 PLx Overflow Figure 8.9-7 PCA Frequency Output Mode

8.9.5 Mode3: PWM Mode

Each PCAx module can be used independently to generate a pulse width modulated (PWM) output. The following Table summarizes the bit (PxFSPn, PxFSNn) settings in the PxCPMn registers used to select the PCA capture/compare module’s operating PWM modes. PxFSPn PxFSNn Function 0 0 8 bit PWM (single slope)) 0 1 16 bit PWM (single slope) 1 0 16 bit phase correction PWM (dual ramp) 1 1 16 bit phase frequency correction PWM (dual ramp) 8-Bit Pulse Width Modulator function When compare/capture module work in 8-bit Pulse Width Modulator (single slope), the value PLx in the low byte of the PCA counter/timer incremented from 0x00 to PxTOPL, when the counter/timer PLx overflows from 0Xff to 0x00, PxCPLn is reloaded automatically with the value stored in the module’s capture/compare high byte (PxCPHn) without software intervention. In this mode,PxTOPL value is fixed 0Xff, but PxTOPH can be configured. PxCPLn 8Bit CompareEnable PxCPHn PxCEXn Match Q Q SET CLR S R Reload PxFSPn PxFSNn PxSMPn PxSMNn PxECOMn PxCCFn PxMATn PxTCPn PLx Interrupt Request PxTOPL 8Bit Compare Clear Clock Select Sysclk Sysclk/12 Sysclk/4 TIMER2 ECIx Crystal/8 PxCPS2~0 PRx 32.768k Sysclk/32 PLx Overflow Figure 8.9-8 PCA 8-Bit PWM Mode Diagram The duty cycle of the PWM output signal is varied using the module's PxCPHn capture/compare register. ( in this mode, PxCPHn register is not double buffered) when PxTCPn = 0, When the value in the low byte of the PCA counter/timer (PLx) is equal to the value in PxCPLn, the output on the PxCEXn pin will be cleared. When the count value in PLx overflows, the PxCEXn output will be set. when PxTCPn = 1, the output on the PxCEXn pin will be opposite polarity. The duty cycle for 8-Bit PWM Mode is given by Equation Duty = (256-(PxCPHn+1))/256.

The dual-slope operation has lower maximum operation frequency than single slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. The PWM resolution for the phase correct PWM mode can be configured by PxTOP. The minimum resolution allowed is 2-bit (PxTOP set to 0x003), and the maximum resolution is 16 -bit. The PWM resolution in bits can be calculated by using the following equation: RPxXPWM = log (PxTOP+1)/log(2). In phase correct PWM mode the counter is incremented until the counter value matches the value in PxTOP. The counter has then reached the TOP and changes the count direction.The PCAx counter value will be equal to TOP for one time clock cycle, then the PxTOP and PxCPn value will be update. The timing diagram for the phase correct PWM mode is shown on Figure 8.9-13. Since the PxTOP and PxCPn update occurs at TOP, the PWM period starts and ends at TOP. In this mode, PxTOP and PxCPHn register is double buffered, Change PxTOP and PxCPHn register value without affecting the value PxTOP and PxCPn in currernt time clock cycle . Cycle 1 2 3 4 5 PxCEXn PxCEXn PCAx Counter set PxCCFn flag bit PxTOP, PxCPn update set CFx flag bit 1 6 7 Figure 8.9-13 16 bit XPWM Waveform It is recommended to use the phase and frequency correct mode instead of the phase correct mode when changing the TOP value while the Timer/Counter is running. When using a static TOP value there are practically no differences between the two modes of operation. The PWM frequency FPxXPWM = fsysclk/2 X PxTOP The 16 phase and frequency correct pulse width modulator (XPPWM16) mode The phase and frequency correct Pulse Width Modulation, or phase and frequency correct PWM mode provides a high resolution phase and frequency correct PWM waveform generation option. The phase and frequency correct PWM mode is, like the phase correct PWM mode, based on a dual-slope operation. The counter counts repeatedly from BOTTOM (0x0000) to TOP (PxTOP) and then from TOP (PxTOP) to BOTTOM (0x0000). When PxTCPNn = 0, the Output of PxCEXn pin is cleared on the compare match between PCAx counter and PxCPn while upcounting, and set on the compare match while downcounting. When PxTCPn = 1, the output is inverted. when a match occurs, the Capture/Compare Flag (PxCCFn) in PxCF is set to logic 1 and an interrupt request is generated if interrupts are enabled. when the counter counts from PxTOP to 0x0000 overflow, the Flag CFx in PxCF is set to logic 1 and an interrupt request is generated if interrupts are enabled. PxCPHn PxCPLn PHx PLx 16Bit CompareEnable Match Interrupt Request PxMATn 0x0000 PxTOP CFx PxFSPn PxFSNn PxSMPn PxSMNn PxECOMn PxCEXn PxTCPn PxCCFn 16Bit Compare Clock Select Sysclk Sysclk/12 Sysclk/4 TIMER2 ECIx Crystal/8 PxCPS2~0 PRx 32.768k Sysclk/32 Q Q SET CLR S R Frigue 8.9-14 16 bit phase and frequency correct mode

The dual-slope operation has lower maximum operation frequency than single slope operation.However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. The main difference between the phase correct, and the phase and frequency correct PWM mode is the time the PxTOP and PxCPn Register is updated by the PxTOP and PxCPn Buffer Register (see figure 8 .9-13 and figure 8.9-15). in contrast to the phase correct mode, symmetrical in all periods. Since the PxTOP and PxCPn Registers are updated at BOTTOM, the length of the rising and the falling slopes will always be equal. This gives symmetrical output pulses and is therefore frequency correct. Figure 8.9-15. Phase and Frequency Correct PWM Mode, Timing Diagram, if the base PWM frequency is actively changed by changing the TOP value, using the PxCPn is clearly a better choice due to its double buffer feature. Cycle 1 2 3 4 5 PxCEXn PxCEXn PCAx Counter Set PxCCFn flag bit 1 6 7 Set CFx flag bit , PxTOP, PxCPn update Frigue 8.9-15 16 bit XPPWM Waveform The PWM resolution for the phase correct PWM mode can be configured by PxTOP. The minimum resolution allowed is 2-bit (PxTOP set to 0x003), and the maximum resolution is 16-bit. FPxXPPWM = fsysclk/2 X PxTOP Duty = (PxTOP-PxCPn+)/PxTOP

8.9.6 Register

Table 8.41 PCAx Flag Register (Bank1) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 P0CF (98H) CF0 - - - - - P0CCF1 P0CCF0 P1CF (C8H) CF1 - - - - P1CCF2 P1CCF1 P1CCF0 P2CF (E8H) CF2 - - - - - P2CCF1 P2CCF0 P3CF (F8H) CF3 - - - - - P3CCF1 P3CCF0 R/W R/W - - - - R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) 0 - - - - 0 0 0 Bit Number Bit Mnemonic Description

7 CFx

PCAx Counter/Timer Overflow Flag Set by hardware when the PCAx Counter/Timer overflows from 0xFFFF to 0x0000. When the Counter/Timer Overflow (CFx) interrupt is enabled, setting this bit causes the CPU to jump to the PCA interrupt service routine. This bit is not automatically cleared by hardware and must be cleared by software.

2 P1CCF2

PCA Module 2 Capture/Compare Flag This bit is set by hardware when a match or capture occurs. When the P1CCF2 interrupt is enabled, setting this bit causes the CPU to jump to the PCA x interrupt service routine. This bit is not automatically cleared by hardware and must be cleared by software.

1 PxCCF1

PxCCF1: Module 1 Capture/Compare Flag This bit is set by hardware when a match or capture occurs. When the P1CCF 1 interrupt is enabled, setting this bit causes the CPU to jump to the PCA x interrupt service routine. Th is bit is not automatically cleared by hardware and must be cleared by software.

0 PxCCF0

PxCCF0: PCAx Module0 Capture/Compare Flag This bit is set by hardware when a match or capture occurs. When the P xCCFx interrupt is enabled, setting this bit causes t he CPU to jump to the PCA x interrupt service routine. This bit is not automatically cleared by hardware and must be cleared by software. Table 8.42 PCA Enable Register D8H (Bank1) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PCACON - - - - PR3 PR2 PR1 PR0 R/W - - - - R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) - - - - 0 0 0 0 Bit Number Bit Mnemonic Description

3 PR3

PCA3 counter/timer run control 0: PCA3 counter/timer disable 1: PCA3 counter/timer enable

2 PR2

PCA2 counter/timer run control 0: PCA2 counter/timer disable 1: PCA2 counter/timer enable

1 PR1

PCA1counter/timer run control 0: PCA1counter/timer disable 1: PCA1 counter/timer enable

0 PR0

PCA0counter/timer run control 0: PCA0 counter/timer disable 1: PCA0 counter/timer enable

Table 8.43 PCAx Mode Register (Bank1) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 P0CMD (99H) ECF0 P0SDEN - - - P0CPS2 P0CPS1 P0CPS0 P1CMD (C9H) ECF1 P1SDEN - - - P1CPS2 P1CPS1 P1CPS0 P2CMD (E9H) ECF2 P2SDEN - - - P2CPS2 P2CPS1 P2CPS0 P3CMD (F9H) ECF3 P3SDEN - - - P3CPS2 P3CPS1 P3CPS0 R/W R/W R/W - - - R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) 0 0 - - - 0 0 0 Bit Number Bit Mnemonic Description

7 ECFx

PCAx counter/timer overflow interrupt enable bit 0: CFx interrupt disable 1: when CFx is set, the PCAx counter/timer overflow interrupt request is permissed. The bit is PCAx counter/timer overflow (CFx) interrupt mask bit

6 PxSDEN

Single/dual ramp select bit 0: PCAx works in a single edge mode, at this time double slope mode of other capture module for PCAx is prohibited 1: PCAx work in the double edge mode, at this time single slope mode of other capture module for PCAx is prohibited

2 PxCPS2 PCAx counter/timer clock select

These bits to select t he PCAx counter clock source. For details please refer to table XXX

1 PxCPS1

0 PxCPS0

Table 8.44 PxCPMn: PCA Capturre/Compare Register (Bank1) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 P0CPM0(9AH) P0SMP0 P0SMN0 P0FSP0 P0FSN0 P0ECOM0 P0TCP0 P0MAT0 P0ECCF0 P0CPM1(9BH) P0SMP1 P0SMN1 P0FSP1 P0FSN1 P0ECOM1 P0TCP1 P0MAT1 P0ECCF1 P1CPM0(CAH) P1SMP0 P1SMN0 P1FSP0 P1FSN0 P1ECOM0 P1TCP0 P1MAT0 P1ECCF0 P1CPM1(CBH) P1SMP1 P1SMN1 P1FSP1 P1FSN1 P1ECOM1 P1TCP1 P1MAT1 P1ECCF1 P1CPM2(D1H) P1SMP2 P1SMN2 P1FSP2 P1FSN2 P1ECOM2 P1TCP2 P1MAT2 P1ECCF2 P2CPM0(EAH) P2SMP0 P2SMN0 P2FSP0 P2FSN0 P2ECOM0 P2TCP0 P2MAT0 P2ECCF0 P2CPM1(EBH) P2SMP1 P2SMN1 P2FSP1 P2FSN1 P2ECOM1 P2TCP1 P2MAT1 P2ECCF1 P3CPM0(FAH) P3SMP0 P3SMN0 P3FSP0 P3FSN0 P3ECOM0 P3TCP0 P3MAT0 P3ECCF0 P3CPM1(F2H) P3SMP1 P3SMN1 P3FSP1 P3FSN1 P3ECOM1 P3TCP1 P3MAT1 P3ECCF1 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) 0 0 0 0 0 0 0 0 (to be continued)

(continue) Bit Number Bit Mnemonic Description

7 PxSMPn

00: capture 01:software timer 10:frequency output 11:PWM output For details please refer to table XXXX

6 PxSMNn

5 PxFSPn

PxSMPn:PxSMNn = 00: capture mode select 0X: The compare/capture module n work in the positive edge triggered mode 10: The compare/capture module n work in the negative edge triggered mode 11: The compare/capture module n work in any edge triggered mode PxSMPn: PxSMNn =10:capture mode select 0X: continuous software timer mod 1X: single software timing mode PxSMPn:PxSMNn = 11: PWM mode select 00: select 8 bit PWM mode 01: select 16 bit PWM mode 10 :select the 16 bit phase correction of PWM mode 11: select the 16 bit phase frequency of PWM mode When PxSMPn:PxSMNn = 10 (frequency output mode) this bit is invalid.

4 PxFSNn

3 PxECOMn

Compare/capture module functions enable bit 0: compare/capture module n disable 1: compare/capture module n enable

2 PxTCPn

When PxSMPn:PxSMNn = 00, the bit is the indicator of signal edge captured 0: PxCEXn pin is low 1: PxCEXn pin is high When PxSMPn:PxSMNn = 01, the bit is waveform output control bit 0: PxCEXn pin doesnot output software waveform 1: PxCEXn pin allows the software waveform output When PxSMPn:PxSMNn = 11, the bit is PWM output from anti - enable bit 0: PWM Normal output waveform (Duty low active) 1: PWM reverse output waveform (Duty high effective)

1 PxMATn

0: don’t set up matching flag of corresponding module 1: set up matching flag of corresponding module

0 PxECCFn

Capture/compare flag interrupt enable bit 0: PxCCFn interrupt disable 1: when the PxCCFn bit is set to '1', capture/compare flag interrupt request is allowed

Table 8.45 PxFORCE Forced Output Control Register (Bank1) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 P0FORCE (DCH) - - P0OSC1 P0OSC0 - - P0FCO1 P0FCO0 P1FORCE (DDH) - P1OSC2 P1OSC1 P1OSC0 - P1FCO2 P1FCO1 P1FCO0 P2FORCE (DEH) - - P2OSC1 P2OSC0 - - P2FCO1 P2FCO0 P3FORCE (DFH) - - P3OSC1 P3OSC0 - - P3FCO1 P3FCO0 R/W - R/W R/W R/W - R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) - 0 0 0 - 0 0 0 Bit Number Bit Mnemonic Description

6 PxOSC2

PxCEX2 output registers of Module2, the bit is effective only when the PxSMPn:PxSMNn = 01 and PxFSPn:PxFSNn = 1x write '0' to this bit, PxCEX2 pin output high level, when the compare match, PxCEX2 pin is pulled low write '1' to this bit, PxCEX2 pin output low level, when the compare match, PxCEX2 pin is set to high

5 PxOSC1

PxCEX1 output registers of Module1,the bit is effective only when the PxSMPn:PxSMNn = 01 and PxFSPn:PxFSNn = 1x write '0' to this bit , PxCEX1 pin output high level , when the compare match, PxCEX1 pin is pulled low write '1' to this bit , PxCEX1pin output low level , when the compare match, PxCEX1pin is pulled high

4 PxOSC0

PxCEX0 output registers of Module0, the bit is effective only when the PxSMPn:PxSMNn = 01 and PxFSPn:PxFSNn = 1x Write '0' to this bit , PxCEX0 pin output high level, when the compare match, PxCEX0 pin is pulled low Write '1' to this bit , PxCEX0 pin output low level , when the comp are match, PxCEX0 pin is pulled high

2 PxFCO2

Module2 mandatory matching control bit (the bit is effective only when PxSMPn:PxSMNn = 01) 0: does not enable forced match, 1: enable forced matching, hardware automatically cleared after matching

1 PxFCO1

Module1 mandatory matching control bit (the bit is effective only when PxSMPn:PxSMNn = 01) 0: does not enable forced match, 1: enable forced matching, hardware automatically cleared after matching

0 PxFCO0

Module0 mandatory matching control bit (the bit is effective only when PxSMPn:PxSMNn = 01) 0: does not enable forced match, 1: enable forced matching, hardware automatically cleared after matching

Table 8.46 PCAx Count Maximum Low Byte (Bank1) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) 1 1 1 1 1 1 1 1 Bit Number Bit Mnemonic Description 7-0 PxTOPL.y (x = 0-3,y = 0-7) PxTOPL:PCAx TOP defines LOW byte(LSB) Table 8.47 PCAx Count Maximum High Byte (Bank1) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 R/W R/W/R/W R/W R/W R/W R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) 1 1 1 1 1 1 1 1 Bit Number Bit Mnemonic Description 7-0 PxTOPH.y (x = 0-3,y = 0-7) PxTOPH:PCAx TOP defines high byte (MSB)

Table 8.48 PCAx Capture/Compare Module Low Byte (Bank1) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) 0 0 0 0 0 0 0 0 Bit Number Bit Mnemonic Description 7-0 PxCPLn （x = 0-3,n = 0,1） PxCPLn: PCAx capture/compare module low byte PxCPLn register retains low byte of 16 bit capture module n (LSB) Table 8.49 PCAx Capture/Compare Module High Byte (Bank1) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) 0 0 0 0 0 0 0 0 Bit Number Bit Mnemonic Description 7-0 PxCPHn （x = 0-3,n = 0,1） PxCPHn: PCAx capture/compare module high byte PxCPHn register retains high byte of 16 bit capture module (MSB)

8.10 Interrupt

8.10.1 Features

 24 interrupt sources  4 interrupt priority levels

8.10.2 Description

The SH88F6161/SH88F6162 provides total 24 interrupt sources: 10 External interrupts (External interrupt2/3/40-47), 2 timer interrupts (Timer2, 3), 4 PCA interrupts (PCA0/1/2/3), 1 TWI interrupt, 1 EUART0 interrupt, 1 EUART1 interrupt, ADC interrupt, DAC interrupt, SPI interrupt, SCM interrupt and USB interrupt.

8.10.3 Interrupt Enable Control

Each interrupt source can be individually enabled or disabled by setting or clearing the corresponding bit in the interrupt enable registers IEN0 or IEN1. The IEN0 register also contains global interrupt enable bit, EA, which can enable/disable all the interrupts at once. Generally, after reset, all interrupt enable bits are set to 0, which means that all the interrupts are disabled. Table 8.50 Primary Interrupt Enable Register A8H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 IEN0 EA EADC ET2 ES0 EPCA3 EPCA2 EPCA1 EPCA0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) 0 0 0 0 0 0 0 0 Bit Number Bit Mnemonic Description 7 EA All interrupt enable bit 0: Disable all interrupt 1: Enable all interrupt

6 EADC

0: Disable ADC interrupt 1: Enable ADC interrupt

5 ET2

Timer2 overflow interrupt enable bit 0: Disable Timer2 overflow interrupt 1: Enable Timer2 overflow interrupt

4 ES0

EUART interrupt enable bit 0: Disable EUART0 interrupt 1: Enable EUART0 interrupt

3 EPCA3

0: Disable PCA3 interrupt 1: Enable PCA3 interrupt

2 EPCA2

0: Disable PCA2 interrupt 1: Enable PCA2 interrupt

1 EPCA1

0: Disable PCA1interrupt 1: Enable PCA1interrupt

0 EPCA0

0: Disable PCA0 interrupt 1: Enable PCA0 interrupt

Table 8.51 Secondary Interrupt Enable Register A9H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 IEN1 ESCM/ELPD ES1 EUSB/ETWI ET3 EX4 EX3 EX2/EDAC ESPI R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) 0 0 0 0 0 0 0 0 Bit Number Bit Mnemonic Description

7 ESCM/ELPD

0: Disable SCM/ LPD interrupt 1: Enable SCM/LPD interrupt

6 ES1

EUART interrupt enable bit 0: Disable EUART1 interrupt 1: Enable EUART1 interrupt

5 EUSB/ETWI

USB/TWI interrupt enable bit 0: Disable USB/TWI interrupt 1: Enable USB/TWI interrupt

4 ET3

Timer3 overflow interrupt enable bit 0: Disable Timer3 overflow interrupt 1: Enable Timer3 overflow interrupt

3 EX4

External interrupt4 enable bit 0: Disable INT4 interrupt 1: Enable INT4 interrupt

2 EX3

External interrupt3 enable bit 0: Disable INT3 interrupt 1: Enable IN T3 interrupt

1 EX2/EDAC

External interrupt2/DAC enable bit 0: Disable INT2/DAC interrupt 1: EnableINT2/DAC interrupt

0 ESPI

0: Disable SPI interrupt 1: Enable SPI interrupt Table 8.52 Interrupt channel Enable Register1 C3H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 IENC EXS47 EXS46 EXS45 EXS44 EXS43 EXS42 EXS41 EXS40 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) 0 0 0 0 0 0 0 0 Bit Number Bit Mnemonic Description 7-0 EXS4x (x = 0-7) External interrupt4 channel select bit (x = 0-7) 0: Disable External interrupt4x 1: Enable External interrupt4x

8.10.4 Interrupt Flag

Each Interrupt source has its own interrupt flag, when interrupt occurs, corresponding flag will be set by hardware, the interrupt flag bits are listed in Table bellow. For external interrupt (INT0/1/2/3), when an external interrupt0/1/2/3 is generated, if the interrupt was edge trigged, the flag (IE0-3 in EXF0) that generated this interrupt is cleared by hardware when the service routine is vectored. If the interrupt was level trigged, then the requesting external source directly controls the request flag, rather than the on-chip hardware. When an external interrupt4 is generated, the flag (IF4x (x = 0-7) in EXF1 register) that generated this interrupt should be cleared by user’s program because the same vector entrance was used in INT4. But if INT4 is setup as level trigged, the flag can’t be cleared by user’s program, it only be controlled by peripheral signal level that connect to INT source pin. The EUART0 interrupt is generated by the logical OR of flag RI and TI in SCON register, which is set by hardware. Neither of these flags can be cleared by hardware when the service routine is vectored. In fact, the service routine will normally have to determine whether it was the receive interrupt flag or the transmission interrupt flag that generated the interrupt, so the flag must be cleared by software. The EUART1 interrupt is generated by the logical OR of flag RI1 and TI 1in SCON register, which is set by hardware. Neither of these flags can be cleared by hardware when the service routine is vectored. In fact, the service routine will normally have to determine whether it was the receive interrupt flag or the transmission interrupt flag that generated the interrupt, so the f lag must be cleared by software. The Timer2 interrupt is generated by the logical OR of flag TF2 and bit EXF2 in T2CON register, which is set by hardware. None of these flags can be cleared by hardware when the service routine is vectored. so the flag must be cleared by software. The Timer3 interrupt is generated when they overflow, the flag TF3 in T3CON register, which is set by hardware, and will be automatically cleared by hardware when the service routine is vectored. The PCAx interrupt is generated by setting PCAx counting overflow flag (CFx, x = 0, 1, 2, 3). Also, the matching or triggering event of each compare/capture module will cause the PxCCFn (n = 0, 1, 2) bit set and PCAx interrupt generated, After the CPU response to the interrupt, the flags should be cleared by software, which cannot be cleared by hardware. The ADC interrupt is generated by ADCIF bit in ADCON1,ACLIF bit and ACGIF in ADCON2. If continuous compare function in ADC module is Enable, ADCIF , ACLIF, ACGIF will not be set at each conversion, but set if converted result is larger than compare value. The flag must be cleared by software. The SPI interrupts are generated by SPIF in SPSTA or set MODF. The flags can be cleared by software. The SCM interrupt is generated by SCMIF in SCM register, which is set by hardware. And the flag can only be cleared by hardware. The TWI interrupts are generated by TWINT in TWICON. The flags can be cleared by software. The USB interrupts are generated by setting the relative flags of the USB. The flags must be cleared by software. (Refer to the USB section for the details of the relative flags) The DAC interrupts are generated by DACIFT in DACCON0. The flags can be cleared by software. The LPD interrupt is generated with LPDIF set when the power voltage is lower than the value set in LPDCON (LPDS[3:0]) register, LPDIF should be cleared by software. Table 8.53 External Interrupt 0/1 Control Register 88H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) 0 0 0 0 0 0 0 0 Bit Number Bit Mnemonic Description 7-6 IT4[1:0] External interrupt4 trigger mode selection bits 00: Low Level trigger 01: Trigger on falling edge 10: Trigger on rising edge 11: Trigger on both edge IT4 [1:0] is effect on external interrupt 4x at the same mode (to be continued)

(continue) 5-4 IT3[1:0] External interrupt3 trigger mode selection bits 00: Low Level trigger 01: Trigger on falling edge 10: Trigger on rising edge 11: Trigger on both edge 3-2 IT2[1:0] External interrupt2 trigger mode selection bits 00: Low Level trigger 01: Trigger on falling edge 10: Trigger on rising edge 11: Trigger on both edge

1 IE3

External interrupt3 request flag bit 0: No interrupt pending 1: Interrupt is pending

0 IE2

External interrupt2 request flag bit 0: No interrupt pending 1: Interrupt is pending Table 8.54 External Interrupt Flag Register1 D8H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 EXF1 IF47 IF46 IF45 IF44 IF43 IF42 IF41 IF40 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) 0 0 0 0 0 0 0 0 Bit Number Bit Mnemonic Description 7-0 IF4x （x = 0-7） External interrupt4 request flag bit 0: No interrupt pending 1: Interrupt is pending IF4x is cleared by software

8.10.5 Interrupt Vector

When an interrupt occurs, the program counter is pushed onto the stack and the corresponding interrupt vector address is loaded into the program counter. The interrupt vector addresses are listed in Interrupt Summary table.

8.10.6 Interrupt Priority

Each interrupt source can be individually programmed to one of four priority levels by setting or clearing corresponding bits in the interrupt priority control registers IPL0, IPH0, IPL1, and IPH1. But the OVL NMI interrupt has the highest Priority Level (except RESET) of all the interrupt sources, with no IPH/IPL control. The interrupt priority service is described below. An interrupt service routine in progress can be interrupted by a higher priority interrupt, but can not by another interrupt with the same or lower priority. The highest priority interrupt service cannot be interrupted by any other interrupt source. If two requests of different priority levels are received simultaneously, the request of higher priority level is serviced. If requests of the same priority level are pending at the start of an instruction period, an internal polling sequence determ ines which request is serviced. Interrupt Priority Priority bits Interrupt Lever Priority IPHx IPHx 0 0 Level 0 (lowest priority) 0 1 Level 1 1 0 Level 2 1 1 Level 3 (highest priority)

Table 8.55 Interrupt Priority Control Registers B8H,B4H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 IPL0 - PADCL PT2L PS0L PPCA3L PPCA2L PPCA1L PPCA0L IPH0 - PADCH PT2H PS0H PPCA3H PPCA2H PPCA1H PPCA0H R/W - R/W R/W R/W R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) - 0 0 0 0 0 0 0 B9H,B5H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 IPL1 PSCM/LPDL PS1L PUSB/TWIL PT3L PX4L PX3L PX2DACL PSPIL IPH1 PSCM/LPDH PS1H PUSB/TWIH PT3H PX4H PX3H PX2DACH PSPIH R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) 0 0 0 0 0 0 0 0 Bit Number Bit Mnemonic Description 7-0 PxxxL/H Corresponding interrupt source xxx’s priority level selection bits

8.10.7 Interrupt Handling

The interrupt flags are sampled and polled at the fetch period of each machine period. All interrupts are sampled at the risi ng edge of the clock. If one of the flags was set, the CPU will find it and the interrupt system will generate a LCALL to the appropriate service routine, provided this hardware-generated LCALL is not blocked by any of the following conditions: An interrupt of equal or higher priority is already in progress. The current period is not in the final period of the instruction in progress. This ensures that the instruction in progress is completed before vectoring to any service routine. The instruction in progress is RETI. This ensures that if the instruction in progress is RETI then at least one more instr uction except RETI will be executed before any interrupt is vectored to; this delay guarantees that the CPU can observe the changes of the interrupt status. Note: Since priority change normally needs 2 instructions, it is recommended to disable corresponding Interrupt Enable flag to avoid interrupt between these 2 instructions during the change of priority. If the flag is no longer active when the blocking condition is removed, the denied interrupt will not be serviced. Every poll ing period interrogates only the valid interrupt requests. The polling period/LCALL sequence is illustrated below: Interrupt Latched Interrupt Polled Long Call to Interrupt Vector Service Interrupt service Cn+8C2C1 Interrupt Pending Interrupt Signal Generated C3~Cn Cn~Cn+7 Interrupt Response Timing The hardware-generated LCALL pushes the contents of the program counter onto the stack (but it does not save the PSW) and reloads the program counter with corresponding address that depends on the source of the interrupt being vectored too, as shown in Interrupt Summary table. Interrupt service execution proceeds from that location until the RETI instruction is encountered. The RETI instruction informs the processor that the interrupt routine is no longer in progress, and then pops the top two bytes from the stack and reloads the program counter. Execution of the interrupted program continues from the point where i t was stopped. Note that the RETI instruction is very important because it informs the processor that the program left the current interrupt service. A simple RET instruction would also have returned execution to the interrupted program, but it would have left the interrupt control system thinking an interrupt with this priority was still in progress. In this case, no interrupt of the same or lower priority level would be acknowledged.

8.10.8 Interrupt Response Timing

If an interrupt is recognized, its request flag is set in every machine period after recognize. The value will be polled by the circuitry until the next machine period; the CPU will generate an interrupt at the third machine period. If the request is active and conditions are right for it to be acknowledged, hardware LCALL to the requested service routine will be the next instruction to be executed. Else the interrupt will pending. The call itself takes 7 machine periods. Thus a minimum of 3+7 complete machine periods will elapse between activation and external interrupt request and the beginning of execution of the first instruction of the service routine. A longer response time would be obtained if the request was blocked by one of the above three previously listed conditions. If an interrupt of equal or higher priority is already in progress, the additional wait time obviously depends on the nature of the other interrupt’s service routine. If the instruction in progress is not in its final period and the instruction in progress is RETI, the additional wait time is 8 machine periods. For a single interrupt system, if the next instruction is 20 machine periods long (the longest instructions DIV & MUL are 20 machine periods long for 16-bit operation), adding the LCALL instruction 7 machine peri ods the total response time is 2+8+20+7 machine periods. Thus interrupt response time is always more than 10 machine periods and less than 37 machine periods. System clock is selected as interrupt sequence sample clock.Sample times and clock frequency division for sequence sample can be set through EXCON register. Table 8.56 External Interrupt Sampling Register C2H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) 0 0 0 0 0 0 0 0 Bit Number Bit Mnemonic Description 7-6 EXT4FS[1:0] External interrupt INT4x frequency division for sample time select bit (x = 0-7) 00:1 01:1/4 10:1/16 11:1/64 5-4 I4P[1:0] External interrupt INT41x sequence sample times select bit (x = 0-7) 00:1 01:2 10:3 11:4 3-2 EXTFS [1:0] External interrupt INT2/3 frequency division for sample time select bit 00:1 01:1/4 10:1/16 11:1/64 1-0 IP[1:0] External interruptINT2/3 sequence sample times select bit 00:1 01:2 10:3 11:4

8.10.9 External Interrupt Input

The SH88F6161/SH88F6162 has 10 external interrupt inputs. External interrupt 2-3 each has one vector address. External interrupt 4 has 8 inputs; all of them share one vector address . These external interrupts can be programmed to be level-triggered or edge-triggered by clearing or setting bit IT2 or IT3 in register EXF0 .If ITn = 0 0 (n = 2, 3), external interrupt 2/3 is triggered by a low level detected at the INT2/3 pin. If ITn (n = 2, 3) = 01, external interrupt INTx (x = 2, 3) is edge triggered. In this mode if consecutive samples of the INTx (x = 2, 3) pin show a high level in one period and a low level in the next period, interrupt request flag in register EXF1 is set, causing an interrupt request. Since the external interrupt pins are sampled once each machine period, an input high or low level should be held for at least one machine period to ensure proper sampling. If the external interrupt is edge-triggered, the external source has to hold the request pin high for at least one machine period, and then hold it low for at least one machine period. This is to ensure that the transition is detected and that interrupt re quest flag is set. Note that IE0-1 is automatically cleared by CPU when the service routine is called while IF4x should be cleared by software. External interrupt4 operates in the similar ways except have different registers and have more selection of trigger. If the external interrupt is level -triggered, the external source must hold the request active until the requested interrupt is generated, which will take 2 machine periods. If the external interrupt is still asserted when the interrupt service routine is completed, another interrupt will be generated. It is not necessary to clear the interrupt flag IEx (x = 2, 3) when the interrupt is level sensitive, it simply tracks the input pin level. If an external interrupt is enabled when the SH88F6161/SH88F6162 is put into Power down or Idle mode, the interrupt occurrence will cause the processor to wake up and resume operation. Note: IE2/3 is automatically cleared by CPU when the service routine is called while IF40-47 should be cleared by software. Sampling Cyle > SN Sampling Cycle High-Level Threshold Low-Level Threshold Low-Level Threshold >SN Sampling Cycle (SN=1,2,3,4 sys,sys/4,sys/16,sys/64) (SN=1,2,3,4 sys,sys/4,sys/16,sys/64) (SN=1,2,3,4 sys,sys/4,sys/16,sys/64) External Interrupt Detecting

8.10.10 Interrupt Summary

Source Vector Address Enable bits Flag bits Polling Priority Interrupt No. (C51) Reset 0000H - - 0 (higest) - PCA0 0003H EPCA0 CF0/P0CCF0/P0CCF1 1 0 PCA1 000BH EPCA1 CF1/P1CCF0/P1CCF1/P1CCF2 2 1 PCA2 0013H EPCA2 CF2/P2CCF0/P2CCF1 3 2 PCA3 001BH EPCA3 CF3/P3CCF0/P3CCF1 4 3 EUART0 0023H ES0 RI+TI 5 4 Timer2 002BH ET2 TF2+EXF2 6 5 ADC 0033H EADC ADCIF/ACLIF/ACGIF 7 6 SPI 003BH ESPI SPIF 8 7 INT2/DAC 0043H EX2/EDAC IE2/DACIF 9 8 INT3 004BH EX3 IE3 10 9 INT4 0053H EX4+IENC IF47-IF40 11 10 Timer3 005BH ET3 TF3 12 11 USB/TWI 0063H EUSB/ETWI USBIF/TWINT 13 12 EUART1 006BH ES1 RI1/TI1 14 13 SCM/LPD 0073H ESCM/ELPD SCMIF/LPDIF 15 14

1. Enhanced Function

9.1 Regulator

9.1.1 Features

 Stable voltage output  Selectable on/off regulator The SH88F6162 has one internal-build regulator. The regulator can output the stable voltage of 3.3V for USB moudle. VDDR pin need to be connected to 1uF capacitance in order to keep the normal output of regulator. The regulator function can be enabled by setting REGEN bit in REGCON register.To ensure the stable output,500 us should be waited after the regulator opened, then the usb module can be enabled. If USB module is not used, it’s recommend that regulator should be closed by clearing REGEN bit in REGCON register to reduce system power consume. REGEN & PowerDown ADC VDDR MCU VDD PGA Regulator OP

9.1.2 Registers

Table 9.1 Regulator Control Register 8FH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 REGCON - - - - - - - REGEN Reset Value (POR/WDT/LVR/PIN) - - - - - - - 0 Bit Number Bit Mnemonic Description

0 REGEN

0: shut down regulator 1: start regulator Output 3.3v after the regulator has been started for 500us The regulator will be shut down by software before MCU switch to Power-Down mode

9.2 LCD/LED Driver

9.2.1 Feature

 LCD driver support 4 X 40, 5 X 39 or 6 X 38 dots  LED driver support 10 X 8 dots  LCD driver support 1/3 Bias  Resistor LCD driver support software contrast adjustment and fast charge mode to reduce power consumption

9.2.2 LCD Driver

The LCD driver contains a controller, a duty cycle generator, 4/5/6 Common signal pins and 40/ 39/38 Segment driver pins. Segment 1-40 and COM1-COM6 can also be used as I/O port, which is controlled by the P1SS, P2SS, P3SS, P4SS, P5SS & P6SS register. LCD COM also can be shared with LED. The 40 bytes display data RAM is addressed to B00H-B27H, which can be used as data memory if needed. The MCU consists normal display topologies with contrast adjustment which supports both 1/4duty -1/3 bias and 1/5duty-1/3 bias and 1/6duty-1/3 bias driving mode.DISPSEL (DISPCON.7) must be cleared before LCD working. the LCD supply power VLCD is selected by VOL[3:0]. When select high frequence crystal as system clock, LCD can still wo rk in PowerDown mode. During the Power on Reset or Pin Reset or LVR Reset or Watch-dog Reset, the LCD will be turned off, and Common and Segment will output low. The features of the LCD Normal Display Mode include the following: - LCD clock source is external 32.768K crystal oscillator or internal 128K RC; - 1/4duty - 1/3 bias, 1/5duty - 1/3 bias or 1/6 duty - 1/3 bias by configuring the DUTY bit in LCDCON register; - LCD frame = 64Hz; - 16 levels contrast adjustment by configuring the VOL[3:0] bits in DISPCON register; - LCD bias resistor (RLCD) can be selected as 20K/75K/300K, bias resistance sum are 60K/225K/900K. It is controlled by MOD[1:0] bit in DISPCON1 register to select as traditional resietance LCD or Fast Charge Mode to reduce power consumption. The relatively high current drain through the 20k resistor will get better LCD display effect, but it may not be suitable for some low current consume application. Lowering this current is possible by configucring the RLCD[2:0] for switching the RLCD value to 75/300K. It will get lower power consumptions, but LCD display effect will get worse. Therefore, SH88F6161/SH88F6162 provides both the low power consumption and display effect of the display mode: fast charge mode. Set MOD[1:0] = 10 to select this mode. When refresh the display data 20k bias resistors are selected to provide larger current. When keep the display data 75k/300K bias resistors are selected to save drive current. Charging time is selected as 1/8, 1/16, 1/32 or 1/64 of LCD com period by FCCTL[1:0] in DISPCON1 register.

LCD Waveform (1/4duty, 1/3bias)

Table 9.2 LCD/LED Control Register C4H, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 DISPCON DISPSEL DISPON DUTY1 DUTY0 VOL3 VOL2 VOL1 VOL0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) 0 0 0 0 0 0 0 0 Bit Number Bit Mnemonic Description

7 DISPSEL

0: select LCD driver, LED driver is not valid 1: select LED driver, LCD driver is not valid

6 DISPON

0: LCD driver disable 1: LCD driver enable 5-4 DUTY[1:0] LCD duty selection bits 00: 1/4 duty, 1/3 bias 01: 1/5 duty, 1/3 bias 1X: 1/6 duty, 1/3 bias 3-0 VOL[3:0] LCD contrast control bits 0000: VLCD = 0.531VDD 0001: VLCD = 0.563VDD 0010: VLCD = 0.594VDD 0011: VLCD = 0.625VDD 0100: VLCD = 0.656VDD 0101: VLCD = 0.688VDD 0110: VLCD = 0.719VDD 0111: VLCD = 0.750VDD 1000: VLCD = 0.781VDD 1001: VLCD = 0.813VDD 1010: VLCD = 0.844VDD 1011: VLCD = 0.875VDD 1100: VLCD = 0.906VDD 1101: VLCD = 0.938VDD 1110: VLCD = 0.969VDD 1111: VLCD = 1.000VDD Note: SH88F6161/SH88F6162 has LCD and LED driver, but can not work in the same time, When DISPSEL = 1 , LCD is disable, DISPSEL = 0, LED is disable. Table 9.3 LCD Control Register1 C5H, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 DISPCON1 - - - RLCD FCCTL1 FCCTL0 MOD1 MOD0 R/W - - - R/W R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) - - - 0 0 0 0 0 Bit Number Bit Mnemonic Description

4 RLCD

LCD bias resistor selection bit 0: LCD bias resistor sum is 225k 1: LCD bias resistor sum is 900k (to be continued)

(continue) 3-2 FCCTL[1:0] Fast charge time control bits 00: 1/8 LCD com period 01: 1/16 LCD com period 10: 1/32 LCD com period 11: 1/64 LCD com period Charge time control bit is effective only in fast charge mode. 1-0 MOD[1:0] Drive mode selection bits 00: traditional mode, bias resistor sum is 225k/900k 01: traditional mode, bias resistor sum is 60k 1X: fast charge mode, bias resistor sum switch between 60K and 225K/900K Table 9.4 LCD Port Selection Register1 C6H, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 P1SS P1S7 P1S6 P1S5 P1S4 P1S3 P1S2 P1S1 P1S0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) 0 0 0 0 0 0 0 0 Bit Number Bit Mnemonic Description

7 P1S7

0: P3.7 is I/O 1: P3.7 is SEG8

6 P1S6

0: P3.6 is I/O 1: P3.6 is SEG7

5 P1S5

0: P3.5 is I/O 1: P3.5 is SEG6

4 P1S4

0: P3.4 isI/O 1: P3.4 is SEG5

3 P1S3

0: P3.3 is I/O 1: P3.3 is SEG4

2 P1S2

0: P3.2 is I/O 1: P3.2 is SEG3

1 P1S1

0: P3.1 is I/O 1: P3.1 is SEG2

0 P1S0

0: P3.0 is I/O 1: P3.0 is SEG1

Table 9.5 LCD Port Selection Register2 C7H, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 P2SS P2S7 P2S6 P2S5 P2S4 P2S3 P2S2 P2S1 P2S0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) 0 0 0 0 0 0 0 0 Bit Number Bit Mnemonic Description

7 P2S7

0: P4.7 is I/O 1: P4.7 is SEG16

6 P2S6

0: P4.6 is I/O 1: P4.6 is SEG15

5 P2S5

0: P4.5 is I/O 1: P4.5 is SEG14

4 P2S4

0: P4.4 is I/O 1: P4.4 is SEG13

3 P2S3

0: P4.3 is I/O 1: P4.3 is SEG12

2 P2S2

0: P4.2 is I/O 1: P4.2 isSEG11

1 P2S1

0: P4.1 is I/O 1: P4.1is SEG10

0 P2S0

0: P4.0 is I/O 1: P4.0 is SEG9

Table 9.6 LCD Port Selection Register3 CEH, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 P3SS P3S7 P3S6 P3S5 P3S4 P3S3 P3S2 P3S1 P3S0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) 0 0 0 0 0 0 0 0 Bit Number Bit Mnemonic Description

7 P3S7

0: P5.7 is I/O 1: P5.7 is SEG24

6 P3S6

0: P5.6 isI/O 1: P5.6 is SEG23

5 P3S5

0: P5.5 is I/O 1: P5.5 is SEG22

4 P3S4

0: P5.4 is I/O 1: P5.4 is SEG21

3 P3S3

0: P5.3 is I/O 1: P5.3 is SEG20

2 P3S2

0: P5.2 is I/O 1: P5.2 isSEG19

1 P3S1

0: P5.1 is I/O 1: P5.1 is SEG18

0 P3S0

0: P5.0 is I/O 1: P5.0 is SEG17

Table 9.7 LCD Port Selection Register4 CFH, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 P4SS P4S7 P4S6 P4S5 P4S4 P4S3 P4S2 P4S1 P4S0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) 0 0 0 0 0 0 0 0 Bit Number Bit Mnemonic Description

7 P4S7

0: P0.3 is I/O 1: P0.3 is SEG32

6 P4S6

0: P0.2 is I/O 1: P0.2 is SEG31

5 P4S5

0: P6.5 is I/O 1: P6.5 is SEG30

4 P4S4

0: P6.4 is I/O 1: P6.4 is SEG29

3 P4S3

0: P6.3 is I/O 1: P6.3 is SEG28

2 P4S2

0: P6.2 is I/O 1: P6.2 is SEG27

1 P4S1

0: P6.1 is I/O 1: P6.1 is SEG26

0 P4S0

0: P6.0 is I/O 1: P6.0 is SEG25

Table 9.8 LCD Port Selection Register5 DFH, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 P5SS P5S7 P5S6 P5S5 P5S4 P5S3 P5S2 P5S1 P5S0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) 0 0 0 0 0 0 0 0 Bit Number Bit Mnemonic Description

7 P5S7

0: P1.3 is I/O 1: P1.3 is COM5/SEG40 P5S7 = 1, P1.3 is COM5 or SEG40 depending on DUTY[1:0] bits DUTY[1:0] = 00: P1.3 to do Segment40 DUTY[1:0] = 01: P1.3 to do Common5 DUTY[1:0] = 1X: P1.3 to do Common5

6 P5S6

0: P1.2 is I/O 1: P1.2 is COM6/SEG39 P5S6 = 1, P1.2 is COM6 or SEG39 depending on DUTY[1:0] bits DUTY[1:0] = 00: P1.2 to do Segment39 DUTY[1:0] = 01: P1.2 to do Segment39 DUTY[1:0] = 1X: P1.2 to do Common6

5 P5S5

0: P1.1 is I/O 1: P1.1 is SEG38

4 P5S4

0: P1.0 is I/O 1: P1.0 is SEG37

3 P5S3

0: P0.7 is I/O 1: P0.7 is SEG36

2 P5S2

0: P0.6 is I/O 1: P0.6 is SEG35

1 P5S1

0: P0.5 is I/O 1: P0.5 is SEG34

0 P5S0

0: P0.4 is I/O 1: P0.4 is SEG33

Table 9.9 LCD Port Selection Register6 E7H, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 P6SS - - - - P6S3 P6S2 P6S1 P6S0 R/W - - - - R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) - - - - 0 0 0 0 Bit Number Bit Mnemonic Description

3 P6S3

0: P1.4 is I/O 1: P1.4 is COM4

2 P6S2

0: P1.5 is I/O 1: P1.5 is COM3

1 P6S1

0: P1.6 is I/O 1: P1.6 is COM2

0 P6S0

0: P1.7 is I/O 1: P1.7 is COM1

LCD 1/4 duty, 1/3 bias (COM1 - 4, SEG1 - 40) Address 7 6 5 4 3 2 1 0 - - - - COM4 COM3 COM2 COM1 B00H - - - - SEG1 SEG1 SEG1 SEG1 B01H - - - - SEG2 SEG2 SEG2 SEG2 B02H - - - - SEG3 SEG3 SEG3 SEG3 B03H - - - - SEG4 SEG4 SEG4 SEG4 B04H - - - - SEG5 SEG5 SEG5 SEG5 B05H - - - - SEG6 SEG6 SEG6 SEG6 B06H - - - - SEG7 SEG7 SEG7 SEG7 B07H - - - - SEG8 SEG8 SEG8 SEG8 B08H - - - - SEG9 SEG9 SEG9 SEG9 B09H - - - - SEG10 SEG10 SEG10 SEG10 B0AH - - - - SEG11 SEG11 SEG11 SEG11 B0BH - - - - SEG12 SEG12 SEG12 SEG12 B0CH - - - - SEG13 SEG13 SEG13 SEG13 B0DH - - - - SEG14 SEG14 SEG14 SEG14 B0EH - - - - SEG15 SEG15 SEG15 SEG15 B0FH - - - - SEG16 SEG16 SEG16 SEG16 B10H - - - - SEG17 SEG17 SEG17 SEG17 B11H - - - - SEG18 SEG18 SEG18 SEG18 B12H - - - - SEG19 SEG19 SEG19 SEG19 B13H - - - - SEG20 SEG20 SEG20 SEG20 B14H - - - - SEG21 SEG21 SEG21 SEG21 B15H - - - - SEG22 SEG22 SEG22 SEG22 B16H - - - - SEG23 SEG23 SEG23 SEG23 B17H - - - - SEG24 SEG24 SEG24 SEG24 B18H - - - - SEG25 SEG25 SEG25 SEG25 B19H - - - - SEG26 SEG26 SEG26 SEG26 B1AH - - - - SEG27 SEG27 SEG27 SEG27 B1BH - - - - SEG28 SEG28 SEG28 SEG28 B1CH - - - - SEG29 SEG29 SEG29 SEG29 B1DH - - - - SEG30 SEG30 SEG30 SEG30 B1EH - - - - SEG31 SEG31 SEG31 SEG31 B1FH - - - - SEG32 SEG32 SEG32 SEG32 B20H - - - - SEG33 SEG33 SEG33 SEG33 B21H - - - - SEG34 SEG34 SEG34 SEG34 B22H - - - - SEG35 SEG35 SEG35 SEG35 B23H - - - - SEG36 SEG36 SEG36 SEG36 B24H - - - - SEG37 SEG37 SEG37 SEG37 B25H - - - - SEG38 SEG38 SEG38 SEG38 B26H - - - - SEG39 SEG39 SEG39 SEG39 B27H - - - - SEG40 SEG40 SEG40 SEG40

LCD 1/5 duty, 1/3 bias (COM1 - 5, SEG1 - 39) Address 7 6 5 4 3 2 1 0 - - - COM5 COM4 COM3 COM2 COM1 B00H - - - SEG1 SEG1 SEG1 SEG1 SEG1 B01H - - - SEG2 SEG2 SEG2 SEG2 SEG2 B02H - - - SEG3 SEG3 SEG3 SEG3 SEG3 B03H - - - SEG4 SEG4 SEG4 SEG4 SEG4 B04H - - - SEG5 SEG5 SEG5 SEG5 SEG5 B05H - - - SEG6 SEG6 SEG6 SEG6 SEG6 B06H - - - SEG7 SEG7 SEG7 SEG7 SEG7 B07H - - - SEG8 SEG8 SEG8 SEG8 SEG8 B08H - - - SEG9 SEG9 SEG9 SEG9 SEG9 B09H - - - SEG10 SEG10 SEG10 SEG10 SEG10 B0AH - - - SEG11 SEG11 SEG11 SEG11 SEG11 B0BH - - - SEG12 SEG12 SEG12 SEG12 SEG12 B0CH - - - SEG13 SEG13 SEG13 SEG13 SEG13 B0DH - - - SEG14 SEG14 SEG14 SEG14 SEG14 B0EH - - - SEG15 SEG15 SEG15 SEG15 SEG15 B0FH - - - SEG16 SEG16 SEG16 SEG16 SEG16 B10H - - - SEG17 SEG17 SEG17 SEG17 SEG17 B11H - - - SEG18 SEG18 SEG18 SEG18 SEG18 B12H - - - SEG19 SEG19 SEG19 SEG19 SEG19 B13H - - - SEG20 SEG20 SEG20 SEG20 SEG20 B14H - - - SEG21 SEG21 SEG21 SEG21 SEG21 B15H - - - SEG22 SEG22 SEG22 SEG22 SEG22 B16H - - - SEG23 SEG23 SEG23 SEG23 SEG23 B17H - - - SEG24 SEG24 SEG24 SEG24 SEG24 B18H - - - SEG25 SEG25 SEG25 SEG25 SEG25 B19H - - - SEG26 SEG26 SEG26 SEG26 SEG26 B1AH - - - SEG27 SEG27 SEG27 SEG27 SEG27 B1BH - - - SEG28 SEG28 SEG28 SEG28 SEG28 B1CH - - - SEG29 SEG29 SEG29 SEG29 SEG29 B1DH - - - SEG30 SEG30 SEG30 SEG30 SEG30 B1EH - - - SEG31 SEG31 SEG31 SEG31 SEG31 B1FH - - - SEG32 SEG32 SEG32 SEG32 SEG32 B20H - - - SEG33 SEG33 SEG33 SEG33 SEG33 B21H - - - SEG34 SEG34 SEG34 SEG34 SEG34 B22H - - - SEG35 SEG35 SEG35 SEG35 SEG35 B23H - - - SEG36 SEG36 SEG36 SEG36 SEG36 B24H - - - SEG37 SEG37 SEG37 SEG37 SEG37 B25H - - - SEG38 SEG38 SEG38 SEG38 SEG38 B26H - - - SEG39 SEG39 SEG39 SEG39 SEG39

LCD 1/5 duty, 1/3 bias (COM1 - 6, SEG1 - 38) Address 7 6 5 4 3 2 1 0 - - COM6 COM5 COM4 COM3 COM2 COM1 B00H - - SEG1 SEG1 SEG1 SEG1 SEG1 SEG1 B01H - - SEG2 SEG2 SEG2 SEG2 SEG2 SEG2 B02H - - SEG3 SEG3 SEG3 SEG3 SEG3 SEG3 B03H - - SEG4 SEG4 SEG4 SEG4 SEG4 SEG4 B04H - - SEG5 SEG5 SEG5 SEG5 SEG5 SEG5 B05H - - SEG6 SEG6 SEG6 SEG6 SEG6 SEG6 B06H - - SEG7 SEG7 SEG7 SEG7 SEG7 SEG7 B07H - - SEG8 SEG8 SEG8 SEG8 SEG8 SEG8 B08H - - SEG9 SEG9 SEG9 SEG9 SEG9 SEG9 B09H - - SEG10 SEG10 SEG10 SEG10 SEG10 SEG10 B0AH - - SEG11 SEG11 SEG11 SEG11 SEG11 SEG11 B0BH - - SEG12 SEG12 SEG12 SEG12 SEG12 SEG12 B0CH - - SEG13 SEG13 SEG13 SEG13 SEG13 SEG13 B0DH - - SEG14 SEG14 SEG14 SEG14 SEG14 SEG14 B0EH - - SEG15 SEG15 SEG15 SEG15 SEG15 SEG15 B0FH - - SEG16 SEG16 SEG16 SEG16 SEG16 SEG16 B10H - - SEG17 SEG17 SEG17 SEG17 SEG17 SEG17 B11H - - SEG18 SEG18 SEG18 SEG18 SEG18 SEG18 B12H - - SEG19 SEG19 SEG19 SEG19 SEG19 SEG19 B13H - - SEG20 SEG20 SEG20 SEG20 SEG20 SEG20 B14H - - SEG21 SEG21 SEG21 SEG21 SEG21 SEG21 B15H - - SEG22 SEG22 SEG22 SEG22 SEG22 SEG22 B16H - - SEG23 SEG23 SEG23 SEG23 SEG23 SEG23 B17H - - SEG24 SEG24 SEG24 SEG24 SEG24 SEG24 B18H - - SEG25 SEG25 SEG25 SEG25 SEG25 SEG25 B19H - - SEG26 SEG26 SEG26 SEG26 SEG26 SEG26 B1AH - - SEG27 SEG27 SEG27 SEG27 SEG27 SEG27 B1BH - - SEG28 SEG28 SEG28 SEG28 SEG28 SEG28 B1CH - - SEG29 SEG29 SEG29 SEG29 SEG29 SEG29 B1DH - - SEG30 SEG30 SEG30 SEG30 SEG30 SEG30 B1EH - - SEG31 SEG31 SEG31 SEG31 SEG31 SEG31 B1FH - - SEG32 SEG32 SEG32 SEG32 SEG32 SEG32 B20H - - SEG33 SEG33 SEG33 SEG33 SEG33 SEG33 B21H - - SEG34 SEG34 SEG34 SEG34 SEG34 SEG34 B22H - - SEG35 SEG35 SEG35 SEG35 SEG35 SEG35 B23H - - SEG36 SEG36 SEG36 SEG36 SEG36 SEG36 B24H - - SEG37 SEG37 SEG37 SEG37 SEG37 SEG37 B25H - - SEG38 SEG38 SEG38 SEG38 SEG38 SEG38

9.2.3 LED Driver

The LED driver contains a controller, a duty cycle generator with 10 Common signal pins and 8 Segment driver pins. When DISPSEL bit is set, LED function is enable,and LCD is disable. LED provides 1/ 10 duty voltage driving mode.The controller consists of display data RAM memory block and a duty generator. LED_SEG1-8 can be used as I/O port. When DISPSEL is 1, LED is valid, LCD is invalid.P2SS - P5SS register is invalid, P1SS individually are used to control LED_SEG1-8 and I/O mode selection. P6SS and P7SS are used to control LED_C1- LED_C10 and I/O mode selection. LED driver work in common cathode mode. LED COM only sink current and LED SEG only drive current. When drive the led, the common cathode led can only be choosed. LED driver does not support the common anode drive mode. When set a bit of LED RAM, the corresponding SEG will output high. Otherwisely, the SEG will output low. DISPSEL must be set to 1 before LED is driven. LED clock source is external 32.768K crystal oscillator or internal 128K RC, LED frame = 64Hz. When MCU enters the Power -Down mode, the LED will be turned off, If 32.768kHz crystal or 128k internal RC works in Power-down mode, the LED is still working. During Power on Reset, Pin Reset, LVR or Watch Dog Reset, LED will be turned off. When LED is turned off, Common and Segment will output low. LED Waveform VDD GND 1/10 DUTY COM1 SEG2 GND VDD UNSELECTSELECT tol VDD GND COM2 SEG1 GND VDD SEG1& COM1 GND VDD Note: tOL is overlap time of LED Common, tOL = 20μs-40μs. Register Table 9.10 LCD/LED Control Register C4H, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 DISPCON DISPSEL DISPON - - - - - R/W R/W R/W - - - - - Reset Value (POR/WDT/LVR/PIN) 0 0 - - - - - Bit Number Bit Mnemonic Description LCD, LED selection control bit 0: select LCD driver, LED driver is not valid 1: select LED driver, LCD driver is not vaild 0: LED driver disable 1: LED driver enable Note: SH88F6161/SH88F6162 has LCD driver and LED driver, which may not be effective at the same time, if DISPSEL = 1, LCD driver is not valid, if DISPSEL = 0, LED driver is not valid.

Table 9.11 LED Selection Register1 C6H, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 P1SS P1S7 P1S6 P1S5 P1S4 P1S3 P1S2 P1S1 P1S0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) 0 0 0 0 0 0 0 0 Bit Number Bit Mnemonic Description LED_S8 selection bit 0: P3.7 is I/O 1: P3.7 is LED_S8 LED_S7 selection bit 0: P3.6 is I/O 1: P3.6 is LED_S7 LED_S6 selection bit 0: P3.5 is I/O 1: P3.5 is LED_S6 LED_S5 selection bit 0: P3.4 is I/O 1: P3.4 is LED_S5 LED_S4 selection bit 0: P3.3 is I/O 1: P3.3 is LED_S4 LED_S3 selection bit 0: P3.2 is I/O 1: P3.2 is LED_S3 LED_S2 selection bit 0: P3.1 is I/O 1: P3.1 is LED_S2 LED_S1 selection bit 0: P3.0 is I/O 1: P3.0 is LED_S1

Table 9.12 LED Selection Registe6 E7H, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 P6SS P6S7 P6S6 P6S5 P6S4 P6S3 P6S2 P6S1 P6S0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) 0 0 0 0 0 0 0 0 Bit Number Bit Mnemonic Description

7 P6S7

LED_C8 selection bit 0: P1.0 is I/O 1: P1.0 is LED_C8

6 P6S6

LED_C7 selection bit 0: P1.1 is I/O 1: P1.1 is LED_C7

5 P6S5

LED_C6 selection bit 0: P1.2 is I/O 1: P1.2 is LED_C6

4 P6S4

LED_C5 selection bit 0: P1.3 is I/O 1: P1.3 is LED_C5 LED_C4 selection bit 0: P1.4 is I/O 1: P1.4 is LED_C4 LED_C3 selection bit 0: P1.5 is I/O 1: P1.5 is LED_C3 LED_C2 selection bit 0: P1.6 is /O 1: P1.6 is LED_C2 LED_C1 selection bit 0: P1.7 is I/O 1: P1.7 is LED_C1

Table 9.13 LED Port Selection Registe7 EFH, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 P7SS - - - - - - P7S1 P7S0 R/W - - - - - - R/W R/W Reset Value (POR/WDT/LVR/PIN) - - - - - - 0 0 Bit Number Bit Mnemonic Description

1 P7S1

LED_C10 selection bit 0: P0.6 is I/O 1: P0.6 is LED_C10

0 P7S0

LED_C9 selection bit 0: P0.7 is I/O 1: P0.7 is LED_C9 LED RAM Configuration LED 1/8 duty (LED_C1 - 10, LED_S1 - 8) Address 7 6 5 4 3 2 1 0 B00H COM1 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 B01H COM2 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 B02H COM3 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 B03H COM4 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 B04H COM5 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 B05H COM6 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 B06H COM7 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 B07H COM8 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 B08H COM9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 B09H COM10 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1

9.3 TWI Serial Interface

9.3.1 Features

 Simple Two-wire Interface  Support Both Master and Slave Mode  Operates as Transmitter or Receiver  Includes the capacity of Arbitration and the Possibility to have Multiple Masters On the Bus  Timeout of Bus Low Voltage can be checked  System in Idle state can be Wake-up  Programmable Slave Address The TWI Interface complete the transition with SDA and SCL, between Master and Slaver.SH88F6161/SH88F6162 has the ability to process and transmit byte, and track the serial transaction automaticly, which conforms to TWI protocol. TWI clock is system clock. As shown follow figure, the TWI protocol allows the systems designer to interconnect up to 128 individually addressable devices. SCL Master Device 1 SDA VDD= 5VVDD= 5V VDD= 5V VDD=5V Slave Device 1 Slave Device 2 Master Device 2 VDD= 5V

9.3.2 Data Transfer Format

Except START and STOP condition, data bit only can be transmitted when a pulse appears on the clock line, The data on the SDA line must be stable during the HIGH period of the clock. Similar to the I2C protocol, a high to low transition on the SDA line while SCL is high is defined to be a START condition or a repeated start. And a low to high transition on the SDA line while the SCL is high is defined to be a STOP condition Data transfer is always initiated or ended by a Bus Master device. The Master starts a transfer by sending a START condition, and ends a transfer by sending a STOP condition. Betwwen Start condition and Stop condition, the bus state is defined as “busy”. A master may start a transfer only if the bus is free. The master can generate either a STOP condition to abort the transfer, or a repeated START condition to start a new transfer. All data packets transmitted on the TWI bus are 9 bits long, consisting of one data byte and an acknowledge bit. During a data transfer, the master generates the clock and the START and STOP conditions, while the receiver is responsible for acknowledging the reception. An Acknowledge (ACK) is signaled by the receiver pulling the SDA line low during the ninth SCL cycle. If the receiver leaves the SDA line high, a NACK is signaled. A NACK should be signaled when the receiver has received the last data byte or cannot receive any more bytes. The MSB of the data byte is transmitted first. A transfer consists of a START condition, address+read/write, one or more data packet and a STOP condition. An empty message, consisting of a START followed by a STOP condition, is illegal. Note that the wired-AND can be used to implement handshaking between the Master and the Slave. The Slave can extend the SCL low period by pulling the SCL line low. This is useful if the clock speed set up by the Master is too fast for the Slave, or the Slave needs extra time for processing between the data transmissions. The Slave extending the SCL low period will not affect the SCL high period, which is determined by the Master. As a consequence, the Slave can reduce TWI data transfer speed by prolonging the TWI duty cycle.

START STARTSTOP Repeated START STOP SH88F6161/SH88F6162 generates an ACK by pulling the SDA line low. After the interrupt flag be set, SH88F6161/SH88F6162 pulls the SCL line low, and releases SDA line. When the inter rupt process has completed, SCL line should be released and TWINT flag should be cleared. Addr MSB Addr MSB R/W ACK Data MSB Data LSB ACK SDA SCL START SLA+R/W Data Byte STOP 1 2 7 8 9 1 2 7 8 9 Clock Synchronization When one or more masters want to drive the bus, all masters will generate their own clock on the SCL line to transfer messages on the I2C-bus. Data is only valid during the HIGH period of the clock. A defined clock is therefore needed for the bit -by-bit arbitration procedure to take place. Clock synchronization is performed using the wired-AND connection of I2C interfaces to the SCL line. This means that a HIGH to LOW transition on the SCL line will cause the devices concerned to start counting off their LOW period and, once a device clock has gone LOW, it will hold the SCL line in that state until the clock HIGH state is reached (see Fig.8). However, the LOW to HIGH transition of this clock may not change the state of the SCL line if another clock is still within its LOW period. The SCL line will therefore be held LOW by the device with the longest LOW period. Devices with shorter LOW periods enter a HIGH wait-state during this time. When all devices concerned have counted off their LOW period, the clock line will be released and go HIGH. There will then be no difference between the device clocks and the state of the SCL line, and all the devices will start counting their HIGH periods. The first device to complete its HIGH period will again pull the SCL line LOW. In this way, a synchronized SCL clock is generated with its LOW period determined by the device with the longest clock LOW period, and its HIGH period determined by the one with the shortest clock HIGH period. SCL from Master A SCL from Master B SCL bus Line Masters Start Counting Low Period Masters Start Counting High Period TAlow TAhigh TBlow TBhigh

A master may start a transfer only if the bus is free. Two or more masters may generate a START condition within the minimum hold time (tHD;STA) of the START condition which results in a defined START condition to the bus. Arbitration takes place on the SDA line, while the SCL line is at the HIGH level, in such a way that the master which transmits a HIGH level, while another master is transmitting a LOW level will switch off its DATA output stage because the level on the bus doesn’t correspond to its own level. Arbitration can continue for many bits. Its first stage is comparison of the address bits. If the masters are each trying to address the same device, arbitration continues with comparison of the data- bits if they are master -transmitter, or acknowledge-bits if they are master -receiver. Because address and data information on the I2C -bus is determined by the winning master, no information is lost during the arbitration process. A master that loses the arbitration can generate clock pulses until the end of the byte in which it loses the arbitration. As an Hs-mode master has a unique 8-bit master code, it will always finish the arbitration during the first byte. If a master also incorporates a slave function and it loses arbitration during the addressing stage, it’s possible that the winning master is trying to address it. The losing master must therefore switch over immediately to its slave mode. Special attention must be paid if, during a serial transfer, the arbitration procedure is still in progress at the moment when a repeated START condition or a STOP condition is transmitted to the I2C -bus. If it’s possible for such a situation to occur, the masters involved must send this repeated START condition or STOP condition at the same position in the format frame. In other words, arbitration isn’t allowed between: (1) A repeated START condition and a data bit (2) A STOP condition and a data bit (3) A repeated START condition and a STOP condition DATA 1 DATA 2 SDA SCL S Transmitter 1 loses arbitration

9.3.3 Overview of the TWI Mouudle

(TWISTA) Address Register (TWIADR) Address Comparator Status Register (TWISTA) Status Machine and Status Control Control Register (TWICON) START/ STOP Control Timeout/ Bus Free Detection Arbitration Detection Address/Data Shift Register (TWIDAT) ACK Bus Interface Unit Address Match Unit Control Unit Bit Rate Generator SCL SDA

This unit contains the Data and Address Shift Register (TWIDAT), a START/STOP Controller,and Arbitration and Bus Timeout detection hardware. The TWIDAT contains the address or data bytes to be transmitted,or the address or data bytes be received. The START/STOP Controller is responsible for generation and detection of START, REPEATED START, and STOP conditions. If SH88F6161/SH88F6162 has initiated a transmission as Master, the Arbitration Detection hardware continuously monitors the transmission trying to determine if arbitration is in process. When lost an arbitration, the Control Unit is informed. Correct action can then be taken and appropriate status codes generated. Data or Address bit to be transferd should keep stable during the period of SCK changing from low to high. When SH88F6161/SH88F6162 transmits ACK/NACK, the SCL changing from low to high will result the TWINT event to generate.SCL will be pulled low when the SCL has been changed from high to low. And SCL will be released after TWINT cleared. When SH88F6161/SH88F6162 has transmitted ACK/NACK with TWINT cleared and SCL still high, SDA jumping will result TWINT interrupt regenerating, and status switching to 00H. Then the current communication of SH88F6161/SH88F6162 will stop.Such state process is the same as general 00H. When SH88F6161/SH88F6162 has transferred ACK/NACK with TWINT not be cleared and SCL still high, the SDA line change will make the state transfer to 00H with no interrupt rehappening. If SH88F6161/SH88F6162 transfers to “00H”state as slaver or master, the communication will be ended. Then SH88F6161/SH88F6162 can initiated transition as master by sending STA, or accept STA+ADR as slaver. After the current communication is terminated, SH88F6161/SH88F6162 will don’t take part in the current transmission. If SH88F6161/SH88F6162 exists as a master, please enable EFREE function to avoid entering logic deadband. SH88F6161/SH88F6162 defines the Bus hold high more than T FREE = TSYS X TWTFREE X 256 (TFREE > tSCL/2) as idle mode, releasing the Bus. The function is only used in the transmission process of one packet (8 + 1 bit). When SH88F6161/SH88F6162 is in slave transfer mode and the first byte of transferred message is low, the function can be used. STA and RSTA is not situable for this function. If SH88F6161/SH88F6162 generates interrupt, TFREE bit in T WICON regiser will be set (if control bit EFREE bit has been set). If SCL is pulled low by slave, the transition will be suspended temporarily; The master also can’t pull SCL line to high. To solve this problem, TWI defines all devices that take part in transmission pull SCL line to low more than N*Tsys as Timeout. TOUT bit in TWICON register will be set (if control bit ETOT has been set). Bit Rate Generator Unit This unit controls the period of SCL when operating in a Master mode. The SCL period is controlled by settings in the TWI Bit Rate Register (TWIBR) and in the TWICON(CR[1:0]). The SCL frequency is generated according to the following equation: fScl = fSYS /(16+2 X CR X TWIBR) Address Match Unit The Address Match unit checks if received address bytes match the seven-bit address in the TWI Address Register (TWIADR). If the General address Enable (GC) bit has be set, the Address Match unit will check if received address bytes match General address (00H). When address matched, the Control Unit is informed. Correct action can then be taken and appropriate status codes generated. Control Unit The Control unit monitors the TWI bus and generates responses corresponding to settings in the TWI Control Register (TWICON). When an event requiring the attention of the application occurs on the TWI bus, the TWI Interrupt Flag (TWINT) is asserted. In the next clock cycle, the TWI Status Register (TWISTA) is updated with a status code identifying the event. The TWSR only contains relevant status information when the TWI Interrupt Flag is asserted. At all other times, the TWSR contains a special status code indicating that no relevant status information is available. As long as the TWINT Flag is set, the SCL line is held low. This allows the application software to complete its tasks before allowing the TWI transmission to continue.

9.3.4 Transmission Modes

TWI is byte-oriented and interrupt based. Interrupts are issued after all bus events, like reception of a byte or transmission of a START condition. Because the TWI is interrupt-based, the application software is free to carry on other operations during a TWI byte transfer. Note that the TWI Interrupt Enable (ENTWI) bit in TWICON together with the Global Interrupt Enable(EA) bit and TWI Interrupt Enable(ETWI) bit in I EN0 allow the application to decide whether or not assertion of the TWINT Flag should generate an interrupt request. If the ETWI or EA bit is cleared, the application must poll the TWINT Flag in order to detect actions on the TWI bus. When the TWINT Flag is asserted, the TWI has finished an operation and awaits application response. In this case, the TWI Status Register (TWISTA) contains a value indicating the current state of the TWI bus. The application software can then decide how the TWI should behave in the next TWI bus cycle by manipulating the TWICON and TWISTA Registers. The following sections describe each of modes. Possible status codes are described along with figures detailing data transmission in each of the modes. These figures contain the following abbreviations: S ：START condition Rs ：REPEATED START condition R ：Read bit (high level at SDA) W ：Write bit (low level at SDA) A ：Acknowledge bit (low level at SDA) Ā ：Not acknowledge bit (high level at SDA) DATA ：8-bit data byte P ：STOP condition SLA ：Slave Address Circles are used to indicate that the TWINT Flag is set. The numbers in the circles show the status code held in TWISTA, with the prescaler bits masked to zero. At these points, actions must be taken by the application to continue or com plete the TWI transfer. The TWI transfer is suspended until the TWINT Flag is cleared by software. For each status code, the required software action and details of the following serial transfer are given in follow section.

In the Master Transmitter mode, a number of data bytes are transmitted to a Slave Receiver. In order to enter a Master mode, a START condition must be transmitted. The format of the following address packet determines whether Master Transmitter or Master Receiver mode is to be entered. If SLA+W is transmitted, MT mode is entered, if SLA+R is transmitted, MR mode is entered. ENTWI and STA must be set,together with STO and TWINT being cleared. The TWI will then test the 2 -wire Serial Bus and generate a START condition as soon as the bus becomes free. After a START condition has been transmitted, the TWINT Flag is set by hardware, and the status code in TWISTA will be 0x08. In order to enter MT mode, SLA+W must be transmitted. This is done by writing SLA+W to TWIDAT. Thereafter the TWINT bit should be cleared to continue the transfer. When SLA+W have been transmitted and an acknowledgement bit has been received, TWINT is set again and a number of status codes in TWISTA are possible. Possible status codes in Master mode are 0x18, 0x20, or 0x38. Possible status codes in Slaver mode are 0x68, 0x78, or 0xB0. Status Codes for Master Transmitter Mode Status TWI bus and serial interface hardware status Application software response Next Action Taken by TWI Hardware R/W data register TWIDAT operation Control bit operation STA STO TW INT AA 08H A START condition has been transmitted Load SLA+W X 0 0 X SLA+W wii be transmitted, ACK or NACK will be received 10H A repeated START condition has been transmitted Load SLA +W X 0 0 X SLA+W wii be transmitted, ACK or NACK will be received Load SLA +R X 0 0 X SLA+R will be transmitted,TWI wiii switch to Master receive rmode 18H SLA+W has been transmitted； ACK has been received Load data byte 0 0 0 X Data bytes wii be transmitted, ACK or NACK will be received No TWIDAT action 1 0 0 X Repeated START will be transmitted 0 1 0 X STOP will be transmitted；clear STO flag 1 1 0 X STOP will be transmitted, START will be transmitted; STO is cleared 20H SLA+W has been transmitted； NACK has been received Load data byte 0 0 0 X Data bytes wii be transmitted, ACK or NACK will be received No TWIDAT action 1 0 0 X Repeated START wii be transmitted 0 1 0 X STOP will be transmitted；clear STO flag 1 1 0 X STOP will be transmitted, START will be transmitted; STO is cleared 28H TWIDAT data has been transmitted； ACK has been received Load data byte 0 0 0 X Data bytes wii be transmitted, ACK or NACK wil l be received No TWIDAT action 1 0 0 X Repeated START wii be transmitted 0 1 0 X STOP will be transmitted；clear STO flag 1 1 0 X STOP will be transmitted, START will be transmitted; STO is cleared 30H TWIDAT data has been transmitted； NACK has been received Load data byte 0 0 0 X Data bytes wi ll be transmitted, ACK or NACK will be received No TWIDAT action 1 0 0 X Repeated START will be transmitted 0 1 0 X STOP will be transmitted；clear STO flag 1 1 0 X STOP will be transmitted, START will be transmitted; STO is cleared 38H Arbitration lost in SLA+W or data bytes No TWIDAT action 0 0 0 X TWI Bus will be released and not addressed Slave mode entered 1 0 0 X A START condition will be transmitted when the bus becomes free

Arbitration lost and addressed as slave Other Master Continue Other Master Continue To Corresponding state in slave mode 18H 28H 20H 38H 30H 38H 68H/78H/B0H Master Transmitter Master Receiver SH88F6161Actions Other Device Actions 08H 10H

In the Master Receiver mode, a number of data bytes are received from a Slave Transmitter. In order to enter a Master mode, a START condition mustbe transmitted. The format of the following address packet determi nes whether MasterTransmitter or Master Receiver mode is to be entered. If SLA+W is transmitted, MTmode is entered, if SLA+R is transmitted, MR mode is entered. ENTWI and STA must be set,together with STO and TWINT being cleared. The TWI will then test the 2-wire Serial Bus and generate a START condition as soon as the bus becomes free. After a START condition has been transmitted, the TWINT Flag is set by hardware, and the status code in TWISTA will be 0x08. In order to enter MT mode, SLA+R must be transmitted. This is done by writing SLA+R to TWIDAT. Thereafter the TWINT bit should be cleared to continue the transfer. When SLA+R have been transmitted and an acknowledgement bit has been received, TWINT is set again and a number of status codes in TWISTA are possible. Possible status codes in Master mode are 0x40, 0x48, or 0x38. Possible status codes in Slaver mode are 0x68, 0x78, or 0xB0. Status Codes for Master Receiver Mode Status TWI bus and serial interface hardware status Application software response Next Action Taken by TWI Hardware R/W data register TWIDAT operation Control bit operation STA STO TW INT AA 08H A START condition has been transmitted Load SLA+R X 0 0 X SLA+R will be transmitted, and ACK or NACK will be received 10H A repeated START condition has been transmitted Load SLA+R X 0 0 X SLA+R will be transmitted, and ACK or NACK will be received Load SLA+W X 0 0 X SLA+W will be transmitted,and TWI will switch to master transmitter mode 38H SLA+R has been transmitted or arbitration lost in NACK No TWIDAT action 0 0 0 X TWIl Bus will be released and not addressed Slave mode entered 1 0 0 X A START condition will be transmitted when the bus becomes free 40H SLA+R has been transmitted; ACK has been received No TWIDAT action 0 0 0 0 Data byte will be received and ACK will be returned 0 0 0 1 Data byte will be received and ACK will be returned 48H SLA+R has been transmitted; NACK has been received No TWIDAT action 1 0 0 X Repeated START will be transmitted 0 1 0 X STOP will be transmitted；clear STO flag 1 1 0 X STOP will be transmitted, Then START will be transmitted; STO is cleared 50H Data byte has been received; ACK has been returned Read data byte 0 0 0 0 Data byte will be received and ACK will be returned 0 0 0 1 Data byte will be received and ACK will be returned 58H Data byte has been received; NACK has been returned Read data byte 1 0 0 X Repeated START will be transmitted 0 1 0 X STOP will be transmitted; clear STO flag 1 1 0 X STOP will be transmitted, Then START will be transmitted; STO is cleared

address or not acknowledged Arbitration lost and addressed as slave Other Master Continue Other Master Continue To Corresponding state in slave mode 40H 58H 48H 38H 38H 68H/78H/B0H Master Receiver Master Transmitter Ack DATA 50H SH88F6161 Actions Other Device Actions Successfull reception from a slave transmitter 08H 10H

In the Slave Transmitter mode, a number of data bytes are transmitted to a Master Receiver. To initiate the Slave transmitter mode, TWICON register and TWIADR register must be initialized: set ENTWI bit and AA bit in TWICON register, clearing STA, STO and TWINT; The high 7-bit in TWIADR register is used to prepare the corresponding address for SH88F6601. If GC is set, SH88F6601 will respond the general address (00H); Otherwise, SH88F6601 will not respond the address. When TWIADR and TWICON have been initialized, SH88F6601 waits until it is addressed by its own slave address (or the general call address if enabled) .If the direction bit is “R”, then TWI enter to the Slave transmitter mode. Otherwise, TWI will enter to the Slave receiver mode. After its own slave address and read bit have been received, TWINT will be set and a valid status code can be read from TWISTA. If the AA bit is cleared during a transfer, TWI will transmit the last byte and get into C0H or C8H state depending on whether the master transmits a NACK or ACK. TWI will switch to the not address slave mode, and ignore the master if it continues the transfer. Thus the master will receive all “1” as serial data. State C8H is entered if the master demands additional data bytes (by transmitting ACK), even though the slaver has transmitted the last byte. Status Codes for Slave Receiver Mode Status TWI bus and serial interface hardware status Application software response Next Action Taken by TWI Hardware R/W data register TWIDAT operation Control bit operation STA STO TW INT AA A8H Own SLA+R has been received; ACK has been returned Load data byte X 0 0 0 Last data byte will be transmitted; waitting ACK or NACK response X 0 0 1 Data byte will be transmitted; waitting ACK or NACK response B0H Arbitration lost in SLA+R/W as Master; own SLA+R has been received; ACK has been returned Load data byte X 0 0 0 Last data byte will be transmitted; waitting ACK or NACK response X 0 0 1 Data byte will be transmitted; waitting ACK or NACK response B8H Data byte in TWIDAT has been transmitted； ACK has been returned Load data byte X 0 0 0 Last data byte will be transmitted; waitting ACK or NACK response X 0 0 1 Data byte will be transmitted; waitting ACK or NACK response C0H Data byte in TWIDAT has been transmitted； NACK has been returned No TWIDAT action 0 0 0 0 Switched to the not addressed Slave mode; no recognition of own SLA or GCA 0 0 0 1 Switched to the not addressed Slave mode; own SLA will be recognized; GCA will be recognized if GC = “1” 1 0 0 0 Switched to the not addre ssed Slave mode; no recognition of own SLA or GCA; a START condition will be transmitted when the bus becomes free 1 0 0 1 Switched to the not addressed Slave mode; own SLA will be recognized; GCA will be recognized if GC = “1”; a START condition will be transmitted when the bus becomes free C8H Last data byte in TWIDAT register has been transmitted (AA=0); ACK has been returned; No TWIDAT action 0 0 0 0 Switched to the not addressed Slave mode; no recognition of own SLA or GCA 0 0 0 1 Switched to the not addressed Slave mode; own SLA will be recognized; GCA will be recognized if GC = “1” 1 0 0 0 Switched to the not addressed Slave mode; no recognition of own SLA or GCA; a START condition will be transmitted when the busbecomes free 1 0 0 1 Switched to the not addressed Slave mode; own SLA will be recognized; GCA will be recognized if TWIADR = “1”; a START condition will be transmitted when the bus becomes free

Arbitration lost as master and addressed as slave transmitter Last data byte transmitted, Switched to not addressed slave (AA = 0) A8H C0H B0H DATA B8H SH88F6161 Actions Other Device Actions C8H Ack Ack All '1' Slave Receiver Mode In the Slave Receiver mode, a number of data bytes are received from a Master Transmitter . To initiate the Slave Receiver mode, TWICON and TWIADR must be initialized: set ENTWI bit and STA bit in TWICON register, clearing STO and TWINT.The upper 7 bits in TWIADR register are the address to which the 2-wire Serial Interface will respond when addressed by a Master. If the GC(LSB) is set, the TWI will respond to the general address (0x00), otherwise it will ignore the general address. When TWIADR and TWCR have been initialized, the TWI waits until it is addressed by its own slave address (or the general call address if enabled). If the direction bit is “0” (write), the TWI will operate in SR mode, otherwise ST mode is entered. After its own slave address and the write bit have been received, the TWINT Flag is set and a valid status code can be read from TWISTA. If the AA bit is cleared during a transfer, TWI will receive the last byte and respond NACK. Responding NACK indicates the current slaver can’t receive more bytes. When AA = 0, SH88F6161/SH88F6162 can’ t respond the visit to its own address. However, SH88F6161/SH88F6162 still monitors the bus status, and address recognition may resume at any time by setting AA. This implies that the AA bit may be used to temporarity isolate SH88F6161/SH88F6162 from the bus. 从机接收模式状态码 Status TWI bus and serial interface hardware status Application software response Next Action Taken by TWI Hardware R/W data register TWIDAT operation Control bit operation STA STO TW INT AA 60H Own SLA+W has been received; ACK has been returned NO TWIDAT action X 0 0 0 data byte will be transmitted and NOT ACK should be received X 0 0 1 data byte will be transmitted and ACK should be received 68H Arbitration lost in SLA+R/W as Master; own SLA+W has been received; ACK has been returned NO TWIDAT action X 0 0 0 data byte will be transmitted and NOT ACK should be received X 0 0 1 data byte will be transmitted and ACK should be received 70H GCA has been received; ACK has been returned NO TWIDAT action X 0 0 0 data byte will be transmitted and NOT ACK should be received X 0 0 1 data byte will be transmitted and ACK should be received (to be continued)

(continue) 78H Arbitration lost in SLA+R/W as Master; own GCA has been received; ACK has been returned NO TWIDAT action X 0 0 0 data byte will be transmitted and NOT ACK should be received X 0 0 1 data byte will be transmitted and ACK should be received 80H Previously addressed with own SLA+W; Data has been received; ACK has been returned Load data byte X 0 0 0 data byte will be transmitted and NOT ACK should be received X 0 0 1 data byte will be transmitted and ACK should be received 88H Previously addressed with own SLA+W; data has been received; NOT ACK has been returned Load data byte 0 0 0 0 Switched to the not addressed Slave mode; no recognition of own SLA or GCA 0 0 0 1 Switched to the not addressed Slave mode; own SLA will be recognized; GCA will be recognized if GC = “1” 1 0 0 0 Switched to the not addressed Slave mode; no recognition of own SLA or GCA; a START condition will be transmitted when the bus becomes free 1 0 0 1 Switched to the not addressed Slave mode; own SLA will be recognized; GCA will be recognized if GC = “1”; a START condition will be transmitted when the bus becomes free 90H Previously addressed with general call; data has been received; ACK has been returned Load data byte X 0 0 0 data byte will be transmitted and NOT ACK should be received X 0 0 1 data byte will be transmitted and ACK should be received 98H Previously addressed with general call; data has been received; NOT ACK has been returned Load data byte 0 0 0 0 Switched to the not addressed Slave mode; no recognition of own SLA or GCA 0 0 0 1 Switched to the not addressed Slave mode; own SLA will be recognized; GCA will be recognized if GC = “1” 1 0 0 0 Switched to the not addressed Slave mode; no recognition of own SLA or GCA; a START condition will be transmitted when the bus becomes free 1 0 0 1 Switched to the not addressed Slave mode; own SLA will be recognized; GCA will be recognized if GC = “1”; a START condition will be transmitted when the bus becomes free A0H A STOP condition or repeated START condition has been received while still addressed as Slave NO TWIDAT action 0 0 0 0 Switched to the not addressed Slave mode; no recognition of own SLA or GCA 0 0 0 1 Switched to the not addressed Slave mode; own SLA will be recognized; GCA will be recognized if GC = “1” 1 0 0 0 Switched to the not addressed Slave mode; no recognition of own SLA or GCA; a START condition will be transmitted when the bus becomes free 1 0 0 1 Switched to the not addressed Slave mode; own SLA will be recognized; GCA will be recognized if GC = “1”; a START condition will be transmitted when the bus becomes free

S SLA+W Ack DATA Ack P or S Nack P or S Ack Reception of the own slave address and one or more data bytes, All are acknowledged Arbitration lost as master and addressed as slave receiver Last data byte received is not acknowledged 80H Ack DATA 80H SH88F6161 Actions Other Device Actions 88H A0H General Call Ack DATA Ack P or S Nack P or S Reception of general call address and one or more data bytes, All are acknowledged Arbitration lost as master and addressed as slave receiver by general call Last data byte received is not acknowledged 90H Ack DATA 70H 98H A0H 68H 60H 78H 90H Ack Miscellaneous States There are two status codes that do not correspond to a defined TWI state. Status 0xF8 indicates that no relevant information is available because the TWINT Flag is not set, and when the TWI is not involved in a serial transfer. Status 0x00 indicates that a bus error has occurred during a TWI Bus transfer. A bus error occurs when a START or STOP condition occurs at an illegal position in the format frame. Examples of such illegal positions are during the serial transfer of an address byte, a data byte, or an acknowledge bit. When a bus error occurs, TWINT is set and TWI switchs to 00H state. To recover from a bus error, the STO Flag must set and TWINT must be cleared.This causes the TWI to enter the not addressed Slave mode and to clear the STO Flag.The SDA and SCL lines are released, and no STOP condition is transmitted. Miscellaneous States Status TWI bus and serial interface hardware status Application software response Next Action Taken by TWI Hardware R/W data register TWIDAT operation Control bit operation STA STO TW INT AA F8H No relevant state information available; TWINT = “0” No TWIDAT action No TWICON action Wait or proceed current transfer 00H Bus error due to an illegal START or STOP condition No TWIDAT action 0 1 0 x Only the internal hardware is affected, the bus will be released,and s witchs to the not addressed Slave mode. STO will be cleared.

9.3.5 Register

Table 9.14 TWI Control Register C0H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TWICON TOUT ENTWI STA STO TWINT AA TFREE EFREE R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset Value (POR/WDT/LVR) 0 0 0 0 0 0 0 0 Bit Number Bit Mnemonic Description

7 TOUT

0: No Timeout 1: Timeout happened when the perio ds of bus low level is more than N X TSYS.Then the bit will be set. It can be cleared by sofware

6 ENTWI

0: Disable TWI 1: Enable TWI

5 STA

0: Not send START condition 1 :Send STA when the bus is free

4 STO

0 :Not send STOP condition 1 :Send STOP condition as Master Not send STOP condition as Slaver, but TWI switchs to the not addressed Slave mode The bit will be cleared by hardware automaticly.

3 TWINT

0: No interrupt happens 1: Generates TWI state except “0F8H” state The bit must be cleared by software. 2 AA TWI Enable Acknowledge Bit 0: Response “NAK” (SDA is high) 1: Response “ACK” (SDA is low)

1 TFREE

SCL TIMEOUT FLAG (HIGH VOLTAGE TIMEOUT) 0: No timeout happens 1: Timeout happens when the SCL keep high level more than TFREE (TFREE = TSYS X TWTFREE X 256) The bit must be cleared by software. Note: TFREE should be kept large than tSCL/2 (tSCL: Sysclk period)

0 EFREE

SCL TIMEOUT ENABLE BIT (HIGH VOLTAGE TIMEOUT) 0: Enable SCLTimeout detect 1: Disable SCL Timeout detect Note: TOUT, TWINT and TFREE can result TWI interurupt. And all of them share the same Vector Address.

Table 9.15 Timeout For Bus Low level Count Register C6H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TWTOUT CNT1 CNT0 - - - - - - R/W R/W R/W - - - - - - Reset Value (POR/WDT/LVR) 0 0 - - - - - - Bit Number Bit Mnemonic Description 7-6 CNT[1:0] Bus Timeout Count 00:N=25000 01:N=50000 10:N=100000 11:N=200000 Table 9.16 TWI Status Register C1H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 R/W R R R R R R/W R/W R/W Reset Value (POR/WDT/LVR) 1 1 1 1 1 0 0 0 Bit Number Bit Mnemonic Description 7-3 TWISTA [7:3] TWI Status 2-1 CR[0:1] TWI Prescaler Bits 00: 64 01: 16 10: 4 11: 1

0 ETOT

0: Enable Bus Timeout detect 1: Disable Bus Timeout detect Table 9.17 Timeout For Bus High level Count Register C7H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset Value (POR/WDT/LVR) 0 0 0 0 0 0 0 0 Bit Number Bit Mnemonic Description 7-0 TWTFREE[7:0] TWTFREE is used for Timeout detect

Table 9.18 TWI Bit Rate Register C2H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) 0 0 0 0 0 0 0 0 Bit Number Bit Mnemonic Description 7-0 TWIBR[7:0] selects the division factor for the bit rate generator Table 9.19 TWI (Slave) Address Register C3H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) 0 0 0 0 0 0 0 0 Bit Number Bit Mnemonic Description 7-1 TWIADR[6:0] TWI (Slave) Address Register: These seven bits constitute the slave address of the TWI unit 0 GC TWI General Call Recognition Enable Bit: 0: Disables the recognition of a General Call given over the 2-wire Serial Bus 1: Enables the recognition of a General Call given over the 2-wire Serial Bus Table 9.20 TWI Data Register C4H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) 0 0 0 0 0 0 0 0 Bit Number Bit Mnemonic Description 7-0 TWIDAT[7:0] These eight bits constitute the next data byte to be transmitted, or the latest data byte received on the 2-wire Serial Bus. Table 9.21 TWI (Slave) Address Mask Register C5H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 R/W R/W R/W R/W R/W R/W R/W R/W - Reset Value (POR/WDT/LVR/PIN) 0 0 0 0 0 0 0 - Bit Number Bit Mnemonic Description 7-1 TWIAMR[7:1] The TWIAMR can be loaded with a 7- bit Salve Address mask. Each of the bits in TWAMR can mask (disable) the corresponding address bits in the TWI Address Register ( TWIADR). If the mask bit is set to one then the address match logic ignores the compare between the incoming address bit and the corresponding bit in TWIADR.

9.4 Serial Peripheral Interface (SPI)

9.4.1 Features

 Full-duplex, three-wire synchronous transfers  Master or slave operation  Six programmable master clock rates  Serial clock with programmable polarity and phase  Master mode fault error flag with MCU interrupt capability  Write collision flag protection  Selectable LSB or MSB transfer The Serial Peripheral Interface (SPI) Module allows full -duplex, synchronous, serial communication between the MCU and peripheral devices, including other MCUs. The following diagram shows a typical SPI bus configuration using one master controller and many slave peripherals. The bus is made of three wires connecting all the devices. The master device selects the individual slave devices by using four pins of a parallel port to control the four SS ——— pins of the Slave devices. MISO MOSI SCK SS Master VDD Port0.0 Port0.1 Port0.2 Port0.3 MISO MOSI SCK SS Slave MISO MOSI SCK SS Slave MISO MOSI SCK SS Slave MISO MOSI SCK SS Slave

9.4.2 Signal Description

Master Output Slave Input (MOSI) This 1-bit signal is directly connected between the master device and slave devices. The MOSI line is used to transfer data in series from the master to the slave. Therefore, it is an output signal from the master, and an input signal to a slave. Master Input Slave Output (MISO) This 1-bit signal is directly connected between the slave devices and master device. The MISO line is used to transfer data in series from the slave to the master. Therefore, it is an output signal from the slave, and an input signal to the master. The MISO pin is placed in a high-impedance state when the SPI operates as a slave that is not selected (SS ——— high). A static high level on the SS ——— pin puts the MISO line of a slave in a high-impedance state. SPI Serial Clock (SCK) This signal is used to synchronize the data movement both in and out of the devices through their MOSI and MISO lines. It is driven by the master for eight clock periods, which allows exchanging one byte on the serial lines. The SCK signal is ignored by a SPI slave when the slave is not selected (SS ——— high). Slave Select (SS ——— Each slave peripheral is selected by one slave select pin (SS ——— ). This signal must stay low for any active slave. It is obvious that only one master (SS ——— high) can drive the network. The master may select each slave device by software through port pins. To prevent bus conflicts on the MISO line, only one slave should be selected at a time by the master for a transmission. In a master configuration, the SS ——— line can be used in conjunction with the MODF flag in the SPI status register to prevent multiple masters from driving MOSI and SCK. The SS ——— pin could be used as a general IO if the following conditions are met: (1) The device is configured as a master and the SSDIS control bit in SPCON is set. This kind of configuration can happen when only one master is driving the network. Therefore, the MODF flag in the SPSTA will never be set. (2) The device is configured as a slave with CPHA and SSDIS control bits set. This kind of configuration can happen when the network comprises only one master and one slave only. Therefore, the device should always be selected and the master will never use the slave’s SS ——— pin to select the target communication slave. Note: When CPHA = ‘0’, a falling edge of SS ——— pin is used to start the transmission. data wtitten in SPDAT register will be send.

9.4.3 Baud Rate

In master mode, the baud rate is chosen from one of the eight clock rates by the division of the internal clock by 2, 4, 8, 16, 32, 64, 128 or 256 set by the three bits SPR[2:0] in the SPCON register.

9.4.4 Functional Description

The following diagram shows a detailed structure of the SPI module. Internal Bus Clock Divider /128 /16 /32 /64 Clock Select Clock Logic SPI Control DIR MSTR CPHA CPOL SSDIS SPR2 SPR1 SPR0 SPEN SPIF MODF WCOL RXOV - - - SPSTA Pin Control Logic MOSI MISO SCK SS M S FCLK PERIPH Recieve Data Register SPI Interrupt Request 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Recieve Register Transmit Register SPDAT 8-bit Bus 1-bit Signal SPI Module Block Diagram

9.4.5 Operating Modes

The Serial Peripheral Interface can be configured as one of the two modes, master mode or slave mode. The configuration and initialization of the SPI module is made through SPCON (the serial peripheral control register) and SPSTA (the serial peripheral status register). Once the SPI is configured, the data exchange is made using SPCON, SPSTA and SPDAT (the serial peripheral data register). During an SPI transmission, data is simultaneously transmitted (shifted out serially) and received (s hifted in serially). A serial clock line (SCK) synchronizes shifting and sampling on the two serial data lines (MOSI and MISO). A slave select line ( SS ——— allows individual selection of a SPI slave; SPI slaves that are not selected do not interfere with SPI bus activities. When the SPI master transmits data to the SPI slave via the MOSI line, the SPI slave responds by sending data to the SPI master via the MISO line. This implies full-duplex transmission with both data out and data in synchronized with the same clock. Both transmit shift register and receive shift register uses the same SFR Address, a write operation to SPDAT will write to the transmit shift register, and a read operation from SPDAT will retrieve the data in receive shift register.

Full-Duplex Master-Slave Interconnection Diagram Master Mode (1) Enable A SPI master device initiates all data transfers on a SPI bus. The SPI operates in master mode when the MSTR is set in SPCON register. Only one master can initiate transmission. (2) Transmit When in SPI master mode, writing a byte of data to the SPI data register (SPDAT) will write to the transmit shift buffer. If the transmit shift register already contains dat a, the SPI master will generate a WCOL signal to indicate writing too fast. But the data in transmit shift register will not be affected, and the transmission continues uninterrupted. Else if the transmit shift register is empty, the SPI master will immediately shifts out the data serially on the MOSI line while providing the serial clock on SCK. The SPIF flag in SPSTA register is set to logic ‘1’ at the end of the transfer. If interrupts are enabled, an interrupt request is generated when the SPIF flag is set (3) Receive While the master transfers data to a slave on the MOSI line, the addressed slave simultaneously transfers the contents of its transmit shift register to the master’s receive shift register on the MISO line in a full-duplex operation. Therefore, the SPIF flag serves as both a transmit-complete and receive-data-ready flag. The data byte received from the slave is transferred MSB-first or LSB-first into the master's shift register. When a byte is fully shifted into the register, it is moved to the receive buffer where it can be read by the processor by reading SPDAT. If an overrun occurs, RXOV signal will be set to indicate data over-run occurs, and the receive shift register keep the byte that SPIF was lastly set, also the SPI master will not receive any further data until SPIF was cleared.During receiving a byte with SPIF cleared, the follwing byte cannot damage the last byte receiving until the last byte has been received. Slave Mode (1) Enable The SPI operates in slave mode when the MSTR is cleared in the SPCON register. Before a data transmission occurs, the slave select (SS ——— ) pin of the Slave device must be set to ‘0’. The SS ——— pin must remain low until the 1-byte transmission is complete. (2) Transmit & Receive When in SPI slave mode, bytes are shifted in through the MOSI pin and out through the MISO pin by a master device controlling the SCK signal. A bit counter counts SCK edges. When 8 bits have been shifted in the receive shift register and another 8 bits have been shifted out the transmit shift register, the SPIF flag is set to logic ‘1’. Data is read from the receive shift register by reading SPDAT. If interrupts are enabled, an interrupt request is generated when the SPIF flag is set. To prevent an overflow condition, the SPI slave software must clear the SPIF bit in SPSTA register before another byte enters the receive shift register. Else a RXOV signal will be set to indicate data over-run occurs, and the receive shift register keep the byte that SPIF was lastly set, also the SPI slave will not receive any further data until SPIF was cleared. A SPI slave cannot initiate transfers. Data to be transferred to the master device is pre-loaded into the shift register by writing to SPDAT. Writes to SPDAT are placed in the transmit buffer first. So a SPI slave must complete the write to the SPDAT (transmit shift register) in one SPI clock before the master starts a new transmission. If the write to SPDAT is late in the first transmission, the SPI slave will transmit a ‘0x00’ byte in the following transmission. if the write operation occurs during this time, a WC OL signal will be set. If the transmit shift register already contains data, the SPI slave will generate a WCOL signal to indicate writing too fast. But the data in transmit shift register will not be affected, and the transmission continues uninterrupted.

9.4.6 Transmission Formats

Software can select any of four combinations of serial clock (SCK) phase and polarity using two bits in the SPCON, the clock polarity CPOL and the clock phase CPHA. CPOL defines the default SCK line level in idle state. It has no significant effect o n the transmission format. CPHA defines the edges on which the input data are sampled and the edges on which the output data are shifted. The clock phase and polarity should be identical for the master and the communicating slave. SPEN (Internal) SCK (CPOL=0) SCK (CPOL=1) MOSI (from Master) bit6MSB bit5 bit4 bit3 bit2 bit1 LSB MISO (from Slave) bit6MSB bit5 bit4 bit3 bit2 bit1 LSB SS (to Slave) SCK Cycle Number 1 2 3 4 5 6 7 8 Capture Point Data Transmission Format (CPHA = 0) If CPHA = 0, the first SCK edge is the capture strobe. Therefore the slave must begin driving its data before the first SCK edge, and a falling edge on the SS ——— pin is used to start the transmission. The SS ——— pin must be toggled high and then low between each byte transmitted. So SSDIS bit is invalid when CPHA = 0. SPEN (Internal) SCK (CPOL=0) SCK (CPOL=1) MOSI (from Master) bit6MSB bit5 bit4 bit3 bit2 bit1 LSB MISO (from Slave) SCK Cycle Number 1 2 3 4 5 6 7 8 Capture Point bit6MSB bit5 bit4 bit3 bit2 bit1 LSB (to Slave)SS Data Transmission Format (CPHA = 1) If CPHA = 1, the master begins driving its MOSI pin on the first SCK edge. Therefore the slave uses the first SCK edge as a start transmission signal. So the user must put the SPDAT before the second edge of the first SCK. The SS ——— pin can remain l ow between transmissions. This format may be preferred in systems with only one master and only one slave. Byte1 Byte2 Byte3MISO/MOSI Master SS Slave SS (CPHA = 0) Slave SS (CPHA = 1) CPHA/SS ——— Timing Note: Before SPI is configured as Slave mode and CPOL bit in SPCON is cleared, the P2.4SCK pin must be set to input mode and enable pull-high resistor before SPEN bit in SPSTA is set to logic ‘1’.

9.4.7 Error detection

The following flags in the SPSTA signal SPI error conditions: (1) Mode Fault (MODF) Mode fault error in master mode SPI indicates that the level on the SS ——— pin is inconsistent with the actual mode of the device. MODF is set to warn that there may be a multi-master conflict for system control. In this case, the SPI system is affected in the following ways:  An SPI receiver/error CPU interrupt request is generated;  The SPEN bit in SPSTA is cleared. This disables the SPI;  The MSTR bit in SPCON is cleared. When SS ——— Disable (SSDIS bit in the SPCON register) is cleared, the MODF flag is set when the SS ——— signal becomes ‘0’. However, as stated before, for a system with one Master, if the SS ——— pin of the master device is pulled low, there is no way that another master attempts to drive the network. In this case, to prevent the MODF flag from being set, software can set the SSDIS bit in the SPCON register and therefore making the SS ——— pin as a general-purpose I/O pin. The user must clear the MODF bit by software, and enable SPEN in SPCON register again for further communication, and enable MSTR bit to continue master mode. (2) Write Collision (WCOL) A write collision (WCOL) flag in the SPSTA is set when a write to the SPDAT register is done during a transmit sequence. WCOL does not cause an interruption, and the transfer continues uninterrupted. The WCOL bit is cleared by software. (3) Overrun Condition (RXOV) An overrun condition occurs when the master or slave tries to send several data bytes and the slave or master has not cleared the SPIF bit issuing from the previous data byte transmitted. In this case, the receive shift register keep the byte that SPIF was lastly set, also the SPI device will not receive any further data until SPIF was cleared. The SPIF still keep on invoke inter rupt before it is cleared, though the transmission can still be driven by SCK. RXOV does not generate an interruption, the RXOV bit is cleared by software.

9.4.8 Interrupts

Two SPI status flags can generate a CPU interrupt requests SPIF & MODF. Serial Peripheral data transfer flag: SPIF. This bit is set by hardware when a transfer has been completed. Mode Fault flag: MODF. This bit becomes set to indicate that the level on the SS ——— pin is inconsistent with the mode of the SPI. MODF with SSDIS reset will generate receiver/error CPU interrupt requests. When SSDIS is set, no MODF interrupt request is generated. SPIF MODF SSDIS SPI Receiver/Error CPU Interrupt Request SPI Transmitter CPU Interrupt Request SPI CPU Interrupt Request SPI Interrupt Requests Generation

9.4.9 Registers

Table 9.22 Serial Peripheral Control Register F9H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SPCON DIR MSTR CPHA CPOL SSDIS SPR2 SPR1 SPR0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) 0 0 0 0 0 0 0 0 Bit Number Bit Mnemonic Description

7 DIR

Transfer Direction Selection 0: MSB first 1: LSB first

6 MSTR

0: Configure the SPI as a Slave 1: Configure the SPI as a Master

5 CPHA

0: Data sampled on first edge of SCK period 1: Data sampled on second edge of SCK period

4 CPOL

0: SCK line low in idle state 1: SCK line high in idle state

3 SSDIS

——— Disable 0: Enable SS ——— pin in both Master and Slave modes 1: Disable SS ——— pin in both master and slave modes MODF interrupt request will not generate, if SSDIS is set. In Slave mode, this bit has no effect if CPHA = 0. 2-0 SPR[2:0] Serial Peripheral Clock Rate 000: fSYS/2 001: fSYS/4 010: fSYS/8 011: fSYS/16 100: fSYS/32 101: fSYS/64 110: fSYS/128 111: fSYS/256

Table 9.23 Serial Peripheral Status Register F8H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SPSTA SPEN SPIF MODF WCOL RXOV - - - R/W R/W R/W R/W R/W R/W - - - Reset Value (POR/WDT/LVR/PIN) 0 0 0 0 0 - - - Bit Number Bit Mnemonic Description

7 SPEN

0: Disable the SPI interface 1: Enable the SPI interface

6 SPIF

Serial Peripheral data transfer flag 0: Clear by software 1: Set by hardware to indicate that the data transfer has been completed

5 MODF

0: Cleared by software 1: Set by hardware to indicate that the SS ——— pin is at inappropriate logic level

4 WCOL

0: Cleared by software to indicate write collision has bee processed 1: Set by hardware to indicate that a collision has been detected

3 RXOV

0: Cleared by software to indicate receive overrun has bee processed 1: Set by hardware to indicate that a receive overrun has been detected Table 9.24 Serial Peripheral Data Register FAH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SPDAT SPDAT7 SPDAT6 SPDAT5 SPDAT4 SPDAT3 SPDAT2 SPDAT1 SPDAT0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) 0 0 0 0 0 0 0 0 Bit Number Bit Mnemonic Description 7-0 SPDAT[7:0] A write to SPDAT places data directly into the transfer shift register. A Read of the SPDAT returns the value located in the receive shift register Note: When SPI is disabled, reading SPDAT is invalid.

9.5 EUART0/EUART1

9.5.1 Features

 The SH88F6161/SH88F6162 has two enhanced EUART compatible with 8051  EUART0/EUART1 with own baud rate generator,and system clock devided or own baud rate generator overflow rate devided by 16 can be selected as baud rate  Enhancements over the standard 8051 the EUART include Framing Error detection and automatic address recognition  EUART0/EUART1can be operated in four modes

9.5.2 EUART0

The EUART0 can be operated in 4 modes. Users must initialize the SCON before an y communication can take place. This involves selection of the Mode and the baud rate. In all of the 4 modes, transmission is initiated by any instruction that uses SBUF as a destination register. Reception is initiated in Mode 0 by the condition RI = 0 and REN = 1. This will generate a clock on the TxD pin and shift in 8 bits on the RxD pin. Reception is initiated in the other modes by the incoming start bit if RI = 0 and REN = 1. The external transmitter will star t the communication by transmitting the start bit. EUART0 Mode Summary SM0 SM1 Mode Type Baud Clock Frame Size Start Bit Stop Bit 9th bit 0 0 0 Sych fSYS/(4 or 12) 8 bits NO NO None 0 1 1 Ansych own baud rate/16 10 bits 1 1 None 1 0 2 Ansych fSYS/(32 or 64) 11 bits 1 1 0, 1 1 1 3 Ansych own baud rate/16 11 bits 1 1 0, 1 Mode0: Synchronous Mode, Half duplex This mode provides synchronous communication with external devices. In this mode serial data is transmitted and received on the RxD line. TxD is used to output the shift clock. The TxD clock is provided by the SH88F6161/SH88F6162whether the device is transmitting or receiving. This mode is therefore a half duplex mode of serial communication. In this mode, 8 bits are transmitted or received per frame. The LSB is transmitted/received first. The baud rate is programmable to either 1/12 or 1/4 of the system clock. This baud rate is determined in the SM2 bit (SCON.5). When this bit is set to 0, the serial port runs at 1/12 of the system clock. When set to 1, the serial port runs at 1/4 of the system clock. The functional block diagram is shown below. Data enters and exits the serial port on the RxD line. The TxD line is used to output the SHIFT CLOCK. The SHIFT CLOCK is used to shift data into and out of the SH88F6161/SH88F6162. 12 4 SERIAL CONTROLLER TX CLOCK TX START TX SHIFT TI RI SHIFT CLOCK RX CLOCK LOAD SBUF RX START RX SHIFT Transmit Shift Register RXD Serial Port Interrupt TXD RI REN PARIN LOAD CLOCK SOUT CLOCK SIN PAROUT RXD SBUF Read SBUF Receive Shift Register Internal Data Bus Write to SBUF SBUF ÷ ÷ System Clock SM2

Any instruction that uses SBUF as a destination register (“write to SBUF” signal) will start the transmission. The next system clock tells the Tx control block to commence a transmission. The data shift occurs at the falling edge of the SHIFT CLOCK, and the contents of the transmit shift register is shifted one position to the right. As data bits shift to the right, zeros come in from the left. After transmission of all 8 bits in the transmit shift register, the Tx control block will deactivates SEND and sets TI (SCON.1) at the rising edge of the next system clock. Write to SBUF D0 D1 D2 D3 D4 D5 D6 D7 RxD TI Send Timing of Mode 0 TxD Reception is initiated by the condition REN (SCON.4) = 1 and RI (SCON.0) = 0. The next system clock activates RECEIVE. The data latch occurs at the rising edge of the SHIFT CLOCK, and the contents of the receive shift register are shifted one position to the left. After the receiving of all 8 bits into the receive shift register, the RX control block will deactivates RECEIVE and sets RI at the rising edge of the next system clock, and the reception will not be enabled till the RI is cleared by software. RxD D0 D1 D2 D3 D4 D5 D6 D7 RI Receive Timing of Mode 0 TxD Mode1: 8-Bit EUART, Variable Baud Rate, Asynchronous Full-Duplex This mode provides the 10 bits full duplex asynchronous communication. The 10 bits consist of a start bit (logical 0), 8 data bits (LSB first), and a stop bit (logical 1). When receiving, the eight data bits are stored in SBUF and the stop bit goes into RB 8 (SCON.2). The baud rate in this mode is 1/16 of own baud rate. The functional block diagram is shown below. SERIAL CONTROLLER TX CLOCK TX START TX SHIFT TI RI RX CLOCK LOAD SBUF RX START RX SHIFT TXD PARIN LOAD CLOCK SOUT CLOCK SIN PAROUT RXD Read SBUF Internal Data Bus Receive Shift Register Internal Data Bus 16÷ 16÷ 1-TO-0 DETECTOR Write to SBUF BIT DETECTOR D8 SBUF RB8 Transmit Shift Register STOP START SAMPLE Serial Port Interrupt Baud rate Generator overflow From 7FFF to 0000

Transmission begins with a “write to SBUF” signal, and it actually commences at the next system clock following the next rollover in the divide-by-16 counter (divide baud-rate by 16), thus, the bit times are synchronized to the divide-by -16 counter, not to the “write to SUBF” signal. The start bit is firstly put out on TxD pin, then are the 8 bits of data. After all 8 bits of data in the transmit shift register are transmitted, the stop bit is put out on the TxD pin, and the TI flag is set at the same time that the stop is send. Write to SBUF Shift CLK D0 D1 D2 D3 D4 D5 D6 D7 TxD StopStart TI Send Timing of Mode 1 Reception is enabled only if REN is high. The serial port actually starts the receiving of serial data with the detection of a falling edge on the RxD pin. For this purpose RxD is sampled at the rate of 16 times baud rate. When a falling edge is detected, the divide-by-16 counter is immediately reset. This helps to align the bit boundaries with the rollovers of the divide- by-16 counter.The 16 states of the counter divide each bit time into 16ths. The bit detector samples the value of RxD at the 7 th, 8th and 9th counter states of each bit time. The value accepted is the value that was seen in at least 2 of the 3 samples. This is done for noise rejection. If the first bit after the falling edge of RxD pin is not 0, which indicates an invalid start bit, and the r eception is immediately aborted. The receive circuits are reset and again waiting for a falling edge in the RxD line. If a valid start bit is detected, then the rest of the bits are also detected and shifted into the shift register. After shifting in 8 data bits and the stop bit, the SBUF and RB8 are loaded and RI are set if the following conditions are met: (1) RI must be 0 (2) Either SM2 = 0, or the received stop bit = 1 If these conditions are met, then the stop bit goes to RB8, the 8 data bits go into SBUF and RI is set. Otherwise the receive d frame may be lost. At the time, the receiver goes back to looking for another falling edge on the RxD pin. And the user should clear RI by software for further reception Receive Timing of Mode 1 D0 D1 D2 D3 D4 D5 D6 D7 RxD StopStart Bit Sample Shift CLK RI

Mode2: 9-Bit EUART, Fixed Baud Rate, Asynchronous Full-Duplex This mode provides the 11 bits full duplex asynchronous communication. The 11 bits consists of one start bit (logical 0), 8 data bits (LSB first), a programmable 9 th data bit, and a stop bit (logical 1). Mode 2 supports multiprocessor communications and hardware address recognition (Refer to Multiprocessor Communication Sect ion for details). When data is transmitted, the 9 th data bit (TB8 in SCON) can be assigned the value of 0 or 1, for example, the parity bit P in the PSW or used as data/address flag in multiprocessor communications. When data is received, the 9th data bit goes into RB8 and the stop bit is not saved. The baud rate is programmable to either 1/32 or 1/64 of the system working frequency, as determined by the SMOD bit in PCON. The functional block diagram is shown below: SERIAL CONTROLLER TX CLOCK TX START TX SHIFT TI RI RX CLOCK LOAD SBUF RX START RX SHIFT TXD Serial Port Interrupt PARIN LOAD CLOCK SOUT CLOCK SIN PAROUT RXD Read SBUF Internal Data Bus Receive Shift Register Internal Data Bus 32÷ 32÷ 1-TO-0 DETECTOR Write to SBUF BIT DETECTOR D8 SBUF RB8 Transmit Shift Register STOP START SAMPLE D8TB8 SMOD System Clock Transmission begins with a “write to SBUF” signal, the “write to SBUF” signal also loads TB8 into the 9 th bit position of the transmit shift register. Transmission actually commences at the next system clock following the next rollover in the divide-by-16 counter (thus, the bit times are synchronized to the divide-by-16 counter, not to the “write to SUBF” signal). The start bit is firstly put out on TxD pin, then are the 9 bits of data. After all 9 bits of data in the transmit shift register are transmitted, the stop bit is put out on the TxD pin, and the TI flag is set at the same time, this will be at the 11th rollover of the divide-by-16 counter after a write to SBUF. Write to SBUF Shift CLK TI Send Timing of Mode 2 TxD D8D0 D1 D2 D3 D4 D5 D6 D7Start Stop

Reception is enabled only if REN is high. The serial port actually starts the receiving of serial data, with the detection of a falling edge on the RxD pin. For this purpose RxD is sampled at the rate of 16 times baud rate. When a falling edge is detected, the divide-by-16 counter is immediately reset. This helps to align the bit boundaries with the rollovers of the divide-by-16 counter. The 16 states of the counter divide each bit time into 16ths. The bit detector samples the value of RxD at the 7 th, 8th and 9th counter state of each bit time. The value accepted is the val ue that was seen in at least 2 of the 3 samples. This is done for noise rejection. If the first bit detected after the falling edge of RxD pin is not 0, which indicates an invalid start bit, and the reception is immediately aborted. The receive circuits are reset and again looks for a falling edge in the RxD line. If a valid start bit is detected, then the rest of the bits are also detected and shifted into the shift register. After shifting in 9 data bi ts and the stop bit, the SBUF and RB8 are loaded and RI is set if the following conditions are met: (1) RI must be 0 (2) Either SM2 = 0, or the received 9th bit = 1 and the received byte accords with Given Address If these conditions are met, then the 9th bit goes to RB8, the 8 data bits go into SBUF and RI is set. Otherwise the received frame may be lost. At the time, the receiver goes back to looking for another falling edge on the RxD pin. And the user should clear RI by software for further reception. Shift CLK RxD Bit Sample D0 D1 D2 D3 D4 D5 D6 D7 D8Start Stop RI Receive Timing of Mode 2 Mode3: 9-Bit EUART, Variable Baud Rate, Asynchronous Full-Duplex Mode3 uses transmission protocol of the Mode2 and baud rate generation of the Mode1. SERIAL CONTROLLER TX CLOCK TX START TX SHIFT TI RI RX CLOCK LOAD SBUF RX START RX SHIFT Serial Port Interrupt CLOCK SIN PAROUT RXD Read SBUF Internal Data Bus Receive Shift Register 16÷ 16÷ 1-TO-0 DETECTOR Write to SBUF BIT DETECTOR D8 SBUF RB8 SAMPLE TXDPARIN LOAD CLOCK SOUT Internal Data Bus Transmit Shift Register START D8TB8 STOP Baud rate Generator overflow From 7FFF to 0000

The baud rate generator is an 15-bit up-counting timer. 15-bit timer \` To EUART Overflow Fsys From 7FFFH to 0000H SBRTH[14:8],SBRTL7:0] Baudrate Generator for EUART SBRTEN=1 The overflow rate of baud rate generator can be calculated as follow: SBRT FsysowrateSBRToverfl −= 32768 , ],[ SBRTLSBRTHSBRT = In Mode0, the baud rate is programmable to either 1/12 or 1/4 of the system frequency. This baud rate is determined by SM2 bit. When set to 0, the serial port runs at 1/12 of the system clock. When set to 1, the serial port runs at 1/4 of the system clock. In Mode1 & Mode3, the baud rate can be fine adjusted. The Mode1 & 3 baud rate equations are shown below, ( ) BFINESBRT FBaudRate +×= -3276816 sys For example: Fsys = 8MHz, to get 115200Hz baud rate, computing method of SBRT and SFINE as shown below: 8000000/16/115200 = 4.34 SBRT = 32768 - 4 = 32764 115200 = 8000000/(16 X 4 + BFINE) BFINE = 5.4 ≈ 5 This fine tuning method to calculate the actual baud rate is 115942Hz and the error is 0.64%, but the error is 8.5% In the past computing method. In Mode2, the baud rate is programmable to either 1/32 or 1/64 of the system clock. This baud rate is determined by the SMOD bit (PCON.7). When this bit is set to 0, the serial port runs at 1/64 of the clock. When set to 1, the serial port runs at 1/32 of the clock. )64(2 SYSSMOD fBaudRate ×=

Multi-Processor Communication Software Address Recognition Modes 2 and 3 of the EUART 0 have a special provision for multi -processor communication. In these modes, 9 data bits are received. The 9th bit goes into RB8. Then a stop bit follows. The EUART 0 can be programmed such that when the stop bit is received, the EUART0 interrupt will be activated (i.e. the request flag RI is set) only if RB8 = 1. This feature is enabled by setting the bit SM2 in SCON. A way to use this feature in multiprocessor communications is as follows. lf the master processor wants to transmit a block of data to one of the several slaves, it first sends out an address byte which identifies the target slave. An address byte differs from a data byte in that the 9th bit is 1 in an address byte and 0 in a data byte. With SM2 = 1, no other slave will be interrupted by a data byte. An address byte, however, will interrupt all slaves, so that each slave can examine the received byte and see if it is being addressed. The addressed slave will clear its SM2 bit and prepare to receive the data bytes that will be coming. After having received a complete message, the slave sets SM2 again. The slaves that were not addressed leave their SM2 set and go on with their business, ignoring the incoming data bytes. Note: In Mode0, SM2 is used to select baud rate doubling. In Mode1, SM2 can be used to check the validity of the stop bit. If SM2 = 1 in Mode1, the receive interrupt will not be activated unless a valid stop bit is received. Automatic (Hardware) Address Recognition In Mode2 & 3, setting the SM2 bit will configure EUART0 act as following: when a stop bit is received, EUART0 will generate an interrupt only if the 9 th bit that goes into RB8 is logic 1 (address byte) and the received data byte matches the EUART 0 slave address. Following the received address interrupt, the slave should clear its SM2 bit to enable interrupts on the reception of the following data byte(s). The 9-bit mode requires that the 9th information bit is a 1 to indicate that the received information is an address and not data. When the master processor wants to transmit a block of data to one of the slaves, it first sends out the address of the targeted slave (or slaves). All the slave processors should have their SM2 bit set high when waiting for an address byte, which ensures that they will be interrupted only by the reception of an address byte. The Automatic address recognition feature further ensures that only the addressed slave will be interrupted. The address comparison is done by hardware not software. After being interrupted, the addressed s lave clears the SM2 bit to receive data bytes. The un-addressed slaves will be unaffected, as they will be still waiting for their address. Once the entire message is received, the addressed slave should set its SM2 bit to ignore all transmissions until it receives the next address byte. The Automatic Address Recognition feature allows a master to selectively communicate with one or more slaves by invoking the Given Address. All of the slaves may be contacted by using the Broadcast address. Two special Func tion Registers are used to define the slave’s address, SADDR, and the address mask, SADEN. The slave address is an 8-bit value specified in the SADDR register. The SADEN register is actually a mask for the byte value in SADDR. If a bit position in SADEN is 0, then the corresponding bit position in SADDR is don’t care. Only those bit positions in SADDR whose corresponding bits in SADEN are 1 are used to obtain the Given Address. This gives the user flexibility to address multiple slaves without changing the slave address in SADDR. Use of the Given Address allows multiple slaves to be recognized while excluding others. Slave 1 Slave 2 SADDR 10100100 10100111 SADEN (0 mask) 11111010 11111001 Given Address 10100x0x 10100xx1 Broadcast Address (OR) 1111111x 11111111 The Given address for slave 1 and 2 differ in the LSB. For slave 1, it is a don’t care, while for slave 2 it is 1. Thus to communicate only with slave 1, the master must send an address with LSB = 0 (10100000). Similarly the bit 1 is 0 for slave 1 and don’t care for slave 2. Hence to communicate only with slave 2 the master has to transmit an address with bit 1 = 1 (1010 0011). If the master wishes to communicate with both slaves simultaneously, then the address must have bit 0 = 1 and bit 1 = 0. T he bit 2 position is don’t care for both the slaves. This allows two different addresses to select both slaves (1010 0001 and 1010 0101). The master can communicate with all the slaves simultaneously with the Broadcast Address. This address is formed from the logical OR of the SADDR and SADEN. The zeros in the result are defined as don’t cares. In most cases, the Broadcast Address is FFh, this address will be acknowledged by all slaves. On reset, the SADDR and SADEN are initialized to 00h. This results in Given Address and Broadcast Address being set as XXXXXXXX (all bits don’t care). This effectively removes the multiprocessor communications feature, since any selectivity is disabled. This ensures that the EUART 0 will reply to any address, which it is backwards compatible with the 80C51 microcontrollers that do not support automatic address recognition. So the user may implement multiprocessor by software address recognition mentioned above.

Error detection is available when the SSTAT bit in register PCON is set to logic 1.The SSTAT bit must be logic 1 to access any of the status bits (FE, RXOV, and TXCOL). The SSTAT bit must be logic 0 to access the Mode Select bits (SM0, SM1, and SM2). All the 3 bits should be cleared by software after they are set, even when the following frames received without any error will not be cleared automatically. Transmit Collision The Transmit Collision bit (TXCOL bit in register SCON) reads ‘1’ if RI is set 0 and user software writes data to the SBUF register while a transmission is still in progress. If this occurs, the new data will be ignored and the transmit buffer will not be written. Receive Overrun The Receive Overrun bit (RXOV in register SCON) reads ‘1’ if a new data byte is latched into the receive buffer before software has read the previous byte. The previous data is lost when this happen. Frame Error The Frame Error bit (FE in register SCON) reads ‘1’ if an invalid (low) STOP bit is detected. Note: Before transmitting, TXD pin must be setted output high. Registers Table 9.25 Power Control Register 87H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PCON SMOD SSTAT - - GF1 GF0 PD IDL R/W R/W R/W - - R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) 0 0 - - 0 0 0 0 Bit Number Bit Mnemonic Description

7 SMOD

0: in Mode2, the baud-rate of EUART is 1/64 of the system clock 1: in Mode2, the baud-rate of EUART is 1/32 of the system clock

6 SSTAT

SCON[7:5] function select bit 0: SCON[7:5] operates as SM0, SM1, SM2 1: SCON[7:5] operates as FE, RXOV, TXCOL 3-2 GF[1:0] General purpose flags for software use

1 PD Power-Down mode control bit

0 IDL Idle mode control bit

Table 9.26 EUART0 Control & Status Register 98H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SCON SM0 /FE SM1 /RXOV SM2 /TXCOL REN TB8 RB8 TI RI R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) 0 0 0 0 0 0 0 0 Bit Number Bit Mnemonic Description 7-6 SM[0:1] EUART0 Serial mode control bits, when SSTAT = 0 00: mode 0, Synchronous Mode, fixed baud rate 01: mode 1, 8-bit Asynchronous Mode, variable baud rate 10: mode 2, 9-bit Asynchronous Mode, fixed baud rate 11: mode 3, 9-bit Asynchronous Mode, variable baud rate (to be continued)

(continue) 7 FE EUART0 Frame Error flag, when FE bit is read, SSTAT bit must be set 1 0: No Frame Error, clear by software 1: Frame error occurs, set by hardware

6 RXOV

EUART0 Receive Over flag, when RXOV bit is read, SSTAT bit must be set 1 0: No Receive Over, clear by software 1: Receive over occurs, set by hardware

5 SM2

EUART0 Multi-processor communication enable bit (9th bit ‘1’ checker), when SSTAT = 0 0: In Mode0, baud-rate is 1/12 of system clock In Mode1, disable stop bit validation check, any stop bit will set RI to generate interrupt In Mode2 & 3, any byte will set RI to generate interrupt 1: In Mode0, baud-rate is 1/4 of system clock In Mode1, Enable stop bit validation check, only valid stop bit (1) will set RI to generate interrupt In Mode2 & 3, only address byte (9th bit = 1) will set RI to generate interrupt

5 TXCOL

EUART0Transmit Collision flag, when TXCOL bit is read, SSTAT bit must be set 1 0: No Transmit Collision, clear by software 1: Transmit Collision occurs, set by hardware

4 REN

EUART0 Receiver enable bit 0: Receive Disable 1: Receive Enable

3 TB8 The 9th bit to be transmitted in Mode2 & 3 of EUART0, set or clear by software

2 RB8

The 9th bit to be received in Mode1, 2 & 3 of EUART0 In Mode0, RB8 is not used In Mode1, if receive interrupt occurs, RB8 is the stop bit that was received In Mode2 & 3 it is the 9th bit that was received 1 TI Transmit interrupt flag of EUART0 0: cleared by software 1: Set by hardware at the end of the 8th bit time in Mode0, or at the beginning of the stop bit in other modes 0 RI Receive interrupt flag of EUART0 0: cleared by software 1: Set by hardware at the end of the 8th bit time in Mode0, or during the stop bit time in other modes Table 9.27 EUART0 Data Buffer Register 99H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) 0 0 0 0 0 0 0 0 Bit Number Bit Mnemonic Description 7-0 SBUF[7:0] This SFR accesses two registers; a transmit shift register and a receive latch register A write of SBUF will send the byte to the transmit shift register and then initiate a transmission A read of SBUF returns the contents of the receive latch

Table 9.28 EUART0 Slave Address & Address Mask Register 9AH-9BH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) 0 0 0 0 0 0 0 0 Bit Number Bit Mnemonic Description 7-0 SADDR[7:0] SFR SADDR defines the EUART0’s slave address 7-0 SADEN[7:0] SFR SADEN is a bit mask to determine which bits of SADDR are checked 0: Corresponding bit in SADDR is a “don’t care” 1: Corresponding bit in SADDR is checked against a received address Table 9.29 EUART0 Baudrate Generator Register 9CH-9DH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) 0 0 0 0 0 0 0 0 Bit Number Bit Mnemonic Description

7 SBRTEN

EUART0Baudrate enable control bit 0: disable (deault) 1: enable 6-0, 7-0 SBRT[14:0] EUART0 Baudrate bits Table 9.30 EUART0 Baudrate Generator fine-tune Register 9EH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFINE - - - - SFINE.3 SFINE.2 SFINE.1 SFINE.0 R/W - - - - R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) - - - - 0 0 0 0 Bit Number Bit Mnemonic Description 3-0 SFINE[3:0] EUART0 Baudrate generator fine-tune register

9.5.3 EUART1

The EUART1can be operated in 4 modes. Users must initialize the SCON 1 before any communication can take place. This involves selection of the Mode and the baud rate. In all of the 4 modes, transmission is initiated by any instruction that uses SBUF1 as a destination register. Reception is initiated in Mode 0 by the condition RI1 = 0 and REN1 = 1. This will generate a clock on the TxD1 pin and shift in 8 bits on the RxD1 pin. Reception is initiated in the other modes by the incoming start bit if RI1 = 0 and REN1 = 1. The external transmitter will start the communication by transmitting the start bit. EUART1 Mode Summary SM10 SM11 Mode Type Baud Clock Frame Size Start Bit Stop Bit 9th bit 0 0 0 Sych fSYS/(4 or 12) 8 bits NO NO None 0 1 1 Ansych own baud rate/16 10 bits 1 1 None 1 0 2 Ansych fSYS/(32 or 64) 11 bits 1 1 0, 1 1 1 3 Ansych own baud rate/16 11 bits 1 1 0, 1 Mode0: Synchronous Mode, Half duplex This mode provides synchronous communication with external devices. In this mode serial data is transmitted and received on the RxD1 line. TxD1 is used to output the shift clock. The TxD 1 clock is provided by the SH88F6161/SH88F6162whether the device is transmitting or receiving. This mode is therefore a half duplex mode of serial communication. In this mode, 8 bits are transmitted or received per frame. The LSB is transmitted/received first. The baud rate is programmable to either 1/12 or 1/4 of the system clock. This baud rate is determined in the SM2 bit (SCON1.5). When this bit is set to 0, the serial port runs at 1/12 of the system clock. When set to 1, the serial port runs at 1/4 of the system clock. The functional block diagram is shown below. Data enters and exits the serial port on the RxD1 line. The TxD 1line is used to output the SHIFT CLOCK. The SHIFT CLOCK is used to shift data into and out of the SH88F6161/SH88F6162. 12 4 SERIAL CONTROLLER TX1 CLOCK TX1 START TX1 SHIFT TI1 RI1 SHIFT CLOCK RX1 CLOCK LOAD SBUF1 RX1 START RX1 SHIFT Transmit Shift Register RXD1 Serial Port Interrupt TXD1 RI1 REN1 PARIN LOAD CLOCK SOUT CLOCK SIN PAROUT RXD1 SBUF1 Read SBUF1 Receive Shift Register Internal Data BusWrite to SBUF1 SBUF1 ÷ ÷ System Clock SM12

Any instruction that uses SBUF1 as a destination register (“write to SBUF1” signal) will start the transmission. The next system clock tells the Tx control block to commence a transmission. The data shift occurs at the falling edge of the SHIFT CLOCK, and the contents of the transmit shift register is shifted one position to the right. As data bits shift to the right, zeros come in from the left. After transmission of all 8 bits in the transmit shift register, the Tx control block will deactivates SEND and sets TI 1(SCON1.1) at the rising edge of the next system clock. Write to SBUF1 D0 D1 D2 D3 D4 D5 D6 D7 RXD1 TI1 Send Timing of Mode 0 TXD1 Reception is initiated by the condition REN 1 (SCON1.4) = 1 and RI 1 (SCON1.0) = 0. The next system clock activates RECEIVE. The data latch occurs at the rising edge of the SHIFT CLOCK, and th e contents of the receive shift register are shifted one position to the left. After the receiving of all 8 bits into the receive shift register, the RX control block will deactivates RECEIVE and sets RI1 at the rising edge of the next system clock, and the reception will not be enabled till the RI1 is cleared by software. RXD1 D0 D1 D2 D3 D4 D5 D6 D7 RI1 Receive Timing of Mode 0 TXD1 Mode1: 8-Bit EUART1, Variable Baud Rate, Asynchronous Full-Duplex This mode provides the 10 bits full duplex asynchronous communication. The 10 bits consist of a start bit (logical 0), 8 data bits (LSB first), and a stop bit (logical 1). When receiving, the eight data bits are stored in SBUF and the stop bit goes into RB 81 (SCON1.2). The baud rate in this mode is 1/16 of own baud rate. The functional block diagram is shown below. SERIAL CONTROLLER TX1 CLOCK TX1 START TX1 SHIFT TI1 RI1 RX1 CLOCK LOAD SBUF1 RX1 START RX1 SHIFT TXD1 PARIN LOAD CLOCK SOUT CLOCK SIN PAROUT RXD1 Read SBUF1 Internal Data Bus Receive Shift Register Internal Data Bus 16÷ 16÷ 1-TO-0 DETECTOR Write to SBUF1 BIT DETECTOR D8 SBUF1 RB81 Transmit Shift Register STOP START SAMPLE Serial Port Interrupt Baud rate Generator overflow From 7FFF to 0000

Transmission begins with a “write to SBUF 1” signal, and it actually commences at the next system clock following the next rollover in the divide-by-16 counter (divide baud-rate by 16), thus, the bit times are synchronized to the divide-by -16 counter, not to the “write to SUB1F” signal. The start bit is firstly put out on TxD1 pin, then are the 8 bits of data. After all 8 bits of data in the transmit shift register are transmitted, the stop bit is put out on the TxD1 pin, and the TI flag is set at the same time that the stop is send. Write to SBUF1 Shift CLK D0 D1 D2 D3 D4 D5 D6 D7 TXD1 StopStart TI1 Send Timing of Mode 1 Reception is enabled only if REN1 is high. The serial port actually starts the receiving of serial data with the detection of a falling edge on the RxD1 pin. For this purpose RxD1 is sampled at the rate of 16 times baud rate. When a falling edge is detected, the divide-by-16 counter is immediately reset. This helps to align the bit boundaries with the rollovers of the divide- by-16 counter.The 16 states of the counter divide each bit time into 16ths. The bit detector samples the value of RxD 1 at the 7th, 8th and 9th counter states of each bit time. The value accepted is the value that was seen in at least 2 of the 3 samples. This is done for noise rejection. If the first bit after the falling edge of RxD1 pin is not 0, which indicates an invalid start bit, and the reception is immediately aborted. The receive circuits are reset and again waiting for a falling edge in the RxD1 line. If a valid start bit is detected, then the rest of the bits are also detected and shifted into the shift register. After shifting in 8 data bits and the stop bit, the SBUF and RB81 are loaded and RI1 are set if the following conditions are met: (1) RI1 must be 0 (2) Either SM12 = 0, or the received stop bit = 1 If these conditions are met, then the stop bit goes to RB81, the 8 data bits go into SBUF1 and RI1 is set. Otherwise the received frame may be lost. At the time, the receiver goes back to looking for another falling edge on the RxD 1 pin. And the user should clear RI 1 by software for further reception. Receive Timing of Mode 1 D0 D1 D2 D3 D4 D5 D6 D7 RXD1 StopStart Bit Sample Shift CLK RI1

Mode2: 9-Bit EUART1, Fixed Baud Rate, Asynchronous Full-Duplex This mode provides the 11 bits full duplex asynchronous communication. The 11 bits consists of one start bit (logical 0), 8 data bits (LSB first), a programmable 9 th data bit, and a stop bit (logical 1). Mode 2 supports multiprocessor communications and hardware address recognition (Refer to Multiprocessor Communication Section for details). When data is transmitted, the 9 th data bit (TB8 in SCON1) can be assigned the value of 0 or 1, for example, the parity bit P in the PSW or used as data/address flag in multiprocessor communications. When data is received, the 9th data bit goes into RB81 and the stop bit is not saved. The baud rate is programmable to either 1/32 or 1/64 of the system working frequency, as determined by the SMOD1 bit in PCON1. SERIAL CONTROLLER TX CLOCK TX START TX SHIFT TI RI RX CLOCK LOAD SBUF RX START RX SHIFT TXD Serial Port Interrupt PARIN LOAD CLOCK SOUT CLOCK SIN PAROUT RXD Read SBUF Internal Data Bus Receive Shift Register Internal Data Bus 32÷ 32÷ 1-TO-0 DETECTOR Write to SBUF BIT DETECTOR D8 SBUF RB8 Transmit Shift Register STOP START SAMPLE D8TB8 SMOD System Clock Transmission begins with a “write to SBUF1” signal, the “write to SBUF1” signal also loads TB81 into the 9th bit position of the transmit shift register. Transmission actually commences at the next system clock following the next rollover in the divide-by-16 counter (thus, the bit times are synchronized to the divide-by-16 counter, not to the “write to SUBF” signal). The start bit is firstly put out on TxD1 pin, then are the 9 bits of data. After all 9 bits of data in the transmit shift register are transmitted, the stop bit is put out on the TxD1 pin, and the TI flag is set at the same time, this will be at the 11th rollover of the divide-by-16 counter after a write to SBUF1. Write to SBUF1 Shift CLK TI1 Send Timing of Mode 2 TXD1 D8D0 D1 D2 D3 D4 D5 D6 D7Start Stop

Reception is enabled only if REN 1 is high. The serial port actually starts the receiving of serial data, with the detection of a falling edge on the RxD 1 pin. For this purpose RxD 1 is sampled at the rate of 16 times baud rate. When a falling edge is detected, the divide-by -16 counter is immediately reset. This helps to align the bit boundaries with the rollov ers of the divide-by-16 counter. The 16 states of the counter divide each bit time into 16ths. The bit detector samples the value of RxD1 at the 7th, 8th and 9th counter state of each bit time. The value accepted is the value that was seen in at least 2 of the 3 samples. This is done for noise rejection. If the first bit detected after the falling edge of RxD1 pin is not 0, which indicates an invalid start bit, and the reception is immediately aborted. The receive circuits are reset and again looks for a falling edge in the RxD1 line. If a valid start bit is detected, then the rest of the bits are also detected and shifted into the shift register. After shifting in 9 data bits and the stop bit, the SBUF1 and RB81 are loaded and RI is set if the following conditions are met: (1) RI1 must be 0 (2) Either SM12 = 0, or the received 9th bit = 1 and the received byte accords with Given Address If these conditions are met, then the 9 th bit goes to RB8, the 8 data bits go into SBUF 1 and RI is set. Otherwise the received frame may be lost. At the time, the receiver goes back to looking for another falling edge on the RxD 1 pin. And the user should clear RI 1 by software for further reception. Shift CLK RXD1 Bit Sample D0 D1 D2 D3 D4 D5 D6 D7 D8Start Stop RI1 Receive Timing of Mode 2 Mode3: 9-Bit EUART1, Variable Baud Rate, Asynchronous Full-Duplex Mode3 uses transmission protocol of the Mode2 and baud rate generation of the Mode1. SERIAL CONTROLLER TX CLOCK TX START TX SHIFT TI RI RX CLOCK LOAD SBUF RX START RX SHIFT Serial Port Interrupt CLOCK SIN PAROUT RXD Read SBUF Internal Data Bus Receive Shift Register 16÷ 16÷ 1-TO-0 DETECTOR Write to SBUF BIT DETECTOR D8 SBUF RB8 SAMPLE TXDPARIN LOAD CLOCK SOUT Internal Data Bus Transmit Shift Register START D8TB8 STOP Baud rate Generator overflow From 7FFF to 0000

The baud rate generator is an 15-bit up-counting timer. 15-bit timer \` To EUART1Overflow Fsys From 7FFFH to 0000H SBRTH1[14:8],SBRTL1[7:0] Baudrate Generator for EUART1 SBRTEN1=1 The overflow rate of baud rate generator can be calculated as follow:

132768 SBRT

FsysowrateSBRToverfl −= , ]1,1[1 SBRTLSBRTHSBRT = In Mode0, the baud rate is programmable to either 1/12 or 1/4 of the system frequency. This baud rate is determined by SM12 bit. When set to 0, the serial port runs at 1/12 of the system clock. When set to 1, the serial port runs at 1/4 of the system clock. In Mode1 & Mode3, the baud rate can be fine adjusted. The Mode1 & 3 baud rate equations are shown below, ( ) 11-3276816 sys SFINESBRT FBaudRate +×= For example: Fsys = 8MHz, to get 115200Hz baud rate, computing method of SBRT1 and SFINE1 as shown below: 8000000/16/115200 = 4.34 SBRT1 = 32768 – 4 = 32764 115200 = 8000000/(16×4 + SFINE1) SFINE1 = 5.4 ≈ 5 This fine tuning method to calculate the actual baud rate is 115942Hz and the error is 0.64%, but the error is 8.5% In the past computing method. In Mode2, the baud rate is programmable to either 1/32 or 1/64 of the system clock. This baud rate is determined by the SMOD1 bit (PCON1.7). When this bit is set to 0, the serial port runs at 1/64 of the clock. When set to 1, the serial port runs at 1/32 of the clock. )64(2 1 SYSSMOD fBaudRate ×=

Multi-Processor Communication Software Address Recognition Modes 2 and 3 of the EUART 1 have a special provision for multi -processor communication. In these modes, 9 data bits are received. The 9th bit goes into RB81. Then a stop bit follows. The EUART1 can be programmed such that when the stop bit is received, the EUART1 interrupt will be activated (i.e. the request flag RI 1 is set) only if RB8 1 = 1. This feature is enabled by setting the bit SM2 in SCON1. A way to use this feature in multiprocessor communications is as follows. lf the master processor wants to transmit a block of data to one of the several slaves, it first sends out an address byte which identifies the target slave. An address byte differs from a data byte in that the 9th bit is 1 in an address byte and 0 in a data byte. With SM12 = 1, no other slave will be interrupted by a data byte. An address byte, however, will interrupt all slaves, so that each slave can examine the received byte and see if it is being addressed. The addressed slave will clear its SM12 bit and prepare to receive the data bytes that will be coming. After having received a complete message, the slave sets SM12 again. The slaves that were not addressed leave their SM12 set and go on with their business, ignoring the incoming data bytes. Note: In Mode0, SM12 is used to select baud rate doubling. In Mode1, SM12 can be used to check the validity of the stop bit. If SM12 = 1 in Mode1, the receive interrupt will not be activated unless a valid stop bit is received. Automatic (Hardware) Address Recognition In Mode2 & 3, setting the SM12 bit will configure EUART1 act as following: when a stop bit is received, EUART1 will generate an interrupt only if the 9 th bit that goes into RB81 is logic 1 (address byte) and the received data byte matches the EUART 1 slave address. Following the received address interrupt, the slave should clear its SM12 bit to enable interrupts on the reception of the following data byte(s). The 9-bit mode requires that the 9 th information bit is a 1 to indicate that the received information is an address and not data. When the master processor wants to transmit a block of data to one of the slaves, it first sends out the address of the targeted slave (or slaves). All the slave processors should have their SM12 bit set high when waiting for an address byte, which ensures that they will be interrupted only by the reception of an address byte. The Automatic address recognition feature further ensures that only the addressed slave will be interrupted. The address comparison is done by hardware not software. After being interrupte d, the addressed slave clears the SM 12 bit to receive data bytes. The un-addressed slaves will be unaffected, as they will be still waiting for their address. Once the entire message is received, the addressed slave should set its SM12 bit to ignore all transmissions until it receives the next address byte. The Automatic Address Recognition feature allows a master to selectively communicate with one or more slaves by invoking the Given Address. All of the slaves may be contacted by using the Broadcast address. Two special Function Registers are used to define the slave’s address, SADDR, and the address mask, SADEN1. The slave address is an 8-bit value specified in the SADDR1 register. The SADEN1 register is actually a mask for the byte value in SADDR1. If a bit position in SADEN1 is 0, then the corresponding bit position in SADDR 1is don’t care. Only those bit positions in SADDR1 whose corresponding bits in SADEN1 are 1 are used to obtain the Given Address. This gives the user flexibility to address multiple slaves without changing the slave address in SADDR1. Use of the Given Address allows multiple slaves to be recognized while excluding others. Slave 1 Slave 2 SADDR1 10100100 10100111 SADEN1 (0 mask) 11111010 11111001 Given Address 10100x0x 10100xx1 Broadcast Address (OR) 1111111x 11111111 The Given address for slave 1 and 2 differ in the LSB. For slave 1, it is a don’t care, while for slave 2 it is 1. Thus to communicate only with slave 1, the master must send an address with LSB = 0 (10100000). Similarly the bit 1 is 0 for slave 1 and don’t care for slave 2. Hence to communicate only with slave 2 the master has to transmit an address with bit 1 = 1 (1010 0011). If the master wishes to communicate with both slaves simultaneously, then the address must have bit 0 = 1 and bit 1 = 0. The bit 2 position is don’t care for both the slaves. This allows two different addresses to select both slaves (1010 0001 and 1010 0101). The master can communicate with all the slaves simultaneously with the Broadcast Address. This address is formed from the logical OR of the SADDR 1 and SADEN1. The zeros in the result are defined as don’t cares. In most cases, the Broadcast Address is FFh, this address will be acknowledged by all slaves. On reset, the SADDR1 and SADEN1 are initialized to 00h. This results in Given Address and Broadcast Address being set as XXXXXXXX (all bits don’t care). This effectively removes the multiprocessor communications feature, since any selectivity is disabled. This ensures that the EUART 1 will re ply to any address, which it is backwards compatible with the 80C51 microcontrollers that do not support automatic address recognition. So the user may implement multiprocessor by software address recognition mentioned above.

Error detection is available when the SSTAT1 bit in register PCON1is set to logic 1.The SSTAT1 bit must be logic 1 to access any of the status bits (FE 1, RXOV1, and TXCOL1). The SSTAT1 bit must be logic 0 to access the Mode Select bits (SM 10, SM11, and SM 12).All the 3 bits should be cleared by software after they are set, even when the following frames received without any error will not be cleared automatically. Transmit Collision The Transmit Collision bit (TXCOL1 bit in register SCON1) reads ‘1’ if RI is set 0 and user software writes data to the SBUF1 register while a transmission is still in progress. If this occurs, the new data will be ignored and the transmit buffer will not be written. Receive Overrun The Receive Overrun bit (RXOV 1 in register SCON 1) reads ‘1’ if a new data byte is latched into the receive buffer before software has read the previous byte. The previous data is lost when this happen. Frame Error The Frame Error bit (FE in register SCON1) reads ‘1’ if an invalid (low) STOP bit is detected. Note: Before transmitting, TXD1 pin must be setted output high. Registers Table 9.31 EUART1 Data cache Registers 87H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PCON1 SMOD1 SSTAT1 - - - - - - R/W R/W R/W - - - - - - Reset Value (POR/WDT/LVR/PIN) 0 0 - - - - - - Bit Number Bit Mnemonic Description

7 SMOD1

0：in Mode2, the baud-rate of EUART is 1/64 of the system clock 1：in Mode2, the baud-rate of EUART is 1/32 of the system clock

6 SSTAT1

SCON1[7:5] function select bit 0：SCON[7:5] operates as SM10, SM11, SM12 1：SCON[7:5] operates as FE1, RXOV1, TXCOL1 Table 9.32 EUART1 Control & Status Register D8H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SCON1 SM10 /FE1 SM11 /RXOV1 SM12 /TXCOL1 REN1 TB81 RB81 TI1 RI1 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) 0 0 0 0 0 0 0 0 Bit Number Bit Mnemonic Description 7-6 SM1[0:1] EUART1 Serial mode control bits, when SSTAT = 0 00: mode 0, Synchronous Mode, fixed baud rate 01: mode 1, 8-bit Asynchronous Mode, variable baud rate 10: mode 2, 9-bit Asynchronous Mode, fixed baud rate 11: mode 3, 9-bit Asynchronous Mode, variable baud rate

7 FE1

EUART1 Frame Error flag, when FE1 bit is read, SSTAT1 bit must be set 1 0: No Frame Error, clear by software 1: Frame error occurs, set by hardware (to be continued)

(continue)

6 RXOV1

EUART1 Receive Over flag, when RXOV1 bit is read, SSTAT1 bit must be set 1 0: No Receive Over, clear by software 1: Receive over occurs, set by hardware

5 SM12

EUART1 Multi-processor communication enable bit (9th bit ‘1’ checker), when SSTAT1 = 0 0: In Mode0, baud-rate is 1/12 of system clock In Mode1, disable stop bit validation check, any stop bit will set RI1 to generate interrupt In Mode2 & 3, any byte will set RI1 to generate interrupt 1: In Mode0, baud-rate is 1/4 of system clock In Mode1, Enable stop bit validation check, only valid stop bit (1) will set RI 1 to generate interrupt In Mode2 & 3, only address byte (9th bit = 1) will set RI1 to generate interrupt

5 TXCOL1

EUART1 Transmit Collision flag, when TXCOL 1 bit is read, SSTAT1 bit must be set 1 0: No Transmit Collision, clear by software 1: Transmit Collision occurs, set by hardware

4 REN1

EUART1 Receiver enable bit 0: Receive Disable 1: Receive Enable

3 TB81 The 9th bit to be transmitted in Mode2 & 3 of EUART1, set or clear by software

2 RB81

The 9th bit to be received in Mode1, 2 & 3 of EUART0 In Mode0, RB81 is not used In Mode1, if receive interrupt occurs, RB81 is the stop bit that was received In Mode2 & 3 it is the 9th bit that was received

1 TI1

Transmit interrupt flag of EUART1 0: cleared by software 1: Set by hardware at the end of the 8th bit time in Mode0, or at the beginning of the stop bit in other modes

0 RI1

Receive interrupt flag of EUART1 0: cleared by software 1: Set by hardware at the end of the 8th bit time in Mode0, or during the stop bit time in other modes Table 9.33 EUART1Data Buffer Registe D9H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) 0 0 0 0 0 0 0 0 Bit Number Bit Mnemonic Description 7-0 SBUF1[7:0] This SFR accesses two registers; a transmit shift register and a receive latch register A write of SBUF1 will send the byte to the transmit shift register and then initiate a transmission A read of SBUF1 returns the contents of the receive latch

Table 9.34 EUART1 Slave Address & Address Mask Register DAH-DBH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) 0 0 0 0 0 0 0 0 Bit Number Bit Mnemonic Description 7-0 SADDR1[7:0] SFR SADDR defines the EUART1’s slave address 7-0 SADEN1[7:0] SFR SADEN1 is a bit mask to determine which bits of SADDR1 are checked 0: Corresponding bit in SADDR1 is a “don’t care” 1: Corresponding bit in SADDR1 is checked against a received address Table 9.35 EUART1 Baudrate Generator Register DCH-DDH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) 0 0 0 0 0 0 0 0 Bit Number Bit Mnemonic Description

7 SBRTEN1

EUART1Baudrate enable control bit 0: disable (deault) 1: enable 6-0, 7-0 SBRT1[14:0] EUART1 Baudrate bits Table 9.36 EUART1 Baudrate Generator fine-tune Register DEH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFINE1 - - - - SFINE1.3 SFINE1.2 SFINE1.1 SFINE1.0 R/W - - - - R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) - - - - 0 0 0 0 Bit Number Bit Mnemonic Description 3-0 SFINE1[3:0] EUART1 Baudrate generator fine-tune register

9.6 Universal Serial Bus (USB)

9.6.1 Features

 Compatible with USB2.0 Full speed (12Mbps)  Support control, interrupt and buck data transfer  Support three endpoints (EP0, EP1, EP2)  On-chip USB transceiver with an internal regulator  Support software reconnect and automatic detect USB host connection SH88F6162 provided an internal USB Serial Interface Engine(SIE) which supports any high speed communication between USB Host and MCU. The internal 3.3v regulator can provide power supply for the internal transceiver in 5V application. Data Transfer Control USB Registers USB Interrupts USB Status Endpoint0 IN OUT Endpoint1 IN OUT Endpoint2 IN OUT

8051 CPU Core

Transceiver Serial Interface Engine(SIE) VDDR 1.5K 150K SW1 SW2 AGND MCU The Universal Serial Bus (USB) support three endpoints: EP0, EP1, EP2. The EP0 is the USB control endpoint, which is used for USB control data transfer. The EP1 and EP2 can support IN/OUT transaction of the bulk/interrupt data transfer. The following table shows the maximum package size of each endpoint. Type Maximum Package Size Type EP0 control IN0: 8 bytes OUT0: 8 bytes EP1 Bulk/interrupt IN1: 16 bytes OUT1: 16 bytes EP2 Bulk/interrupt IN2: 64 bytes OUT2: 64 bytes 00H CPU External RAM LCD RAM Reserved USB RAM EP0 OUT Buf0B28H 0B30H EP0 IN Buf EP1 OUT Buf EP2 OUT Buf 0B38H 0B48H 0B58H 0B68H EP1 IN Buf reserve EP2 IN Buf reserve 0BA8H 0BE8H 0C27H

9.6.2 USB Flow

OUT DATA0(nbytes) ACK Endpoint read byte 0 Endpoint read byte 1 Endpoint read byte 2 Endpoint read byte n OEPnIF=1;OEPnRDY=0 OEPnIF=0;OEPnRDY=1 OUT DATA1 OUT DATA1 NAK NAK OUT DATA1 ACK Endpoint read byte 0OEPnIF=1;OEPnRDY=0 Host USB SIE 8051 CPU USB Bulk/Interrupt Transfer (OUT transaction) Flow IN NAK Endpoint write byte 0 Endpoint write byte 1 Endpoint write byte 2 Endpoint write byte n IEPnIF=0;OEPnRDY=1 IN IN NAK NAK IN IEPnIF=1;IEPnRDY=0 Host USB SIE 8051 CPU ACK DATA0(nbytes) Endpoint write byte 0 USB Bulk/Interrupt Transfer (IN transaction) Flow

9.6.3 Suspend/Resume Control

When the USB controller detected suspend signal, the SUSPIF will be setted by hardware, the USB interrupt will be generated, if the USB interrupt has been enable. The device must be setted to suspend s tate by software in 7ms (Set GOSUSP bit in USBCON register). To reduce power consumption maximumly, the software may close high frequency clock by following the steps below. When code option OP_OSC = 1010 or 1101: (1) Set GOSUSP bit in USBCON register (2) Clear FS bit in CLKCON register (32.768kHz oscillator is selected as OSCSCLK) (3) Clear PLLFS bit in PLLCON register (4) Clear PLLON bit in PLLCON register (Close PLL) (5) Clear OSC2ON bit in CLKCON register (Close OSC2) (6) Set EUSB bit in IEN1 register. Set EA bit in IEN0 register. Set PUPIE, RESMIE, PBRSTIE bits in USBIE1 register (7) Make CPU entering Idle mode to reduce power consumption When code option OP_OSC = 0000: (1) Set GOSUSP bit in USBCON register (2) Clear FS bit in CLKCON register (Internal 128kHz RC oscillator is selected as OSCSCLK) (3) Clear PLLFS bit in PLLCON register (4) Clear PLLON bit in PLLCON register (Close PLL) (5) Clear OSC2ON bit in CLKCON register (Close OSC2) (6) Set EUSB bit in IEN1 register. Set EA bit in IEN0 register. Set PUPIE, RESMIE, PBRSTIE bits in USBIE1 register (7) Make CPU entering Power-down mode to reduce power consumption When the USB controller detected the following three USB states below in suspend state, the interrupt will be generated, if the related interrupt has been enable. (1) Detected Resume Command (2) Detected BUS RESET Command (3) Detected Plug/Unplug If CPU is in Power -down/Idle mode, theCPU will be waked, and entering the related interrupt. The software may open high frequency clock refer to 7.4 System Clock and Oscillator section in sequence. And then clear GOSUSP. Design SPEC: (1) If the USB controller has not goes into suspend mode (GOSUSP), any USB command (including insertion/extraction interrupt) judgment all use 48MHz (2) If the USB controller goes into suspend mode, D+/D- level which has happened any changes, will wake up CPU (if CPU in ilde or power -down condition), after wake up, us ing the system clock to judge which state (Resume/bus reset/insertion/extraction interrupt) wake up CPU, and to set the corresponding flag. (3) If awakening is caused by interference, then can only enter the USB interrupt with no flags set.At this time, the user can check whether or not the system is awaked by interference through judging DPSTA and DMSTA state. (4) When the CPU go to PowerDown mode, if USB wakes up, LDO remains open.

9.6.4 Register

There are three reset sources for USB registers control (1) POR/WDT/LVR/PIN etc traditional reset sources. (2) Bus Reset. It is the USB bus reset. Some registers will be reset by bus reset. (3) USB Software Reset. It is generated by setting SWRST bit in USBCON register. Some USB module registers will be reset, and the USB status machine resume to initial states. Table 9.37 USB Control Register B1H (Bank1) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 USBCON ENUSB SW1CON SWRST DPSTA DMSTA SW2CON WKUP GOSUSP R/W R/W R/W R/W R R R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) 0 0 0 0 0 0 0 0 Bus Reset Value (BUS RESET) U U U U U U U U USB Software Reset U U U U U U 0 0 Bit Number Bit Mnemonic Description

7 ENUSB

0: Disable USB module 1: Enable USB module

6 SW1CON

0: Open 1.5K Pull-high resistor on the D+ line 1: Connect 1.5K Pull-high resistor on the D+ line User's program may simulate the USB plug/unplug process by SW1 on-off bit. If disable the USB module, this bit will be auto-cleared.

5 SWRST

0: Exit USB Software Reset 1: Writing ‘1’ will generate USB Software Reset. Some USB module registers will be reset, and the USB status machine resume to initial states

4 DPSTA

0: D+ Low 1: D+ High

3 DMSTA

0: D- Low 1: D- High

2 SW2CON

0: disconnect 150K pull-up resistor on D- line 1: connect 150K pull-up resistor on D- line Connect the 150K pull-up resistor can detect the pull-out interrupt

1 WKUP

Remote wake-up control bit 0: after send the final signal recovery, cleared by hardware, software to write zero is invalid. 1: send recovery signal from DEVICE to USB BUS, the time keep for 5ms.

0 GOSUSP

USB Suspend State Selection bit 0: Exit Suspend State 1: Enter Suspend State When user‘s program need to set the device into suspend state, this bit should be setted. When the USB port received R esume Command or Bus Reset Command, this bit should be cleared to exit suspend state

Table 9.38 USB Interrupt Vector Register1 B0H (Bank1) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 USBIF1 PUPIF OVERIF OW SETUPIF SOFIF RESMIF SUSPIF USBRSTIF R/W R/W R/W R/W R R R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) 0 0 0 0 0 0 0 0 Bus Reset Value (BUS RESET) U U U U U U U U USB Software Reset U U U U U U 0 0 Bit Number Bit Mnemonic Description

7 PUPIF

Plug/Unplug Interrupt Flag bit 0: No Plug/Unplug interrupt generating, cleared by software 1: Set by hardware to indicate the USB device plugged or unplugged in the host

6 OVERIF

Setup Transaction Overwrite Interrupt Flag bit 0: No setup transaction overwrite interrupt flag generating, cleared by software. Befor this bit cleared by software, cleared SETUPIF bit first 1: Set by hardware to indicate setup transaction is received when output buffer of EP0 is not empty and data is written into the output buffer of EP0 and input/output data package is received again 5 OW Setup Transaction Overwrite State Flag bit 0: No setup transaction overwrite generating 1: Set by hardware to indicate setup transaction is received again when output buffer of EP0 is not empty (OEP0RDY = 0, When setup transaction is received, regardlessly error or returned an ACK lastly) and data is written into the output buffer of EP0 USB software reset or cleared by software. OVERIF may clear this bit.

4 SETUPIF

Setup Transaction Interrupt Flag bit 0: No setup transaction received 1: Setup transaction is received, returns an ACK, and asserts setup transaction interrupt When data is read out from the output buffer of EP0, this bit will be cleared

3 SOFIF

Start-Of-Frame(SOF) Transaction Interrupt Flag bit 0: No SOF transaction received, cleared by software 1: SOF transaction received, and asserts SOF transaction interrupt

2 RESMIF

Resume Command Interrupt Flag bit 0: No resume command received, cleared by software 1: Resume command received, and asserts resume command interrupt

1 SUSPIF

Suspend Command Interrupt Flag bit 0: No suspend command received, cleared by software 1: Suspend command received, and asserts suspend command interrupt When suspend command is received, the device must be setted to suspend state by software in 7m s (Set GOSUSP bit in USBCON register), if the device obtain current from USB bus not more than suspend current (Refer to USB SPEC for details).

0 BUSRSTIF

Bus Reset Command Interrupt Flag bit 0: No bus reset command received, cleared by software 1: Bus reset command received, and asserts bus reset command interrupt

Table 9.39 Interrupt Vector Register2 88H (Bank1) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 USBIF2 - OEP2IF OEP1IF OEP0IF - IEP2IF IEP1IF IEP0IF R/W - R/W R/W R/W - R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) - 0 0 0 - 0 0 0 Bus Reset Value (BUS RESET) - U U U - U U U USB Software Reset - 0 0 0 - 0 0 0 Bit Number Bit Mnemonic Description

6 OEP2IF

Endpoint 2 OUT Interrupt Flag bit 0: No Endpoint 2 OUT transaction occurred, cleared by software 1: Set by hardware to indicate Endpoint 2 OUT transaction occurred

5 OEP1IF

Endpoint 1 OUT Interrupt Flag bit 0: No Endpoint 1 OUT transaction occurred, cleared by software 1: Set by hardware to indicate Endpoint 1 OUT transaction occurred

4 OEP0IF

Endpoint 0 OUT Interrupt Flag bit 0: No Endpoint 0 OUT transaction occurred, cleared by software 1: Set by hardware to indicate Endpoint 0 OUT transaction occurred

2 IEP2IF

Endpoint 2 IN Interrupt Flag bit 0: No Endpoint 2 IN transaction occurred, cleared by software 1: Set by hardware to indicate Endpoint 2 IN transaction occurred

1 IEP1IF

Endpoint 1 IN Interrupt Flag bit 0: No Endpoint 1 IN transaction occurred, cleared by software 1: Set by hardware to indicate Endpoint 1 IN transaction occurred

0 IEP0IF

Endpoint 0 IN Interrupt Flag bit 0: No Endpoint 0 IN transaction occurred, cleared by software 1: Set by hardware to indicate Endpoint 0 IN transaction occurred

Table 9.40 USB Interrupt Enable Register1 B2H (Bank1) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 USBIE1 PUPIE OVERIE - SETUPIE SOFIE RESMIE SUSPIE PBRSTIE R/W R/W R/W - R/W R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) 0 0 - 0 0 0 0 0 Bus Reset Value (BUS RESET) U U - U U U U U USB Software Reset U 0 - 0 U 0 0 0 Bit Number Bit Mnemonic Description

7 PUPIE

Plug/Unplug Interrupt Enable bit 0: Disable Plug/Unplug interrupt 1: Enable Plug/Unplug interrupt

6 OVERIE

Setup Transaction Overwrite Interrupt Enable bit 0: Disable setup transaction overwrite interrupt 1: Enable setup transaction overwrite interrupt

4 SETUPIE

Setup Transaction Interrupt Enable bit 0: Disable setup transaction interrupt 1: Enable setup transaction interrupt

3 SOFIE

SOF Transaction Interrupt Enable bit 0: Disable SOF transaction interrupt 1: Enable SOF transaction interrupt

2 RESMIE

Resume Command Interrupt Enable bit 0: Disable resume command interrupt 1: Enable resume command interrupt

1 SUSPIE

Suspend Command Interrupt Enable bit 0: Disable suspend command interrupt 1: Enable suspend command interrupt

0 PBRSTIE

Bus Reset Command Interrupt Enable bit 0: Disable bus reset command interrupt 1: Enable bus reset command interrupt

Table 9.41 USB Interrupt Enable Register2 B3H (Bank1) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 USBIE2 - OEP2IE OEP1IE OEP0IE - IEP2IE IEP1IE IEP0IE R/W - R/W R/W R/W - R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) - 0 0 0 - 0 0 0 Bus Reset Value (BUS RESET) - U U U - U U U USB Software Reset - 0 0 0 - 0 0 0 Bit Number Bit Mnemonic Description

6 OEP2IE

Endpoint 2 OUT Interrupt Enable bit 0: Disable Endpoint 2 OUT transaction interrupt 1: Enable Endpoint 2 OUT transaction interrupt

5 OEP1IE

Endpoint 1 OUT Interrupt Enable bit 0: Disable Endpoint 1 OUT transaction interrupt 1: Enable Endpoint 1 OUT transaction interrupt

4 OEP0IE

Endpoint 0 OUT Interrupt Enable bit 0: Disable Endpoint 0 OUT transaction interrupt 1: Enable Endpoint 0 OUT transaction interrupt

2 IEP2IE

Endpoint 2 IN Interrupt Enable bit 0: Disable Endpoint 2 IN transaction interrupt 1: Enable Endpoint 2 IN transaction interrupt

1 IEP1IE

Endpoint 1 IN Interrupt Enable bit 0: Disable Endpoint 1 IN transaction interrupt 1: Enable Endpoint 1 IN transaction interrupt

0 IEP0IE

Endpoint 0 IN Interrupt Enable bit 0: Disable Endpoint 0 IN transaction interrupt 1: Enable Endpoint 0 IN transaction interrupt Table 9.42 USB Device Address Register BEH (Bank1) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 USBADDR - USBADDR6 USBADDR5 USBADDR4 USBADDR3 USBADDR2 USBADDR1 USBADDR0 R/W - R/W R/W R/W R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) - 0 0 0 0 0 0 0 Bus Reset Value (BUS RESET) - 0 0 0 0 0 0 0 USB Software Reset - 0 0 0 0 0 0 0 Bit Number Bit Mnemonic Description 6-0 USBADDR USB communication device address

Table 9.43 Endpoint 0 Control Register BFH (Bank1) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 EP0CON IEP0DTG OEP0DTG - - IEP0STL IEP0RDY OEP0STL OEP0RDY R/W R/W R/W - - R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) 0 0 - - 0 0 0 0 Bus Reset Value (BUS RESET) 0 0 - - 0 U 0 U USB Software Reset 0 0 - - 0 0 0 0 Bit Number Bit Mnemonic Description

7 IEP0DTG

Endpoint 0 IN Data Toggle bit 0: Reading out ‘0’ indicates that the next data toggle bit is Data0, writing in ‘0’ indicates that the next data toggle bit will be setted as Data0 1: Reading out ‘1’ indicates that the next data toggle bit is Data1, writing in ‘1’ indicates that the next data toggle bit will be setted as Data1

6 OEP0DTG

Endpoint 0 OUT Data Toggle bit 0: Reading out ‘0’ indicates that the next data toggle bit is Data0 , writing in ‘0’ indicates that the next data toggle bit will be setted as Data0 1: Reading out ‘1’ indicates that the next data toggle bit is Data1, writing in ‘1’ indicates that the next data toggle bit will be setted as Data1

3 IEP0STL

Endpoint 0 IN STALL Enable bit 0: Disable Endpoint 0 IN STALL 1: Enable Endpoint 0 IN STALL, When the host sends IN transaction to Endpoint 0, returns a STALL When setup transaction is received, IEP0STL is auto-cleared

2 IEP0RDY

0: Endpoint 0 IN is not ready, When the host sends IN transaction to Endpoint 0, returns a NAK 1: Endpoint 0 IN is ready When the host sends IN transaction to Endpoint 0, if this bit is ‘1’, the USB transceiver sends data in Endpoint 0 buffer, and after receiving an ACK from the host, this bit is cleared, generate Endpoint 0 IN interrupt. Writing the data (need to be sent to the host) into Endpoint 0 buffer again by software, and setting this bit indicates the next IN transaction can be received. Software write 0 has no effect.

1 OEP0STL

Endpoint 0 OUT STALL Enable bit 0: Disable Endpoint 0 OUT STALL 1: Enable Endpoint 0 OUT STALL, when the host sends OUT transaction to Endpoint 0, returns a STALL When setup transaction is received, OEP0STL is auto-cleared

0 OEP0RDY

0: Endpoint 0 OUT is not ready, When the host sends OUT transaction to Endpoint 0, returns a NAK 1: Endpoint 0 OUT is ready When the host sends OUT transaction to Endpoint 0, if this bit is ‘1’, the USB transceiver writes data into Endpoint 0 buffer, and after returning an ACK to the host, this bit is cleared, generate Endpoint 0 OUT interrupt. After reading out the data in Endpoint 0 buffer by software, setting this bit indicates the next OUT transacti on can be received. Software write 0 has no effect.

Table 9.44 Endpoint 1 Control Register AAH (Bank1) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 EP1CON IEP1DTG OEP1DTG - - IEP1STL IEP1RDY OEP1STL OEP1RDY R/W R/W R/W - - R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) 0 0 0 0 0 0 0 0 Bus Reset Value (BUS RESET) 0 0 0 0 0 U 0 U USB Software Reset 0 0 0 0 0 0 0 0 Bit Number Bit Mnemonic Description

7 IEP1DTG

Endpoint 1 IN Data Toggle bit 0: Reading out ‘0’ indicates that the next data toggle bit is Data0, writing in ‘0’ indicates that the next data toggle bit will be setted as Data0 1: Reading out ‘1’ indicates that the next data toggle bit is Data1, writing in ‘1’ indicates that the next data toggle bit will be setted as Data1

6 OEP1DTG

Endpoint 1 OUT Data Toggle bit 0: Reading out ‘0’ indicates that the next data toggle bit is Data0, writing in ‘0’ indicates that the next data toggle bit will be setted as Data0 1: Reading out ‘1’ indicates that the next data toggle bit is Data1, writing in ‘1’ indicates that the next data toggle bit will be setted as Data1 5 - This bit must be set 0 4 - This bit must be set 0

3 IEP1STL

Endpoint 1 IN STALL Enable bit 0: Disable Endpoint 1 IN STALL 1: Enable Endpoint 1 IN STALL, When the host sends IN transaction to Endpoint 1, returns a STALL

2 IEP1RDY

0: Endpoint 1 IN is not ready, When the host sends IN transaction to Endpoint 1, returns a NAK 1: Endpoint 1 IN is ready When the host sends IN transaction to Endpoint 1, if this bit i s ‘1’, the USB transceiver sends data in Endpoint 1 buffer, and after receiving an ACK from the host, this bit is cleared, generate Endpoint 1 IN interrupt. Writing the data(need to be sent to the host) into Endpoint 1 buffer again by software, and setting this bit indicates the next IN transaction can be received. Software write 0 has no effect.

1 OEP1STL

Endpoint 1 OUT STALL Enable bit 0: Disable Endpoint 1 OUT STALL 1: Enable Endpoint 1 OUT STALL, When the host sends OUT transaction to Endpoint 1, returns a STALL

0 OEP1RDY

0: Endpoint 1 OUT is not ready, When the host sends OUT transaction to Endpoint 1, returns a NAK 1: Endpoint 1 OUT is ready When the host sends OUT transaction to Endpoint 1, if this bit is ‘1’, the US B transceiver writes data into Endpoint 1 buffer, and after returning an ACK to the host, this bit is cleared, generate Endpoint 1 OUT interrupt. After reading out the data in Endpoint 1 buffer by software, setting this bit indicates the next OUT transact ion can be received. Software write 0 has no effect.

Table 9.45 Endpoint 2 Control Register ABH (Bank1) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 EP2CON IEP2DTG OEP2DTG - - IEP2STL IEP2RDY OEP2STL OEP2RDY R/W R/W R/W - - R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) 0 0 0 0 0 0 0 0 Bus Reset Value (BUS RESET) 0 0 0 0 0 U 0 U USB Software Reset 0 0 0 0 0 0 0 0 Bit Number Bit Mnemonic Description

7 IEP2DTG

Endpoint 2 IN Data Toggle bit 0: Reading out ‘0’ indicates that the next data toggle bit is Data0, writing in ‘0’ indicates that the next data toggle bit will be setted as Data0 1: Reading out ‘1’ indicates that the next data toggle bit is Data1, writing in ‘1’ indicates that the next data toggle bit will be setted as Data1

6 OEP2DTG

Endpoint 2 OUT Data Toggle bit 0: Reading out ‘0’ indicates that the next data toggle bit is Data1, writing in ‘0’ indicates that the next data toggle bit will be setted as Data1 1: Reading out ‘1’ indicates that the next data toggle bit is Data0, writing in ‘1’ indicates that the next data toggle bit will be setted as Data0 5 - This bit must be set 0 4 - This bit must be set 0

3 IEP2STL

Endpoint 2 IN STALL Enable bit 0: Disable Endpoint 2 IN STALL 1: Enable Endpoint 2 IN STALL, When the host sends IN transaction to Endpoint 2, returns a STALL

2 IEP2RDY

0: Endpoint 2 IN is not ready, When the host sends IN transaction to Endpoint 2, returns a NAK 1: Endpoint 2 IN is ready When the host sends IN transaction to Endpoint 2, if this bit is ‘1’, the USB transceiver sends data in Endpoint 2 buffer, and after receiving an ACK from the host, this bit is cleared, generate Endpoint 2 IN interrupt. Writing the data(need to be sent to the host) into Endpoint 2 buffer again by software, and setting this bit indicates the next IN transaction can be received. Software write 0 has no effect.

1 OEP2STL

Endpoint 2 OUT STALL Enable bit 0: Disable Endpoint 2 OUT STALL 1: Enable Endpoint 2 OUT STALL, When the host sends OUT transaction to Endpoint 2, returns a STALL

0 OEP2RDY

0: Endpoint 2 OUT is not ready, When the host sends OUT transaction to Endpoint 2, returns a NAK 1: Endpoint 2 OUT is ready When the host sends OUT transaction to Endpoint 2, if this bit is ‘1’, the USB transceiver writes data into Endpoint 2 buffer, and after returning an ACK to the host, this bit is cleared, generate Endpoint 2 OUT interrupt. After reading out the data in Endpoint 2 buffer by software, setting this bit indicates the next OUT transaction can be received. Software write 0 has no effect.

Table 9.46 Endpoint 0 IN Data Buffer Length Register ACH (Bank1) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 IEP0CNT - - - - IEP0CNT3 IEP0CNT2 IEP0CNT1 IEP0CNT0 R/W - - - - R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) - - - - 0 0 0 0 Bus Reset Value (BUS RESET) - - - - U U U U USB Software Reset - - - - 0 0 0 0 Bit Number Bit Mnemonic Description 3-0 IEP0CNT The length of Endpoint 0 IN data buffer Note: if the value written in the register is larger than 0x8, the register value will be 0x8 Table 9.47 Endpoint 1 IN Data Buffer Length Register ADH (Bank1) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 IEP1CNT - - - IEP1CNT4 IEP1CNT3 IEP1CNT2 IEP1CNT1 IEP1CNT0 R/W - - - R/W R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) - - - 0 0 0 0 0 Bus Reset Value (BUS RESET) - - - U U U U U USB Software Reset - - - 0 0 0 0 0 Bit Number Bit Mnemonic Description 4-0 IEP1CNT The length of Endpoint 1 IN data buffer Note: if the value written in the register is larger than 0x10, the register value will be 0x10 Table 9.48 Endpoint 2 IN Data Buffer Length Register AEH (Bank1) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 IEP2CNT - IEP2CNT6 IEP2CNT5 IEP2CNT4 IEP2CNT3 IEP2CNT2 IEP2CNT1 IEP2CNT0 R/W - R/W R/W R/W R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) - 0 0 0 0 0 0 0 Bus Reset Value (BUS RESET) - U U U U U U U USB Software Reset - 0 0 0 0 0 0 0 Bit Number Bit Mnemonic Description 6-0 IEP2CNT The length of Endpoint 2 IN data buffer Note: if the value written in the register is larger than 0x40, the register value will be 0x40

Table 9.49 Endpoint 0 OUT Data Buffer Length Register AFH (Bank1) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 OEP0CNT - - - - OEP0CNT3 OEP0CNT2 OEP0CNT1 OEP0CNT0 R/W - - - - R R R R Reset Value (POR/WDT/LVR/PIN) - - - - 0 0 0 0 Bus Reset Value (BUS RESET) - - - - U U U U USB Software Reset - - - - 0 0 0 0 Bit Number Bit Mnemonic Description 3-0 OEP0CNT The length of Endpoint 0 OUT data buffer Table 9.50 Endpoint 1 OUT Data Buffer Length Register B6H (Bank1) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 OEP1CNT - - - OEP1CNT4 OEP1CNT3 OEP1CNT2 OEP1CNT1 OEP1CNT0 R/W - - - R R R R R Reset Value (POR/WDT/LVR/PIN) - - - 0 0 0 0 0 Bus Reset Value (BUS RESET) - - - U U U U U USB Software Reset - - - 0 0 0 0 0 Bit Number Bit Mnemonic Description 4-0 OEP1CNT The length of Endpoint 1 OUT data buffer Table 9.51 Endpoint 2 OUT Data Buffer Length Register B7H (Bank1) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 OEP2CNT - OEP2CNT6 OEP2CNT5 OEP2CNT4 OEP2CNT3 OEP2CNT2 OEP2CNT1 OEP2CNT0 R/W - R R R R R R R Reset Value (POR/WDT/LVR/PIN) - 0 0 0 0 0 0 0 Bus Reset Value (BUS RESET) - U U U U U U U USB Software Reset - 0 0 0 0 0 0 0 Bit Number Bit Mnemonic Description 6-0 OEP2CNT The length of Endpoint 2 OUT data buffer

9.7 Analog Digital Converter (ADC)

9.7.1 Features

 12-bit Resolution  Up to 1MSPS  4 reference voltage Selectable: external VREF, built-in 1.5V/2.5V reference voltage or VDD  12 external Multiplexed Input Channels, 3 internal Multiplexed Channels  6 Selectable Trigger Source  Sequence Conversion or Free Running Mode with digital comparator The SH88F6161/SH88F6162 includes a single ended, 12-bit SAR Analog to Digital Converter (ADC Analog-to-Digit Converter) module as shown in figure. The AD C converts an analog input voltage to a 12- bit digital value through successive approximation. The minimum value represent GND and the maximum value represents the voltage on the Vref(selected reference voltage) minus 1LSB. Optionally, VDD(default), external reference or an internal 1.5V/2.5V reference voltage may be selected as the reference voltage. The external reference and internal 1.5V/2.5V reference may thus be decoupled by an external capacitor at the VREF pin to improve noise immunity. The 12 external channels and 3 internal channels can be selected dependently but only one at a time. A single conversion is started by setting the GO/DOWN bit, this bit stays high as long as the conversion is in progress and will be cleared by hardware when the conversion is completed. The result is presented in the ADC Date Registers, ADCH and ADCL. The interrupt flag ADCIF is set by hardware and an interrupt event can occur when complete interrupt is enabled( setting EADC and EADCI). The Data Registers are read only.By default, the result is left adjusted, but can optionally be presented right adjusted by setting the ALR bit. Once the ADCH is read, ADC access to the ADCH and ADCL Registers isn ’t re-enabled until ADCL is read to ensure that the content of the Data Registers belongs to the same conversion. If the conversion completes during the Data Register is blocked, the interrupt flag ADCIF is still set,but the convertion data will be lost. The digital comparator can compare the analog input with the digital va lue continuously. The function of digital comparator is enabled after setting the ADON and EC bit. In this mode the ADC will perform successive conversions independently of whether the ADC Interrupt Flag, ADIF is cleared or not. The GO/DOWN bit remains high during the continuous conversions. Make sure the result is read correctly everytime. If the greater interrupt is enabled(the ACGIE bit is set) and the conversio n result of analog input is greater than the value of ADCGTH/L, the greater interrupt flag ACGIF is set by hardware, and the less interrupt performe alike. Clear GO/DOWN or EC bit can quit this mode. The ADC module can work in IDLE mode and the ADC interrupt can wake up the IDLE mode. It is disabled in Power -Down mode.

9.7.2 Starting and Ending a Conversion

The starting of ADC includes software start and hardware start. Software starting: The ADC is enabled by setting the ADC Enable bit, ADON in ADCON1. Voltage reference and input channel selections will not go into effect until ADON is set. The ADC does not consume power when ADON is cleared, so it is recommended to switch off the ADC before entering Power -Down mode. A single conversion is started by setting the GO/DOWN bit in ADCON1. This bit stays high as long as the conversion is in progress and will be cleared by hardware when the conversion is completed. If a different data channel is selected while a conversion is in progress, the ADC will finish t he current conversion before performing the channel change. Hardware Start: Auto Triggering is enabled by setting the Trigger Enable bit, TRE in ADCON1. The trigger source is selected by setting the Trigger Select bits, TRS in ADCON1. When a trigger source occurs on the selected trigger signal, the ADC prescaler is reset and a conversion is started. If the trigger signal still is set when the conversion completes, a new conversion will not be started. If another positive edge occurs on the trigger signal during conversion, the edge will be ignored. Note that an Interrupt Flag will be set even if the specific interrupt is disabled or the Global Interrupt Enable bit is cleared. the Interrupt Flag must be cleared in order to trigger a new conversion at the next interrupt event. If Auto Triggering is enabled, single conversions can be started by writing GO/DOWN in ADCON1 to one (Software Start). If an auto trigger source occurs while a conversion is in progress, the ADC will end the current conversion and restart a new conversion. The ADC module contains a prescaler, which generates an acceptable ADC clock frequency. The prescaling is set by the TADC bits. The total time of a normal conversion contains sample-and-hold time and conversion time. If a lower resolution than 12 bits is needed, the conversion frequency of the ADC can be higher than 100kHz (up to 1M) to get a higher sample rate (Table10.2-10.3). The analog input channel is selected by writing to the SCH bits. Voltage reference and input channel selections will not go into effect until ADON is set. If a different data channel is selected while a conversion is in progress, the ADC will finish the current conversion before performing the channel change. When switching to internal-build reference, make sure keep 500us for stable output.

If EC or TRE is written to one, an interrupt event can occur at any time. If the SCH bits are changed in this period, the user cannot tell if the next conversion is based on the old or the new settings. SCH can be safely updated in the following ways: (1) When TRE or EC is cleared. (2) When EC is set, and a conversion is in progress. When updating SCH in one of these conditions, the new settings will affect the next ADC conversion. Note: (1) Do not updata SCH or reference voltage in 1MSPS mode. (2) Do not updata ADT while EC = 1. (3) Set ADON first and wait for 10us before every conversion start. Internal reference voltage of 1.5V/2.5V channel is used for calibration.

9.7.3 ADC Diagram

1.5V/ 2.5V SCH[3:0] MUX Vref 1.5v/2.5v VDD Vref[1:0] ADCON compareEC ACGIF/ACLIF ADCGTH/L ADCLTH/L ADCMPCON Prescale fsys Trigger mux INT2 PCA0 PCA1 Timer2 Timer3 capture TRS[2:0] ADCH/L ADCIF OPO DACO ADC Diagram

9.7.4 ADC Register

ADC Registers: Function Name Register Description ADC Clock Register ADT Configuration of ADC clock, sample time ADC control Register ADCON1 Enable of ADC module, compare function, trigger mode and sources, interrupt flag ADCON2 Interrupt enable ADC Data Register ADCL Low byte of Data Register ADCH High byte of Data Register Greater Compare Register ADCGTL Low byte of Greater Compare Register ADCGTH High byte of Greater Compare Register Less Compare Register ADCLTL Low byte of Less Compare Register ADCLTH High byte of Less Compare Register Channel Select Register SCHCON1 Selection of reference voltage, channel, direction of Data Register SCHCON2 channel0 - 7port share SCHCON3 channel8 - 11port share Table 9.52 ADT (ADC Clock Configure Register) 89H (Bank1) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ADT - TADC2 TADC1 TADC0 TS3 TS2 TS1 TS0 R/W - R/W R/W R/W R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) - 0 0 0 0 0 0 0 Bit Number Bit Mnemonic Description 6-4 TADC[2:0] ADC Clock Period Select bits 000: ADC Clock Period tAD = 1 tSYS 001: ADC Clock Period tAD = 2 tSYS 010: ADC Clock Period tAD = 4 tSYS 011: ADC Clock Period tAD = 8 tSYS 100: ADC Clock Period tAD = 16 tSYS 101: ADC Clock Period tAD = 32 tSYS 110: ADC Clock Period tAD = 64 tSYS 111: ADC Clock Period tAD = 128 tSYS 3-0 TS[3:0] Sample time select bits 2 tAD ≤ Sample time = (TS[3:0]+1) X tAD ≤ 15 tAD Note: (1) The minimum sample time is 2 t AD, even TS[3:0] = 0000/0001, The maximum sample time is 5 t AD, even TS[3:0] = 1110/1111. (2) Make sure that the series resistance connected with ADC input pin is no more than 10kΩ when 2 tAD sample time is selected. (3) When in free running mode, the sample time is TS+2, except for the first conversion.

Table 9.53 ADCON1 (ADC Control Register1) 91H (Bank1) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ADCON1 ADON ADCIF EC TRE TRS2 TRS1 TRS0 GO/DONE ———— R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) 0 0 0 0 0 0 0 0 Bit Number Bit Mnemonic Description

7 ADON

0: Disable the ADC module 1: Enable the ADC module

6 ADCIF

0: No ADC interrupt, cleared by software 1: Set by hardware to indicate that the AD Convert has been completed, software clear 5 EC Compare Function Enable bit 0: Compare function disabled 1: Compare function enabled

4 TRE

0: Disable trigger mode 1: Enable triiger mode 3-1 TRS[2:0] Trigger Source Select Bits 00X: none 010: Rising-edge of EX2 011: Match interrupt of module 0 in PCA0 100: Timer2 overflow 101: Match interrupt of module 1 in PCA1 110: Timer3 overflow 111: Catch flag of P1CEX0 in PCA1

0 GO/DONE

———— ADC Status Flag bit 0: Automatically cleared by hardware when AD convert is com pleted. Clearing this bit during converting time will stop current conversion. If Compare function is enabled, this bit will not be cleared by hardware until software clear. 1: Set to start AD convert or digital compare. Do not change this bit during DAC calibration

Table 9.54 ADCON2 (ADC Control Register2) 8DH (Bank1) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ADCON2 ADCIE - - ACLIE ACGIE ACLIF ACGIF - R/W R/W - - R/W R/W R/W R/W - Reset Value (POR/WDT/LVR/PIN) 0 - - 0 0 0 0 - Bit Number Bit Mnemonic Description

7 ADCIE

ADC Conversion Complete Interrupt Enable Bit 0: disable ADC conversion complete interrupt. 1: enable ADC conversion complete interrupt

4 ACLIE

Less Compare Interrupt Enable Bit 0: disable less compare interrupt 1: enable less compare interrupt

3 ACGIE

Greater Compare Interrupt Enable Bit 0: diable greater compare interrupt. 1: enable greater compare interrupt.

2 ACLIF

Less Compare Interrupt Flag 0: no less compare interrupt,Data Register is greater than or equal to ADCLTH/L 1: set by hardware to indicate that Data Register is less than ADCLTH/L this bit should be cleared by software

1 ACGIF

Greater Compare Interrupt Flag 0: no greater compare interrupt ,Data Register is less than or eual to ADCLTH/L 1: set by hardware to indicate that Data Register is greater than ADCLTH/L this bit should be cleared by software

Table 9.55 SCHCON1 (Channel Configure Register) 8AH (Bank1) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SCHCON1 VREF1 VREF0 ALR - SCH3 SCH2 SCH1 SCH0 R/W R/W R/W R/W - R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) 0 0 0 - 0 0 0 0 Bit Number Bit Mnemonic Description 7-6 VREF[1:0] Reference Selection Bits 00: internal reference, VDD 01: external reference, with capacitor at VREF pin 1x: internal 1.5V/2.5V (selected by REFON and REFSEL in DAC), with external capacitor at CREF pin Note: internal 1.5V/2.5V get good performance in 100K mode, keep 500us to set up when change internal reference voltage first time.

5 ALR

0: left adjust 1: right adjust 3-0 SCH[3:0] ADC channel select bit 0000: ADC channel ADC0 0001: ADC channel ADC1 0010: ADC channel ADC2 0011: ADC channel ADC3 0100: ADC channel ADC4 0101: ADC channel ADC5 0110: ADC channel ADC6 0111: ADC channel ADC7 1000: ADC channel ADC8 1001: ADC channel ADC9 1010: ADC channel ADC10 1011: ADC channel ADC11 1100: internal DACO input 1101: internal OPO input 111x: select internal 1.5V/2.5V as reference source Table 9.56 SCHCON2 (Channel Register) 8BH (Bank1) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SCHCON2 ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) 0 0 0 0 0 0 0 0 Bit Number Bit Mnemonic Description 7-0 ADC[7:0] Channel Configuration bits 0: P0.x (x = 0 - 7) are I/O port 1: P0.x (x = 0 - 7) are ADC input port

Table 9.57 SCHCON3 (Channel Register) 8CH (Bank1) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SCHCON3 - - - - ADC11 ADC10 ADC9 ADC8 R/W - - - - R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) - - - - 0 0 0 0 Bit Number Bit Mnemonic Description 3-0 ADC[11:8] ADC channel select 0: P1.3 - P1.0 are I/O port 1: P1.3 - P1.0 are ADC input port Table 9.58 ADCL/H (ADC Result Register) Left Mode 92H (Bank1) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ADCL A3 A2 A1 A0 - - - - R/W R R R R - - - - Reset Value (POR/WDT/LVR/PIN) 0 0 0 0 - - - - 93H (Bank1) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ADCH A11 A10 A9 A8 A7 A6 A5 A4 R/W R R R R R R R R Reset Value (POR/WDT/LVR/PIN) 0 0 0 0 0 0 0 0 Table 9.59 ADCL/H (ADC Result Register) Right Mode 92H (Bank1) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ADCL A7 A6 A5 A4 A3 A2 A1 A0 R/W R R R R R R R R Reset Value (POR/WDT/LVR/PIN) 0 0 0 0 0 0 0 0 93H (Bank1) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ADCH - - - - A11 A10 A9 A8 R/W - - - - R R R R Reset Value (POR/WDT/LVR/PIN） - - - - 0 0 0 0 Bit Number Bit Mnemonic Description 7-0, 7-4/ 3-0, 7-0 A11-A0 Left Mode (ALR = 0) After the convert has completed, the data will be updated and put in the ADCL/H register The highest eight bits are written in the ADCH,and the lowest four bits correspond to the highest four bits of ADCL register Right Mode (ALR = 1) After the convert has completed, the data will be updated and put in the ADCL/H register The highest four bits correspond to the lowest four bits of ADCH regi ster, and the lowest eight bits correspond to ADCL register

Table 9.60 ADCGTL/H (ADC Greater Compare Register) 94H (Bank1) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ADCGTL GT7 GT6 GT5 GT4 GT3 GT2 GT1 GT0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) 0 0 0 0 0 0 0 0 95H (Bank1) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ADCGTH - - - - GT11 GT10 GT9 GT8 R/W - - - - R R R R Reset Value (POR/WDT/LVR/PIN） - - - - 0 0 0 0 Bit Number Bit Mnemonic Description 11-0 GT11 - GT0 The result register’s value will be compared with ADCGTL/H after the conversion completed,if the register ’s value is larger than or equal to the data in ADCGTL/H,ACGIF in ADCON2 will be set and not change until cleared by software. Table 9.61 ADCLTL/H (ADC Less Compare Register) 96H (Bank1) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ADCLTL LT7 LT6 LT5 LT4 LT3 LT2 LT1 LT0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) 0 0 0 0 0 0 0 0 97H (Bank1) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ADCLTH - - - - LT11 LT10 LT9 LT8 R/W - - - - R R R R Reset Value (POR/WDT/LVR/PIN） - - - - 0 0 0 0 Bit Number Bit Mnemonic Description 11-0 LT11 - LT0 The result register’s value will be compared with ADCGTL/H after the conversion completed,if the register ’s value is smaller than the data in ADCGTL/H,ACGIF in ADCON2 will be set and not change until cleared by software.

The Approach for starting ADC Conversion by software: (1) Select reference voltage (2) Select the analog input channels (3) Clear 0ADCIF, ACLIF, ACGIF (4) Enable the ADC module (5) Set GO/DONE ———— = 1 to start the ADC conversion (6) Wait until GO/DONE ———— = 0 or ADCIF = 1, if the ADC interrupt is enabled, the ADC interrupt will occur (7) Acquire the converted data from ADCH/L (8) Repeat step 3-7 if another conversion is required The Approach for starting ADC Conversion by hardware: (1) Select reference voltage (2) Select the analog input channels (3) Clear ADCIF, ACLIF, ACGIF (4) Set TRE to 1; set TRS[2:0] to select trigger source (5) Enable the ADC module (6) If ADCIF=1,and the ADC interrupt is enabled, the interrupt will occur (7) Acquire the converted data from ADCH/L The Approach for starting Digital Compare Function: (1) Select reference voltage. (2) Select the analog input channels (3) Write the compare value. (4) Clear ADCIF, ACLIF, ACGIF (5) Set EC = 1 to enable the compare function. (6) Enable the ADC module (7) If the analog input is lager than or less than compare value, the ADC interrupt will occur (8) The compare function will continue work until the EC or GO/DONE ———— bit is cleared to 0

9.8 12Bit Votage Type DAC

9.8.1 Features

 12-bit monotonic output  Internal or external reference selection  Self-calibration option for offset correction  Straight binary or 2s compliment data format  Internal 128K be selected to count the time used for DAC converting.When DACEN = 1, 128k start to warmup.When DACEN = 0, 128k is closed. Thus the 128K warmup time should be concerned when DAC convert the first data. The time for DAC to convert data can be selected by OP_DACTIME in Customer Option. The Block Diagram of DAC DACLDACH DACLSEL[1:0] DAC LATCH DACIO Other functionTimer2 Timer3 DACL VR- VR+ DACSREF[1:0] VDD VREF 1.5V 2.5V GND DACDF PCA0 DACOSEL[1:0]

9.8.2 DAC Control

Reference voltage is the only parament to influence the DAC output value.And it’s the important part of DAC module. DAC can choose the internal and external reference voltage. DAC has four types reference voltage: V DD, Internal build 1.5V, Internal build 2.5V, external VREF. After the chip has been reseted, VDD is used as reference voltage. When select external V REF as reference voltage. When VREF connected external is used, resistance performance can be improved by connecting the capacitance to the external pin. When use the internal-build reference voltage, 1uf capacitance should be connected to the external CREF pin to guarantee precision. Update Output On-Demand The Output is updated “On-Demand” on a write to the DACL. It is important to note that writes to DACH are held in this mode, and have no effect on the DAC output until a write to DACL takes place. So the write sequence should be IDA0L followed by IDA0H. Update Output Based on Timer Overflow The DAC outputs can use a Timer overflow to schedule an output update event. This feature is useful in systems where the DAC is used to generate a waveform of a defined sampling rate by eliminating the effects of variable interrupt lat ency and instruction execution on the timing of the DAC output. When the bits (DACLSEL [1:0]) are set to ‘01’, ‘10’ or ‘11’, writes to both DAC data registers (DACLand DACH) are held until an associated Timer overflow event occurs, at which time the DACH:DACL contents are copied to the DAC input latches, allowing the DAC output to change to the new value. Note: During the period of DAC converting,if the tri gger signal appears again, DAC will reconvert.In the Power -Down mode, DAC module cannot work.When resume from the Power-Down mode, DAC output value is the same as it was when the system is ready to enter Power-Down mode.

9.8.3 Self-calibration Option for Offset Correction

Before using DAC, it should be corrected because of offset error exiting. offset calibration sequence can be initiated by setting DACCALON control bit. After the process complete, DACCALON will be cleared. The operation is as follow: (1) Enable DAC Self-calibration a. DACEN = 1, DACCALON = 1 (2) Set DAC parameter a. DACDF = x, DACSREF = XX (The reference is defined by the application circuit) (3) Set ADC parameter a. ADON = 1, REFC = XX (The reference is the same as DAC), SCH[3:0] = 1100 (select internal DACO as input) (4) Start DAC convert a. DACH = 08H, DACL = 00H (5) Self-calibration complete, the hardware will work a. DACH, DACL are cleared by hardware b. DACO is pulled low by hardware c. DACCALON is cleared by hardware d. DACCAL is updated by hardware. And the value is held after the Self-calibration complete e Other registers keep the value before Self-calibration (6) After the Self-calibration complete,the software will operate a. If DACCALON = 0, Self-calibration complete b. Decide whether ADC should be disable or not depending on application,and whether channel should switch c. DAC can be used as normal Note: DAC self-calibration, should be done more times and the average value should be selected. self-calibration function DACLDACH DAC LATCH DACEN DACL VR- VR+ GND DACDF DACCALON = 1 Offset Data of OP DACSREF[1:0] VDD VREF 1.5V 2.5V ADC_Channel_DACO (Internal)

9.8.4 Register

Table 9.62 DAC Control Register0 8BH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 DACCON0 DACEN DACOSEL.1 DACOSEL.0 DACLSEL.1 DACLSEL.0 DACDF DACIO DACIF R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) 0 0 0 0 0 0 0 0 Bit Number Bit Mnemonic Description

7 DACEN

0: disable DAC 1: enable DAC 6-5 DACOSEL[1:0] DAC output range select 00: DAC output with no buffer 01: DAC output with buffer (one time) 1x: DAC output with buffer (three times) 4-3 DACLSEL[1:0] DAC load select. 00: DAC latch loads when DACL written 01: DAC latch loads when the overflow of timer2 happening 10: DAC latch loads when the overflow of timer3 happening 11: DAC latch loads when the overflow of PCA0 timer happening

2 DACDF

0: Straight binary 1: 2s complement

1 DACIO

0: P1.6 act as IO port 1: P1.6 act as DAC output

0 DACIF

0: DAC conversion not complete． 1: DAC conversion has completed, and the bit should be cleared by software

Table 9.63 DAC Control Register1 9FH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 DACCON1 DACCALON OFFSETSW - VREFS REFSEL REFON DACSREF.1 DACSREF.0 R/W R/W R/W - R/W R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) 0 0 - 0 0 0 0 0 Bit Number Bit Mnemonic Description

7 DACCALON

DAC calibration on (when DACOSEL[1:0] = 01 or 1x, calibration function is valid) 0: Calibration is not active (it is automatically reset by hardware when the calibration completes) 1: Initiate calibration/calibration in progress

6 OFFSETSW

0: Enable DAC compensation 1: Disable DAC compensation

4 VREFS

External reference voltage input port selection 0: P1.4 as I/O pin 1: P1.4 as VREF input pin

3 REFSEL

Built-in voltage selection 0: built-in 2.5V 1: built-in 1.5V (when switch built-in voltage, 1ms time is needed to keep stable)

2 REFON

Built-in 1.5V/2.5V control 0: close built-in 1.5V/2.5V (P1.5 act as I/O port) 1: open built-in 1.5V/2.5V (P1.5 act as internal reference voltage output pin) (when Open built-in voltage, 500us time is needed to keep stable) 1-0 DACSREF[1:0] DAC select reference voltage 00: select VDD as reference 01: select input value of external VREF port as reference 1x: select built-in 1.5V/2.5V as reference (When select built-in 1.5V/2.5V as reference, REFON should be set advance.) Note: When select external reference voltage or built-in voltage as reference voltage, REFON should be set advance. After the voltage selected is stable, the reference only can be choose. REFON and DACSREF cannot be written at the same time.

Table 9.64 DAC Self-calibration Control Register A4H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 DACCAL OFFSET SIGN - OFFSET DATA.5 OFFSET DATA.4 OFFSET DATA.3 OFFSET DATA.2 OFFSET DATA.1 OFFSET DATA.0 R/W R/W - R/W R/W R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) 0 - 0 0 0 0 0 0 Bit Number Bit Mnemonic Description

7 OFFSETSIGN

The Sign of compensation voltage for DAC Self-calibration 0: Positive (the conversion value is larger than the real value) 1: Negative (the conversion value is smaller than the real value) 5-0 OFFSET DATA[5:0] The compensation voltage data for DAC Self-calibration (After the completion of the Self -calibration, this register will be updated according to the result of calibration. When OFFSETSW = 0 , the real DAC output voltage can be calculated by DACH:DACL and OFFSETDAT register to gain high precision. When OFFSETSW = 1, DAC will output voltage corresponding to DACH:DACL) Table 9.65 DAC Data Register 8DH，8CH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 DACH (8DH) - - - - DAC.11 DAC.10 DAC.9 DAC.8 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) 0 0 0 0 0 0 0 0 Bit Number Bit Mnemonic Description 3-0 7-0 DAC[11:0] DAC Data Bit 3 - 0: the hignest four bits of 12-bit DAC data Bit 7 - 0: the lowest eight bits of 12-bit DAC data

9.9 High-performance Operational Amplifier (OP)

9.9.1 Features

 More input source selection  The SH88F6161/SH88F6162 provides Internally high-performance operational amplifier, Single power supply  Op can be shut dowm by software in order to reduce power consume 10DAC OPP0 OPOPPSEL OPP1 DAC OPN0 OPNSEL OPN1 00 OPN2

9.9.2 Registers

Table 9.66 OP Control Register A1H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 OPCON OPEN - - - OPPSEL.1 OPPSEL.0 OPNSEL.1 OPNSEL.0 R/W R/W - - - R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) 0 - - - 0 0 0 0 Bit Number Bit Mnemonic Description

7 OPEN

0: disable OP function 1: enable OP function 3-2 OPPSEL[1:0] OP positive phase input source selection bit 00: OPP0 01: OPP1 10: DAC internal input 1-0 OPNSEL[1:0] OP negative phase input source select 00: OPN0 01: OPN1 10: OPN2 11: DAC internal input (DAC external PIN as IO used) Table 9.67 OP Port Configuration Register A2H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 OPIOS - - - OPN2IO OPN1IO OPN0IO OPP1IO OPP0IO R/W - - - R/W R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) - - - 0 0 0 0 0 Bit Number Bit Mnemonic Description 4-2 OPNyIO OP negative phase input channel port configuration (y = 0, 1, 2) 0: P2.2 - P2.0 as IO 1: P2.2 - P2.0 as OP negative phase input 1-0 OPPxIO OP positive phase input channel port configuration (x = 0, 1) 0: P2.5 - P2.4 as IO 1: P2.5 - P2.4 as OP positive phase input

9.10 Low Voltage Reset (LVR)

9.10.1 Features

 Enabled by the code option and VLVR is 2.1V, 2.7V, 3.7V or 4.1V  LVR de-bounce timer TLVR is about 60μs  An internal reset flag indicates low voltage reset generates The LVR function is used to monitor the supply voltage and generate an internal reset in the device when the supply voltage below the specified value VLVR. The LVR de-bounce timer TLVR is about 60μs. The LVR circuit has the following functions when the LVR function is enabled: (T1 means the time of the supply voltage below VLVR) Generates a system reset when VDD ≤ VLVR and T1 ≥ TLVR; When VDD > VLVR + VHYS, release system reset. When VDD < VLVR, and T1 < TLVR, system reset can not occur. VHYS is in the range of 0.04V - 0.10V. VDD VLVR TLVR VHYS LVR Reset Here, VDD is the power supply voltage, VLVR is LVR detection voltage, VHYS is the hysteresis voltage of low voltage reset. The LVR function is enabled by the code option. It is typically used in AC line or large battery supplier applications, where heavy loads may be switched on and cause the MCU supply-voltage temporarily falls below the minimum specified operating voltage. This feature can protect system from working under bad power supply environment.

9.11 Low Power Detect (LPD)

9.11.1 Features

 An internal flag indicates low power is detected  LPD detect voltage is selectable  LPD the time jitter is 30-60μs of TLPD The low power detect (LPD) is used to monitor the supply voltage and generate an internal flag if the voltage decrease below the specified value. It is used to inform CPU whether the power is shut off or the battery is used out, so the software may d o some protection action before the voltage drop down to the minimal operation voltage. LPD interrupt can wake the Power-down mode.

9.11.2 Register

Table 9.68 Low Power Detection Control Register B3H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 LPDCON LPDEN - LPDMD LPDIF LPDS3 LPDS2 LPDS1 LPDS0 R/W R/W - R/W R/W R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) 0 - 0 0 0 0 0 0 Bit Number Bit Mnemonic Description

7 LPDEN

0: Disable lower power detection 1: Enable lower power detection

5 LPDMD

LPD mode selection control bit 0: when the V DD voltage is smaller than the LPD detect voltage set ting, the LPDIF flag is set to 1. 1: when the VDD voltage is larger than the LPD detect voltage setting, the LPDIF flag is set to 1.

4 LPDIF

0: no LPD interrupt occurred, clear to 0 by the software 1: LPD interrupt occurred ,set to one by the hardware 3-0 LPDS[3:0] LPD Voltage Select bit 0000: 2.1V 0001: 2.2V 0010: 2.3V 0011: 2.4V 0100: 2.5V 0101: 2.6V 0110: 2.7V 0111: 2.8V 1000: 2.9V 1001: 3.0V 1010: 3.1V 1011: 3.2V 1100: 3.3V 1101: 3.4V 1110: 3.5V 1111: 3.6V

9.12 Watchdog Timer (WDT) and Reset State

9.12.1 Features

 Auto detect Program Counter (PC) over range, and generate OVL Reset  WDT runs even in the Power-Down mode  Selectable different WDT overflow frequency OVL Reset To enhance the anti-noise ability, SH88F6161/SH88F6162 built in Program Counter (PC) over range detect circuit, if program counter value is larger than flash romsize, or detect operation code equal to A5H which is not exist in 8051 instruction set, a OVL reset will be generate to reset CPU, and set WDOF bit. So, to make use of this feature, you should fill unused flash rom with A5H. Watchdog Timer The watchdog timer is a down counter, and its clock source is an independent built-in RC oscillator, so it always runs even in the Power-Down mode. The watchdog timer will generate a device reset when it overflows. It can be enabled or disabled permanently by the code option. The watchdog timer control bits (WDT.2-0) are used to select different overflow frequency. The watchdog timer overflow flag (WDOF) will be automatically set to “1” by hardware when overflow happens. To prevent overflow happen, by reading or writing the WDT register RSTSTAT, the watchdog timer should re-count before the overflow happens.

9.12.2 Registers

Table 9.69 Reset Control Register B1H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 RSTSTAT WDOF - PORF LVRF CLRF WDT.2 WDT.1 WDT.0 R/D R/W - R/W R/W R/W R/W R/W R/W Reset Value (POR) 0 - 1 0 0 0 0 0 Reset Value (WDT) 1 - u u u 0 0 0 Reset Value (LVR) u - u 1 u 0 0 0 Reset Value (PIN) u - u u 1 0 0 0 Bit Number Bit Mnemonic Description

7 WDOF

Watch Dog Timer Overflow or OVL Reset Flag Set by hardware when WDT overflow or OVL reset happened, cleared by software or Power On Reset 0: Watch Dog not overflows and no OVL reset generated 1: Watch Dog overflow or OVL reset occurred

5 PORF

Set only by Power On Reset, cleared only by software 0: No Power On Reset 1: Power On Reset occurred

4 LVRF

Set only by Low Voltage Reset, cleared by software or Power On Reset 0: No Low Voltage Reset occurs 1: Low Voltage Reset occurred

3 CLRF

Set only by pin reset, cleared by software or Power On Reset 0: No Pin Reset occurs 1: Pin Reset occurred 2-0 WDT[2:0] WDT Overflow period control bits 000: Overflow period minimal value= 4096ms 001: Overflow period minimal value= 1024ms 010: Overflow period minimal value = 256ms 011: Overflow period minimal value = 128ms 100: Overflow period minimal value = 64ms 101: Overflow period minimal value = 16ms 110: Overflow period minimal value = 4ms 111: Overflow period minimal value = 1ms Notes: If WDT_opt is enable in application, you must clear WatchDog periodically, and the interval must be less than the value list above.

9.13 Power Management

9.13.1 Features

 Two power saving modes: Idle mode and Power-Down mode  Two ways to exit Idle and Power-Down mode: interrupt and reset To reduce power consumption, SH88F6161/SH88F6162 supplies two power saving modes: Idle mode and Power-Down mode. These two modes are controlled by PCON & SUSLO register.

9.13.2 Idle Mode

In this mode, the clock to CPU is frozen, the program execution is halted, and t he CPU will stop at a defined state. But the peripherals continue to be clocked. When entering idle mode, all the CPU status before entering will be preserved. Such as: PSW, PC, SFR & RAM are all retained. By two consecutive instructions: setting SUSLO register as 0x55, and immediately followed by setting the IDL bit in PCON register, will make SH88F6161/SH88F6162 enter Idle mode. If the consecutive instruction sequence requirement is not met, the CPU will clear either SUSLO register or IDL bit in the next machine period. And the CPU will not enter Idle mode. The setting of IDL bit will be the last instruction that CPU executed. There are two ways to exit Idle mode: (1) An interrupt generated. The clock to the CPU will be restored, and the hardware will c lear SUSLO register and IDL bit in PCON register. Then the program will execute the interrupt service routine first, and then jumps to the instruction immediately following the instruction that activated Idle mode. (2) Reset signal (logic low on the RESET pin, WDT RESET if enabled, LVR REST if enabled), this will restore the clock to the CPU, the SUSLO register and the IDL bit in PCON register will be cleared by hardware, finally the SH88F6161/SH88F6162 will be reset. And the program will execute from address 0000H. The RAM will keep unchanged and the SFR value might be changed according to different function module.

9.13.3 Power-Down Mode

The Power-Down mode places the SH88F6161/SH88F6162 in a very low power state.If the system clock is the low frequence clock (32.768KHz or128K RC), Power-Down mode will stop all the clocks including CPU and peripherals , and high frequency clock and low frequency clock will be closed; if the high-frequency oscillator (oscillator of 2 external 2M - 12M, the internal 12M RC or 1/2 prescale of PLL) is used as the system clock, high-frequency oscillator will be closed with 32.768KHz crystal or 128KHz RC clock of LCD andTimer3 reserved when enters power down mode. If enable WDT through code option, WDT modules will continue to work. Before entering power down mode all the state of the CPU have been preserved, such as PC, PSW, SFR, RAM and so on. By two consecutive instructions: setting SUSLO register as 0x55, and immediately followed by setting the PD bit in PCON register, will make SH88F6161/SH88F6162 enter Power-Down mode. If the consecutive instruction sequence requirement is not met, the CPU will clear either SUSLO register or PD bit in the next machine period. And the CPU will not enter Power-Down mode. The setting of PD bit will be the last instruction that CPU executed. Note: If IDL bit and PD bit are set simultaneously, the SH88F6161/SH88F6162 enters Power-Down mode. The CPU will not go in Idle mode when exiting from Power-Down mode, and the hardware will clear both IDL & PD bit after exit form Power-Down mode. There are 3 ways to exit the Power-Down mode: (1) An active external Interrupt such as INT2, INT3 or INT40 - 47, LPD Interrupt、USB Interrupt (Detect plug/unplug, a bus reset, the resume command) and Timer3 on external counting Interrupt will make SH88F6161/SH88F6162 exit Power -Down mode. The oscillator will start after interrupt happens, and after warm-up time, the clocks to the CPU and peripheral will be restored, the SUSLO register and PD bit in PCON register will be cleared by hardware. Program execution resumes with the interrupt service routine. After completion of the interrupt service routine, program execution resumes with the instruction immediately following the instruction that activated Power-Down mode. (2) If the 32.768kHz crystal or 128KHz RC is not closed, timer 3 interrupt generation will cause SH88F6161/SH88F6162 enter to Power-Down mode. after warm-up time, the clocks to the CPU and peripheral will be restored, the SUSLO register and PD bit in PCON register will be cleared by hardware. Program execution resumes with the interrupt service routine. After completion of the interrupt service routine, program execution resumes with the instruction immediately following the instruction that activated Power-Down mode. (3) Reset signal (logic high on the RESET pin, WDT RESET if enabled, LVR REST if enabled). This will resume the clock to the CPU after warm -up time, the SUSLO register and the PD bit in PCON register will be cleared by hardware, finally the SH88F6161/SH88F6162 will be reset. And the program will execute from address 0000H. The RAM will keep unchanged and the SFR value might be changed according to different function module. Note: (1) In order to entering Idle/Power-Down, it is necessary to add 3 NOPs after setting IDL/PD bit in PCON. (2) In order to entering Idle/Power-Down, all ports are not floating, set to output or input with pull-high.

9.13.4 Register

Table 9.70 Power Control Register 87H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PCON - - - - GF1 GF0 PD IDL R/W - - - - R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) - - - - 0 0 0 0 Bit Number Bit Mnemonic Description 3-2 GF[1:0] General purpose flags for software use 1 PD Power-Down mode control bit 0: Cleared by hardware when an interrupt or reset occurs 1: Set by software to activate the Power-Down mode

0 IDL

0: Cleared by hardware when an interrupt or reset occurs 1: Set by software to activate the Idle mode Table 9.71 Suspend Mode Control Register 8EH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) 0 0 0 0 0 0 0 0 Bit Number Bit Mnemonic Description 7-0 SUSLO[7:0] This register is used to control the CPU enter suspend mode (Idle or Power-Down). Only consecutive instructi ons like below will make CPU enter suspend mode. Otherwise the either SUSLO, IDL or PD bit will be cleared by hardware in the next machine period. IDLE_MODE: MOV SUSLO, #55H ORL PCON, #01H NOP NOP NOP POWERDOWN_MODE: MOV SUSLO, #55H ORL PCON, #02H NOP NOP NOP

9.14 Warm-up Timer

9.14.1 Featueres

 Built-in power on warm-up counter to eliminate unstable state of power on  Built-in oscillator warm-up counter to eliminate unstable state when oscillation startup SH88F6161/SH88F6162 has a built-in power warm-up counter; it is designed to eliminate unstable state after power on or to do some internal initial operation such as read customer option etc. SH88F6161/SH88F6162 has also a built-in oscillator warm-up counter, it is designed to eliminate unstable state when oscillator starts oscillating in the following conditions: Power -on reset, Pin reset, LVR reset, Watchdog Reset and Wake up from Power-down mode. After power-on, SH88F6161/SH88F6162 will start power warm-up procedure first, and then oscillator warm-up procedure. Power Warm-up Time Power On Reset/ Pin Reset/ Low Voltage Reset WDT Reset (Not in Power-Down Mode) WDT Reset (Wakeup from Power-Down Mode) Wakeup from Power-Down Mode (Only for interrupt) TPWRT** OSC Warm up* TPWRT** OSC Warm up* TPWRT** OSC Warm up* TPWRT** OSC Warm up* 11ms YES 500us NO 500us YES 32us YES OSC Warm-up Time Option OP_WMT Oscillator Type 00 01 10 11 Ceramic/Crystal 217 X Tosc 214 X Tosc 211 X Tosc 28 X Tosc 32kHz Crystal 214 X Tosc Internal RC 27 X Tosc PLL 2ms

9.15 Code Option

OP_WDT: 0: Disable WDT function (default) 1: Enable WDT function OP_WDTPD: 0: Disable WDT function in Power-Down mode (default) 1: Enable WDT function in Power-Down mode OP_WMT: (unavailable for 32kHz crystal and Internal RC) 00: longest warm up time (default) 01: longer warm up time 10: shorter warm up time 11: shortest warm up time OP_RST: 0: enable pin reset(default) 1: select P7.0 as IO OP_LVREN: 0: Disable LVR function (default) 1: Enable LVR function OP_LVRLEVEL: 00: 4.1V 01: 3.7V (default) 10: 2.7V 11: 2.1V OP_SCM: 0: SCM is invalid in warm up period (default) 1: SCM is valid in warm up period OP_OSC[3:0]: 0011: OSC1CLK is internal 128KHz RC oscillator, OSC2CLK is internal 12MHz RC oscillator (default) 0110: OSC1CLK is internal 128K RC, OSC2CLK is 2M - 12M crystal/ceramic resonator input from XTAL 1010: OSC1CLK is 32.768kHz crystal resonator input from XTAL, OSC2CLK is internal 12M RC oscillator 1101: OSC1CLK is 32.768kHz crystal resonator input from XTAL, OSC2CLK is 2M - 12M crystal/ceramic resonator input from XTALX Other: OSC1CLK is 128KHz internal RC oscillator, OSC2CLK is internal 12MHz RC oscillator OP_ISP: 0: Enable ISP function (default) 1: Disable ISP function OP_ISPPIN: 0: Enter ISP mode directly regardless the condition of P3.4 and P3.5 (default) 1: Enter ISP mode only when P3.4 and P3.5 are connected to GND, simultaneously Note: When OP_ISP = 0, this option is available. OP_DACTIME: (DAC conversion time selection) 00: 100us (default) 01: 70us 10: 150us 11: 200us OP_OSCDRV: 011: 8M - 12M crystal (default) 001: 4M crystal 111: 12M ceramic 101: 8M ceramic 110: 4M ceramic 100: 2M ceramic OP_SINK: 0: current sinking capability of the P0/P1 port remains constant (default) 1: Increase the current sinking capability of the P0/P1 port OP_DRIVE: 0: the current drive capability of the P3/P4 port remained unchanged (default) 1: Increasing the driving current capacity of the P3/P4 port

1. Instruction Set ARITHMETIC OPERATIONS Opcode Description Code Byte Period ADD A, Rn Add register to accumulator 0x28-0x2F 1 1 ADD A, direct Add direct byte to accumulator 0x25 2 2 ADD A, @Ri Add indirect RAM to accumulator 0x26-0x27 1 2 ADD A, #data Add immediate data to accumulator 0x24 2 2 ADDC A, Rn Add register to accumulator with carry flag 0x38-0x3F 1 1 ADDC A, direct Add direct byte to A with carry flag 0x35 2 2 ADDC A, @Ri Add indirect RAM to A with carry flag 0x36-0x37 1 2 ADDC A, #data Add immediate data to A with carry flag 0x34 2 2 SUBB A, Rn Subtract register from A with borrow 0x98-0x9F 1 1 SUBB A, direct Subtract direct byte from A with borrow 0x95 2 2 SUBB A, @Ri Subtract indirect RAM from A with borrow 0x96-0x97 1 2 SUBB A, #data Subtract immediate data from A with borrow 0x94 2 2 INC A Increment accumulator 0x04 1 1 INC Rn Increment register 0x08-0x0F 1 2 INC direct Increment direct byte 0x05 2 3 INC @Ri Increment indirect RAM 0x06-0x07 1 3 DEC A Decrement accumulator 0x14 1 1 DEC Rn Decrement register 0x18-0x1F 1 2 DEC direct Decrement direct byte 0x15 2 3 DEC @Ri Decrement indirect RAM 0x16-0x17 1 3 INC DPTR Increment data pointer 0xA3 1 4 MUL AB 8 X 8

16 X 8 Multiply A and B 0xA4 1 11

16 / 8 Divide A by B 0x84 1 11 DA A Decimal adjust accumulator 0xD4 1 1

Opcode Description Code Byte Period ANL A, Rn AND register to accumulator 0x58-0x5F 1 1 ANL A, direct AND direct byte to accumulator 0x55 2 2 ANL A, @Ri AND indirect RAM to accumulator 0x56-0x57 1 2 ANL A, #data AND immediate data to accumulator 0x54 2 2 ANL direct, A AND accumulator to direct byte 0x52 2 3 ANL direct, #data AND immediate data to direct byte 0x53 3 3 ORL A, Rn OR register to accumulator 0x48-0x4F 1 1 ORL A, direct OR direct byte to accumulator 0x45 2 2 ORL A, @Ri OR indirect RAM to accumulator 0x46-0x47 1 2 ORL A, #data OR immediate data to accumulator 0x44 2 2 ORL direct, A OR accumulator to direct byte 0x42 2 3 ORL direct, #data OR immediate data to direct byte 0x43 3 3 XRL A, Rn Exclusive OR register to accumulator 0x68-0x6F 1 1 XRL A, direct Exclusive OR direct byte to accumulator 0x65 2 2 XRL A, @Ri Exclusive OR indirect RAM to accumulator 0x66-0x67 1 2 XRL A, #data Exclusive OR immediate data to accumulator 0x64 2 2 XRL direct, A Exclusive OR accumulator to direct byte 0x62 2 3 XRL direct, #data Exclusive OR immediate data to direct byte 0x63 3 3 CLR A Clear accumulator 0xE4 1 1 CPL A Complement accumulator 0xF4 1 1 RL A Rotate accumulator left 0x23 1 1 RLC A Rotate accumulator left through carry 0x33 1 1 RR A Rotate accumulator right 0x03 1 1 RRC A Rotate accumulator right through carry 0x13 1 1 SWAP A Swap nibbles within the accumulator 0xC4 1 4

Opcode Description Code Byte Period MOV A, Rn Move register to accumulator 0xE8-0xEF 1 1 MOV A, direct Move direct byte to accumulator 0xE5 2 2 MOV A, @Ri Move indirect RAM to accumulator 0xE6-0xE7 1 2 MOV A, #data Move immediate data to accumulator 0x74 2 2 MOV Rn, A Move accumulator to register 0xF8-0xFF 1 2 MOV Rn, direct Move direct byte to register 0xA8-0xAF 2 3 MOV Rn, #data Move immediate data to register 0x78-0x7F 2 2 MOV direct, A Move accumulator to direct byte 0xF5 2 2 MOV direct, Rn Move register to direct byte 0x88-0x8F 2 2 MOV direct1, direct2 Move direct byte to direct byte 0x85 3 3 MOV direct, @Ri Move indirect RAM to direct byte 0x86-0x87 2 3 MOV direct, #data Move immediate data to direct byte 0x75 3 3 MOV @Ri, A Move accumulator to indirect RAM 0xF6-0xF7 1 2 MOV @Ri, direct Move direct byte to indirect RAM 0xA6-0xA7 2 3 MOV @Ri, #data Move immediate data to indirect RAM 0x76-0x77 2 2 MOV DPTR, #data16 Load data pointer with a 16-bit constant 0x90 3 3 MOVC A, @A+DPTR Move code byte relative to DPTR to A 0x93 1 7 MOVC A, @A+PC Move code byte relative to PC to A 0x83 1 8 MOVX A, @Ri Move external RAM (8-bit address) to A 0xE2-0xE3 1 5 MOVX A, @DPTR Move external RAM (16-bit address) to A 0xE0 1 6 MOVX @Ri, A Move A to external RAM (8-bit address) 0xF2-F3 1 4 MOVX @DPTR, A Move A to external RAM (16-bit address) 0xF0 1 5 PUSH direct Push direct byte onto stack 0xC0 2 5 POP direct Pop direct byte from stack 0xD0 2 4 XCH A, Rn Exchange register with accumulator 0xC8-0xCF 1 3 XCH A, direct Exchange direct byte with accumulator 0xC5 2 4 XCH A, @Ri Exchange indirect RAM with accumulator 0xC6-0xC7 1 4 XCHD A, @Ri Exchange low-order nibble indirect RAM with A 0xD6-0xD7 1 4

Opcode Description Code Byte Period ACALL addr11 Absolute subroutine call 0x11-0xF1 2 7 LCALL addr16 Long subroutine call 0x12 3 7 RET Return from subroutine 0x22 1 8 RETI Return from interrupt 0x32 1 8 AJMP addr11 Absolute jump 0x01-0xE1 2 4 LJMP addr16 Long jump 0x02 3 5 SJMP rel Short jump (relative address) 0x80 2 4 JMP @A+DPTR Jump indirect relative to the DPTR 0x73 1 6 JZ rel (not taken) (taken) Jump if accumulator is zero 0x60 2 3 JNZ rel (not taken) (taken) Jump if accumulator is not zero 0x70 2 3 JC rel (not taken) (taken) Jump if carry flag is set 0x40 2 2 JNC rel (not taken) (taken) Jump if carry flag is not set 0x50 2 2 JB bit, rel (not taken) (taken) Jump if direct bit is set 0x20 3 4 JNB bit, rel (not taken) (taken) Jump if direct bit is not set 0x30 3 4 JBC bit, rel (not taken) (taken) Jump if direct bit is set and clear bit 0x10 3 4 CJNE A, direct, rel (not taken) (taken) Compare direct byte to A and jump if not equal 0xB5 3 4 CJNE A, #data, rel (not taken) (taken) Compare immediate to A and jump if not equal 0xB4 3 4 CJNE Rn, #data, rel (not taken) (taken) Compare immediate to reg. and jump if not equal 0xB8-0xBF 3 4 CJNE @Ri, #data, rel (not taken) (taken) Compare immediate to Ri and jump if not equal 0xB6-0xB7 3 4 DJNZ Rn, rel (not taken) (taken) Decrement register and jump if not zero 0xD8-0xDF 2 3 DJNZ direct, rel (not taken) (taken) Decrement direct byte and jump if not zero 0xD5 3 4 NOP No operation 0 1 1

Opcode Description Code Byte Period CLR C Clear carry flag 0xC3 1 1 CLR bit Clear direct bit 0xC2 2 3 SETB C Set carry flag 0xD3 1 1 SETB bit Set direct bit 0xD2 2 3 CPL C Complement carry flag 0xB3 1 1 CPL bit Complement direct bit 0xB2 2 3 ANL C, bit AND direct bit to carry flag 0x82 2 2 ANL C, /bit AND complement of direct bit to carry 0xB0 2 2 ORL C, bit OR direct bit to carry flag 0x72 2 2 ORL C, /bit OR complement of direct bit to carry 0xA0 2 2 MOV C, bit Move direct bit to carry flag 0xA2 2 2 MOV bit, C Move carry flag to direct bit 0x92 2 3

1. Electrical Characteristics Absolute Maximum Ratings *Comments Stresses exceed those listed under “ Absolute Maximum Ratings” may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. Parameter Symbol Min. Typ.∗ Max. Unit Condition Operating Voltage VDD 2.0 5.0 5.5 V fOSC = 12MHz Operating Current IOP1 - 4 8 mA fOSC = 12MHz, VDD = 5.0V All output pins unload (including all digital input pins unfloating) CPU on (execute NOP instruction), t he WDT and LVR on, all other function block off IOP2 - 40 80 µA fOSC = 128kHz, VDD = 5.0V All output pins unload (including all digital input pins unfloating) CPU on (execute NOP instruction), the WDT and LVR on, all other function block off IOP3 - 25 35 µA fOSC = 32.768kHz, VDD = 5.0V All output pins unload (including all digital input pins unfloating) CPU on (execute NOP instruction), the WDT and LVR on, all other function block off Stand by Current (IDLE) ISB1 - 3 5 mA fOSC = 12MHz, VDD = 5.0V All output pins unload (including all digital input pins unfloating) CPU off (idle), the WDT turn off, LVR and LCD turn on (VOL[3:0] = 0000, LCD bias resistor sum is 900K, not including LCD panel ), all other function block off ISB2 - 25 45 µA fOSC =128KHz, VDD = 5.0V All output pins unload (including all digital input pins unfloating) CPU off (idle), the WDT turn off, LVR and LCD turn on (VOL[3:0] = 0000, LCD bias resistor sum is 900K, not including LCD panel) , all other function block off ISB3 - 15 22 µA fOSC = 32.768kHz, VDD = 5.0V All output pins unload (including all digital input pins unfloating) CPU off (idle), the WDT turn off, LVR and LCD turn on (VOL[3:0] = 0000, LCD bias resistor sum is 900K, not including LCD panel), all other function block off (to be continued)

(continue) Stand by Current (power-down) ISB4 - 20 27 µA fOSC = 128kHz the high frequency oscillator closed, VDD = 5.0V All output pins unload (including all digital input pins unfloating) CPU off (power-down), the WDT turn off, LVR and LCD turn on (VOL[3:0] = 0000, LCD bias resistor sum is 900K , not including LCD panel ), Timer3 opened, all other function block off ISB5 - 8 15 µA fOSC = 32.768kHz, the high frequency oscillator closed, VDD = 5.0V All output pins unload (including all digital input pins unfloating), CPU off (power-down), the WDT turn off, LVR turn ON, all other function block off ISB6 - 5 10 µA fOSC closed, VDD = 5.0V All output pins unload (including all digital input pins unfloating) CPU off (power-down), the WDT and LVR off, all other function block off WDT Current IWDT - 1 3 µA VDD = 5.0V, WDT on LCD Current1 ILCD1 - 3 5 µA The traditional LCD model, VDD = 5.0V LCD bias resistor sum is 900K VOL[3:0] = 0000 (not including LCD panel) LCD Current2 ILCD2 - 6 8 µA LCD fast change power model, VDD = 5.0V LCD bias resistor sum is 900K, 1/16 period of LCD com VOL[3:0] = 0000 (not including LCD panel) Input low Voltage1 VIL1 GND - 0.3 X VDD V I/O port Input High Voltage1 VIH1 0.7 X VDD - VDD V I/O port Input low Voltage2 VIL2 GND - 0.2 X VDD V RESET , T2, T3, INT/2/3/4, T2EX, RXD, RXD1, PxCEX0 – 1 (x = 0 - 3), P1CEX2, MISO, MOSI, ECI0 - 3, SDA, SCL, SCK, SS VDD = 2.4V - 5.5V Input High Voltage2 VIH2 0.8 X VDD - VDD V RESET , T2, T3, INT/2/3/4, T2EX, RXD, RXD1, PxCEX0 – 1 (x = 0 - 3), P1CEX2, MISO, MOSI, ECI0 - 3, SDA, SCL, SCK, SS VDD = 2.4V~5.5V Input Leakage Current IIL -1 - 1 µA Input port, VIN = VDD or GND Pull-high Resistor RPH - 30 - kΩ VDD = 5.0V, VIN = GND Output High Voltage VOH VDD - 0.7 - - V I/O port, IOH = -10mA, VDD = 5.0V Output Low Voltage VOL - - GND + 0.6 V I/O port, IOL = 15mA, VDD = 5.0V LCD output Resistor VON - 5 - kΩ COM1-6, SEG1-40, VDD = 2.0V - 5.5V V1, V2, V3 voltage deviation is lower than 0.2V LED SEG Drive current ILED_SEG 7 10 - mA LED SEG port, VDD = 5.0V, VOH = VDD - 0.7V LED COM Sink current ILED_COM 56 80 - mA LED COM port, VDD = 5.0V, VOL = GND + 1.5V P1, P0 port sink current capability IOL 80 100 - mA P1, P0 (OP_SINK = 1), VDD = 5.0V, VOL = GND + 1.5V P3, P4 port drive current capability IOH - 15 - mA P3, P4 (OP_DRIVE = 1), VDD = 5.0V, output high voltage ≥ VDD - 0.7 Note: (1) “∗” Data in “Typ.” Column is at 5.0V, 25°C, unless otherwise specified. (2) Maximum value of the supply current to VDD is 100mA. (3) Maximum value of the output current from GND is 150mA.

High Speed Conversion Mode 10 BIT Analog/Digital Converter Electrical Characteristics (1LSB = VDD/1024) The Conversion Rate of 1M SPS. (VDD = 2.7 - 5.5V, GND = 0V, TA = +25°C, unless otherwise specified) Parameter Symbol Min. Typ Max. Unit Condition Operating voltage range VAD 2.7 5.0 5.5 V Resolution NR - 10 - bit VREF = 5.0V A/D input voltage VAIN GND - VREF V A/D input resistance RAIN 2 - - MΩ VIN = 5.0V The external analog reference voltage VREF 2.5 VDD V In order to ensure the accuracy of input is greater than 2.5V Recommended impedance of input analog voltage source ZAIN - - 1 kΩ A/D switching current IAD - 1.5 3 mA ADC model working, VDD = 5.0V Differential linearity error IAD - 1.5 3 mA VDD = 5.0V, VREF = 5.0V, ADC CLK ≤ 27MHz Integral linearity error DLE - - ±1 LSB VDD = 5.0V, VREF = 5.0V, ADC CLK ≤ 27MHz Full scale error ILE - - ±2 LSB VDD = 5.0V, VREF = 5.0V, ADC CLK ≤ 27MHz Offset error EF - ±3 LSB VDD = 5.0V, VREF = 5.0V, ADC CLK ≤ 27MHz Total absolute error EZ - - ±2 LSB VDD = 5.0V, VREF = 5.0V, ADC CLK ≤ 27MHz ADC clock period EAD - - ±3 LSB VREF = 5.0V ADC sampling time tAD 0.04 - 80 µs Total conversion time tSAMP 2 - 15 tAD Operating voltage range TCON 16 - 29 tAD Low Speed Conversion Mode, 12 BIT Analog/Digital Converter Electrical Characteristics (1LSB = VDD/4096) The Conversion Rate of 100K SPS. (VDD = 2.4 - 5.5V, GND = 0V, TA = +25°C, unless otherwise specified) Parameter Symbol Min. Typ Max. Unit Condition Operating voltage range VAD 2.4 5.0 5.5 V Precision NR - 12 - bit VREF = 5.0V A/D input voltage* VAIN GND - VREF V A/D input resistance RAIN 2 - - MΩ VIN = 5.0V The external analog reference voltage VREF 2.5 - VDD V Recommended impedance of analog voltage source ZAIN - - 5 kΩ A/D convert current IAD - 1.5 3 mA ADC model working, VDD = 5.0V Differential linearity error DLE - - ±1 LSB VDD = 5.0V, VREF = 5.0V, ADC CLK ≤ 2.7MHz Integral linearity error ILE - - ±2 LSB VDD = 5.0V, VREF = 5.0V, ADC CLK ≤ 2.7MHz Full scale error EF - - ±8 LSB VDD = 5.0V, VREF = 5.0V, ADC CLK ≤ 2.7MHz Offset error EZ - - ±8 LSB VDD = 5.0V, VREF = 5.0V, ADC CLK ≤ 2.7MHz Total absolute error EAD - - ±8 LSB VDD = 5.0V, VREF = 5.0V, ADC CLK ≤ 2.7MHz ADC clock period tAD 0.3 - 80 µs ADC sampling time tSAMP 2 - 15 tAD Total conversion time TCON 16 - 29 tAD operating voltage range VAD 2.4 5.0 5.5 V

12bit Voltage Type DAC (VDD = 2.4 - 5.5V, GND = 0V, TA = +25°C, unless otherwise specified) Parameter Symbol Min. Typ Max. Unit Condition Operating Voltage VDD 2.4 - 5.5 V Operating Current IDD - - 1 mA The conversion rate is 100us; buffer output; buffer no load The power supply rejection ratio PSRR - 70 - dB VDD plus 100mV, 1KHz sine wave Differential linearity error DNL - - ±1.0 LSB VREF = 1.5V/2.5V, without buffer output Integral linearity error INL - - ±3.0 LSB VREF = 2.5V, without buffer output - - ±5.0 VREF = 1.5V, without buffer output Resolution NR 12 - - bit VDD = 2.4 - 5.5V, the monotone output Offset error VOFF - - ±10 mV VREF = 1.5V/2.5V, with buffer output, digital output 1/2 VREF; compare the true output voltage with the theoretical values, without calibration - - ±3 mV VREF = 1.5V/2.5V, with buffer output, digital output 1/2 VREF; compare the true output voltage with the theoretical values, without calibration - - ±1 mV VREF = 1.5V/2.5V, without buffer output, digital output 0; compare the true output voltage with the theoretical values Temperature drift of offset error DvOFF/Dt - 30 - uV/°C TA = -40~85℃, with buffer output, does not contain the VREF offset Gain error Vgain - - ±2 %FSR VREF = 1.5V/2.5V, with buffer output, does not contain the VREF offset Temperature drift of gain error Dvgain /Dt - 10 - ppm FSR/°C TA = -40~85 ℃, with buffer output, does not contain the VREF offset Output current capability IL -1 - 1 mA VDD = 2.4 - 5.5V, with buffer output capability Output Voltage VOUTL_ NOBUFFER 0.0005 - - V without buffer output VOUTH_ NOBUFFER - VREF-1 LSB - V without buffer output VOUTL_ BUFFER 0.2 - - V with buffer output VOUTH_ BUFFER - - VDD-0.2 V with buffer output Stable Time Tsettling - - 10 µs DAC data change from 000H to FFFH, and then return to 000H within output stability to 1/2 LSB, CLOAD = 10pF, without buffer output - - 60 µs DAC data from 000H to FFFH, and then return to the 000H, within output voltage stability to 1/2 LSB, CLOAD =100pF, with buffer (*1) output - - 60 µs DAC data from 000H to FFFH, and then return to the 000H, within output voltage stability to 1/2 LSB, C LOAD = 100pF, with buffer (*3) output - - 60 µs DAC data from 308H to 408H, and then return to the 308H, within output voltage stability to 1/2 LSB C LOAD = 10pF, without buffer output - - 30 µs DAC data from 308H to 408H, and then return to the 308H, C LOAD = 100pF, within output voltage stability to 1/2 LSB, with buffer (*1) output - - 30 µs DAC data from 308H to 408H, and then return to the 308H, C LOAD = 100pF, within output voltage stability to 1/2 LSB, with buffer (*3) output (to be continued)

(continue) Reference Voltage VREF 1.4775 1.5 1.5225 V VDD = 2.4 - 5.5V Temperature drift for reference voltage TREF - - 100 ppm/° C TA = -40 - 85℃ Parameter Symbol Min. Typ Max. Unit Condition Input High Voltage (Driving) VIH(USB) 2.0 - - V D-, D+ Input High Voltage (Floating) VIHZ(USB) 2.7 - 3.6 V D-, D+ Input Low Voltage VIO(USB) - - 0.8 V D-, D+ Differential Input Sensitivity VDI(USB) 0.2 - - V D-, D+ (|VD+-VD-|) Differential Common-Mode Input Range VCM(USB) 0.8 - 2.5 V D-, D+ (Include VDI range) Output Low Voltage VOL(USB) 0.0 - 0.3 V D-, D+ Output High Voltage (Driving) VOH(USB) 2.8 - 3.6 V D-, D+ Output Cross Voltage VCRS(USB) 1.3 - 2.0 V D-, D+, VDD = 4.0V - 5.5V Parameter Symbol Min. Typ Max. Unit Condition Input high voltage VIH 0.7 X VDD - VDD+0.7V V SDA, SCL Input low voltage VIL - - 0.3 X VDD V SDA, SCL Output low voltage VOL 0 - 0.4 V SDA and SCL, IOL = -7mA@ VDD = 3V TWI frequency range fTWI 0 - 400 kHz fSYS ≧ 4MHz, SH88F6161/SH88F6162 in slave mode 0 - 100 fSYS ≧ 1MHz, SH88F6161/SH88F6162 in slave mode - FSYS/(16 + 2 X CR X TWIBR) - SH88F6161/SH88F6162 in Master mode Bus idle interval tBUF 4.7 - - µs fSYS ≧ 1MHz, SH88F6161/SH88F6162 in slave mode 1.3 - - fSYS ≧ 4MHz, SH88F6161/SH88F6162 in slave mode - 1/2fTWI - - SH88F6161/SH88F6162 in Master mode low level period tLOW 4.7 - - µs fSYS ≧ 1MHz, SH88F6161/SH88F6162 in slave mode 1.3 - - fSYS ≧ 4MHz, SH88F6161/SH88F6162 in slave mode - 1/2fTWI - - SH88F6161/SH88F6162 in Master mode High level period tHIGH 4.0 - - µs fSYS ≧ 1MHz, SH88F6161/SH88F6162 in slave mode 0.6 - - fSYS≧4MHz, SH88F6161/SH88F6162 in slave mode - 1/2fTWI - - SH88F6161/SH88F6162 in Master mode Data hold time tHD: DAT 300 - - ns fSYS ≧ 1MHz, SH88F6161/SH88F6162 in slave mode 0 - - fSYS≧4MHz, SH88F6161/SH88F6162 in slave mode - 1/2fTWI - - SH88F6161/SH88F6162 in Master mode Data set up time tSU: DAT 250 - - ns fSYS ≧ 1MHz, SH88F6161/SH88F6162 in slave mode 100 - - fSYS ≧ 4MHz, SH88F6161/SH88F6162 in slave mode 250 - - SH88F6161/SH88F6162 in Master mode (to be continued)

(continue) STA hold time tHD: STA 4.0 - - µs fSYS ≧ 1MHz, SH88F6161/SH88F6162 in slave mode 1.0 - - fSYS ≧ 4MHz, SH88F6161/SH88F6162 in slave mode - 1/2fTWI - - SH88F6161/SH88F6162 in Master mode STA set up time tSU: STA 4.7 - - µs fSYS ≧ 1MHz, SH88F6161/SH88F6162 in slave mode 0.6 - - fSYS ≧ 4MHz, SH88F6161/SH88F6162 in slave mode - 1/2fTWI - - SH88F6161/SH88F6162 in Master mode STO set up time tSU: STO 4.0 - - µs fSYS ≧ 1MHz, SH88F6161/SH88F6162 in slave mode 0.6 - - fSYS ≧ 4MHz, SH88F6161/SH88F6162 in slave mode - 1/2fTWI - - SH88F6161/SH88F6162 in Master mode Rise time tR - - 1000 ns fSYS ≧ 1MHz, SH88F6161/SH88F6162 in slave mode 300 fSYS ≧ 4MHz, (VILMAX - 0.15V) to (VIHMIN + 0.15V), SH88F6161/SH88F6162 in slave mode or master mode Fall time tF - - 300 ns (VIHMIN + 0.15V) to (VILMAX - 0.15), SH88F6161/SH88F6162 in slave mode or master mode The timeout period tTIMEOUT - N*Tsys - ms SH88F6161/SH88F6162 in slave mode or master mode Operational Amplifier Electrical Characteristics (VDD = 2.4 - 5.5V, GND = 0V, TA = +25°C, the test voltage fllower mode) Parameter Symbol Min. Typ Max. Unit Condition Operating voltage VDD 2.4 - 5.5 V Operating current IOP - 300 450 uA Input common- mode voltage VICM 0 - VDD-1.2 V Input offset voltage VIO - - 8 mV Conversion rate SR - 1.2 - V/us CL = 50pF Output high voltage VOH VDD-0.2 - VDD V Output low voltage VOL 0 - 0.2 V Voltage rejection ratio PSRR - 65 - dB DC characteristics The common-mode rejection ratio CMRR - 80 - dB DC characteristics The unity gain band width GBW - 3 - MHz Voltage gain for Open loop - - 100 - dB Output capacity (sink current and pull current capability) IO 30 mA VDD = 5V, VOUT =1.0V (sink current) or 4V (pull current) Regulator Electrical Characteristics (VDD = 3.6 - 5.5V, GND = 0V, TA = 25°C, unless otherwise specified) Parameter Symbol Min. Typ Max. Unit Condition Operating Voltage VDD 3.6 - 5.5 V Output Current IDRV - 30 - mA Supply Current ISS - 50 100 µA

Parameter Symbol Min. Typ Max. unit condition Oscillator start time TOSC1 - 1 2 ms fOSC = 12MHz TOSC2 - 1 2 s fOSC = 32.768kHz RESET pulse width tRESET 10 - - µs Low active RESET Pin Pull-high Resistor RRPH - 30 - kΩ VDD = 3.0V, VIN = GND WDT RC Frequency FWDT - - 2 KHz RC Frequency in high-frequency mode FRC 11.88 12 12.12 MHz 12M internal RC, Contains the changes between piece and piece (VDD = 2.0 - 5.5V, TA = 25°C) PLL Frequency FRC 11.76 12 12.24 % 48M PLL Oscillator, Contains the changes between piece and piece 32.768kHz oscillator starting error < 0.01% Oscillator start time FPLL - 48 - MHz fOSC = 12MHz Low Voltage Reset Electrical Characteristics (VDD = 2.0 - 5.5V, GND = 0V, TA = 25°C, unless otherwise specified) Parameter Symbol Min. Typ Max. unit condition LVR voltage1 VLVR1 2.0 2.1 2.2 V LVR enable VDD = VLVR1 - 5.5V LVR voltage2 VLVR2 2.6 2.7 2.8 V LVR enable VDD = VLVR2 - 5.5V LVR voltage3 VLVR3 3.6 3.7 3.8 V LVR enable VDD = VLVR3 - 5.5V LVR voltage4 VLVR4 4.0 4.1 4.2 V LVR enable VDD = VLVR4 - 5.5V Drop-Down Pulse Width for LVR TLVR - 60 - µs

1. Ordering Information Part No. Package SH88F6161S/064SR LQFP64 SH88F6162S/064SR LQFP64 SH88F6161U/048UR TQFP48 SH88F6162U/048UR TQFP48

1. Product Identification System R:Tray S:LQFP64(7*7) Package 064:Package Pin Number is 64 /:Separator SH 88 F 6 161 S / 064 S R S:LQFP64(7*7) Package 161:Product Serial Number F:flash Product 88:8051 Kernel SH:SinoWealth 6:ROM Size 64K bytes R:Tray S:LQFP64(7*7) Package 064:Package Pin Number is 64 /:Separator SH 88 F 6 162 S / 064 S R S:LQFP64(7*7) Package 162:Product Serial Number F:flash Product 88:8051 Kernel SH:SinoWealth 6:ROM Size 64K bytes

R:Tray U:TQFP Package 048:Package Pin Number is 48 /:Separator SH 88 F 6 161 U / 048 U R U:TQFP Package 161:Product Serial Number F:flash Product 88:8051 Kernel SH:SinoWealth 6:ROM Size 64K bytes R:Tray U:TQFP Package 048:Package Pin Number is 48 /:Separator SH 88 F 6 162 U / 048 U R U:TQFP Package 162:Product Serial Number F:flash Product 88:8051 Kernel SH:SinoWealth 6:ROM Size 64K bytes

1. Package Information LQFP 64L Outline Dimensions (BODY SIZE: 7 X 7) unit: inch/mm b D HD E HE 17 32 4964 See Detail F A A2A1 L c DETAIL F e Symbol Dimensions in inches Dimensions in mm MIN MAX MIN MAX A1 0.002 0.006 0.050 0.150 A2 0.053 0.057 1.350 1.450 D 0.272 0.280 6.900 7.100 E 0.272 0.280 6.900 7.100 HD 0.346 0.362 8.800 9.200 HE 0.346 0.362 8.800 9.200 b 0.006 0.009 0.160 0.240 e 0.016BSC 0.400BSC c 0.004 0.008 0.090 0.200 L 0.016 0.030 0.400 0.750 L1 0.033 0.045 0.850 1.150 θ2 0° 10° 0° 10° Notice: 1. Both package length and width do not include mold flash. 2. Tolerance is ±0.1mm if not specified. 3. Coplanarity:0.1mm max. 4. Controlling dimension: mm.

TQFP 48L Outline Dimensions unit: inch/mm b D HD E HE 13 24 3748 See Detail F A A2A1 L c DETAIL F e Symbol Dimensions in inches Dimensions in mm MIN MAX MIN MAX A1 0.002 0.006 0.05 0.15 A2 0.035 0.041 0.9 1.05 D 0.270 0.281 6.85 7.15 E 0.270 0.281 6.85 7.15 HD 0.346 0.362 8.8 9.2 HE 0.346 0.362 8.8 9.2 b 0.005 0.011 0.15 0.27 e 0.020 TYP 0.500 TYP c 0.004 0.008 0.090 0.200 L 0.018 0.030 0.45 0.75 L1 0.033 0.045 0.85 1.15 θ2 0° 10° 0° 10° Notice: 1. Both package length and width do not include mold flash. 2. Tolerance is ±0.1mm if not specified. 3. Coplanarity:0.1mm max. 4. Controlling dimension: mm.

1. Product Change Notice Version Content Data 2.2 1. Modify COM BUF of USB 2. change the header 3. update package information 4. increase Product Identification System 5. Modify mistakes July .2018 2.1 Original Apr. 2018