SH33F2801

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Document overview

• Manufacturer or author: Jason
• PDF pages: 407

Technical content

32-bit High Performance Motor Control MCU Based on ARM® Star 1 V1.0 1. Features  32-bit ARM Star core - With frequency up to 84MHz - DSP and FPU - 32-bit hardware multiply/divide unit - High-speed memory and instruction accelerator - Instruction set compatible with Cortex-M4  Built-in math arithmetic coprocessor (MACP) - Hardware 32-bit CORDIC operator, supporting sine & cosine, arctangent, modulo calculation, Park transform and inverse transform - FOC dedicated SVPWM hardware engine, supporting five-segment and seven-segment  Memories - Up to 128K bytes 128-bit width FLASH memory - Up to 16K bytes of RAM  - Up to 4K bytes of EEPROM - 1K bytes of OTP (one-time programming) memory - Supports full code protection, including two-levels of reading protection, writing protection, erasing protection, customer security code protection, etc.  Clock, reset and power management - 2.4V - 5.5V power supply range, covering 3V/5V typical system - Power-on reset, brownout detection, low-voltage reset - Independent watchdog timer (IWDT) and window watchdog timer (WWDT) - Integrates PLL, up to84MHz clock output - 4M - 12MHz crystal oscillator/ceramic oscillator - Internal high frequency RC oscillator: 8MHz (0.2% accuracy under normal temperature) - Built-in low frequency RC oscillator: 128kHz - Clock Security Monitor (CSM)  1 x independent 12-bit high speed ADCs - Up to 2M SPS sampling rate - 16 channels (with 16 ANx sampling pins) - Configurable sequence conversion with 16 AD conversion result registers for ADC - Support PWM synchronously triggering AD sampling - Single/intermittent/continuous conversion modes, support event-triggered sampling - Internal reference voltage or external input voltage as reference source  Up to 45 fast GPIO ports (GPIOx) - Internal pull-up/pull-down resistors for all I/Os -45 I/Os for TQFP48 and 29 for LQFP32  8 channels external interrupt/event controller (EXTI) - Support edge trigger, level trigger, software trigger - Applicable for generating normal interrupts, wake-up events , and NMI interrupt  1 motor-specific control modules (MCMx) - 6 PWM outputs for each MCM, 16-bit resolution - Support complementary/independent output mode, support symmetric and asymmetric waveform generation - Integrates dead time logic, fault protection, logic exception protection, wave-by-wave current limiting, etc. - Each MCM integrates 4 event comparators, providing

4 AD sampling moments

• Support phase shift function, suitable for single shunt sampling  Two 32-bit PCA0-1 with compare/capture/PWM modules  Two 16-bit basic timers/counters (TIMx) - Capable of cascade-connected as 32-bit timer - Automatically reload counter  1 quadrature encoder interface (QEI) with independent 32-bit timer included  Multiple serial communication interfaces - 3 universal asynchronous receiver transmitter (UARTx) - 1 serial peripheral interfaces (SPI) - 1 two-wire serial interface (TWI), master-slave mode, compatible with I2C  CAN - Comply with CAN 2.0b specification - 15 message buffers, support remote frames, receive filters  Other analog modules on chip - 4 independent high speed operational amplifiers (OPx) - 1 independent high speed comparators (CMPx) - Internal high accuracy reference voltage  CRC calculation unit - supporting 8/16/32-bit polynomial - applicable for code verification, data verification  LVR function (2 thresholds), BOD function (16 thresholds)  96-bit unique ID  Low power modes: sleep mode & stop mode  Supports 2-wire SWD interface  Operating temperature: -40 ~ 105℃  Package: TQFP48, LQFP32

1. OverView SH33F2801 is a high-performance 32-bit microcontroller based on ARM Star core, operating at a frequency of up to 84MHz. Due to the memory instruction acceleration structure using, it can achieve a performance equivalent to about 0 wait state program execution from flash memory at top frequency. The ARM Star core is mature and reliable, has a complete ecosystem and is able to give efficient instructions. SH33F2801 fully exploits the advantages of the ARM Star core and focuses on providing highly integrated, highly reliable monolithic integrated circuits. It is mainly applied to motor control application and other industrial control fields, including various brushless DC motors, permanent magnet synchronous motors, high-performance inverters, high-efficiency DC-AC inverters, etc. On the aspect of calculating, the ARM Star core has built-in DSP, FPU, and a hardware 32-bit multiplier, divider, and shift register. Additionally, SH33F2801 further provides a mathematical operation coprocessing unit (with MACP module), offering hardware CORDIC operation and achieving fast coordinate rotation, sine and cosine, arctangent and modulo calculations, also can achieve direct calculation of Park transform or inverse transform. It can also provide hardware IQ division operation; achieve fast 32-bit Q-format division, and support low-bit zero-padding for 64-bit divide-32-bit operation. Finally, it can provide hardware SVPWM circuit and achieve the generation of hardware-based SVPWM waveform with five-segment and seven-segment. SH33F2801 has an independent motor control PWM modules (MCM), 2 programmable counter arrays (PCA), integrates 4 high-speed operational amplifiers and 1 analog comparators as well as a 12-bit 2M SPS multi-channel high-speed ADCs. It also has built-in temperature sensor circuit and reference voltage generating circuit. SH33F2801 is very suitable for high performance motor control applications, especially for various Brushless DC motor (BLDC) and permanent magnet synchronous motor (PMSM) controls. SH33F2801 provides 8/16/32-bit CRC code & data verification,IWDT, WWDT, low voltage reset circuit, brownout detection circuit, clock security monitor circuit, and can provide code protection mechanism to ensure system reliability and code security based on customer security code.

1. Block Diagram Bus Matrix Flash 128KB SRAM 16KB AHB / APB Bus MCM PCA0/1 TIM7/8 External Interrupt (0~7) UARTs 0/1/2 Clock Generator (RC8M / Crystal / PLL) CAN ADC OPAs 0/1/2/3 CMPs 0/1 SPI TWI GPIOB (16 channel) GPIOA (16 channel) GPIOC (13 channel) IWDT Reset Circuit Power Module PA0~PA15 VDD NRST PB0~PB15 PC0~PC12 Systick WWDT E2Prom 4KB CRC / RAMBIST NVIC MACP (CORDIC / SVPWM) ARM Star 84MHz GND OTP 1KB SW debug port

1. Definition of Pins 32 31 30 29 28 27 26 1 2 3 4 5 6 7 8 9 10 11 SH33F2801 NRST VDD GND PB0/PWMFLT/PCA1ECI/SS/EXTI0 PB1/PWM21 PB2/PWM11 PB3/PWM01 PB4/PWM2 PB5/PWM1 PB6/PWM0 ADTRG/XTAL1/EXTI5/TXD2/CP1OUT/T8/SDA/PA2 T7/CAN_RX/PA3 RXD0/SWDIO/PA7 TXD0/SWCLK/PA8 PCA0FLT/MISO/PA4 PA11/PCA0C/RXD0 BOOT/EXTI2/SC1/SCK/CAN_TX/PCA0B/PA10 ADTRG/PCA1B/MOSI/PA5 EXTI4/SCK/PCA0B/RXD2/PA6 PA12/PCA1A/TXD0 PA13/PCA1B/RXD1/CAN_RX/SDA/EXTI1 EXTI6/CAN_TX/PCA0ECI/SC0/PA1 RXD1/OP3OUT/AN14/PC1 (TQFP48) PCA1C/QEA/OP0P1/AN8/PC9 PCA1A/INDEX/OP0N/AN10/PC11 EXTI7/PCA1FLT/OP0OUT/AN11/CP0OUT/PC12 PA15/PCA1FLT/SC2 PB7/AN0/SC0/QEA PB8/AN1/SC1/QEB PCA1B/QEB/OP0P2/AN9/PC10 XTAL2/RXD2/CP0OUT/T7/SCL/PA0 PB12/CP1N/MOSI/PCA1B PB13/AN5/CP1P0/SCK/PCA0B PC0/OP3N/TXD1 PB15/OP3P/CP1P1/SS PB14/T8/CAN_RX/AN6/VREF PB11/AN4/MISO/CP1OUT OP0P0/AN7/PC8 CP1P2/OP1P/PC7 ADTRG/OP1N/PC6 OP1OUT/AN12/PC5 PCA0A/OP2P/PC4 EXTI3/SS/TXD2/PCA0A/PA9 PB9/AN2/SC2/INDEX PB10/AN3 PCA0B/OP2N/PC3 PCA0C/OP2OUT/AN13/PC2 3536 PA14/PCA1C/TXD1/CAN_TX/SCL/ADTRG

(LQFP32) NRST RXD1/OP3OUT/AN14/PC1 PCA1C/QEA/OP0P1/AN8/PC9 PCA1A/INDEX/OP0N/AN10/PC11 EXTI7/PCA1FLT/OP0OUT/AN11/CP0OUT/PC12 PCA1B/QEB/OP0P2/AN9/PC10 OP0P0/AN7/PC8 PCA0A/OP2P/PC4 PCA0B/OP2N/PC3 PCA0C/OP2OUT/AN13/PC2 VDD GND PB12/CP1N/MOSI/PCA1B PB13/AN5/CP1P0/SCK/PCA0B PC0/OP3N/TXD1 PB15/OP3P/CP1P1/SS PB11/AN4/MISO/CP1OUT PB1/PWM21 PB2/PWM11 PB3/PWM01 PB4/PWM2 PB5/PWM1 PB6/PWM0 EXTI1/SDA/CAN_RX/RXD1/PCA1B/PA13 PA14/ADTRG/SCL/CAN_TX/TXD1/PCA1C RXD0/SWDIO/PA7 TXD0/SWCLK/PA8 PB14/T8/CAN_RX/AN6/VREF BOOT/EXTI2/SC1/SCK/CAN_TX/PCA0B/PA10 ADTRG/XTAL1/EXTI5/TXD2/CP1OUT/T8/SDA/PA2 XTAL2/RXD2/CP0OUT/T7/SCL/PA0 PB0/PWMFLT/PCA1ECI/SS/EXTI0 Except for power, reset, all other pins have alternate functions. The alternate functions are selected and set by the Alternate Function Register (AFRL/AFRH). The SWJ port and XTAL port can also alternate as GPIO ports, which are set in SWJCFG@SYSCFG_SAFR and OSCCFG@SYSCFG_SAFR.

1. Description of Pins

5.1 Function description of Pins

Pin No. Type Description I/O Port PA0 – PA15 I/O 16-bit bidirectional I/O ports PB0 – PB15 I/O 16-bit bidirectional I/O ports PC0 – PC12 I/O 13-bit bidirectional I/O ports programmable counter arrays(PCA0～PCA1) PCA0A I/O PCA0 input/output A PCA0B I/O PCA0 input/output B PCA0C I/O PCA0 input/output C PCA0FLT I PCA0 fault detection input PCA0ECI I PCA0 external clock input PCA1A I/O PCA1 input/output A PCA1B I/O PCA1 input/output B PCA1C I/O PCA1 input/output C PCA1FLT I PCA1 fault detection input PCA1ECI I PCA1 external clock input Quadrature encoder interface (QEA/QEB/INDEX) QEA I Quadrature encoder QEA input QEB I Quadrature encoder QEB input INDEX I Quadrature encoder INDEX input Basic timer(TIM7~8) T7 I/O External clock input/clock compare output T8 I/O External clock input/clock compare output MCM (MCM, three-phase motor control module) PWM0/PWM01 PWM1/PWM11 PWM2/PWM21 O MCM module 16BIT PWM complementary output PWMFLT I MCM module 16BIT PWM fault signal input SC0 I MCM module wave-by-wave current limit compare digital signal 0 input SC1 I MCM module wave-by-wave current limit compare digital signal 1 input SC2 I MCM module wave-by-wave current limit compare digital signal 2 input ADC (ADC, multichannel analog-to-digital converter) AN0~14 I ADC independent input channel (15) VREF I/O External reference voltage input interface ADTRG I/O ADC external sampling trigger signal input

Interrupt, reset, clock and power NRST I CPU will reset when this pin remains at low level for more than 10μs. Because there is internal 30kΩ pull-up resistor, a reset pulse can be generated by connecting only one external 0.1uF capacitor (add 4.7kΩ to 10kΩ resistor for additional pull-up requirement). BOOT I Reserved for using as a boot mode select pin. BOOT=1 means normal booting from flash memory and BOOT=0 means booting from ISP memory. XTAL1 I Resonator input XTAL2 O Resonator output GND P Digital ground VDD P Digital power (2.4 - 5.5V) UART(UART0/1/2, Universal synchronous-asynchronous serial transceiver) RXD0/1/2 I/O UART0/1/2 Serial data input TXD/01/2 O UART0/1/2 Serial data output SPI(Serial Peripheral Interface) MOSI I/O SPI master output slave input MISO I/O SPI master input slave output SCK I/O SPI serial clock SS I SPI slave device select TWI(Two-Wire Serial Interface) SCL I/O TWI clock signal (supporting master/slave mode) SDA I/O TWI clock signal (supporting master/slave mode) CAN(CAN Interface) CAN_RX I/O CAN data input CAN_TX I/O CAN data output Analog comparator on chip (CP0/CP1) CP0P0/ CP0P1/ CP0P2 CP1P0/ CP1P1/ CP1P2 I Comparator 0/1 in-phase input port CP0N/CP1N I Comparator 0/1 inverted input port CP0OUT/CP1OUT O Comparator 0/1 output (digital signal) port Analog operational amplifier on chip (OP0/OP1/OP2/OP3, 4 independent operational amplifiers, only supporting external resister feedback amplifier) OP0P0/OP0P1/OP0P2/ OP1P/OP2P/OP3P I Amplifier 0～3 in-phase input port OP0N / OP1N/OP2N/OP3N I Amplifier 0～3 inverted input port OP0OUT/OP1OUT/OP2 OUT/OP3OUT O Amplifier 0～3 output port

Debug Interface(SWD, Serial wire debug interface) SWDIO I/O SWD data input and output SWCLK I SWD clock input Note: 1. These two ports are presented as debug interfaces by default during system power-on, and they have default pull-up or pull-down properties. For more details, see “GPIO” part. These two debug interfaces can alternate as GPIO ports, but pay attention to the effect of pull-up and pull-down during system power-on. For more details, see “SYSCFG” part.

5.2 Alternate Function Mapping

PORT SYS AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 TQFP48 LQFP32 PA0 XTAL2 OFF GPIO T7 RXD2 SCL CP0OUT Y Y PA1 OFF GPIO SC0 PCA0ECI CAN_TX Y PA2 XTAL1 OFF GPIO ADTRG T8 TXD2 SDA CP1OUT Y Y PA3 OFF GPIO T7 CAN_RX Y PA4 OFF GPIO PCA0FLT MISO Y PA5 OFF GPIO ADTRG PCA1B MOSI Y PA6 OFF GPIO PCA0B RXD2 SCK Y PA7 SWDIO OFF GPIO RXD0 Y Y PA8 SWCLK OFF GPIO TXD0 Y Y PA9 OFF GPIO PCA0A TXD2 SS Y PA10 OFF GPIO SC1 PCA0B SCK CAN_TX Y Y PA11 OFF GPIO PCA0C RXD0 Y PA12 OFF GPIO PCA1A TXD0 Y PA13 OFF GPIO PCA1B RXD1 SDA CAN_RX Y Y PA14 OFF GPIO ADTRG PCA1C TXD1 SCL CAN_TX Y Y PA15 OFF GPIO SC2 PCA1FLT Y PB0 OFF GPIO PWMFLT PCA1ECI SS Y Y PB1 OFF GPIO PWM21 Y Y PB2 OFF GPIO PWM11 Y Y PB3 OFF GPIO PWM01 Y Y PB4 OFF GPIO PWM2 Y Y PB5 OFF GPIO PWM1 Y Y PB6 OFF GPIO PWM0 Y Y PB7 OFF GPIO SC0 QEA AN0 Y PB8 OFF GPIO SC1 QEB AN1 Y PB9 OFF GPIO SC2 INDEX AN2 Y PB10 OFF GPIO AN3 Y PB11 OFF GPIO MISO CP1OUT AN4 Y Y PB12 OFF GPIO PCA1B MOSI CP1N Y Y PB13 OFF GPIO PCA0B SCK AN5/CP1P0 Y Y PB14 OFF GPIO T8 CAN_RX AN6/VREF Y Y PB15 OFF GPIO SS OP3P/CP1P1 Y Y PC0 OFF GPIO TXD1 OP3N Y Y PC1 OFF GPIO RXD1 AN14/OP3OUT Y Y PC2 OFF GPIO PCA0C AN13/OP2OUT Y Y PC3 OFF GPIO PCA0B OP2N Y Y PC4 OFF GPIO PCA0A OP2P Y Y PC5 OFF GPIO AN12/OP1OUT Y PC6 OFF GPIO ADTRG OP1N Y PC7 OFF GPIO OP1P_CP1P2 Y PC8 OFF GPIO AN7/OP0P0/CP 0P0 Y Y PC9 OFF GPIO PCA1C QEA AN8/OP0P1/CP 0P1 Y Y PC10 OFF GPIO PCA1B QEB AN9/OP0P2/CP 0P2 Y Y PC11 OFF GPIO PCA1A INDEX AN10/OP0N/CP 0N Y Y PC12 OFF GPIO PCA1FLT CP0OUT AN11/OP0OUT Y Y

1. Related Documents  The following reference documents and materials are available from Sinowealth or other associated channels. Sinowealth reserves the right to update documentation without notice. Please check Sinowealth website or associated channels regularly for version updates and discrepancies.  Data Sheet: this manual, the most basic and authoritative documentation of the chip;  Flash Programming Manual: introduction to reading, erasing, programming, and protection of flash (with internal EEPROM);  Application Note: introduction for matters need attention, typical peripheral configuration, and general usage introduction of this chip;  StdLib Manual: documentation associated with the peripheral library;  Development Kit: Software and hardware supporting tools involved in the chip development. Including plug-ins for common IDE developing environments (Keil, IAR, etc.), project creation wizard, motor-specific auxiliary tools, hardware development evaluation platform based on this chip, etc.

1. Core

7.1 ARM® Star Core

The ARM Star processor is a high-performance 32-bit processor that is designed for the microcontroller market. The processor offers outstanding performance, fast interrupts handling, and enhanced system debug with extensive breakpoint and trace capabilities. SH33F2801 uses the latest r0p1 version of the ARM® Star.

7.2 Register Group

ARM Star processor has registers R0 to R15.

7.2.1 General Purpose Registers

R0-R12 are all 32-bit general purpose registers for data operation. Note: Some 16-bit Thumb instructions can only access a subset of these registers (low registers, R0 to R7)

7.2.2 Stack Register

Stack pointer (SP) R13: alias of banked registers, SP_process and SP_main. The ARM Star contains stack pointers, R13. They are banked so that only one is visible at a time. Main stack pointer (MSP): The default stack pointer, used by OS kernel and exception handlers. Process Stack Pointer (PSP): The process stack pointer is used in process mode. The lowest two bits of the stack pointer are always 0, which means they are always 4-byte aligned. After the reset is complete, all code uses the main stack. Exception handler (such as SVC) can change the stack used in thread mode by changing the EXC_RETURN value which it uses when exiting. All exceptions continue to use the main stack. Stack pointer R13 is banked register, switching between SP_main and SP_process. Of process stack and main stack, only one is visible at any time, which is indicated by R13. Except for using the value of EXC_RETURN when exiting from handler mode, writing on CONTROL[1] using the MSR instruction can also help switch from main stack to process stack in thread mode. In the field of ARM programming, any event that interrupts the sequential execution of a program is called an exception. Except for external interrupts, the execution of programs may be interrupted when an instruction performs an "illegal operation" or accesses prohibited memory, or fault occurs due to various errors, or a non-maskable interrupt occurs. These conditions above are collectively referred to as exceptions. Exceptions and interrupts can also be mixed in less strict context. In addition, the program code can also actively request to enter the exception state (usually used for system calls).

7.2.3 Link Register

R14 is the subroutine link register. When a subroutine is called, the returned address is stored by R14. Different from other processors’ cores, ARM stores the returned address directly in the register in order to reduce the number of accesses to memories. All level subroutines can be called without accessing memories (stack memories), which improves the efficiency of subroutine calls. If the level is more than 1, pushing R14 value of the previous level onto the stack is required. When programming on ARM, recommend using general-purpose registers to save intermediate results for reducing memory access.

7.2.4 Program Count Register

The program counter (R15) is the current program address. This register can be written to control the program flow. Bit[0] is always 0, so instructions are always aligned to word or half-word boundaries.

7.3 Special-purpose Registers

ARM Star Core also has several special registers on core level, as shown in the following table: Table7-1 ARM Star Core Special Registers and Their Functions Register Function xPSR Provide ALU flags (zero flag, carry flag, negative flag, overflow flag), execution status, and current executing interrupt number PRIMASK Disable all interrupts except the non-maskable interrupt(NMI) and Hard Fault FAULTMASK Disable all interrupts except the NMI BASEPRI Disable all interrupts of specific priority level or lower priority level CONTROL Define privilege status and stack pointer selection

7.3.1 Program Status Registers

The program status registers are subdivided into three status registers. These three registers are: application PSR (APSR), interrupt PSR (IPSR), and execution PSR (EPSR). The three PSRs can be accessed together or separately using the special register access instructions MSR and MRS. When they are accessed as a collective item, the name xPSR is used.

7.3.1.1 Application PSR

Application PSR (APSR) contains condition code flags. The ARM Star processor stores the condition code flags on the stack before entering the exception. You can read the APSR using MRS instruction and can change the APSR using the MSR instruction, but EPSR and IPSR are read-only. b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 N Z C V Q Reserved RW RW RW RW RW - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 N Negative 1: the result is negative 0: the result is positive 30 Z Zero 1: the result is 0 0: the result is not 0 29 C Carry/borrow 1: carry or borrow 0: no carry or borrow 28 V Overflow 1: overflow 0: no overflow

27 Q DSP Overflow and Sticky saturation flag

7.3.1.2 Interrupt PSR

Interrupted PSR (IPSR) contains the ISR number of the currently active exception. b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Reserved Interrupt No. - RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 - 9 Reserved - 8 - 0 ISR NUMBER Preemptive anomaly number 0 = Thread mode. 1 = Reset. 2 = NMI. 3 = HardFault. 4 = MemManage. 5 = BusFault. 6 = UsageFault 7 = SecureFault 8-10 = Reserved. 11 = SVCall. 12 = DebugMonitor. 13 = Reserved. 14 = PendSV. 15 =SysTick 16 = IRQ0 17 = IRQ1 53 = IRQ27 54 = IRQ28

7.3.1.3 Execution PSR

Execution PSR (EPSR) contains two overlapping areas: Interrupt-Continual Instruction (ICI) area is used for loading multiple operations and storing multiple operation instructions Execution status area is used for if-then (IT) instructions and T bit (Thumb status bit) Interrupt-Continual Instruction (ICI) area Multiple-load/store (LDM/STM) is interruptible. The ICI area of the EPSR is used to store the information required to continue performing multiple loading and storing operations at the point of being interrupted. If-Then instruction status area The IT area of EPSR contains the execution status bits of If-Then instructions. EPSR cannot be accessed directly, to modify EPSR, one of the following two events must occur: An interrupt occurs when LDM or STM instructions are executed. The If-Then instructions are executed Note: ICI area and IT area overlap each other, so multiple-load/store operations with If-Then conditions are not interruptible-continual. b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved ICI/T T Reserved - RW RW - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 B5 b4 b3 b2 b1 b0 ICT/IT Reserved RO - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 - 27 Reserved - 15 - 12 ICI Interrupt-Continual Instruction bits. If an interrupt occurs while executing an LDM or STM operation, the LDM or STM operation is suspended. EPSR uses [15:12] bit to store the index of the next register operand in the operation. After the interrupt is responded, the processor returns to the register stored in [15:12] and resumes operation. If the index is not in the register list of the instruction, the processor continues to execute the LDM/STM operation using the next register in the list (if any). 15 - 10:26 - IT If-Then bits. They are the execution status bits of If-Then instruction, containing the number of these instructions and their execution conditions.

24 T The T bit is cleared using an interactive instruction, and the PC bit 0 written

here is zero. It can also be cleared by the exception POP operation (T bit pushed in stack is 0). Executing an instruction when the T bit is 0 causes an INVSTATE exception. 23 - 16 Reserved - 9 - 0 Reserved - Base register update in LDM and STM operations There are cases when an LDM or STM updates the base register: When the instruction specifies base register write-back, the base register changes to the updated address. An abort restores the original base value. When the base register is in the register list of an LDM, and is not the last register in the list, the base register changes to the loaded value. An LDM/STM is restarted rather than continued if: The instruction faults The instruction is inside an IT If an LDM has completed a base load, it is continued from before the base load. Store xPSR bit When entering an exception, the three status registers combined and stored into the stack.

7.3.2 Interrupt Mask Registers

Interrupt Mask Registers (PRIMASK, FAULTMASK, and BASEPRI) are used to disable exceptions. Name Description PRIMASK A 1-bit register. When this is set, it allows NMI and the hard fault exception; all other interrupts and exceptions are masked. The default value is 0, which means that no masking is set. FAULTMASK A 1-bit register. When this is set, it allows only the NMI, and all interrupts and fault handling exceptions are disabled. The default value is 0, which means that no masking is set. BASEPRI A register of up to 9 bits (depending on the bit width implemented for priority level). It defines the masking priority level. When this is set, it disables all interrupts of the same or lower level (larger priority value). Higher-priority interrupts can still be allowed. If this is set to 0, the masking function is disabled (this is the default). To access PRIMASK, FAULTMASK and BASEPRI, MRS/MSR instructions should also be used, such as: MRS R0, BASEPRI ; read BASEPRI to R0 MRS R0, FAULTMASK ; read FAULTMASK to R0 MRS R0, PRIMASK ; read PRIMASK to R0 MSR BASEPRI, R0 ; write R0 to BASEPRI MSR FAULTMASK, R0 ; write R0 to FAULTMASK MSR PRIMASK, R0 ; write R0 to PRIMASK Access to these three registers is allowed only at privilege level. In order to quickly enable or disable interrupts, CM3 also sets a CPS instruction with the following 4 usages: CPSID I ;PRIMASK=1 ; disables interrupt CPSIE I ;PRIMASK=0 ; enables interrupt CPSID F ;FAULTMASK=1 ; disables exception CPSIE F ;FAULTMASK=0 ; enables exception

7.3.3 Control Register

Control Register (CONTROL) is used to define the privilege level and is also used to select which stack pointer is currently used. Name Description of Functions CONTROL[1] Stack pointer selection 0=selects the main stack pointer MSP (default value after reset) 1=selects process stack pointer PSP (Alternate stack is used) If it is in the Thread or base level, the alternate stack is the PSP. There is no alternate stack for handler mode, so this bit must be zero when the processor is in handler mode. (In the core, CONTROL[1] is always 0 in handler mode. In the thread or base level, it can be either 0 or 1. This bit is writable only when the core is in Thread mode and privileged. In the user state or hander mode, writing to this bit is not allowed. Aside from writing to this register, another way to change this bit is to change bit 2 of the LR when in exception return. ) CONTROL[0] 0=Privileged in Thread mode 1=User state in Thread mode If in handler mode (not Thread mode), the processor operates in privileged mode. (The CONTROL[0] bit is writable only in a privileged state. Once it enters the user state, the only way to switch back to privileged is to trigger an interrupt and change this in the exception handler. ) To access the CONTROL register, the MRS and MSR instructions are used: MRS R0, CONTROL MSR CONTROL, R0

7.4 Operation Mode, Operating States and Access Mode

7.4.1 Operation Modes

The ARM Star processor supports two modes of operation, Thread mode and Handler mode: The processor enters Thread mode on Reset, or as a result of an exception return. Privileged and user (Unprivileged) code can run in Thread mode. The processor enters Handler mode as a result of an exception. All code is privileged in Handler mode.

7.4.2 Operating States

The processor can operate in one of two operating states: Thumb state: This is the normal execution running 16-bit and 32-bit halfword aligned Thumb and thumb-2 instructions. Debug state: This is the state when the processor is in halting debug.

7.4.3 Privileged Access and User Access

Code can execute as privileged or unprivileged. Unprivileged execution limits or excludes access to some resources. Privileged execution has access to all resources. Handler mode is always privileged. Thread mode can be privileged or unprivileged. Access is privileged in thread mode after reset, but you can configure it to unprivilege by MSR instruction to clear CONTROL[0]. The following access is prohibited: Some instructions, such as the CPS instruction to set FAULTMASK and PRIMASK Access to most of the registers in the System Control Space (SCS) When changed from privileged to unprivileged in thread mode, it cannot return to privilege itself. Only handler operations can change the access mode of the thread mode. Access is always privileged in handler mode.

7.5 Instruction Set

Mnemonic Operands Brief description Flags ADC, ADCS {Rd,} Rn, Op2 Add with Carry N,Z,C,V ADD, ADDS {Rd,} Rn, Op2 Add N,Z,C,V ADD, ADDW {Rd,} Rn, #imm12 Add - ADR Rd, label Address to Register - AND, ANDS {Rd,} Rn, Op2 Logical AND N,Z,C ASR, ASRS Rd, Rm, <Rs|#n> Arithmetic Shift Right N,Z,C B {cond} label Branch {conditionally} - BFC Rd, #lsb, #width Bit Field Clear - BFI Rd, Rn, #lsb, #width Bit Field Insert - BIC, BICS {Rd,} Rn, Op2 Bit Clear N,Z,C BKPT #imm8 Breakpoint - BL label Branch with Link - BLX Rm Branch indirect with Link and Exchange - BLXNS Rm Branch indirect with Link and Exchange, Non-secure - BX Rm Branch and Exchange - BXNS Rm Branch and Exchange, Non secure - CBNZ Rn, label Compare and Branch on Non Zero - CBZ Rn, label Compare and Branch on Zero - CDP, CDP2 {cond} coproc, #op1, Rt, CRn, CRm{, #op2} Coprocessor Data Processing - CLREX - Clear Exclusive - CLZ Rd, Rm Count Leading Zeros - CMN Rn, Op2 Compare Negative N,Z,C,V CMP Rn, Op2 Compare N,Z,C,V CPSID i Change Processor State, Disable Interrupts - CPSIE i Change Processor State, Enable Interrupts - DMB {opt} Data Memory Barrier - DSB {opt} Data Synchronization Barrier - EOR, EORS {Rd,} Rn, Op2 Exclusive OR N,Z,C FLDMDBX ,FLDMIAX Rn FLDMX (Decrement Before, Increment After) loads - FSTMDBX,FSTMIAX Rn FSTMX (Decrement Before, Increment After) stores - ISB {opt} Instruction Synchronization Barrier - IT - If Then condition block - LDA Rd, [Rn] Load-Acquire Word LDAB Rd, [Rn] Load-Acquire Byte LDAEX Rd, [Rn] Load-Acquire Exclusive Word - LDAEXB Rd, [Rn] Load-Acquire Exclusive Byte - LDAEXH Rd, [Rn] Load-Acquire Exclusive Halfword - LDAH Rd, [Rn] Load-Acquire Halfword - LDM Rn{!}, reglist Load Multiple - LDMDB, LDMEA Rn{!}, reglist Load Multiple Decrement Before - LDMIA, LDMFD Rn{!}, reglist Load Multiple, Increment After - LDR Rt, [Rn, Rm {, LSL #shift}] Load Register Word (register offset) - LDR Rt, label Load Register Word (literal) - LDR, LDRT Rt, [Rn, #offset] Load Register Word (immediate offset, unprivileged) - LDRB Rt, [Rn, Rm {, LSL #shift}] Load Register Byte (register offset) - LDRB Rt, label Load Register Byte (literal) - LDRB, LDRBT Rt, [Rn, #offset] Load Register Byte (immediate offset, unprivileged) - LDRD Rt, Rt2, [Rn, #offset] Load Register Dual (immediate offset) - LDRD Rt, Rt2, label Load Register Dual (PC relative) - LDREX Rt, [Rn, #offset] Load Register Exclusive - LDREXB Rt, [Rn] Load Register Exclusive Byte - LDREXH Rt, [Rn] Load Register Exclusive Halfword -

LDRH Rt, [Rn, Rm {, LSL #shift}] Load Register Halfword (register offset) - LDRH Rt, label Load Register Halfword (literal) - LDRH, LDRHT Rt, [Rn, #offset] Load Register Halfword (immediate offset, unprivileged) - LDRSB Rt, [Rn, Rm {, LSL #shift}] Load Register Signed Byte (register offset) - LDRSB Rt, label Load Register Signed Byte (PC-relative) - LDRSB, LDRSBT Rt, [Rn, #offset] Load Register Signed Byte (immediate offset, unprivileged) - LDRSH Rt, [Rn, Rm {, LSL #shift}] Load Register Signed Halfword (register offset) - LDRSH Rt, label Load Register Signed Halfword (PC-relative) - LDRSH, LDRSHT Rt, [Rn, #offset] Load Register Signed Halfword (immediate offset, unprivileged) - LSL, LSLS Rd, Rm, <Rs|#n> Logical Shift Left N,Z,C LSR, LSRS Rd, Rm, <Rs|#n> Logical Shift Right N,Z,C MCR,MCR2 {cond} coproc, #opc1, Rt, CRn, CRm{, #opc2} Move to Coprocessor from Register - MCRR,MCRR2 {cond} coproc, #opc1, Rt, Rt2, CRm Move to Coprocessor from two Registers - MLA Rd, Rn, Rm, Ra Multiply Accumulate - MLS Rd, Rn, Rm, Ra Multiply and Subtract - MOV, MOVS Rd, Op2 Move N,Z,C MOV, MOVS Rd, Rm Move (register) N,Z MOVT Rd, #imm16 Move Top - MOVW Rd, #imm16 Move 16-bit constant N,Z,C MRC,MRC2 {cond} coproc, #opc1, Rt, CRn, CRm{, #opc2} Move to Register from | Coprocessor - MRRC,MRRC2 {cond} coproc, #opc1, Rt, Rt2, CRm Move to two Registers from Coprocessor. - MRS Rd, spec_reg Move from Special Register to general register - MSR spec_reg, Rn Move from general register to Special Register - MUL, MULS {Rd,} Rn, Rm Multiply N,Z MVN, MVNS Rd, Op2 Bitwise NOT N,Z,C NOP - No Operation - ORN, ORNS {Rd,} Rn, Op2 Logical OR NOT N,Z,C ORR, ORRS {Rd,} Rn, Op2 Logical OR N,Z,C PKHTB, PKHBT {Rd,} Rn, Rm, {, Op2} Pack Halfword - PLD [Rn {, #offset}] Preload Data - POP reglist Pop registers from stack - PUSH reglist Push registers onto stack - QADD {Rd,} Rn, Rm Saturating Add Q QADD16 {Rd,} Rn, Rm Saturating Add 16 - QADD8 {Rd,} Rn, Rm Saturating Add 8 - QASX {Rd,} Rn, Rm Saturating Add and Subtract with Exchange - QDADD {Rd,} Rn, Rm Saturating Double and Add Q QDSUB {Rd,} Rn, Rm Saturating Double and Subtract Q QSAX {Rd,} Rn, Rm Saturating Subtract and Add with Exchange - QSUB {Rd,} Rn, Rm Saturating Subtract Q QSUB16 {Rd,} Rn, Rm Saturating Subtract 16 - QSUB8 {Rd,} Rn, Rm Saturating Subtract 8 - RBIT Rd, Rn Reverse Bits - REV Rd, Rn Reverse byte order in a word - REV16 Rd, Rn Reverse byte order in each halfword - REVSH Rd, Rn Reverse byte order in bottom halfword and sign extend - ROR, RORS Rd, Rm, <Rs|#n> Rotate Right N,Z,C RRX, RRXS Rd, Rm Rotate Right with Extend N,Z,C RSB, RSBS {Rd,} Rn, Op2 Reverse Subtract N,Z,C,V SADD16 {Rd,} Rn, Rm Signed Add 16 GE

SADD8 {Rd,} Rn, Rm Signed Add 8 GE SASX {Rd,} Rn, Rm Signed Add and Subtract with Exchange GE SBC, SBCS {Rd,} Rn, Op2 Subtract with Carry N,Z,C,V SBFX Rd, Rn, #lsb, #width Signed Bit Field Extract - SDIV {Rd,} Rn, Rm Signed Divide - SEL {Rd,} Rn, Rm Select bytes GE SEV - Send Event - SG - Secure Gateway - SHADD16 {Rd,} Rn, Rm Signed Halving Add 16 - SHADD8 {Rd,} Rn, Rm Signed Halving Add 8 - SHASX {Rd,} Rn, Rm Signed Halving Add and Subtract with Exchange - SHSAX {Rd,} Rn, Rm Signed Halving Subtract and Add with Exchange - SHSUB16 {Rd,} Rn, Rm Signed Halving Subtract 16 - SHSUB8 {Rd,} Rn, Rm Signed Halving Subtract 8 - SMLABB, SMLABT, SMLATB, SMLATT Rd, Rn, Rm, Ra Signed Multiply Accumulate halfwords Q SMLAD, SMLADX Rd, Rn, Rm, Ra Signed Multiply Accumulate Dual Q SMLAL RdLo, RdHi, Rn, Rm Signed Multiply Accumulate Long (32 × 32 + 64), 64-bit result - SMLALBB, MLALBT, SMLALTB, SMLALTT RdLo, RdHi, Rn, Rm Signed Multiply Accumulate Long, halfwords - SMLALD, SMLALDX RdLo, RdHi, Rn, Rm Signed Multiply Accumulate Long Dual - SMLAWB, SMLAWT Rd, Rn, Rm, Ra Signed Multiply Accumulate, word by halfword Q SMLSD, SMLSDX Rd, Rn, Rm, Ra Signed Multiply Subtract Dual Q SMLSLD, SMLSLDX RdLo, RdHi, Rn, Rm Signed Multiply Subtract Long Dual - SMMLA, SMMLAR Rd, Rn, Rm, Ra Signed Most Significant Word Multiply Accumulate - SMMLS, SMMLSR Rd, Rn, Rm, Ra Signed Most Significant Word Multiply Subtract - SMMUL, SMMULR Rd, Rn, Rm Signed Most Significant Word Multiply - SMUAD, SMUADX {Rd,} Rn, Rm Signed Dual Multiply Add Q. SMULBB, SMULBT, SMULTB, SMULTT {Rd,} Rn, Rm Signed Multiply (halfwords) - SMULL RdLo, RdHi, Rn, Rm Signed Multiply Long (32 × 32), 64-bit result - SMULWB, SMULWT {Rd,} Rn, Rm Signed Multiply word by halfword - SMUSD, SMUSDX {Rd,} Rn, Rm Signed Dual Multiply Subtract - SSAT Rd, #n, Rm {,shift #s} Signed Saturate Q SSAT16 Rd, #n, Rm Signed Saturate 16 Q SSAX {Rd,} Rn, Rm Signed Subtract and Add with Exchange GE SSUB16 {Rd,} Rn, Rm Signed Subtract 16 GE SSUB8 {Rd,} Rn, Rm Signed Subtract 8 GE STL Rt, [Rn] Store-Release Word - STLB Rt, [Rn] Store-Release Byte - STLEX Rt, Rt [Rn] Store-Release Exclusive Word - STLEXB Rt, Rt [Rn] Store-Release Exclusive Byte - STLEXH Rt, Rt [Rn] Store-Release Exclusive Halfword - STLH Rt, [Rn] Store-Release Halfword - STM Rn{!}, reglist Store Multiple - STMDB, STMEA Rn{!}, reglist Store Multiple Decrement Before - STMIA, STMFD Rn{!}, reglist Store Multiple Increment After - STR Rt, [Rn, Rm {, LSL #shift}] Store Register Word (register offset) - STR, STRT Rt, [Rn, #offset] Store Register Word (immediate offset, unprivileged) - STRB Rt, [Rn, Rm {, LSL #shift}] Store Register Byte (register offset) - STRB, STRBT Rt, [Rn, #offset] Store Register Byte (immediate offset, unprivileged) - STRD Rt, Rt2, [Rn, #offset] Store Register Dual two words - STREX Rd, Rt, [Rn, #offset] Store Register Exclusive - STREXB Rd, Rt, [Rn] Store Register Exclusive Byte - STREXH Rd, Rt, [Rn] Store Register Exclusive Halfword -

STRH Rt, [Rn, Rm {, LSL #shift}] Store Register Halfword (register offset) - STRH, STRHT Rt, [Rn, #offset] Store Register Halfword (immediate offset, unprivileged) - SUB, SUBS {Rd,} Rn, Op2 Subtract N,Z,C,V SUB, SUBW {Rd,} Rn, #imm12 Subtract - SVC #imm Supervisor Call - SXTAB {Rd,} Rn, Rm {,ROR #n} Sign extend 8 bits to 32 and Add - SXTAB16 {Rd,} Rn, Rm {,ROR #n} Sign extend two 8-bit values to 16 and Add - SXTAH {Rd,} Rn, Rm {,ROR #n} Sign extend 16 bits to 32 and Add - SXTB Rd, Rm {,ROR #n} Sign extend 8 bits to 32 - SXTB16 {Rd,} Rm {,ROR #n} Sign extend 8 bits to 16 - SXTH {Rd,} Rm {,ROR #n} Sign extend a Halfword to 32 - TBB [Rn, Rm] Table Branch Byte - TBH [Rn, Rm, LSL #1] Table Branch Halfword - TEQ Rn, Op2 Test Equivalence N,Z,C TST Rn, Op2 Test N,Z,C TT Rd, [Rn] Test Target - TTA Rd, [Rn] Test Target Alternate Domain - TTAT Rd, [Rn] Test Target Alternate Domain Unprivileged - TTT Rd, [Rn] Test Target Unprivileged - UADD16 {Rd,} Rn, Rm Unsigned Add 16 GE UADD8 {Rd,} Rn, Rm Unsigned Add 8 GE UASX {Rd,} Rn, Rm Unsigned Add and Subtract with Exchange GE UBFX Rd, Rn, #lsb, #width Unsigned Bit Field Extract - UDF {c}{q} {#}imm Permanently Undefined. - UDIV {Rd,} Rn, Rm Unsigned Divide - UHADD16 {Rd,} Rn, Rm Unsigned Halving Add 16 - UHADD8 {Rd,} Rn, Rm Unsigned Halving Add 8 - UHASX {Rd,} Rn, Rm Unsigned Halving Add and Subtract with Exchange - UHSAX {Rd,} Rn, Rm Unsigned Halving Subtract and Add with Exchange - UHSUB16 {Rd,} Rn, Rm Unsigned Halving Subtract 16 - UHSUB8 {Rd,} Rn, Rm Unsigned Halving Subtract 8 - UMAAL RdLo, RdHi, Rn, Rm Unsigned Multiply Accumulate Accumulate Long (32 × 32 + 32 + 32), 64-bit result UMLAL RdLo, RdHi, Rn, Rm Unsigned Multiply Accumulate Long (32 × 32 + 64), 64-bit result - UMULL RdLo, RdHi, Rn, Rm Unsigned Multiply Long (32 × 32), 64-bit result - UQADD16 {Rd,} Rn, Rm Unsigned Saturating Add 16 - UQADD8 {Rd,} Rn, Rm Unsigned Saturating Add 8 - UQASX {Rd,} Rn, Rm Unsigned Saturating Add and Subtract with Exchange - UQSAX {Rd,} Rn, Rm Unsigned Saturating Subtract and Add with Exchange - UQSUB16 {Rd,} Rn, Rm Unsigned Saturating Subtract 16 - UQSUB8 {Rd,} Rn, Rm Unsigned Saturating Subtract 8 - USAD8 {Rd,} Rn, Rm Unsigned Sum of Absolute Differences - USADA8 Rd, Rn, Rm, Ra Unsigned Sum of Absolute Differences and Accumulate - USAT Rd, #n, Rm{,shift #s}, Ra Unsigned Saturate Q USAT16 Rd, #n, Rm Unsigned Saturate 16 Q USAX {Rd,} Rn, Rm Unsigned Subtract and Add with Exchange GE USUB16 {Rd,} Rn, Rm Unsigned Subtract 16 GE USUB8 {Rd,} Rn, Rm Unsigned Subtract 8 GE UXTAB {Rd,} Rn, Rm {,ROR #n} Rotate, unsigned extend 8 bits to 32 and Add - UXTAB16 {Rd,} Rn, Rm {,ROR #n} Rotate, unsigned extend two 8-bit values to 16 and Add -

UXTAH {Rd,} Rn, Rm {,ROR #n} Rotate, unsigned extend and Add Halfword - UXTB Rd, Rm {,ROR #n} Unsigned zero-extend Byte - UXTB16 {Rd,} Rm {,ROR #n} Unsigned zero-extend Byte 16 - UXTH Rd, Rm {,ROR #n} Unsigned zero-extend Halfword - VABS .F32 Sd, Sm Floating-point Absolute - VADD .F32 {Sd,} Sn, Sm Floating-point Add - VCMP .F32 Sd, <<Sm| #0.0> Compare two floating-point registers, or one floating point register and zero N,Z,C,V VCMPE .F32 Sd, <<Sm| #0.0> Compare two floating-point registers, or one floating point register and zero with Invalid Operation check N,Z,C,V VCVT .F32.Tm <Sd>, Sm Convert from floating-point to integer - VCVT .Td.F32 Sd, Sd, #fbits Convert from floating-point to fixed point - VCVTA .Tm.F32 <Sd>, Sm Convert from floating-point to integer with directed rounding to nearest with Ties Away - VCVTB VCVTT .F32.F16 Sd, Sm Convert half-precision value to single-precision or double-precision - VCVTB VCVTT .F16.F32 Sd, Sm Convert single-precision or double-precision register to half-precision - VCVTM .Tm.F32 <Sd>, Sm Convert from floating-point to integer with directed rounding towards Minus infinity - VCVTN .Tm.F32 <Sd>, Sm Convert from floating-point to integer with directed rounding to nearest with Ties to even - VCVTP .Tm.F32 <Sd>, Sm Convert from floating-point to integer with directed rounding towards Plus infinity - VCVTR .Tm.F32 <Sd>, Sm Convert between floating point and integer with rounding. - VDIV .F32 {Sd,} Sn, Sm Floating-point Divide - VFMA .F32 {Sd,} Sn, Sm Floating-point Fused Multiply Accumulate - VFMS .F32 {Sd,} Sn, Sm Floating-point Fused Multiply Subtract - VFNMA .F32 {Sd,} Sn, Sm Floating-point Fused Negate Multiply Accumulate - VFNMS .F32 {Sd,} Sn, Sm Floating-point Fused Negate Multiply Subtract - VLDM {mode}{.size} Rn{!}, list Floating-point Load Multiple extension registers - VLDR .F32 Sd, [<Rn> {, #offset}] Floating-point Load an extension register from memory (immediate) - VLDR .F32 Sd, <label> Load an extension register from memory - VLDR .F32 Sd, [PC,#-0] Load an extension register from memory - VLLDM <c> Rn Floating-point Lazy Load multiple - VLSTM <c> Rn Floating-point Lazy Store multiple - VMAXNM .F32 Sd, Sn, Sm Maximum of two floating point numbers with IEEE754-2008 NaN handling - VMINNM .F32 Sd, Sn, Sm Minimum of two floating point numbers with IEEE754-2008 NaN handling - VMLA .F32 Sd, Sn, Sm Floating-point Multiply Accumulate - VMLS .F32 Sd, Sn, Sm Floating-point Multiply Subtract - VMOV <Sn|Rt>, <Rt|Sn> Copy core register to single precision - <Rt|Sm>, <Rt2|Sm1> Copy two core registers to two single-precision - VMOV {.size} Dd[x], Rt Copy core register to scalar - VMOV {.dt} Rt, Dn[x] Copy scalar to core register - VMOV .F32 Sd, #immm Floating-point Move immediate - VMOV .F32 Sd, Sd, Sm Copies the contents of one register to another - <Rt2|Dm> Floating-point Move transfers two words between two core registers and a doubleword register - VMRS Rt, FPSCR Move to core register from floating-point Special Register N,Z,C,V VMSR FPSCR, Rt Move to floating-point Special Register from core register -

VMUL .F32 {Sd,} Sn, Sm Floating-point Multiply - VNEG .F32 Sd, Sm Floating-point Negate - VNMLA .F32 Sd, Sn, Sm Floating-point Multiply Accumulate and Negate - VNMLS .F32 Sd, Sn, Sm Floating-point Multiply, Subtract and Negate - VNMUL .F32 {Sd,} Sn, Sm Floating-point Multiply and Negate - VPOP {.size} list Load multiple consecutive floating-point registers from the stack - VPUSH {.size} list Store multiple consecutive floating-point registers to the stack - VRINTA .F32 Sd, Sm Float to integer in floating point format conversion with directed rounding to Nearest with Ties Away - VRINTM .F32 Sd, Sm Float to integer in floating point format conversion with directed rounding to Minus infinity - VRINTN .F32 Sd, Sm Float to integer in floating point format conversion with directed rounding to Nearest with Ties to even - VRINTP .F32 Sd, Sm Float to integer in floating point format conversion with directed rounding to Plus infinity - VRINTR .F32 Sd, Sm Float to integer in floating point format conversion with rounding towards value specified in FPSCR - VRINTX .F32 Sd, Sm Float to integer in floating point format conversion with rounding specified in FPSCR - VRINTZ .F32 Sd, Sm Float to integer in floating point format conversion with rounding towards Zero - VSEL .F32 Sd, Sn, Sm Select register, alternative to a pair of conditional VMOV - VSQRT .F32 Sd, Sm Calculates floating-point Square Root - VSTM {mode}{.size} Rn{!}, list Floating-point Store Multiple - VSTR .F32 Sd, [Rn{, #offset}] Floating-point Store Register stores an extension register to memory - VSUB F32 {Sd,} Sn, Sm Floating-point Subtract - WFE - Wait For Event - WFI - Wait For Interrupt - YIELD - Suspend task -

1. Memories and Bus Architecture The ARM® Star bus interface is based on the AMBA 5 AHB protocols, and their rules refer to “AMBA 5 AHB Specification”.

8.1 System Architecture

The SH33F2801 main system is interconnected and driven by a multi-layer AHB bus matrix, as shown in the following figure: FLASH SRAM ARM Star GPIO CRC MCM AHB AHB Bus Matrix M0 M1 C-Bus S-Bus S0 S1 S2 S3 MACP SYSCFG AHB-APB TIM7/8 PCA0/1 ADC EXTI QEI APB IWDT/WWDT AHBFLASH Accelerator UART0/1/2 AMOC SPI CAN TWI FIFO0/1/2 Figure8-1 SH33F2801 System Architecture Block Diagram AHB Peripheral Bus The AHB peripheral bus is mounted on the bus matrix, and some peripherals that require high speed and being tightly coupled to the system are mounted on the bus. The AHB/APB bridge is also mounted on this bus. AHB/APB Bridge The AHB-APB bridge provide synchronous connections between the AHB and the APB buses. APB is specialized peripheral buses, with the former having a maximum speed of 42MHz (generally set to one-half of the AHB clock). Before using a peripheral, the corresponding control bits of the clock registers AHBENR/APBENR must be set to turn on that peripheral's clock. See the “Reset and Clock Control (RCC)” part for more details.

8.2 Memory Organization

SH33F2801 follows ARM® Star basic rules for memory organization. The basic organization of the memory is as follows: Table8-1 SH33F2801 Basic Memory Organization Address Range Use Detailed Address Range Description 0x0000 0000 – 0x0FFF FFFF On-chip non-volatile code memory area (Flash) 0x0000 0000 – 0x0001 FFFF 128K flash on the chip On-chip non-volatile system memory (System Block) 0x0FFF 0000 – 0x0FFF 0FFF On-chip EEProm-Like Memory (4K in total) Reserved Area Reserved Area 0x0FFF F800 – 0x0FFF FBFF On-chip OTP area (1K in total) 0x2000 0000 – 0x3FFF FFFF On-chip volatile data storage area(SRAM) 0x2000 0000 – 0x2000 3FFF On-chip 16K SRAM 0x2000 2000 – 0x3FFF FFFF Reserved Area 0x4000 0000 – 0x5FFF FFFF On-chip peripheral area 0x4000 0000 – 0x4001 FFFF On-chip APB peripheral area, with each peripheral allocated 1K byte address space (in the peripheral bit-band area) 0x4002 0000 – 0x4003 FFFF Reserved Area 0x4004 0000 – 0x400F FFFF On-chip AHB peripheral area, with each peripheral allocated 1K byte address space (in the peripheral bit-band area) 0x6000 0000 – 0x9FFF FFFF Reserved Area - Can expand external RAM devices in this area 0xA000 0000 – 0xDFFF FFFF Reserved Area - Can expand external peripheral devices in this area 0xE000 0000 – 0xE00F FFFF ARM Star private peripheral area 0xE000 1000 – 0xE000 1FFF Data observation points and tracking (DWT) 0xE000 2000 – 0xE000 2FFF Flash address overload and breakpoint unit (FPB) 0xE000 3000 – 0xE000 DFFF Reserved Area 0xE000 E000 – 0xE000 EFFF Nested vectored interrupt controller (NVIC) 0xE000 F000 – 0xE004 FFFF Reserved Area

8.2.1 Register Image

Table 8-2 lists the base addresses of all built-in peripherals (not including the ARM Star core device) in SH33F2801. For the register image of each peripheral, see the register address map in the peripheral "Registers" part. Peripheral register address: peripheral base address plus register offset address Table8-2 Basic Addresses of SH33F2801 Built-in Peripherals Base Address Peripherals Bus 0x4000 0000 ~ 0x4000 03FF Reserved APB Bus: 0x4000 0000 - 0x4003 FFFF 0x4000 0400 ~ 0x4000 07FF PCA0 0x4000 0800 ~ 0x4000 0BFF PCA1 0x4000 0C00 ~ 0x4000 0FFF TIM7 0x4000 1000 ~ 0x4000 13FF TIM8 0x4000 1400 ~ 0x4000 17FF QEI 0x4000 1800 ~ 0x4000 1BFF UART0 0x4000 1C00 ~ 0x4000 1FFF UART1 0x4000 2000 ~ 0x4000 23FF UART2 0x4000 2400 ~ 0x4000 27FF SPI 0x4000 2800 ~ 0x4000 2BFF TWI 0x4000 2C00 ~ 0x4000 2FFF CAN 0x4000 3000 ~ 0x4000 33FF IWDT 0x4000 3400 ~ 0x4000 37FF WWDT 0x4000 3800 ~ 0x4000 3BFF AMOC 0x4000 3C00 ~ 0x4000 3FFF ADC 0x4000 4000 ~ 0x4000 43FF EXIT 0x4000 4400 ~ 0x4000 47FF FIFO0 0x4000 4800 ~ 0x4000 4BFF FIFO1 0x4000 4C00 ~ 0x4000 4FFF FIFO2 0x4000 5000 ~ 0x4003 FFFF Reserved 0x4004 0000 ~ 0x4004 01FF GPIO AHB Bus: 0x4004 0000 - 0x4005 FFFF 0x4004 0400 ~ 0x4004 07FF MCM 0x4004 0800 ~ 0x4004 0BFF SYSCFG 0x4004 0C00 ~ 0x4004 0FFF RCC 0x4004 1000 ~ 0x4004 13FF FLASH 0x4004 1400 ~ 0x4004 17FF MACP 0x4004 1800 ~ 0x4004 1BFF CRC 0x4004 1C00 ~ 0x4005 FFFF Reserved

8.2.2 Data Memory (SRAM)

The SH33F2801 has built-in 16K data RAM (SRAM). It can be accessed in bytes, half-words (16 bits) or words (32 bits). The starting address of the SRAM is 0x2000 0000.

8.2.3 Program Memory

The SH33F2801has a built-in flash memory, which is divided into three parts: main memory block, EEPROM-like block and OTP block: -The main memory block is 128K bytes and is divided into 128 1K byte sectors. -EEPROM-like block is 4K bytes, and itcan be operated byprogramming tools and SSP (Self-Sector Programming). -OTP block is 1K bytes and can only be written once. It cannot be changed after writing. For details on the Flash program memory, see the next part "Flash Program Memory".

8.3 Flash Program Memory

8.3.1 Features

 Flash main memory includes 128 sectors of 1KB each, a total of 128KB  Flash EEPROM-like block includes 4 sectors of 1KB each, a total of 4KB  Flash OTP block includes 1 sector of 1KB Flash Program / Erase operation within working voltage range  Flash write operation supports 32-bit & 16-bit write  Flash read protection to prevent illegal access  Flash write protection to prevent accidental operation  Flash customer security code protection, user authentication protection of higher level

8.3.2 Introduction

4KB built-in EEPROM like block is used to store user data, with 1024 bytes per sector. The 1KB OTP block is used to store initialization data. Once the OTP block data is written, it cannot be erased. The structure of the flash memory is shown in the figure below. Main program memory block Flash EEPROM like data block (infomation block) Reserved 128K Reserved 00000000H 0001FFFFH 0FFF0000H Protect block Customer block 0FFFE000H 0FFFE800H OTP block0FFFF800H 0FFFFFFFH Reserved Reserved Reserved 0FFFE3FFH 0FFFEBFFH 0FFFFBFFH Figure8-2 Flash Memory Structure

Table8-3 Table of Flash Memory Structure Block Name Base address Size(bytes) Main memory Sector 0 0x0000 0000 - 0x0000 03FF 1024 Sector 1 0x0000 0400 - 0x0000 07FF 1024 Sector 2 0x0000 0800 - 0x0000 0BFF 1024 Sector 3 0x0000 0C00 - 0x0000 0FFF 1024 Sector 4 0x0000 1000 - 0x0000 13FF 1024 … … … … … … Sector 126 0x0001 F800 - 0x0001 FBFF 1024 Sector 127 0x0001 FC00 - 0x0001 FFFF 1024 Information Block EEPROM Block 0x0FFF 0000 - 0x0FFF 0FFF 4096 Protect Block 0x0FFF E000 - 0x0FFF E3FF 1024 Customer Block 0x0FFF E800 - 0x0FFF EBFF 1024 OTP Block 0x0FFF F800 - 0x0FFF FBFF 1024 Flash memory Operation registers FLASH_ACR 0x4004 1000 - 0x4004 1003 4 FLASH_MKYR 0x4004 1004 - 0x4004 1007 4 FLASH_E2KYR 0x4004 1008 - 0x4004 100B 4 FLASH_SR 0x4004 100C - 0x4004 100F 4 FLASH_CR 0x4004 1010 - 0x4004 1013 4 Reversed 0x4004 1014 - 0x4004 102F 4 FLASH_CNTR 0x4004 1030 - 0x4004 1033 4 FLASH_UPCNTR 0x4004 1034 - 0x4004 1037 4 FLASH_CNTCR 0x4004 1038 - 0x4004 103B 4 Reversed 0x4004 103C - 0x4004 103F 4 FLASH_IKYR 0x4004 1040 - 0x4004 1043 4 Reversed 0x4004 1044 - 0x4004 10FF 188

8.3.3 Flash Memory Function Description

8.3.3.1 Programming and erasing the Flash memory

After the system is reset, the flash memory operation register is locked, so the flash memory operation register needs to be unlocked before performing erasure programming operation on flash. Different flash memory blocks have different unlock registers, and corresponding registers need to be unlocked to execute operations to different blocks. There are two cases for unlocking flash operations. One is to perform a single operation on flash after unlocking, and the other is to perform multiple operations on flash after unlocking. If the flash memory operation register is unlocked, the flash memory blocks can be erased or programmed by controlling the FLASH_CR register. However, in order to prevent the flash from being misoperated, when accessing the flash memory control register, the count value of the Flash operation timer must be guaranteed within a valid range. Otherwise, operations on flash memory blocks will be prohibited. The main Flash memory can be programmed 16 bits or 32bits at a time. After the main memory block is erased, every 16 bits or 32 bits can only be programmed once, which means if each bit of the programmed 16-bit or 32-bit data is not 0, it cannot be programmed again, otherwise the corresponding error flag is set to 1. Whole-chip erase and sector erase of the main memory block, programming of the main memory block, sector erase and programming of the EEPROM-like memory block, sector erase and program of the client information block, programming of the OTP block, they all can be achieved by running the program in RAM or directly accessing the flash operation register in debug mode. The main program block in flash can be prevented from being illegally read by setting read protection. Similarly, write protection can be set for each sector of the flash memory block to prevent from being accidentally changed under the circumstance of program fleet. For a 128KB flash memory block, the basic unit of write protection is 4 sectors as a protection unit.

8.3.3.2 Flash Control Register Unlock

After the system is reset, the flash memory operation register is locked, so the flash memory operation register needs to be unlocked before performing erasure programming operation on flash. Different flash memory blocks have different unlock registers, and corresponding registers need to be unlocked to execute operations to different blocks. To unlock flash, two unlocking values are required to be written to the corresponding unlock register. Whenever writing error occurs on the first or the second key value, the corresponding flash block cannot be unlocked, and a bus error will be generated. Unlocking the unlock register when any one block is unlocked will also generate a bus error. There are also two cases on flash unlocking operations. One is to perform a single operation on flash after unlocking, while the other to perform multiple operations on flash after unlocking. If the flash memory operation register is in unlock state, the flash memory block can be erased and programmed by controlling FLASH_CR. After reset, bit MNLCK@FLASH_CR is set to 1. The FLASH_CR can be unlocked by first writing the flash unlock value 0x8ACE 0246 to the FLASH_MKYR register, then writing the single operation unlock value 0xC3C3 C3C3 or the multiple operation unlock value 0xB4B4 B4B4 to the FLASH_MKYR register. After two correct unlock values writing operations are completed, bit MNLCK@FLASH_CR is cleared by hardware. The software can set the control bit MNLCK@FLASH_CR to 1 to lock the main program block. Main program block is locked by the FLASH_MKYR register. After unlocking, the main program block can be operated by running a program in RAM, running a program in the main program block, running a program in boot block, or directly accessing the flash operation register using a debugging tool. EEPROM-like block of the special information block can be locked by the FLASH_E2KYR register. The unlocking process also contains two write operations. After flash unlock value 0x9BDF 1357 is written to FLASH_E2KYR register, and single operation unlock value 0xC3C3 C3C3 or multiple operation unlock value 0xB4B4 B4B4 is written to FLASH_E2KYR register, this block can be unlocked and the control bit E2LCK@FLASH_CR is cleared by hardware. The software can set the control bit E2LCK@FLASH_CR to 1 to lock the EEPROM-like block of the special information block. It is the EEPROM-like block of the special information block which is locked by FLASH_E2KYR register. After this block is unlocked, operations can be performed by running a program in RAM, running a program in the main program block, running a program in boot block, or directly accessing the flash operation register using a debugging tool. OTP block of the special information block can be locked by the FLASH_IKYR register. The unlocking process also contains two write operations. After flash unlock value 0xABCD 5678 is written to FLASH_IKYR register, and single operation unlock value 0xC3C3 C3C3 or multiple operation unlock value 0xB4B4 B4B4 is written to FLASH_IKYR register, this block can be unlocked and the control bit INFLCK@FLASH_CR is cleared by hardware. The software can set the control bit INFLCK@FLASH_CR to 1 to lock the OTP block of the special information block. It is the OTP block of the special information block which is locked by FLASH_IKYR register. OTP block can be operated by running a program in RAM or a program in the main program block. For flash single unlock operation, after MNLCK@FLASH_CR or E2WRE/INFLCK@FLASH_CR is cleared to 0, only one programming or erasing operation on flash is allowed. After the operation is completed, MNLCK@FLASH_CR or E2WRE/INFLCK@FLASH_CR is automatically set to 1 by hardware, locking the related flash block again. For flash multiple unlock operation, after MNLCK@FLASH_CR or E2WRE/INFLCK@FLASH_CR is cleared to 0, only one programming or erasing operation on flash is allowed. After the operation is completed, MNLCK@FLASH_CR or E2WRE/INFLCK@FLASH_CR must be set to 1 by software, and then the related flash block can be locked again. Table8-4 Unlock Value and Description of Each Unlocking Register Register Function Flash Initial Unlock Value Flash Single Operation Unlock Value Flash Multiple Operation Unlock/Lock Value

Description

FLASH_M KYR Unlock main program block 0x8ACE 0246 0xC3C3 C3C3 0xB4B4 B4B4 Directly access by running a program in RAM or a program in main program block FLASH_E 2KYR Unlock EEPROM-like block of special information block 0x9BDF 1357 0xC3C3 C3C3 0xB4B4 B4B4 Directly access by running a program in RAM or a program in main program block FLASH_I KYR Unlock OTP block of special information block 0xABCD 5678 0xC3C3 C3C3 0xB4B4 B4B4 Directly access by running a program in RAM or a program in main program block

8.3.3.3 Flash Operation Timer Function

The flash control module has an operation timer. The count value of the flash operation timer uses the system clock as its clock source. The count value of the flash operation timer must be less than the upper limit of the flash operation timer, and is greater than zero, then operations can be performed on flash memory, or a 32-bit/16-bit data can be written to target address. If a flash operation is initiated, which means when STRT@FLASH_CR bit is set to 1 or write operation to flash is initiated, the flash operation timer count value is not in the valid time window, then the flash operation cannot be performed and PGWERR@FLASH_SR bit is set to 1. For detailed usage of flash operation timer, see the figure below: Is the FLASH_CNT within the valid range of the time window? (Perform by hardware) BSY@FLASH_SR =0？ Yes No Set the FLASH_CNT window counter, set the FLASH_UPCNT counter upper CNTEN@CNTCR = 1 Start FLASH erase/program operation setting STRT@FLASH_CR = 1 Or the data is written to the desired address Yes End No OPERR@FLASH_SR = 1 （Perform by hardware） Perform flash erase/program sub- operation (Perform by hardware ) Figure8-3 Flash Operation Timer Flowchart

8.3.3.4 Main Program Block Mass Erase

The flash operation provides a full-chip erase function that erases the contents of the main memory block block. Detailed steps are as follows: (1) Unlock Flash main block by writing the correct sequence of keys into FLASH_KEYR, and check that MNLCK@FLASH_CR is cleared. (2) Check that no Flash memory operation is ongoing by checking the BSY bit in the FLASH_SR register. (3) When the BSY@FLASH_SR bit is cleared, write the flash main block mass erase command word to the FLASH_CR register. (4) Set STRT@FLASH_CR bit to start the operation. (5) Wait for the BSY@FLASH_SR bit to be cleared. (6) The operation is done when BSY@FLASH_SR bit is 0. EOP@FLASH_SR is set that indicates the operation has been completed. All flash data is reset to 0x0000 0000 after being erased. The flowchart is as follows: Figure8-4 Main Program Block Total Erasure

8.3.3.5 Main Program Block Sector Erasure

Each sector of the flash memory can be erased independently without affecting other sector contents. The steps to erase the sector by the flash operation are as follows: (a) Erase a sector separately (1) Unlock Flash main block by writing the correct sequence of keys into FLASH_KEYR, and check that MNLCK@FLASH_CR is cleared. (2) Check that no Flash memory operation is ongoing by checking the BSY bit in the FLASH_SR register. (3) When the BSY@FLASH_SR bit is cleared, write the flash main block sector erase command word (MSE) to the FLASH_CR register. (4) Set STRT@FLASH_CR bit to start the operation. (5) Wait for the BSY@FLASH_SR bit to be cleared. (6) The operation is done when BSY@FLASH_SR bit is 0. The flowchart is as follows: Figure8-5 Main Program Block Sector Erase (Single Sector)

(b) Erase multiple sectors (1) Unlock Flash main block by writing the correct sequence of keys into FLASH_KEYR, and check that MNLCK@FLASH_CR is cleared. (2) Check that no Flash memory operation is ongoing by checking the BSY bit in the FLASH_SR register. (3) When the BSY@FLASH_SR bit is cleared, write the flash main block sector erase command word (MSE) and sector number to the FLASH_CR register. (4) Set STRT@FLASH_CR bit to start the operation. (5) Wait for the BSY@FLASH_SR bit to be cleared. (6) Repeat steps 3 to 5 to erase other sectors. (7) Set MNLCK@FLASH_CR bit to 1 to lock the block. The flowchart is as follows: Figure8-6 Main Program Block Sector Erasure (Multiple Sector) When target erasure sector is used to fetch instructions or access data, the corresponding erasure operation is invalid, but the flash operation will not provide any notification, so it is necessary to ensure that the target erasure sector address is correct. EOP@FLASH_SR bit indicates the end of the operation.

8.3.3.6 Main Program Block Programming

The Flash operation provides a 32-bit word/16-bit half-word programming function to modify the contents of the flash main memory block. To program on main flash program block, 32 bits/16 bits can be written each time. The addresses must be aligned by 32 bits/16 bits. If they are not aligned, the corresponding operation is invalid and the relevant error flag is set to 1. When the FLASH_CR register operation instruction word is set to main program block programming, writing a word or half word at a flash address will initiate a programming. During the programming process (bit BSY@FLASH_SR bit is '1'), any operation that reads or writes to flash will cause CPU to pause until the end of this flash programming. The following steps show the procedure of word programming operation register. (a) Single word or half-word programming (1) Unlock Flash main block by writing the correct sequence of keys into FLASH_KEYR, and check that MNLCK@FLASH_CR is cleared. (2) Check that no Flash memory operation is ongoing by checking the BSY bit in the FLASH_SR register. (3) When the BSY@FLASH_SR bit is cleared, write the flash main program block command (MPG) word and program operation width selection bit to the FLASH_CR register. (4) Set STRT@FLASH_CR bit. (5) Write a 32-bit word/16-bit half-word into the desired address. (6) Check BSY@FLASH_SR bit to determine whether the programming instruction has been executed. (7) The operation is done when BSY@FLASH_SR bit is cleared. The operation flowchart is as follows: Figure8-7 Main Program Block Programming (Single Word or Half-word)

(b) Page Programming (1) Unlock Flash main block by writing the correct sequence of keys into FLASH_KEYR, and check that MNLCK@FLASH_CR is cleared. (2) Check that no Flash memory operation is ongoing by checking the BSY bit in the FLASH_SR register. (3) When the BSY@FLASH_SR bit is cleared, write the flash main program block command (MPG) word and program operation width selection bit to the FLASH_CR register. (4) Set STRT@FLASH_CR bit. (5) Write a 32-bit word/16-bit half-word into the desired address. (6) Check BSY@FLASH_SR bit to determine whether the programming instruction has been executed. (7) Repeat steps 3 to 6 until the operations are done. (8) The operation is done when BSY@FLASH_SR bit is cleared. (9) Set MNLCK@FLASH_CR bit to 1 to lock the block. Figure8-8 Main Program Block Programming (Continuous multi-word)

For the Flash main block, can only be programmed once, Each 16-bit or 32-bit data can be programmed when the value of the address is 0x00. Otherwise the operation is aborted and the programming error flag PGERR@FLASH_SR bit is set. If the sector of the main flash program block has been protected by the write protection bit, when the sector is operated, the operation is aborted and the write protection error flag WRPRTERR @FLASH_SR bit is set.

8.3.3.7 EEPROM-like Memory Block Erasure Programming

EEPROM-like memory block erasure programming is similar to main program block sector erasure and programming. The difference lies in flash unlock registers. The operation instruction words written to FLASH_CR register are different, and the flag bits of the lock memory block are different.

8.3.3.8 OTP Block Programming

OTP block can only be programmed once, and it cannot be erased after programming. The programming of the OTP block is similar to the programming of the main program block. The difference lies in flash unlock registers. The operation instruction words written to FLASH_CR register are different, and the flag bits of the lock memory block are different.

8.3.3.9 Main Memory Block Protection

The main Flash memory can be protected against different types of unwanted access(read/write/erase). There are two types of protection: (1) Read Protection Read protection is effective immediately after writing. Read protection has three levels of protection: no read protection, low-level read protection, and high-level read protection. No read protection: When the read protection byte is set to 0xA55A, read protection is not performed, and the read, write, and erase operations on flash are not limited. Low-level limit protection: When the read protection byte is set to a value other than 0xA55A and 0xC33C, the low-level read protection becomes effective, and the read protection byte read at this time is 0xAAAA. In low-level read protection status, the operation of indirectly accessing the flash main memory in debug mode is also prohibited. When low-level read protection is active, the user code is only allowed to read the flash main program memory in non-debug mode. In read protection status, the code executed in the flash main memory can program the flash to achieve functions such as IAP or data storage. Under low-level protection, code can be loaded into the built-in RAM in debug mode (SWD) and code instructions can be excuted to remove low-level read protection (full-chip erase), or Sinowealth tool (SWD) can also be used to perfrom mass erase to relieve low-level read protection. High-level read protection: High-level read protection is active when the read protection byte is set to 0xC33C. Under high-level read protection, the debug function (SWD) is turned off. (2) Write Protection The write protection bit is used to protect against unwanted write operations.. Setting WRP[31:0] bits of the write protection bytes can enable the protection for corresponding sector. SH33F2801 provides protection in units of 4 sectors. If an erase/program operation to a write-protected part of the Flash memory is attempted (sector protected by write protection bit), the write protection error flag (WRPRTERR) is set in the FLASH_SR register. The following table shows the mapping of write protection bits to corresponding protected sectors. Table8-5 Write Protection Mapping Table WP bit Protected Sector WP[0] Sector0 ~ Sector3 WP[1] Sector4 ~ Sector7 WP[2] Sector8 ~ Sector11 - - - - - - WP[30] Sector120 ~ Sector123 WP[31] Sector124 ~ Sector127

(3) Customer Security Code SH33F2801 supports the customer security code setting function. The customer can set a custom security code to lock the read, write and erase operation of the programming simulation tool on the chip. The customer security code is 6 bytes long and the customer can set any non-all zero security code. After the chip is produced, the defaut custromer security code is all zeros. When effective security code set is programmed into the chip and is powered again, this chip must be read, written and erased via tools under the condition that security code is correctly input. The customer security code can be set using the 32-bit product mass programming tool (ProWriter-32) and the simulation tool (SinoLink). Once the setting is completed, the security code must be matched for further operation.

8.4 Flash Access Acceleration Control

SH33F2801 adds a flash access acceleration control module to resolve the contradiction between high system main frequency and slow flash memory access. The high-speed read-ahead buffer block allows instructions and data to be loaded into the buffer in advance, thereby reducing or eliminating the effects of mismatch between flash memory and system frequency. For SH33F2801, when the system is running at 84MHz main frequency, it is required to set the flash memory wait period to 2 (Flash LATENCY = 2), and enable the prefetch buffer block, instruction buffer block, and data buffer block for optimal execution performance similar to zero wait of flash memory.

8.5 Flash Block Division Function

In order to ensure that the backup program on the chip and the main program can be quickly switched, SH33F2801 is equipped with the flash block division function. Refer to "27. User code options" for code options related to flash block division. Among them: FLASH_BACKUP is the enable bit of flash block division, which is used to control whether the flash block division function is enabled; FLASH_SELECT is the switch control bit of mapping flash logical address, which is only valid when FLASH_BACKUP is 1; In the bootloader and main programs, "erase" and "erase - program" operations are allowed for FLASH_BACKUP and FLASH_ SELECT. At this time, the lock register of flash module needs to be written "0x5aa5" to unlock before modification. The specific operation mode is the same as the "customer information area" programming/erasing mode. After modifying FLASH_SELECT, vector reset can be generated by software reset (SW reset) or power on reset, so that the logical address mapping corresponding to PC pointer can be switched. After power on reset or other system reset, according to the values of FLASH_BACKUP and FLASH_SELECT, the hardware will automatically map the flash logical address to corresponding address.

Main Memory (64KB) FLASH Backup Memory (64KB) (Illegal Address, Bus Fault) 0000 0000H

0000 FFFFH

0001 FFFFH

FLASH_BACKUP = 1 FLASH_SELECT = 0 OP_ROM [1:0] = 00 Main Memory (64KB) (Illegal Address, Bus Fault) FLASH Backup Memory (64KB) 0000 0000H FLASH_BACKUP = 1 FLASH_SELECT = 1 OP_ROM [1:0] = 00 Figure8-9 Address configuration block diagram after 128/64KB flash block division (1) When FLASH_SELECT is 0, the logical address of flash area is consistent with the physical address. And after the system is reset, the content of PC pointer is that: point to the logical address 0000 0000H, physical address 0000 0000H; (2) When FLASH_SELECT is 1, the logical address of the main memory block will swap with backup memory block in flash area. At this time: A. Main memory block logical address = physical address + 0001 0000H; B. Backup Memory block logical address = physical address - 0001 0000H; And after the system is reset, the content of PC pointer is that: point to the logical address 0000 0000H, physical address 0001 0000H. When FLASH_SELECT is 0, the PC pointer points to the main memory block. When the PC pointer exceeds the logical address range of the main memory block (0000 0000H~0000 FFFFH), it is considered that the program flies and bus fault is generated. When FLASH_ SELECT is 1, the logical address of the main memory block will swap with backup memory block in flash area. The PC pointer points to the backup memory block. When the PC pointer exceeds the logical address range of the backup memory block (0000 0000H~0000 FFFFH), it is considered that the program flies and bus fault is generated. In a word, when the flash block division function is turned on, the corresponding block can be selected as the area accessed by PC pointer through FLASH_SELECT. If the PC pointer is beyond the range of the selected block, it is considered that the program flies and bus fault is generated. However, it should be noted that the non selected flash block can still be read/written as ROM at this time, but the program is not allowed to run.

8.6 Register

FLASH Module Register List (Base Address: 0x4004 5000) Address Register Name Description 0x4004 1000 ACR Flash access control register 0x4004 1004 MKYR Flash main program memory block unlock control trigger 0x4004 1008 E2KYR EEPROM-like memory block unlock control trigger 0x4004 100C SR Flash status and clear register 0x4004 1010 CR Flash control register 0x4004 101C OPR Flash Option Register 0x4004 1020 RPR Flash read protection register 0x4004 1024 WRPR Flash write protection register 0x4004 1030 CNTR Flash operation timer count register 0x4004 1034 UPCNTR Flash operation timer upper limit 0x4004 1038 CNTCR Flash operation timer start register 0x4004 1040 IKYR Flash special information strorage block unlock control register 0x4004 1100 MEMRMP Memory mapping selection register

8.6.1 Flash Acess Control Register (FLASH_ACR)

Offset Address: 0x0000 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 LOCK[15:0] WO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Reserved CRST DCEN Reserv ed PRFTE N Reserved LATENCY[2:0] - RW RW - RW - RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Symbol Description 31 ~ 16 LOCK[15:0] Register lock bits 0x5AA5: Unlock this register Other: Lock this register When configuring this register, 0x5AA5 must be input to the unlock bits at the same time. After the operation is completed, it will be automatically locked. Reading this LOCK bits will firmly get 0x0000. 15 ~ 12 Reserved -

11 CRST Reset buffer block

0: no reset buffer 1: reset buffer (data buffer and instruction butter block are reset at the same time)

10 DCEN Data buffer enabling

0: Data buffer block is disable 1: Data buffer block is enable

9 Reserved -

8 PRFTEN Prefetch buffer enabling

0: Prefetch buffer block is disable 1: Prefetch buffer block is enable 7 ~ 3 Reserved - 2 ~ 0 LATENCY[2:0] SYSCLK (system clock) cycle and flash access time configuration settings 000: 0 waiting status 001: 1 waiting status 010: 2 waiting status 011: 3 waiting status 100: 4 waiting status 101: 5 waiting status 110: 6 waiting status 111: 7 waiting status

8.6.2 Flash Main Program Memory Block Unlock Control Register (FLASH_MKYR)

Offset Address: 0x0004 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 MKY[31:0] WO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 MKY[31:0] WO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Symbol Description 31 ~ 0 MKY[31:0] Flash main program memory block unlock control bit Write the correct flash unlock value and operation unlock value sequentially to MKY[31:0] to unlock the operation of the main flash program storage block. After the unlock is successfully done, the MNLCK@FLASH_CR bit is cleared by hardware, and MKY[31:0] hardware is cleared. For flash single unlock operation, when MNLCK@FLASH_CR bit is cleared, only one programming or erasure operation to flash is allowed. After the operation is done, MNLCK@FLASH_CR bit is automatically set to 1, and main flash program storage block is locked again. For flash multiple unlock operation, when MNLCK@FLASH_CR bit is cleared, multiple programming or erasure operations are allowed. But after the operation is done, MNLCK@FLASH_CR bit can be automatically set to 1 by software, thus main flash program storage block can be locked again. These bits can only be written by software.

8.6.3 EEPROM-like Memory Block Unlock Control Register (FLASH_E2KYR)

Offset Address: 0x0008 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 E2KY[31:0] WO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 E2KY[31:0] WO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Symbol Description 31 ~ 0 E2KY[31:0] EEPROM-like storage block unlock control byte Write the correct flash unlock value and operation unlock value sequentially to E2KY [31:0] can unlock EEPROM-like block. After the unlock operation is successfully done, the E2WRE@FLASH_CR bit is set to 1 by hardware, and E2KY [31:0] hardware is cleared. For flash single unlock operation, when the unlock operation is successfully done, only one programming or erase operation is allowed. After the operation is done, E2WRE@FLASH_CR bit is automatically set to 1 by hardware, and related flash blocks are locked again. For flash multiple unlock operation, when the unlock operation is successfully done, multiple programming or erasure operations are allowed. But after the operation is done, E2WRE@FLASH_CR bit must be set to 1 by software, thus related flash blocks can be locked again. These bits can only be written by software.

8.6.4 Flash Status and Clear Register (FLASH_SR)

Offset Address: 0x000C Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved STAER RC PGWE RRC PGPE RRC WRPR TERR C FLSER RC Reserv ed OPER RC EOPC - WO WO WO WO WO - WO WO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 BSY Reserved STAER R PGWE RR PGPE RR WRPR TERR FLSER R Reserv ed OPER R EOP RO - RO RO RO RO RO - RO RO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Symbol Description 31 ~ 24 Reserved -

23 STAERRC Flash status error flag clear bit

0: invalid 1: clear

22 PGWERRC Programming window error flag clear bit

0: invalid 1: clear

21 PGPERRC Programming error flag clear bit

0: invalid 1: clear

20 WRPRTERRC Write protection error flag clear bit

0: invalid 1: clear

19 FLSERRC Flash hardware error status clear bit

0: invalid 1: clear

18 Reserved -

17 OPERRC Flash operation error flag clear bit

0: invalid 1: clear

16 EOPC Operation execution flag clear bit

0: invalid 1: clear

15 BSY Busy flag bit

This bit indicates that a flash operation is in progress. This bit is set at the beginning of the flash operation, and it is cleared at the end of the operation or when an error occurs. 14 ~ 8 Reserved -

7 STAERR Flash status error flag bit

Set by hardware, in the case where flash is not properly unlocked, when attempting to erase or program on flash. Set by hardware, in the case where STRT@FLASH_CR is not set to '1', when attempting to program on flash Cleared by writing ‘1’ to STAERRC@FLASH_SR.

6 PGWERR Programming window error flag bit

Set by hardware indicates that when a flash operation is initiated, which means when STRT@FLASH_CR bit is set to ‘1’ or write operation on flash is initiated, thecount value of flash operation timer is not in the valid time window, and the flash operation is not executed. This bit can be cleared by writing ‘1’ to PGWERRC@FLASH_SR.

5 PGPERR Programming error flag bit

Set by hardware if attempt to program on an address that has been programmed (a certain bit is no longer 0) This bit can be cleared by writing ‘1’ to PGPERRC@FLASH_SR.

4 WRPRTERR Write protection error flag bit

Attempt to program or erase the flash address that is write protected and the bit is set to ’1'. This bit can be cleared by writing ‘1’ to WRPRTERRC@FLASH_SR.

3 FLSERR Flash hardware error flag bit

Flash operation over time, and this error flag is set to '1'. This bit status can be cleared by writing ‘1’ to FLSERRC@FLASH_SR.

2 Reserved -

1 OPERR Flash operation error flag bit

Set by hardware if Flash operation failed. This bit can be cleared by writing ‘1’ to OPERRC@FLASH_SR. See PGWERR、PGPERR、WRPRTERR、STAERR error flag bits for detailed information.

0 EOP End of Operation

When flash has finished executing programming/earse operation, the hardware is set to ’1’. This bit can be cleared by writing ‘1’ to EOPC@FLASH_SR. Note: Every programming or erase operation is executed, EOP@FLASH_SR status will be set.

8.6.5 Flash Control Register (FLASH_CR)

Offset Address: 0x0010 Reset Value: 0x0000 D000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 CMD[15:0] RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 MNLC K E2LCK Reserv ed INFLC K PSIZE Reserved STRT Reserv ed SNB[6:0] RW1s RW1s - RW1s RW - RW - RW 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 Bit Symbol Description 31 ~ 16 CMD[15:0] Flash operation command word 0xE619: main block sector erase (MSE) 0x6E91: main block programming (MPG) 0xB44B: E2Prom block programming (IPG) 0x4BB4: E2Prom block sector erase (E2Prom-like) (E2SE) 0xF00F: OTP block programming (OPG) Other: reserved value

15 MNLCK Main program block lock flag

After writing the correct flash unlock value and operation unlock value sequentially to FLASH_MKYR, this bit is cleared by hardware. Only when this time erasure or programming operation can be executed on main flash storage block. This bit can only be cleared by hardware and set to ‘1’ by software.

14 E2LCK EEPROM-like storage block lock flag

After writing the correct flash unlock value and operation unlock value sequentially to FLASH_E2KYR, this bit is cleared by hardware. Then erase or program operation is allowed to be executed on EEPROM-like storage block. This bit can only be cleared by hardware and set to ‘1’ by software.

13 Reserved -

12 INFLCK Special information block lock flag(OTP block)

After the flash unlock value and the multiple operation unlock value are sequentially written into FLASH_IKYR, this bit is celared by hardware. At this time, special information block OTP block is allowed to be erased or programmed. This bit can only be cleared by hardware and set to ‘1’ by software.

11 PSIZE Program operation bit width selection

0: 32-bit simultaneously programmed 1: 16-bit simultaneously programmed 10 ~ 9 Reserved -

8 STRT Starting flag bit

An operation will be triggered when this bit is '1'. This bit can only be set to '1' by software and cleared to '0' when BSY@FLASH_SR becomes '1'.

7 Reserved -

6 ~ 0 SNB[6:0] Sector erase selection These bits select the sector to erase. 0000000: Sector 0 0000001: Sector 1 0000010: Sector 2 …….. 1111110: Sector 126 1111111: Sector 127 Note: This bit is effective only when the CMD[15:0] is MSE or E2SE. When the main program block is erased by sector, each sector size is 1024 bytes. When the EEPROM-like block is erased by sector, each sector size is 1024 bytes.

8.6.6 Flash Option Register (FLASH_OPR)

Offset Address: 0x001C Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 OPT3[7:0] OPT2[7:0] RO RO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 OPT1[7:0] OPT0[7:0] RO RO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Symbol Description 31 ~ 24 OPT3[7:0] Customer Option 3 23 ~ 16 OPT2[7:0] Customer Option 2 15 ~ 8 OPT1[7:0] Customer Option 1 7 ~ 0 OPT0[7:0] Customer Option 0

8.6.7 Flash Read Protection Reigster (FLASH_RPR)

Offset Address: 0x0020 Reset Value: 0x0000 XXXX b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 RDP[15:0] RO X X X X X X X X X X X X X X X X Bit Symbol Description 31 ~ 16 Reserved - 15 ~ 0 RDP[15:0] Read Protection This register contains the read protection option bytes loaded from the Flash information block loader after reset.

8.6.8 Flash Write Protection Register (FLASH_WRPR)

Offset Address: 0x0024 Reset Value: 0xXXXX XXXX b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 WRP[31:0] RO X X X X X X X X X X X X X X X X b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 WRP[31:0] RO X X X X X X X X X X X X X X X X Bit Symbol Description 31 ~ 0 WRP[31:0] Write Protection This register contains the write protection option bytes loaded from the Flash information block loader after reset. 0: write protection invalid 1: write protection valid Note: these bits are read-only.

8.6.9 Flash Operation Timer Count Register (FLASH_CNTR)

Offset Address: 0x0030 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 CNT[31:0] RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 CNT[31:0] RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

31 ~ 0 CNT[31:0] Flash operation timer count value register Flash operation timer based on system clock, it enables or disables countdown function according to CNTEN@CNTCR bit. Only when the count value is counted down to the upper limit of the flash operation timer, the flash memory is allowed to operate. When the flash operation timer count value is counted down to zero, the operation of the flash memory is prohibited.

8.6.10 Flash Operation Timer Upper Limit Register (FLASH_UPCNTR)

Offset Address: 0x0034 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 UPCNT[31:0] RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 UPCNT[31:0] RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Symbol Description 31 ~ 0 UPCNT[31:0] Flash operation timer upper limit Only when the count value of flash operation timer is counted down to the upper limit of the flash operation timer or the initial set value is lower than the upper limit of the flash operation timer, the flash memory is allowed to operate. When the flash operation timer count value is counted down to zero, the operation of the flash memory is prohibited. Note: When UPCNT=0 and CNT=0, the operation of the flash memory is prohibited.

8.6.11 Flash Operation Timer Start Register (FLASH_CNTCR)

Offset Address: 0x0038 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Reserved CNTE N - RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Symbol Description 31 ~ 1 Reserved -

0 CNTEN Flash operation timer start bit

0: flash operation timer enabled 1: flash operation timer disabled Note: CNTEN@CNTCR is set to 1, and the counting down function of flash operation timer is enabled. The counter is counted down to 0, this bit is cleared, and the flash operation timer is disabled.

8.6.12 Flash Special Information Memory Block Unlock Control Register (FLASH_IKYR)

Offset Address: 0x0040 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 INFO_KEY[31:0] WO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 INFO_KEY[31:0] WO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Symbol Description 31 ~ 0 INFO_KEY[31:0] Flash special information memory block unlock control bit Writing the flash unlock value and operation unlock value sequentially to INFO_KEY[31:0] can unlock the OTP block of flash special information blocks. After the unlocking is successfully done, INFLCK@FLASH_CR bit is clearedby hardware and INFO_KEY[31:0] is cleared. For the Flash single unlock operation, after the unlocking is successfully done, only one programming or erasing operation of the flash is allowed. After the operation is completed, the INFLCK@FLASH_CR bit is automatically set to '1' by hardware, and the flash related block is locked again. For the Flash multiple unlock operation, after the unlocking is successfully done, multiple programming or erasing operations of the flash are allowed. But after the operations are completed, the INFLCK@FLASH_CR bit must be set to '1' by software, and then the flash related block can be locked again. These bits can be written by software only.

8.6.13 Memory Mapping Selection Register (FLASH_MEMRMP)

Offset Address: 0x0100 Reset Value: 0x0000 XXXX b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 MEMMODE[15:0] RW X X X X X X X X X X X X X X X X Bit Symbol Description 31 ~ 16 Reserved - 15 ~ 0 MEMMODE[15:0] Memory mapping selection These bits are set by hardware after reset and can be read or written by software. 0x5AA5: Boot block mapped to address 0x0 Other: Main flash memory mapped to address 0x0 Map to main flash memory as long as it does not satisfy 0x5AA5

1. Power Control (PWR) The system operating voltage (VDD) of SH33F2801 is 2.4 to 5.5V. An embedded linear voltage regulator is used to supply the system core power. The SH33F2801 has a complete set of power-on reset and brownout detection (BOD) circuits, the BOD is important in some battery applications.

9.1 Brownout Detection (BOD)

 Enable by setting register  Both rising and falling can generate an interrupt  Adjustable voltage detection  Has hysteresis to reduce the impact of voltage fluctuations  Hardware debounce, debounce time is about 60μs  Wake-up stop mode Brownout detection is used to monitor the supply voltage. If the voltage is above or below the specified value, an internal flag is generated and an interrupt is generated. It is mainly used to detect changes in the voltage of power and is also used to monitor the power supply of the system. In some applications, it can be used for low-voltage detection, and the system software can take some protection measures according to it such as data backup, site retention, etc. BOD can cause an NMI interrupt, enabled by the IEN_BOD@SYSCFG_SAFR control bit.

9.2 Low-voltage Reset (LVR)

In AC or high-capacity battery applications, switching on a large load can easily cause the MCU power supply to temporarily fall below the set operating voltage. A low voltage reset means that the protection system generates a valid reset below the set voltage.  Can be chosen to be turned on via power control register, and can set LVR voltage via power control register  Debounce time of LVR-TLVR is about 60µs.  When power voltage is lower than the set voltage VLVR, internal reset will be generated. After LVR function is turned on, it has the following features (t indicates the duration of which the voltage is lower than the set voltage VLVR): When VDD ≤ VLVR and t ≥ TLVR, system reset is generated. When VDD > VLVR or VDD < VLVR, but the duration t < TLVR, system reset will not be generated.

9.3 Low Consumption Management

SH33F2801 can reduce system power consumption by:  Use low voltage power supply;  Lower system clock;  Turn off unused peripheral clocks on APB and AHB buses (default is off);  Lower the current on GPIO and peripheral interface circuits; SH33F2801 supports two low power modes:  Sleep Mode: basic low power mode, the MCU core stops running, but the peripherals used, including the core peripherals of the CPU, such as NVIC, SysTick, etc. are still running;  Stop Mode: deep low power mode, in addition to shutdown of the core, most of the peripherals used are stopped, leaving only individual peripherals that are responsible for the wake-up task to keep running (clocks provided by LSI), such as IWDT, BOD, LVR, etc. Table9-1 Low Consumption Modes Mode Enter Wake-Up Wake-up Delay Sleep Mode WFI/WFE, keep SLEEPDEEP=0 Any interrupt/wake-up event/reset signal None Stop Mode WFI/WFE, keep SLEEPDEEP=1 Any external interrupt/reset signal 1. HSI wake-up time; 2. HSE and PLL wake-up time (if used); 3. Core power supply wake-up time.

9.3.1 Sleep Mode

Sleep mode can reduce system power consumption. In this mode, the program aborts and the CPU clock stops, but the peripheral clock continues to run. In sleep mode, the CPU stops in a confirmed state, and all CPU states are saved (including the system clock register) before entering sleep mode, SRAM and register contents are retained, and GPIO remains in level state as when it enters.

9.3.2 Stop Mode

The stop mode allows the chip to enter a state of very low power consumption. The stop mode will stop all clocks for the CPU and peripherals (except for the LSI clock) and put the power supply module into low consumption state. Because the IWDT clock source is LSI, IWDT can continue to operate in stop mode, and LVR and BOD can also operate normally in stop mode (there are independent switches, which can be turned off if not needed). The states of all CPUs are saved before entering stop mode, SRAM and register contents are retained, and GPIO remains in level state as when it enters, but PWM outputs (MCM and PCA modules) are fixedly switched to the high-resistance state. Note: For digital peripherals, such as UART, SPI, TIMER, etc., although the module enabling is not turned off during shutdown, the module is in stop state due to the clock cut off, and the module pin level remains at the level before stop mode. For analog peripherals, such as ADC, OP, CMP, if the module enabling is not turned off, the digital part of the clock is turned off and stopped when the shutdown takes place, but the power supply of analog part will not be automatically cut off, and power supply of this part can be manually turned off according to the control requirements (generally by turning off module enabling). For PWM module (MCM and PCA), not only is it stopped when the shutdown takes place, it will also be forced to switch to high-resistance output to protect the external drive circuit. In application, in order to avoid the state change before and after the shutdown from affecting the system operation, it is recommended that the user manually turn off the PWM module before entering shutdown, and then re-initialize the PWM after wake-up. PLL, HSI, and HSE circuits are all automatically turned off during shutdown. When the system enters stop mode, the control bits of SW, SWS, PLLON, PLLRDY, HSEON, HSERDY, PLLRDYIE, PLLRDYIF, HSERDYIE, and HSERDYIF of the RCC module are in reset state. In stop mode, the following modules can operate normally:  Independent watchdog (IWDT), once IWDT is started, it can no longer be stopped except for system reset (note);  Brownout Detection (BOD), turned on by user;  Low frequency internal RC clock (LSI), always turned on；  Wakeup Timer, which uses the TIM7/TIM8 timer to configure, and LSICLK clock source is required to be configured, or an external clock input is required to be done; Note: By default, IWDT is turned on in stop mode (provided IWDT is turned on), in which case the stop mode will be woken up by IWDT. The user code option "OP_WDTPD" can be set to not turn on to avoid IWDT from waking up the shutdown. The clock safety monitoring (CSM) module is invalid in stop mode, and the CSM can work normally in sleep mode.

9.4 Register

SYSCFG Module Register List (Base Address: 0x4004 4000) Address Register Name Description 0x4004 0800 PWRCR Power control register 0x4004 0804 PWRSR Power status register

9.4.1 Power control register (SYSCFG_PWRCR)

Offset Address: 0x0000 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Reserved LVREN VLVR BODE N BODIE BODMD[1:0] VBOD[3:0] - RW RW RW RW RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

31 ~ 8 Reserved -

9 LVREN

0: LVR is disabled 1: LVR is enabled

8 VLVR

the Voltage of LVR control bit 0: 4.1 V 1: 2.8 V

7 BODEN BOD enable bit

0: Brownout detection is disabled 1: Brownout detection is enabled

6 BODIE BOD interrupt enable bit

5 ~ 4 BODMD[1:0] BOD mode selection control bit 00: The BODIF flag is set to 1 only when VDD voltage is from less than BOD threshold to greater than BOD threshold 01: The BODIF flag is set to 1 only when VDD voltage is from greater than BOD threshold to less than BOD threshold 10: When VDD voltage is from greater than threshold to less than threshold, or is from less than threshold to greater than threshold, the BODIF flag is set 11: Reserved 3 ~ 0 VBOD[3:0] BOD threshold voltage setting bit 0000: 2.80 V 0001: 2.90 V 0010: 3.00 V 0011: 3.10 V 0100: 3.20 V 0101: 3.30 V 0110: 3.40 V 0111: 3.50 V 1000: 3.60 V 1001: 3.70 V 1010: 3.80 V 1011: 3.90 V 1100: 4.00 V 1101: 4.10 V 1110: 4.20 V 1111: 4.30 V

9.4.2 Power Status Register (SYSCFG_PWRSR)

Offset Address: 0x0004 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Reserved BODF BODIF - RO RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Symbol Description 31 ~ 2 Reserved -

1 BODF BOD flag bit

0: The current voltage is higher than BOD voltage set in VBOD[3:0] 1: The current voltage is lower than BOD voltage set in VBOD[3:0]

0 BODIF BOD interrupt request flag

0: No interrupt pending, clear pending 1: Interrupt pending

1. Reset and Clock Control (RCC)

10.1 Reset

There are two types of reset: system reset (SYSRESET) and power reset (PWRESET).

10.1.1 System Reset

Except for the reset flags in RCC_CSR register of the clock controller, system reset will set all registers to their reset values. A system reset is generated when any of the following events occur:  Low level on the NRST pin (external reset)  Independent watchdog count termination (IWDT reset)  Window watchdog count termination (WWDT reset)  Software reset (SW reset) The source of the reset event can be identified by checking the reset status flag bit in RCC_CSR control status register.

10.1.1.1 Pin Reset

SH33F2801 has an independent reset pin, NRST, and a period of time of low level on this pin will cause a system reset.

10.1.1.2 Independent Watchdog Reset (IWDT)

After independent watchdog reset, IWDTRSTF@RCC_CSR flag is generated. See the introduction of “Independent Watchdog” part for details.

10.1.1.3 Window Watchdog Reset (WWDT)

After window watchdog reset, WWDTRSTF@RCC_CSR flag is generated. See the introduction of “Window Watchdog” part for details.

10.1.1.4 Software Reset

Software reset (core and peripheral) is achieved by setting the SYSRESETREQ bit to '1' in application interrupt and reset control register of the ARM Star core. Another control bit, VECTRESET, in this register resets only the ARM Star core and does not reset the peripheral. For more information, please see the ARM official manual "ARM Star Technical Reference Manual - Revision r2p1".

10.1.2 Power Reset

A power reset occurs when one of the following events occurs:  Power-on reset (POR reset)  Low voltage reset (LVR reset) Power reset will reset all registers.

10.1.2.1 Power-on Reset

SH33F2801 has a complete power-on reset (POR) circuit inside, and the system works normally when the supply voltage reaches VPOR. When VDD is lower than the specified limit voltage VPOR, the system remains in the reset state.

10.1.2.2 Low Voltage Reset

Low Voltage Reset (LVR) is a mandatory reset that can be turned on by the customer option "OP_LVR". When the power supply voltage is lower than VLVR, the MCU will generate a reset. See the introduction of “Low Voltage Reset” part for details.

10.2 Clock

Three different clock sources can be used to drive the system clock (SYSCLK):  HSI oscillator clock (8MHz)  HSE oscillator clock (4MHz～12MHz)  PLL clock (up to 84MHz) The PLL clock can select HSI and HSE as the clock source. 8MHz RC IWDT m u x m u x /4SYSCLK PLLCLK HSICLK HSECLK SW[1:0] HPRE[2:0] XTALX1 XTALX2 crystal ceramic CSM 128k RC LSICLK /16 PPRE[2:0] HCLK PCLK APB periphral clock clock enable AHB periphral clock PLLXTPRE HSEON OSCCFG[1:0] PLLSRC PLLF[5:0] clock enable /8 To systick System Clock 4M~12M 4M~84M Wakeup Timer(TIM8) m u x CLKS[1:0] From other clock source CSM output /16 /32 PLLK[2:0] PLL PLLCLKIN PRECLK reset VCOCLK /2 DIVCLK PLLON FCLK/HCLK Figure10-1 Clock Block Diagram User can configure the frequencies of AHB and APB through multiple prescalers.  HCLK: AHB bus clock, with maximum frequency being 84MHz. ARM Star core, memory, etc. are driven by HCLK.  PCLK: APB bus clock, with maximum frequency being 42MHz. Peripherals on APB bus are driven by PCLK. After the frequency RCC is divided by 8 via the AHB clock (HCLK), RCC is used as the external clock of SysTick. The above clock or core clock can be selected as the SysTick clock source by setting SysTick control and status registers.

10.2.1 HSE Clock

High-speed external clock signal (HSE) is generated from two clock sources: (1) External crystal/ceramic resonator: 4MHz - 12MHz XTAL1 XTAL2 Crystal/ Ceramic The 4~12Mz external oscillator (including crystal resonator and ceramic resonator) provides a more accurate clock for the system. The HSERDY@RCC_CR bit in the clock control register is used to indicate if the high-speed external oscillator is stable. At startup, the clock is not released until this bit is set to '1' by hardware. If an interrupt is allowed to be generated in the clock interrupt register RCC_CIENR, a corresponding interrupt will be generated. HSE crystal can be turned on and off by setting the HSEON@RCC_CR bit in the clock control register. In order to reduce the distortion of the clock output and shorten the startup stabilizing time, the crystal/ceramic resonator and the load capacitor must be as close as possible to the oscillator pins. The load capacitance value must be adjusted according to the selected oscillator. (2) External input clock: 4MHz – 12MHz XTAL1 XTAL2 External Clock In this mode, external clock must be provided. Its frequency could be as high as 12MHz. In this mode, the user must first fill the external clock on XTAL1, and then turn on the HSEON bit, while XTAL2 must be left floating at this time. However, XTAL2 can be set to be used as a GPIO port by setting the OSCCFG@SYSCFG_SAFR bit to 10b. Same as the external oscillator, the external clock also has a warm-up time and a Ready signal. The external clock is also monitored by the CSM.

10.2.2 HSI Clock

The HSI clock signal is generated by internal 8MHz RC oscillator and can be used directly as the system clock or as PLL input source. When acting as PLL input, it is recommended to turn on the PLL prescaler factor PLLXTPRE@RCC_CFGR, which also means pre-division, is turned on. HSI also has the following features:  After system reset, HSI is selected as the system clock.  HSI is always open after system power-on (whether or not the system clock uses HSI) and is turned off in stop mode.  Startup time of HSI RC oscillator is shorter than HSE crystal oscillator.  The HSI RC is calibrated to 0.2% (25°C) after production and does not exceed 1% over the full temperature range. At system reset, the factory calibration value is loaded into HSICAL[7:0] bit of the clock control register. If the user's application is based on different voltages or environment temperatures, this will affect the accuracy of the RC oscillator. The HSI frequency can be further adjusted by HSITRIM[2:0] bit in the clock control register.

10.2.3 PLL

The internal PLL can be used to multiply by frequency the internal RC output clock of the HSI or the external crystal oscillator output clock of the HSE. The PLL settings must be completed before PLL is activated. These parameters include PLLSRC, PLLXTPRE, PLLF, PLLK, and they cannot be changed once PLL is activated. If PLL interrupt is allowed in the clock interrupt register, an interrupt request can be generated when PLL is ready. The PLL frequency multiplication factor consists of three parameters, N, F, and K. The calculation formula is: N PLLCLKINPRECLK = (1) FPRECLKVCOCLK ×= (2) K VCOCLKPLLCLK ×= (3) N: determined by the prescaler factor PLLXTPRE, taking 1 or 2; F: specified by the frequency doubling factor PLLF, ranging from 15 to 78; K: specified by the frequency division factor PLLK, ranging from 1 to 8; For HSI clock source, it is recommended to take 2 as the prescaler factor N. For HSE clock source, take 1 as N. For PLL module, the PLLCLKIN input clock range is 4MHz to 12MHz, the PRECLK prescaler clock is required to meet the range of 4MHz to 8MHz, and the VCOCLK multiplier output clock is required to meet the range of 150MHz to 300MHz. The final PLLCLK clock is required to meet the range of 4MHz to 84MHz. The configuration of N, F, and K parameters must meet the above clock range requirements (Note). Note: PRECLK, VCOCLK, and PLLCLK are all required to be set within the allowable range. The over-range PLL parameter configuration cannot guarantee the stability of the clock system. Take the setting of 84MHz system main frequency as an example: (1) Select 8MHz as the clock source, set PLLXTPRE=0 (N=1), PLLF=6 (F=21), PLLK=0 (K=1), then PRECLK=8MHz, VCOCLK=168MHz, output PLLCLK is 8 × 21 / 1/2 = 84MHz; (2) Select 8MHz as the clock source, set PLLXTPRE=1 (N=2), PLLF=27 (F=42), PLLK=0 (K=1), then PRECLK=4MHz, VCOCLK=168MHz, output PLLCLK is 4 × 42 / 1/2 = 84 MHz.

10.2.4 LSI Clock

LSI RC provides a low consumption clock source for shutdown wake-up module drivers, including IWDT and Wakeup Timer. LSI cannot be used for system clock. The LSI clock frequency is around 128 KHz. The LSI RC is not an accurate clock source. The maximum error sometimes reaches ±40%. The LSI RC does not support calibration. But actual error of the LSI (128kHz) RC normal temperature 25 degrees has been written to 0 x0FFF F050H (LSB) and 0x0FFF F051H(MSB). The error calculation formula is (measured values - 128000) / 100, unit Hz, the user can read the error value from the flash memory. The LSI is always turned on after system power-on. It remains on in stop mode.

10.2.5 System Clock (SYSCLK) Selection

After system reset, the HSI oscillator is selected as the system clock. Switching from HSI clock to HSE or PLL clock is allowed only when the destination clock source is ready (HSE ready or PLL ready). The system clock is set by the SW control bit in the RCC_CR register.

10.2.6 Clock Safety Monitoring (CSM)

In order to enhance the reliability of the system and prevent serious consequences of system failure or even crash due to clock failure, SH33F2801 adds a clock safety monitoring (CSM) module. CSM monitors two sources: (1) The oscillation of the HSE, including the conditions of the crystal oscillator, the ceramic oscillator, or the external clock input. Once the vibration or oscillation is stopped or abnormal (the frequency is lower or higher than the normal value), the abnormality flag HSECSMF is sent; (2) The loss of lock for PLL (in the case PLL is used), once loss of lock occurs, the exception flag PLLCSMF is sent; The user can query the corresponding interrupt flag at RCC@CISTR to determine what kind of exception it is. If the above exception affects the system clock, a CSM interrupt is requested, which is connected to NMI non-maskable interrupt (enabled by the IEN_CSM@SYSCFG.SAFR control bit). For specific system clock and exception relationships, and when to generate CSM interrupts, see "CSM Exception Function Definition and Processing Table" below. The CSM power-on is always turned on, but can be turned off by the user code option "OP_CSM". When CSM is turned on, monitoring is only effective after HSE ready or PLL lock. After CSM occurs, except for HSECSMF and PLLCSMF being set, other RCC register control and status bits such as HSEON(Note), HSERDY, HSERDYIE, HSERDYIF, PLLON, PLLRDY, PLLRDYIE, PLLRDYIF may change (will not reset unitedly). To ensure the consistency of the state when the clock is restored, the user program is required to clear these control and status bits, return to the initial power-on state, and turn on the clock according to the steps and switch to the original working state. Note: HSEON cannot be turned off when PLLSRC=1, so turning off HSEON requires resetting the PLLSRC first; Note: Once CSM interrupt is generated, which causes NMI to execute without stop until the CSM interrupt pending bit is cleared. Therefore, in NMI processing program, the CSM interrupt must be cleared by setting the CSMC bit in the clock interrupt register RCC@CICLR (two exception flags will be cleared at the same time). The following code demonstrates the process of clock failure and recovery. CSM can be configured to generate an NMI interrupt, and the interrupt service program performs clock recovery judgment and switching operations. Vo id NMI Exception (void)  if (CSM interrupt is generated) (1) The system clock has been automatically switched to HSI; (2) The RCC related control and status bits have been automatically reset;  (3) User can add application-related protection codes here; /* The following steps are preparations for HSE / PLL recovery, once recovered the ready flag will be queried (can also use interrupt mode)*/ (4) User manually turns on HSE and PLL; (5) The program waits for HSE ready; (6) If it times out, it indicates that the HSE has not been restored, and the waiting can continue. The program still runs under the HSI clock. (7) HSE ready, continue waiting for PLL ready; (8) If it times out, it indicates that the PLL has not been recovered, and the waiting can continue. The program still runs under the HSI clock. (9) PLL ready, the system clock is switched to PLL operation; (10) Clear the CSM interrupt pending bit;

10.2.7 System Tick Timer (SysTick)

SysTick is a 24-bit down-count timer implemented in the ARM Star core. A fixed interval of time ticks can be provided, which can be used for monitoring or timing in the main flow. Because all ARM Star chips have SysTick, it helps cross-platform migration for operating systems or programs. SysTick can use core clock or external reference clock, and its period can be set by the "Reload Value Register". For specific register definitions, please see the ARM official manual. SH33F2801 provides an external reference clock to the SysTick, fixed to HCLK/8, and its standard value is fixed at 105000, which is a 10ms time reference generated at a frequency of 84MHz for HCLK.

10.2.8 HSI Trimming Function (HSITRIM)

When SH33F2801 is produced in factory, its HSI has been calibrated to a very high accuracy (normal temperature 0.2%), but the HSI accuracy will decrease in full temperature range (the accuracy is different in different temperature range, see “Electrical Characteristics” for details), then the user can fine-tune HSI using the 3bit control bits HSITRIM[2:0] again to properly improve the accuracy. SH33F2801 adds a small function. In case the system just has another external clock reference (note), this external clock reference can be used to calibrate the HSI clock online by using HSI to measure the external clock reference after 4096 frequency division, and the result is stored in TRIMREF[12:0]@RCC_HSICAL. According to the result, the user can fine-tune HSITRIM[2:0], so as to compensate for the temperature change. This function is turned on by TRIMRUN@RCC_HSICAL. The calculation formula is: HSI current frequency = (TRIMREF[12:0]+1)/4096 * Reference clock frequency For example, the external clock reference is 8.000MHz. If TRIMREF[12:0]=4086 is obtained, it means that the current HSI the table is +0.25%. . If the system clock uses HSI+PLL, PLL needs to be turned back on after HSI fine tuning.

10.3 Register

RCC Module Register List (Base Address: 0x4004 0C00) Address Register Description 0x4004 0C00 CR Clock control register 0x4004 0C04 CFGR Clock configuration register 0x4004 0C08 CIENR Clock interrupt enable register 0x4004 0C0C CISTR Clock interrupt status register 0x4004 0C10 CICLR Clock interrupt flag clear register 0x4004 0C14 AHBRSTR AHB peripheral reset register 0x4004 0C1C APB0RSTR APB peripheral reset register 0x4004 0C20 AHBENR AHB peripheral clock enable register 0x4004 0C28 APB0ENR APB peripheral clock enable register 0x4004 0C2C RSTSTR RESET status register 0x4004 0C30 RSTCLR RESET status clear register 0x4004 0C34 HSICAL HSI oscillator calibration register 0x4004 0C38 RCCLOCK RCC configuration lock register

10.3.1 Clock Control Register (RCC_CR)

Offset Address: 0x0000 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Reserved CSM ON PLL RDY PLL ON HSE RDY HSE ON SWS[1:0] SW[1:0] - RW RO RW RO RW RO RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Symbol Description 31 ~ 9 Reserved -

8 CSMON CSM Clock detection Enable Bit

0: CSM Disable 1: CSM Enable

7 PLLRDY PLL clock ready flag

After the PLL is locked, it is set to '1' by hardware. 0: PLL is not locked 1: PLL is locked

6 PLLON PLL enable

Set to '1' by software or cleared to enable or disable PLL This bit cannot be cleared when PLL clock is used as the system clock. 0: PLL is disabled 1: PLL is enabled

5 HSERDY External high frequency oscillator ready flag

Set to 1 by hardware to indicate that the external high frequency oscillator is stabilized After the HSEON bit is cleared, this bit requires 6 external 4-12MHz clock cycles to be cleared. 0: External 4-12MHz clock is not ready 1: External 4-12MHz clock is ready Description: This bit is dependent on HSEON and only indicates the external high frequency oscillator ready state.

4 HSEON External high frequency oscillator enable

Set to 1 or cleared by software This bit cannot be cleared when the HSE is used directly or indirectly as the system clock. 0: HSE oscillator is disabled 1: HSE oscillator is enabled 3 ~ 2 SWS[1:0] System clock switch status Set to ‘1’ or cleared by hardware to indicate the system clock source. 00: HSI as the system clock 01: HSE as the system clock 1x: PLL output as system clock

1 ~ 0 SW[1:0] System clock switch Set to ‘1’ or cleared by software to select the system clock source. 00: HSI as the system clock 01: HSE as the system clock 1x: PLL output as system clock

10.3.2 Clock Configuration Register (RCC_CFGR)

Offset Address: 0x0004 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved HSE 16M PLL XTP RE PLL SRC PLLF[5:0] - RW RW RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 PLLF[5:0] PLLK[2:0] Reserved PPRE[2:0] HPRE[2:0] RW RW - RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Symbol Description 31 ~ 20 Reserved -

20 HSEM Crystal oscillator high frequency mode

0: Crystal oscillator high frequency mode is off 1: Crystal oscillator high frequency mode is on

19 PLLXTPRE Pre-divider for PLL entry

After being divided by setting to ‘1’ or clearing by software, it is used as a PLL input clock. This bit can only be written when the PLL is turned off. 0: No pre-division 1: 2 frequency division

18 PLLSRC PLL entry clock source

Set to ‘1’ or cleared by software to select the PLL input clock source. This bit can only be written when the PLL is turned off. 0: HSI clock as PLL input clock 1: HSE clock as PLL input clock 17 ~ 12 PLLF[5:0] PLL multiplication factor F Determine the PLL multiplier parameter by software settings This can be written only when the PLL is turned off. 000000: F=15 000001: F=16 000010: F=17 111101: F=76 111110: F=77 111111: F=78

11 ~ 9 PLLK[2:0] PLL multiplication factor K Determine the PLL multiplier parameter by software settings This can be written only when the PLL is turned off. 000: K=1 001: K=2 010: K=3 011: K=4 100: K=5 101: K=6 110: K=7 111: K=8 8 ~ 6 Reserved - 5 ~ 3 PPRE[2:0] APB low-speed prescaler (APB) Set to ‘1’ or cleared by software to control the pre-division coefficient of the low speed APB clock (PCLK). 0xx: HCLK no division 100: HCLK 2 frequency division 101: HCLK 4 frequency division 110: HCLK 8 frequency division 111: HCLK 16 frequency division Warning: The software must ensure that the APB clock frequency does not exceed 42MHz. 2 ~ 0 HPRE[2:0] AHB Prescaler Set to ‘1’ or cleared by software to control the pre-division coefficient of the AHB clock 000: SYSCLK no division 001: SYSCLK 2 frequency division 010: SYSCLK 4 frequency division 011: SYSCLK 8 frequency division 100: SYSCLK 16 frequency division 101: SYSCLK 32 frequency division Other: SYSCLK 32 frequency division

10.3.3 Clock interrupt enable register (RCC_CIENR)

Offset Address: 0x0008 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Reserved PLLRD YIE HSER DYIE Reserved - RW RW - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Symbol Description 31 ~ 5 Reserved -

4 PLLRDYIE PLL ready interrupt enable

Set to ‘1’ or cleared by software to enable or disable the PLL ready interrupt. 0: PLL ready interrupt is disabled; 1: PLL ready interrupt is enabled.

3 HSERDYIE HSE ready interrupt enable

Set to ‘1’ or cleared by software to enable or disable external 4-12MHz oscillator. 0: HSE ready interrupt is disabled; 1: HSE ready interrupt is enabled. 2 ~ 0 Reserved -

10.3.4 Clock Interrupt Status Register (RCC_CISTR)

Offset Address: 0x000C Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Reserved CSMP LLF CSMH SEF Reserv ed PLLRD YIF HSER DYIF Reserved - RO RO - RO RO - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Symbol Description 31 ~ 8 Reserved -

7 CSMPLLF PLL clock security monitor interrupt flag

It is valid when the PLL loses lock and is set to '1' by hardware. Cleared by software by setting the CSMC bit to ‘1’. 0: CSM interrupt is not caused by PLL exception; 1: CSM interrupt is caused by a PLL exception;

6 CSMHSEF HSE clock security monitor interrupt flag

It is valid when the HSE loses effect and is set to '1' by hardware. Cleared by software by setting the CSMC bit to ‘1’. 0: CSM interrupt is not caused by HSE invalidity ; 1: CSM interrupt is caused by a HSE invalidity ;

5 Reserved -

4 PLLRDYIF PLL ready interrupt flag

It is set to '1' by hardware, and is cleared by setting PLLRDYC bit to ‘1’. 0: Clock ready interrupt is not generated by PLL lock; 1: Clock ready interrupt is caused by PLL lock.

3 HSERDYIF HSE ready interrupt flag

It is set to '1' by hardware, and is cleared by setting HSERDYC bit to ‘1’. 0: Clock ready interrupt is not generated by external 4-12MHz oscillator; 1: Clock ready interrupt is caused by external 4-12MHz oscillator. 2 ~ 0 Reserved -

10.3.5 Clock Interrupt Flag Clear Register (RCC_CICLR)

Offset Address: 0x0010 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Reserved CSMC Reserved PLLRD YC HSER DYC Reserved - WO - WO WO - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Symbol Description 31 ~ 8 Reserved -

7 CSMC Clock security monitor interrupt clear

The CSM interrupt flag bit CSMIF is cleared by setting this bit to '1' by software. 0: No effect; 1: Clear the CSMPLLF and CSMHSEF interrupt flag bits. 6 ~ 5 Reserved -

4 PLLRDYC PLL ready interrupt clear

The PLL ready interrupt flag bit PLLRDYF is cleared by setting this bit to '1' by software. 0: No effect; 1: Clear the PLL ready interrupt flag bit PLLRDYF.

3 HSERDYC HSE ready interrupt clear

The HSE ready interrupt flag bit HSERDYF is cleared by setting this bit to '1' by software. 0: No effect; 1: Clear the HSE ready interrupt flag bit HSERDYF. 2 ~ 0 Reserved -

10.3.6 AHB Peripheral Reset Register (RCC_AHBRSTR)

Offset Address: 0x0014 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Reserved MAC PRS T CRC RST SYS CFG RST MCM RST GPI ORS T - RW1s RW1s RW1s RW1s RW1s 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Symbol Description 31 ~ 5 Reserved -

4 MACPRST Math co-processor reset

Set to ‘1’ by software, cleared by hardware 0: No effect 1: Math co-processor reset

3 CRCRST CRC module reset

Set to ‘1’ by software, cleared by hardware 0: No effect 1: CRC module reset

2 SYSCFGRST SYSCFG reset

Set to ‘1’ by software, cleared by hardware 0: No effect 1: SYSCFG reset Note: The one-time register in this module cannot be reset.

1 MCMRST MCM module peripheral control reset

Set to '1' by software, cleared by hardware 0: No effect 1: MCM reset

0 GPIORST GPIO configuration block reset

Set to ‘1’ by software, cleared by hardware 0: No effect 1: GPIO configuration block reset

10.3.7 APB Peripheral Reset Register (RCC_APB0RSTR)

Offset Address: 0x001C Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved FIFO 2RS T FIFO 1RS T - RW1s RW1s 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 FIFO 0RS T Rese rved CAN 0RS T ADC RST PCA 1RS T PCA 0RS T AMO CRS T WW DTR ST TWI0 RST SPI0 RST UAR T2R ST UAR T1R ST UAR T0R ST QEI RST TIM8 RST TIM7 RST RW1s - RW1s RW1s RW1s RW1s RW1s RW1s RW1s RW1s RW1s RW1s RW1s RW1s RW1s RW1s 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Symbol Description 31 ~ 18 Reserved -

17 FIFO2RST FIFO2 reset

Set to ‘1’ by software, cleared by hardware 0: No effect 1: FIFO2 reset

16 FIFO1RST FIFO1 reset

Set to ‘1’ by software, cleared by hardware 0: No effect 1: FIFO1 reset

15 FIFO0RST FIFO0 reset

Set to ‘1’ by software, cleared by hardware 0: No effect 1: FIFO0 reset

14 Reserved -

13 CAN0RST CAN0 reset

Set to ‘1’ by software, cleared by hardware 0: No effect 1: CAN0 reset

12 ADCRST ADC reset

Set to ‘1’ by software, cleared by hardware 0: No effect 1: ADC reset

11 PCA1RST PCA1 reset

Set to ‘1’ by software, cleared by hardware 0: No effect 1: PCA1 reset

10 PCA0RST PCA0 reset

Set to ‘1’ by software, cleared by hardware 0: No effect 1: PCA0 reset

9 AMOCRST Analog module on chip reset

Set to ‘1’ by software, cleared by hardware 0: No effect 1: Analog module on chip reset

8 WWDTRST Window watchdog reset

Set to ‘1’ by software, cleared by hardware 0: No effect 1: Window watchdog reset

7 TWI0RST TWI 0 reset

Set to ‘1’ by software, cleared by hardware 0: No effect 1: TWI0 reset

6 SPI0RST SPI 0 reset

Set to ‘1’ by software, cleared by hardware 0: No effect 1: SPI0 reset

5 UART2RST UART 2 reset

Set to ‘1’ by software, cleared by hardware 0: No effect 1: UART2 reset

4 UART1RST UART 1 reset

Set to ‘1’ by software, cleared by hardware 0: No effect 1: UART1 reset

3 UART0RST UART0 reset

Set to ‘1’ by software, cleared by hardware 0: No effect 1: UART0 reset

2 QEIRST QEI reset

Set to ‘1’ by software, cleared by hardware 0: No effect 1: QEI reset

1 TIM8RST Timer 8 reset

Set to ‘1’ by software, cleared by hardware 0: No effect 1: Timer 8 reset

0 TIM7RST Timer 7 reset

Set to ‘1’ by software, cleared by hardware 0: No effect 1: Timer 7 reset

10.3.8 AHB Peripheral Clock Enable Register (RCC_AHBENR)

Offset Address: 0x0020 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Reserved MAC PEN CRC EN SYS CFG EN MCM EN GPI OEN - RW RW RW RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Symbol Description 31 ~ 5 Reserved -

4 MACPEN Math co-processor clock enable

Set to ‘1’ or cleared by software 0: math co-processor clock is disabled 1: math co-processor clock is enabled

3 CRCEN CRC clock enable

Set to ‘1’ or cleared by software 0: CRC clock is disabled 1: CRC clock is enabled

2 SYSCFGEN SYSCFG clock enable

Set to ‘1’ or cleared by software 0: SYSCFG clock is disabled 1: SYSCFG clock is enabled Note: The one-time register in this module cannot be reset.

1 MCMEN MCM module external control clock enable

Set to ‘1’ or cleared by software 0: MCM clock is disabled 1: MCM clock is enabled

0 GPIOEN GPIO configuration block clock enable

Set to ‘1’ or cleared by software 0: GPIO block clock is disabled 1: GPIO block clock is enabled

10.3.9 APB Peripheral Clock Enable Register (RCC_APBENR)

Offset Address: 0x0028 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved FIFO 2EN FIFO 1EN - RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 FIFO 0EN Rese rved CAN 0EN ADC EN PCA 1EN PCA 0EN AMO CEN WW DTE N TWI0 EN SPI0 EN UAR T2E N UAR T1E N UAR T0E N QEIE N TIM8 EN TIM7 EN RW - RW RW RW RW RW RW RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Symbol Description 31 ~ 14 Reserved -

17 FIFO2EN FIFO2 clock enable

Set to ‘1’ or cleared by software 0: FIFO2 clock is disabled 1: FIFO2 clock is enabled

16 FIFO1EN FIFO1 clock enable

Set to ‘1’ or cleared by software 0: FIFO1 clock is disabled 1: FIFO1 clock is enabled

15 FIFO0EN FIFO0 clock enable

Set to ‘1’ or cleared by software 0: FIFO0 clock is disabled 1: FIFO0 clock is enabled

13 CANEN CAN clock enable

Set to ‘1’ or cleared by software 0: CAN clock is disabled 1: CAN clock is enabled

12 ADCEN ADC clock enable

Set to ‘1’ or cleared by software 0: ADC clock is disabled 1: ADC clock is enabled

11 PCA1EN PCA1 clock enable

Set to ‘1’ or cleared by software 0: PCA1 clock is disabled 1: PCA1 clock is enabled

10 PCA0EN PCA0 clock enable

Set to ‘1’ or cleared by software 0: PCA0 clock is disabled 1: PCA0 clock is enabled

9 AMOCEN Analog module on chip clock enable

Set to ‘1’ or cleared by software 0: analog module on chip clock is disabled 1: analog module on chip clock is enabled

8 WWDTEN Window watchdog clock enable

Set to ‘1’ or cleared by software 0: window watchdog clock is disabled 1: window watchdog clock is enabled

7 TWI0EN TWI1 clock enable

Set to ‘1’ or cleared by software 0: TWI0 clock is disabled 1: TWI0 clock is enabled

6 SPI0EN SPI1 clock enable

Set to ‘1’ or cleared by software 0: SPI0 clock is disabled 1: SPI0 clock is enabled

5 UART2EN UART2 clock enable

Set to ‘1’ or cleared by software 0: UART2 clock is disabled 1: UART2 clock is enabled

4 UART1EN UART1 clock enable

Set to ‘1’ or cleared by software 0: UART1 clock is disabled 1: UART1 clock is enabled

3 UART0EN UART0 clock enable

Set to ‘1’ or cleared by software 0: UART0 clock is disabled 1: UART0 clock is enabled

2 QEIEN QEI clock enable

Set to ‘1’ or cleared by software 0: QEI clock is disabled 1: QEI clock is enabled

1 TIM8EN Timer 8 clock enable

Set to ‘1’ or cleared by software 0: timer 8 clock is disabled 1: timer 8 clock is enabled

0 TIM7EN Timer 7 clock enable

Set to ‘1’ or cleared by software 0: timer 7 clock is disabled 1: timer 7 clock is enabled

10.3.10 RESET Status Register (RCC_RSTSTR)

Offset Address: 0x002C Reset Value: 0x0000 0004 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Reserved Reserv ed WWDT RSTF IWDTR STF SWRS TF PORS TF LVRST F PINRS TF - - RO RO RO RO RO RO 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 Bit Symbol Description 31 ~ 6 Reserved -

5 WWDTRSTF Window watchdog reset flag

Set to ‘1’ by hardware when window watchdog reset occurs. Cleared by software via writing on WWDTRSTFC bit. 0: No window watchdog reset occurs 1: A window watchdog reset occurs

4 IWDTRSTF Independent watchdog reset flag

Set to ‘1’ by hardware when independent watchdog reset occurs. Cleared by software via writing on IWDTRSTFC bit. 0: No independent watchdog reset occurs 1: An independent watchdog reset occurs

3 SWRSTF Software reset flag

Set to ‘1’ by hardware when software reset occurs. Cleared by software via writing on SWRSTFC bit. 0: No software reset occurs 1: A software reset occurs

2 PORSTF POR reset flag

Set to ‘1’ by hardware when POR reset occurs. Cleared by software via writing on PORSTFC bit. 0: No POR reset occurs 1: A POR reset occurs

1 LVRSTF LVR reset flag

Set to ‘1’ by hardware when LVR reset occurs. Cleared by software via writing on LVRSTFC bit. 0: No LVR reset occurs 1: An LVR reset occurs

0 PINRSTF PIN reset flag

Set to ‘1’ by hardware when NRST pin reset occurs. Cleared by software via writing on PINRSTFC bit. 0: No NRST pin reset occurs 1: An NRST pin reset occurs

10.3.11 RESET Status Clear Register (RCC_RSTCLR)

Offset Address: 0x0030 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Reserved Reserv ed WWDT RSTFC IWDTR STFC SWRS TFC PORS TFC LVRST FC PINRS TFC - - WO WO WO WO WO WO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Symbol Description 31 ~ 6 Reserved -

5 WWDTRSTFC WWDT reset flag clear

Set to ‘1’ by software to clear reset flag. 0: No effect 1: Clears reset flag

4 IWDTRSTFC IWDT reset flag clear

Set to ‘1’ by software to clear reset flag. 0: No effect 1: Clears reset flag

3 SWRSTFC SOFTWARE reset flag clear

Set to ‘1’ by software to clear reset flag. 0: No effect 1: Clears reset flag

2 PORSTFC POR reset flag clear

Set to ‘1’ by software to clear reset flag. 0: No effect 1: Clears reset flag

1 LVRSTFC LVR reset flag clear

Set to ‘1’ by software to clear reset flag. 0: No effect 1: Clears reset flag

0 PINRSTFC PIN reset flag clear

Set to ‘1’ by software to clear reset flag. 0: No effect 1: Clears reset flag

10.3.12 HSI Oscillator Calibration Register (RCC_HSICAL)

Offset Address: 0x0034 Reset Value: 0xXXXX XX00 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 TRIMR UN Reserved TRIMREF[12:0] RW - RO 0 0 0 X X X X X X X X X X X X X b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 HSICAL[7:0] Reserved HSITRIM[2:0] RO - RW X X X X X X X X 0 0 0 0 0 0 0 0 Bit Symbol Description

31 TRIMRUN HSI user adjustment switch, can only be set to 1 by software, and cleared

0: The operation has ended or not started 1: Start HSI ADJ, the flag is 1 during the calculation, and the flag is cleared by hardware after the calculation is completed. Note: Allowing clearing RUN during the calculation to force the calculation to end. 30 ~ 29 Reserved - 28 ~ 16 TRIMREF[12:0] HSI user calibration parameter value After the RUN operation is completed, the user can read the HSI user calibration parameter value from this register. (HSI count HSE division source) 15 ~ 8 HSICAL[7:0] Internal high frequency RC oscillator calibration These bits are automatically initialized at system startup 7 ~ 3 Reserved - 2 ~ 0 HSITRIM[2:0] Internal high frequency RC oscillator adjustment Write by software to adjust the HSI frequency, which are superimposed on the HSICAL[7:0] value. These bits are based on HSICAL[7:0], allowing the user to enter an adjustment value to adjust the frequency of the internal HSI RC oscillator based on voltage and temperature changes. 000: +0 (default) 001: +0.25% 010: +0.5% 011: +0.75% 100: -1% 101: -0.75% 110: -0.5% 111: -0.25%

10.3.13 RCC Configuration Lock Register (RCC_RCCLOCK)

Offset Address: 0x0038 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 LOCK[15:0] RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Symbol Description 31 ~ 16 Reserved - 15 ~ 0 LOCK[15:0] RCC register lock bit 0x33CC: Unlock Other: Lock

10.3.14 SysTick Control and Status Register（SysTick_CTRL）

Address: 0xE000 E010 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved CTF LAG - R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Reserved CLK SOU RCE TICK INT ENA BLE - RW RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Symbol Description 31 ~ 17 Reserved -

16 CTFLAG Count Flag

Returns 1 if timer counted to 0 since the last read of this register. 15 ~ 3 Reserved -

2 CLKSOURCE Selects the SysTick timer clock source

0: External reference clock（HCLK/8） 1: Processor clock（HCLK）

1 TICKINT Enables SysTick exception request

0: Counting down to zero does not assert the SysTick exception request. 1: Counting down to zero asserts the SysTick exception request.

0 ENABLE Enables the counter

0: Disable 1: Enable

10.3.15 SysTick Reload Value Register（SysTick_LOAD）

Address: 0xE000 E014 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved RELOAD[23:16] - RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 RELOAD[15:0] RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Symbol Description 31 ~ 24 Reserved - 23 ~ 0 RELOAD[23:0] SysTick Reload Value Register Value to load into the SYST_CVR when the counter is enabled and when it reaches 0。

10.3.16 SysTick Current Value Register（SysTick_VAL）

Address: 0xE000 E018 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved CURRENT[23:16] - RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 CURRENT[15:0] RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Symbol Description 31 ~ 24 Reserved - 23 ~ 0 CURRENT[23:0] SysTick Current Value Register Reads the current value of the SysTick counter. A write of any value clears the field to 0, and also clears the SYST_CSR.COUNTFLAG bit to 0.

10.3.17 SysTick Calibration Register（SysTick_CALIB）

Address: 0xE000 E01C Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 NORE F SKEW Reserved TENMS[23:16] R R - RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 TENMS[15:0] RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Symbol Description

31 NOREF Indicates whether the device provides a reference clock to the processor

1: Reference clock provided. 0: No reference clock provided.

30 SKEW Indicates whether the TENMS value is exact

1: TENMS value is exact 0: TENMS value is inexact, or not given 29 ~ 24 Reserved - 23 ~ 0 TENMS[23:0] SysTick calibration value Reload value for 10ms (100Hz) timing, subject to system clock skew errors. If the value reads as zero, the calibration value is not known.

1. Watchdog Timer (WDT)

11.1 Independent Watchdog Timer (IWDT)

The independent watchdog (IWDG) is clocked by its own dedicated low-speed clock (LSI) and thus stays active even if the main clock fails. If the IWDT feature is enabled through the customer option "OP_IWDT", the watchdog is automatically enabled at power-on, and will generate a reset unless the IWDT_CLR register is written by the software before the counter reaches end of count. If the IWDT feature is disabled through the customer option "OP_IWDT", the watchdog can be turned on in the program via the control bit IWDTON@IWDT_CR by software. When the independent watchdog is enabled, the counter starts down-count operation from the reset value of IWDTRLR@IWDT_CR. When it reaches the end of count value (0x000) a reset signal is generated (IWDG reset) and the IWDTRSTF@RCC_CSR flag will be set. Before the timer overflows, the counter is restarted by writing 0xAAAA to the dog feeding register IWDT_CLR to update the counter and then avoid overflow. If the IWDT is on, it can’t be off by software. IWDT can operate in stop mode, so it can be used as a wake-up timer. The code option OP_WDTPD can be used to select whether to turn the watchdog on or off during the stop mode (turned on in stop mode by default). The independent watchdog timer is a 12-bit decreasing counter with a separate built-in RC oscillator as its clock source, and the default overflow time is 4096*32/128 = 1024ms. Of course due to the inaccuracy of LSI, this overflow time is also inaccurate. When the microcontroller enters debug mode (The core halted), the IWDG counter either continues to work normally or stops, depending on DBG_IWDT@ DBGCR configuration bit.

11.2 Window Watchdog Timer(WWDT)

The window watchdog (WWDG) clock is prescaled from the APB clock and has a configurable time-window that can be programmed to detect abnormally late or early application behavior. It is suitable for applications that work in a precise timing window. A reset signal is generated when the window watchdog is refreshed too early or too late. The window watchdog is an 8-bit decreasing counter. The dog feeding area is a window area. Feeding the dog earlier than the window dog feeding area will generate an advanced abnormal event. Feeding the dog later than the window dog feeding area will generate a delayed abnormal event. In both cases, a reset will be caused. In addition, when the counter reaches the lower boundary of the window feeding dog area, it is the latest feeding time, and the WWDT interrupt can be applied. The lower boundary of the WWDT window in SH33F2801 is fixed to 0. When the counter of WWDT is 0, the WWDT interrupt occurs(if INT is enabled). In the handle, feeding the dog must be done in one WWDT cycle. If not, a reset is generated when the counter reaches 0xFF. The window watchdog is turned on in WWDT_CR. Once turned on, it can be turned off only when it is reset. The window watchdog’s working clock is PCLK. WT t1 t2 time Counter Latest Feeding Time Delayed Abnormal Area Advanced Abnormal Area The Window of Feeding Dog RL Figure11-1 Window Watchdog Diagram When applying WWDT, first set the WWDT window reload value WWDTRLR (labeled RL in the figure) and the window value WWDTWTR (labeled WT in the figure), then turn on WWDT, and the counter starts running (counter is initially the reload value, down-count operation). In the normal dog feeding area, the dog is fed by writing 0x5555 to the dog feeding register WWDTCLR. By setting RL>WT, the normal window monitoring function can be achieved, and advanced abnormality and delayed abnormality can be monitored. If RL<=WT is set, there is no advanced abnormality monitoring function, leaving only delayed abnormality monitoring function, and the function is similar to ordinary watchdog.

The window is the largest when RL=WT=0xFF. When the microcontroller enters debug mode (ARM Star core halted), the WWDT counter can continue to operate or stop according to the status of the DBG_WWDT@ DBGCR configuration bit. See the "Debug Interface" part for details.

11.3 IWDT Register

IWDT Module Register List (Base Address: 0x4000 2C00) Address Register Name Description 0x4000 2C00 CR Independent watchdog control register 0x4000 2C04 CLR Independent watchdog feeding register

11.3.1 Independent Watchdog Control Register (IWDT_CR)

Offset Address: 0x0000 Reset Value: 0x0000 7FFF b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 LOCK[15:0] WO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 IWDTO N IWDTPR[2:0] IWDTRLR[11:0] RW1t RW RW 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit Symbol Description 31 ~ 16 LOCK[15:0] Register lock bit 0x5AA5: Unlocks this register Other: Locks this register When configuring this register, the unlock bit must be input 0x5AA5 at the same time. After the operation is completed, it will be automatically locked. 0x0 will be fixedly read when reading this LOCK.

15 IWDTON Independent watchdog enable, this bit is set to '1' by software, but can

only be cleared by hardware after reset. This control bit is effective only when OP_IWDT=0101b. 0: IWDT is disabled 1: IWDT is enabled 14 ~ 12 IWDTPR[2:0] Independent watchdog clock pre-division setting 000: Pre-division factor = 4 001: Pre-division factor=8 010: Pre-division factor=16 011: Pre-division factor=32 (default) 100: Pre-division factor=64 101: Pre-division factor=128 110: Pre-division factor=256 111: Pre-division factor=512 11 ~ 0 IWDTRLR[11:0] Independent watchdog reload register Used to define the reload value of the watchdog counter. Note: The reset value of IWDTRLR[11:0] is 0x0FFF.

11.3.2 Independent Watchdog Feeding Register (IWDT_CLR)

Offset Address: 0x0004 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 IWDTCLR[15:0] WO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Symbol Description 31 ~ 16 Reserved - 15 ~ 0 IWDTCLR[15:0] Independent watchdog feeding register 0xAAAA: Feeds the dog (update the watchdog counter with IWDTRLR) Other: No action Reading this register after the dog is fed will fixedly return to 0x0.

11.4 WWDT Register

WWDT Module Register List (Base Address: 0x4000 3000) Address Register Name Description 0x4000 3000 CR Window watchdog control register 0x4000 3004 SR Window watchdog status register 0x4000 3008 CLR Window watchdog feeding register 0x4000 300C WTR Window watchdog window register

11.4.1 Window Watchdog Control Register (WWDT_CR)

Offset Address: 0x0000 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 LOCK[15:0] WO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 WWDT ON WWDT IE Reserved WWDTPR[2:0] WWDTRLR[7:0] RW1t RW - RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Symbol Description 31 ~ 16 LOCK[15:0] Register lock bit 0x5AA5: Unlocks this register Other: Locks this register When configuring this register, the unlock bit must be input 0x5AA5 at the same time. After the operation is completed, it will be automatically locked. 0x0000 will be fixedly read when reading this LOCK.

15 WWDTON Window watchdog enable, this bit is set to '1' by software, but can only

be cleared by hardware after reset. 0: WWDT is disabled 1: IWDT is enabled

14 WWDTIE Window watchdog latest dog feeding interrupt enable, this bit is set to ‘1’

and cleared by software. 0: WWDT is disabled 1: WWDT is enabled 13 ~ 11 Reserved - 10 ~ 8 WWDTPR[2:0] Window watchdog clock pre-division setting 000: Pre-division factor =1X256 001: Pre-division factor=2X256 010: Pre-division factor=4X256 011: Pre-division factor=8X256 100: Pre-division factor=16X256 101: Pre-division factor=32X256 110: Pre-division factor=64X256 111: Pre-division factor=128X256 7 ~ 0 WWDTRLR[7:0] Window watchdog reload register Used to define the reload value of the watchdog counter.

11.4.2 Window Watchdog Status Register (WWDT_SR)

Offset Address: 0x0004 Reset Value: 0x0000 00FF b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 WWDT IF Reserved TCNT[7:0] RW - RO 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Bit Symbol Description 31 ~ 16 Reserved -

15 WWDTIF Window watchdog latest dog feeding interrupt flag bit, this bit is set to ‘1’

by software or hardware, and cleared by software. 0: No WWDT interrupt is generated 1: A WWDT interrupt is generated 14 ~ 8 Reserved - 7 ~ 0 TCNT[7:0] Window watchdog count register Indicates the current watchdog count, set to maximum value 0xFF by default when initiated.

11.4.3 Window Watchdog Feeding Register (WWDT_CLR)

Offset Address: 0x0008 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 WWDTCLR[15:0] WO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Symbol Description 31 ~ 16 Reserved - 15 ~ 0 WWDTCLR[15:0] Window watchdog feeding register 0x5555: Feeds the dog (update the watchdog counter with WWDTRLR) Other: No action Reading this register after the dog is fed will fixedly return to 0x0.

11.4.4 Window Watchdog Window Register (WWDT_WTR)

Offset Address: 0x000C Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 LOCK[15:0] WO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Reserved WWDTWTR[7:0] - RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Symbol Description 31 ~ 16 LOCK[15:0] Register lock bit 0x5AA5: Unlocks this register Other: Locks this register When configuring this register, the unlock bit must be input 0x5AA5 at the same time. After the operation is completed, it will be automatically locked. 0x0000 will be fixedly read when reading this LOCK. 15 ~ 8 Reserved - 7 ~ 0 WWDTWTR[7:0] Window watchdog window value register Used to define the window value of the watchdog. This register has write protection, it can only be written when LOCK bit is 0x5AA5. No limit for reading.

1. CRC Calculation Unit

12.1 Introduction

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from an 8/16/32-bit data and configured polynomial. Among other applications, CRC-based techniques are used to verify data transmitting or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a software signature during runtime, to be compared with a reference signature generated at link-time and stored at a given memory location.

12.2 Main Features

 Supports various CRC polynomial (1) CRC-32: ( 0x04C11DB7) Polynomial: 1 245781011121622232632 ++++++++++++++ xxxxxxxxxxxxxx Polynomial: 1 21516 +++ xxx (3) CRC-CCITT: (0x1021) Polynomial: 1 51216 +++ xxx (4) CRC-8: (0x7): Polynomial: 1 +++ xxx  Provides CRC_INIT register to define first data in data register. When calculating CRC-16, the lower 16 bits of CRC_INIT are valid. When calculating CRC-8, the lower 8 bits of CRC_INIT are valid.  Configurable input/output data conversion, includes byte reversal, bit reversal in byte, and 1’s complement (bitwise NOT).  Supports 8/16/32-bit data input. If intput data is 8-bit then 8-bit data will be calculated. If intput data is 16-bit then 16-bit data will be calculated. If intput data is 32-bit then 32-bit data will be calculated. The bits of intput data is independent of the CRC format. The atom unit for calculating data is 8-bit, so if multi-byte data inputted, low byte in order will be calculated first.  CRC-8 computation done in 1 clock cycle, CRC-16 computation done in 2 clock cycles, CRC-32 computation done in 4 clock cycles .

12.3 Function Description

When calculating CRC, CRC_CR is firstly set according to the actual application. Then polynomial and CRC initial values required are set. After setting, RELOAD@CRC_CR needs to be written to ‘1’ to load the initial value into the CRC_DR register. Then register CRC_DR can be written to calculation and be read to get the result When writing, 8-bit, 16-bit and 32-bit data are allowed, but word alignment is required when writing/reading (4-byte alignment, which means it must be the address of CRC_DR), otherwise the result is unpredictable. Each write operation into the data register creates a combination of the previous CRC value and the new one. Therefore, when the input conversion is set to all 0s (which means no conversion is performed before written to data register), the CRC results obtained by writing 0x12345678 once and continuously writing 0x78, 0x56, 0x34, 0x12 are the same.

12.3.1 CRC Format Conversion Description

Since the data register operation can be 8-bit, 16-bit or 32-bit. Therefore, different processing will be carried out according to the difference of input data during calculating. Reading is only related to CRC Mode. Table12-1 Data Conversion Description 8-bit Writing Reading MODE COMPLW (Byte) RBITW (bit) RBYTEW (Byte) COMPLR (Byte) RBITR (bit) RBYTER (Byte) CRC_16 B0 = ~B0 b[0..7]=b[7..0] Ignore B0 = ~B0 B1=~B1 b[0..7]=b[7..0] b[8..15]=b[15..8] B0=B1’ B1=B0’ CRC_32 B0 = ~B0 b[0..7]=b[7..0] Ignore B0 = ~B0 B1 = ~B1 B2 = ~B2 B3 = ~B3 b[0..7]=b[7..0] b[8..15]=b[15..8] B0=B3’ B3=B0’ B1=B2’ B2=B1’ 16-bit Writing Reading MODE COMPLW RBITW RBYTEW COMPLR RBITR RBYTER CRC_8 B0 = ~B0 B1 = ~B1 b[0..7]=b[7..0] b[8..15]=b[15..8] B0=B1’ B1=B0’ B0 = ~B0 b[0..7]=b[7..0] Ignore CRC_16 B0 = ~B0 B1 = ~B1 b[0..7]=b[7..0] b[8..15]=b[15..8] B0=B1’ B1=B0’ B0 = ~B0 B1=~B1 b[0..7]=b[7..0] b[8..15]=b[15..8] B0=B1’ B1=B0’ CRC_32 B0 = ~B0 B1 = ~B1 b[0..7]=b[7..0] b[8..15]=b[15..8] B0=B1’ B1=B0’ B0 = ~B0 B1 = ~B1 B2 = ~B2 B3 = ~B3 b[0..7]=b[7..0] b[8..15]=b[15..8] B0=B3’ B3=B0’ B1=B2’ B2=B1’ 32-bit Writing Reading MODE COMPLW RBITW RBYTEW COMPLR RBITR RBYTER CRC_8 B0 = ~B0 B1 = ~B1 B2 = ~B2 B3 = ~B3 b[0..7]=b[7..0] b[8..15]=b[15..8] B0=B3’ B3=B0’ B1=B2’ B2=B1’ B0 = ~B0 b[0..7]=b[7..0] Ignore CRC_16 B0 = ~B0 B1 = ~B1 B2 = ~B2 B3 = ~B3 b[0..7]=b[7..0] b[8..15]=b[15..8] B0=B3’ B3=B0’ B1=B2’ B2=B1’ B0 = ~B0 B1=~B1 b[0..7]=b[7..0] b[8..15]=b[15..8] B0=B1’ B1=B0’ CRC_32 B0 = ~B0 B1 = ~B1 B2 = ~B2 B3 = ~B3 b[0..7]=b[7..0] b[8..15]=b[15..8] B0=B3’ B3=B0’ B1=B2’ B2=B1’ B0 = ~B0 B1 = ~B1 B2 = ~B2 B3 = ~B3 b[0..7]=b[7..0] b[8..15]=b[15..8] B0=B3’ B3=B0’ B1=B2’ B2=B1’

12.3.2 Configuration of Common Formats

(1) Configuration of CRC32 (0x04C11DB7) 245781011121622232632 ++++++++++++++ xxxxxxxxxxxxxx CRC_INIT : 0xFFFFFFFF CRC_CR.MODE : 0 CRC_CR.RBITW : 0 CRC_CR.RBYTEW : 0 CRC_CR.COMPLW : 0 CRC_CR.RBITR : 0 CRC_CR.RBYTER : 0 CRC_CR.COMPLR : 0 Input: 8-bit: Calculate 1 byte at a time 16-bit: Calculate 2 bytes at a time, low byte first 32-bit: Calculate 4 bytes at a time, low byte first CRC result: all 32-bit of CRC_DR

(2) Configuration of CRC16 (0x8005) 21516 +++ xxx CRC_INIT : 0xFFFF CRC_CR.MODE : 1 CRC_CR.RBITW : 0 CRC_CR.RBYTEW : 0 CRC_CR.COMPLW : 0 CRC_CR.RBITR : 0 CRC_CR.RBYTER : 0 CRC_CR.COMPLR : 0 Input: 8-bit: Calculate 1 byte at a time 16-bit: Calculate 2 bytes at a time, low byte first 32-bit: Calculate 4 bytes at a time, low byte first CRC result: low 16-bit of CRC_DR (3) Configuration of CRC16-CITT (0x1021) 51216 +++ xxx CRC_INIT : 0xFFFF CRC_CR.MODE : 2 CRC_CR.RBITW : 0 CRC_CR.RBYTEW : 0 CRC_CR.COMPLW : 0 CRC_CR.RBITR : 0 CRC_CR.RBYTER : 0 CRC_CR.COMPLR : 0 Input: 8-bit: Calculate 1 byte at a time 16-bit: Calculate 2 bytes at a time, low byte first 32-bit: Calculate 4 bytes at a time, low byte first CRC result: low 16-bit of CRC_DR (4) Configuration of CRC8 (0x7) +++ xxx CRC_INIT : 0xFF CRC_CR.MODE : 3 CRC_CR.RBITW : 0 CRC_CR.RBYTEW : 0 CRC_CR.COMPLW : 0 CRC_CR.RBITR : 0 CRC_CR.RBYTER : 0 CRC_CR.COMPLR : 0 Input: 8-bit: Calculate 1 byte at a time 16-bit: Calculate 2 bytes at a time, low byte first 32-bit: Calculate 4 bytes at a time, low byte first CRC result: low 8-bit of CRC_DR

12.4 CRC Register

CRC Module Register List (Base Address: 0x4004 1800) Address Register Name Description 0x4004 1800 DR CRC data register 0x4004 1804 CR CRC control register 0x4004 1808 INIT CRC initial value register

12.4.1 CRC data register (CRC_DR)

Offset Address: 0x0000 Reset Value: 0xFFFF FFFF b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 DR[31:0] RW 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 DR[31:0] RW 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit Symbol Description 31 ~ 0 DR[31:0] 1. Used as an input register when writing new data to the CRC calculator. 2. Holds the previous CRC calculation result when it is read 3. 8-bit, 16-bit, and 32-bit written operations are allowed

12.4.2 CRC Control Register (CRC_CR)

Offset Address: 0x0004 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 RBYTE R RBITR COMP LR RBYTE W RBITW COMP LW MODE[1:0] Reserved RELO AD RW RW RW RW RW RW RW - WO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Symbol Description 31 ~ 16 Reserved - 15 RBYTER Reverses the byte order of the data in DR and then read. 0: Remains unchanged 1: Reverses byte order (refer to Table 12-1 for detailed conversion) 14 RBITR Reverses the byte inner bit order of the data in DR and then read. 0: Remains unchanged 1: Reverses byte inner bit order (refer to Table 12-1 for detailed conversion) 13 COMPLR Does a 1's complement transformation to the data in DR and then read. (i.e. do bitwise inversion to the read data) 0: Remains unchanged 1: Does a 1's complement transformation

12 RBYTEW Reverses the byte order of the written data

0: Remains unchanged 1: Reverses byte order (refer to Table 12-1 for detailed conversion)

11 RBITW Reverses the byte inner bit order of the written data. 0: Remains unchanged 1: Reverses byte inner bit order (refer to Table 12-1 for detailed conversion) 10 COMPLW Does a 1's complement transformation to the written data. 0: Remains unchanged 1: Does a 1's complement transformation 9 ~ 8 MODE[1:0] CRC mode selection, because of the inverse algorithm is used, the actual value of the polynomial is bitwise reversed. 00: CRC-32 (0x04C11DB7) 01: CRC-16 (generator polynomial is 0x8005) 10: CRC-CITT (generator polynomial is0x1021) 11: CRC-8 (generator polynomial is0x7) 7 ~ 1 Reserved -

0 RELOAD Reloads the initial value into the data register

1: Writes 1 to reload. Reload INIT@CRC_INIT into the DR@CRC_DR register and other register values remain unchanged. 0: Writes 0 to remain unchanged, this Bit cannot be read, and it is always 0.

12.4.3 CRC Initial Value Register (CRC_INIT)

Offset Address: 0x0008 Reset Value: 0xFFFF FFFF b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 INIT[31:0] RW 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 INIT[31:0] RW 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit Symbol Description 31 ~ 0 INIT[31:0] Stores initial value of CRC. After writing 1 to RELOAD@CRC_CR, this value is automatically loaded into the DR@CRC_DR register. MODE=0: 32-bit valid MODE=1: Lower 16-bit valid MODE=2: Lower 16-bit valid MODE=3: Lower 8-bit valid

1. General-Purpose I/O (GPIO)

13.1 Introduction

SH33F2801 provides up to 45 general-purpose I/O ports, divided into five groups of ports (A to C), each group contains up to 16 input/output pins, and has separate configuration registers and data registers. For SH33F2801, each I/O port has alternate functions, some alternate with the digital peripherals on chip, some alternate with analog peripherals on chip, and some alternate with external interrupt and debug interfaces. All I/Os support pull-up and push-pull, and some of them support open-drain output.

13.2 Main Features

 All port groups are mounted on the AHB bus, supporting fast input and output  Input/output direction control  Input pin can be configured with weak pull-up  Output pin can be configured as push-pull, and some of them can be configured as open-drain.  All ports support per-bit set/reset operation  All Ports support per-byte read/write operation  some ports can be used as external interrupt input, with trigger edge settable (configure in EXTI part)  I/O port can be configured as normal input/output function or digital peripheral function or analog peripheral function  I/O port alternate function uses multiplexers, which can only be configured as one function at a time.  Allows Reading pin status when I/O port is alternated as digital peripheral function  I/O port supports alternate function remapping to other pin  Supports port configuration lock function Bit set/reset registers Output data register Input data register Read Write Read/write From on-chip peripheral Digital function input On/off Analog To on-chip peripheral Digital function output Output control P-MOS N-MOS VDD VSS VDD VSS VDD I/O PIN Protection diode Protection diode Pull up Analog On/off On/off Push-pull, Open-drain Input channel Output channel Schmitt trigger Figure13-1 I/O Port Basic Structure Block Diagram

13.3 Function Description

Each I/O port configuration is completed via four basic configuration registers (MODER, OTYPER, ODRVR, PUPDR) for configuring I/O input/output mode (direction), output push-pull/open-drain mode, refunction selection, and port pull up properties. The basic working mode of the I/O port is shown in the following table: Table13-1 I/O Port Basic Working Mode List Port Function AFRL/AFRH MODER OTYPE I/O Attribute All off AF0 (default) - - Input & output all turned off Note 1 GPIO AF1 0 - GPIO input

0 GPIO push-pull

peripherals AF6/7 - - Analog input/output Note 3 System Interface - - - SWD/XTAL Note 4 In this table, x means don’t care. Note 1: After the startup completing, the default status is input floating (high resistance) status. Note 2: The input and output configuration of the digital peripheral is bound to the peripheral. After enabling a digital peripheral alternate function, the user only needs to configure the OTYPE and PUPDR registers. Note 3: The input/output configuration of the Analog peripherals is bound to the peripherals and does not need to configure the MODER and OTYPE registers. PUPDR is allowed for special applications that provide weak pull up capabilities for analog ports. Note 4: The port is used as system port, which includes the debug interface SWJ and the external oscillator interface XTAL, a total of 4 ports. System port can also be alternated as GPIO or digital peripheral interfaces. However, the above basic configuration registers are invalid when they’re used as system port. These two interfaces are further described in SYSCFG. All ports are push-pull by default, only TWI ports support push-pull/open-drain mode, as following table. For ports that do not support open-drain, the open-drain selector of the OTYPE register is invalid and fixed as push-pull. Table13-2 The ports with open-drain mode I/O Alternate Function PA0 SCL PA2 SDA PA13 (SDA) PA14 (SCL)

13.3.1 Default Configuration of I/O Pins

During reset and after reset, the I/O port function is configured as “GPIO floating input” function, except for the SWJ interface. After system reset, SWD interface is selected as the default function. In order to ensure proper entry into the debug mode, it is necessary to keep the SWD port as non-floating status. To achieve this, the corresponding SWD pins are set as follows after reset:  SWDIO: input pull-up  SWCLK: input pull-down Once the SWD interface is released by the user code (see control bit SWDCFG@SYSCFG_SAFR), the software can use these I/O ports as general purpose I/O ports. Unlike the SWD interface, the external oscillator interface XTAL1/XTAL2 is GPIO function by default. The XTAL interface attribute needs to be turned on by the user code (see control bit OSCCFG@SYSCFG_SAFR).

13.3.2 I/O Control Register

Each I/O port has four 32-bit registers for configuring the working modes: MODER, OTYPER, PUPDR and AFR. MODER: set input and output direction; OTYPER: set the output type, which are push-pull output and open-drain output (just for individual pins); PUPDR: set internal weak pull-up. This register can be set during input and output. AFR: Set the Alternate Function. There are altogether 8 options AF0 ~ AF7, as detailed in the "Alternate Mapping table". The system interface does not belong to AFR setting.

13.3.3 I/O Data Register

Each GPIO port has two 16-bit data registers: IDR, ODR. IDR: input data register, read access to the input data register can get I/O status ODR: output data register, the value written to the output data register (ODR) is output to the corresponding I/O pin..

13.3.4 I/O Bit Set And Bit Reset

Bit set and reset register (BSRR) is a 32-bit register that allows each bit of the Output Register (ODR) to be independently set and cleared (reset). The lower 16 bits of the BSRR are set operations, and the higher 16 bits are reset operations, allowing simultaneous set and reset operations on different I/O ports in a single slot of AHB write operation. If set and reset the same I/ O port at the same time, the set operation has higher priority. The reading and writing of BSRR can be word, half-word or byte. The following example shows how to use word access to simultaneously switch two I/O ports in the same level or opposite level: ；Switch PA.0 and PA.1 simultaneously in the same level GPIOA_BSRR = 0x00000003 GPIOA_BSRR = 0x00030000 ；Switch PA.0 and PA.1 simultaneously in the opposite level GPIOA_BSRR = 0x00020001 GPIOA_BSRR = 0x00010002 If half-word is used to achieve switching simultaneously in the same level with half-word, the method is as follows: #define GPIOA_BitSet_ADDR = 0xXX ; point to the base address of GPIO_BSRR_A (used to set) #define GPIOA_BitReset_ADDR = 0xXX + 2; point to the high half-word offset address of GPIO_BSRR_A (used to reset) *(u16*) GPIOA_BitSet_ADDR = 0x03 *(u16*) GPIOA_BitReset_ADDR = 0x03 The bit operation of BSRR on ODR is a single operation, BSRR control bit will be automatically cleared by hardware, and the corresponding bit of ODR will be modified simultaneously. Also, BSRR is an ‘atom’ operation, user can execute BSRR operation and ODR operation successively, and two operations will be effective on I/O port sequentially..

13.3.5 I/O Locking Mechanism

The locking mechanism allows freezing the IO configuration. The lockable registers are: OTYPER, PUPDR and AFR. Each lock bit LCKy is used to lock an I/O port. Writing lock bit also needs to write a special control word (0x5AA5) to the corresponding unlock field (LOCK).

13.3.6 I/O Configured as External Interrupt/Wake-up Line

All ports can be selected to connect to the external interrupt input line via the external interrupt configuration register (EXTI_CFG, in the EXTI module). In order to use an external interrupt line, the port needs to be configured in input mode. For more information on external interrupts, see the "External Interrupt/Event Controller (EXTI)" part.

13.3.7 TTL Input Selection

Some pins support TTL level inputs for reliable receiving of external 3V TTL input signals. SH33F2801 provides 10 TTL level input ports, which are turned on correspondingly by the TTL configuration register (GPIOx_ TTLEN). Table13-3 The ports with TTL Input mode I/O口 Alternate Function PA0 RXD2/SCL PA2 TXD2/SDA PA6 RXD2/PCA0B PA9 TXD2/PCA0A PA11 RXD0/PCA0C PA12 TXD0/PCA1A PA13 RXD1/PCA1B PA14 TXD1/PCA1C PC0 TXD1 PC1 RXD1

13.3.8 I/O Alternate Function

The registers AFRL and AFRH define the port's alternate function (multiplexing function), allowing the same port to act as a shared input/output port for multiple multiplexing functions. Each port has a 8-input I/O multiplex selector for selecting the desired alternate function, which means only one peripheral connection is allowed per port at the same time. The 8 channels of multiplex selector (AF0 to AF7) are divided into 4 categories:  AF0: input and output all turned off  AF1: GPIO basic functions (default);  AF2～AF6: digital peripheral alternate function;  AF6/7: analog peripheral alternate function; Input and output all turned off channel: AF0 This is the default configuration after the I/O port is powered on and reset. This channel is a special state that forces input and output channels of the port to be closed, but pull-up and pull-down are also allowed. GPIO basic channel: AF1 All I/O ports are configured to GPIO input floating state, except for the SWD interface. If the pull-up is not enabled, the default is the float state. The SWD interface pin can be used as the AF1 function only after the SWJ-DP interface is closed by SWJCFG@SYSCFG_SAFR. Digital peripheral alternate channel: AF2 ~ AF6 The input and output attribute (MODER) of digital peripheral alternate function is automatically set by hardware, but the output type (OTYPE), pull-up (PUPDR) and channel selection (AFR) parameters require user software configuration. See the “Alternate Function Mapping Table” in “Section 4” for complete mapping information.. Analog peripheral alternate channel: AF6/7 This channel is used for analog peripherals on chip. Input and output attribute, output types, and output driver configurations are meaningless, but the mode of pull-up is allowed. The analog channel turns off the output buffer and the input Schmitt trigger, which equals to disconnecting the digital input and output channels to avoid leakage.

13.3.9 GPIO Input Function(AF1)

When I/O port is configured as a GPIO input:  Input is valid  Output is invalid (note)  Pull-up and pull-down resistors are connected or disconnected depending on pull-up and pull-down configuration.  I/O status can be obtained by read access to the input data register. The figure below shows the GPIO input configuration of the I/O port bits. Bit set/reset registers Output data register Input data register Read Write Read/write on VDD VSS VDD I/O PIN Protection diode Protection diode Pull up On/off Input driver Output driver Schmitt Figure13-2 GPIO Input Configuration of I/O Port Bits Block Diagram

13.3.10 GPIO Output Function (AF1)

When the I/O port is configured as a GPIO output:  Output is valid - Open-drain mode: '0' on the output register activates N-MOS, while '1' on the output register places the port in a high-resistance state (P-MOS inactive). - Push-pull mode: '0' on the output register activates N-MOS, while '1' on the output register activates P-MOS.  Input is valid  Pull-up and pull-down resistors are connected or disconnected depending on pull-up and pull-down configuration.  I/O status can be obtained by read access to the input data register (note).  The last written value is obtained by read access to the output data register. The figure below shows the GPIO output configuration for the I/O port bits. Bit set/reset registers Output data register Input data register Read Write Read/write On Output control P-MOS N-MOS VDD VSS VDD VSS VDD I/O PIN Protection diode Protection diode Pull up On/off Push-pull or Open-drain Input driver Output driver Schmitt Figure13-3 GPIO Output Configuration Block Diagram

13.3.11 Digital Alternate Function (AF2-AF6)

When the I/O port is configured for digital multiplexing:  The output buffer is turned off as digital multiplexing input.  The output buffer is turned on as digital multiplexed output (disconnect GPIO output data register).  Digitally multiplexed input or output attributes are determined by peripheral and are automatically configured when the function is activated.  The input channel is open no matter it is input or output.  Pull-up and pull-down resistors are connected or disconnected depending on the pull-up and pull-down configuration.  I/O port status is available when reading the input data register. The following figure shows the I/O port bit digital multiplexing function configuration: Bit set/reset registers Output data register Input data register Read Write Read/write From on-chip peripheral Alternate function input On To on-chip peripheral Alternate function output Output control P-MOS N-MOS VDD VSS VDD VSS VDD I/O PIN Protection diode Protection diode Pull up On/off Push-pull or Open-drain Input driver Output driver Schmitt Figure13-4 Digital Alternate Function Configuration Block Diagram If software configures an I/O pin as a digital multiplexed output function, but the peripheral is not activated, the output buffer is turned off and the output channel is in high-resistance state. Of course, the user can give a certain level by configuring pull-up or pull-down.

13.3.12 Analog Alternate Function (AF6/AF7)

When the I/O port is configured for analog multiplexing:  The output buffer is disabled;  Automatically turn off the Schmitt trigger input to achieve zero consumption on each analog I/O pin, and the Schmitt trigger output value is forced to '0';  When reading the input data register, the value is '0';  Allow turn on pull-up or pull-down The following figure shows the analog multiplexing configuration of the I/O port bits: Bit set/reset registers Output data register Input data register Read Write Read/write From on-chip peripheral off AnalogTo on-chip peripheral VDD VSS VDD I/O PIN Protection diode Protection diode Pull up Analog On/off Input driver Schmitt Figure13-5 Analog Alternate Function Configuration Block Diagram

13.3.13 Turn off All Function (AF0)

This function is a special state of the I/O port. By cutting off the input channel and the output channel enable bit, the leakage problem caused by the misconfiguration of the I/O port can be eliminated, which means for the sake of simplicity, the unused I/O port can be configured to be fully turned off. During power-on reset, all I/O ports except SWD are in turn-off-all state.

13.4 Register

GPIO Module Register List (Base Address: 0x4004 0000) Address Register List Description 0x4004 0000+ 0x080*x+0x000 MODER Port x mode configuration (X represents ports A, B and C, and corresponding values are 0, 1 and 2 in the calculation of offset address, the same below) 0x4004 0000+ 0x080*x+0x004 IDR Port x input data register (Ports A to C correspond to x: 0 to 4) 0x4004 0000+ 0x080*x+0x008 ODR Port x output data register (Ports A to C correspond to x: 0 to 4) 0x4004 0000+ 0x080*x+0x00C BSRR Port x clear/reset register (Ports A to C correspond to x: 0 to 4) 0x4004 0000+ 0x080*x+0x010 LCKR Port x configuration lock register (Ports A to C correspond to x: 0 to 2) 0x4004 0000+ 0x080*x+0x014 IE Port x input enable register 0x4004 0000+ 0x080*x+0x018 OTYPER Port x output type configuration register (Ports A to C correspond to x: 0 to 4) 0x4004 0000+ 0x080*x+0x01C ODRVR Port x output driver configuration register (Ports A to C correspond to x: 0 to 4) 0x4004 0000+ 0x080*x+0x020 PUPDR Port x pull-up & pull-down configuration register (Ports A to C correspond to x: 0 to 2) 0x4004 0000+ 0x080*x+0x024 TTLEN Port x partial pin TTL level selection register (Ports A to C correspond to x: 0 to 2) 0x4004 0000+ 0x080*x+0x028 AFRL Port x alternate function register low bit (Ports A to C correspond to x: 0 to 2) 0x4004 0000+ 0x080*x+0x02C AFRH Port x alternate function register high bit (Ports A to C correspond to x: 0 to 2)

13.4.1 Port X Mode Configuration (GPIOx_IOD_MODER)

Offset Address: 0x0000 + 0x80*x Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 MOD ER1 MOD ER1 MOD ER1 MOD ER1 MOD ER1 MOD ER1 MOD ER9 MOD ER8 MOD ER7 MOD ER6 MOD ER5 MOD ER4 MOD ER3 MOD ER2 MOD ER1 MOD ER0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Symbol Description 31 ~ 16 Reserved -

15 MODER15 Port x mode configuration is configured by software

0: Input mode (reset state) 1: Output mode

14 MODER14 Port x mode configuration is configured by software

0: Input mode (reset state) 1: Output mode

13 MODER13 Port x mode configuration is configured by software

0: Input mode (reset state) 1: Output mode

12 MODER12 Port x mode configuration is configured by software

0: Input mode (reset state) 1: Output mode

11 MODER11 Port x mode configuration is configured by software

0: Input mode (reset state) 1: Output mode

10 MODER10 Port x mode configuration is configured by software

0: Input mode (reset state) 1: Output mode

9 MODER9 Port x mode configuration is configured by software

0: Input mode (reset state) 1: Output mode

8 MODER8 Port x mode configuration is configured by software

0: Input mode (reset state) 1: Output mode

7 MODER7 Port x mode configuration is configured by software

0: Input mode (reset state) 1: Output mode

6 MODER6 Port x mode configuration is configured by software

0: Input mode (reset state) 1: Output mode

5 MODER5 Port x mode configuration is configured by software

0: Input mode (reset state) 1: Output mode

4 MODER4 Port x mode configuration is configured by software

0: Input mode (reset state) 1: Output mode

3 MODER3 Port x mode configuration is configured by software

0: Input mode (reset state) 1: Output mode

2 MODER2 Port x mode configuration is configured by software

0: Input mode (reset state) 1: Output mode

1 MODER1 Port x mode configuration is configured by software

0: Input mode (reset state) 1: Output mode

0 MODER0 Port x mode configuration is configured by software

0: Input mode (reset state) 1: Output mode

13.4.2 Port X Input Data Register (GPIOx_ IDR)

Offset Address: 0x0004 + 0x80*x Reset Value: 0x0000 XXXX b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 IDRy(y=15~0) RO X X X X X X X X X X X X X X X X Bit Symbol Description 31 ~ 16 Reserved - 15 ~ 0 IDRy(y=15~0) Port x input data register This register is read-only and stores the level value read by the port.

13.4.3 Port X Output Data Register (GPIOx_ ODR)

Offset Address: 0x0008 + 0x80*x Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 ODRy(y=15~0) RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Symbol Description 31 ~ 16 Reserved - 15 ~ 0 ODRy(y=15~0) Port x output data register This register can be read and written by software. Through the BSRR register after it, the ODR can be bit-set and reset independently to implement atomic bit operations.

13.4.4 Port X Clear/Reset Register (GPIOx_BSRR)

Offset Address: 0x000C + 0x80*x Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 BRy(y=15~0) WO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 BSy(y=15~0) WO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Symbol Description 31 ~ 16 BRy(y=15~0) Port x reset bit These bits are writed only, reading these bits returns 0x0000. 0: No effect 1: Clears the corresponding IDRy bit Note: If the BRy and BSy of the same port are set at the same time, the BSy priority is higher. 15 ~ 0 BSy(y=15~0) Port x set bit These bits are writed only, reading these bits returns 0x0000. 0: No effect 1: Resets the corresponding IDRy bit Note: If the same BRy and BSy of the same port are set at the same time, the BSy priority is higher.

13.4.5 Port X Configuration Lock Register (GPIOx_ LCKR)

Offset Address: 0x0010 + 0x80*x Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 LOCK[15:0] WO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 LCKy(y=15~0) RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Symbol Description 31 ~ 16 LOCK[15:0] LCK control bit operation unlock bit These bits are write only, and reading these bits returns 0x0000. 0x5AA5: Unlock Other: Lock 15 ~ 0 LCKy(y=15~0) Port x lock bit These bits are readable and writable, and writing to these bits must satisfy the LOCK unlock condition (not required for reading) 0: Port bit configuration is unlocked 1: Port bit configuration is locked

13.4.6 Port X Input Enable Register (GPIOx_IE)

Offset Address: 0x0014 + 0x080*x Reset Value: 0x0000 FFFF b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 IE15 IE14 IE13 IE12 IE11 IE10 IE9 IE8 IE7 IE6 IE5 IE4 IE3 IE2 IE1 IE0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit Sign Description 31 ~ 16 Reserved - 15 ~ 0 IEy(y=15~0) Portx Input Enable Bit 0: Input Disable 1: Input Enable(default)

13.4.7 Port X Output Type Configuration Register (GPIOx_OTYPER)

Offset Address: 0x0018 + 0x080*x Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Rese rved OT1 OT1 Reserved OT2 Rese rved OT0 - RW RW - RW - RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

31 ~ 15 Reserved -

14 OT14 Port PA14 output type configuration is configured by software

0: Outputs push-pull(reset state) 1: Outputs open-drain

13 OT13 Port PA13 output type configuration is configured by software

0: Outputs push-pull(reset state) 1: Outputs open-drain 12 ~ 3 Reserved -

2 OT2 Port PA2 output type configuration is configured by software

0: Outputs push-pull(reset state) 1: Outputs open-drain

1 Reserved -

0 OT0 Port PA0 output type configuration is configured by software

0: Outputs push-pull(reset state) 1: Outputs open-drain Note: The OT property is only available in the four ports of PA, and the register is meaningless in PB and PC ports (address space is reserved, but registers do not exist).

13.4.8 Port X Output Driver Configuration Register (GPIOx_ODRVR)

Offset Address: 0x001C + 0x080*x Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 0 Reserved -

13.4.9 Port X Pull-up Configuration (GPIOx_PUPDR)

Offset Address: 0x0020 + 0x080*x Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Rese rved PHD R15 Rese rved PHD R14 Rese rved PHD R13 Rese rved PHD R12 Rese rved PHD R11 Rese rved PHD R10 Rese rved PHD Rese rved PHD - RW - RW - RW - RW - RW - RW - RW - RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Rese rved PHD Rese rved PHD Rese rved PHD Rese rved PHD Rese rved PHD Rese rved PHD Rese rved PHD Rese rved PHD - RW - RW - RW - RW - RW - RW - RW - RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

31 Reserved -

30 PHDR15 Port x pull-up configuration is configured by software

0: No pull-up (reset state) 1: Pull-up

29 Reserved -

28 PHDR14 Port x pull-up configuration is configured by software

0: No pull-up (reset state) 1: Pull-up

27 Reserved -

26 PHDR13 Port x pull-up configuration is configured by software

0: No pull-up (reset state) 1: Pull-up

25 Reserved -

24 PHDR12 Port x pull-up configuration is configured by software

0: No pull-up (reset state) 1: Pull-up

23 Reserved -

22 PHDR11 Port x pull-up configuration is configured by software

0: No pull-up (reset state) 1: Pull-up

21 Reserved -

20 PHDR10 Port x pull-up configuration is configured by software

0: No pull-up (reset state) 1: Pull-up

19 Reserved -

18 PHDR9 Port x pull-up configuration is configured by software

0: No pull-up (reset state) 1: Pull-up

17 Reserved -

16 PHDR8 Port x pull-up configuration is configured by software

0: No pull-up (reset state) 1: Pull-up

15 Reserved -

14 PHDR7 Port x pull-up configuration is configured by software

0: No pull-up (reset state) 1: Pull-up

12 PHDR6 Port x pull-up configuration is configured by software

0: No pull-up (reset state) 1: Pull-up

11 Reserved -

10 PHDR5 Port x pull-up configuration is configured by software

0: No pull-up (reset state) 1: Pull-up

8 PHDR4 Port x pull-up configuration is configured by software

0: No pull-up (reset state) 1: Pull-up

6 PHDR3 Port x pull-up configuration is configured by software

0: No pull-up (reset state) 1: Pull-up

4 PHDR2 Port x pull-up configuration is configured by software

0: No pull-up (reset state) 1: Pull-up

3 Reserved -

2 PHDR1 Port x pull-up configuration is configured by software

0: No pull-up (reset state) 1: Pull-up

0 PHDR0 Port x pull-up configuration is configured by software

0: No pull-up (reset state) 1: Pull-up

13.4.10 Port X Partial Pin TTL Level Selection Register (GPIOBx_TTLEN)

Offset Address: 0x0024 + 0x080*x Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Rese rved TTL EN1 TTL EN1 TTL EN1 TTL EN1 Rese rved TTL EN9 Reserved TTL EN6 Reserved TTL EN2 TTL EN1 TTL EN0 - RW RW RW RW - RW - RW - RW RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 15 Reserved -

14 TTLEN14 PA14 pin TTL/CMOS input selection

0: Selects CMOS input 1: Selects TTL input See “Electrical Characteristics” for TTL parameters, nothing will be done in stop mode.

13 TTLEN13 PA13 pin TTL/CMOS input selection

0: Selects CMOS input 1: Selects TTL input See “Electrical Characteristics” for TTL parameters, nothing will be done in stop mode.

12 TTLEN12 PA12 pin TTL/CMOS input selection

0: Selects CMOS input 1: Selects TTL input See “Electrical Characteristics” for TTL parameters, nothing will be done in stop mode.

11 TTLEN11 PA11 pin TTL/CMOS input selection

0: Selects CMOS input 1: Selects TTL input See “Electrical Characteristics” for TTL parameters, nothing will be done in stop mode.

10 Reserved -

9 TTLEN9 PA9 pin TTL/CMOS input selection

0: Selects CMOS input 1: Selects TTL input See “Electrical Characteristics” for TTL parameters, nothing will be done in stop mode.

8 ~ 7 Reserved -

6 TTLEN6 PA6 pin TTL/CMOS input selection

0: Selects CMOS input 1: Selects TTL input See “Electrical Characteristics” for TTL parameters, nothing will be done in stop mode. 5 ~ 3 Reserved -

2 TTLEN2 PA2 pin TTL/CMOS input selection

0: Selects CMOS input 1: Selects TTL input See “Electrical Characteristics” for TTL parameters, nothing will be done in stop mode.

0 TTLEN0 PA0 pin TTL/CMOS input selection

0: Selects CMOS input 1: Selects TTL input See “Electrical Characteristics” for TTL parameters, nothing will be done in stop mode. Note: The TTL input attribute is not available on every port. For details, see “TTL input selection” in SYSCFG part. The PA port is described here.

13.4.11 Port X Alternate Function Selection (GPIOx_AFRL)

Offset Address: 0x0028 + 0x080*x Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Rese rved AFR7[2:0] Rese rved AFR6[2:0] Rese rved AFR5[2:0] Rese rved AFR4[2:0] - RW - RW - RW - RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Rese rved AFR3[2:0] Rese rved AFR2[2:0] Rese rved AFR1[2:0] Rese rved AFR0[2:0] - RW - RW - RW - RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 30 ~ 28 AFR7[2:0] Port x alternate function selection is configured by software 000: AF0 001: AF1 010: AF2 011: AF3 100: AF4 101: AF5 110: AF6 111: AF7 26 ~ 24 AFR6[2:0] Port x alternate function selection is configured by software 000: AF0 001: AF1 010: AF2 011: AF3 100: AF4 101: AF5 110: AF6 111: AF7

22 ~ 20 AFR5[2:0] Port x alternate function selection is configured by software 000: AF0 001: AF1 010: AF2 011: AF3 100: AF4 101: AF5 110: AF6 111: AF7 18 ~ 16 AFR4[2:0] Port x alternate function selection is configured by software 000: AF0 001: AF1 010: AF2 011: AF3 100: AF4 101: AF5 110: AF6 111: AF7 14 ~ 12 AFR3[2:0] Port x alternate function selection is configured by software 000: AF0 001: AF1 010: AF2 011: AF3 100: AF4 101: AF5 110: AF6 111: AF7 10 ~ 8 AFR2[2:0] Port x alternate function selection is configured by software 000: AF0 001: AF1 010: AF2 011: AF3 100: AF4 101: AF5 110: AF6 111: AF7 6 ~ 4 AFR1[2:0] Port x alternate function selection is configured by software 000: AF0 001: AF1 010: AF2 011: AF3 100: AF4 101: AF5 110: AF6 111: AF7 2 ~ 0 AFR0[2:0] Port x alternate function selection is configured by software 000: AF0 001: AF1 010: AF2 011: AF3 100: AF4 101: AF5 110: AF6 111: AF7

13.4.12 Port X Alternate Function Selection (GPIOx_AFRH)

Offset Address: 0x002C + 0x080*x Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Rese rved AFR15[2:0] Rese rved AFR14[2:0] Rese rved AFR13[2:0] Rese rved AFR12[2:0] - RW - RW - RW - RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Rese rved AFR11[2:0] Rese rved AFR10[2:0] Rese rved AFR9[2:0] Rese rved AFR8[2:0] - RW - RW - RW - RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 30 ~ 28 AFR15[2:0] Port x alternate function selection is configured by software 000: AF0 001: AF1 010: AF2 011: AF3 100: AF4 101: AF5 110: AF6 111: AF7 26 ~ 24 AFR14[2:0] Port x alternate function selection is configured by software 000: AF0 001: AF1 010: AF2 011: AF3 100: AF4 101: AF5 110: AF6 111: AF7 22 ~ 20 AFR13[2:0] Port x alternate function selection is configured by software 000: AF0 001: AF1 010: AF2 011: AF3 100: AF4 101: AF5 110: AF6 111: AF7 18 ~ 16 AFR12[2:0] Port x alternate function selection is configured by software 000: AF0 001: AF1 010: AF2 011: AF3 100: AF4 101: AF5 110: AF6 111: AF7

14 ~ 12 AFR11[2:0] Port x alternate function selection is configured by software 000: AF0 001: AF1 010: AF2 011: AF3 100: AF4 101: AF5 110: AF6 111: AF7 10 ~ 8 AFR10[2:0] Port x alternate function selection is configured by software 000: AF0 001: AF1 010: AF2 011: AF3 100: AF4 101: AF5 110: AF6 111: AF7 6 ~ 4 AFR9[2:0] Port x alternate function selection is configured by software 000: AF0 001: AF1 010: AF2 011: AF3 100: AF4 101: AF5 110: AF6 111: AF7 2 ~ 0 AFR8[2:0] Port x alternate function selection is configured by software 000: AF0 001: AF1 010: AF2 011: AF3 100: AF4 101: AF5 110: AF6 111: AF7

1. System Configuration Module (SYSCFG) This module is used for related configuration on system level, including PWR configuration, SAFR special multiplexing function definition, CRAM lock definition, DBG control. The module is attached to the AHB bus and has independent enable and reset control.

14.1 System Configuration Correlation

14.1.1 PWR Configuration

Here is only the configuration of the BOD and its switch control, including two registers: the PWRCR and PWRSR. For details, see "Power-Down Detection" part.

14.1.1.1 NMI Exception Source Switch

NMI is a non-maskable interrupt. SH33F2801 provides three NMI exception sources: clock exception CSM, brownout detection BOD, and external interrupt (only EXTI 0 valid). Each source has a separate NMI enabled control. After the NMI is enabled, the interrupt path of the original exception source is not affected. For example, the interrupt paths of the BOD and EXTI0 themselves are also effective. Of course, the priority of the NMI is higher.

14.1.1.2 SWD & XTAL Pin Multiplexing Function Definition

The SWD interface is a two-wire SWD interface, and it can be configured as a GPIO port through SWJCFG@SYSCFG_SAFR. Once the configuration is complete, it can only be back to the debug interface state by resetting (note). Note: If SWD interfaces are all configured as GPIO ports, if connecting the debugger again is required after power off, NRST pin need to be short pressed (pin reset) in SWD interface mode to enter. Note: The SWD interface enters debug mode at system power-on and has a default pull up and pull-down attribute. When multiplexing to GPIO output, pay attention to the influence of power level at system power-on. But it is okay to be multiplexed to GPIO input. The external oscillator pins XTAL1 and XTAL2 are used as GPIO interfaces by default. They can be configured as external oscillator interface or external clock interface through OSCCFG@SYSCFG_SAFR. Once configured, they can only be back to the default interface state by reset. When SWD interface and XTAL interface are used as non-GPIO interfaces, the GPIO configuration parameters are invalid (can be written but have no effect), including input & output, pull-up and other configurations.

14.1.2 Debug Interface Register

DBGCR is the debug interface register. The working status of each major peripheral module in debug mode and the system state when entering low consumption mode are defined. The debugging switch options are provided. For more details, see "Debug Interface" part.

14.2 Register

SYSCFG Module Register List (Base Address: 0x4004 0800) Address Register Name Description 0x4004 0808 SAFR System configuration register 0x4004 0810 DBGCR Debug interface control register

14.2.1 System Configuration Register (SYSCFG_SAFR)

Offset Address: 0x0008 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 LOCK[15:0] WO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Reserved IEN_ CSM IEN_ BOD IEN_ EXTI Reserved SWJ CFG OSCCFG[1:0 - RW RW RW - RW1t RW1t 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Symbol Description 31 ~ 16 LOCK[15:0] Unlock bit of this register These bits are writed only, reading these bits returns 0x00. 0x5AA5: Unlocked Other: Locked Note: Writing to this register need to cooperate with unlocking control. Reading this register does not require unlocking. 15 ~ 8 Reserved -

7 IEN_CSM CSM causes NMI interrupt enable bit

6 IEN_BOD BOD causes NMI interrupt enable bit

5 IEN_EXTI0 EXTI0 causes NMI interrupt enable bit

4 ~ 3 Reserved -

2 SWJCFG Serial-Wire Pin Multiplexing Function Definition

These bits can only be written by software (reading these bits will return undefined values) for configuring SWD alternate functions. To release part or all of the debug ports to general purpose I/O ports, the user software can set SWJCFG after reset. 0: SWD debug port can not be multiplexed as general purpose I/O. SWDIO and SWCLK are used as debug pins. 1: SWD turned off; SWDIO and SWCLK can be multiplexed as general purpose I/O in normal operation state, and they are still forced to be used as debug interfaces in debug mode state. Note: Once this control bit is set, it can only be modified by resetting. Users should carefully configure this bit, because some options will cause the SWD interface to be unusable, but they can be recovered through the SWD interface, while cooperating with the reset signal is required. 1 ~ 0 OSCCFG[1:0] XTAL1/XTAL2 Pin Multiplexing Function Definition 00: XTAL1/XTAL2 is used as GPIO (default) 01: External oscillator interface (crystal and ceramic) 10: XTAL1 is externally clocked, XTAL2 is used as GPIO 11: Reserved Note: Once this control bit is set, it can only be modified after reset.

14.2.2 Debug Interface Control Register (SYSCFG_DBGCR)

Offset Address: 0x0010 Reset Value: 0x0000 0080 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 LOCK[15:0] WO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 DBG_T WI DBG_ SPI DBG_ UART DBG_ MCM DBG_T IM DBG_ GPT DBG_ WWDT DBG_I WDT DBG_ DMA Reserved DBG_ STOP DBG_ SLEEP RW RW RW RW RW RW RW RW RW - RW RW 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 Bit Symbol Description 31 ~ 16 LOCK[15:0] Unlock bit of this register These bits are written only, reading these bits returns 0x0000. 0x5AA5: Unlocked Other: Locked Note: Writing to this register need to cooperate with unlocking control. Reading this register does not require unlocking.

15 DBG_TWI TWI stopped when core is halted

0: TWI is stopped 1: TWI is still working properly

14 DBG_SPI SPI stopped when core is halted

0: SPI is stopped 1: SPI is still working properly

13 DBG_UART UART stopped when core is halted

0: UART is stopped 1: UART is still working properly

12 DBG_MCM UART stopped when core is halted

0: MCM is stopped 1: MCM is still working properly

11 DBG_TIM TIM7-TIM8 counter stopped when core is halted

0: Of TIM7-TIM8 the clock of the involved timer counter is stopped when the core is halted. 1: Of TIM7-TIM8 the clock of the involved timer counter is fed event if the core is halted and the outputs behave normally.

10 DBG_PCA PCA stoped when core is halted

0: PCA is stopped 1: PCA is still working properly

9 DBG_WWDT Window watchdog stopped when core is haled

0: Window watchdog counter is stopped 1: Window watchdog counter is still working properly

8 DBG_IWDT Watchdog stopped when core is haled

0: Watchdog counter is stopped 1: Watchdog counter is still working properly

7 DBG_QEI QEI stopped when core is halted

0: QEI is stopped 1: QEI is still working properly 6 ~ 2 Reserved -

1 DBG_STOP Debug stop mode

0: In stop mode, the system clock is held and it is the internal RC oscillator which provides the system clock (including HCLK and FCLK). When exiting stop mode, the software must reconfigure the clock system to start the PLL, crystal oscillator, etc. (same operation when configuring this bit to 0) 1: In stop mode, the system clock is turned off and the clock controller disables all clocks (including HCLK and FCLK). When exiting from stop mode, the configuration of the clock is the same as after the reset (the microcontroller is clocked by the 8MHz internal RC oscillator (HSI)). Therefore, the software must reconfigure the clock control system to start the PLL, crystal oscillator, etc. Note: HCLK remains on when DBG_STOP = 0, but the external device clock is masked. HCLK maintains the connection of the debug interface, which means the debugger can read the status information of CPU and peripherals before the shutdown.

0 Reserved -

1. Interrupts and events

15.1 Nestable Interrupt Vector Controller (NVIC)

15.1.1 Introduction

NVIC is an integrated part of ARM Star processor. It is closely linked to the ARM Star CPU core logic, reducing interrupt latency and allowing new interrupts to be processed efficiently. NVIC can also handle system exceptions, including: Reset, Non-maskable Interrupt (NMI), Hard Fault, Memory Manage Fault, Bus Fault, Usage Fault, Call System Services (SVCall), Debug Monitor, PendSV, and Systick.

15.1.2 Main Features

 Nested vector controller is an integral part of ARM Star core  Highly coupled interrupt controllers provide low interrupt latency.  Processing system exceptions and peripheral interrupts  Support 29 maskable interrupts (Not excluding 16 ARM Star interrupts).  8 programmable interrupt priorities (prioritized grouping is available)  Low latency exceptions and interrupt handling  Interrupts maskable  Software interrupt Nested interrupt support The NVIC provides nested interrupt support. All external interrupts and most of system exceptions can be programmed to different priority levels. The current priority is stored in a dedicated field of xPSR. When an interrupt occurs, the NVIC compares the priority of this interrupt to the current exception priority to see which one is higher. If an exception with higher priority is found, the processor interrupts the current interrupt service routine and serves the new one, which means interrupt preemption. Vectored interrupt support The ARM Star processor has vectored interrupt support. When an interrupt is accepted, the starting address of the interrupt service routine (ISR) is located from a vector table in memory. Priority levels of interrupts can be changed by software during runtime. Interrupts that are being serviced are blocked from further activation until the ISR is completed, so their priority can be changed without risk of accidental reentry. Reduction of Interrupt Latency The ARM Star processor also includes a number of advanced features to lower the interrupt latency. These include automatic saving and restoring some register contents, reducing delay in switching from one ISR to another. For more information, please see the ARM official manual. Interrupts masking Interrupts and system exceptions can be masked based on their priority level or masked completely using the interrupt masking registers BASEPRI, PRIMASK, and FAULTMASK. They can be used to ensure that time-critical tasks can be finished on time without being interrupted.

15.1.3 Interrupts Summary

The summary of all interrupt is shown in the following table: The NMI source contains CSM, EXTI0, BOD, and every source has separate control bits (see the SYSCFG_SAFR register). In addition to the NMI entry, EXTI0 also has a separate EXTI0 entry, so user needs to choose from generating NMI or EXTI0 (can be enabled at the same time). BOD also has two interrupt entries, while CSM has only NMI interrupt entries.

9 Exception + 29 HWINT

Interrupt No. /Exception No. Interrupt Source Vector Address Priority Description -16 / 0 - 0x0000 - Stack initial pointer value -15 / 1 Reset 0x0004 -3(Highest) Reset PC value, asynchronous attribute. -14 / 2 NMI 0x0008 -2 Non-maskable interrupt. From external interrupt input pin (EXTI0 only in this example) and clock monitoring signal (CSM), brownout monitoring signal (BOD). Asynchronous attribute. All types of failures when the failure cannot be activated due to priority reasons or configurable fault handling is prohibited. Synchronization properties. -13 / 3 HardFault 0x000C -1 All types of failures when those failures cannot be activated due to priority reasons or configurable fault handling is prohibited. Synchronization attribute. -12 / 4 MemManage 0x0010 Adjustable(1) MPU mismatch, including violation of access specifications and mismatch. Synchronous. Even if MPU is disabled or does not exist, it can be used to support the XN area mapped by the default memory. -11 / 5 BusFault 0x0014 Adjustable (1) Prefetch failures, memory access failures, and other related address/storage failures. It is synchronous when it is precise, and asynchronous when it is not precise. -10 / 6 UsageFault 0x0018 Adjustable(1) Use failure. For example, executing an undefined instruction or attempting an illegal state transition. Synchronization attribute. -9 / 7 - 0x001C - -8 / 8 - 0x0020 - -7 / 9 - 0x0024 - -6 / 10 - 0x0028 - -5 / 11 SVCall 0x002C Adjustable(1) Calls system services using SVC instructions. Synchronization attribute. -4 / 12 DebugMonitor 0x0030 Adjustable(1) Debug monitoring, which occurs when the processor is not stopped. It is synchronous, but only valid when enabled. If its priority is lower than the priority of the currently active exception, it cannot be activated. -3 / 13 - 0x0034 -2 / 14 PendSV 0x0038 Adjustable(1) System service request that can be pended. It is asynchronous, and pending can only be achieved by software. -1 / 15 SysTick 0x003C Adjustable(1) The system tick timer is decreased to zero. Asynchronous attribute.

0 WWDT 0x0040 Adjustable(2) Window watchdog timer interrupt

1 BOD 0x0044 Adjustable(2) Brownout detection interrupt

2 RCC 0x0048 Adjustable(2) PLL and external clock ready interrupt

3 EXTI0 0x004C Adjustable(2) EXTI pin 0 interrupt

4 EXTI1 0x0050 Adjustable(2) EXTI pin 1 interrupt

5 EXTI2 0x0054 Adjustable(2) EXTI pin 2 interrupt

6 EXTI3 0x0058 Adjustable(2) EXTI pin 3 interrupt

7 MCM_FLT 0x005C Adjustable(2) MCM module PWM fault interrupt

8 MCM_PWM 0x0060 Adjustable(2) MCM module PWM interrupt

9 ADC 0x0064 Adjustable(2) ADC interrupt

10 PCA0 0x0068 Adjustable(2) PCA0 interrupt

11 PCA1 0x006C Adjustable(2) PCA1 interrupt

12 PCA0_FLT 0x0070 Adjustable(2) PCA0 fault interrupt

13 PCA1_FLT 0x0074 Adjustable(2) PCA1 fault interrupt

14 CMP0 0x0078 Adjustable(2) Comparator 0 interrupt

15 CMP1 0x007C Adjustable(2) Comparator 1 interrupt

16 QEI 0x0080 Adjustable(2) Quadrature encoder interface (QEI) interrupt

17 CAN 0x0084 Adjustable(2) CAN interrupt

18 TWI 0x0088 Adjustable(2) Two-wire serial interface interrupt

19 SPI 0x008C Adjustable(2) SPI interrupt

20 UART0 0x0090 Adjustable(2) UART0 interrupt

21 UART1 0x0094 Adjustable(2) UART1 interrupt

22 UART2 0x0098 Adjustable(2) UART2 interrupt

23 TIM7 0x009C Adjustable(2) Timer7 interrupt

24 TIM8 0x00A0 Adjustable(2) Timer8 interrupt

25 EXTI4_7 0x00A4 Adjustable(2) EXTI 4~7 interrupt

26 FIFO0 0x00A8 Adjustable(2) FIFO0 interrupt

27 FIFO1 0x00AC Adjustable(2) FIFO1 interrupt

28 FIFO2 0x00B0 Adjustable(2) FIFO2 interrupt

Note: 1. Using the NVIC system handler priority register, the priority of the exception type can be changed. For more information, please see the ARM official manual. 2. Using the NVIC Interrupt Priority Register, the interrupt priority can be changed. For the above interrupt source (except for system reset interrupt), only when the triggering of interrupt is allowed by both corresponding interrupt mask bit and interrupt enable bit, the corresponding interrupt flag is set by hardware, then the interrupt will be triggered. The interrupt response process is determined by interrupt priority settings and nesting settings.

15.1.4 NVIC Register List

Address Register Type Description Reset Value 0xE000E004 ICTR Read only Interrupt control type register 0x00000001 0xE000E010 SCTRL Read/write SysTick control and status register 0x00000000 0xE000E014 SLOAD Read/write SysTick reload value register Unpredictable 0xE000E018 SVAL Read/write/clear SysTick current value register Unpredictable 0xE000E01C SCALIB Read only SysTick calibration value register 0x40019A28 0xE000E100 ISER0_31 Read/write Irq0～31 enable setting register 0x00000000 0xE000E104 ISER32_63 Read/write Irq32～63 enable setting register 0x00000000 0xE000E180 ICER0_31 Read/write Irq0～31 enable clear register 0x00000000 0xE000E184 ICER32_63 Read/write Irq32～63 enable clear register 0x00000000 0xE000E200 ISPR0_31 Read/write Irq0～31 pending setting register 0x00000000 0xE000E204 ISPR32_63 Read/write Irq32～63 pending setting register 0x00000000 0xE000E280 ICPR0_31 Read/write Irq0～31 pending clear register 0x00000000 0xE000E284 ICPR32_63 Read/write Irq32～63 pending clear register 0x00000000 0xE000E300 IABR0_31 Read only Irq0～31 activation bit register 0x00000000 0xE000E304 IABR32_63 Read only Irq32～63 activation bit register 0x00000000 0xE000E400 IPR0_3 Read/write Irq0~3 priority register 0x00000000 0xE000E404 IPR4_7 Read/write Irq4~7 priority register 0x00000000 0xE000E408 IPR8_11 Read/write Irq8~11 priority register 0x00000000 0xE000E40C IPR12_15 Read/write Irq12~15 priority register 0x00000000 0xE000E410 IPR16_19 Read/write Irq16~19 priority register 0x00000000 0xE000E414 IPR20_3 Read/write Irq20~23 priority register 0x00000000 0xE000E418 IPR24_27 Read/write Irq24~27 priority register 0x00000000 0xE000E41C IPR28_31 Read/write Irq28~31 priority register 0x00000000 0xE000E420 IPR32_35 Read/write Irq32~35 priority register 0x00000000 0xE000E424 IPR36_39 Read/write Irq36~39 priority register 0x00000000 0xE000E428 IPR40_43 Read/write Irq40~43 priority register 0x00000000 0xE000E42C IPR44_47 Read/write Irq44~47 priority register 0x00000000 0xE000E430 IPR48_51 Read/write Irq48~51 priority register 0x00000000 0xE000E434 IPR52_55 Read/write Irq52~55 priority register 0x00000000 0xE000E438 IPR56_59 Read/write Irq56~59 priority register 0x00000000 0xE000E43C IPR60_63 Read/write Irq60~63 priority register 0x00000000 0xE000ED00 CPUID Read only CPUID base address register 0x412FC231 0xE000ED04 ICSR Read/write or read only Interrupt control status register 0x00000000 0xE000ED08 VTOR Read/write Vector table offset register 0x00000000 0xE000ED0C AIRCR Read/write Application interrupt/reset control register 0x00000000 0xE000ED10 SCR Read/write System control register 0x00000000 0xE000ED14 CCR Read/write Configuration control register 0x00000000 0xE000ED18 SHPR4_7 Read/write System handler 4-7 priority register, MemManage is 4, Bus Fault is 5, and Usage Fault is 6 0x00000000 0xE000ED1C SHPR8_11 Read/write System handler 8-11 priority register, SVCall is 11 0x00000000 0xE000ED20 SHPR12_15 Read/write System handler 12-15 priority register, PendSV is 14, SysTick is 15 0x00000000 0xE000ED24 SHCSR Read/write System processor control and status register 0x00000000 0xE000ED2C CFSR Read/write Configurable fault status register 0x00000000 0xE000ED30 HFSR Read/write Hard fault status register 0x00000000 0xE000ED34 DFSR Read/write Debug fault status register 0x00000000 0xE000ED38 MMFAR Read/write Memory management address register 不可预测 0xE000ED3C BFAR Read/write Bus fault address register 不可预测 0xE000ED40 AFSR Read/write/clear Auxiliary fault status register 0x00000000 0xE000EF00 STIR Write only Software trigger interrupt register - Note: For more detail description of the above registers, please see the ARM official manual.

15.2 External Interrupt/Event Controller (EXTI)

The external interrupt/event controller consists of 8 levels and edge detectors, all of those 8 lines can be configured to the GPIO port. Each input line can be independently configured with an input type (level or edge) and the corresponding trigger event (high/low level, rising/falling edge or both edges). Each input line can also enabled independently. A pending register maintains the status line of the interrupt requests.

15.2.1 Main Features

 Independent enable control on each interrupt/event line  Dedicated status bit for each interrupt line  Generation of up to 8 software interrupt/event requests  Adjustable input debounce filter parameters Peripheral interface Interrupt enable register Request pending Software trigger interrupt Rising /high trigger selection Falling/low trigger selection Edge detection/level detection circuit Event signal generation Event enable register To NVIC interrupt controller Event generated by EXTI EXTI input line PCLK Figure15-1 External Interrupt/Event Controller Block Diagram

15.2.2 Wake-up Event Management

SH33F2801 can handle external or internal events to wake up the core (WFE). Wake-up events can be generated by the following configuration:  Enable an interrupt in the peripheral control register, but not in NVIC, and enabling the SEVONPEND bit in the ARM Star system control register. When the MCU resumes from the WFE, the peripheral interrupt pending bit (in the EXTI pending register) and the peripheral NVIC IRQ channel pending bit (in the NVIC interrupt pending clear register) have to be cleared.  Configure an external or internal EXTI line to be in event mode. When CPU resumes from WFE, because the interrupt pending bit in the corresponding event line (in EXTI pending register) will also be set, the software needs to clear the corresponding pending bit. To use the external I/O port as a wake-up event, see the “GPIO Configuration for External Interrupt/Wake-up Line” description in the GPIO part. EXTI0 and EXTI2 can wake STOP mode; other EXTI cannot wake STOP mode. All EXTI can wake up SLEEP mode.

15.2.3 Function Description

To generate an interrupt, the interrupt line must be configured and enabled. Two trigger registers are set according to the required edge/level detection, and enabling interrupt request by writing '1' to the corresponding bit of the interrupt enable register. When the expected edge/level occurs on the external interrupt line, an interrupt request is generated and the corresponding pending bit is also set. This request is reset by writing '1' to the clear bit of the pending register. To generate an event, the event line must be configured and enabled. Two trigger registers are set according to the required edge/level detection, and enabling event request by writing '1' to the corresponding bit of the event enable register. When the expected edge/level occurs on the event line, an event request pulse is generated and the pending bit (PR) corresponding to the interrupt path is also set. SH33F2801 supports level triggering. By setting the trigger mode to level trigger and setting the high level or low level trigger, EXTI can work in the level trigger state, which is different from the edge trigger. If the trigger level does not change, it will continue triggering. The EXTI input signal supports sampling filtering. It uses PCLK as the clock source during normal operation, and supports sampling clock prescaler (up to 128 division), supports multiple sampling to achieve filtering effect. In stop mode, since PCLK is turned off, EXTI uses LSI as the clock source (note). See the “EXTI Sampling Control Register” for details. Note: When LSI is used as the filter clock source, it is not recommended to turn on the prescaler processing due to low frequency. EXTI0 can cause an NMI interrupt, which is enabled by the IEN_EXTI0@SYSCFG_SAFR control bit. Hardware interrupts selection Use the following procedure to configure 8 input lines as the interrupt sources:  Configure the enable bits of 8 interrupt lines (EXTI_IMR)  Configure the trigger selection bits (EXTI_RTSR and EXTI_FTSR) of the 8 interrupt lines  Configure the enable bits of the NVIC interrupt channel mapped to the external interrupt controller (EXTI) so that an interrupt coming from one of the 8 interrupt lines can be correctly acknowledged. Hardware event selection Use the following procedure to configure 8 input lines as the event sources:  Configure the enable bits of 8 event lines (EXTI_EMR)  Configure the trigger selection bits (EXTI_RTSR and EXTI_FTSR) of the event line Software triggered interrupt selection The 8 lines can be configured as software trigger interrupt lines. The following is the process of generating a software interrupt:  Configure enable bits of 8 interrupt lines (EXTI_IMR)  Set the required bit of the software trigger interrupt register (EXTI_SWIER)

15.2.4 External Interrupt/Event Line Mapping

All GPIOs are connected to the 8 external interrupt/event lines in the following manner: To enable an EXTI function , the I/O port must be configured as AF1(Input function closed in AF0 mode, including external interrupt). Then you turn on the external interrupt/event line switch, which is controlled by the corresponding bit in the EXTI CFG register, EXTIn_EN(n=0~7)is set to 1. Note: When setting AF2/AF3, The I/O port input function is also open and can be configured, as detailed in the "GPIO" section.

Table15-1 External Interrupt General I/O Mapping I/O EXTIn_EN EXTI Line extended function PB0 EXTI0_EN=1 EXTI0 Support to NMI interrupt and support to wake up STOP PA13 EXTI1_EN=1 EXTI1 - PA10 EXTI2_EN=1 EXTI2 Support to wake STOP, support as TIM8 clock input PA9 EXTI3_EN=1 EXTI3 - PA6 EXTI4_EN=1 EXTI4 - PA2 EXTI5_EN=1 EXTI5 - PA1 EXTI6_EN=1 EXTI6 - PC12 EXTI7_EN=1 EXTI7 -

15.3 Register

EXTI Module Register List (Base Address: 0x4000 4000) Address Register Name Description 0x4000 4000 IMR Interrupt enable register 0x4000 4004 EMR Event enable register 0x4000 4008 TMSR Trigger mode selection register 0x4000 400C RTSR Rising edge/high level trigger mode selection register 0x4000 4010 FTSR Falling edge/low level trigger mode selection register 0x4000 4014 SWIER Software trigger interrupt register 0x4000 4018 PR Pending Register 0x4000 401C CFGL External interrupt configuration low register 0x4000 4020 CFGH External interrupt configuration high register 0x4000 4024 SAMP EXTI sample control high register

15.3.1 Interrupt Enable Register (EXTI_IMR)

Offset Address: 0x0000 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Reserved IMRy (y=7~0) - RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Symbol Description 31 ~ 8 Reserved - 7 ~ 0 IMRy (y=7~0) Interrupt mask on line y 0: Masks interrupt requests from line y 1: Opens interrupt request from line y

15.3.2 Event Enable Register (EXTI_EMR)

Offset Address: 0x0004 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Reserved EMRy (y=7~0) - RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Symbol Description 31 ~ 8 Reserved - 7 ~ 0 EMRy (y=7~0) Event mask on line y 0: Masks event requests from line y 1: Opens event request from line y

15.3.3 Trigger Mode Selection Register (EXTI_TMSR)

Offset Address: 0x0008 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Reserved TMRy (y=7~0) - RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Symbol Description 31 ~ 8 Reserved - 7 ~ 0 TMRy (y=7~0) Trigger mode selection on line y 0: Edge trigger 1: Level trigger Note: The edge trigger is one-shot mode. After the trigger, the software clear pending flag is used to clear the flag. The level trigger is level mode. After triggering, the flag can only be cleared by external level change and cannot be cleared by software.

15.3.4 Rising Edge/High Level Trigger Mode Selection Register (EXTI_RTSR)

Offset Address: 0x000C Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Reserved RTRy (y=7~0) - RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Symbol Description 31 ~ 8 Reserved - 7 ~ 0 RTRy(y=7~0) Rising edge/high level trigger event configuration bit of line y 0: Rising edge/high level trigger on input line y (interrupt and event) is enabled 1: Rising edge/high level trigger on input line y (interrupt and event) is disabled

15.3.5 Falling Edge/Low Level Trigger Mode Selection Register

Offset Address: 0x0010 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Reserved FTRy (y=7~0) - RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Symbol Description 31 ~ 8 Reserved - 7 ~ 0 FTRy (y=7~0) Falling edge/low level trigger event configuration bit of line y 0: Falling edge/low level trigger on input line y (interrupt and event) is enabled 1: Falling edge/low level trigger on input line y (interrupt and event) is disabled

15.3.6 Software Trigger Interrupt Register (EXTI_SWIER)

Offset Address: 0x0014 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Reserved SWIERy (y=7~0) - WO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Symbol Description 31 ~ 8 Reserved - 7 ~ 0 SWIERy (y=7~0) Software interrupt on line y When the bit is '0', writing '1' will set the corresponding pending bit in EXTI_PR. If EXTI_IMR allows interrupt to be generated, an interrupt will be generated at this time. 0: No action 1: Sets the corresponding pending bit of EXTI_PR, causing software trigger This signal is automatically cleared by hardware. If the corresponding EXTI_PR is already set, this operation is invalid.

15.3.7 Pending Register (EXTI_PR)

Offset Address: 0x0018 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved PRCy (y=7~0) - WO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Reserved Pry (y=7~0) - RO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Symbol Description 31 ~ 24 Reserved - 23 ~ 16 PRCy (y=7~0) Pending clear bit 0: No action 1: Clears 15 ~ 8 Reserved - 7 ~ 0 PRy (y=7~0) Pending bit 0: No trigger request has occurred 1: Selected trigger request has occurred This bit is set to '1' when a selected trigger interrupt/event occurs on the external interrupt line. Note: For level trigger, if the external level does not change, pending bit will be generated again immediately after clearing the pending bit.

15.3.8 External Interrupt Configuration Low Register (EXTI_CFGL)

Offset Address: 0x001C Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Reserved EXTI 7_E N EXTI 6_E N EXTI 5_E N EXTI 4_E N EXTI 3_E N EXTI 2_E N EXTI 1_E N EXTI 0_E N - RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 8 Reserved -

7 EXTI7_EN EXTI 7 Channel configuration switch

0: Disable EXTI7 1: Enable EXTI7

6 EXTI6_EN EXTI 6 Channel configuration switch

0: Disable EXTI6 1: Enable EXTI6

5 EXTI5_EN EXTI 5 Channel configuration switch

0: Disable EXTI5 1: Enable EXTI5

4 EXTI4_EN EXTI 4 Channel configuration switch

0: Disable EXTI4 1: Enable EXTI4

3 EXTI3_EN EXTI 3 Channel configuration switch

0: Disable EXTI3 1: Enable EXTI3

2 EXTI2_EN EXTI 2 Channel configuration switch

0: Disable EXTI2 1: Enable EXTI2

1 EXTI1_EN EXTI 1 Channel configuration switch

0: Disable EXTI1 1: Enable EXTI1

0 EXTI0_EN EXTI 0 Channel configuration switch

0: Disable EXTI0 1: Enable EXTI0

15.3.9 External Interrupt Configuration High Register (EXTI_CFGH)

Offset Address: 0x0020 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 0 Reserved -

15.3.10 EXTI Sample Control Low Register (EXTI_SAMP)

Offset Address: 0x0024 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Symbol Description 31 ~ 30 PS7[1:0] EXTI7 sampling clock prescaler selection bit 00: 1/1 01: 1/4 10: 1/16 11: 1/128 29 ~ 28 SN7[1:0] EXTI7 continuous sample number selection bit 00: 1 01: 2 10: 3 11: 4 27 ~ 26 PS6[1:0] EXTI6 sampling clock prescaler selection bit 00: 1/1 01: 1/4 10: 1/16 11: 1/128 25 ~ 24 SN6[1:0] EXTI6 continuous sample number selection bit 00: 1 01: 2 10: 3 11: 4 23 ~ 22 PS5[1:0] EXTI5 sampling clock prescaler selection bit 00: 1/1 01: 1/4 10: 1/16 11: 1/128 21 ~ 20 SN5[1:0] EXTI5 continuous sample number selection bit 00: 1 01: 2 10: 3 11: 4 19 ~ 18 PS4[1:0] EXTI4 sampling clock prescaler selection bit 00: 1/1 01: 1/4 10: 1/16 11: 1/128 17 ~ 16 SN4[1:0] EXTI4 continuous sample number selection bit 00: 1 01: 2 10: 3 11: 4 15 ~ 14 PS3[1:0] EXTI3 sampling clock prescaler selection bit 00: 1/1 01: 1/4 10: 1/16 11: 1/128

13 ~ 12 SN3[1:0] EXTI3 continuous sample number selection bit 00: 1 01: 2 10: 3 11: 4 11 ~ 10 PS2[1:0] EXTI2 sampling clock prescaler selection bit 00: 1/1 01: 1/4 10: 1/16 11: 1/128 9 ~ 8 SN2[1:0] EXTI2 continuous sample number selection bit 00: 1 01: 2 10: 3 11: 4 7 ~ 6 PS1[1:0] EXTI1 sampling clock prescaler selection bit 00: 1/1 01: 1/4 10: 1/16 11: 1/128 5 ~ 4 SN1[1:0] EXTI1 continuous sample number selection bit 00: 1 01: 2 10: 3 11: 4 3 ~ 2 PS0[1:0] EXTI0 sampling clock prescaler selection bit 00: 1/1 01: 1/4 10: 1/16 11: 1/128 1 ~ 0 SN0[1:0] EXTI0 continuous sample number selection bit 00: 1 01: 2 10: 3 11: 4

1. Motor Control Module (MCM)

16.1 Introduction

SH33F2801 has a built-in motor control PWM modules. The PWM module consists of PWM Time Base Block, Wave Generator, Dead & Polarity Logic, Fault Detect Logic, and Output Control Logic, as shown in Figure 16-1. The PWM clock is counted via a 16-bit counter (PWM Counter) in the time base module, and the value of the counter is used to compare with the period register and 0 to generate a periodic matching signal and a zero matching signal, compare with the duty cycle register to generate a duty cycle matching signal, and combine with the waveform generation module to generate the original 6 PWM signals Px_O/Px1_O. After this original PWM signal passes through the dead zone & polarity control module, PWM signal Px_D/Px1_D with dead zone and polarity is generated. The final output control module and fault detection module determine whether to output the Px_D/Px1_D signal to the PWM pin PWMx/PWMx1. HCLK PWM0 P0_O x=0,1,2 Fault_Signal FLT Output of ComparatorFLTCON Duty Compare Duty Compare PWM0/01 Wave Generator PWM1/11 Wave Generator PWM2/21 Wave Generator Pre-Counter Logic PWM Counter Period Compare P01_O P1_O P11_O P2_O P21_O PWM0/01 Dead &Polarity Logic PWM1/11 Dead &Polarity Logic PWM2/21 Dead &Polarity Logic P0_D P01_D P1_D P11_D P2_D P21_D Output Control Logic PWM01 PWM1 PWM11 PWM2 PWM21 Fault Detect LogicPWMx/X1s@PWMCON1 PTMOD OSYNC@PWMCON2 PWMOE PDCONx@PWMCON1 Post Counter PWMINT1/2/3Interrupt Control Period Match Zero Match Gated&Scaled Reload Signal Scaled Period Match Scaled Zero Match 6 Duty Match ADC Triger Logic ADC Trigger Signal TIM Triger Logic Timer Trigger Signal PMANUALCON1/2 POSTPS@PWMCON1 PWM Time Base Block PWM0D/PWM01D BUFFER PWMP BUFFER PWMPSQ BUFFER PWMP BUFFER PWMDT0&1 BUFFER Figure16-1 PWM Module Diagram

16.2 Main Features

 The important register is controlled by the protected register PWMRLDEN  16-bit time base counter  Three time base counting modes: edge-aligned count, center-aligned count, and single-count mode  Two waveform output modes: complementary mode and independent mode  In complementary mode, provides dead zone control logic and supports both symmetric and asymmetric modes  Providing PWM periodic matching interrupt, zero matching interrupt, duty cycle compare matching interrupt, fault protection interrupt  3 complementary PWM output or 6 independent PWM output, with output polarity selectable  Provides fault detection function to close PWM output at emergency  Provides register reload enable bit to ensure register reload synchronization  16-bit pre-division, 8 stages post-division  Switchable manual control PWM output  Triggers ADC at any four moments in a PWM time base period  PWM final output can be configured as mapping to pins in a different order (see User Code Options chapter)

16.3 Function Description

16.3.1 PWM0/1/2 Time Base Block

In the PWM module, the time base block consists primarily of a 16-bit counter combined with a prescaler and a postscaler. As shown in Figure 16-2, the wave generator uses the value of the 16-bit counter in the time base module to compare with the duty cycle register and combines dead & polarity logic and output control logic to finally generate the PWM waveform. Figure 16-2 shows a logical diagram of the time base module. 16-Bit PWM CounterPre-Counter 16bit HCLK Clock Control PTMOD1/0 PWMEN Comparator PWMPSQ BUFFER PWM Counter Control Zero Detection PWMP BUFFER Zero MatchPWM Clock Dir Signal Reset Signal Post-Counter 1:1~1:8 Period Match Scaled Zero MatchGated Reload Scaled Period Match PWMRLDEN==0xAA Scaled Period Match Scaled Zero Match Duty Resgiters Reload Signal PWM Time Base Block POSTPS PDLDEN@PWMCON2 Figure16-2 PWM Time Base Logic Diagram

16.3.1.1 PWM Clock

The PWM clock frequency is divided from the APB clock (PCLK). It is determined in the PWMPSQ register via the prescaler (Pre-Counter) that the PWM module clock is (PWMPSQ+1) division of PCLK. The PWM time base module can be enabled / disabled by software setting/clearing the PWMOE register. When PWMOE is set from 0 to 1, the PWM counter begins counting up the PWM clock from the PWMC value. When the PWMOE bit is cleared, the pre-division internal counter, the post-division internal counter, and the PWM counter are all cleared. Note 1: If it is in the edge mode, and the initial value written to PWMC is greater than or equal to the value of PWMP, the PWMC first starts from PWMP to 0, and then starts up-count operation. Note 2: If it is in the center-aligned mode, and the initial value written to PWMC is greater than the value of PWMP, the PWMC counts down from PWMP. Note 3: PWMC is cleared once when the module is stopped, and can be written afterwards.

16.3.1.2 PWM Time Base Working Mode

The 16-bit PWM counter in the PWM time base has three modes of operation, which are determined by the PTMOD[1:0] bit segment in the PWMCON1 register. The modification of the counting mode needs to be completed before the PWM module is enabled. If the counting mode is modified after the PWM module is enabled, unexpected results may be obtained.

16.3.1.3 Edge Aligned Counting Mode

Set the PTMOD bit segment of PWMCON1 to 00, and the PWM counter in the time base module will work in edge-aligned counting mode. In this mode, the software sets the PWMOE bit to 1. The PWM counter will count up from the PWMC value until it matches the PWM periodic register PWMP, then the PWM counter is reset to 0 and continues up-count operation, thus reciprocating. The time when the PWM counter is reset to 0 is the Zero Match. The software clears the PWMOE bit to 0, and the PWM Counter will stop counting and reset to 0 on the next PCLK edge and stop counting. If PWMP = 5 and the initial PWMC=0, the operation of the PWM counter in this mode is shown in Figure 16-3. PWMP = 5 PWM Counter PWM Clock Zero Match Zero Match PWMOE Figure16-3 Edge Aligned Counting Mode

16.3.1.4 Center Aligned Counting Mode

Set the PTMOD bit segment of PWMCON1 to 01b, and the PWM counter in the time base module will work in the center-aligned counting mode. In this mode, the software sets the PWMOE bit from 0 to 1, and the PWM counter will count up from the PWMC value until it matches the PWM periodic register PWMP, then the PWM counter starts down-count operation until it returns to zero, thus reciprocating. The time when the PWM counter counts down to zero is the Zero Match, and the time when the PWM counter matches the periodic register is the Period Match. The software clears the PWMOE bit from 1 to 0, and the PWM Counter will stop counting and reset to 0 on the next PCLK edge and stop counting. If PWMP = 5 is set and the initial PWMC=0, the operation of the PWM counter in this mode is shown in Figure 16-4.

4PWMP=5 PWM Counter PWM Clock Zero MatchPeirod Match Period Match PWMOE Figure16-4 Center Aligned Counting Mode

16.3.1.5 Single Counting Mode

Set the PTMOD bit segment of PWMCON1 to 10b or 11b, and the PWM counter in the time base module will work in single counting mode. In this mode, the software sets the PWMOE bit from 0 to 1. The PWM counter will count up from the PWMC value until when it matches the PWM period register PWMP, the PWM counter is reset to 0, the PWMOE bit is cleared by hardware at the same time, and the PWM output is in high resistance status. The time when the PWM counter is reset to 0 is the Zero Match. If the software sets the PWMOE bit from 1 to 0 during the PWM counter up-count operation process, the PWM Counter will reset to 0 on the next PCLK edge and stop counting. If PWMP = 5 is set and the initial PWMC = 0, the operation of the PWM counter in this mode is shown in Figure 16-5. PWMP = 5 PWM Counter PWM Clock Zero Match PWMOE Figure16-5 Single Counting Mode

16.3.1.6 Post-Division

Post-division is useful when updating the duty cycle of PWM every cycle is not needed. As shown in Figure 16-2, the periodic matching signal and the zero matching signal generated by the PWM counter pass through the post-division counter, being able to achieve 1/1, 1/2, 1/3, 1/4, 1/5, 1/6, 1/7, 1/8 frequency division. The above eight-stagers post-division can be selected via the POTSTS bit in the register PWMCON1. Let POOSTS = 0, then pre-division is forbidden, and the periodic matching signal and zero matching signal will not be divided. Firstly, the divided periodic matching signal and zero matching signal, combining with the PWMRLDEN register value, are used to control the period register PWMP, the clock pre-division factor PWMPSQ[15:0], and reloading of the duty cycle register. Secondly, the divided Scaled periodic matching signal and zero matching signals can be used to generate a zero matching interrupt and a periodic matching interrupt, as shown in Figure 16-1. See the “Time Base Interruption” chapter for details. Finally, the triggering of AD signal by PWM compare register is also controlled by the post-division coefficient. The ADC can be triggered when the PWM count value is equal to the PWM compare value during the post-division valid period. However, the post-division is only valid for the periodic matching signal and the zero matching signal, and is invalid for the duty-matching timing. For example, when the duty cycle interrupt and the zero matching signals are interrupted, and when the post-division is set to 8 divisions, the zero matching signal interrupt will only introduce an interrupt after 8 PWM cycles, while the duty-matching signal will still trigger an interrupt every PWM cycle.

16.3.1.7 Time Base Interrupt

The time base interrupt includes periodic interrupt triggered by the divided periodic matching signal and zero matching interrupt triggered by the divided zero matching signal. When the divided periodic matching signal occurs, the PWMPIF bit in the register PWMINTF will be set to 1. At this time, if the PWMPIE bit in PWMINTEN is 1, the periodic interrupt will be triggered. When the divided zero matching signal occurs, the PWMZIF bit in the register PWMINTF will be set to 1. At this time, if the PWMZIE bit in PWMINTEN is 1, the zero matching interrupt will be triggered. The PWMPIF bit and the PWMZIF bit must be cleared by the software PWMPIFC and PWMZIFC write 1 respectively. When the POTSPS segment of PWMCON1 is equal to 0, the periodic matching signal and zero matching signal of the PWM counter will not be divided. Therefore, the PWMPIF bit will be set to 1 every time the periodic matching signal occurs, and the PWMZIF bit will be set to 1 every time the zero matching signals occurs.

16.3.1.8 PWM Periodic Register and Automatic Reloading of Pre-Division & Post-Division Coefficients

The period register PWMP has a buffer register, and the user can read and write PWMP but cannot operate its buffer register, as shown in Figure 16-2. When the PWM time base counter is running, it is actually compared with BUFFER of the periodic register to generate periodic matching signal. The clock pre-division coefficient PWMPSQ, also has a buffer register, and the user can read and write PWMPSQ but not its buffer register, as shown in Figure 16-2. PCLK is actually divided using BUFFER of the pre-division coefficient bit segment PWMPSQ to generate PWM clock. The POSTPS bit segment in the PWMCON1 register also has a buffer register, and the user can read and write POTSTS bit segment but cannot operate its buffer register, as shown in Figure 16-2. PCLK is actually doing post-divided operation by using the BUFFER of the post-division coefficient bit segment POTSPS. Since there are buffer registers, there are special rules for reading and writing the periodic register, pre-division and post-division register bits: 0x55, these registers are allowed to be modified. Then, only when the value of the PWMRLDEN register is 0xAA, the PWMP register and PWMPSQ are latched in the corresponding buffer register when the divided zero matching signal occurs. This can avoid reloading during register modification and avoid glitch when register modification takes effect immediately. Therefore, the modification of the above registers must come with the cooperation of the PWMRLDEN register to complete. Note: The reloading moments of these 3 registers are not configurable and can only occur in the zero matching.

16.3.2 PWM0/1/2 Waveform Generation Module

The PWM waveform generation module refers to the Wave Generator module in Figure 16-1. The waveform generation module compares the value of the PWM counter in the PWM time base module with six 16-bit duty cycle values to produce the original 6-channel PWM waveforms: P0_O, P01_O, P1_O, P11_O, P2_O, and P21_O. The original 6-channel PWM waveform signal is finally reflected on the six PWM output pins through the dead-zone & polarity logic and output control logic, as shown in Figure 16-1. The logic diagram of the waveform generator is shown in Figure 16-6. Px_O PWMx/PWMx1 Wave Generator Px1_O PWMxD BUFFER PWMx1D BUFFER PWMCON2[PTMODx]

16 Bits data from

x = 0~2 PWMINTF[PTUDxIF] PWMINTF[PTDDxIF] PDCONx Figure16-6 Waveform Generator Logic Diagram

16.3.2.1 PWM0/1/2 Output Mode

The PWM module contains three waveform generation modules, corresponding to three pairs of PWM outputs: PWM0/PWM01, PWM1/PWM11, and PWM2/PWM21, as shown in Figure 16-1. For each pair of PWM outputs, they can be configured in complementary mode or independent mode.

16.3.2.2 PWM Complementary Output Mode

Clear the POUTMOD bit in the PWMCON1 register to 0, then PWMx/PWMx1 is working in the complementary state. When working in symmetrical waveform output mode (PWMSYM@PWMCON1=0), the 16-bit PWM counter is compared with the duty cycle register PWMxD to generate Px_O and Px1_O waveforms, so the PWM waveforms output on PWMx and PWMx1 pins are using the same duty cycle register PWMxD. In this output mode, the polarity of the output waveform on the PWMx/PWMx1 pin can be set by the register PWMCON1 and the dead zone can be set by the registers PWMDT0x and PWMDT1x (see Chapter 16.3.3 “PWM Dead Zone and Polarity Control Module” for details). (x = 0 - 2) When working in asymmetric waveform output mode (PWMSYM@PWMCON1=1, valid only in center-aligned technology mode), the 16-bit PWM counter is compared with the duty cycle register PWMxD during the up-count operation process to generate the Px_O and Px1_O waveforms, and it is compared with the duty cycle register PWMx1D during the down-count operation process to generate the Px_O and Px1_O waveforms. In this output mode, the polarity of the output waveform on the PWMx/PWMx1 pin can be set by the register PWMCON1 and the dead zone can be set by the registers PWMDT0x and PWMDT1x (see Chapter 16.3.3 “PWM Dead Zone and Polarity Control Module” for details). (x = 0 - 2)

16.3.2.3 PWM Independent Output Mode

Set the POUTMOD bit in the PWMCON1 register to 1, then PWMx/PWMx1 is working in the independent state, the 16-bit PWM counter is compared with the duty cycle register PWMxD to generate the Px_O waveform, and the 16-bit PWM counter is compared with the value of the duty cycle register PWMx1D to generate the Px1_O waveform. Therefore, the final output PWM waveforms on the PWMx and PWMx1 pins use different duty cycle registers PWMxD and PWMx1D. In the independent output mode, the polarity of the output waveform on the PWMx/PWMx1 pin can be set by the register PWMCON1, but the registers PWMDT0x and PWMDT1x will be invalid, which means the PWM output has no dead zone in the independent output mode (see Chapter 16.3.3 “PWM Dead Zone and Polarity Control Module” for details.). (x = 0 - 2)

16.3.2.4 PWM Duty Cycle Duty Zone

In various modes, the duty cycle duty zone is defined by PDCONx@PWMCON1 (x=0-2). When PDCONx=0, in edge mode or independent mode, count value which is smaller than the duty cycle register is defined as the duty cycle Duty Zone, and the remaining area is the non-duty cycle zone (None-Duty Zone). In center mode, during up-count operation, the count value which is smaller than the duty cycle register is defined as the duty cycle Duty Zone, and the remaining area is the non-duty cycle zone (None-Duty Zone). During down-count operation, the count value which is smaller than or equal to the duty cycle register is defined as the duty cycle Duty Zone, and the remaining area is the None-Duty Zone. When PDCONx=1, in edge mode or independent mode, the count value which is greater than or equal to the duty cycle register is defined as the Duty Zone, and the remaining area is the None-Duty Zone; in the center mode, during up-count operation, the count value which is greater than or equal to the duty cycle register is defined as the Duty Zone, and the remaining area is the None-Duty Zone. During down-count operation, the count value which is smaller than the duty cycle register is defined as Duty Zone, the remaining area is None-Duty Zone.

16.3.2.5 PWM0/1/2 Original Waveforms in Edge-Aligned Counting Mode

PTMOD@ MCM_PWMCON1 is set 00b, and PWM is working in Edge-aligned counting mode. In the complementary output mode, the PWM original output waveforms Px_O and Px1_O are shown in Figure 16-8. After PWMOE is set to 1, the Px_O and Px1_O waveforms change to be high. After the PWM counter is matched with the duty cycle register PWMxD, the Px_O and Px1_O waveforms will be low until the PWM counter returns to zero, thus reciprocating. PWMP = 5 PWM Counter PWM Clock PWMOE Px_O/Px1_O PWMxD = 4 None-Duty Zone PWMx1D = 2 PTUDxIF = 1 PTDDxIF= 0 PTUDxIF = 1 PTDDxIF= 0 PDCONx = 0 Px_O/Px1_O PDCONx = 1 None-Duty Zone Duty Zone Duty Zone Figure16-7 PWM Original Waveforms in Edge-Aligned Counting and Complementary Output Mode In the independent output mode, the PWM original output waveforms Px_O and Px1_O are shown in Figure 16-8. After PWMOE is set from 0 to 1, the Px_O and Px1_O waveforms change to be high. After the PWM counter is matched with the duty cycle register PWMxD, the Px_O waveform will be low until the PWM counter returns to zero. After the PWM counter is matched with the duty cycle register PWMx1D, the Px1_O waveform will be low until the PWM counter returns to zero, thus reciprocating.

PWMP = 5 PWM Counter PWM Clock PWMOE Px_O PWMxD = 4 Duty Zone None-Duty Zone PWMx1D = 2 Px1_O PTUDxIF = 1 PTDDxIF= 0 PTUDxIF = 1 PTDDxIF= 0 PDCONx=0 PDCONx=0 Px_O Duty Zone None-Duty Zone Px1_O PDCONx=1 PDCONx=1 Figure16-8 PWM Original Waveforms in Edge-Aligned Counting and Independent Output Mode

16.3.2.6 PWM0/1/2 Original Waveforms in Center-Aligned Counting Mode

4PWMP=5 PWM Counter PWM Clock PWMOE PWMxD = 4 Duty ZoneNone-Duty Zone Px_O/Px1_O PTUDxIF = 1 PTDDxIF = 0 PTUDxIF = 0 PTDDxIF = 1 PTUDxIF = 1 PTDDxIF = 0 PTUDxIF = 0 PTDDxIF = 1 None-Duty Zone Duty Zone None-Duty Zone Px_O/Px1_O PDCONx = 0 PDCONx = 1 Figure16-9 PWM Original Waveforms in Center-Aligned Counting and Complementary Output Mode (Symmetrical Waveform) Let PTMOD = 01 in PWMCON1 and set the PWM time base to the center-aligned counting mode. In the complementary output mode, let PWMSYM = 0 in PWMCON1, the PWM waveform generation module is working in the symmetrical waveform output mode, and the PWM o output waveforms Px_O and Px1_O are shown in Figure 16-9. After PWMOE is set to 1, the Px_O and Px1_O waveforms remain high. After the PWM counter is matched with PWMxD during up-count operation, the Px_O and Px1_O waveforms will be low until the PWM counter is matched with PWMxD again during down-count operation, thus reciprocating.

4PWMP=5 PWM Counter PWM Clock PWMOE PWMxD = 4 Duty ZoneNone-Duty Zone Px_O/Px1_O PTUDxIF = 1 PTDDxIF = 0 PTUDxIF = 0 PTDDxIF = 1 PTUDxIF = 1 PTDDxIF = 0 PTUDxIF = 0 PTDDxIF = 1 None-Duty Zone PWMx1D = 3 None-Duty Zone Duty Zone Px_O/Px1_O PDCONx = 0 PDCONx = 1 Figure16-10 PWM Original Waveforms in Center-Aligned Counting and Complementary Output Mode (Asymmetric Waveform) Let set PTMOD = 01 in PWMCON1 and set the PWM time base to the center-aligned counting mode. In the complementary output mode, set PWMSYM =1 in PWMCON1, the PWM waveform generation module is working in the asymmetric waveform output mode, and the PWM original output waveforms Px_O and Px1_O are shown in Figure 16-10. After PWMOE is set to 1, the Px_O and Px1_O waveforms remain high. After the PWM counter is matched with PWMxD during up-count operation, the Px_O and Px1_O waveforms will be low until the PWM counter is matched with PWMx1D during down-count operation, thus reciprocating.

4PWMP=5 PWM Counter PWM Clock PWMOE PWMxD = 4 PWMx1D = 2 Duty ZoneNone-Duty Zone Px_O Px1_O PTUDxIF = 1 PTDDxIF = 0 PTUDxIF = 0 PTDDxIF = 1 PTUDxIF = 1 PTDDxIF = 0 PTUDxIF = 0 PTDDxIF = 1 Px_O Px1_O Duty Zone None-Duty Zone PDCONx= 0 PDCONx= 0 PDCONx= 1 PDCONx= 1 Figure16-11 PWM Original Waveforms in Center-Aligned Counting and Independent Output Mode In the independent output mode, the PWM original output waveforms Px_O and Px1_O are shown in Figure 16-11. After PWMOE is set to 1, the Px_O and Px1_O waveforms change to be high. After the PWM counter is matched with PWMxD during up-count operation, the Px_O waveform will be low until the PWM counter is matched with PWMxD again during down-count operation. After the PWM counter is matched with PWMxD during up-count operation the Px1_O waveform will be low until the PWM counter is match with PWMx1D again during down-count operation, thus reciprocating.

16.3.2.7 PWM0/1/2 Original Waveforms in Single Counting Mode

PTMOD@ MCM_PWMCON1 is set 10b or 11b, and PWM is working in single counting mode. In the complementary output mode, the PWM original output waveforms Px_O and Px1_O are shown in Figure 16-12. After PWMOE is set to 1, the Px_O and Px1_O waveforms change to be high, and the Px_O and Px1_O waveforms will be low after the PWM counter is matched with PWMxD during up-count operation. PWMP = 5 PWM Counter PWM Clock PWMOE Px_O/Px1_O PWMxD = 4 Duty Zone None-Duty Zone PWMx1D = 2 PTUDxIF = 1 PTDDxIF= 0 Px_O/Px1_O PDCONx= 0 PDCONx= 1 Duty Zone Figure16-12 PWM Original Waveforms in Single Counting and Complementary Output Mode In the independent output mode, after PWMOE is set to 1, the Px_O and Px1_O waveforms change to be high (PDCONx = 0), and the Px_O waveform will be low after the PWM counter is matched with PWMxD during up-count operation. After the PWM counter is matched with PWMx1D during up-count operation, the Px1_O waveform will be low.

16.3.2.8 Duty Cycle Definition and Automatic Reloading of Duty Cycle Register

As shown in Figure 16-6, the six duty cycle registers all have corresponding buffer registers. The 16-bit PWM counter is actually compared with BUFFER to control the change of the original PWM waveform. The user can read and write six duty cycle registers but cannot operate their corresponding cache registers. This can be seen in conjunction with Figures 16-2 and 16-6. The PDCONx (x=0-2) bit segment in the PWMCON2 register also have buffer registers, and the user can read and write the PDCONx bit segment but cannot operate their buffer registers, as shown in Figure 16-6. Due to the presence of the buffer register, as with the periodic register, there are special provisions for the duty cycle definition and the reading and writing of the duty cycle register: When the value of the PWMRLDEN register is 0x55, the duty cycle definition and the duty cycle register are allowed to be modified. Then, only when the value in the PWMRLDEN register is 0xAA, and when the divided zero matching signal occurs, the duty cycle definition and duty cycle registers are latched into the corresponding buffer registers to avoid reloading during register modification process and to avoid glitches when register modifications take effect immediately. Therefore, the modification of the above registers must come with the cooperation of the PWMRLDEN register to complete. For the zero matching signals, if the PDLDEN bit in PWMCON2 is 1, the divided cycle matching signal will also automatically latch the duty cycle definition and six duty cycle registers into the corresponding buffer registers. Therefore, in the edge counting mode and the single counting mode, since the time base module only has a zero matching signal, each time the PWM counter is reset from 1 to 0, a reloading of duty cycle definition and duty cycle register will occur. In the center-aligned counting mode, the time base module can generate zero matching and periodic match signal, so the PWM counter can reload the duty cycle definition and the duty cycle register each time it is reset to 0 and matched with the period register.

16.3.2.9 PWM Duty Cycle Interrupt

When the PWM0/1/2 time base counter is counting up, the PTUDxIF bit in the PWMINTF register can be set to 1 when the count value is matched with the duty cycle register PWMxD, in any mode. If the PTUDxIE bit in the PWMINTEN register is 1, the duty cycle interrupt can be triggered, as shown in Figure 16-7/Figure 16-9. In the center-aligned counting mode, when the PWM time base counter is counting down, the PTDDxIF bit in the PWMINTF register will be set to 1 when the count value is matched with PWMxD. At this time, if the PTDDxIE bit in the PWMINTEN register is 1, the duty cycle interrupt can be triggered, as shown in Figure 16-9. Note 1: In complementary symmetrical output mode and independent output mode, the duty cycle interrupt is only generated when the PWM counter is compared with PWMxD-related. When it is matched with PWMx1D-related, the duty cycle interrupt flag will not be changed. Note 2: In complementary asymmetric output mode, the duty cycle interrupt is generated when the PWM counter is compared with PWMxD-related during up-count operation, and is generated when the PWM counter is compared with PWMx1D-related during down-count operation. Note 3: When the duty cycle is set to 0 or cycle, both the PTUDxIF bit and the PTDDxIF bit are set to 1.

16.3.2.10 PWM0/1/2 Duty Cycle Register Update Mode

The six duty cycle registers PWMxD and PWMx1D can achieve immediate updates and fixed time (periodic and zero matching) updates. When DILDEN@PWMCON2=1, the setting values of PWMxD and PWMx1D are modified. After this value is reloaded, it will be directly updated to the buffer register, meanwhile the buffer running function will not change. When DILDEN@PWMCON2=0, the setting values of PWMxD and PWMx1D are modified. The way in which this value updates the buffer register is controlled by the PDLDEN and ZDLDEN bits of the PWMCON2 register. Note: When DILDEN@PWMCON2=1, the duty cycle register is also controlled by the PDLDEN and ZDLDEN bits of the PWMCON2 register, and the update method of the dead-zone and PDCONx registers is still controlled by these two bits. In the immediate update mode, according to the relationship between PWM count value and the old and new setting values of the duty cycle register when PWMxD and PWMx1D registers are written, the processing results are as follows: (a) (b) (c) (e) (f) (g) PWMxD/PWMx1D (new) PWMxD/PWMx1D (old) Px_O/Px1_O PWMxD/PWMx1D (old) Px_O/Px1_O PWMxD/PWMx1D (new) PWMxD/1D changed PWMxD/1D changed PWMxD/1D changed PWMxD/1D changed PWMxD/1D changed PWMxD/1D changed Figure16-13 PWMxD and PWMx1D Register Updates for the up-count operation Process (x=0~2)

(a) (b) (c) (e) (f) (g) PWMxD/PWMx1D (new) PWMxD/PWMx1D (old) Px_O/Px1_O PWMxD/PWMx1D (old) Px_O/Px1_O PWMxD/PWMx1D (new) PWMxD/1D changed PWMxD/1D changed PWMxD/1D changed PWMxD/1D changed PWMxD/1D changed PWMxD/1D changed Figure16-14 PWMxD and PWMx1D Register Updates for the down-count operation Process (x=0~2) Note 1: Immediately update the logical processing when the dead zone occurs. Note 2: All duty cycle registers are valid after reloading, which means after writing PWMRLDEN to 0xAA.

16.3.2.11 Event Triggered Register Update Mode

Four PWM event trigger registers PWMCMPx, can achieve immediate updates and fixed moment (periodic and zero matching) updates. When CILDEN@PWMCON2 =1, the setting value of PWMCMPx is modified. After this value is reloaded, it will be directly updated to the buffer register, and the buffer running function will not change. When CILDEN@PWMCON2 =0, the setting value of PWMCMPx is modified. The way this value updates the buffer register is controlled by the PCMLDEN and ZCMLDEN bits of the PWMCON2 register.

16.3.3 PWM Dead-Zone and Polarity Logic Module

As shown in Figure 16-1, the PWM original waveform Px_O/Px1_O generated by the wave generator generates the final PWM waveform Px_D/Px1_D through the dead-zone & polarity logic module. The output control logic and fault detect logic modules determine whether the PWM signal Px_D/Px1_D with dead zone and polarity is sent by pin PWMx/PWMx1 (x = 0 - 2) or not. The logic diagram of the polarity control module is shown in Figure 16-15. Px_D Px1_D Px_O Px1_O 1[ ] PWMx/x1Dead & Polarity Logic POUTMOD@PWMCON1 1[ ] Rising Edge Delay Falling Edge Delay PWMDT1x BUFFER PWMDT0x BUFFER PWMxS@PWMCON1 PWMxS@PWMCON1 Figure16-15 Dead-Zone & Polarity Control Logic Diagram

16.3.3.1 Implementation of PWM Dead Zone

As shown in Figure 16-15, the dead-zone logic is implemented by delaying the rising edge of the PWM original signal Px_O and the falling edge of Px1_O for a period of time. When the POUTMOD bit in the PWMCON1 register is 1, the PWM original signal Px_O/Px1_O will not go through the dead-zone logic, which means when the PWMx/PWMx1 pin output is in independent mode, there is no dead zone. When the POUTMOD bit in the PWMCON1 register is 0, the PWM original signal Px_O/Px1_O will go through the dead-zone logic, which means when the PWMx/PWMx1 pin is in complementary mode, dead zone will be introduced. The dead time is determined by the registers PWMDT0x and PWMDT1x: Rising Edge Delay = PWMDT0x * TPWM CLOCK Falling Edge Delay = PWMDT1x * TPWM CLOCK Under different polarity settings, the PWM waveform will be different after inserting dead zone. For details, see the chapter "PWM Wave with Dead Zone in Different Polarity Settings". Note: When PWMDT0x = 0, the rising edge of the original PWM waveform Px_O will not trigger the delay; when PWMDT1x = 0, the falling edge of the original PWM waveform Px1_O will not trigger the delay.

16.3.3.2 PWM Polarity Setting

In order to effectively describe the polarity of the waveform on the PWM pin, a PWM period is devided into "Duty Zone" and "Non-Duty Zone". In various time base counting modes, the division of the duty zone and the non-duty zone is shown in Figure 16-7 to Figure 16-11. The levels of the duty zone periods Px_D and Px1_D are determined by the bits PWMxS/PWMx1S in the register PWMCON1. PWMxS controls the polarity of Px_D. When PWMxS = 0, the duty zone period of Px_D is at high level, and the non-duty zone period is at low level; when PWMxS = 1, the duty zone period of Px_D is at low level, and the non-duty zone period is at high level. PWMx1S controls the polarity of Px1_D. When PWMx1S = 0, the duty zone period of Px1_D is at low level, and the non-duty zone period is at high level; when PWMx1S = 1, the duty zone period of Px1_D is at high level, and the non-duty period is at low level. Combine with the PWM original waveform Px_O/Px1_O shown in Figure 16-7 to Figure 16-11 as well as Figure 16-15, the implementation of dead-zone and polarity can be clearly reflected.

16.3.3.3 Automatic Reload of Dead Zone and Dead-Zone Mode Selection bit Segment

The PWM dead zone is also the same as duty cycle and period, coming with its own buffer register . The automatic reload function is similar to the automatic reload of duty cycle and can be reloaded when the periodic matching and zero matching signals occur. Modifications to the dead-zone registers must also be made when the value of the PWMRLDEN register is 0x55, and then the reload takes effect only when the value in the PWMRLDEN register is 0xAA.

16.3.3.4 PWM Waveforms with Dead Zone under Different Poliarity Settings

Figure 16-16 shows a pair of waveforms which is set to complementary output mode by PWM outputs Px_D/Px1_D, and comes with dead zone under all polarity combinations.

Px_O Px1_O Px_O with Rising Edge Delayed Px1_O with Falling Edge Delayed Px_D,PWMxS=0 Px1_D,PWMx1S=0 CASE1:Default Px_D,PWMxS=0 CASE2 Px_D,PWMxS=1 CASE3 Px_D,PWMxS=1 CASE4 Px1_D,PWMx1S=1 Duty Zone One PWM Period None-Duty Zone None-Duty Zone DR DF Figure16-16 Edge Aligned Counting Mode Note: DR in the figure indicates the rising edge dead zone, DF indicates the falling edge dead zone, and the three-phase rising edges and falling edges dead zone are set to the same value.

16.3.3.5 PWM0/1/2 Output Control & Fault Detection

PWM output control logic & fault detect logic is used to determine whether the final PWM waveform Px_D is output on the PWMx pin and whether Px1_D is output on the PWMx1 pin. The logic diagram of the output control module and fault detection module is shown in Figure 16-17.

PMANUALy@PMANUALCON1 POUTy@PMANUALCON2 AF(GPIO) Py_D PWMy Output Control logic Fault_Signal FLTSTAT Fault Dealing logic x stands for 0,1,2 y stands for 0 or 01 when x=0 y stands for 1 or 11 when x=1 y stands for 2 or 21 when x=2 PWMEN@PWMOE High Impedance MCMFLT FLTxEN Figure16-17 Output Control and Fault Detection Logic Diagram

16.3.4 PWM Fault Detection Mode

The PWM module has a fault detection logic. When the FLT1EN bit or the FLT2EN in the FLTCON register is 1, the function of this module is enabled. If both FLT1EN and FLT2EN are 0, the function of this module is disabled. The main purpose of PWM fault detection is: when the fault occurs (such as over current), the PWM output can be cut off, and the invalid drive state can be entered (can be set to high level, low level and high resistance state), thereby achieving the purpose of protecting the external power device. Because it is controlled by hardware, its response is very fast. The logic diagram of the fault detection module is shown in Figure 16-17. Combined with the output control logic, the aforementioned protection functions can be implemented. Note 1: When the MCM module clock is turned off , fault protection can also work normally. Note 2: When protection occurs, if the fault is recovered, the PWM output will be restored when periodic matching or zero matching occurs.

16.3.4.1 Selection of Fault Signal Input Source

The output of the comparator (1/2/3) or the FLT pin input can be selected as the fault detection input signal, as shown in Figure 16-17. Regardless of whether the fault signal comes from the comparator 1/2/3 output or FLT, the high level is the valid fault signal, which means the output of the comparator is automatically cut off when the comparator output goes from low to high. As shown in Figure 16-17, if FLT1EN = 1, the output of comparator 1 or 2 or 3 will be used as the fault detection input signal. Once the output of the comparator goes higher and the filter time is maintained (described in the next section), the 6 channel PWM pins PWMx/PWMx1 immediately enter the invalid drive state (x = 0 - 2). Similarly, if FLT2EN = 1, the FLT pin input is used as the fault detection input signal. Once the FLT pin input goes higher (FLT2S = 0) and the filter time is maintained, the 6 channel PWM pins PWMx/PWMx1 immediately enter the invalid drive state (x = 0 - 2). If FLT2EN = 0, the fault detection function of the FLT pin is then forbidden, and the FLT pin is used as normal IO (but the comparator's fault detection function is not affected). When using the PWM module to control the inverter bridge shown in Figure 16-18, the six tubes are high-level driven power tubes. Set PWMxS/PWMx1S = 0 (x = 0 - 2), then PWM0/1/2 output is at high level during the duty zone period, and the output of PWM01/11/21 is at low level during the duty zone period (see the chapter "Setting the PWM Polarity"). Set the POUTMOD bit in the PWMCON1 register to 0, which means complementary output with PWM0 and PWM01, complementary output with PWM1 and PWM11, complementary output with PWM2 and PWM21. After the fault detection is enabled, if a fault occurs, the 6 channel PWM enters the invalid drive state (can be set to high level, low level, and high resistance state). VDC PWM0 PWM01 PWM1 PWM11 PWM2 PWM21 Figure16-18 Example of PWM Control Inverter Bridge

16.3.4.2 Filtering of the Signal on FLT Pin and the Output Signal of the Comparator

When FLT2EN = 1, the input signal of the FLT pin is used as the fault detection input signal. At this time, the filter time of this signal can be set by the FLT2DEB[3:0] bit segment in the FLTCON register. When FLT2DEB[3:0] = 0, there is no filtering effect. When FLT2S = 0, protection is immediately triggered when the level of fault detection input signal goes high level from low level. When FLT2DEB[3:0] = 0 - 15, the filter time can be set to 0~32us and 16 stages in total, when fault detection input signal goes high level from low level, being at high level needs to maintain at least the length of time defined by FLT2DEB[3:0], then the fault detection module will consider that the level of the fault detection input signal becomes higher, thereby triggering protection. When the level of the fault detection input signal goes low level from high, being at low level needs to maintain at least the length of time defined by FLT2DEB[3:0], then the fault detection module will consider that the effective fault level on the FLT pin has disappeared, and the output of the 6 channel PWM is acting based on the protection mode (introduced in the next section). When FLT2S = 1, the FLT fault detection signal becomes low-level valid, as opposed to the situation when FLT2S = 0. According to the characteristics of the power tube, properly set filtering time can filter out the noise on the fault detection input signal. The description of filter time setting is as follows: (1) The upper limit of the counter is set to the filter constant, the lower limit is 0. If the upper and lower limits are exceeded, adding and subtracting operations are not performed. (2) Filter counter initial value setting: if the FLT pin is set to high level valid, the initial value of the counter is 0; if the FLT pin is set to low level valid, the initial value of the filter counter is set to the filter constant. (3) The filter output stabilization requires a settling time, roughly the time set by the filter constant. If the filter constant is set to 256, the filter output is stable after 256 system clocks, and before that, the filter output is undefined.

When FLT1EN = 1, the output signals of the comparators 0 and 1 can be selected and used as the fault detection input signal. When the comparator output changes from 0 to 1, the protection is triggered. At this time, the output filtering time and algorithm of the comparators 0 and 1 are set in registers CMP0CON and CMP1CON respectively. (See the Operational Amplifier and Comparator Modules chapter for details)

16.3.4.3 Protection Mode

There are two fault detection modes: latch mode and sequential mode. (1) Fault protection status After fault protection, invalid level state is entered immediately, and invalid level can output high resistance state, high level and low level. (2) Latch mode FOUTx@FLTCON. If the valid fault signal does not disappear, the 6 channel PWM pins PWMx/PWMx1 will maintain the set level state of the output FLTCON.FOUTx (x = 0, 1). The software cannot clear the FLTSTAT flag bit and the 6 channel PWM pins cannot restore normal output. When the valid fault signal disappears, the 6 channel PWM pins PWMx/PWMx1 (x = 0 - 2) will not return to normal output, either. Only after the FLTSTAT bit is cleared by software to 0, PWMx/PWMx1 will return to normal output at the most recent time when PWM counter returns to 0 or matches with the value of the periodic register PWMP after FLTSTAT is cleared. (In the edge-aligned mode, the output is restored when the PWM counter returns to 0. In the center-aligned mode, the output is restored when the PWM register matches with the periodic register PWMP or returns to 0. ). (3) Sequential mode Setting the FLTM bit in the FLTCON register to 1 will enable the sequential mode. In the sequential mode, whether the PWMx/PWMx1 pin outputs the PWM waveform is directly controlled by the output signal filtered by the comparator. The FLTSTAT bit is also directly controlled by the filtered fault signal. If the filtered fault signal is high, the FLTSTAT bit is 1; if the filtered fault signal is low, the FLTSTAT bit is 0. When the fault detection module detects a valid fault signal, the 6 channel PWM pins PWMx/PWMx1 immediately output invalid level state (x = 0 - 2), and the FLTSTAT bit is also set to 1 by hardware. If the valid fault signal does not disappear, the 6 channel PWM pins PWMx/PWMx1 will maintain outputting invalid level state (x = 0 - 2), and the software cannot restore the 6 channel PWM pins to normal output. When the valid fault signal disappears, the 6 channel PWM pins PWMx/PWMx1 (x = 0 - 2) will automatically return to normal output at the most recent time when PWM counter returns to 0 or matches with the value of the period register PWMP after the valid fault signal disappears, and the FLTSTAT bit will also be returned to zero. Note: Before the PWM is turned on for the first time (including system power-on), the PWM output is fixed to a high resistance state.

16.3.4.4 Fault Protection Interrupt

When fault protection occurs, interrupt can be placed and the interrupt routine can be entered.

16.3.5 PWM Exception Protection

MCM module can protect the output level. When the upper and lower bridges simultaneously output the set valid level, PWM enters exception protection. In addition, clock vibration stop can be detected. After the external crystal oscillator stops, PWM enters exception protection. When exception protection occurs, the PWM output state can be set to high level, low level, and high resistance state.

16.3.5.1 PWM Output Level Exception Protection

First, set the valid level of PWM protection. In the PWM output pin set by the PWM output enable register (PWMOE) enable bit, when the upper and lower bridges simultaneously output the PWM valid level set by OLSGxx@POSCR, the exception flag bit is set up. The PWM output state after protection can also be selected. The FOUT0@FLTCON and FOUT1@FLTCON settings can be used to select the output as high level, low level and high resistance state. As shown in the figure below, the valid level is set to low level, and high resistance state is output after output protection.

Figure16-19 PWM Output Level Comparison Note: If only 3 lower bridge outputs or 3 upper bridge outputs are set, the output level exception protection will never occur

16.3.5.2 Oscillator Exception Protection

If an external oscillator exception is detected (see CSM chapter), the exception flag is set up and whether the PWM output pin state set by the PWM output enable register (PWMOE) enable bit is set to the protection level can be selected. The PWM protection level can be set to high level, low level and high resistance state, set via FOUT0@FLTCON and FOUT1@FLTCON.

16.3.5.3 Exception Protection Recovery

The exception protection can be restored by system reset, module reset or clearing corresponding protection flag. Note 1: During level exception protection, when it is at level exception, even if 0 is written to the error flag, the flag bit cannot be cleared. Note 2: The exception protection can also work normally when the MCM module clock is turned off.

16.3.5.4 Exception Protection Interrupt

When exception protection occurs, interrupt can be set up and the interrupt routine can be entered.

16.3.6 PWM Output Control Module

16.3.6.1 PWM Output Pin and IO Function Multiplexing

The PWM pin PWMx/PWMx1 is multiplexed with the IO function (x = 0 - 2) and is controlled by the I/O multiplex register, as shown in Figure 16-17.

16.3.6.2 Manual Control PWM Output

When the PWMOE bit is 1, if the PMANUALx/PMANUALx1 bit in the PMANUALCON1 register is 1, the PWMx/PWMx1 pin will output the value of the POUTx/POUTx1 bit in the PMANUALCON2 register; if the PMANUALx/PMANUALx1 bit in the PMANUALCON1 register is 0, then The PWMx/PWMx1 pin will output the PWM waveform Px_D/Px1_D. This function is similar to the output function of the PORT port. The only difference is that in the manual control PWM output mode, its output is controlled by the PWM fault detection input signal, and in the I/O output mode, it is not controlled by this signal. The details are shown in Figure 16-17. When the PMANUALCON1 and PMANUALCON2 registers are changed, the PWMx/PWMx1 pin output changes are in synchronization with PCLK2, and the output state change takes effect immediately.

16.3.6.3 Output of PWM Pin When Time Base is Stopped

When the PWMOE bit is 0, the time base module will stop working, as shown in Figure 16-17.

16.3.7 Event Trigger Function

PWM events can trigger ADC, automatic reload, interrupt of registers.

16.3.7.1 PWM0/1/2 Counter Triggers ADC

If CMPx = 1 (x =1-4) in the PWMCON2 register, an ADC sequence conversion can be automatically triggered when the counter value is equal to the PWMCMPx (x =1-4) setting value during PWM counting (if the ADON and the corresponding bit in ADSTRS[6:0] of the ADCON1 register in ADC module are allowed, a sequence conversion will be initiated); CMPx = 2 (x =1-4), then only when the counter value is equal to the PWMCMPx (x =1-4) setting value during PWM up-count operation, an ADC sequence conversion can be automatically triggered (if the ADON and the corresponding bit in ADSTRS[6:0] of the ADCON1 register in ADC module are allowed, a sequence conversion will be initiated); CMPx = 3 (x =1-4), then only when the counter value is equal to the PWMCMPx (x =1-4) setting value during PWM down-count operation, an ADC sequence conversion can be automatically triggered (if the ADON and the corresponding bit in ADSTRS[6:0] of the ADCON1 register in ADC module are allowed, a sequence conversion will be initiated). The PWM compare register triggering AD signal is also controlled by the post-division coefficient. PWM CLK PWMx PWMx 1 Low level overlap detection High resistance state

16.3.7.2 Compare Register X and Its Startup AD Control Bit(PWMCON2.CMPx[1:0] CMPx[1:0]@PWMCON2) Automatic Reload Same as the periodic and duty cycle registers, the compare value register also has its corresponding buffer register . When the compare value register is allowed to be modified, then only when the value in the PWMRLDEN register is 0xAA, the compare value register is latched in the corresponding buffer register when the divided zero matching signal occurs. This can avoid reloading during register modification, and avoid glitch when register modification takes effect immediately. Therefore, the modification of the above registers must come with the cooperation of the PWMRLDEN register to complete. The compare value register can select whether to reload with the zero matching signals. If set the ZCMLDEN bit in PWMCON2 to 1, the divided zero matching signals will automatically reload the compare value register into the corresponding buffer register). For zero matching signals, if the PWMLDEN bit in PWMCON2 is 1, the divided periodic matching signal will automatically reload the compare value register into the corresponding buffer register reload. Therefore, in the edge counting mode and the single counting mode, since the time base module only has zero matching signal, a reload of the compare value register occurs every time the PWM counter is reset to 0; in the center-aligned counting mode, the time base module can generate zero matching signal and periodic matching signal, so the compare value register is reloaded each time PWM counter is reset to 0 and matches with the periodic register. The reload of CMPx(x=1-4) in PWMCON2 is also controlled by the zero matching signal or the periodic matching signal.

16.3.7.3 Interrupt Summary of PWM Module

The PWM module interrupt includes the PWM counter zero matching interrupt generated by the time base module, the periodic interrupt generated when the PWM counter value matches with the periodic register (see the “Time Base Interrupt” chapter) and the duty cycle interrupt generated when the PWM counter value matches with the duty cycle register PWMxD (x = 0 - 2) (see the section "Duty Cycle Interrupts"). In addition, PWM module interrupt includes PWM Fault interrupt、PWM Output Level Exception Protection interrupt and Oscillator Exception Protection interrupt.

16.3.8 PWM Duty Cycle Saturation Function

The saturation module has a compare output function. When the saturation function is set (STATEN@PSCON is 1), the value of the PWMxD (x=0, 1, 2, 01, 11, 21) register is written (after buffering). The start-up bit is turned on, and the start-up bit is automatically cleared after this function is completed. First compare the values of PWMxD (x=0, 1, 2, 01, 11, 21) and PWMDMAX registers, and select the compare output PWMxD value by setting the [MaxSelect] selection bit in the PSCON register (x=0, 1, 2, 01, 11, 21). Then compare the values of the two registers PWMxD (x=0, 1, 2, 01, 11, 21) and PWMDMIN, and select the compare output value by setting the MINSELECT@PSCON selection bit. The specific implementation is as follows: Figure16-20 Saturation Function Diagram P WMDMAX PWMxD P WMDMIN PWMxD MAXSELECT @ PSCON MAXSELECT [ 1 : 0 ] 00 : No compare function 01 : When PWMxD is greater than or equal to PWMDMAX, P WMDMAX is output 1 x : When PWMxD is greater, periodic register PWMP is output MINSELECT @ PSCON : No compare function 01 : When PWMxD is smaller, PWMDMIN is output 1 x : When PWMxD is smaller, 0 is output MINSELECT [ 1 : 0 ] PWMP Note: With any setting, when PWMxD is smaller, PWM is output Note: With any setting, when PWMxD is greater, PWM is output

16.3.9 PWM Phase Shift Function

In the motor control single shunt plan, when the difference between two duty cycles with adjacent size of the given three duty cycles is less than a certain value, the two-phase current value sampling cannot be achieved. With the PWM phase shift function, the phase shift can be done automatically to meet the time required for two-phase current sampling. The phase shift start-up bit is turned on, and the start-up bit is automatically cleared after the function is completed. The system block diagram is as follows: SECTOR@PSCON Max-Med-Min 0: 2D>=1D>=0D 1: 2D>=0D>=1D 2: 0D>=2D>=1D 3: 0D>=1D>=2D 4: 1D>=0D>=2D 5: 1D>=2D>=0D CMP2=Med-Min PWM01D PWM11D PWM21D PWM0D PWM1D PWM2D output: Max Med Min Saturation modulePWM0D Saturation modulePWM1D Saturation modulePWM2D output: CMP1=Max-Med Max Max1 Med Med1 Min Min1 SECTOR@PSCON PWMDCMP1 PWMDCMP2 SHIFT MODULE Max/Max1- Med/Med1- Min/Min1 0: 2D/21D- 1D/11D-0D/01D 1: 2D/21D- 0D/01D-1D/11D 2: 0D/01D- 2D/21D-1D/11D 3: 0D/01D- 1D/11D-2D/21D 4: 1D/11D- 0D/01D-2D/21D 5: 1D/11D- 2D/21D-0D/01D SECTOR Figure16-21 PWM Phase Shift Function Diagram The phase shift function is turned on by the SHIFTRUN@PSCON start-up bit. Firstly, the maximum value, the intermediate value and the minimum value duty cycle are distinguished according to the quadrant, and then processed by the shift module to obtain the three duty cycle values after shifting. And then according to the quadrant relationship, the two duty cycle registers PWMxD and PWMx1D of the asymmetric PWM are given, and the output asymmetric PWM wave achieves the phase shift function.

16.3.9.1 Quadrant Selection Module

The motor rotates to different sectors, and the PWM three-phase duty cycle (PWM0D, PWM1D, and PWM2D) shall have different size relationships. Therefore, the PWM three-phase duty cycle size should be judged according to SECTOR@PSCON, with the correspondence shown in Figure 16-23. The value of the comparison result BUFFER is given via the size order duty cycle register Buffer, and all of the data is output to the shift module.

16.3.9.2 Shift Module

The shift module is mainly used to output different asymmetric duty cycles by judging the size of comparison result BUFFER value and the comparison register value, and the achieving block diagram is as follows:

(CMP1>=PWMDCMP1) (CMP2>=PWMDCMP2) (CMP1+CMP2)>=(PWMDCMP1+PWMDCMP2) No Yes No CMP1>=PWMDCMP1 CMP1>=PWMDCMP1 Part 1: ... Part 2: ... Min1=Min +(PWMDCMP2- CMP2) Min=Min -(PWMDCMP2- CMP2) Max=Max Max1=Max Med=Med Med1=Med OVER@PSCON = 0 Med1=Med+(PWMDCMP1- CMP1) Med=Med-(PWMDCMP1-CMP1) Min1=Min+(PWMDCMP1- CMP1)+(PWMDCMP2-CMP2) Min=Min-(PWMDCMP1-CMP1)- (PWMDCMP2-CMP2) Max=Max Max1=Max OVER@PSCON = 0 Yes No Yes No Max=Max Max1=Max Med=Med Med1 =Med Min=Min Min1=Min OVER@PS CON = 0 Yes Figure16-22 PWM Phase Shift Achieving Diagram

Med1 =0 Med =2*Med Max=Max Max1=Max Min1=Min+(PWMDCMP2-CMP2-Med) Min=Min-(PWMDCMP2-CMP2-Med) OVER@PSCON = 0 Med> (PWMDCMP2-CMP2) Med1 =Med-(PWMDCMP2- CMP2) Med =Med+(PWMDCMP2- CMP2) Max=Max Max1=Max Min=Min Min1=Min OVER@PSCON = 0 Yes No Min> (PWMDCMP2-CMP2- Med) Med1 =0 Med =2*Med Max=Max Max1=Max Min1=Min*2 Min=0 OVER@PSCON = 1 Yes No Figure16-23 PWM Phase Shift Achieving Diagram Part1

Med1=PWMP Med =Med-(PWMP-Med) Max=PWMP Max1=Max-(PWMP-Max) Min=Min Min1=Min OVER@PSCON = 1 PWMP<(Med+ (PWMDCMP1-CMP1)) Yes Med1=Med+(PWMDCMP1- CMP1) Med =Med-(PWMDCMP1- CMP1) Max=Max Max1=Max Min=Min Min1=Min OVER@PSCON = 0 Med1=PWMP Med =Med-(PWMP-Med) Max1=Max-(PWMDCMP1- CMP1-(PWMP-Med)) Max=Max+(PWMDCMP1- CMP1-(PWMP-Med)) Min=Min Min1=Min OVER@PSCON = 0 PWMP<(Max+PWMDCM P1-CMP1-(PWMP-Med)) No Yes No Figure16-24 PWM Phase Shift Achieving Diagram Part2

16.3.9.3 Saturated Phase Shift Application Example

Setting: MCM CLK frequency is 60Mhz, MCM frequency not divided, air conditioner compressor carrier frequency is 6K, then PWM periodic register PWMP = 5000, the output range is limited within (PWMDMIN~PWMDMAX) range, set MaxSelect@PSCON= 01b, MinSelect@PSCON=01b, PWMDMAX = 4500, PWMDMIN = 500, PWMDCMP1 = PWMDCMP2 = 500, the motor current running quadrant Sector = 4, the three-phase duty cycles are PWM0D = 4200, PWM1D = 4800 and PWM2D = 300 respectively. Set PSCON |= 0x101, first turn on the saturation phase shift function, then each register and BUFFER value of the intermediate process are: (passing through the saturation output) PWM0D = 4200, PWM1D = 4500, PWM2D = 500, then PDMaxBuffer = 4500, PDMumBuffer = 4200, PDMinBuffer = 500, CMP1BUFFER = 300, CMP2BUFFER = 3800. After passing through the shift module, PDMaxBuffer = 4500, PDMax1Buffer = 4500, PDMumBuffer = 4000, PDMum1Buffer = 4400, PDMinBuffer = 500, PDMin1Buffer = 500, then the six PWM duty cycle registers selected through sector are PWM0D = 4000, PWM01D = 4400, PWM1D = 4500, PWM11D = 4500, PWM2D = 500, PWM21D = 500. The original waveform is as follows:

t Figure16-25 PWM Waveform before Saturation Phase Shift

After saturation phase shift, the waveform is as follows: PWM0 PWM1 PWM2 PWMC 500 4000 4400 5000 t 4500 Figure16-26 PWM Waveform after Saturation Phase Shift Note 1: The start-up method of saturation and phase shift is that software writes start-up bit. After the calculation is completed, the bit is automatically cleared by hardware. Note 2: If the saturation and phase shift are started at the same time, the saturation process is performed first, and the phase shift process is performed after the end. Note 3: The register reload is reloaded after the PWMRLDEN writes 0xAA, and the saturation and phase shift start-up bits are 0. If the saturation or phase shift is running, it will be reloaded after the end of the run.

16.3.10 PWM Wave-by-Wave Current Limiting Function

16.3.10.1 Function Introduction

The wave-by-wave current limiting is entered, and the level after the wave-by-wave current limiting is determined according to OLSGx@POSCR (x=0, 1, 2, 01, 11, 21). For example, OLSG0@POSCR = 1, when the wave-by-wave current limiting occurs, the PWM0 pin outputs low level. The current limiting protection time can also be set via SCTIME@SCxCON[3:0] (x=1, 2, 3). Note: The wave-by-wave current limiting function and the fault detection module can be turned on at the same time.

16.3.10.2 Wave-by-Wave Current Limiting Function Application Example

Setting: MCM1 controls the motor, three-phase complementary with dead zone output PWM0, PWM1 and PWM2, the invalid levels are all low. SC1 protects PWM0, the protection time is set to 2400 PLCK (40us); SC2 protects PWM1, the protection time is set to 3600 PLCK (60us); SC3 protects PWM2, and the protection time is set to 4800 PLCK2 (80us). In the protection time for the waveform of the example, the thick dotted line part of the PWM output is the waveform under the assumption that there is no SC protection, and the solid line is the actual waveform after protection.

Figure16-27 Wave-by-Wave Current Limiting Application Example Wave-by-Wave current limiting SCx pin filtering configuration description: 1. The upper limit of the counter is set to 2 times the constant, the lower limit is 0. If the upper and lower limits are exceeded, the adding and subtracting operations are not performed. 2. Filter counter initial value setting: if the step-by-step current limiting pin is set to high level valid, the initial value of the counter is 0; if the step-to-step current limiting pin is set to low level valid, the initial value of the filter counter is set as the filter constant x2. 3. The filter output stabilization requires a settling time, roughly the time set by the filter constant. If the filter constant is set to 256, the filter output is stable after 256 system clocks. Before this, the filter output is uncertain.

16.3.11 Write Protection of PWM Register

16.3.11.1 Write Protection and Reloading of Normal Register

The PWM module registers, except for the interrupt flag register PWMINTF, as well as manual control registers PMANUALCON2, FLTCON, POSCR, and POSTDCR, have restrictions on modification of other registers. Software modification is allowed only when PWMRLDEN = 0x55, otherwise the modification is invalid. There are some registers in the PWM module with buffer registers, including the duty cycle register, periodic register, PWM clock pre-division register PWMPSQ, dead zone register and PWM event trigger register. Software modification is allowed only when PWMRLDEN = 0xAA, otherwise the modification is invalid. Note: The reload time of the register is as follows: 1. Registers with BUFFER and fixed to zero matching reset: periodic register PWMP, PWM clock pre-division register PWMPSQ, post-division register POTSTS[2:0]@ PWMCON1. 2. Registers with BUFFER, the reload point is zero matching and the cycle is settable: dead zone register PWMDTxx (xx = 00, 10, 20, 01, 11, 21), duty select register PDCONx@PWMCON1 (x = 0, 1, 2), PWMSYM@PWMCON1, CMPx@PWMCON2 (x=1~4). 3. Registers with BUFFER, the reload point is zero matching and the cycle and immediate update are settable: empty ratio registers PWMxD and PWMx1D (x = 0, 1, 2), PWM event trigger register PWMCMPx (x = 1, 2, 3, 4).

16.3.11.2 Write Protection of Protection Registers

The writing of protection registers of the PWM module, the fault detection register FLTCON, the exception protection registers POSCR and POSTDCR have restrictions. The software modification is allowed only when FLTWEN = 0x33CC, otherwise the modification is invalid.

16.3.12 Usage Notes

16.3.12.1 Value of the Duty Cycle Register in Edge-Aligned Mode Being 0 or Periodic Value

In the edge-aligned count mode, if the duty cycle register is 0 or period value, PWMx/PWMx1 should output a waveform with a duty cycle of 0% or 100% depending on the polarity setting. Let PWMOE = 1, PWMDT0x = 0, PWMDT1x = 0, in the edge-aligned time base count and complementary output mode, the waveform, interrupt flag trigger position, event trigger position and register reload position of the PWM pin output with different duty cycle values are shown in Figure 16-28 - Figure 16-30. Note: When the PWM time base is enabled, although the time base counter is 0, no zero matching signal will be generated, so the PWMZIF flag will not be set and the event trigger signal will not be generated, and the register reload signal occurs immediately when PWMOE= 0.

PWMP = 5 PWM Counter PWM Clock PWMx(PWMxS=0) Duty Zone None-Duty Zone PWMxD PWMZIF = 1 Reload PWMP& PWMx/x1D &DT[1:0]&PWMDT0/1 PWMxD PWMxD PWMx1(PWMx1S=0) PWMx(PWMxS=1) PWMxD PWMxD PWMxD PWMx1(PWMx1S=1) PWMxD = 3 PWMxD = 3 x = 0~2 PWMOE High Impedance High Impedance High Impedance High Impedance PWMZIF = 1 Reload PWMP& PWMx/x1D &DT[1:0]&PWMDT0/1 PWMZIF = 1 Reload PWMP& PWMx/x1D &DT[1:0]&PWMDT0/1 PTUDxIF = 1 PTDDxIF = 0 PTUDxIF = 1 PTDDxIF = 0 PTUDxIF = 1 PTDDxIF = 0 Figure16-28 Edge-Aligned Count and Complementary Output Mode

PWMP = 5 PWM Counter PWM Clock PWMZIF = 1 Reload PWMP& PWMx/x1D &DT[1:0]&PWMDT0/1 x = 0~2 PWMOE PWMZIF = 1 Reload PWMP& PWMx/x1D &DT[1:0]&PWMDT0/1 PWMZIF = 1 Reload PWMP& PWMx/x1D &DT[1:0]&PWMDT0/1 None-Duty Zone PWMx(PWMxS=0) PWMx1(PWMx1S=0) PWMxD = 0 PWMx outputs 0 PWMx1 outputs 1None-Duty Zone High Impedance High Impedance Figure16-29 Edge-Aligned Count, Complementary Output Mode and Duty Cycle = 0 PWMP = 5 PWM Counter PWM Clock PWMZIF = 1 Reload PWMP& PWMx/x1D &DT[1:0]&PWMDT0/1 x = 0~2 PWMOE PWMZIF = 1 Reload PWMP& PWMx/x1D &DT[1:0]&PWMDT0/1 PWMZIF = 1 Reload PWMP& PWMx/x1D &DT[1:0]&PWMDT0/1 Duty Zone PWMx(PWMxS=0) PWMx1(PWMx1S=0) PWMxD = PWMP PWMx outputs 1 PWMx1 outputs 0 Duty Zone High Impedance High Impedance Figure16-30 Edge-Aligned Count, Complementary Output Mode and Duty Cycle = Periodic Register

16.3.12.2 Value of the Duty Cycle Register in Center-Aligned Mode Being 0 or Periodic Value

In the center-aligned count mode, if the duty cycle register is 0 or period value, PWMx/PWMx1 should output a waveform with a duty cycle of 0% or 100% depending on the polarity setting. Let PWMOE = 1, PWMDT0x = 0, PWMDT1x = 0, in the edge-aligned time base count and complementary output mode, the waveform, interrupt flag trigger position, event trigger position and register reload position of the PWM pin output with different duty cycle values are shown in Figure 16-31 - Figure 16-33. 4PWMP=5 PWM Counter PWM Clock PWMx(PWMxS=0) None-Duty ZoneDuty Zone PWMxD PWMPIF=1 if(PDLDEN==1) {Reload PWMP& PWMx/x1D &DT[1:0]&PWMDT0/1} PWMxDPWMxD PWMxDPWMxD = 2 PWMx1(PWMx1S=0) PWMx(PWMxS=1) PWMxD = 2 PWMx1(PWMx1S=1) x = 0~2 None-Duty Zone High Impedance High Impedance High Impedance High Impedance PWMOE PWMPIF=1 if(PDLDEN==1) {Reload PWMP& PWMx/x1D &DT[1:0]&PWMDT0/1} PTUDxIF = 1 PTDDxIF = 0 PTUDxIF = 0 PTDDxIF = 1 PTUDxIF = 1 PTDDxIF = 0 PTUDxIF = 0 PTDDxIF = 1 PWMZIF = 1 Reload PWMP& PWMx/x1D &DT[1:0]&PWMDT PWMZIF = 1 Reload PWMP& PWMx/x1D &DT[1:0]&PWMDT Figure16-31 Center-Aligned Count and Complementary Output Mode

4PWMP=5 PWM Counter PWM Clock Duty Zone, PWMx outputs 0 Duty Zone, PWMx1 outputs 1 PWMPIF=1 if(PDLDEN==1) {Reload PWMP& PWMx/x1D &DT[1:0]&PWMDT0/1} PWMx(PWMxS=0) PWMxD = 0 PWMx1(PWMx1S=0) x = 0~2 PWMOE PWMZIF = 1 Reload PWMP& PWMx/x1D &DT[1:0]&PWMDT0/1 PWMPIF=1 if(PDLDEN==1) {Reload PWMP& PWMx/x1D &DT[1:0]&PWMDT0/1} PWMZIF = 1 Reload PWMP& PWMx/x1D &DT[1:0]&PWMDT0/1& High Impedance High Impedance Figure16-32 Center-Aligned Count, Complementary Output Mode and Duty Cycle = 0 4PWMP=5 PWM Counter PWM Clock Duty Zone, PWMx outputs 1 Duty Zone, PWMx1 outputs 0 PWMPIF=1 if(PDLDEN==1) {Reload PWMP& PWMx/x1D &DT[1:0]&PWMDT0/1} PWMx(PWMxS=0) PWMxD = PWMP PWMx1(PWMx1S=0) x = 0~2 PWMOE PWMZIF = 1 Reload PWMP& PWMx/x1D &DT[1:0]&PWMDT0/1 PWMPIF=1 if(PDLDEN==1) {Reload PWMP& PWMx/x1D &DT[1:0]&PWMDT0/1} PWMZIF = 1 Reload PWMP& PWMx/x1D &DT[1:0]&PWMDT0/1 High Impedance High Impedance Figure16-33 Center-Aligned Count, Complementary Output Mode and Duty Cycle = Period

16.3.12.3 Periodic Register Value Being 0

Regardless of the mode of the time base counter, if the periodic register is 0, PWM output is in high resistance state. At this point, all interrupt flags will not be generated and no event trigger signal will be generated, but reload signal will be generated.

16.3.12.4 PWM Output in Simulation Status

SH33F2801 supports online simulation. There is no difference between operating in simulation state and normal state. If the operating is stopped or running with single step in simulation state, the PWM output will switch to high resistance state, ensuring that the external power tube will not be triggered by mistake.

16.3.12.5 Waveform Output Status of PWM0/1/2 While Entering IDLE Mode

After entering IDLE mode, the PWM output port is not affected. For example, the PWM0 port originally outputs 1K square wave. After entering IDLE mode, it will continue to output 1K square wave. However, if the PWM0/1/2 interrupt is set, the IDLE mode will be awakened, continuing to execute the program after IDLE.

16.3.12.6 Waveform Output Status of PWM0/1/2 While Entering STOP Mode

When entering STOP mode, if the MCM module output is enabled, PWMOE is turned off, and the PWM output port will output high resistance state. Even if the PWM0/1/2 interrupt is set, the power-down mode cannot be awakened. The power-down mode must be awakened by other means. See the Power Management chapter for details. The software needs to open PWMOE after exiting STOP mode. Note: To avoid uncertainty in status after recovery from STOP mode, it is recommended that the software turns off the PWM before entering STOP, and reconfigure and turn on PWM after exiting STOP.

16.4 Register

MCM Module Register List (Base Address: 0x4002 0000) Address Register Name Description 0x4004 0400 PWMOE PWM output enable register 0x4004 0404 PWMCON1 PWM module control register 1 0x4004 0408 PWMCON2 PWM module control register 2 0x4004 040C PWMP PWM periodic register 0x4004 0410 PWMC PWM counting register 0x4004 0414 PWMPSQ PWM clock pre-division register 0x4004 0418 PWM0D PWM0 duty cycle register 0x4004 041C PWM1D PWM1duty cycle register 0x4004 0420 PWM2D PWM2duty cycle register 0x4004 0424 PWM01D PWM01duty cycle register 0x4004 0428 PWM11D PWM11duty cycle register 0x4004 042C PWM21D PWM21duty cycle register 0x4004 0430 PWMCMP1 Event trigger compare register 1 0x4004 0434 PWMCMP2 Event trigger compare register 2 0x4004 0438 PWMCMP3 Event trigger compare register 3 0x4004 043C PWMCMP4 Event trigger compare register 4 0x4004 0440 PWMDT00 PWM channel 0 rising edge dead zone control register 0x4004 0444 PWMDT01 PWM channel 0 falling edge dead zone control register 0x4004 0448 PWMDT10 PWM channel 1 rising edge dead zone control register 0x4004 044C PWMDT11 PWM channel 1 falling edge dead zone control register 0x4004 0450 PWMDT20 PWM channel 2 rising edge dead zone control register 0x4004 0454 PWMDT21 PWM channel 2 falling edge dead zone control register 0x4004 0458 PMANUALCON1 PWM0/1/2 manual output setting register 1 0x4004 045C PMANUALCON2 PWM0/1/2 manual output setting register 2 0x4004 0460 FLTCON PWM0/1/2 fault detection protection register

0x4004 0464 POSCR PWM0/1/2 output level protection control register 0x4004 0470 POSTDCR PWM0/1/2 oscillator stop detection protection control bit 0x4004 0474 PWMINTEN PWM interrupt enable control register 0x4004 0478 PWMINTF PWM interrupt flag and clear register 0x4004 047C PWMRLDEN Register modification and reload control register 0x4004 0480 PSCON PWM saturation/phase shift control register 0x4004 0484 PWMDMAX PWM duty cycle upper limit compare register 0x4004 0488 PWMDMIN PWM duty cycle lower limit compare register 0x4004 048C PWMDCMP1 PWM duty cycle phase shift minimum sampling interval register 1 0x4004 0490 PWMDCMP2 PWM duty cycle phase shift minimum sampling interval register 2 0x4004 0494 SC0CON Wave-by-wave current limiting pin 1 function selection register 0x4004 0498 SC1CON Wave-by-wave current limiting pin 2 function selection register 0x4004 049C SC2CON Wave-by-wave current limiting pin 3 function selection register 0x4004 04A0 FLTWEN Register modification and reload protection control register

16.4.1 PWM Output Enable Register (MCMx_PWMOE)

Offset Address: 0x0000 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Reserved PWMO E - RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Symbol Description 31 ~ 1 Reserved -

0 PWMOE MCM time base enable control bit (Note: PWM0/1/2 shares a time base)

0: Turns off the MCM (PWM0/1/2) time base 1: Turns on the MCM (PWM0/1/2) time base

16.4.2 PWM Module Control Register 1 (MCMx_PWMCON1)

Offset Address: 0x0004 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 POUT MOD POSTPS[2:0] PTMOD[1:0] PWMS YM PDCO PDCO PDCO PWM2 PWM1 PWM0 PWM2 S PWM1 S PWM0 S RW RW RW RW RW RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Symbol Description 31 ~ 16 Reserved -

15 POUTMOD PWM0/1/2 output mode (independent/complementary) control bit

0: The entire module is configured as 3-channel complementary output 1: The entire module is configured as 6-channel independent output 14 ~ 12 POSTPS[2:0] Post-division coefficient selection bit segment 000: No post-division function 001: Interrupt, reload signal and event trigger signal will be divided by 2 010: Interrupt, reload signal and event trigger signal will be divided by 3 011: Interrupt, reload signal and event trigger signal will be divided by 4 100: Interrupt, reload signal and event trigger signal will be divided by 5 101: Interrupt, reload signal and event trigger signal will be divided by 6 110: Interrupt, reload signal and event trigger signal will be divided by 7 111: Interrupt, reload signal and event trigger signal will be divided by 8 11 ~ 10 PTMOD[1:0] PWM counter working mode selection bit segment in PWM0/1/2 time base module 00: Edge-aligned counting mode, in which only zero matching will occur for the time base counter 01: Center-aligned counting mode, in which zero matching and periodic matching will occur for the time base counter 1x: Single count mode, in which only zero matching will occur for the time base counter

9 PWMSYM PWM waveform symmetry control bit (valid only for complementary

output in center-aligned count mode) 0: Complementary outputs symmetric PWM waveform 1: Complementary outputs asymmetric PWM waveform

8 PDCON2 PWM2/PWM21 original waveform DUTY zone control bit

0: Defined as DUTY zone when the counter value is less than the duty cycle register 1: Defined as DUTY zone when the counter value is greater than or equal to the duty cycle register

7 PDCON1 PWM1/PWM11 original waveform DUTY zone control bit

0: Defined as DUTY zone when the counter value is less than the duty cycle register 1: Defined as DUTY zone when the counter value is greater than or equal to the duty cycle register

6 PDCON0 PWM0/PWM01 original waveform DUTY zone control bit

0: Defined as DUTY zone when the counter value is less than the duty cycle register 1: Defined as DUTY zone when the counter value is greater than or equal to the duty cycle register

5 PWM21S PWM21 output active polar selection bit

0: PWM21 outputs low level in the Duty zone, and outputs high level in the remaining time 1: PWM21 outputs high level in the Duty zone, and outputs low level in the remaining time

4 PWM11S PWM11 output active polar selection bit

0: PWM11 outputs low level in the Duty zone, and outputs high level in the remaining time 1: PWM11 outputs high level in the Duty zone, and outputs low level in the remaining time

3 PWM01S PWM01 output active polar selection bit

0: PWM01 outputs low level in the Duty zone, and outputs high level in the remaining time 1: PWM01 outputs high level in the Duty zone, and outputs low level in the remaining time

2 PWM2S PWM2 output active polar selection bit

0: PWM2 outputs high level in the Duty zone, and outputs low level in the remaining time 1: PWM2 outputs low level in the Duty zone, and outputs high level in the remaining time

1 PWM1S PWM1 output active polar selection bit

0: PWM1 outputs high level in the Duty zone, and outputs low level in the remaining time 1: PWM1 outputs low level in the Duty zone, and outputs high level in the remaining time

0 PWM0S PWM0 output active polar selection bit

0: PWM0 outputs high level in the Duty zone, and outputs low level in the remaining time 1: PWM0 outputs low level in the Duty zone, and outputs high level in the remaining time

16.4.3 PWM Module Control Register 2 (MCMx_PWMCON2)

Offset Address: 0x0008 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Reserv ed PCML DEN ZCML DEN PDLDE N ZDLDE N CILDE N DILDE N OSYN C CMP4[1:0] CMP3[1:0] CMP2[1:0] CMP1[1:0] - RW RW RW RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 15 Reserved -

14 PCMLDEN During periodic matching for the PWM counter, reload event trigger

compare register (PWMCMPx, x=1, 2, 3, 4) and AD start-up mode register (CMP1~4[1:0]) enable bit (valid only in center-aligned count mode) 0: Reloading event trigger register (PWMCMPx, x=1, 2, 3, 4) is not allowed at the moment of periodic matching. 1: Reloading event trigger register (PWMCMPx, x=1, 2, 3, 4) is allowed at the moment of periodic matching.

13 ZCMLDEN During zero matching for the PWM counter, reload event trigger compare

register (PWMCMPx, x=1, 2, 3, 4) and AD start-up mode register (CMP1~4[1:0]) enable bit 0: Reloading event trigger register (PWMCMPx, x=1, 2, 3, 4) is not allowed at the moment of zero matching. 1: Reloading event trigger register (PWMCMPx, x=1, 2, 3, 4) is allowed at the moment of zero matching.

12 PDLDEN During periodic matching for the PWM counter, reload duty cycle dead

zone register enable bit (valid only in center-aligned mode) 0: Reloading duty cycle register and dead zone register is not allowed during periodic matching 1: Reloading duty cycle register and dead zone register is allowed during periodic matching Note: Regardless of the register setting, the PWM period register, post-division register, pre-division register are not reloaded during periodic matching.

11 ZDLDEN During zero matching for the PWM counter, reload duty cycle dead zone

0: Reloading duty cycle register and dead zone register is not allowed during zero matching 1: Reloading duty cycle register and dead zone register is allowed during zero matching Note: Regardless of whether this value is set or not, periodic register, post-division register and pre-division register are reloaded automatically during zero matching

10 CILDEN PWM event trigger compare register (PWMCMPx, x=1, 2, 3, 4) immediate

0: Reloading is disabled immediately 1: Reloading is enabled immediately

9 DILDEN PWM duty cycle register immediate reloading enable bit

0: Reloading is disabled immediately 1: Reloading is enabled immediately

8 OSYNC Manually modifies the PWMx/PWMx1 output synchronous bit: (manual

modification is achieved by setting the PMANUALCON1/2 register, any register modification and when it is valid are all controlled by this register) 0: Takes effect immediately after manual modification 1: Takes effect after manual modification periodic matches with PWM 7 ~ 6 CMP4[1:0] Compare register 4 AD start-up control bit 00: Does not trigger AD start-up 01: Triggers AD start-up as long as the PWM counter is equal to compare register 4 10: Triggers AD start-up only when the PWM counter is equal to compare register 4 during the up-count operation process (only valid in PTMOD = 01 center-aligned mode) 11: Triggers AD start-up as long as the PWM counter is equal to compare register 4 during the down-count operation process (only valid in PTMOD = 01 center-aligned mode) 5 ~ 4 CMP3[1:0] Compare register 3 AD start-up control bit 00: do not trigger AD start-up 01: Triggers AD start-up as long as the PWM counter is equal to compare register 3 10: Triggers AD start-up only when the PWM counter is equal to compare register 3 during the up-count operation process (only valid in PTMOD = 01 center-aligned mode) 11: Triggers AD start-up as long as the PWM counter is equal to compare register 3 during the down-count operation process (only valid in PTMOD = 01 center-aligned mode)

3 ~ 2 CMP2[1:0] Compare register 2 AD start-up control bit 00: do not trigger AD start-up 01: Triggers AD start-up as long as the PWM counter is equal to compare register 2 10: Triggers AD start-up only when the PWM counter is equal to compare register 2 during the up-count operation process (only valid in PTMOD = 01 center-aligned mode) 11: Triggers AD start-up as long as the PWM counter is equal to compare register 2 during the down-count operation process (only valid in PTMOD = 01 center-aligned mode) 1 ~ 0 CMP1[1:0] Compare register 2 AD start-up control bit 00: do not trigger AD start-up 01: Triggers AD start-up as long as the PWM counter is equal to compare register 1 10: Triggers AD start-up only when the PWM counter is equal to compare register 1 during the up-count operation process (only valid in PTMOD = 01 center-aligned mode) 11: Triggers AD start-up as long as the PWM counter is equal to compare register 1 during the down-count operation process (only valid in PTMOD = 01 center-aligned mode)

16.4.4 PWM Periodic Register (MCMx_PWMP)

Offset Address: 0x000C Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 PWMP[15:0] RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 16 Reserved - 15 ~ 0 PWMP[15:0] PWM periodic register

16.4.5 PWM Counting Register (MCMx_PWMC)

Offset Address: 0x0010 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 PWMC[15:0] RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

31 ~ 16 Reserved - 15 ~ 0 PWMC[15:0] PWM counting register Note 1: PWMC can only be written when counting is stopped, and can only be read at other times. Note 2: PWMC is cleared by hardware once when the module is stopped, and can be written afterwards. Note 3: If the module stop signal and the PWMC write signal come at the same time, the module stop signal has a higher priority.

16.4.6 PWM Clock Pre-Division Register (MCMx_PWMPSQ)

Offset Address: 0x0014 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 PWMPSQ[15:0] RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 16 Reserved - 15 ~ 0 PWMPSQ[15:0] PWM clock is (PCLK2/(PSQ[15:0]+1)) 16.4.7 PWM0 Duty Cycle Register (MCMx_PWMnD)(n=0..2) Offset Address: 0x0018 : 0x001C : 0x0020 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 PWMnD[15:0] RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 16 Reserved - 15 ~ 0 PWMnD[15:0] PWMn duty cycle register

16.4.8 PWM01 Duty Cycle Register (MCMx_PWMn1D)(n=0..2) Offset Address: 0x0024 : 0x0028 : 0x002C Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 PWMn1D[15:0] RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 16 Reserved - 15 ~ 0 PWMn1D[15:0] PWMn1 duty cycle register 16.4.9 Event Trigger Compare Register 1 (MCMx_PWMCMPn)(n=1..4) Offset Address: 0x0030 : 0x0034 : 0x0038 : 0x003C Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 PWMCMPn[15:0] RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 16 Reserved - 15 ~ 0 PWMCMPn[15:0] Event trigger compare register n

16.4.10 PWM Channel 0 Rising Edge Dead Zone Control Register (MCMx_PWMDT00)

Offset Address: 0x0040 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 PWMDTn0[15:0] RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 16 Reserved - 15 ~ 0 PWMDTn0[15:0] PWM channel n rising edge dead zone control register

16.4.11 PWM Channel 0 Rising Edge Dead Zone Control Register (MCMx_PWMDT01)

Offset Address: 0x0044 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 PWMDTn0[15:0] RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 16 Reserved - 15 ~ 0 PWMDTn0[15:0] PWM channel n rising edge dead zone control register

16.4.12 PWM Channel 0 Rising Edge Dead Zone Control Register (MCMx_PWMDT10)

Offset Address: 0x0048 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 PWMDTn0[15:0] RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 16 Reserved - 15 ~ 0 PWMDTn0[15:0] PWM channel n rising edge dead zone control register

16.4.13 PWM Channel 0 Falling Edge Dead Zone Control Register (MCMx_PWMDT11)

Offset Address: 0x004C Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 PWMDTn1[15:0] RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 16 Reserved - 15 ~ 0 PWMDTn1[15:0] PWM channel n falling edge dead zone control register

16.4.14 PWM Channel 0 Falling Edge Dead Zone Control Register (MCMx_PWMDT20)

Offset Address: 0x0050 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 PWMDTn1[15:0] RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 16 Reserved - 15 ~ 0 PWMDTn1[15:0] PWM channel n falling edge dead zone control register

16.4.15 PWM Channel 0 Falling Edge Dead Zone Control Register (MCMx_PWMDT21)

Offset Address: 0x0054 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 PWMDTn1[15:0] RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 16 Reserved - 15 ~ 0 PWMDTn1[15:0] PWM channel n falling edge dead zone control register

16.4.16 PWM0/1/2 Manual Output Setting Register 1 (MCMx_PMANUALCON1)

Offset Address: 0x0058 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Reserved PMAN UAL21 PMAN UAL11 PMAN UAL01 PMAN UAL2 PMAN UAL1 PMAN UAL0 - RW RW RW RW RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 6 Reserved -

5 PMANUAL21 PWM21 port output control bit

0: PWM21 port outputs PWM waveform 1: PWM21 port output is controlled by POUT21 bit in PMANUALCON2 register

4 PMANUAL11 PWM11 port output control bit

0: PWM11 port outputs PWM waveform 1: PWM11 port output is controlled by POUT11 bit in PMANUALCON2 register

3 PMANUAL01 PWM01 port output control bit

0: PWM01 port outputs PWM waveform 1: PWM01 port output is controlled by POUT01 bit in PMANUALCON2 register

2 PMANUAL2 PWM2 port output control bit

0: PWM2 port outputs PWM waveform 1: PWM2 port output is controlled by POUT2 bit in PMANUALCON2 register

1 PMANUAL1 PWM1 port output control bit

0: PWM1 port outputs PWM waveform 1: PWM1 port output is controlled by POUT1 bit in PMANUALCON2 register

0 PMANUAL0 PWM0 port output control bit

0: PWM0 port outputs PWM waveform 1: PWM0 port output is controlled by POUT0 bit in PMANUALCON2 register

16.4.17 PWM0/1/2 Manual Output Setting Register 2 (MCMx_PMANUALCON2)

Offset Address: 0x005C Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Reserved POUT2 POUT1 POUT0 POUT2 POUT1 POUT0 - RW RW RW RW RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 6 Reserved -

5 POUT21 When PMANUAL21 = 1, output level of PWM21 port is determined

0: Outputs 0 1: Outputs 1

4 POUT11 When PMANUAL11 = 1, output level of PWM11 port is determined

0: Outputs 0 1: Outputs 1

3 POUT01 When PMANUAL01 = 1, output level of PWM01 port is determined

0: Outputs 0 1: Outputs 1

2 POUT2 When PMANUAL2 = 1, output level of PWM2 port is determined

0: Outputs 0 1: Outputs 1

1 POUT1 When PMANUAL1 = 1, output level of PWM1 port is determined

0: Outputs 0 1: Outputs 1

0 POUT0 When PMANUAL0 = 1, output level of PWM0 port is determined

0: Outputs 0 1: Outputs 1 Note: When configuring the PMANUALCON1 register for the first time, the PMANUALCON2 register must be configured first and then the PMANUALCON1 register.

16.4.18 PWM0/1/2 Fault Detection Protection Register (MCMx_FLTCON)

Offset Address: 0x0060 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved FOUT1[1:0] FOUT0[1:0] Rese rved FLT0 STA TC FLT1 STA TC FLT2 STA TC - RW RW - WO WO WO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 FLT0 EN FLT0 S FLT0 M FLT0 STA T FLT1 EN FLT1 S FLT1 M FLT1 STA T FLT2DEB[3:0] FLT2 EN FLT2 S FLT2 M FLT2 STA T RW RW RW RO RW RW RW RO RW RW RW RW RO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 24 Reserved - 23 ~ 22 FOUT1[1:0] PWMx1 pin (three pins on lower bridge) output status selection bit after the fault occurs: 0x: Outputs high resistance state 10: Outputs low level 11: Outputs high level 21 ~ 20 FOUT0[1:0] PWMx pin (three pins on upper bridge) output status selection bit after the fault occurs: 0x: Outputs high resistance state 10: Outputs low level 11: Outputs high level

18 FLT0STATC FLT0 fault detection flag clearance bit

0: Invalid 1: Clear

17 FLT1STATC FLT1 fault detection flag clearance bit

0: Invalid 1: Clear

16 FLT2STATC FLT2 fault detection flag clearance bit

0: Invalid 1: Clear

15 FLT0EN Fault detection 0 function control bit

0: Fault detection 0 function is prohibited 1: Fault detection 0 function is turned on, comparator 0 can be selected as input source

14 FLT0S Fault detection 0 valid level selection bit

0: Fault detection 1 CMP0 output is valid on high level 1: Fault detection 1 CMP0 output is valid on low level

13 FLT0M Fault detection 0 unction mode selection

0: Latch mode, when the fault input is detected to be valid, FLTSTAT is set to 1 by hardware, PWM will stop output immediately, and the state will remain unchanged when the fault input becomes invalid. Only when FLTSTAT is cleared by software, the PWM waveform will resume output at the zero matching moment of the PWM time base counter or when it matches with the value of the periodic register PWMP. (FLTSTAT cannot be cleared by software when the fault input keeps being valid)

12 FLT0STAT Fault 0 detection flag bit

0: PWM0/1/2 module is in normal output state 1: Over current detected, PWM0/1/2 module is in stop output state. If it is in latch mode, it can be cleared by software and PWM output can be resumed. Note: The difference between FLTSTAT and FLTIF is that in successive mode, FLTSTAT will be cleared.

11 FLT1EN Fault detection 1 function control bit

0: Fault detection 1 function is prohibited 1: Fault detection 1 function is turned on, comparator 1 can be selected as input source

10 FLT1S Fault detection 1 valid level selection bit

0: Fault detection 1 CMP1 output is valid on high level 1: Fault detection 1 CMP1 output is valid on low level

9 FLT1M Fault detection 1 unction mode selection

0: Latch mode, when the fault input is detected to be valid, FLTSTAT is set to 1 by hardware, PWM will stop output immediately, and the state will remain unchanged when the fault input becomes invalid. Only when FLTSTAT is cleared by software, the PWM waveform will resume output at the zero matching moment of the PWM time base counter or when it matches with the value of the periodic register PWMP. (FLTSTAT cannot be cleared by software when the fault input keeps being valid) 1: Sequential mode, the PWM output is directly controlled by the fault detection input port. If the fault input is valid, FLTSTAT is set to 1 by hardware and the PWM output is immediately turned off. If the fault input becomes invalid, FLTSTAT is automatically cleared to 0, and the PWM0/1/2 waveform will automatically resume output when the PWM time base counter returns to

8 FLT1STAT Fault detection flag bit

0: PWM0/1/2 module is in normal output state 1: Over current detected, PWM0/1/2 module is in stop output state. If it is in latch mode, it can be cleared by software and PWM output can be resumed. Note: The difference between FLTSTAT and FLTIF is that in successive mode, FLTSTAT will be cleared. 7 ~ 4 FLT2DEB[3:0] Fault detection 2 input filter parameter selection 0000: no filtering 0001: 0.5us 0010: 1us 0011: 1.5us 0100: 2us 0101: 3us 0110: 4us 0111: 6us 1000: 8us 1001: 10us 1010: 12us 1011: 14us 1100: 16us 1101: 20us 1110: 24us 1111: 32us Note 1: The above filter constant time is not exact value and is for reference only. Note 2: Filter description: The input signal is sampled by the internal clock. If the sampling result is high level, the counter is incremented by 1, and the counter result exceeds the set constant, then when the filter outputs 1, the counter is simultaneously set to filter constant × 2; if the sampling result is low level, the counter is decremented by 1, and the counter result is less than the filter constant. Then when the filter outputs 0, the counter is simultaneously set to 0.

3 FLT2EN Fault detection 2 function control bit (note 1)

0: Fault detection 2 function is prohibited 1: Fault detection 2 function is turned on, the input source is FLT pin

2 FLT2S Fault detection 2 valid level selection bit

0: Fault detection 2 FLT input is valid on high level 1: Fault detection 2 FLT input is valid on low level

1 FLT2M Detection function mode selection

0: Latch mode, when the fault input is detected to be valid, FLTSTAT is set to 1 by hardware, PWM will stop output immediately, and the state will remain unchanged when the fault input becomes invalid. Only when FLTSTAT is cleared by software, the PWM waveform will resume output at the zero matching moment of the PWM time base counter or when it matches with the value of the periodic register PWMP. (FLTSTAT cannot be cleared by software when the fault input keeps being valid) 1: Sequential mode, the PWM output is directly controlled by the fault detection input port. If the fault input is valid, FLTSTAT is set to 1 by hardware and the PWM output is immediately turned off. If the fault input becomes invalid, FLTSTAT is automatically cleared to 0, and the PWM0/1/2 waveform will automatically resume output when the PWM time base counter returns to

0 FLT2STAT Fault detection flag bit

0: PWM0/1/2 module is in normal output state 1: Overcurrent detected, PWM0/1/2 module is in stop output state. If it is in latch mode, it can be cleared by software and PWM output can be resumed. Note: The difference between FLTSTAT and FLTIF is that in successive mode, FLTSTAT will be cleared. Note 1: Fault detection inputs 1 and 2 can be turned on at the same time. If any signal is valid, the PWM0/1/2 module output will be turned off.

16.4.19 PWM0/1/2 Output Level Protection Control Register (MCMx_POSCR)

Offset Address: 0x0064 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Reserved OLSE N Reserv ed OLSG2 OLSG1 OLSG0 OLSG2 OLSG1 OLSG0 - RW - RW RW RW RW RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 8 Reserved -

7 OLSEN Output level protection enable bit

0: Disabled 1: Enabled

6 Reserved -

5 OLSG21 Valid level setting bit of PWM21 in the output short circuit protection

0: Low level valid 1: High level valid

4 OLSG11 Valid level setting bit of PWM11 in the output short circuit protection

0: Low level valid 1: High level valid

3 OLSG01 Valid level setting bit of PWM01 in the output short circuit protection

0: Low level valid 1: High level valid

2 OLSG2 Valid level setting bit of PWM2 in the output short circuit protection

0: Low level valid 1: High level valid

1 OLSG1 Valid level setting bit of PWM1 in the output short circuit protection

0: Low level valid 1: High level valid

0 OLSG0 Valid level setting bit of PWM0 in the output short circuit protection

0: Low level valid 1: High level valid

16.4.20 PWM0/1/2 Oscillator Stop Detection Protection Control Bit (MCMx_POSTDCR)

Offset Address: 0x0070 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Reserved OSTD EN Reserved - RW - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 8 Reserved -

7 OSTDEN Oscillator stop protection PWM output enable bit

0: Disabled 1: Enabled 6 ~ 0 Reserved -

16.4.21 PWM Interrupt Enable Control Register (MCMx_PWMINTEN)

Offset Address: 0x0074 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Reserved OST DIE OIE FLT CMP 1IE FLT CMP 0IE FLTI E PW MPI E PW MZIE PTD D2IE PTU D2IE PTD D1IE PTU D1IE PTD D0IE PTU D0IE - RW RW RW RW RW RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 13 Reserved -

12 OSTDIE Oscillator stop protection PWM output interrupt enable bit

0: Interrupt request is disabled 1: Interrupt request is enabled

11 OIE Interrupt enable bit of output short circuit

0: Interrupt request is disabled 1: Interrupt request is enabled

10 FLTCMP1IE CMP1 Fault interrupt enable bit

0: Fault detection interrupt is disabled 1: Fault detection interrupt is enabled

9 FLTCMP0IE CMP0 Fault interrupt enable bit

0: Fault detection interrupt is disabled 1: Fault detection interrupt is enabled

8 FLTIE Pin Fault interrupt enable bit

0: Fault detection interrupt is disabled 1: Fault detection interrupt is enabled

7 PWMPIE PWM time base periodic matching interrupt allowance bit (only valid in

center aligned mode) 0: PWM time base periodic matching interrupt is disabled 1: PWM time base periodic matching interrupt is enabled

6 PWMZIE PWM time base zero matching interrupt enable bit

0: PWM time base zero matching interrupt is disabled 1: PWM time base zero matching interrupt is enabled

5 PTDD2IE Interrupt enable bit when the PWM time base counter is matching with

the duty cycle register PWM2D during down-count operation (only valid in center aligned mode) 0: Disables interrupt from being triggered when the PWM counter is matching with PWM2D during down-count operation 1: Enables interrupt to be triggered when the PWM counter is matching with PWM2D during down-count operation

4 PTUD2IE Interrupt enable bit when the PWM time base counter is matching with

the duty cycle register PWM2D during up-count operation 0: Disables interrupt from being triggered when the PWM counter is matching with PWM2D during up-count operation 1: Enables interrupt to be triggered when the PWM counter is matching with PWM2D during up-count operation

3 PTDD1IE Interrupt enable bit when the PWM time base counter is matching with

the duty cycle register PWM1D during down-count operation (only valid in center aligned mode) 0: Disables interrupt from being triggered when the PWM counter is matching with PWM1D during down-count operation 1: Enables interrupt to be triggered when the PWM counter is matching with PWM1D during down-count operation

2 PTUD1IE Interrupt enable bit when the PWM time base counter is matching with

the duty cycle register PWM1D during up-count operation 0: Disables interrupt from being triggered when the PWM counter is matching with PWM1D during up-count operation 1: Enables interrupt to be triggered when the PWM counter is matching with PWM1D during up-count operation

1 PTDD0IE Interrupt enable bit when the PWM time base counter is matching with

the duty cycle register PWM0D during down-count operation (only valid in center aligned mode) 0: Disables interrupt from being triggered when the PWM counter is matching with PWM0D during down-count operation 1: Enables interrupt to be triggered when the PWM counter is matching with PWM0D during down-count operation

0 PTUD0IE Interrupt enable bit when the PWM time base counter is matching with

the duty cycle register PWM0D during up-count operation 0: Disables interrupt from being triggered when the PWM counter is matching with PWM0D during up-count operation 1: Enables interrupt to be triggered when the PWM counter is matching with PWM0D during up-count operation

16.4.22 PWM Interrupt Flag and Clear Register (MCMx_PWMINTF)

Offset Address: 0x0078 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 SC2 STA TC SC1 STA TC SC0 STA TC OST DFC OSF C FLT CMP 1IFC FLT CMP 0IFC FLTI FC PW MPIF C PW MZIF C PTD D2IF C PTU D2IF C PTD D1IF C PTU D1IF C PTD D0IF C PTU D0IF C WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 SC2 STA T SC1 STA T SC0 STA T OST DF OSF FLT CMP 1IF FLT CMP 0IF FLTI F PW MPIF PW MZIF PTD D2IF PTU D2IF PTD D1IF PTU D1IF PTD D0IF PTU D0IF RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description

31 SC3STATC SC3 fault detection flag bit clear bit

0: Invalid 1: Clear

30 SC2STATC SC2 fault detection flag bit clear bit

0: Invalid 1: Clear

29 SC1STATC SC1 fault detection flag bit clear bit

0: Invalid 1: Clear

28 OSTDFC Oscillator stop protection PWM output interrupt flag clear bit

0: Invalid 1: Clear

27 OSFC Output short circuit flag bit clear bit

0: Invalid 1: Clear

26 FLTCMP1IFC CMP1 Fault interrupt flag bit clear bit

0: Invalid 1: Clear

25 FLTCMP0IFC CMP0 Fault interrupt flag bit clear bit

0: Invalid 1: Clear

24 FLTIFC Fault interrupt flag bit clear bit

0: Invalid 1: Clear

23 PWMPIFC PWM time base periodic matching interrupt flag bit clear bit

0: Invalid 1: Clear

22 PWMZIFC PWM time base zero matching interrupt flag bit clear bit

0: Invalid 1: Clear

21 PTDD2IFC Interrupt flag bit clear bit when PWM time base is matching with duty

cycle register PWM2D during down-count operation 0: Invalid 1: Clear

20 PTUD2IFC Interrupt flag bit clear bit when PWM time base is matching with duty

cycle register PWM2D during up-count operation 0: Invalid 1: Clear

19 PTDD1IFC Interrupt flag bit clear bit when PWM time base is matching with duty

cycle register PWM1D during down-count operation 0: Invalid 1: Clear

18 PTUD1IFC Interrupt flag bit clear bit when PWM time base is matching with duty

cycle register PWM1D during up-count operation 0: Invalid 1: Clear

17 PTDD0IFC Interrupt flag bit clear bit when PWM time base is matching with duty

cycle register PWM0D during down-count operation 0: Invalid 1: Clear

16 PTUD0IFC Interrupt flag bit clear bit when PWM time base is matching with duty

cycle register PWM0D during up-count operation 0: Invalid 1: Clear 15 ~ 14 Reserved -

13 SC3STAT SC3 fault detection flag bit

0: SC3 selected channel is in normal output state 1: Overcurrent is detected, SC3 selected channel is in outputting invalid level state

12 SC2STAT SC2 fault detection flag bit

0: SC2 selected channel is in normal output state 1: Overcurrent is detected, SC2 selected channel is in outputting invalid level state

11 SC1STAT SC1 fault detection flag bit

0: SC1 selected channel is in normal output state 1: Overcurrent is detected, SC1 selected channel is in outputting invalid level state

10 OSTDF Oscillator stop protection PWM output interrupt flag bit

0: No oscillator vibration stop occurs 1: Oscillator vibration stop has occurred

9 OSF Output short circuit flag

0: Does not become valid level at the same time 1: Becomes valid level at the same time (at least one of the three groups of 2-phase outputs in MCM is at valid level at the same time)

8 FLTIF Fault interrupt flag bit

0: No fault detection interrupt occurs 1: Fault detection interrupt has occurred

7 PWMPIF PWM time base periodic matching interrupt flag bit (only valid in center

aligned mode) 0: No PWM periodic matching interrupt occurs 1: PWM periodic matching interrupt occurs

6 PWMZIF PWM time base zero matching interrupt flag bit

0: No PWM zero matching interrupt occurs 1: PWM zero matching interrupt occurs

5 PTDD2IF Interrupt flag bit when PWM time base is matching with duty cycle

register PWM2D during down-count operation (only valid in center aligned mode) 0: No interrupt is generated 1: Interrupt is generated

4 PTUD2IF Interrupt flag bit when PWM time base is matching with duty cycle

register PWM2D during up-count operation 0: No interrupt is generated 1: Interrupt is generated

3 PTDD1IF Interrupt flag bit when PWM time base is matching with duty cycle

register PWM1D during down-count operation (only valid in center aligned mode) 0: No interrupt is generated 1: Interrupt is generated

2 PTUD1IF Interrupt flag bit when PWM time base is matching with duty cycle

register PWM1D during up-count operation 0: No interrupt is generated 1: Interrupt is generated

1 PTDD0IF Interrupt flag bit when PWM time base is matching with duty cycle

register PWM0D during down-count operation (only valid in center aligned mode) 0: No interrupt is generated 1: Interrupt is generated

0 PTUD0IF Interrupt flag bit when PWM time base is matching with duty cycle

register PWM0D during up-count operation 0: No interrupt is generated 1: Interrupt is generated Note: When PTDDxIF is set to 1, the hardware will automatically clear PTUDxIF. Similarly, when PTUDxIF is set to 1, the hardware will automatically clear PTDDxIF. Therefore, by judging these two flags, it can be judged whether the current PWM waveform is in a valid state or an invalid state. .

16.4.23 Register Modification and Reload Control Register (MCMx_PWMRLDEN)

Offset Address: 0x007C Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Reserved PWMRLDEN[7:0] - RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 8 Reserved - 7 ~ 0 PWMRLDEN[7:0] Register modification and reload control register 0x55: Allows modification to module register by software 0xAA: Allows reloading of module register with buffering Note: 1. The PWM module registers, except for the interrupt flag register PWMINTF, manual control registers PMANUALCON2, FLTCON, POSCR, POSTDCR and FLTWEN, the other registers are allowed to be modified by software only when PWMRLDEN = 0x55, otherwise the modification is invalid. 2. There are some registers in the PWM module with buffer registers, including duty cycle register PWMxD&PWMx1D, periodic register PWMP and PWM clock pre-division register PWMPSQ, post-division register POTSTS[2:0]@ PWMCON1, duty select register PDCONx@ PWMCON1, symmetry control register PWMSYM@PWMCON1, dead zone register PWMDTxx, compare register AD start-up control bit CMPx@PWMCON2 and PWM event trigger register PWMCMPx.

16.4.24 PWM Saturation/Phase Shift Control Register (MCMx_PSCON)

Offset Address: 0x0080 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Reserved STATR UN MINSELECT[1: MAXSELECT[1 :0] SECTOR[2:0] SHIFT RUN - RW1s RW RW RW RW1s 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 9 Reserved -

8 STATRUN Duty cycle register saturation function start-up bit:

0: Invalid or operation completed 1: Turns on duty cycle register saturation function, PWMxD Note 1: There’s a total of 6 duty cycle registers Note 2: It is set to 1 by software, and cleared by hardware after the completion of calculation. Note 3: Completed within single hardware MCM clock cycle 7 ~ 6 MINSELECT[1:0] During saturation processing, the PWM duty value selection bit after being compared with the lower limit comparison value. 00: The value of PWMx duty cycle (PWMxD) is unchanged at any time 01: PWMxD is modified to PWMDMIN when PWMxD is less than or equal to PWMDMIN; otherwise unchanged 1x: PWMxD is modified to 0 when PWMxD is less than or equal to PWMDMIN; otherwise unchanged 5 ~ 4 MAXSELECT[1:0] During saturation processing, the PWM duty value selection bit after being compared with the upper limit comparison value. 00: The value of PWMx duty cycle (PWMxD) is unchanged at any time 01: PWMxD is modified to PWMDMAX when PWMxD is more than or equal to PWMDMAX; otherwise unchanged 1x: PWMxD is modified to 0 when PWMxD is more than or equal to PWMDMAX; otherwise unchanged 3 ~ 1 SECTOR[2:0] SVPWM quadrant setting bit, with which the order of PWM0D, PWM1D and PWM2D, especially the order in number when there are two equal values is determined MAX MUM MIN 000: PWM2D PWM1D PWM0D 001: PWM2D PWM0D PWM1D 010: PWM0D PWM2D PWM1D 011: PWM0D PWM1D PWM2D 100: PWM1D PWM0D PWM2D 101: PWM1D PWM2D PWM0D Note: invalid when setting 110 and 111

0 SHIFTRUN Phase shift module start-up bit

0: Invalid or completed operation 1: Turns on phase shift function of duty cycle register Note 1: It is set to 1 by software, and cleared by hardware after the completion of calculation. Note 2: Completed within single hardware MCM clock cycle

16.4.25 PWM Duty Cycle Upper Limit Compare Register (MCMx_PWMDMAX)

Offset Address: 0x0084 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 PWMDMAX[15:0] RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 16 Reserved - 15 ~ 0 PWMDMAX[15:0] PWM duty cycle upper limit compare register

16.4.26 PWM Duty Cycle Lower Limit Compare Register (MCMx_PWMDMIN)

Offset Address: 0x0088 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 PWMDMIN[15:0] RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 16 Reserved - 15 ~ 0 PWMDMIN[15:0] PWM duty cycle lower limit compare register 16.4.27 PWM Duty Cycle Phase Shift Minimum Sampling Interval Register 1 (MCMx_PWMDCMPn)(n=1..2) Offset Address: 0x008C : 0x0090 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 PWMDCMPn[15:0] RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 16 Reserved - 15 ~ 0 PWMDCMPn[15:0] PWM duty cycle phase shift minimum sampling interval register n

16.4.28 Wave-by-Wave Current Limiting Pin 0 Function Select Register (MCMx_SCnCON)(n=0..2) Offset Address: 0x0094 : 0x0098 : 0x009C Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Reserved SCEN[1:0] SCS SCP WM2 EN SCP WM1 EN SCP WM0 EN SCDEB[3:0] SCTIME[3:0] - RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 14 Reserved - 13 ~ 12 SCEN[1:0] Fault detection 1 function control bit 00: SCn pin wave-by-wave current limiting function is disabled 01: SCn pin wave-by-wave current limiting function is enabled 10: CMP0 output as a current limiting N input, high level effective 11: CMP1 output as a current limiting N input, high level effective

11 SCS SCn valid level selection bit

0: Wave-by-wave current limiting SCn input is valid at high level 1: Wave-by-wave current limiting SCn input is valid at low level

10 SCPWM2EN PWM2 protection enable bit

0: SCn doesn’t protect PWM2 1: SCn protects PWM2

9 SCPWM1EN PWM1 protection enable bit

0: SCn doesn’t protect PWM1 1: SCn protects PWM1

8 SCPWM0EN PWM0 protection enable bit:

0: SCn doesn’t protect PWM0 1: SCn protects PWM0

7 ~ 4 SCDEB[3:0] Wave-by-wave current limiting SCn input filtering parameter selection 0000: 0 0001: 40*HCLK 0010: 80*HCLK 0011: 120*HCLK 0100: 160*HCLK 0101: 240*HCLK 0110: 320*HCLK 0111: 480*HCLK 1000: 640*HCLK 1001: 800*HCLK 1010: 960*HCLK 1011: 1120*HCLK 1100: 1280*HCLK 1101: 1600*HCLK 1110: 1920*HCLK 1111: 2560*HCLK Note 1: The above filter constant time is not exact value and is for reference only. Note 2: Filter description: The input signal is sampled by the internal clock. If the sampling result is high level, the counter is incremented by 1, and the counter result exceeds the set constant, then when the filter outputs 1, the counter is set to the filter constant simultaneously; if the sampling result is at low level, the counter is decremented by 1, the counter result is less than the filter constant, then when the filter outputs 0, the counter is set to 0 simultaneously. 3 ~ 0 SCTIME[3:0] Protection time selection bit 0000: Restore the MCM output when the next return to zero match 0001: 1200*HCLK 0010: 1600*HCLK 0011: 2000*HCLK 0100: 2400*HCLK 0101: 2800*HCLK 0110: 3200*HCLK 0111: 4000*HCLK 1000: 4800*HCLK 1001: 6400*HCLK 1010: 8000*HCLK 1011: 16000*HCLK 1100: 32000*HCLK 1101: 48000*HCLK 1110: 64000*HCLK 1111: Manually restore the MCM output, by clearing SCnSTATC@PWMINTF

16.4.29 Register Modification and Reload Protection Control Register (MCMx_FLTWEN)

Offset Address: 0x00A0 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 FLTWEN[15:0] RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 16 Reserved - 15 ~ 0 FLTWEN[15:0] Register modification and reload protection control register 0x33CC: allows software to modify the protection module registers Note: The protection registers include FLTCON, POSCR and POSTDCR. For modification of these registers, software modification is allowed only when FLTWEN = 0x33CC, otherwise the modification is invalid.

1. Programmable Counter Array (PCA, PCA0～PCA1)

17.1 Introduction

Programmable counter array PCAx provides the enhanced timer function, which requires less CPU intervention. SH33F2801 has 2 built-in PCAs, and each PCA has 3 input capture or output compare channels. PCA modules support input capture, output compare, frequency output and PWM mode.

17.2 Feature

 32/16 bits Timer  3 independent input/output channels  Support input capture/output compare  Support square wave output with adjustable frequency  Support 32bit PWM output, 4 mode selectable

17.3 Function Description

Programmable counter array PCAx includes a base timer, three 32-bit capture/compare modules, and a fault detect module. Every PCAx has 3 independent input/output channels (PCAxA/PCAxB/PCAxC), which can be set to input capture or output compare. Note: The small subscript x is the PCA ordinal number, such as PCAx (x= 0, 1). PCAx will be used uniformly below and the value of x will not be explained anymore. Figure17-1 Schematic Diagram of PCAx

17.3.1 PCA Counter

The PCAx consists of a 32-bit periodic register (PCAx PR), a 32-bit counter register (PCAx CNT) and a 16-bit prescaler register (PCAx PSQ). There are two counting modes for 32-bit counters, edge-aligned mode and one for center-aligned mode. When the SDEN @PCAx CFGR is 0, the counter works in edge-aligned mode, and when SDEN is 1, the counter works in center-aligned mode. In edge-aligned mode, the counter counts from 0 up to the value of the PCAx_PR, then counts again from 0 and a counter overflow event is generated, while the CIF bit in the PCAx_SR is set to 1 by the hardware. If the CIE@ PCAx_CFGR is set, an interrupt occurs. In center-aligned mode, the counter counts from 0 up to the value of the PCAx_PR. If PIE@ PCAx_CFGR is set, a period interrupt occurs. And then the counter counts down from the value of the PCAx_PR to 1 and a counter overflow event is generated, while the CIF bit in the PCAx_SR is set to 1 by the hardware. If the CIE@ PCAx_CFGR is set, an overflow interrupt occurs. Note: The edge-aligned mode is also called the sawtooth mode, and the center-aligned counting mode is also called the triangular mode.

17.3.2 Counter Clock Source

The counter/timer of PCAx has a programmable clock source, and 3 clock source can be chosen, PCLK, an external clock signal on the PCAx_ECI input pin and built-in128kHz RC. Select clock source of the counter/timer by CPS[2:0] bit in PCAx_CFGR register, as shown in following table. CPS[2] CPS[1] CPS[0] 0 0 0 PCLK 0 0 1 The Falling edge of PCAxECI Pin 0 1 0 LSI(RC 128KHz) 0 1 1 Reserved

17.4 Mode Configuration of PCAx

The PCAx have 3 capture/compare modules to realize the enhanced function. Each capture/compare module can be configured to work independently. Each module has its own mode control registers (PCAx_CCMRn, PCAx_CCRn). These registers are used to configure how the module works and exchange data with the module. The module can be enabled in one of the following four operating modes by configuring the bits SM[1:0] and FS[1:0] in the respective module PCAx_CCMRn register: edge-triggered capture, compare match output, frequency output, and PWM output modes. The working methods are selected as shown in the following table: Table17-1 PCAx Mode Select Table Mode SDEN SM[1] SM[0] FS[1] FS[0] Function Mode0 0 0 0

0 X Capture triggered by positive edge

(edge-aligned mode) 1 0 Capture triggered by negative edge (edge-aligned mode) 1 1 Capture triggered by transition (edge-aligned mode) Mode1 0 0 1

0 X Continuous software timer

(edge-aligned mode)

1 X Single software timer (edge-aligned

mode) Mode2 0 1 0 X X Frequency output (edge-aligned mode) Mode3 1 1 0 0 16 bit PWM1 (edge-aligned mode) 0 1 32 bit PWM2 (edge-aligned mode) 1 1 0 32-bit PWM3 (center-aligned) 1 1 1 32-bit PWM4 (center-aligned) Others - PCAx Counter correctly, but the compare/capture module does not work. X: Don’t Care;

17.4.1 Input Capture Mode

In the input capture mode, a valid transition on the PCAxA/B/C pin causes the PCAx to capture the value of the PCAx counter/timer and load it into the corresponding module's 32-bit capture/compare register (CCRn). The FS[1:0] bits in the PCAx_CCMRn register are used to select the type of transition that triggers the capture: low-to-high transition (positive edges trigger FS[1:0] = 0X), high-to-low transition (negative edge trigger FS[1:0] = 10), or either transition (positive or negative edge trigger FS[1:0] = 11). When a capture occurs, the Capture/Compare Flag (CCnIF) in PCAx_SR is set to logic 1 and an interrupt request is generated if CCnIF interrupts are enabled. The CCnIF bit is not automatically cleared by hardware; it must be cleared by software. The bit of CCnIFC@ PCAx SR is set to 1; CCnIF@ PCAx SR will be cleared. If both FS[1:0] are set to logic 1, then the state of the Port pin associated with TCP can be read directly to determine whether a rising-edge or falling-edge caused the capture. When capture occurs, CC@PCAx_CCMRn can control the operation of clearing counter. If CC is 0, the counter value will not be cleared when capture occurs. If CC is 1, the hardware will capture the current counter value to the PCAx_CCRn register and then clear the counter value to 0 when capture occurs. If CC is 1, when the input signal is actually captured, the value of CCRn register is the actual pulse width of the input signal. The input channel of each module has an independent filtering function, ICF@PCAx CCMRn can be set to select the filtering time. When ICF[2:0]=0, there is no filtering effect on the input signal. When ICF[2:0]=1~7, the filtering time is respectively 40PCLK, 80PCLK, 160PCLK..., 2560 PCLK. The transition of input signal must be longer than the filter time at least, otherwise it is considered to be a valid level by the internal detection circuit. Figure17-2 PCA Capture Mode Diagram

17.4.2 Output Compare Mode

This function is used to control an output waveform or indicating when a period of time has elapsed, which is also called software timer mode. In this mode, FS = 0Xb, which enables continuous matching capture. When a match is found between the capture/compare register (PCAx_CCRn) and the counter, the capture/compare flag (CCnIF) in PCA_SR is set to logic '1' and on the module's PCAxA/B/C pin the logic level will change (setting the TCP bit enables this function). If CCnIF interrupt is enabled, an interrupt request is generated. When the CPU turns to the interrupt service routine, the CCnIF bit cannot be automatically cleared by hardware and must be cleared by software. The bit of CCnIFC@ PCAx SR is set to 1; CCnIF@ PCAx SR will be cleared. In this mode, FS = 0Xb, which enables single matching capture. The initial level of the output waveform is changed through the TCP bit in PCAx CCMRn. When TCP is 0, the initial level of the output waveform is high; when TCP bit is 1, the initial level of the output waveform is low. Figure17-3 PCAx Capture Mode Diagram In addition, when the module operates in the software timer mode, a compare match can be forced by setting FCOn@PCAx_FORCE. However, such a match is not a true match. It does not set the compare match flag and does not affect the register. The value will only produce a level toggle output on the PCAxA/B/C pin (forced matching will generate the corresponding level when in single trigger mode). When a forced match is generated (Set FCOn@PCAx_FORCE to '1'), this bit will be automatically cleared by hardware.

17.4.3 Frequency Output Mode

The frequency output mode generates a square wave of programmable frequency. Configure SM[1:0] = 10 to enable this mode and the PCAxA/B/C pin can output the wave. In this mode, the periodic register PR, counter CNT, and capture/output register CCRn are divided into two 16-bit registers by 32-bit, distinguished by 16-bit high registers (such as PRH) and 16-bit low registers (PRL). In the frequency output mode, the 16-bit low register PRL is fixed 0xFFFF. The 32-bit values of PRH and PRL are the value of periodic register PR_PCAx. If PRH is set to 0x053C, the value of PR_PCAx is 0x053CFFFF. When the counter counts from 0 to the value of PR_PCAx, overflow occurs. The overflow flag CCnIF@ PCAx_SR is set at the same time, and an interrupt generates if the corresponding interrupt mask is set (CCnIE@PCAx_CCRn). The 16-bit low CCRL of the capture/compare module is compared with the 16-bit low CNTL of the PCAx counter; if the two match, the level of the PCAxA/B/C pin changes, and the value of CCRH as the offset is added to CCRL; then the value of CCRL is updated immediately. CNTL continues to count until it matches the update value of CCRL. The level of PCAxA/B/C pin changes and the PCAxA/B/C pin output frequency is controlled by CCRH. PCAx works in frequency output mode, and only the 16-bit low CCRL is used. So the value of CCRL will overflow after accumulating to 0xFFFF and the low 16-bit after overflow will continue to be compared with the counter CNTL. The initial level of the output pin PCAxA/B/C can be selected according to the TCP bit; when TCP is 0, the initial level is high; when TCP is 1, the initial level is low. Figure17-4 PCAx Frequency Output Mode Diagram

17.4.4 PWM Output

Each PCAx module can be used independently to generate a pulse width modulated (PWM) output. Configuring SM[1:0]=11 will enable compare/capture module n to operate in PWM mode. In this mode, configuring the FS[1] and FS[0] bits enables the compare/capture module n to operate in one of four PWM functions. FS[1] FS[0] Function 0 0 16-bit PWM1 (edge-aligned mode) 0 1 32-bit PWM2 (edge-aligned mode) 1 0 32-bit PWM3 (center-aligned mode) 1 1 32-bit PWM4 (center-aligned mode)  16-bit PWM1 Mode When the compare/capture module operates in the 16-bit PWM1 function, the value of PCAx_PRL is fixed to 0xFFFF. the low 16-bit PCAx_CNTL of PCAx counter counts incrementally from 0x0000 to PCAx_PRL (in edge-aligned mode), and when PCAx_CNTL overflows (from 0xFFFF to 0x00), the value stored in PCAx_CCRnH is automatically loaded into PCAx_CCRL, this process does not require software intervention. Figure17-5 16–Bit PWM1 Mode Diagram(in edge-aligned mode) The module's capture/compare register PCAx_CCRHn is used to change the duty cycle of the PWM output signal. When TCP= 0, the output on the PCAxA/B/C pin is high to low when the low byte (PCAx_PRL) of the PCA counter/timer equals the value in PCAx_CCRL; when the count value in PCAx_PRL overflows, the PCAxA/B/C output is from low to high; when TCP= 1, the PCAxA/B/C pin outputs a waveform of opposite polarity.

 32-bit PWM2 Mode The 32-bit pulse width modulation PWM is similar to the 16-bit PWM mode, which is based on the edge-aligned counting mode of PCAx Counter. In this way, the 32-bit capture/comparison module PCAx_CCRn is used to define the PCAx clock number of PWM signal low level time. When TCP = 0, the PCAx counter matches the PCAx_CCRn value of the matching register of the module, and the output of PCAxA/B/C is from high to low. When the counter overflows, the PCAxA/B/C output is from low to high, and when TCP = 1, the PCAxA/B/C pin outputs a waveform with opposite polarity. Figure17-6 32-Bit PWM2 Mode (in edge-aligned mode)  32-bit PWM3 Mode The 32-bit PWM3 mode is used as 32-bit PWM output, the TCP bit in register PCAx CCMRn can be used to select the Duty zone level. This mode is based on center-aligned mode. That is, the counter repeatedly counts from 0x0000 0000 to PCAx_PR and then back again from PCAx_PR to 0x0000. When TCP = 0, if the PCAx Counter matches PCAx_CCRn while the timer is counting towards PCAx_PR, PCAxA/B/C will be cleared low; if the PCAx Counter matches PCAx_CCRn while the timer is counting towards 0x0000, PCAxA/B/C will be set high level. When TCP = 1, the PCAxA/B/C pin outputs an inverted waveform. When a match occurs, the match flag CCnIF is set to '1'. If the interrupt is enabled (CCnIE = 1), a PCAx interrupt will be generated. When PCAx counts down from PCAx_PR and back to 0x0000 0000, the PCAx interrupt flag CCnIFx will also be set to '1'. If the interrupt is enabled, the PCAx interrupt will be generated. When operating in the 32-bit PWM3 mode, the PCAx counter value is equal to the PCAx_PR value during a timer clock cycle, and then PCAx_PR and PCAx_CCRn will be updated on the next circle. The PWM period starts at the PCAx_PR point and ends at the PCAx_PR point, and the values of the PCAx_PR and PCAx_CCRn registers can be updated only when the PCAx reaches the PCAx_PR value. Therefore, if the PR value and the CCR value are modified when the counter is counting from 0 to PR, the CCRn value can be used during the half period which the counter returns from PR value to 0x0, and the modified PR value can only be used in the new period after the counter returns from PR to 0x0 value. So when the PR value is modified, the value of the counter will not change suddenly.  32-bit PWM4 Mode The 32-bit PWM4 mode is used as 32-bit PWM output, the TCP bit in register PCAx CCMRn can be used to select the Duty zone level. This mode is based on center-aligned mode. That is, the counter repeatedly counts from 0x0000 0000 to PCAx_PR and then back again from PCAx_PR to 0x0000. When TCP = 0, if the PCAx Counter matches PCAx_CCRn while the timer is counting towards PCAx_PR, PCAxA/B/C will be cleared low; if the PCAx Counter matches PCAx_CCRn while the timer is counting towards 0x0000, PCAxA/B/C will be set high level. When TCP = 1, the PCAxA/B/C pin outputs an inverted waveform. When a match occurs, the match flag CCnIF is set to '1'. If the interrupt is enabled (CCnIE = 1), a PCAx interrupt will be generated. When PCAx counts down from PCAx_PR and back to 0x0000 0000, the PCAx interrupt flag CCnIFx will also be set to '1'. If the interrupt is enabled, the PCAx interrupt will be generated. When operating in the 32-bit PWM4 mode, the values of the PCAx_PR and PCAx_CCRn registers can be updated only when the CNT_PCAx is equal to 0(CNT_PCAx = 0). Therefore, if the PR value and the CCR value are modified when the counter is equal to 0, the CCRn value and the PR value can be updated in the next period synchronously.

The difference between PWM4 mode and PWM3 mode is that PCAx PR and PCAx CCR have different update times, so PWM3 mode can output asymmetric waveform, while PWM4 mode always outputs symmetric waveform. PWM4 mode updates the CCR and PR register values when CNT is 0x0. PWM3 mode updates the CCR and PR register values when CNT is equal to the value of PR.

17.5 Interrupt

PCAx has two independent interrupt vector addresses, in which counter overflow and 3 channels input capture/output comparison share one interrupt vector, and the output fault detection module has an independent interrupt vector. The counter overflow and 3 channels input capture/output compare module are sharing an interrupt vector, but they have independent interrupt request sources. When the counter overflow, CIF is set. If the enable bit of interruption CIE is 1, the interrupt occurs. The 3 channels input capture/output compare modules have the same function. When the output fault is detected, the fault detection flag bit FLTIF will be set to 1. At this point, if the enable bit of the fault detection interrupt is 1, the fault detection interrupt will be triggered. Figure17-7 PCAx Interrupt Source

17.6 Register Value Update Function

The PCAx_CCR and PCAx_PR can be selected to take effect immediately or in the next cycle by setting the corresponding bit in CFGR. If PUE@ PCAx_CFGR is 0, the value written to PR takes effect in the next cycle; if PUE@ PCAx_CFGR is 0, the value written to PR takes effect immediately. If CC0UE@ PCAx_CFGR is 0, the value written to CCR0 takes effect in the next cycle; if CC0UE@ PCAx_CFGR is 0, the value written to CCR0 takes effect immediately. If CC1UE@ PCAx_CFGR is 0, the value written to CCR1 takes effect in the next cycle; if CC1UE@ PCAx_CFGR is 0, the value written to CCR1 takes effect immediately. If CC2UE@ PCAx_CFGR is 0, the value written to CCR2 takes effect in the next cycle; if CC2UE@ PCAx_CFGR is 0, the value written to CCR2 takes effect immediately.

17.7 Register Lock

PCAx module has two lock registers, LCKR and FLTWPR。 If FLTPWR = 0x33CC, it allows modification to FLTCR register by software. If LCKR = 0x33CC, the other registers of PCAx module can be modified by software, including CR, CFGR, PR, PSC, CNT, CCMR0, CCMR1, CCMR2, CCR0, CCR1, CCR2, ADTR.

17.8 PCA Fault Detection Mode

The PCAx module has fault detection logic. When the FLT1EN bit or the FLT2EN in the PCAx_FLTCR register is 1, the function of Mode1/2/3 is enabled. If both FLT1EN and FLT2EN are 0, the function of this module is disabled. The main purpose of PCAx fault detection is: when the fault occurs (such as over current), the PCAx output can be cut off, and the invalid drive state can be entered (can be set to high level, low level and high resistance state), thereby achieving the purpose of protecting the external power device. Because it is controlled by hardware, its response is very fast. Note 1: When the PCAx module clock is turned off, fault protection can also work normally.

17.8.1 Selection of Fault Signal Input Source

The output of the comparator0/1 or the FLT pin input can be selected as the fault detection input signal. Regardless of whether the fault signal comes from the comparator 0/1 output or FLT, the high level is the valid fault signal, which means the output of the comparator is automatically cut off when the comparator output goes from low to high. If FLT1EN = 1, the output of comparator 1 or 2 will be used as the fault detection input signal. Once the output of the comparator goes higher and the filter time is maintained, the 3 channel PCA pins PCAxA/B/C immediately enter the invalid drive state (x = 0 - 1). Similarly, if FLT2EN = 1, the FLT pin input is used as the fault detection input signal. Once the FLT pin input matches the setting state (controlled by FLT2S) and the filter time is maintained, the 3 channel PCA pins PCAxA/B/C immediately enter the invalid drive state (x = 0 - 1). If FLT2EN = 0, the fault detection function of the FLT pin is then forbidden, and the FLT pin is used as normal IO (but the comparator's fault detection function is not affected).

17.8.2 Filtering of the Signal on FLT Pin and the Output Signal of the Comparator

When FLT2EN = 1, the input signal of the FLT pin is used as the fault detection input signal. At this time, the filter time of this signal can be set by the FLT2DEB[3:0] bit segment in the PCAx_FLTCR register. When FLT2DEB[3:0] = 0, there is no filtering effect. When FLT2S = 0, protection is immediately triggered when the level of fault detection input signal goes high level from low level. When FLT2DEB[3:0] = 0 - 15, the filter time can be set to 0~32us and 16 stages in total, when fault detection input signal goes high level from low level, being at high level needs to maintain at least the length of time defined by FLT2DEB[3:0], then the fault detection module will consider that the level of the fault detection input signal becomes higher, thereby triggering protection. When the level of the fault detection input signal goes low level from high, being at low level needs to maintain at least the length of time defined by FLT2DEB[3:0], then the fault detection module will consider that the effective fault level on the FLT pin has disappeared, and the output of 3 channel PCA pins PCAxA/B/C is acting based on the protection mode (introduced in the next section). When FLT2S = 1, the FLT fault detection signal becomes low-level valid, as opposed to the situation when FLT2S = 0. According to the characteristics of the power tube, properly set filtering time can filter out the noise on the fault detection input signal. The description of filter time setting is as follows: 1. The upper limit of the counter is set to the filter constant, the lower limit is 0. If the upper and lower limits are exceeded, adding and subtracting operations are not performed. 2. Filter counter initial value setting: if the FLT pin is set to high level valid, the initial value of the counter is 0; if the FLT pin is set to low level valid, the initial value of the filter counter is set to the filter constant. 3. The filter output stabilization requires a settling time, roughly the time set by the filter constant. If the filter constant is set to 256, the filter output is stable after 256 system clocks, and before that, the filter output is undefined. When FLT1EN = 1, the output signals of the comparators 0 can be selected and used as the fault detection input signal. When the comparator output changes from 0 to 1, the protection is triggered. At this time, the output filtering time and algorithm of the comparators1/0 are set in registers CMP0CON and CMP1CON. (See the Operational Amplifier and Comparator Modules chapter for details)

17.8.3 Fault Detection Synchronization Control

If FLTSYN@ PCAx_FLTCR is set, Regardless of whether the fault signal comes from the comparator 0/1 output or FLT, the PCA modules will enter the invalid drive state. Note: FLTSYN@ PCA0_FLTCR and FLTSYN@ PCA1_FLTCR can enable simultaneously or separately.

17.9 Trigger ADC

In mode1/2/3, setting ADTSEL[1:0]@PCA_CFGR can trigger an A/D conversion request. If ADTSEL[1:0]=00b, PCAx can’t trigger ADC. If ADTSEL[1:0]=01b, when counter is incremented, if the counter value matches PCAx_ADTR, PCAx can trigger ADC. If ADTSEL[1:0]=10b, when counter is decremented, if the counter value matches PCAx_ADTR, PCAx can trigger ADC. If ADTSEL[1:0]=11b, when counter is incremented or decremented, if the counter value matches PCAx_ADTR, PCAx can trigger ADC. If SDEN = 0, the counter cannot decrease, so ADTSEL[1:0]=10b/11b is not valid, and cannot trigger ADC.

17.10 PCA waveform synchronization

17.10.1 PCA synchronization

SYN[1:0]@ PCAx_CFGR is used as the synchronous control bits of PCA. If SYN[1:0]@ PCA0_CFGR is set to 01b, PCA0 turns on or turns off that is controlled by PCA1, and PEN@ PCA0_CR synchronizes with PEN@ PCA1_CR. If SYN[1:0]@ PCA1_CFGR is set to 01b, PCA1turns on or turns off that is controlled by PCA0, and PEN@ PCA1_CR synchronizes with PEN@ PCA0_CR.

17.10.2 MCM synchronization

PCA modules can be synchronized by MCM module. If SYN[1:0]@ PCA0_CFGR is set to 10b, PCA0 turns on or turns off that is controlled by MCM, and PEN@ PCA0_CR synchronizes with PWMOE @ MCM_PWMOE. If SYN[1:0]@ PCA1_CFGR is set to 10b, PCA1 turns on or turns off that is controlled by MCM, and PEN@ PCA0_CR synchronizes with PWMOE @ MCM_PWMOE.

17.11 Usage Notes

17.11.1 PCA Output in Simulation Status

SH33F2801 supports online simulation. There is no difference between operating in simulation state and normal state. If the operating is stopped or running with single step in simulation state, the PCA output will switch to high resistance state, ensuring that the external power tube will not be triggered by mistake.

17.11.2 Output Status of PCA While Entering STOP Mode

When entering STOP mode, if the PCA module output is enabled, PEN is cleared, and the PCA output port will output high resistance state. Even if the PCA interrupt is set, the power-down mode cannot be awakened. The power-down mode must be awakened by other means. See the Power Management chapter for details. The software needs to open PEN after exiting STOP mode. Note: To avoid uncertainty in status after recovery from STOP mode, it is recommended that the software turns off the PCA before entering STOP, and reconfigure and turn on PCA after exiting STOP.

17.12 Register

PCA Module Register List (Base Address: 0x4000 0400) Address Register Name Description 0x4000 0400 CR PCAx Control Register 0x4000 0404 CFGR PCAx Mode Register 0x4000 0408 SR PCAx State Register 0x4000 040C FORCE PCAx Forced Output Control Register 0x4000 0410 CNT PCAx Counter Register 0x4000 0414 PSC Prescaler Register 0x4000 0418 PR PCAx Period Register 0x4000 041C CCMR0 PCAx Compare/Capture module0 Register 0x4000 0420 CCMR1 PCAx Compare/Capture module1 Register 0x4000 0424 CCMR2 PCAx Compare/Capture module2 Register 0x4000 0428 CCR0 PCAx Compare/Capture Value0 0x4000 042C CCR1 PCAx Compare/Capture Value1 0x4000 0430 CCR2 PCAx Compare/Capture Value2 0x4000 0434 LCKR PCAx Lock Register 0x4000 0438 ADTR ADC Compare Trigger Register 0x4000 043C FLTWPR PCAx Fault Detection Protection Register 0x4000 0440 FLTCR PCAx Fault Detection Control Register

17.12.1 PCAx Control Register (PCAx_CR)

Offset Address: 0x0000 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Reserved PEN - RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 1 Reserved -

0 PEN PCA counter/timer Enable bit

0: Disable PCA counter/timer 1: Enable PCA counter/timer

17.12.2 PCAx Mode Register (PCAx_CFGR)

Offset Address: 0x0004 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved SYN[1:0] ECF[1:0] - RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 PUE CC2 UE CC1 UE CC0 UE Rese rved ADTSEL[1:0] PIE CIE SDE N Reserved CPS[2:0] RW RW RW RW - RW RW RW RW - RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 20 Reserved - 19 ~ 18 SYN[1:0] PCA waveform synchronization control bit 00: No synchronization 01: PEN@ PCAx_CR is set or cleared by the other PCA synchronously. 10: PEN@ PCAx_CR is set or cleared by MCM synchronously. 11: Reserved Note: if SYN@ PCA0_CFGR and SYN@ PCA1_CFGR are set to 01b, set or clear the PEN of one PCA, the PEN of the other PCA can be set or clear synchronously. 17 ~ 16 ECF[1:0] PCAx_ECI Input signal filter time 00: No filter 01: Filter time constant is 8*PCLK 10: Filter time constant is 16*PCLK 11: Filter time constant is 32*PCLK

15 PUE PACx period register update control bit

0: The value written to PR takes effect in the next cycle 1: The value written to PR takes effect immediately

14 CC2UE PACxC Module update control bit

0: The value written to CCR2 takes effect in the next cycle 1: The value written to CCR2 takes effect immediately

13 CC1UE PACxB Module update control bit

0: The value written to CCR1 takes effect in the next cycle 1: The value written to CCR1 takes effect immediately

12 CC0UE PACxA Module update control bit

0: The value written to CCR0 takes effect in the next cycle 1: The value written to CCR0 takes effect immediately 10 ~ 9 ADTSEL[1:0] PCAx trigger ADC selection bit 00: No trigger 01: Trigger ADC when counter is incremented. 10: Trigger ADC when counter is decremented.( SDEN must be set 1) 11: Trigger ADC when counter is incremented or decremented. ( SDEN must be set 1) Note: If SDEN=0, ADTSEL[1:0] is not set to 10b or 11b.

8 PIE PCAx Counter/timer period interrupt enable bit

0: Disable counter/timer overflow interrupt 1: when the PIF is set, the counter/timer overflow interrupt is enable This bit is the mask bit of the PCAx counter/timer overflow (PIF) interrupt

7 CIE PCAx Counter/timer overflow interrupt enable bit

0: Disable counter/timer overflow interrupt 1: when the CIF is set, the counter/timer overflow interrupt is enable This bit is the mask bit of the PCAx counter/timer overflow (CIF) interrupt

6 SDEN PCA counter working mode selection bit

0: PCA works in Edge-aligned mode(Capture mode, Compare mode, Frequency output mode,PWM1,PWM2) 1: PCA works in Center-aligned mode( For PWM3, PWM4) 5 ~ 3 Reserved - 2 ~ 0 CPS[2:0] PCAx counter / timer clock select 000 : PCLK 001 : PCAxECI Falling edge 010 : RC128K 011 : Reserved 100 : Reserved 101 : Reserved 110 : Reserved 111 : Reserved

17.12.3 PCAx State Register (PCAx_SR)

Offset Address: 0x0008 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved CIFC Reserved PIFC FLTI FC CC2I FC CC1I FC CC0I FC - WO - WO WO WO WO WO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Reserved CIF Reserved PIF FLTI F CC2I F CC1I F CC0I F - RO - RO RO RO RO RO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 24 Reserved -

23 CIFC PCAx time base periodic matching interrupt flag clear bit

0: Invalid 1: Clear 22 ~ 21 Reserved -

20 PIFC PCAx time base periodic matching interrupt flag clear bit

0: Invalid 1: Clear

19 FLTIFC Fault detection interrupt flag clear bit

0: Invalid 1: Clear

18 CC2IFC PCAxC capture/compare flag clear bit

0: Invalid 1: Clear

17 CC1IFC PCAxB capture/compare flag clear bit

0: Invalid 1: Clear

16 CC0IFC PCAxA capture/compare flag clear bit

0: Invalid 1: Clear 15 ~ 8 Reserved -

7 CIF PCA time base zero matching interrupt flag bit

0: No PCA zero matching interrupt occurs 1: PCA zero matching interrupt occurs Cleared by software. 6 ~ 5 Reserved -

4 PIF PCAx time base periodic matching interrupt flag bit (only valid in center

aligned mode) 0: No PCA periodic matching interrupt occurs 1: PCA periodic matching interrupt occurs Cleared by software.

3 FLTIF Fault Detection Interrupt Flag

0: No Fault Interrupt 1: Fault Interrupt occurred

2 CC2IF PCAxC Capture/Compare Flag

0: No capture/compare 1: Capture/compare event occurred The bit is set by the hardware when a match or capture occurs. When CCIE2 interrupt is allowed, setting the bit will cause the CPU to switch to the PCA interrupt service code. The bit can’t be cleared by hardware automatically; it must be cleared by software.

1 CC1IF PCAxB Capture/Compare Flag

0: No capture/compare 1: Capture/compare event occurred The bit is set by the hardware when a match or capture occurs. When CCIE1 interrupt is allowed, setting the bit will cause the CPU to switch to the PCA interrupt service code. The bit can’t be cleared by hardware automatically; it must be cleared by software.

0 CC0IF Paxar Capture/Compare Flag

0: No capture/compare 1: Capture/compare event occurred The bit is set by the hardware when a match or capture occurs. When CCIE0 interrupt is allowed, setting the bit will cause the CPU to switch to the PCA interrupt service code. The bit can’t be cleared by hardware automatically; it must be cleared by software.

17.12.4 PCAx Force Output Control Register (PCAx_FORCE)

Offset Address: 0x000C Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Reserved FCO FCO FCO - RW RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 3 Reserved -

2 FCO2 PCAxC force output setting bit(SM[1:0] =01)

0: No force output 1: Force output, cleared by hardware.

1 FCO1 PCAxB force output setting bit(SM[1:0] =01)

0: No force output 1: Force output, cleared by hardware.

0 FCO0 PCAxA force output setting bit(SM[1:0] =01)

0: No force output 1: Force output, cleared by hardware.

17.12.5 PCAx Counter Value Register (PCAx_CNT)

Offset Address: 0x0010 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 CNTH[15:0] RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 CNTL[15:0] RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 16 CNTH[15:0] PCAx Counter High 16-Bit 15 ~ 0 CNTL[15:0] PCAx Counter Low 16-Bit

17.12.6 Prescaler (PCAx_PSC)

Offset Address: 0x0014 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 PSC[15:0] RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 16 Reserved - 15 ~ 0 PSC[15:0] Prescaler Value The PCA counter clock frequency is equal to PCLK / (PSC[15:0] + 1). PSC contains the value to be loaded in the active prescaler register at each update event

17.12.7 PCAx Period Register (PCAx_PR)

Offset Address: 0x0018 Reset Value: 0xFFFF FFFF b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 PRH[15:0] RW 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 PRL[15:0] RW 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit Sign Description 31 ~ 16 PRH[15:0] PCAx Period Value(MSB) 15 ~ 0 PRL[15:0] PCAx Period Value(LSB)

17.12.8 PCAx Capture/Compare Register0 (PCAx_CCMR0)

Offset Address: 0x001C Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Reserved CSS EL ICF[2:0] CC SM[1:0] FS[1:0] CEN TCP Rese rved CCIE - RW RW RW RW RW RW RW - RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 13 Reserved -

12 CSSEL Capture source selection bit

0: PCAxA is used as the capture input source. 1: CMP0_C0OUT0 is used as the capture input source. Note: Only valid in capture mode 11 ~ 9 ICF[2:0] PCAxC input Channel filter selection bit(only for Mode0) 000: No filter 001: Filter time constant is 40*PCLK 010: Filter time constant is 80*PCLK 011: Filter time constant is 160*PCLK 100: Filter time constant is 320*PCLK 101: Filter time constant is 640*PCLK 110: Filter time constant is 1280*PCLK 111: Filter time constant is 2560*PCLK

8 CC The Enable bit of Clearing Counter, after capture occurs

0: No clear, after capture occurs 1: Clear counter, after capture occurs 7 ~ 6 SM[1:0] PCAx Mode Selection 00: Capture mode 01: Compare mode 10: Frequency output mode 11: PWM mode 5 ~ 4 FS[1:0] While SM[1:0] is 00b, the bits are for capture mode. 0X: Trigger at the rising edge 10: Trigger at the falling edge 11: Trigger at the rising and falling edges While SM[1:0] is 01b, the bits are for compare mode. 0X: Continuous match 1X:Single match While SM[1:0] is 11b, the bits are for PWM mode. 00: 16-bit PWM1 mode 01: 32-bit PWM2 mode 10: 32-bit PWM3 mode 11: 32-bit PWM4 mode While SM[1:0] is 10b, the bits are invalid.

3 CEN Capture/Compare Control Bit

0: Disable capture/compare module 0 1: Enable capture/compare module 0

2 TCP While SM[1:0] is 00b, this bit is the flag of capture mode

0: Capture at the falling edge of PCAxA 1: Capture at the rising edge of PCAxA While SM[1:0] is 01b or 10b or 11b, this bit is the control bit of wave output. 0: The initial level is high. 1: The initial level is low.

0 CCIE Capture/Compare Interrupt Control Bit

0: Disable capture/compare interrupt 1: Enable capture/compare interrupt

17.12.9 PCAx Capture/Compare Register1 (PCAx_CCMR1)

Offset Address: 0x0020 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Reserved CSS EL ICF[2:0] CC SM[1:0] FS[1:0] CEN TCP Rese rved CCIE - RW RW RW RW RW RW RW - RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 13 Reserved - 0: PCAxB is used as the capture input source. 1: CMP0_C0OUT1 is used as the capture input source. Note: Only valid in capture mode 11 ~ 9 ICF[2:0] PCAxB Input Channel Filter selection Bit(only for Mode0) 000: No filter 001: Filter time constant is 40*PCLK 010: Filter time constant is 80*PCLK 011: Filter time constant is 160*PCLK 100: Filter time constant is 320*PCLK 101: Filter time constant is 640*PCLK 110: Filter time constant is 1280*PCLK 111: Filter time constant is 2560*PCLK 0: No clear, after capture occurs 1: Clear counter, after capture occurs 7 ~ 6 SM[1:0] PCAx Mode Selection 00: Capture mode 01: Compare mode 10: Frequency output mode 11: PWM mode 5 ~ 4 FS[1:0] While SM[1:0] is 00b, the bits are for capture mode. 0X: Trigger at the rising edge 10: Trigger at the falling edge 11: Trigger at the rising and falling edges While SM[1:0] is 01b, the bits are for compare mode. 0X: Continuous match 1X:Single match While SM[1:0] is 11b, the bits are for PWM mode. 00: 16-bit PWM1 mode 01: 32-bit PWM2 mode 10: 32-bit PWM3 mode 11: 32-bit PWM4 mode While SM[1:0] is 10b, the bits are invalid. 0: Disable capture/compare module 1 1: Enable capture/compare module 1

0: Capture at the falling edge of PCAxB 1: Capture at the rising edge of PCAxB While SM[1:0] is 01b or 10b or 11b, this bit is the control bit of wave output. 0: The initial level is high. 1: The initial level is low. 0: Disable capture/compare interrupt 1: Enable capture/compare interrupt

17.12.10 PCAx Capture/Compare Register2(PCAx_CCMR2)

Offset Address: 0x0024 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Reserved CSS EL ICF[2:0] CC SM[1:0] FS[1:0] CEN TCP Rese rved CCIE - RW RW RW RW RW RW RW - RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 13 Reserved - 0: PCAxC is used as the capture input source. 1: CMP0_C0OUT2 is used as the capture input source. Note: Only valid in capture mode 11 ~ 9 ICF[2:0] PCAxC input Channel filter selection bit(only for Mode0) 000: No filter 001: Filter time constant is 40*PCLK 010: Filter time constant is 80*PCLK 011: Filter time constant is 160*PCLK 100: Filter time constant is 320*PCLK 101: Filter time constant is 640*PCLK 110: Filter time constant is 1280*PCLK 111: Filter time constant is 2560*PCLK 0: No clear, after capture occurs 1: Clear counter, after capture occurs 7 ~ 6 SM[1:0] PCAx Mode Selection 00: Capture mode 01: Compare mode 10: Frequency output mode 11: PWM mode

5 ~ 4 FS[1:0] While SM[1:0] is 00b, the bits are for capture mode. 0X: Trigger at the rising edge 10: Trigger at the falling edge 11: Trigger at the rising and falling edges While SM[1:0] is 01b, the bits are for compare mode. 0X: Continuous match 1X:Single match While SM[1:0] is 11b, the bits are for PWM mode. 00: 16-bit PWM1 mode 01: 32-bit PWM2 mode 10: 32-bit PWM3 mode 11: 32-bit PWM4 mode While SM[1:0] is 10b, the bits are invalid. 0: Disable capture/compare module2 1: Enable capture/compare module 2 0: Capture at the falling edge of PCAxC 1: Capture at the rising edge of PCAxC While SM[1:0] is 01b or 10b or 11b, this bit is the control bit of wave output. 0: The initial level is high. 1: The initial level is low. 0: Disable capture/compare interrupt 1: Enable capture/compare interrupt

17.12.11 PCAx Capture/Compare Register 0 (PCAx_CCR0)

Offset Address: 0x0028 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 CCR0H[15:0] RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 CCR0L[15:0] RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 16 CCR0H[15:0] PCAx Capture/Compare Register 0(MSB) 15 ~ 0 CCR0L[15:0] PCAx Capture/Compare Register 0(LSB) 17.12.12 PCAx Capture/Compare Register n (PCAx_CCRn)(n=1..2) Offset Address: 0x002C :0x0030 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 CCRnH[15:0] RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 CCRnL[15:0] RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

31 ~ 16 CCRnH[15:0] PCAx Capture/Compare Register n(MSB) 15 ~ 0 CCRnL[15:0] PCAx Capture/Compare Register n(LSB)

17.12.13 PCAx Lock Register (PCAx_LCKR)

Offset Address: 0x0034 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 KEY[15:0] RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 16 Reserved - 15 ~ 0 KEY[15:0] Lock Register 0x33CC: Allows modification to PCA registers by software. Others: Forbids modification to PCA registers by software. Note: Protected Registers are CR,CFGR,PR,PSC,CNT,CCMR0,CCMR1,CCMR2,CCR0,CCR1,CCR2,ADTR

17.12.14 ADC Compare Trigger Register (PCAx_ADTR)

Offset Address: 0x0038 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 DATA[31:0] RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 DATA[31:0] RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 0 DATA[31:0] 触发ADC比较Register 此Register的数值与计数器匹配时, 会触发ADC转换。

17.12.15 PCA Fault Detection Protection Register (PCAx_FLTWPR)

Offset Address: 0x003C Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 KEY[15:0] RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 16 Reserved - 15 ~ 0 KEY[15:0] Register Write Protection Register 0x33CC: Allows modification to FLTCR register by software. Others: Forbids modification to FLTCR register by software.

17.12.16 PCA Fault Detection Control Register (PCAx_FLTCR)

Offset Address: 0x0040 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Rese rved FLTI E FOUT[1:0] FLT SYN FLT1 EN FLT1SEL[1:0 FLT2DEB[3:0] FLT2 EN FLT2 S FLT M FLT STA T - RW RW RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 15 Reserved -

14 FLTIE Fault detection interrupt control bit

0: Fault detection interrupt disables. 1: Fault detection interrupt enables. 13 ~ 12 FOUT[1:0] Output status selection bit after the fault occurs: 0x: Outputs high resistance state 10: Outputs low level 11: Outputs high level

11 FLTSYN Fault detection synchronous control bit

0: Fault detection synchronous disables. 1: Fault detection synchronous enables. Note: When this bit of PCAx is set, another PCA fault detection (including fault detection 1 and fault detection 2) occurs, which will simultaneously change the output of both of PCA to a pre-set state.

10 FLT1EN Fault detection 1 function control bit

0: Fault detection 1 function disables. 1: Fault detection 1 function enables, comparator 0 or comparator 1 can be selected as input source

9 ~ 8 FLT1SEL[1:0] Fault detection 1 input source selection control bit 00: Output filtered by comparator 0 is used as input source of PCA fault detection 1, high level valid 01: Output filtered by comparator is used as input source of PCA fault detection 1, high level valid 1X: Reserved 7 ~ 4 FLT2DEB[3:0] Fault detection 2 input filter parameter selection 0000: No filter 0001: 0.5us 0010: 1us 0011: 1.5us 0100: 2us 0101: 3us 0110: 4us 0111: 6us 1000: 8us 1001: 10us 1010: 12us 1011: 14us 1100: 16us 1101: 20us 1110: 24us 1111: 32us Note : The above filter constant time is not exact value and is for reference only.

3 FLT2EN Fault detection 2 function control bit

0: Fault detection 2 function disables 1: Fault detection 2 function enables, the input source is FLT pin 0: Fault detection 2 FLT input is valid on high level 1: Fault detection 2 FLT input is valid on low level

1 FLTM Detection function mode selection

0: Latch mode, when the fault input is detected to be valid, FLTSTAT is set to 1 by hardware, PCA will stop output immediately, and the state will remain unchanged when the fault input becomes invalid. Only when FLTSTAT is cleared by software, the PCA waveform will resume output at the zero matching moment of the PCA time base counter or when it matches with the value of the periodic register PCAx_PR. (FLTSTAT cannot be cleared by software when the fault input keeps being valid) 1: Sequential mode, the PCA output is directly controlled by the fault detection input port. If the fault input is valid, FLTSTAT is set to 1 by hardware and the PCA output is immediately turned off. If the fault input becomes invalid, FLTSTAT is automatically cleared to 0, and the PCAxA/B/C waveform will automatically resume output when the PCA time base counter returns to 0.

0 FLTSTAT Fault detection flag bit

0: PCA module is in normal output state 1: Overcurrent is detected; PCA module is in stop output state. If it is in latch mode, it can be cleared by software and PCA output can be resumed.

1. Basic Timer(TIM7～TIM8)

18.1 Introduction

There are two basic 16-bit timers that can be cascaded into two 32-bit timers. The two timers are clocked by the APB bus clock (PCLK) and can be configured to run with the PCLK clock. Two timers can be running on the low frequency RC (128K LSICLK) clock, and woks under STOP mode.

18.2 Features

 2x16-bit timers  Each timer is an auto-reload up-counter  Each timer can choose independent clock source  Each timer can select external clock source, which can be used as counter  Four 16-bit timers can be cascaded into two 32-bit timers

18.3 Function Description

○: can — : cannot PCLK is APB clock, and ICLK is clock source Item TIM7 TIM8 Clock source (ICLK) (1) PCLK (2) T7 (3) 128kHz RC(LSI) (1) PCLK (2) T8 (3) 128kHz RC(LSI) Clock source division ICLK/(PSQ[15:0]+1) ICLK/(PSQ[15:0]+1) Periodic setting register TIM7.TPR TIM8.TPR Input pin T7 T8 Output pin T7 T8 Cascading operation ○ ○ A/D conversion start-up trigger — TCNT overflow (TIM8.TF) Interrupt source TCNT overflow (TIM7.TF) TCNT overflow (TIM8.TF)

18.3.1 Operation of Counter/Timer

Each timer has a 16-bit counter TIMx_TCNT (x=7~8). There is a 2-bit clock source selector CLKS[1:0]@TIMx_CR, and there is a clock source divider TIMx_PSQ[15:0] (x=7~8). If set the IE bit of the TIMx_CR (x=7~8) register, the timer interrupt is enabled. When the timer is started, the counter counts up. When the register TIMx.TPR (x=7~8) overflow, TFx@TIMx is set and TCNT (x=7~8) is cleared. If TIMx interrupts are allowed, an interrupt will occur. CLKS[1:0] @TIMx is the selection bit of clock source for timer: PCLK, rising edge of TIMx input pin (Tx), internal LSI 128kHz RC, and another TIM overflow flag can be selected. Only TIM7 can select the overflow flag bit of TIM8 as the clock source (cascade).

When STR@TIMx_CR is set to 1, the timer is not reset, which means that if the STR@TIMx_CR bit is set to 1, the timer register will start counting from TIMx_TCNT. Therefore, the initial value of the timer counter should be set before the timer is allowed. In timer mode, the TC@TIMx_CR bit can be configured to automatically flip the Tx pin output level when TIMx overflows. With this configuration, the Tx pin is automatically set to output. Note 1: When the initial value written to TIMx_TCNT is greater than TIMx_TPR, TIMx_TCNT will continue to count up until it reaches 0xFFFF, and then it returns to 0x0000. Note 2: TIMx_TCNT can be modified while the timer is running and cleared once by hardware when the timer is stopped. Note 3: Timer overflow refers to the zero matching moment after the TIMx_TCNT counts up to be the same as TIMx_TPR. Note 4: The prescaler register can be modified while the timer is stopped and running. Note 5: The fastest frequency of Tx input is 1/2*PCLK. Note 6: The initial state of the Tx output level is consistent with the value of the IO port data register. The following figure shows the timer block diagram, where TIM7 and TIM8 can wake up STOP mode. Figure18-1 Timer Block Diagram Note 1: Timer 7 and 8 can operate in low consumption mode and can wake up low consumption with means of cascading. Note 2: In stop mode, the Tx port can also work. The Tx port has a 128K filter Note 3: When modifying TIMx_TCNT, make sure STR @CR_TIMx is 0. If CLKS[1:0]@TIMx_CR is 00, TIMx operates in normal mode. If CLKS[1:0]@TIMx_CR is 01 and the Tx port inputs external clock, TIMx can operate in normal mode or low consumption mode. If CLKS[1:0]@TIM7_CR is 10, the clock source of timer is 128K RC and TIMx can operate in low consumption mode and support turning on cascading function. Cascading Operation Cascading operation is the function of connecting 16-bit counters of 2 channels to form a 32-bit counter. The function of cascade operation is achieved by setting CASCEN@TIM7_CR to 1. The two combinations of cascades are as follows: Combination Upper 16-bit Lower 16-bit Timer 7 & 8 TIM7 TIM8

For the example of counter cascade operation, set the clock source of TIM7 to the falling edge of external pin T7 port, and the count is as shown below: Figure18-2 Cascade Operation Diagram Note 1: After cascading, only the value of TIM7 needs to be configured, and TIM8 need not to be configured. The lower value of TIM7_TCNT is automatically mapped to the lower 16-bit of TIM8_TCNT, so only the 32-bit register of TIM7 needs to be read while reading. The lower 16-bit registers of TIM8_TCNT are read-only. If it is required to write high 16-bit count value before counting, TIM7_TCNT need to be written. Note 2: When cascading, turning on the STR@CR bit of the lower bit TIM (TIM7) can start two timers simultaneously. External input clock source filtering When CLKS[1:0] @timx CR is set to 01b, the clock of the counter is provided by the falling edge of the external Tx pin. When ECF=0, there is no filtering effect; when ECF=1,2,3, the filtering time is 8PCLK,16PCLK, and 32PCLK clock cycle respectively.

18.4 Register

TIM Module Register List (base address: 0x4000 0C00) Address Register List Description 0x4000 0C00 CR TIM control register 0x4000 0C04 TCNT TIM count register 0x4000 0C08 TPR TIM periodic register 0x4000 0C0C PSQ TIM pre-division register 0x4000 0C10 TIMINTF TIMx interrupt flag and clear register

18.4.1 TIM Control Register (TIMx_CR)

Offset Address: 0x0000 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 CAS CEN Rese rved ECF[1:0] Rese rved TC ETE N TRIG EN IE Rese rved CLKS[1:0] OPM Reserved STR RW - RW - RW RW RW RW - RW RW - RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

31 ~ 16 Reserved -

15 CASCEN TIMx cascade enable bit (x=7, only valid at cascade high bit timer)

0: TIM7/TIM8 cascade function disabled 1: TIM7/TIM8 cascade function enabled Note: This bit can only be modified if both cascading timers have stopped counting. 13 ~ 12 ECF[1:0] Tx Input signal filter time 00: No filter 01: Filter time constant is 8*PCLK 10: Filter time constant is 16*PCLK 11: Filter time constant is 32*PCLK

10 TC Compare output function enable bit

0: Compare output function of timer x is disabled 1: Compare output function of timer x is enabled Note: When the timer allows compare output (TC = 1), the clock source cannot select the Tx (x = 7, 8) port.

9 ETEN TIMx overflow event enable bit

0: Timer overflow from waking up core is disabled 1: Timer overflow to wake up core is enabled

8 TRIGEN TIMx overflow trigger external module enable bit

0: Timer x overflow is disabled to trigger ADC modules 1: Timer x overflow is enabled to trigger ADC modules only TIM8 can trigger ADC

7 IE TIMx overflow interrupt enable bit

0: TIMx overflow interrupt is disabled 1: TIMx overflow interrupt is enabled 5 ~ 4 CLKS[1:0] TIMx clock source (ICLK) selection bit 00: Internal APB clock (PCLK) 01: Tx (x=7, 8) port input, automatic pull-up 10: Internal low frequency 128KHz RC oscillator (LSICLK) 11: Reserved Note: This bit of the high 16-bit TIM is invalid when cascading, read-only attribute, same as this bit of the lower bit TIM

3 OPM Single pulse mode

0: When timer x overflows, the timer doesn’t stop 1: When timer x overflows, the timer stops Note: This bit of the high 16-bit TIM is invalid when cascading, read-only attribute, same as this bit of the lower bit TIM 2 ~ 1 Reserved -

0 STR TIMx start-up bit (x= 7, 8)

Note 1: Can be triggered by software or by external module Note 2 This bit of the high 16-bit TIM is invalid when cascading, read-only attribute, same as this bit of the lower bit TIM

18.4.2 TIM Counter Register (TIMx_TCNT)

Offset Address: 0x0004 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 TCNTH[15:0] RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 TCNTL[15:0] RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 16 TCNTH[15:0] Timer count value upper 16-bit: only TIM7 bits valid Note: Only valid when cascading. 15 ~ 0 TCNTL[15:0] Timer count value lower 16-bit: all TIM valid Note: This register is automatically cleared and only cleared once when the timer is stopped.

18.4.3 TIM Periodic Register (TIMx_TPR)

Offset Address: 0x0008 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 TPRH[15:0] RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 TPRL[15:0] RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 16 TPRH[15:0] Timer automatic reload upper 16-bit: only TIM7 bits valid Note: Only valid when cascading, for example, the read and write values of TIM8.TCNTL and TIM7.TCNTH are the same. 15 ~ 0 TPRL[15:0] Timer automatic reload register Note: Lower 16-bits, all TIM valid.

18.4.4 TIM Pre-division Register (TIMx_PSQ)

Offset Address: 0x000C Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 PSQH[15:0] RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 PSQL[15:0] RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 16 PSQH[15:0] Timer pre-division higher 16-bit: only TIM7bits valid Note: Only valid when cascading. 15 ~ 0 PSQL[15:0] Timer pre-division lower 16-bit: all TIM valid Note: The timer clock is (ICLK/(PSQ[15:0]+1)).

18.4.5 TIMx Interrupt Flag and Clear Register (TIMx_TIMINTF)

Offset Address: 0x0010 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved TFC - WO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Reserved TF - RO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 17 Reserved -

16 TFC TIMx overflow flag bit clear bit

0: Invalid 1: Clear 15 ~ 1 Reserved -

0 TF TIMx overflow flag bit

0: TIMx has no overflow and can be cleared by software. 1: TIMx overflows and is set to 1 by hardware Note: After cascading, the flag bit is set only at 32-bit overflow.

1. Math Co-Processor Unit, MACP

19.1 Introduction

The math co-processor unit of SH33F2801includes a 32-bit CORDIC calculation unit (referred to as CORDIC) and a motor-specified SVPWM enhancement engine (referred to as SVPWM). The CORDIC unit can achieve rotation and vector operations based on circular functions, linear function and hyperbolic function iteration, especially can quickly complete high-precision sine and cosines operation, modulus operation, square root operation, etc.. The motor-specified SVPWM enhancement engine can complete the seven-segment SVPWM calculation commonly used in motor vector control in hardware method, which effectively improves the calculation efficiency and is very meaningful in high-performance motor control. Since the math co-processor unit is implemented by independent hardware, it can effectively save program operating time, reduce CPU load, and improve the execution efficiency of key algorithms.

19.2 Register List

MACP Module Register List (Base address: 0x4004 1400) Address Register Name Description 0x4004 1400 CORDCSR0 CORDIC control and status register 0 0x4004 1404 OPRDX0 CORDIC operation operand X register 0 0x4004 1408 OPRDY0 CORDIC operation operand Y register 0 0x4004 140C OPRDZ0 CORDIC operation operand Z register 0 0x4004 1410 CORDCSR1 CORDIC control and status register 1 0x4004 1414 OPRDX1 CORDIC calculation operand X register 0x4004 1418 OPRDY1 CORDIC calculation operand X register 0x4004 141C OPRDZ1 CORDIC calculation operand X register 0x4004 1600 SVCON SVPWM calculation start-up flag register 0x4004 1604 SVUALPHA SVPWM input Ualpha value register 0x4004 1608 SVUBETA SVPWM input Ubeta value register 0x4004 160C SVIQN SVPWM data format configuration register 0x4004 1610 SVTA SVPWM output Ta value register 0x4004 1614 SVTB SVPWM output Tb value register 0x4004 1618 SVTC SVPWM output Tc value register 0x4004 161C SVSECTOR SVPWM quadrant register

19.3 CORDIC Calculation Unit

19.3.1 Main Features

 Achieving rotation mode and vector mode based on CORDIC algorithm (circle function)  CORDIC calculation uses pre-processing and post-processing logic and is able to support the full range of round functions  CORDIC calculation supports three preset data formats of IQ26/IQ24/IQ15  CORDIC supports the automatic elimination of the K factor of calculation results  One calculation engine, two sets of control and operand registers

19.3.2 Function Description

19.3.2.1 CORDIC Calculation Unit

SH33F2801 has a hardware CORDIC calculation unit built in, which can achieve the basic CORDIC algorithm. The CORDIC algorithm is an iterative process, which is performed N times of iterations per calculation, and is completed in N+2 cycles (when the K factor is not turned on). It can be used to solve the circular function (trigonometric function) and more. The general CORDIC algorithm corresponds to the following CORDIC equation: i iii ydmxx − + ⋅⋅⋅−= 2i1 i iiii xdyy − + ⋅⋅+= 21 iiii edzz ⋅−=+1 Where m=1 is circular function iteration, m=0 is linear function iteration, and m=-1 is hyperbolic function iteration. In rotation mode: 0, ii →= zzsigndi ）（ In vector mode: 0 , ii →= yysigndi ）（ )2arctan( i ie −=

19.3.2.2 Operation of CORDIC Co-processor

The CORDIC co-processor can work in rotation or vector mode; it is used to calculate circular function (trigonometric function) (note). The rotation or vector mode can be set via the MODE@MACP_CORDCSRx. Through ARITH[1:0] @macp CORDCSRx control bits, circular function iteration, linear function iteration and hyperbolic function iteration can be selected to realize different functions respectively. The commonly used circular function iteration can realize sine function, cosine function, phase Angle, modulus and other general operations. Linear iteration can implement linear functions. Hyperbolic iteration can realize hyperbolic sine, hyperbolic cosine and other operations, and can be extended to realize the square root operation. After the corresponding initial value is assigned to the X, Y, Z data registers according to the function that needs to be executed, the CORDIC calculation is started (RUN = 1). CORDIC loads the contents of the data register into the core calculation register, and start the operation by setting RUN. The RUN bit is always 1 during the calculation. It is cleared by hardware after the calculation has ended, and the calculation result is automatically output to the result register. If the RUN bit is forcibly cleared during the calculation process, the current calculation stops immediately and the result of the calculation is not output to the result register (keeping previous value). After the calculation has ended, if there is data overflow, the OVF flag bit is set. Since the CORDIC calculation results have the K factor inherent in the algorithm, if it is required to eliminate the factor, the elimination can be done after turning on K factor, or be calculated and done by user software. The CORDIC calculation engine has only one set (note 1), but has two sets of completely independent control and operand registers (group 0 and group 1). The two sets of registers can be independently configured for the operating mode. Set the RUN control bits of the two sets of registers (RUN0 and RUN1 are in two register addresses and cannot be set at the same time. Here RUN0 being set first is assumed), then group 0 operates first, group 1 is in the waiting state. After group 0 has finished its operation, immediately switch to group 1 operation. Note 1: This means rotation mode and vector mode can only be operated in succession. The input data register cannot be modified during operation to ensure that the operation data will not be tampered with, but the MODE@MACP_CORDCSRx control bit is not masked. If the MODE bit is changed during operation, error result will be obtained, and this requires guarantee from the user software.

A typical application is to use register group 0 to perform an operation (rotation or vector) in the main flow, and use register group 1 to perform another operation (rotation or vector) in the interrupt. Because the hardware has automatic convergence processing for these two operations, the overhead of status query and data input & output can be reduced.

19.3.2.3 Data accuracy and iteration times

CORDIC allows up to 27 bits of data precision, corresponding to 27 iterations; the default data format IQ26, input data requirements between IQ26(-1) and IQ26(+1). CORDIC also supports 16 bits of data precision, corresponding to 16 iterations; the default data format IQ15, input data requirements between IQ15(-1) and IQ15(+1). For 32Bit system, the CORDIC operand register is 32-bit width. When using 27-bit CORDIC to calculate, The input data range is IQ26(-1) ~ IQ26(+1) actually, and CORDIC will directly intercept SignBit and effective data Bit for operation. 02531 30 Valid Data BitsSign Bit Invalid Data Bits The effective Bit of 32Bit input data at the time of 27-bit CORDIC calculation Note: If the input data is stored in a 2’s complement format, the invalid data Bit here is a SignBit extension. For a 16Bit system, the CORDIC operand register is still 32Bit wide, and the high 16Bit data is invalid. 14 0151631 Invalid Data Bits Valid Data Bits Sign Bit The effective data Bit of 32Bit input data in 16-bit CORDIC calculation

19.3.2.4 Data Format

The initial data X, Y, and Z inputs of the CORDIC co-processor are all signed number two-complement format. The result data is also signed number two-complement format. There is one exception being that the X result data in vector mode will be stored as unsigned numbers, which prevents potential X data results from overflowing. In this case, MSB (highest bit) is also a data bit. The X operation result is always positive only when working in vector mode. The X and Y input data formats can be integers or fixed-point numbers, but the X data and Y data must be consistent in any calculation. If they are a fixed-point decimals, they must have the same number of decimal places. As for Z data, it is always normalized integer value. In rotation mode, Z represents angle when it is used as input data, and ]2 1-2,[ N N ππ ）（− is represented by ]1-2,2[ NN ）（− . In vector mode, Z also represents angle when it is used as input data, and the resolution of angle is N2 π . Initial value of input Z = Initial value of real number Z (radian) × π Result data of real number Z (radian) = Z result data × N2 π Note: N can be 15 and 26, corresponding to 16 and 27 CORDIC respectively. It should be noted that the calculation result of CORDIC contains an intrinsic gain factor K caused by rotation mode or vector mode, while in the circle function K≈1. 6467602579.

19.3.2.5 Overflow Flag and Amplitude Adjustment

If overflow occurs during the CORDIC calculation process, an OVF flag is generated. There is one exception being that the X result data in the circular function vector mode will be fixedly stored as an unsigned number, if the calculation result is within the range of [0, 2^(N+1)], no overflow flag will be generated. In addition, the XYMRS bit of CORDCSR can be used to set the amplitude adjustment of the CORDIC result data. If XYMRS is set to 1, then after the CORDIC iteration is finished, calculation results of X and Y are divided by 2 and stored in X and Y registers, and this can effectively prevent the result data from overflowing.

19.3.2.6 Operation Mode and Corresponding Result Data

The CORDIC equation is as follows. The coprocessor operation mode and corresponding result data are shown in the table below. Xresult, Yresult, Zresult are the final data, and X, Y, Z represents initial values. i iii ydxx − + ⋅⋅−= 2i1 i iiii xdyy − + ⋅⋅+= 21 iiii edzz ⋅−=+1 Table19-1 CORDIC Operation Mode and Corresponding Result Data(circular function) Circular function )2arctan( i ie −= Rotation Mode Vector Mode 0zzsignd iii →= ,）（ 0y ,ysignd iii →= ）（ )]sin()cos([ ZYZXKX result −= )]cos()sin([ ZYZXKYresult += 0=resultZ In these, K≈1.6467602579 22X YKX result += 0=resultY )/arctan( XYZZresult += In these, K≈1.6467602579 Set 0,1 == YKX Then )cos(ZX result = , )sin(ZYresult = Because CORDIC internally uses preprocessing logic, X, Y and Z can take the full range ( ]1-2,2[ NN ）（− ) of values (N can be 15 and 26). Set KYYKXX == , Then vector magnitude

22 YXX result +=

Because CORDIC internally uses preprocessing and postprocessing logic, X, Y can take the full range ( ]1-2,2[ NN ）（− ) of values (N can be 15 and 26). Set 0=Z Then )/arctan( XYZresult = Because CORDIC internally uses preprocessing and postprocessing logic, X, Y can take the full range ( ]2,2[ ）（ 1-NN− ) of values (N can be 15 and 26), except for the case X=0.

19.3.2.7 K factor post-processing

As shown in the above table, there is a K factor in the CORDIC calculation results. When the factor needs to be removed in some applications, the K factor post-processing function can be turned on(KADJ@MACP.CORDCSR). When setting KADJ=1, the output of X and Y is multiplied by 1/K(the output of Z is not affected). Take circular function iteration as an example:  27-bit CORDIC, Q26(1/K) = Q26 (0.607252935) = 0x26DD3B6  16-bit CORDIC, Q15(1/K)= Q15 (0.607252935) = 0x4DBA K-factor post-processing is in the output phase of CORDIC operation, after overflow processing, so it is meaningless to carry out k-factor processing on the data overflow from the front end. K factor post-processing will add an additional 3 cycles of operation time, and the total operation time will increase to N+5. Park and iPark algorithms commonly used in motor vector control can be realized by using CORDIC circle function iteration, and k-factor post-processing needs to be turned on. PARK IPARK )sin(I)cos(I )sin(I)cos(I θθ θθ βα αβ d q I I )sin()cos( )sin()cos( θθ θθ β α dq qd UUU UUU dresultqresult dresultqresult IYIX KADJoutput KIYKIX KADJoutput Z IYIX input θ αβ βα βα θ UYUX KADJoutput KUYKUX KADJoutput Z UYUX input resultresult resultresult qd

19.3.2.8 CORDIC computational accuracy

In circular function rotation mode, X and Y can be any fixed point format (Qx or IQx)。But considering the error of the result and the improvement of resolution, the value should be enlarged as much as possible. In extreme cases, if the absolute value of input X and Y is too small (after fixed point), a large calculation error will occur. Therefore, if possible, users are recommended to fixed-point according to the maximum value, such as IQ26 for 32-bit system and IQ15 for 16-bit system.

19.3.2.9 IQ24 Data format

The CORDIC module uses the 27-bit CORDIC arithmetic kernel to support the IQ24 data format, adding the necessary preprocessing and post-processing. The user selects FORMAT=01b, the hardware can complete the processing without software processing.

Table19-2 Range of input and output values in different patterns and data formats of CORDIC (take circular function iteration as an example) CORDIC Default data format IQ26 IQ24 IQ15 rotate input: X: IQ26[-1]～IQ26(+1) Y: IQ26[-1]～IQ26(+1) Z: IQ26[-1]～IQ26(+1) input: X: IQ24[-4]～IQ24(+4) Y: IQ24[-4]～IQ24(+4) Z: IQ24[-1]～IQ24(+1) Z ×4 is automatically processed inside CORDIC input: X: IQ15[-1]～IQ15(+1) Y: IQ15[-1]～IQ15(+1) Z: IQ15[-1]～IQ15(+1) output: (bypass KADJ) X: IQ26[-1]～IQ26(+1) Y: IQ26[-1]～IQ26(+1) Z: -->0 output: (bypass KADJ) X: IQ24[-4]～IQ24(+4) Y: IQ24[-4]～IQ24(+4) Z: -->0 output: (bypass KADJ) X: IQ15[-1]～IQ15(+1) Y: IQ15[-1]～IQ15(+1) Z: -->0 output: (enable KADJ) X: IQ26[-1/K]～IQ26(+1/K) Y: IQ26[-1/K]～IQ26(+1/K) Z: -->0 output: (enable KADJ) X: IQ24[-4/K]～IQ24(+4/K) Y: IQ24[-4/K]～IQ24(+4/K) Z: -->0 Note: There will be no automatic shift in X and Y, and the shift is only for Z. output: (enable KADJ) X: IQ15[-1/K]～IQ15(+1/K) Y: IQ15[-1/K]～IQ15(+1/K) Z: -->0 vector input: X: IQ26[-1]～IQ26(+1) Y: IQ26[-1]～IQ26(+1) Z: IQ26[-1]～IQ26(+1) input: X: IQ24[-4]～IQ24(+4) Y: IQ24[-4]～IQ24(+4) Z: IQ24[-1]～IQ24(+1) Z "×4" is automatically processed inside CORDIC input: X: IQ15[-1]～IQ15(+1) Y: IQ15[-1]～IQ15(+1) Z: IQ15[-1]～IQ15(+1) output: (bypass KADJ) X: IQ26[0]～IQ26(+2) Y: -->0 Z: IQ26[-1]～IQ26(+1) output: (bypass KADJ) X: IQ24[0]～IQ24(+8) Y: -->0 Z: IQ24[-1]～IQ24(+1) Z "×4" is automatically processed inside CORDIC output: (bypass KADJ) X: IQ15[0]～IQ15(+2) Y: -->0 Z: IQ15[-1]～IQ15(+1) output: (enable KADJ) X: IQ26[0]～IQ26(+2/K) Y: -->0 Z: IQ26[-1]～IQ26(+1) output: (enable KADJ) X: IQ24[0]～IQ24(+8/K) Y: -->0 Z: IQ24[-1]～IQ24(+1) Z "×4" is automatically processed inside CORDIC output: (enable KADJ) X: IQ15[0]～IQ15(+2/K) Y: -->0 Z: IQ15[-1]～IQ15(+1)

19.3.3 CORDIC Register

Offset Address: 0x0000 :0x0010 Reset Value: 0x0000 1F00 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Rese rved ARITH[1:0] ITERA[4:0] MOD E FORMAT[1:0 Rese rved XYM RS KAD J OVF RUN - RW RW RW RW - RW RW RO RW 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 15 Reserved - 14 ~ 13 ARITH[1:0] CORDIC Iterative algorithm selection 00: Circular function iteration (default) 01: Linear function iteration 1x: Hyperbolic function iteration 12 ~ 8 ITERA[4:0] Iteration number selection The maximum number of iterations is 31, which is set in FORMAT by default In IQ24/IQ26 format, the default is 27 iterations In IQ15 format, it is recommended to set 16 times, which needs to be manually modified by the user Generally, the number of iterations should match the data format, but the user can also adjust the number of iterations artificially to balance the accuracy and speed. The detailed accuracy should refer to the theoretical analysis and be confirmed by the user himself. Here, only the calculation results are given and no judgment is made.

7 MODE CORDIC mode selection bit

0: Rotation bit 1: Vector bit 6 ~ 5 FORMAT[1:0] CORDIC calculation data format 00: IQ26 format (default) 01: IQ24 format 1x: IQ15 format Note: IQ26/IQ24 are both operating with 27-bit CORDIC, and IQ15 is operating with 16-bit CORDIC. The operating data format is not limited to the above three types, and the user can input in other formats, but the input and output need to be adjusted.

4 Reserved -

3 XYMRS CORDIC calculation XY amplitude adjustment selection bit

0: X and Y are unchanged as the final result after the last iteration 1: X and Y are divided by 2 to be the final result after the last iteration. Note: Setting the XYMRS bit correctly will prevent the result data from overflowing

2 KADJ CORDIC calculation K factor adjustment selection bit

0: The operation result is not adjusted by 1/K. 1: The operation result is multiplied by 1/K to eliminate the K factor. Note: K=1.646760

1 OVF CORDIC calculation overflow flag bit (set to 1 or cleared by hardware)

0: No overflow occurs 1: There is overflow occurring Note: After the calculation is completed, this flag remains until it is cleared when the module is reset or the next calculation starts.

0 RUN CORDIC calculation start-up and flag bit, can only be set to 1 by

software, and cleared by hardware of software 0: Calculation has completed or not started 1: Starts cordic calculation, the flag is 1 during the calculation, and it is cleared by hardware after the calculation is completed. Note: RUN is allowed to be cleared during the calculation to force the calculation to end. The CORDIC internal flag is cleared when starts RUN. Offset Address: 0x0004 :0x0014 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 OPRDXn[31:0] RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 OPRDXn[31:0] RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 0 OPRDXn[31:0] Before the calculation: Stores Cordic calculation X operand After the calculation is completed: Stores Cordic calculation X result Offset Address: 0x0008 :0x0018 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 OPRDYn[31:0] RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 OPRDYn[31:0] RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

31 ~ 0 OPRDYn[31:0] Before the calculation: Stores Cordic calculation Y operand After the calculation is completed: Stores Cordic calculation Y result Offset Address: 0x000C :0x001C Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 OPRDZn[31:0] RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 OPRDZn[31:0] RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 0 OPRDZn[31:0] Before the calculation: Stores Cordic calculation Z operand After the calculation is completed: Stores Cordic calculation Z result

19.4 Motor-specified SVPWM Enhancement Engine

19.4.1 SVPWM Function

The SH33F2801 includes a space vector pulse width modulation (SVPWM) algorithm for three-phase motor; It is corresponding to a special switch trigger sequence and combination of pulse width for power component of a three-phase voltage source inverter in AC induction motor or permanent magnet synchronous motor. This switch trigger sequence and combination will produce 3-phase sinusoidal currents in the stator coil that are 120 degrees apart from each other.

19.4.1.1 Principle of SVPWM Algorithm

The pulse width modulation signal of the 3-phase motor voltage signal is generated by the SVPWM algorithm, and the generation process of the pulse width per phase can be simplified into several first-order equations. The output of each phase of the 3-phase inverter can be one of two states, which means the inverter output can be connected to the positive bus terminal or the negative bus terminal, which makes the 3-phase inverter output have 8 possible statuses in total. The two states in which the 3-phase outputs are all connected to the positive bus terminal or the negative bus terminal are regarded as invalid, because no line voltage exists between any two phases at this time. These two states are drawn as origins in the star map. The remaining six states are represented as vectors with a rotation interval of 60 degrees between each two adjacent states, as shown in the following figure. Figure19-1 Space Vector Modulation The process of space vector modulation allows any spatial voltage vector to be represented by the sum of the components of two adjacent vectors. In the figure below, UOUT is the expected space voltage vector. This vector is located in the interval between U60 and U0. If, during a given PWM period T, the output time of U0 is T1/T and the output time of U60 is T2/T, the average voltage value of the entire period is UOUT. Figure19-2 Average Space Vector Modulation Period Invalid vector

T0 represents the time at which there is no effective voltage on the winding, which means invalid vector is applied. In each of the six intervals, one axis is exactly opposite to this interval, and the other two axes are symmetrically formed to form the boundary of the interval. The vector components along these two boundary axes are T1 and T2 respectively.

19.4.1.2 SVPWM Algorithm Implementation Process

First, transform the stationary 2-axis α-β coordinate system into the defined stationary 3-axis reference coordinate system; it requires Uα and Uβ inputs from two stationary coordinate systems. Shown as follows: ( ) ( ) −−= +−= 2/*3 2/*3 αβ αβ β UUV UUV UV r r r At the same time, three variables a, b, c are defined. If Vr1>0, then a=1, otherwise a=0; if Vr2>0, then b=1, otherwise b=0; if Vr3>0, then c=1, otherwise c=0. Then define a variable sector, sector = a*1+b*2+c*4, and divide the space into 6 sectors according to the sector. Additionally, define: ( ) ( ) 2/*3 2/*3 αβ αβ β UUZ UUY UX For T1, T2 values of different sectors, the correspondences are as follows: Table19-3 Sector and Time Correspondence Table Sector 1 2 3 4 5 6 T1 Z Y -Z -X X -Y T2 Y -X X Z -Y -Z In the PWM period T, the output time of the vector T1 is T1/T, the output time of the vector T2 is T2/T, and the invalid vector is output for the remaining time. The invalid vector can be composed of all zeros and is a five-segment SVPWM waveform. It can also be composed of all ones in the middle and all zeros on both ends, which is an SVPWM waveform with seven-segment.

19.4.1.3 Five-Segment SVPWM Algorithm

The figure below shows a SVPWM waveform with five-segment with the PWM signal configured to output center-aligned. This configuration method can generate one line-to-line pulse per period. Figure19-3 PWM in Period T

SH33F2801 can achieve direct calculation of the 3-phase duty cycles of Ta, Tb, and Tc from Ualpha and Ubeta. The data format of input and output can be set. 饱和处理 Ta Tb Tc 1() ra sign V= sec 2* 4*t o r abc= ++ 1r betaVU= 2 ( * 3) / 2r beta alfaV UU= −+ 3 ( * 3) / 2r beta alfaV UU= −− alphaU betaU Sector Sector=SvpwmSector[Sector] Sector=0,7: Ta=Tb=Tc=IQN(0.5); Sector=1: t1 = Z; t2 = Y; Tc = 0; Ta = Tc + t2; Tb = Ta + t1; Sector=2: t1 = Y; t2 = -X; Tb = 0; Tc = Tb + t2; Ta = Tc + t1; Sector=3: t1 = -Z; t2 = X; Tc = 0; Tb = Tc + t2; Ta = Tb + t1; Sector=4: t1 = -X; t2 = Z; Ta = 0; Tb = Ta + t2; Tc = Tb + t1; Sector=5: t1 = X; t2 = -Y; Ta = 0; Tc = Ta + t2; Tb = Tc + t1; Sector=6: t1 = -Y; t2 = -Z; Tb = 0; Ta = Tb + t2; Tc = Ta + t1; Saturation algorithm Ta Tb Tc Sector IQN betaXU= ( * 3) / 2beta alfaYU U= + ( * 3) / 2beta alfaZU U= − 2() rb sign V= 3() rc sign V= Figure19-4 Flowchart of five-Segment SVPWM algorithm Note1：Ualpha, Ubeta, T1, T2 ,Ta,Tb and Tc Signed 32 bits, IQN and Sector are unsigned 8 bits. Note2：Multiplication is IQN format multiplication. Note3 ： SvpwmSector[]={0,1,5,0,3,2,4,0}

19.4.1.4 Seven-Segment SVPWM Algorithm

The figure below shows a SVPWM waveform with seven-segment with the PWM signal configured to output center-aligned. This configuration method can generate two line-to-line pulses per period. The effective switching frequency is doubled, the ripple current is reduced, and the switching consumption of the power component is not increased. Figure19-5 PWM in Period T SH33F2801 can achieve direct calculation of the 3-phase duty cycles of Ta, Tb, and Tc from Ualpha and Ubeta. The data format of input and output can be set.

1() ra sign V= sec 2* 4*t o r abc= ++ 1r betaVU= 2 ( * 3) / 2r beta alfaV UU= −+ 3 ( * 3) / 2r beta alfaV UU= −− alphaU betaU Sector Sector=SvpwmSector[Sector] Sector=0,7: Ta=Tb=Tc=IQN(0.5); Sector=1: t1 = Z; t2 = Y; Tc = (IQN(1) - t1 -t2) >> 1; Ta = Tc + t2; Tb = Ta + t1; Sector=2: t1 = Y; t2 = -X; Tb = (IQN(1) - t1 -t2) >> 1; Tc = Tb + t2; Ta = Tc + t1; Sector=3: t1 = -Z; t2 = X; Tc = (IQN(1) - t1 -t2) >> 1; Tb = Tc + t2; Ta = Tb + t1; Sector=4: t1 = -X; t2 = Z; Ta = (IQN(1) - t1 -t2) >> 1; Tb = Ta + t2; Tc = Tb + t1; Sector=5: t1 = X; t2 = -Y; Ta = (IQN(1) - t1 -t2) >> 1; Tc = Ta + t2; Tb = Tc + t1; Sector=6: t1 = -Y; t2 = -Z; Tb = (IQN(1) - t1 -t2) >> 1; Ta = Tb + t2; Tc = Ta + t1; Saturation algorithm Ta Tb Tc Sector IQN betaXU= ( * 3) / 2beta alfaYU U= + ( * 3) / 2beta alfaZU U= − 2() rb sign V= 3() rc sign V= Figure19-6 Flowchart of Seven-Segment SVPWM algorithm Note1：Ualpha, Ubeta, T1, T2 ,Ta,Tb and Tc Signed 32 bits, IQN and Sector are unsigned 8 bits. Note2：Multiplication is IQN format multiplication. Note3 ： SvpwmSector[]={0,1,5,0,3,2,4,0}

19.4.1.5 Sign Algorithm

Where Sign is the sign algorithm, the detailed algorithm is as follows a = sign(x): if (x > 0) a = 1; else a = 0;

19.4.1.6 Saturation algorithm

No matter the five-stage formula or the seven-stage formula, there may be overflow. When any calculation result of Ta/Tb/Tc exceeds the range, the overflow flag BitOVER @sviqn will be set. In order to prevent overflow of calculation results, saturation treatment of Ta,Tb and Tc is added. Register SATEN@SVIQN is used to select whether to saturate. The detailed algorithm is as follows: if(Tx < 0) OVER@SVIQN = 1; if (1 == SATEN@SVIQN) Tx = 0; else if(Tx > IQN(1)) OVER@SVIQN = 1; if(1 == SATEN@SVIQN) Tx = IQN(1); Note1: x=a,b,c Note 2: The calculation time of the whole SVPWM hardware is 3 AHB CLK. Note 3 The bit of the overflow flag is updated with each calculation.

19.4.2 SVPWM Register

19.4.2.1 SVPWM Calculation Start-up and Flag Register (MACP_SVCON)

Offset Address: 0x0200 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Reserved RUN - RW1 s 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 1 Reserved -

0 RUN SVPWM calculation start-up and flag bit, can only be cleared by

hardware and set to 1 by software 0: Calculation has completed, not started 1: Starts SVPWM calculation, the flag is 1 during calculation, and it is cleared by software when the calculation is complete

19.4.2.2 SVPWM Input Ualpha Value Register (MACP_SVUALPHA)

Offset Address: 0x0204 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 SVUALPHA[31:0] RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 SVUALPHA[31:0] RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 0 SVUALPHA[31:0] SVPWM Input Ualpha Value

19.4.2.3 SVPWM Input Ubeta Value Register (MACP_SVUBETA)

Offset Address: 0x0208 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 SVUBETA[31:0] RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 SVUBETA[31:0] RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 0 SVUBETA[31:0] SVPWM Input Ubeta Value

19.4.2.4 SVPWM Data Format Configuration Register (MACP_SVIQN)

Offset Address: 0x020C Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 OVE RCH OVE RBH OVE RAH OVE RCL OVE RBL OVE RAL SAT EN SVT YP SVIQN[7:0] RO RO RO RO RO RO RW RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 16 Reserved -

15 OVERCH Overflow flag Bit -C duty cycle is more than IQN:

0:No overflow 1: overflow Note: Reload the flag each calculation.

14 OVERBH Overflow flag Bit -B duty cycle is more than IQN:

0: No overflow 1: overflow Note: Reload the flag each calculation.

13 OVERAH Overflow flag Bit -A duty cycle is more than IQN:

0: No overflow 1: overflow Note: Reload the flag each calculation.

12 OVERCL Overflow flag Bit -C duty cycle is less than 0:

0: No overflow 1: overflow Note: Reload the flag each calculation.

11 OVERBL Overflow flag Bit -B duty cycle is less than 0:

0: No overflow 1: overflow Note: Reload the flag each calculation.

10 OVERAL Overflow flag Bit -A duty cycle is less than 0:

0: No overflow 1: overflow Note: Reload the flag each calculation.

9 SATEN Output saturation enable Bit:

0:Disable 1:Enable

8 SVTYP Five-segment/seven-segment selection bit

0: Seven-segment 1: Five-segment 7 ~ 0 SVIQN[7:0] SVPWM data format

19.4.2.5 SVPWM Output Ta Value Register (MACP_SVTA)

Offset Address: 0x0210 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 SVTA[31:0] RO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 SVTA[31:0] RO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 0 SVTA[31:0] SVPWM output Ta value

19.4.2.6 SVPWM Output Tb Value Register (MACP_SVTB)

Offset Address: 0x0214 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 SVTB[31:0] RO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 SVTB[31:0] RO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 0 SVTB[31:0] SVPWM output Tb value

19.4.2.7 SVPWM Output Tc Value Register (MACP_SVTC)

Offset Address: 0x0218 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 SVTC[31:0] RO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 SVTC[31:0] RO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 0 SVTC[31:0] SVPWM output Tc value

19.4.2.8 SVPWM Quadrant Register (MACP_SVSECTOR)

Offset Address: 0x021C Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Reserved SVSECTOR[7:0] - RO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 8 Reserved - 7 ~ 0 SVSECTOR[7:0] SVPWM quadrant

1. Analog to Digital Converter(ADC)

20.1 Introduction

SH33F2801 includes a single-ended 12-bit high-speed successive-approximation analog-to-digital converter (ADC). The block diagram is shown in Figure 20-1. The ADC reference voltage uses VDD by default after a chip reset. The user can also select the input of the external VREF port or the built-in VREF as the reference voltage. ADC Module has 16 analog input channels(AN0~AN10, OPxOUT(x=0,1,2,3), Vbg). The ADC can be programmed into the sequence for automatic conversion. The result is stored in the corresponding result register ADDRx (x = 0 - 15). Each time the sequence is converted; the value of the result register is updated once and compared once. The mapping relationship between the result register and the analog input channel can be freely programmed to form a conversion sequence, and one certain analog input channel can be repeatedly programmed in the sequence to obtain results successive conversions of this analog input channel in the result register. With a unique single resistance sampling mode, different hardware sources can trigger different starting channels and the number of channels. It has single transformation mode, discontinuous transformation mode and continuous transformation mode. When the succcessive conversion function is started, the sequence automatically periodically starts the conversion, and the result register is continuously updated, and each updated value is compared with the limit value. For a single channel, the conversion rate can be up to 2MSPS, the ADC clock frequency can be set by the register TADC[3:0]@ADCON2, and TS[3:0]@ADCON2 sets the first sample time of each channel of the ADC. The time interval between adjacent channels in the sequence (which can also be used as the second sample time for each channel) can be set by the registers TGAP[2:0]@ADCON2 and GAPENx@ADGAPON.

ADC_CLK TADC@ADCON2 ADC_Clk MUX MUX ADDR0 ADDR15 ADDRn Software Trigger EOCSOC SOC EOC AN0 EXVREF REFC@ADCON1 AVDD Refc AN9 OP0OUT OP1OUT 12-Bits ADC MUX Mode Arbiter REG MUX Pre-Counter for ADC clock,4-bit SOC Stands for Start of Convertion EOC Stands for End of Convertion Compare Logic ADDGTADDLT 12 12 ADGIF ADLIF Time Gap Logic MUX ADDR0 ... ADDR7 ... sequence mode SEQCH0 Event Trigger SEQCHn Channel pointer + SEQCH15 OP2OUT MUX AN10 ADPCH OP3OUT Vbg Figure20-1 ADC Module Diagram

20.2 Features

 A built-in successive approximation 12-bit A/D converter.  The selection of reference voltage can be external VREF or VDD, and the external VREF can output to other modules, such as OP and comparator.  11 analog input ports, 4 OP output ports, one built-in reference voltage, and a total of 16 ADC analog input channels.  Starting the ADC once can automatically complete multi-channel conversion (sequence), and each channel can be configured as any channel of the multiple channel analog inputs.  The sequence can be configured as single or multi-channel, and a sequence can contain up to 16 channels. The conversion result is stored in 16 result registers.  There are four conversion methods: sequence conversion mode, intermittent conversion mode, successive conversion mode and single resistance conversion mode.  The time interval between adjacent channel conversions during sequence conversion can be set by software  AD conversion can be automatically started by trigger signals from MCM module, two PCAs, one normal timer (TIM8) and one external pins  Single channel conversion rate is up to 2MSPS.  Four conversion methods are all with comparison function.

20.3 Function Description

20.3.1 Single Conversion Method

When ADCTU[1:0] = 00b, the ADC is configured to single-sequence conversion method, converting one sequence at a time. A sequence consists of a single channel or multiple channels. Converting a sequence means converting the channels in the sequence one by one. In hardware, it can be achieved by making multiple signals convert at the same time point (the shortest sampling interval between 2 channels is 0.5us, which can be approximated as simultaneous). The result of the conversion is stored in the corresponding result registers. At the same time as the sequence conversion is completed, the value of a specified result register is compared with the values of ADDGT and ADDLT, and the result of the comparison is indicated by a flag. In the single sequence conversion mode, after ADSOC is set to 1, coversion starts from channel 0. After each single-channel conversion is completed, the ADPCH register is automatically incremented by one, and then the conversion of the next channel is performed. When the number of single-sequence conversion channels reaches the setting value (ADMAXCH[3:0]), the current sequence conversion ends and the ADSOC bit is cleared, indicating that the sequence conversion is completed and the ADPCH register is automatically reset to 0. At the same time, the ADIF bit in ADINTF is set by hardware. At this time, if the ADCIE bit in ADCON1 is '1' (note: the ADC interrupt is not masked), the sequence conversion completion interrupt will be triggered and the ADIF flag needs to be cleared by software. Example: There are 4 channels that need to be converted, sorted by priority to AN0, AN2, AN4, AN7, then set to ADMAXCH[2:0] = 3, SEQCH0 = 0, SEQCH1 = 2, SEQCH2 = 4, SEQCH3 = 7. Then each time AD conversion (ADSOC=1) is started, then the 4 channels starting from channel 0 will be sequentially converted, and the result will be stored in ADDR0, ADDR1, ADDR2, ADDR3 sequentially. CASE1: 1 2 3ADPCH AN0 AN2 AN4 AN7 ADC_CLK ADSOC Channel Select for A/D Converter ADIF cleared by software ADMAXCH=3, SEQCH0=0, SEQCH1=2, SEQCH2=4, SEQCH3=7, ... , SEQCH7=3 Figure20-2 Single Conversion Method Waveform Example Diagram

20.3.2 Intermittent Conversion Method

When ADCTU[1:0] = 01b, the ADC operates in the intermittent conversion method. The ADC directly converts from the channel specified by the ADPCH register. When the number of conversions reaches the (ADMAXCH[3:0]) setting, this sequence conversion ends. The maximum ADC sampling channel number is 15, so when the conversion channel pointer register ADPCH exceeds 15, it will automatically return to 0. After a sequence conversion is completed, if the ADPCH software is rewritten to n at this time, the next conversion starts from channel n. If the ADPCH is not rewritten, the next conversion channel starts from the ADPCH value at the end of the last sampling. The ending of hardware sampling ends will not clear the value of ADPCH, so the program rewriting of the ADPCH register needs to be treated carefully (during ADC conversion period (ADSOC =1), ADPCH cannot be modified). For example, SEQCH0=2, SEQCH1=4, SEQCH2=7, SEQCH3=3, SEQCH4=5, SEQCH5=6, SEQCH14=1, SEQCH15=0, when ADMAXCH=3, if the current ADPCH=14, in the intermittent conversion mode, SEQCH14, SEQCH15, SEQCH0 and SEQCH1 will select registers for valid channels, the channel sequence thus formed is AN1, AN0, AN2 and AN4, and the sampling results will be sequentially stored in ADDR14, ADDR15, ADDR0, ADDR1. After the conversion, the ADPCH value should be 2, and when AD conversion is started again, AN7, AN3, AN5 and AN6 will be sequentially converted, and the result will be stored in ADDR2, ADDR3, ADDR4, ADDR5 sequentially. The ADPCH value should be 6 after the conversion, and so on. In this example, the time order relationship of each key signal is shown in Figure 20-3: CASE1: ADPCH ADC_CLK ADSOC Channel Select for A/D Converter ADIF cleared by software ADMAXCH1=3, SEQCH0=2，SEQCH1=4，SEQCH2=7，SEQCH3=3，SEQCH4=5，SEQCH5=6，SEQCH14=1， SEQCH15=0 14 15 0 1 AN0 AN2 AN4 AN7 3 6 cleared by software 2 54 AN1 AN3 AN5 AN6 Figure20-3 Waveform Example Diagram in Single Sequence Sequential Sampling Mode and with Intermittent Conversion Method Note 1: ADPCH can only be written by software when the ADC is not sampling (ADSOC is equal to 0), and can only be written by software in intermittent mode. Note 2: ADPCH is modified when each channel conversion is completed and the sampling result is sent out, which means the ADPCH modification moment coincides with the moment when the ADC result is sent out.

20.3.3 Continuous Conversion Method

When ADCTU[1:0] = 10b, ADC selects the continuous conversion method. After converting one sequence, the next conversion of this sequence is performed, and this sequence conversion keeps cycling. For some register settings for continuous conversion, see "Single Conversion Method". Each time the sequence conversion is completed, the value of a specified result register is compared with the values of ADDGT and ADDLT, and the result of the comparison is indicated by a flag. When the ADSOC bit is cleared by software, the conversion of AD are stopped immediately. For example, SEQCH0=2, SEQCH1=5, SEQCH2=0, SEQCH3=4,...,SEQCH6=1, SEQCH7=6, when ADMAXCH=3, SEQCH0, SEQCH1, SEQCH2 and SEQCH3 are valid channels select registers after the start of the conversion, the channel sequence thus formed is AN2, AN5, AN0, AN4. In this example, the time order relationship of each key signal is shown in Figure 20-4: Note: The value of ADPCH is cleared at the end of sampling.

CASE1: 1 2 3ADPCH AN2 AN5 AN0 AIN2AN4 ADC_CLK ADSOC Channel Select for A/D Converter ADIF cleared by software ADMAXCH=3, SEQCH0=2, SEQCH1=5, SEQCH2=0, SEQCH3=4, ... , SEQCH6=1, SEQCH7=6 AN2 AN5 AN0 AN4 0 1 2 3 cleared by software AN2 AN5 cleared by software Figure20-4 Continuous Conversion Method Waveform Example Diagram

20.3.4 Single resistance conversion mode

When ADCTU[1:0] = 11b, the ADC operates in the single resistance conversion mode. When the hardware trig gers the ADC, the conversion starts directly from the specified channel of the HARDCHSEL register corresponding to the hardware trigger source. When the number of conversions reaches the HARDCHLH set value, the sequence conversion ends. When the software triggers the ADC, the ADC is converted directly from the channel specified by the ADPCH register. When the number of conversions reaches the (ADMAXCH[3:0]) setting, this sequence conversion ends. The maximum ADC sampling channel number is 15, so when the conversion channel pointer register ADPCH exceeds 15, it will automatically return to 0. The ending of hardware sampling ends will not clear the value of ADPCH, so the program rewriting of the ADPCH register needs to be treated carefully (during ADC conversion period (ADSOC =1), ADPCH cannot be modified). For example, SEQCH7=3，SEQCH8=5，SEQCH9=6，SEQCH14=1，SEQCH15=0， PWMCMP1@HARDCHLH=1， PWMCMP2@HARDCHLH=2，PWMCMP1@HARDCHSEL=14，PWMCMP2@HARDCHSEL =7. In the single resistance conversion mode, When PWMCMP1 of MCM triggers ADC, SEQCH14 and SEQCH15 are selected, the channel sequence thus formed is AN1, AN0, and the sampling results will be sequentially stored in ADDR14, ADDR15. When PWMCMP2 of MCM triggers ADC, SEQCH7, SEQCH8, and SEQCH9 are valid channel selection registers, and the channel sequences AN3, AN5, and AN6 formed therefrom wi ll be converted successively, and the results will be stored in ADDR7, ADDR8, and ADDR9 successively, and so on.In this example, the time order relationship of each key signal is shown in Figure 20-5: CASE1: ADPCH ADC_CLK ADSOC Channel Select for A/D Converter ADIF cleared by software SEQCH7=3，SEQCH8=5，SEQCH9=6，SEQCH14=1，SEQCH15=0 AN0 cleared by software AN1 AN3 AN5 AN6 TRIGGER PWMCMP1 PWMCMP2 15 14 PWMCMP1 AN0AN1 cleared by software Figure20-5 Single Resistance Conversion Mode Waveform Diagram

20.3.5 Other Function Description

20.3.5.1 Channel Selection Settings in Sequence Conversion

A sequence can contain single or multiple channels, the numbers of channels to be converted are stored in the channel register SEQCHx (x = 0 - 15), and the register SEQCHx has 16 groups, so up to 16 channels can be converted at a time during sequence conversion. The number of channels per conversion is determined by the value of ADMAXCH[3:0] in the ADCON2 register. Example: ADMAXCH[3:0] = 0, which means single channel conversion, converting the channel stored in SEQCH0; ADMAXCH[3:0] = 3, then there are 4 channels in the sequence, and the channels stored in SEQCH0 to SEQCH3 are converted sequentially. The channel number to be converted is stored in the channel register SEQCHx (x = 0 - 15). Example: There are 3 channels to be converted, sorted by priority to OP1OUT, AN2, AN7, then set to ADMAXCH[3:0] = 2, SEQCH0 = 12, SEQCH1 = 2, SEQCH2 = 7, they will be converted sequentially. Note 1: For the analog channel IO which needs to be converted, its multiplexing must be configured as analog function (GPIOx_CFG_AFRH/L is set to AF7). The same channel number can also be set in SEQCHx. For example, the values in SEQCHx are all set to AN3, and the result register will store the converted values of AN3 in different time periods. Note 2: SEQCHx is not allowed to be modified during ADC sampling (ADSOC = 1).

20.3.5.2 Gap Time Setting during Sequence Conversion

During sequence conversion, the time between the converting moment of the previous channel and the starting sampling moment of the next channel can be set by the registers TGAP[2:0]@ADCON2 and GAPENx@ADGAPON bit segment. When TGAP[2:0] = 0 or GAPENx=0, the sampling of the next channel starts immediately after the conversion of one channel, and there is no waiting time between them. Gap time of each channel can be set separately, so gap time can also be used as the sampling time for each channel. The gap time of all channels can only be set to one value, but each channel can be individually set to enable or disable gap time. Note: Gap Time can also be set for the first channel, which can also be used as sampling Time.

20.3.5.3 Start-up and Stop of Sequence Conversion Mode

By setting the ADON bit in ADCON1 to 1, the clock ADC_CLK of ADC module can be enabled. Also setting the ADON bit to 1 can power up the analog circuitry in the ADC module. The start-up of the sequence conversion mode can be divided into software start-up and hardware start-up. Software start-up: When the ADSOC bit in the ADCON1 register is set to 1, conversion is started. When a sequence conversion is completed, the ADSOC is cleared by hardware and compared at the same time (explained in 20.3.6). When reading ADSOC and getting 1, the flag conversion is not completed. If the ADSOC bit is cleared during the conversion process, the conversion is terminated. Hartdware start-up: External pin raising edge start-up, MCM module trigger start-up, PCA module trigger start-up and normal timer (TIM8) module trigger start-up are four types of hardware start-up. There types are selected by setting the ADTGREN@ADCON1 bits, CMPx@MCM_PWMCON2, ADTSEL @ PCAx_CFGR, and TRIGEN@TIM8_CR.When external pin raising edge triggers ADC, there is a filter of 2 PCLK. The hardware trigger signal takes precedence over the software trigger signal. When the software is already in sequence conversion, the hardware trigger terminates the previous sequence conversion and restarts a sequence conversion, whose conversion value will overwrite the previous result. Note 1: After setting the ADON bit in ADCON1, it is needed to wait for 10us before starting sampling. Note 2: In the case of any hardware trigger single sequence, intermittent conversion and continuous conversion, once another hardware trigger occurs, the previous conversion is terminated and a new conversion is restarted.

20.3.5.4 Sequence Conversion Completion Interrupt

After the sequence conversion is completed, ADIF@ADINTF will be set by hardware. If the corresponding ADIE@ADCON1 is 1, the sequence conversion completion interrupt will be triggered. The ADIF@ADINTF bit can only be cleared by software by setting ADIFC@ADINTF to 1.

20.3.6 Compare Function

20.3.6.1 Specifying of Result Registers Used for Comparison

The result register being compared is specified by the register CSEL[2:0]@ADCMPCON. If CSEL[2:0] = n, the result register ADDRn will be compared with the values of ADDGT and ADDLT. If CSEL[2:0] = 2 is set, the value of ADDR2 is compared with the values of ADDGT and ADDLT each time the sequence conversion is completed. It should be noted that if a result register that is not used by a sequence conversion is specified, no comparison action will occur. In the above example, CSEL[2:0] = 3, the result register ADDR3 is not used after conversion, so no compare action occurs, and the values of the flag bits ADGIF and ADLIF do not change. Note: When writing the comparison values ADDGT and ADDLT, it should be noted that storage method of the result register is left-aligned or right -aligned, and the data write format should be consistent with the storage format of the result register. The ADDGT and ADDLT write values take effect immediately, and the last updated value of ADDGT and ADDLT is used for comparison.

20.3.6.2 Compare Process

Let set CSEL[2:0] = n, ADDGT = Max, ADDLT = Min, when the sequence conversion is completed, immediately compare the value of the specified result register ADDRn with Max and Min. If ADDRn >= Max, the ADGIF bit in the ADCMPCON register will be set to 1. If the ADGIE bit is 1, a compare interrupt can be triggered (sharing an interrupt vector with the sequence conversion completion). The ADGIF bit will remain at 1 until the software clears it. If ADDRn <= Min, the ADLIF bit in the ADCMPCON register will be set to 1. If the ADLIE bit is 1, a compare interrupt can also be triggered (sharing an interrupt vector with the sequence conversion completion), and the ADLIF bit will remain at 1 until the software clears it. Let set ADDGT = 0x3DF, ADDLT = 0x8FE, CSEL[2:0] = n, then the relationship between the value of ADDRn and the median values of ADGIF and ADLIF bits is shown in the left half of Figure 20-6; set ADDGT = 0x8FE, ADDLT = 0x3DF, CSEL = n, then the relationship between the value of ADDRn and the median values of ADGIF and ADLIF bits is shown in the right half of Figure 20-6. ADDGT 0x3DF 0x8FE 0x000 0xFFF ADRRn ADDLT ADGIF = 1 ADLIF = 1 ADLIF = 1 ADGIF not affected ADGIF = 1 ADLIF not affected ADDLT 0x3DF 0x8FE 0x000 0xFFF ADRRn ADDGT ADGIF not affected ADLIF not affected ADLIF = 1 ADGIF not affected ADGIF = 1 ADLIF not affected Figure20-6 Compare Process Diagram

20.3.6.3 Compare Interrupt

Each time the sequence conversion is completed, the value of the specified result register is compared. If it exceeds the limit, a compare interrupt can be generated. Since the comparison and sequence conversion are completed at the same time, the generation of the interrupt is also simultaneous.

20.3.7 ADC Conversion Time Setting

The ADC clock and sampling time can be set via the ADCON2 register. The ADC clock is set via TADC[3:0]@ADCON2. The sampling time tSAMP for each channel is set via register TS[3:0]@ADCON2, TGAP[2:0]@ADCON2 and GAPENx@ADGAPON, tSAMP = (TS[3:0]+ TGAP[2:0]* GAPEN +1) * tAD, see the ADC Register part for details. For 12BIT mode AD conversion, the AD conversion time per channel is fixed at 15 * tAD. Therefore the total conversion time per channel = tSAMP + 15 * tAD. The ADC clock can be set to 40MHz at the fastest.

20.3.8 ADC Module Reference Voltage Setting

The input voltage on chip VDD or VREF pin can be selected as the reference voltage for the ADC module. After the chip is reset, the reference voltage of the ADC module is the VDD of the chip. Setting the REFC[1:0] bit in the ADCON1 register to 1 will cause the ADC module to use the voltage on the VREF pin as reference voltage.

20.3.9 ADC Channel and IO Port Function Setting

The ADC input I/O port is set to analog port. For details, please refer to the “GPIO” part.

20.3.10 Requirements for Sensor Output Resistance during AD Conversion

As shown in Figure 20-7, in order to ensure that the AD conversion can convert and get accurate AD results under certain conversion rate, it is necessary to charge the SH33F2801 internal sampling capacitor within a certain period of time (sampling time Tsamp). If the sampling capacitor fails to be fully charged within the specified sampling time, which means V0 < V1, the AD conversion result will produce accuracy error. Because R0 (SH33F2801 internal resistance) and C (internal sampling capacitor) are constant, which has been determined by the chip. Whether the AD result within the allowable accuracy range can be obtained from the conversion depends on the internal equivalent resistance Rx of the sensor. Let the resolution of the AD conversion result be M (the resolution of the 12-bit result is 4096). If the accuracy requirement of the AD conversion is N, the selection of the sensor resistance has the following requirements: sensor circuit Rx AN0 Sample circuit Figure20-7 Output Resistance 12- 100.8 01*105 ×−−× V VVLn TRx The above formula can also be expressed as: 12- 100.8 M N*105 Ln TRx For 12bit mode, i.e. 4096 resolution, if the ADC clock is 40M, TS is set to 0xF, Tgap is off, then the sampling time is 16*Tadc, which is 0.4us. When the theoretical precision error is controlled within 0.1LSB, substitute according to the above formula and get:

0.4 10 0.8 10 6.730.15 10 4096 Rx K Ln This means, to meet the accuracy error within 0.1LSB, the internal equivalent resistance of the sensor selection should be less than 6.73KΩ. Note: Under the above configuration, it doesn’t mean a signal source greater than 6.73 KΩ resistance cannot be used, but the theoretical accuracy error will exceed 0.1LSB. Theoretically, the bigger the resistance is, the greater the accuracy error. Specifically, it can be calculated according to the above formula. By reducing the sampling rate, the theoretical equivalent resistance upper limit is correspondingly increased.

20.3.11 Usage Notes

For ADC conversion, it is better to turn on ADON@ADCON1 for 10us and then set ADSOC@ADCON1 to 1 to perform the conversion. Because the ADC module has stabilizing time after it is turned on. If ADSOC is set, the registers like ADCON2、ADPCH、SEQCHSEL0/1、ADGAPON, etc., cannot be changed. The operations of the registers are invalid. If converting the gain amplification path is required, the OP function needs to be turned on first. The OP requires establish time (about 100us) to stabilize the output stability, and then performs AD conversion. The OPOUT0, OPOUT1, OPOUT2 and OPOUT3 paths are selected during the conversion. When converting an analog channel, the port must be set to the AD channel function first in order to convert smoothly. When ADIE, ADLIE, and ADGIE are both turned on, any one setting of ADIF, ADLIF, or ADGIF can cause an interrupt, and they share an interrupt vector. Determine specific interrupt source by discriminating which one of ADIF, ADLIF, and ADGIF is 1 and customize specific operations. Note 1: During single and intermittent conversion, which means when ADSOC is 1, writing to all ADC registers except for ADCON1.ADON, ADCON2, ADDGT, and ADDLT will be regarded as invalid. Note 2: During continuous conversion, which means when ADSOC is 1, writing to all ADC registers except for ADCON1.ADON, ADCON2, ADCMPCON, ADDGT, and ADDLT will be regarded as invalid.

20.4 Register

ADC Module Register List (Base address:0x4000 3C00) Address Regester Name Description 0x4000 3C00 ADCON1 ADC control register 1 0x4000 3C04 ADCON2 ADC control register 2 0x4000 3C08 ADPCH ADC sampling conversion channel pointer register 0x4000 3C0C ADDR0 ADC result register 0 0x4000 3C10 ADDR1 ADC result register 1 0x4000 3C14 ADDR2 ADC result register 2 0x4000 3C18 ADDR3 ADC result register 3 0x4000 3C1C ADDR4 ADC result register 4 0x4000 3C20 ADDR5 ADC result register 5 0x4000 3C24 ADDR6 ADC result register 6 0x4000 3C28 ADDR7 ADC result register 7 0x4000 3C2C ADDR8 ADC result register 8 0x4000 3C30 ADDR9 ADC result register 9 0x4000 3C34 ADDR10 ADC result register 10 0x4000 3C38 ADDR11 ADC result register 11 0x4000 3C3C ADDR12 ADC result register12 0x4000 3C40 ADDR13 ADC result register13 0x4000 3C44 ADDR14 ADC result register14 0x4000 3C48 ADDR15 ADC result register15 0x4000 3C4C ADCMPCON ADC compare control register 0x4000 3C50 ADDGT ADC upper limit compare register 0x4000 3C54 ADDLT ADC lower limit compare register 0x4000 3C58 SEQCHSEL0 ADC channel select register0 0x4000 3C5C SEQCHSEL1 ADC channel select register1 0x4000 3C60 HARDCHSEL The ADC's start channel selection of hardware triggering register(Single resistance mode) 0x4000 3C64 HARDCHLH The ADC's channel length of hardware triggering register(Single resistance mode) 0x4000 3C68 ADGAPON ADC channel GAP control register 0x4000 3C6C ADINTF ADC interrupt flag and clear register

20.4.1 ADC Control Register1 (ADC_ADCON1)

Offset Address: 0x0000 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Reserved ADO UT ADO N ADIE ADT GRE N REF C Rese rved ADCTU[1:0] ADS OC - RW RW RW RW RW - RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 9 Reserved -

8 ADOUT ADC Convertion Output Control:

0: Prohibit the output of ADSOC state through ADTRG pin 1: Enable the output of ADSOC state through ADTRG pin

7 ADON ADC enable bit

0: ADCx module is disabled 1: ADCx module is enabled

6 ADIE Channel sequence conversion end interrupt enable bit

0: ADC conversion end interrupt is disabled 1: ADC conversion end interrupt is enabled

5 ADTGREN The enable bit of external pin triggering the ADC

0: Disable 1: Enable

4 REFC Reference voltage selection

0: Selects VDD as reference voltage 1: Selects external VREF port input as reference voltage 2 ~ 1 ADCTU[1:0] Conversion method control bit of ADC channel sequence 00: Single sequence conversion method 01: Intermittent sequence conversion method 10: Continuous conversion method 11: Single resistance conversion mode(When the hardware trigger ADC ,the start channel is selected by HARDCHSEL, the number of sampling channels is set by HARDCHLH)。In this mode, ADPCH changes with the change of sampling channel. The ADC mode triggered by software is discontinuous sequence conversion mode. Note: Modifying this control bit will not take effect until the next time the AD conversion process is started.

0 ADSOC ADC channel sequence start-up AD conversion request bit

0: Sequence conversion/continuous conversion is not done or has been completed. Writing 0 cancels the conversion that is currently in progress. 1: In the single and intermittent conversion modes, the sequence conversion starts when this is set to 1 and remains at 1 during the conversion process. This is automatically cleared by hardware after the conversion is completed (if cleared during conversion, this bit will immediately terminate the sequence conversion.) In continuous conversion mode, set 1 to start continuous conversion, then this bit will not be cleared by hardware, and can be cleared and terminated immediately by software.

20.4.2 ADCControl Register2 (ADC_ADCON2)

Offset Address: 0x0004 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Rese rved TGAP [2:0] TS [3:0] ADMAXCH[3:0] TADC[3:0] - RW RW RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 15 Reserved - 14 ~ 12 TGAP [2:0] Time interval between adjacent channels while in sequence setting bit segment In a sequence conversion, the time interval between the completion of one channel conversion and the start of sampling of the next channel 000: no wait time 001: 2ADC clock period 010: 4ADC clock period 011: 8ADC clock period 100: 16ADC clock period 101: 32ADC clock period 110: 64ADC clock period 111: 128ADC clock period 11 ~ 8 TS [3:0] Sampling time setting 1 tAD ≤ (TS [3:0]+1) * tAD ≤ 16 tAD Note 1: The total sampling time of a channel consists of two parts: TS + TGAP, the TS part is set here; Note 2: Total sampling time range: 1 tAD ≤ ((TS[3:0])+1+TGAP[2:0]*GAPEN)* tAD ≤ 144 tAD, where whether to enable TGAP is controlled by GAPEN; Note 3: Before setting TS[3:0], the series resistance connected to the ADC input pin needs to be estimated to achieve the best sampling accuracy. When selecting 1 * tAD as the sampling time, make sure that the series resistance connected to the ADC input pin meets the input resistance requirements, see 20.3.10 for details; Note 4: The TADC setting needs to guarantee the ADC clock period Tadc ≥ 25ns Note 5: Total sampling conversion time of one channel in 12-bit mode = 15tAD + sampling time 7 ~ 4 ADMAXCH[3:0] Total length setting bit of ADC channel sequence (set value 0~15) The total number of analog channels for one AD conversion process is ADMAXCH+1

3 ~ 0 TADC[3:0] ADC clock period selection 0000: ADCclock period tAD = 1 tPCLK 0001: ADC clock period tAD = 2 tPCLK 0010: ADC clock period tAD = 3 tPCLK 0011: ADC clock period tAD = 4 tPCLK 0100: ADC clock period tAD = 5 tPCLK 0101: ADC clock period tAD = 6 tPCLK 0110: ADC clock period tAD = 8 tPCLK 0111: ADC clock period tAD = 12 tPCLK 1000: ADC clock period tAD = 16 tPCLK 1001: ADC clock period tAD = 24 tPCLK 1010: ADC clock period tAD = 32 tPCLK 1011: ADC clock period tAD = 48 tPCLK 1100: ADC clock period tAD = 64 tPCLK 1101: ADC clock period tAD = 128 tPCLK 1110: ADC clock period tAD = 256 tPCLK 1111: ADC clock period tAD = 320 tPCLK Note: tPCLK is the clock period of PCLK.

20.4.3 ADC Sampling Conversion Channel Pointer Register (ADC_ADPCH)

Offset Address: 0x0008 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Reserved ADPCH[3:0] - RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 4 Reserved - 3 ~ 0 ADPCH[3:0] ADC sampling conversion channel pointer register ADC current sampling channel is SEQCHn(n=ADPCH[3:0]) Note: ADPCH can only be written by software when ADC is not sampling (ADSOC=0) and ADCTU@ADCON1=1.

20.4.4 ADC Result Register 0 (ADC_ADDRn)(n=0..15) Offset Address: 0x000C :0x0010 :0x0014 :0x0018 :0x001C :0x0020 :0x0024 :0x0028 :0x002C :0x0030 :0x0034 :0x0038 :0x003C :0x0040 :0x0044 :0x0048 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Reserved ADDRn[11:0] - RO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 12 Reserved - 11 ~ 0 ADDRn[11:0] After conversion of a channel is completed, the data is immediately updated and stored in ADDRn (n = 0~15). With one sequence conversion, all result registers are also updated once.

20.4.5 ADC Compare Control Register (ADC_ADCMPCON)

Offset Address: 0x004C Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Reserved ADG IE Rese rved ADLI E Rese rved CSEL[3:0] - RW - RW - RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 8 Reserved -

7 ADGIE Upper limit compare interrupt enable bit

0: Upper limit compare interrupt is disabled 1: Upper limit compare interrupt is enabled

5 ADLIE Lower limit compare interrupt enable bit

0: Lower limit compare interrupt is disabled 1: Lower limit compare interrupt is enabled

3 ~ 0 CSEL[3:0] Result register used for comparison selection bit segment Selects the value in ADDRn to compare with ADDGT, ADDLT

20.4.6 ADC Upper Limit Compare Register (ADC_ADDGT)

Offset Address: 0x0050 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 GT[15:0] RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 16 Reserved - 15 ~ 0 GT[15:0] ADC upper limit compare register When a sequence conversion is completed, the value of the result register specified by CSEL bit segment in the ADCMPCON register is immediately compared with the value in ADDGT. If it is greater than or equal to the value in ADDGT, the ADGIF bit in ADCMPCON is set to 1, and the ADGIF bit will remain at 1 until it is cleared by software.

20.4.7 ADC Lower Limit Compare Register (ADC_ADDLT)

Offset Address: 0x0054 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 LT[15:0] RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 16 Reserved - 15 ~ 0 LT[15:0] ADC lower limit compare register When a sequence conversion is completed, the value of the result register specified by CSEL bit segment in the ADCMPCON register is immediately compared with the value in ADDLT. If it is smaller than or equal to the value in ADDLT, the ADLIFbit in ADCMPCON is set to 1, and the ADLIF bit will remain at 1 until it is cleared by software.

20.4.8 ADC Channel Select Register 0 (ADC_SEQCHSEL0)

Offset Address: 0x0058 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 SEQCH7[3:0] SEQCH6[3:0] SEQCH5[3:0] SEQCH4[3:0] RW RW RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 SEQCH3[3:0] SEQCH2[3:0] SEQCH1[3:0] SEQCH0[3:0] RW RW RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 28 SEQCH7[3:0] Analog channel 7 select register group, specifying the corresponding analog input channel: 0000 - AN0 0001 - AN1 0010 - AN2 0011 - AN3 0100 - AN4 0101 - AN5 0110 - AN6 0111 - AN7 1000 - AN8 1001 - AN9 1010 - AN10 1011 - OP0OUT/AN11 1100 - OP1OUT/AN12 1101 - OP2OUT/AN13 1110 - OP3OUT/AN14 1111 - Vbg 27 ~ 24 SEQCH6[3:0] Analog channel 6 select register group, specifying the corresponding analog input channel: 0000 - AN0 0001 - AN1 0010 - AN2 0011 - AN3 0100 - AN4 0101 - AN5 0110 - AN6 0111 - AN7 1000 - AN8 1001 - AN9 1010 - AN10 1011 - OP0OUT/AN11 1100 - OP1OUT/AN12 1101 - OP2OUT/AN13 1110 - OP3OUT/AN14 1111 - Vbg

23 ~ 20 SEQCH5[3:0] Analog channel 5 select register group, specifying the corresponding analog input channel: 0000 - AN0 0001 - AN1 0010 - AN2 0011 - AN3 0100 - AN4 0101 - AN5 0110 - AN6 0111 - AN7 1000 - AN8 1001 - AN9 1010 - AN10 1011 - OP0OUT/AN11 1100 - OP1OUT/AN12 1101 - OP2OUT/AN13 1110 - OP3OUT/AN14 1111 - Vbg 19 ~ 16 SEQCH4[3:0] Analog channel 4 select register group, specifying the corresponding analog input channel: 0000 - AN0 0001 - AN1 0010 - AN2 0011 - AN3 0100 - AN4 0101 - AN5 0110 - AN6 0111 - AN7 1000 - AN8 1001 - AN9 1010 - AN10 1011 - OP0OUT/AN11 1100 - OP1OUT/AN12 1101 - OP2OUT/AN13 1110 - OP3OUT/AN14 1111 - Vbg 15 ~ 12 SEQCH3[3:0] Analog channel 3 select register group, specifying the corresponding analog input channel: 0000 - AN0 0001 - AN1 0010 - AN2 0011 - AN3 0100 - AN4 0101 - AN5 0110 - AN6 0111 - AN7 1000 - AN8 1001 - AN9 1010 - AN10 1011 - OP0OUT/AN11 1100 - OP1OUT/AN12 1101 - OP2OUT/AN13 1110 - OP3OUT/AN14 1111 - Vbg

11 ~ 8 SEQCH2[3:0] Analog channel 2 select register group, specifying the corresponding analog input channel: 0000 - AN0 0001 - AN1 0010 - AN2 0011 - AN3 0100 - AN4 0101 - AN5 0110 - AN6 0111 - AN7 1000 - AN8 1001 - AN9 1010 - AN10 1011 - OP0OUT/AN11 1100 - OP1OUT/AN12 1101 - OP2OUT/AN13 1110 - OP3OUT/AN14 1111 - Vbg 7 ~ 4 SEQCH1[3:0] Analog channel 1 select register group, specifying the corresponding analog input channel: 0000 - AN0 0001 - AN1 0010 - AN2 0011 - AN3 0100 - AN4 0101 - AN5 0110 - AN6 0111 - AN7 1000 - AN8 1001 - AN9 1010 - AN10 1011 - OP0OUT/AN11 1100 - OP1OUT/AN12 1101 - OP2OUT/AN13 1110 - OP3OUT/AN14 1111 - Vbg 3 ~ 0 SEQCH0[3:0] Analog channel 0 select register group, specifying the corresponding analog input channel: 0000 - AN0 0001 - AN1 0010 - AN2 0011 - AN3 0100 - AN4 0101 - AN5 0110 - AN6 0111 - AN7 1000 - AN8 1001 - AN9 1010 - AN10 1011 - OP0OUT/AN11 1100 - OP1OUT/AN12 1101 - OP2OUT/AN13 1110 - OP3OUT/AN14 1111 - Vbg

20.4.9 ADC Channel Select Register 1 (ADC_SEQCHSEL1)

Offset Address: 0x005C Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 SEQCH15[3:0] SEQCH14[3:0] SEQCH13[3:0] SEQCH12[3:0] RW RW RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 SEQCH11[3:0] SEQCH10[3:0] SEQCH9[3:0] SEQCH8[3:0] RW RW RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 28 SEQCH15[3:0] Analog channel 15 select register group, specifying the corresponding analog input channel: 0000 - AN0 0001 - AN1 0010 - AN2 0011 - AN3 0100 - AN4 0101 - AN5 0110 - AN6 0111 - AN7 1000 - AN8 1001 - AN9 1010 - AN10 1011 - OP0OUT/AN11 1100 - OP1OUT/AN12 1101 - OP2OUT/AN13 1110 - OP3OUT/AN14 1111 - Vbg 27 ~ 24 SEQCH14[3:0] Analog channel 14 select register group, specifying the corresponding analog input channel: 0000 - AN0 0001 - AN1 0010 - AN2 0011 - AN3 0100 - AN4 0101 - AN5 0110 - AN6 0111 - AN7 1000 - AN8 1001 - AN9 1010 - AN10 1011 - OP0OUT/AN11 1100 - OP1OUT/AN12 1101 - OP2OUT/AN13 1110 - OP3OUT/AN14 1111 - Vbg

23 ~ 20 SEQCH13[3:0] Analog channel 13 select register group, specifying the corresponding analog input channel: 0000 - AN0 0001 - AN1 0010 - AN2 0011 - AN3 0100 - AN4 0101 - AN5 0110 - AN6 0111 - AN7 1000 - AN8 1001 - AN9 1010 - AN10 1011 - OP0OUT/AN11 1100 - OP1OUT/AN12 1101 - OP2OUT/AN13 1110 - OP3OUT/AN14 1111 - Vbg 19 ~ 16 SEQCH12[3:0] Analog channel 12 select register group, specifying the corresponding analog input channel: 0000 - AN0 0001 - AN1 0010 - AN2 0011 - AN3 0100 - AN4 0101 - AN5 0110 - AN6 0111 - AN7 1000 - AN8 1001 - AN9 1010 - AN10 1011 - OP0OUT/AN11 1100 - OP1OUT/AN12 1101 - OP2OUT/AN13 1110 - OP3OUT/AN14 1111 - Vbg 15 ~ 12 SEQCH11[3:0] Analog channel 11 select register group, specifying the corresponding analog input channel: 0000 - AN0 0001 - AN1 0010 - AN2 0011 - AN3 0100 - AN4 0101 - AN5 0110 - AN6 0111 - AN7 1000 - AN8 1001 - AN9 1010 - AN10 1011 - OP0OUT/AN11 1100 - OP1OUT/AN12 1101 - OP2OUT/AN13 1110 - OP3OUT/AN14 1111 - Vbg

11 ~ 8 SEQCH10[3:0] Analog channel 10 select register group, specifying the corresponding analog input channel: 0000 - AN0 0001 - AN1 0010 - AN2 0011 - AN3 0100 - AN4 0101 - AN5 0110 - AN6 0111 - AN7 1000 - AN8 1001 - AN9 1010 - AN10 1011 - OP0OUT/AN11 1100 - OP1OUT/AN12 1101 - OP2OUT/AN13 1110 - OP3OUT/AN14 1111 - Vbg 7 ~ 4 SEQCH9[3:0] Analog channel 9 select register group, specifying the corresponding analog input channel: 0000 - AN0 0001 - AN1 0010 - AN2 0011 - AN3 0100 - AN4 0101 - AN5 0110 - AN6 0111 - AN7 1000 - AN8 1001 - AN9 1010 - AN10 1011 - OP0OUT/AN11 1100 - OP1OUT/AN12 1101 - OP2OUT/AN13 1110 - OP3OUT/AN14 1111 - Vbg 3 ~ 0 SEQCH8[3:0] Analog channel 8 select register group, specifying the corresponding analog input channel: 0000 - AN0 0001 - AN1 0010 - AN2 0011 - AN3 0100 - AN4 0101 - AN5 0110 - AN6 0111 - AN7 1000 - AN8 1001 - AN9 1010 - AN10 1011 - OP0OUT/AN11 1100 - OP1OUT/AN12 1101 - OP2OUT/AN13 1110 - OP3OUT/AN14 1111 - Vbg

20.4.10 The ADC's start channel selection of hardware triggering register (Single resistance mode)

(ADC_HARDCHSEL) Offset Address: 0x0060 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 ADTRG[3:0] TIM8SEL[3:0] PCA1SEL[3:0] PCA0SEL[3:0] RW RW RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 PWMCMP4[3:0] PWMCMP3[3:0] PWMCMP2[3:0] PWMCMP1[3:0] RW RW RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 28 ADTRG[3:0] Set the Initial channel triggered by the external pin ADTRG: Sample from channel n (n=ADTRG[3:0]) 27 ~ 24 TIM8SEL[3:0] Set the Initial channel triggered by TIM8: Sample from channel n (n=TIM8SEL[3:0]) 23 ~ 20 PCA1SEL[3:0] Set the Initial channel triggered by PCA1: Sample from channel n (n=PCA1 SEL [3:0]) 19 ~ 16 PCA0SEL[3:0] Set the Initial channel triggered by PCA0: Sample from channel n (n=PCA0 SEL [3:0]) 15 ~ 12 PWMCMP4[3:0] Set the Initial channel triggered by PWMCMP4_MCM: Sample from channel n (n= PWMCMP4[3:0]) 11 ~ 8 PWMCMP3[3:0] Set the Initial channel triggered by PWMCMP3_MCM: Sample from channel n (n= PWMCMP3[3:0]) 7 ~ 4 PWMCMP2[3:0] Set the Initial channel triggered by PWMCMP2_MCM: Sample from channel n (n= PWMCMP2[3:0]) 3 ~ 0 PWMCMP1[3:0] Set the Initial channel triggered by PWMCMP1_MCM: Sample from channel n (n= PWMCMP1[3:0])

20.4.11 The ADC's channel length of hardware triggering register (Single resistance mode)

(ADC_HARDCHLH) Offset Address: 0x0064 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 ADTRG[3:0] TIM8LH[3:0] PCA1LH[3:0] PCA0LH[3:0] RW RW RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 PWMCMP4[3:0] PWMCMP3[3:0] PWMCMP2[3:0] PWMCMP1[3:0] RW RW RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 28 ADTRG[3:0] Set the number of channels triggered by the external pin ADTRG: Sample n+1 channels (n=ADTRG[3:0]) 27 ~ 24 TIM8LH[3:0] Set the number of channels triggered by TIM8: Sample n+1 channels (n=TIM8LH[3:0]) 23 ~ 20 PCA1LH[3:0] Set the number of channels triggered by PCA1: Sample n+1 channels (n= PCA1LH [3:0]) 19 ~ 16 PCA0LH[3:0] Set the number of channels triggered by PCA0: Sample n+1 channels (n= PCA0LH [3:0]) 15 ~ 12 PWMCMP4[3:0] Set the number of channels triggered by PWMCMP4_MCM: Sample n+1 channels (n=PWMCMP4[3:0])

11 ~ 8 PWMCMP3[3:0] Set the number of channels triggered by PWMCMP3_MCM: Sample n+1 channels (n=PWMCMP3[3:0]) 7 ~ 4 PWMCMP2[3:0] Set the number of channels triggered by PWMCMP2_MCM: Sample n+1 channels (n=PWMCMP2[3:0]) 3 ~ 0 PWMCMP1[3:0] Set the number of channels triggered by PWMCMP1_MCM: Sample n+1 channels (n=PWMCMP1[3:0])

20.4.12 ADC Channel GAP Control Bit (ADC_ADGAPON)

Offset Address: 0x0068 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 GAPENy(y=15~0) RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 16 Reserved - 15 ~ 0 GAPENy(y=15~0) GAP time enable bit of ADC channel y 0: Disabled 1: Enabled

20.4.13 ADC Interrupt Flag and Clear Register (ADC_ADINTF)

Offset Address: 0x006C Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved ADIF C ADG IFC ADLI FC - WO WO WO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Reserved ADIF ADG IF ADLI F - RO RO RO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 19 Reserved -

18 ADIFC SHB channel sequence conversion end interrupt flag bit clear bit in

two-channel independent sequential sampling mode 0: Invalid 1: Clear

17 ADGIFC Upper limit compare interrupt flag bit clear bit

0: Invalid 1: Clear

16 ADLIFC Lower limit compare interrupt flag bit clear bit

0: Invalid 1: Clear 15 ~ 3 Reserved -

2 ADIF SHB channel sequence conversion end interrupt flag bit in two-channel

independent sequential sampling mode 0: No channel sequence conversion end interrupt occurs 1: There is channel sequence conversion end interrupt occurring

1 ADGIF Upper limit compare interrupt flag bit

0: No upper limit interrupt occurs, and the latest updated value in the result register specified by the CSEL bit segment is smaller than the value in ADDGT 1: There is upper limit interrupt occurring, and the latest updated value in the result register specified by the CSEL bit segment is greater than or equal to the value in ADDGT. This flag needs to be cleared by software after it is set.

0 ADLIF Lower limit compare interrupt flag bit

0: no lower limit interrupt occurs, and the last updated value in the result register specified by the CSEL bit segment is greater than the value in ADDLT 1: upper limit interrupt occurs, and the latest updated value in the result register specified by the CSEL bit segment is smaller than or equal to the value in ADDLT. This flag needs to be cleared by software after it is set.

1. Quadrature Encoder Interface (QEI)

21.1 Introduction

Incremental rotary encoders are often used in motor control systems to real-time monitor the position and speed of the rotating system. The encoder usually has three output signals: two square wave signals QEA, QEB with a phase difference of 90 degrees, and an index signal INDEX. In practical applications, the encoder is usually mounted on a rotating shaft, such as a motor rotor. The QEA/QEB signal frequency output by the encoder is proportional to the motor rotation rate. For example, a 1000-line encoder is mounted on a motor with a speed of 6000 rpm. The encoder will generate 100 KHz QEA and QEB signals, so the motor speed can be determined by measuring the QEA or QEB output. When rotating clockwise, most encoders output QEA signals advance QEB signals, and when rotating counterclockwise, QEA signals output lags QEB signals. An INDEX pulse signal is output every revolution to indicate an absolute position. The pulse width of the index signal INDEX varies from different encoders, and the signals are roughly classified into two types: gated index signals and non-gated index signals. The pulse rising and falling edges of gated index signals must be aligned with two of the four edges of the quadrature signal QEA/QEB, with a pulse width of 1/4, 1/2 or the entire QEA/QEB signal period, and edges of non-gated index signals are not absolutely associated with edges of QEA/QEB. The quadrature signal QEA/QEB output by the encoder can have four states. The typical incremental rotary encoder output signals are shown below: Figure21-1 Output Signals of Incremental Rotary Encoders The following figure provides a logical block diagram: QEI Decoder Input Filter Input Filter QEA QEB INDEX QEIA QDIR QEIB QIDX QIDXCPS QSWAP pre- dividerPclk1 pre- divider QABCPS QIDXS QDIR QCLK QPOSCNT QMAXCNT Cmp Swap QPOSLAT QCNT QTMLAT pre- divider Control Logic Pclk1 Figure21-2 Logical Block Diagram of Quadrature Encoder Interface (QEI) QEA QEB INDEX (a) (b) Corotation Reversion

21.2 Main Features

 3 input pins: two phase signals QEA, QEB and one index pulse signal INDEX  16-bit incremental/decremental bidirectional position counter  2 position count modes: x2 mode and x4 mode  Digital filter function of input pin  Provides two application solutions: low speed measurement and high-speed measurement  Contains a 32-bit Qtimer

21.3 Function Description

To improve system immunity, the QEI module provides internal digital filtering circuitry for three input pins QEA, QEB and INDEX. User can control whether QEA/QEB and INDEX pins use the filtering function via QABFEN and QIDXFEN respectively. When QABFEN=1, the filter circuits of pins QEA and QEB are valid, and the level of the QEA and QEB pin input signals must be stable for at least 3 filter clock periods to make the filtered output signal change. The filter clock is divided by the APB clock division (PCLK), and the division value is set by QABCPS. When QIDXFEN=1, the filter circuit of pin INDEX is valid, and the level of the INDEX pin input signal must be kept at a stable state for at least 3 filter clock periods to make the filtered output signal change. The filter clock is divided by the APB clock division (PCLK), and the division value is set by QIDXCPS. When different filter setting states are sampled from the QEA, QEB, and INDEX pins, the phases of the three input signals of the subsequent stage circuit will change. User needs to set the filtering function reasonably to ensure that the working result of the subsequent stage circuit conforms to the design intent. .

21.3.1 Quadrature Decoder

The quadrature decoder built in the QEI module. It is used for decoding the input signals of the pins QEA and QEB to determine the operating state of the incremental rotary encoder.

21.3.1.1 Interface Signals of Quadrature Decoders

After passing through the filter circuit, the signal input from pin QEA/QEB is first controlled by the QSWAP bit and then input to the quadrature decoder for decoding. Modifying the QSWAP control bit can meet the application requirements of different incremental rotary encoders. QSWAP=0, the QEA and QEB signals of the pin input are directly decoded without exchanging, and are often used for the rotary encoder with QEA phase leading QEB corresponding to corotation. QSWAP=1, the QEA and QEB signals of the pin input are exchanged first and then decoded, and they could be used for the rotary encoder with QEA phase leading QEB corresponding to reversion. The following sections all take the setting of QSWAP=0 as an example, and the case of QSWAP=1 can be analogized. The quadrature decoder outputs the QCLK signal as the count clock of the position counter QPOSCNT. The generation of QCLK is controlled by QPMOD[1:0]. Under different setting conditions, the quadrature decoder provides two QCLK generation modes: x2 mode and x4 mode. The quadrature decoder outputs QPDIR to indicate the counting direction, and user can read the register of the same name via software to determine the counting direction. QPDIR=0, QPOSCNT counts QCLK down; QPDIR=1, QPOSCNT counts QCLK up.

21.3.1.2 Rotation Direction and Counting Direction

The quadrature decoder determines the rotation direction of the incremental rotary encoder based on the state of the input QEA/QEB signals. With [QEA:QEB] as the state word, the possible state transition process is shown in the figure below, and the description of each icon is as follows: 1101 00 10 S R F R FRRF PE QEA QEB 10 11 01 00 (a) Forward 0111 10 00 (b) Reverse PE SS S QEA QEB 11 01 00 1000 11 10 00 01 11 1001 F Figure21-3 QEA/QEB State Switch Diagram

F indicates that the QEA phase leads QEB, the encoder rotates in the forward direction, and the [QEA:QEB] state word is converted clockwise according to the figure. In this process, QPDIR will output 1; R indicates that the QEB phase leads QEA, the encoder rotates in the reverse direction, and the [QEA:QEB] status word is converted counterclockwise according to the figure. In this process, QPDIR will output 0; PE indicates that QEA and QEB are in same phase or opposite phase (the transition between the diagonal states shown in the figure should not occur when the encoder is working normally). At this time, the decoder will determine the occurring of phase error and set the interrupt flag QPEIF. S indicates that the phase relationship between QEA and QEB has not changed.

21.3.2 Position Counter

The QEI module has internal 16-bit position counter QPOSCNT, which performs incremental/decremental bidirectional counting on QCLK output by the quadrature decoder. The counting direction is controlled by QPDIR, and the count mode and reset mode are controlled by QPMOD. The QPMOD[1:0] control bit provides two count modes, which are also the QCLK generation modes: x2 mode and x4 mode. The QPMOD[1:0] control bit provides two reset modes: automatic loop reset and INDEX reset.

21.3.2.1 Count Mode of Position Counter

When QPMOD = 00/01, the position counter operates in x2 count mode, in which QCLK generates a pulse on the rising and falling edges of QEA, thus the counter counts both edges of QEA. The operating timing of the counter in x2 count mode is shown in the figure below: 10 11 01 00 10 10 00 01 11 10 00 01 11 11 01 00 10 QEA QEB QPDIR QCLK Figure21-4 QPOSCNT Operating Timing in x2 Count Mode When QPMOD=10/11, the position counter operates in x4 count mode, in which QCLK generates a pulse on the rising and falling edges of both QEA and QEB, so the counter counts both edges of QEA and QEB. The operating timing of the counter in x4 count mode is as shown below: 10 11 01 00 10 10 00 01 11 10 00 01 11 11 01 00 10 QEA QEB QPDIR QCLK Figure21-5 QPOSCNT Operating Timing in x4 Count Mode

21.3.2.2 Reset Mode of Position Register

When QPMOD = 00/10, the position counter uses the index pulse INDEX reset mode. In this reset mode, the hardware will automatically detects the input signal of the INDEX pin. Each time after INDEX changes from 0 to 1, the first QCLK count pulse that satisfies the condition will trigger a reset action. If QPOSCNT is in the up-count operation process when the reset action occurs, QPOSCNT is automatically reset to 0. If QPOSCNT is in the down-count operation process, QPOSCNT automatically reloads the QPOSMAX setting value. The reset action is also controlled by QIDXEN. When QIDXEN=1, all reset actions are valid. After the first reset action, QPOSCNT will perform cycle counting in the range of 0~QPOSMAX. When QIDXEN=0, all reset actions are invalid. QPOSCNT is automatically reset to 0 after up-count operation to QPOSMAX. After down-count operation to 0, it is automatically reset to QPOSMAX, and performs loop count in the range of 0~QPOSMAX. When a reset action occurs, the QEIIF interrupt flag is set by hardware regardless of the QIDXEN setting state. In order to ensure the symmetry of the count values during the corotation and reversion process, each time the QEI function is rebooted (QEIEN changes from 0 to 1) or each time QPMOD is written to a new set value. Hardware will record the changing edge state of the corresponding QEA or QEB at the time of the first INDEX reset event after this. Then, each time in the following INDEX changes from 0 to 1, it finds the first reset event that satisfies the condition according to the table below and triggers the reset action. There are four combinations to set QEA and QEB: S0 is 00, S1 is 10, S2 is 11, and S3 is 01. First reset event after reboot Reset event n after reboot (n≠1) Sn->Sm Same direction as the first reset event after reboot Sn->Sm Opposite direction as the first reset event after reboot Sm->Sn Note 1: The ranges of n and m are both 1~4. Note 2: Assuming 0-1=3, 3+1=0, then the relationship between m and n is, m=n+1 during corotation, m=n-1 during reversion. Note 3: Four state changes are detected at the rising edge of INDEX, and the INDEX falling edge will end the detection after a change is detected. Taking QPMOD[1:0]=10 and QPOSMAX=99 as an example, if S3->S0 is occurred during the first reset action after the QEI function is rebooted, the timing relationship of each key signal is shown in the figure below (the gray box indicates the location of the reset event): 10 11 01 00 10 10 00 01 11 10 00 01 11 10 00 01 QEA QEB QPDIR QCLK QPOSCNT 5 4 98 INDEX 3 2 1 043210nn-1n-2 10 11 01 00 1st 2nd 97 96 95 QEIIF cleared by software cleared by software Figure21-6 Operating Timing of the Reset Mode of Index Pulse INDEX (x4 Count Mode)

When QPMOD[1:0]=01/11, the position counter uses the automatic loop reset mode. In this reset mode, when QPOSCNT is equal to the QPOSMAX setting value during the up-count operation process, QPOSCNT is automatically reset to 0 at the next QCLK, and then continues to count up QCLK; when QPOSCNT is equal to 0 during the down-count operation process, QPOSCNT reloads the QPOSMAX setting value at the next QCLK, and then continues to count down. The automatic loop reset mode is not controlled by the INDEX signal, and the position counter QPOSCNT is automatically made to loop count in the range of 0~QPOSMAX. Hardware automatically sets the QEIIF flag during overflow/underflow reset of QPOSCNT. Taking QPMOD=11 and QPOSMAX=99 as an example, the timing relationship of each key signal is shown in the following figure: 10 11 01 00 10 10 00 01 11 10 00 01 11 11 01 00 QEA QEB QPDIR QCLK QPOSCNT 5 4 983 2 1 043210999897 10 11 01 00 99 97 96 95 QEIIF cleared by software cleared by software Figure21-7 Operating Timing of the Automatic Loop Mode (x4 Count Mode)

21.3.3 Speed Measurement Modes

There are two modes for speed measurement, low-speed and high-speed. In low-speed applications, the increment of the corresponding time is detected by fixing the value of QPOSCNT. In high-speed applications, the increment of the corresponding time is detected by the changing value of QPOSCNT, which improves the measurement accuracy.

21.3.3.1 Low-speed Measurement Mode

In low speed tachometer applications, the QEI module uses QTimer as a counter for time increments. Note: When QTimer modifies the QTPSQ to the new setting value during normal operation, it will change the frequency of the counting clock immediately. It is recommended that user should modify the QTPSQ setting value when the QTimer is in non-counting state to ensure the stability of the counting clock frequency. When the QEI function is turned on, each QCLK output by the quadrature decoder can trigger a capture event, and the frequency of occurrence of the capture event is set by QTEPS. When a valid capture event occurs, the hardware automatically latches the current QCNT count value into the QTMLAT register, and sets the QTCAPIF interrupt flag (when QEIEN=1 the first capture event after the QTimer count is started does not set the flag), then clear the QTimer counter to 0 and restart the up-count operation. After detecting the QTCAPIF flag, user can calculate the rotation speed according to the event trigger frequency setting (fixed QPOSCNT change value) and the QTMLAT latch value. The QTCAPIF flag is cleared by user software writing 0. When QTimer counts to QTPR, the hardware automatically resets the counter to 0 and restarts up-count operation, and sets the QTIF flag. User needs to accurately set QTEPS to prevent QTimer from overflowing before the capture event occurs. By querying the QTIF flag, it can be judged whether the QTimer has overflowed before the capture occurs. When QEIEN=1, QTEPS is modified to new setting value change in QTimer boot state, and the new setting value won’t be valid until the next capture event occurs. In the low-speed speed measurement application, the timing relationship of each key signal is shown in the figure below (the QTCAP signal indicates that a capture event has occurred and the QTCAPIF flag bit is set):

11 01 00 00 10 11 01 00 10 11 01 00 1010 11 QTIF QCNT 0000 QTPR Figure21-8 Key Signals Diagram of Low-speed Measurement Application (QTEPS=0001)

21.3.3.2 High-speed Measurement Mode

When the motor speed is very fast, the number of QCNTs captured by the encoder during a QCLK is relatively small, and the speed accuracy obtained at this time cannot meet the requirements. By setting the QCNTMIN value, if the value of QCNT is less than QCNTMIN when the capture signal occurs, the capture signal is ignored, and QCNT continues to increase, but the number of captures is recorded. Until QCNT is greater than or equal to QCNTMIN when a capture signal occurs, QTCAPIF can be set, then the recorded capture division times is placed in the upper 16-bit of QTMLAT, and QCNT is placed in the lower 16-bit of QTMLAT, with one CLOCK storing 32-bit data. As shown in the following figure, set QCNTMIN to 0x1200. During the first 6 times of division for QTCAP, the values of QCNT are all less than QCNTMIN. At the seventh division, QCNT is 0x1234, which is greater than 0x1200 of QCNTMIN, so capture overflow is triggered at this time. 7 is placed at the high 16-bit of QTMLAT and 0x1234 is placed at the lower 16-bit of QTMLAT simultaneously. QEA QEB QCLK QTCAP 00 10 QTCAPIF 11 01 00 00 10 11 01 00 10 11 01 00 1010 11 QCNT 0000 QCNTMIN QTMLAT 0x0007 1234 0x1234 0x0008 1500 Figure21-9 Key Signals Diagram of High-speed Measurement Application (QTEPS=0001)

21.3.4 Interrupt of QEI Module

21.3.4.1 QEI Function Interrupt

The QEI module uses QEIIE and QEIIF to control and indicate the interrupt of the QEI function, which is only valid when the QEI function is on (QEIEN=1). When QPMOD=00/10, the position counter uses the index pulse INDEX reset mode. When an INDEX reset event occurs, the hardware automatically sets the QEIIF flag. If QEIIE=1 at this time, the corresponding interrupt is triggered. The interrupt flag bit QEIIF is cleared by user software writing 0. When QPMOD=01/11, the position counter uses the automatic loop reset mode. In this reset mode, the position counter QPOSCNT automatically performs loop counting in the range of 0~QPOSMAX. When the count overflows or underflows, the QEIIF flag is automatically set by hardware. If QEIIE=1 at this time, the corresponding interrupt is triggered. The interrupt flag bit QEIIF is cleared by the user software writing 1 to QEIIFC.

21.3.4.2 Count Error Interrupt

When the QEI function is on (QEIEN=1) and QPMOD=00/10 uses the index pulse INDEX reset mode, the hardware uses QCEIE and QCEIF to control and indicate the count error interrupt. This interrupt is only valid after the first reset event. When the first reset event occurs, the QPOSCNT count value will range from 0 to QPOSMAX. When during the following up-count operation process the count value changes from QPOSMAX to QPOSMAX+1, or during the down-count operation process the count value changes from 0 to 0xFFFF, the QCEIF flag is automatically set by hardware to indicate that count error has occurred. If QCEIE=1 at this time, the corresponding interrupt is triggered. The interrupt flag bit QCEIF is cleared by the user software writing 1 to QCEIFC.

21.3.4.3 Phase Error Interrupt

When the QEI function is on (QEIEN=1), the quadrature decoder will automatically check the state transition process of [QEA:QEB]. When the QEA and QEB are detected to be in the same phase or reversed phase, the decoder will determine the occurrence of phase detection error, and set the interrupt flag QPEIF. If QPEIE=1 at this time, the corresponding interrupt is triggered. The interrupt flag bit QPEIF is cleared by the user software writing 1 to QPEIFC.

21.3.4.4 QEI(QTimer) Capture Event Interrupt

When the QEI function is on (QEIEN=1), QTimer is used as a secondary timer for the QEI function, and the hardware uses QTCAPIE and QTCAPIF to control and indicate capture event interrupts. When a valid capture event occurs, the hardware automatically latches the current QCNT count value into the QTMLAT register and sets the QTCAPIF interrupt flag (after QEIEN=1 starts the QTimer count, the first capture event does not set the flag). If QTCAPIE=1 at this time, the corresponding interrupt is triggered. The interrupt flag bit QTCAPIF is cleared by the user software writing 1 to QTCAPIFC.

21.3.4.5 QTimer Overflow Interrupt

As a separate 32-bit timer, QTimer overflows after counting to the QTPR setting value. The counter is automatically reset to 0 and restarts up-count operation, and the QTIF flag is set at the same time. If QTIE =1 at this time, the corresponding interrupt is triggered. The interrupt flag bit QTIF is cleared by the user software writing 1 to QTIFC.

21.4 Registers

QEI Module Register List (Base Address: 0x4000 1400) Address Register Name Description 0x4000 1400 QEICON QEI control register 0x4000 1404 QFLTCON QEI input pin filter control register 0x4000 1408 QPOSCNT QEI position count register 0x4000 140C QPOSMAX QEI maximum count value register 0x4000 1410 QTMLAT QEI count value latch register 0x4000 1414 QCNT QEI count register 0x4000 1418 QCNTMIN QEI counter minimum count value during capture 0x4000 141C QTPR QEI counter period register 0x4000 1420 QTPSQ QEI counter pre-division register 0x4000 1424 QEIINT QEI interrupt and state counter register 0x4000 1428 QTINTF QEI interrupt flag and clear register

21.4.1 QEI Control Register (QEI_QEICON)

Offset Address: 0x0000 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Reserved QTEPS[3:0] QPDIR QIDXS QSWA P QIDXE N QEIEN QTSR QPMOD[1:0] - RW RO RO RW RW RW RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 12 Reserved - 11 ~ 8 QTEPS[3:0] QEI (QTimer) capture event division setting bit (only valid when QEI function is on): 0000: QCLK/1 0001: QCLK/2 0010: QCLK/4 0011: QCLK/8 0100: QCLK/16 0101: QCLK/32 0110: QCLK/64 0111: QCLK/128 1000: QCLK/256 1001: QCLK/512 1010: QCLK/1024 1011: QCLK/2048 Others: Reserved

7 QPDIR Encoder rotation direction state bit:

0: QEA signal phase is behind QEB, encoder performs reverse rotation, position counter counts down 1: QEA signal phase leads QEB, the encoder perfoms forward rotation, position counter counts up.

6 QIDXS INDEX input signal (QEI quadrature decoder input position) level state

indicate bit: 0: INDEX input low level 1: INDEX input high level

5 QSWAP QEA and QEB input exchange selection bit:

0: QEA phase and QEB phase input are not exchanged and are directly provided to the quadrature decoder. 1: QEA phase is exchanged with QEB phase input and then provided to quadrature decoder

4 QIDXEN Position counter reset enable bit: (valid only when QPMOD=00/10)

0: Index pulse INDEX cannot reset position counter 1: Index pulse INDEX can reset position counter

3 QEIEN QEI function enable control bit:

0: QEI function is disabled 1: QEI function is enabled, and the specific working mode is controlled by QPMOD.

2 QTSR QEI counter start-up bit:

0: Does not start Qtimer 1: Starts Qtimer Note: This bit is the open bit of whether Qtimer is operating when QEIEN is 0. When QEIEN is 1, this bit control is invalid. 1 ~ 0 QPMOD[1:0] QEI position counter count selection bit: (only valid when QEI function is on) 00: ×2 count mode, resets position counter using index pulse INDEX 01: ×2 count mode, position counter automatically loop counts between 0~QPOSMAX 10: ×4 count mode, resets position counter using index pulse INDEX 11: ×4 count mode, position counter automatically loop counts between 0~QPOSMAX

21.4.2 QEI Input Pin Filter Control Register (QEI_QFLTCON)

Offset Address: 0x0004 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Reserved QIDXF EN QIDXCPS[2:0] QABF EN QABCPS[2:0] - RW RW RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 8 Reserved -

7 QIDXFEN INDEX input pin filter enable bit:

0: Filter function of INDEX input pin is disabled 1: Filter function of INDEX input pin is enabled 6 ~ 4 QIDXCPS[2:0] INDEX pin filter clock division coefficient: 000: 1/1 PCLK 001: 1/2 PCLK 010: 1/4 PCLK 011: 1/16 PCLK 100: 1/32 PCLK 101: 1/64 PCLK 110: 1/128 PCLK 111: 1/256 PCLK

3 QABFEN QEA and QEB input pin filter enable bit:

0: Filter function of QEA & QEB input pin is disabled 1: Filter function of QEA & QEB input pin is enabled

2 ~ 0 QABCPS[2:0] QEA and QEB pin filter clock division coefficient: 000: 1/1 PCLK 001: 1/2 PCLK 010: 1/4 PCLK 011: 1/16 PCLK 100: 1/32 PCLK 101: 1/64 PCLK 110: 1/128 PCLK 111: 1/256 PCLK

21.4.3 QEI Position Count Register (QEI_QPOSCNT)

Offset Address: 0x0008 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 QPOSCNT[15:0] RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 16 Reserved - 15 ~ 0 QPOSCNT[15:0] 16-bit incremental/decremental bidirectional counter, with counting direction controlled by QPDIR bit

21.4.4 QEI Maximum Count Value Register (QEI_QPOSMAX)

Offset Address: 0x000C Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 QPOSMAX[15:0] RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 16 Reserved - 15 ~ 0 QPOSMAX[15:0] Maximum count value register of position counter

21.4.5 QEI Count Value Latch Register (QEI_QTMLAT)

Offset Address: 0x0010 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 QTMLAT [31:0] RO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 QTMLAT [31:0] RO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 0 QTMLAT [31:0] Latches QCNT count value when condition is required

21.4.6 QEI Count Register (QEI_QCNT)

Offset Address: 0x0014 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 QCNT [31:0] RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 QCNT [31:0] RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 0 QCNT [31:0] 32-bit counter Note: Cannot be modified when QEIEN is 1

21.4.7 QEI Counter Minimum Count Value during Capture (QEI_QCNTMIN)

Offset Address: 0x0018 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 QCNTMIN[15:0] RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

31 ~ 16 Reserved - 15 ~ 0 QCNTMIN[15:0] When the capture event occurs, if the value of QCNT is less than the value of the QCNTMIN register, then the capture event does not occur, and the internal capture division is incremented by one until the value captured and occurred to QCNT is greater than QCNTMIN, then the division and current QCNT are automatically latched into QTMLAT.

21.4.8 QEI Counter Periodic Register (QEI_QTPR)

Offset Address: 0x001C Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 QTPR [31:0] RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 QTPR [31:0] RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 0 QTPR [31:0] 32-bit periodic register

21.4.9 QEI Counter Clock Predivision Value (QEI_QTPSQ)

Offset Address: 0x0020 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 QTPSQ[15:0] RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 16 Reserved - 15 ~ 0 QTPSQ[15:0] Counter clock pre-division value

21.4.10 QEI Interrupt and State Counter (QEI_QEIINT)

Offset Address: 0x0024 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Reserved QTIE QTCA PIE QEIIE QCEIE QPEIE - RW RW RW RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 5 Reserved -

4 QTIE Qtimer overflow interrupt enable bit:

0: Disables triggering interrupt when Qtimer overflow event occurs 1: Enables triggering interrupt when Qtimer overflow event occurs

3 QTCAPIE QTimer capture event interrupt enable bit (only valid when QEI function

is on): 0: Disables triggering interrupt when capture event occurs 1: Enables triggering interrupt when capture event occurs

2 QEIIE QEI function interrupt enable bit:

0: Disables QEI interrupt 1: Enables QEI interrupt

1 QCEIE In INDEX signal reset position counter mode, error detection interrupt

enable bit: 0: Disables error detection interrupt 1: Enables error detection interrupt

0 QPEIE Encoder input phase error interrupt enable bit, with QEA/QEB signals

considered phase error when they are in the same phase or opposite phases: 0: Disables phase error interrupt 1: Enables phase error interrupt

21.4.11 QEI Interrupt Flag and Clear Register (QEI_QTINTF)

Offset Address: 0x0028 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved QTIFC QTCA PIFC QEIIFC QCEIF C QPEIF C - WO WO WO WO WO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Reserved QTIF QTCA PIF QEIIF QCEIF QPEIF - RO RO RO RO RO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

31 ~ 21 Reserved -

20 QTIFC Qtimer overflow flag clear bit

0: Invalid 1: Clear

19 QTCAPIFC QEI(QTimer) capture event interrupt flag clear bit

0: Invalid 1: Clear

18 QEIIFC QEI function interrupt flag clear bit

0: Invalid 1: Clear

17 QCEIFC QEI position counter count error flag clear bit

0: Invalid 1: Clear

16 QPEIFC QEI decoder phase error flag clear bit

0: Invalid 1: Clear 15 ~ 5 Reserved -

4 QTIF QTimer overflow flag bit:

0: OTPR value overflow being counted is not occurred in QCNT 1: OTPR value overflow being counted is occurred in QCNT

3 QTCAPIF QEI(QTimer) capture event interrupt flag bit (only valid when QEI

function is on): 0: No capture event occurs 1: There is capture event occurring, and software has latched Qtimer.CNT value into QTMLAT

2 QEIIF QEI function interrupt flag bit, used as INDEX reset event when

QPMOD=00/10 0: No INDEX reset event occurs 1: INDEX reset event has occurred QEI function interrupt flag bit, used as position count overflow or underflow flag when QPMOD=01/11 0: Position counter overflow or underflow occurs 1: Position counter overflow or underflow has occurred

1 QCEIF QEI position counter count error flag bit:

0: Count misalignment interrupt does not occur in QEI position counter 1: Count misalignment interrupt has occurred in QEI position counter

0 QPEIF QEI decoder phase error flag bit:

0: No input signal phase detection error interrupt occurs 1: Input signal phase detection error interrupt has occurred

1. Analog Module On Chip (AMOC)

22.1 Introduction

SH33F2801 integrates four high-speed operational amplifiers and two comparators on chip. The operational amplifiers select the amplification factor via external resistors, and the amplified signal can be directly sampled by ADC. The comparators are multi-input comparators, and the positive input of the comparator and the positive input of the OP can be multiplexed. Both functions can be implemented simultaneously.

22.2 Main Features

 Integrates 4 general-purpose operational amplifiers, the input and output ports of the amplifier are open, and the op amp gain can be adjusted via external resistors.  The amplifier output can be used directly as input of the ADC conversion module or as positive input port of the comparators  Amplifier 0 can choose internal gain mode, there are eight gain multiples, the maximum 32 gain  Two comparators are multi-input comparators, the positive input has three external pins, or OP output can be selected  Comparator output result can be used as MCM and PCA fault detection input signal after filtering  Comparator negative input reference signal can be input from external devices, or as reversed input using internal reference voltage (8 thresholds)  Comparator has internal Schmitt window and digital filter circuit, the output can trigger interrupts of the rising edge, the falling edge and both edges

22.3 Operational Amplifier

22.3.1 Op Amp Typical Application Diagram

x 1.8K OPxOUT VDD 102 20K 1KVin OPxP OPxN ADC SEQx OPxG =0 10K Figure22-1 Op Amp Typical Application Diagram OP0 IO VDD 102 20K 1KVin OP0P0 IO ADC SEQx OP0G Figure22-2 Op Amp Typical Application Diagram(OP0P0 Internal Gain)

22.4 Comparator

22.4.1 Comparator Usage

SH33F2801 has two comparators, comparator 0 and comparator 1. The outputs of the two comparators can be used as fault inputs of the MCM and PCA modules to automatically turn off PWM output quickly to achieve fast protection. They could also be used in some voltage/current closed loops. All two comparators integrate filter constant programmable digital filter circuit, while providing interrupt function at the same time. They are suitable for applications requiring accurate comparison, such as the back electromotive force zero-crossing detection of DC brushless motor. Comparator 1 have programmable Schmitt windows, The difference between comparator 0 and comparator 1 is that it is implemented in a different way. Comparator 0 is implemented through OP0, and Comparator 1 is an independent comparator. Note: 1. The power-on default state of the comparators is off. 2. The function of the comparator1 and the function of the amplifier1 can be implemented simultaneously. 3. The function of the comparator0 and the function of the amplifier0 cannot be implemented simultaneously. Comparator filter method description: use the internal clock (RC8M) to sample filter input, if the sampling result is high level, the counter is incremented by 1, until the counter result exceeds the set constant, then the filter outputs 1 and the counter is set to the filter constant. If the sampling result is low level, the counter is decremented by 1, until the counter result is less than the filter constant, then the filter outputs 0 and the counter is set to zero. Note: 1. The upper limit of the counter is set to the filter constant, the lower limit is 0. If the upper and lower limits are exceeded, no addition and subtraction is performed. 2. Filter counter initial value setting: if the comparator interrupt is set to rising edge trigger, the initial value of the counter is 0; if it is set to falling edge trigger, the initial value of the filter counter is set to the filter constant. If set to both edges triggering and no triggering, the initial value of the filter counter is set to the filter constant. 3. The filter output stabilizing needs a settling time, which is roughly the time set by the filter constant. If the filter constant is set to 256, the filter output is stable after 256 system clocks. Before this, the filter output is not certain, and the interrupt flag CxIF may be set wrongly to 1, so when the filter is just turned on, this interrupt flag bit is required to be cleared by software after the filter output is stable.

22.4.2 Comparator Block Diagram

For details of the flow of the output waveform of the comparator, refer to the following figure: C0N C0NCHS AVDD CMP0EN MUX CMP0 Debounce C0DEB[2:0] C0OUT C0IF MUX C0PCHS MUX CMP0VRS C0P MCM_PWM 0/1/2Fault PCA0 A/B/CFault PCA1 A/B/CFault CP0P0/OP0P0 MUX AVDD VREF CMP0VCMP CP0P1/OP0P1 CP0P2/OP0P2 OP1OUT OP2OUT OP3OUT Figure22-3 Multi-channel Input Analog Comparator 0

C1DEB[1:0] C1OUT C1IF MUX C1PCHS C1SMT[1:0] CMP1 CP1P2 C1N C1NCHS MUX MUX CMP1VRS MUX AVDD VREF CMP1VCMP OP3OUT MCM_PWM 0/1/2Fault PCA0 A/B/CFault PCA1 A/B/CFault Figure22-4 Multi-channel Input Analog Comparator 1 Comparator 1 can set the Schmitt comparator window (hysteresis comparator) by setting register CxSMT[1:0] (x=0/1), as shown in the figure below: OUTPUT INTPUT C1P C1N VOH VOL Schmit-Triger window Schmit-Triger window CxSMT[1:0] = 0 CxSMT[1:0] != 0 CxSMT[1:0] = 0 CxSMT[1:0] != 0 Figure22-5 Schmitt comparator window Note: The VREF in Figure 22-3 and Figure 22-4 refers to the external VREF pin (PB14)。

22.5 Register

AMOC Module Register List (Base Address: 0x4000 3800) Address Register Name Description 0x4000 3800 CMP0CON Comparator 0 control register 0x4000 3804 CMP1CON Comparator 1 control register 0x4000 3808 CMPINTF Comparator interrupt flag and clear register 0x4000 380C OPCON Amplifier control register

22.5.1 Comparator 0 control register (AMOC_CMP0CON)

Offset Address: 0x0000 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Rese rved C0O UT2 C0O UT1 C0O UT0 CMP AUT O TRG POL PWMTRGS[1 :0] CMPGAP[1: CMP0VRS[5:0] - RO RO RO RW RW RW RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 CMP 0EN CMP 0VC MP CP0 NOU TEN C0O UTE N C0IES[1:0] Reserved C0N CHS C0PCHS[2:0] C0O UT C0DEB[2:0] RW RW RW RW RW - RW RW RO RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description

30 C0OUT2 Enable automatic rotation comparison of CMP0, the comparison

result of CP0P2(OP0P2)

29 C0OUT1 Enable automatic rotation comparison of CMP0, the comparison

result of CP0P1(OP0P1)

28 C0OUT0 Enable automatic rotation comparison of CMP0, the comparison

result of CP0P0(OP0P0)

27 CMPAUTO Comparator 0 automatic rotation comparison function enable bit

0: Turn off automatic rotation comparison 1: Turn on automatic rotation comparison Note: If CMPAUTO = 0, the input to comparator 0 is determined by the C0PCHS[2:0] bits; if CMPAUTO = 1, OP0P0~OP0P2 are the inputs of CMP0

26 TRGPOL Comparator 0 comparison function control bit

0: Compare only during the valid period of PWM output 1: Compare only during invalid PWM output 25 ~ 24 PWMTRGS[1:0] Comparator 0 synchronizes comparison control bits 00: Continuous comparison mode, no synchronous comparison function 01: Synchronize with PWM0 output 10: Synchronize with PWM1 output 11: Synchronize with PWM2 output 23 ~ 22 CMPGAP[1:0] The intervals of automatic rotation comparison: 00: 32 APB Clock 01: 48 APB Clock 10: 64 APB Clock 11: 80 APB Clock

21 ~ 16 CMP0VRS[5:0] Comparator 0 Negative terminal reference voltage selector bit xxx: (1+CMP0VRS[5:0])/ 64 *Vcmp Note: Negative terminal voltage range is 1/64~64/64

15 CMP0EN Comparator 0 enable control bit

0: Comparator is off 1: Comparator is on

14 CMP0VCMP Comparator 0 negative terminal reference voltage source Vcmp

0: AVDD 1: External VREF(PB14)

13 CP0NOUTEN When Internal reference source is used as the negative terminal of

comparator, whether the comparator N output to CP0N 0: No output 1: Output Note: This bit is only valid while C0NCHS = 1 and OP0EN = 0.

12 C0OUTEN Comparator 0 I/O output port enable

0: Disables outputting C0OUT to IO(CP0OUT) , CP0OUT is normal IO 1: Enables outputting C0OUT to IO(CP0OUT) Note: I/O output has filter function, with filter parameter being the set value of C0DEB[2:0] 11 ~ 10 C0IES[1:0] Comparator 0 interrupt mode selection bit 00: Interrupt flag is not triggered 01: Falling edge triggers, interrupt flag is triggered when comparator 0 output is from high to low 10: Rising edge triggers, interrupt flag is triggered when comparator 0 output is from low to high 11: Both edges trigger, interrupt flag is triggered when comparator 0 output is from high to low and from low to high. 9 ~ 8 Reserved -

7 C0NCHS Comparator 0 negative input port selection bit

0: Selects C0N as the negative input port of comparator 0 1: Selects internal reference CMP0VRS as comparator 0 negative input port. 6 ~ 4 C0PCHS[2:0] Comparator 0 positive input port selection bit 000: Selects OP0P0 as comparator positive input port of comparator 001: Selects OP0P1 as comparator positive input port of comparator 010: Selects OP0P2 as comparator positive input port of comparator 011: Reserved 100: Selects OP1OUT as comparator positive input port of comparator 0 101: Selects OP2OUT as comparator positive input port of comparator 0 110: Selects OP3OUT as comparator positive input port of comparator 0 111: Reserved

3 C0OUT Comparator 0 output state flag bit (indicating the state after

passing through filter, read only) 0: Comparator output is low 1: Comparator output is high

2 ~ 0 C0DEB[2:0] Comparator 0 output signal filter time 000: No filter 001: Filter time constant is 0.5us 010: Filter time constant is 1us 011: Filter time constant is 2us 100: Filter time constant is 4us 101: Filter time constant is 8us 110: Filter time constant is 12us 111: Filter time constant is 16us Note 1: The above filter constant time is not exact value and is for reference only. Note 2: Filter description: the input signal is sampled by the internal clock. If the sampling result is high level, the counter is incremented by 1, and the counter result exceeds the set constant, then the filter outputs 1 and the counter is simultaneously set to filter constant*2; if the sampling result is low level, the counter is decremented by 1, and the counter result is less than the filter constant, then the filter outputs 0 and the counter is set to 0

22.5.2 Comparator 1 control register (AMOC_CMP1CON)

Offset Address: 0x0004 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved CMP1VRS[5:0] - RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 CMP 1EN CMP 1VC MP CP1 NOU TEN C1O UTE N C1IES[1:0] C1SMT[1:0] C1N CHS C1PCHS[2:0] C1O UT C1DEB[2:0] RW RW RW RW RW RW RW RW RO RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 22 Reserved - 21 ~ 16 CMP1VRS[5:0] Comparator 1 Negative terminal reference voltage selector bit xxx: (1+CMP1VRS[5:0])/ 64 *Vcmp Note: Negative terminal voltage range is 1/64~64/64

15 CMP1EN Comparator 1 enable control bit

0: Comparator is off 1: Comparator is on

14 CMP1VCMP Comparator 1 negative end terminal reference voltage source Vcmp

selection bit: 0: VDD 1: External VREF(PB14)

13 CP1NOUTEN When Internal reference source is used as the negative terminal of

comparator, whether the comparator N output to CP1N 0: No output 1: Output Note: This bit is only valid while C1NCHS = 1.

12 C1OUTEN Comparator 1 I/O output port enable

0: Disables outputting C1OUT to IO(CP1OUT) , CP1OUT is normal IO 1: Enables outputting C1OUT to IO(CP1OUT) Note: I/O output has filter function, with filter parameter being the set value of C1DEB[2:0]

11 ~ 10 C1IES[1:0] Comparator 1 interrupt mode selection bit 00: Interrupt flag is not triggered 01: Falling edge triggers, interrupt flag is triggered when comparator 2 output is from high to low 10: Rising edge triggers, interrupt flag is triggered when comparator 2 output is from low to high 11: Both edges trigger, interrupt flag is triggered when comparator 2 output is from high to low and from low to high. 9 ~ 8 C1SMT[1:0] Comparator 1 Schmitt voltage selection bit: 00: No Schmitt window feature 01: Schmidt window is 10mv 10: Schmidt window is 20mv 11: Schmidt window is 50mv

7 C1NCHS Comparator 1 negative input port selection bit

0: Selects C1N as the negative input port of comparator 1 1: Selects internal reference CMP1VRS as comparator 1 negative input port, CP1N is used for GPIO. Note: If the internal VREF is used, the reference source should be turned on 100us in advance, which means the register [AGCON: VREFEN] bit is set to 6 ~ 4 C1PCHS[2:0] Comparator 1 positive input port selection bit 000: Selects C1P0 as comparator positive input port of comparator 1 001: Selects C1P1 as comparator positive input port of comparator 1 010: Selects C1P2 as comparator positive input port of comparator 1 011: Selects OP1OUT as comparator positive input port of comparator 1 100: Selects OP2OUT as comparator positive input port of comparator 1 101: Selects OP3OUT as comparator positive input port of comparator 1 11x: Reserved

3 C1OUT Comparator 1 output state flag bit (indicating the state after passing

through filter, read only) 0: Comparator output is low 1: Comparator output is high 2 ~ 0 C1DEB[2:0] Comparator 1 output signal filter time 000: No filter 001: Filter time constant is 0.5us 010: Filter time constant is 1us 011: Filter time constant is 2us 100: Filter time constant is 4us 101: Filter time constant is 8us 110: Filter time constant is 12us 111: Filter time constant is 16us Note 1: The above filter constant time is not exact value and is for reference only. Note 2: Filter description: the input signal is sampled by the internal clock. If the sampling result is high level, the counter is incremented by 1, and the counter result exceeds the set constant, then the filter outputs 1 and the counter is simultaneously set to filter constant*2; if the sampling result is low level, the counter is decremented by 1, and the counter result is less than the filter constant, then the filter outputs 0 and the counter is set to 0 simultaneously.

22.5.3 Comparator interrupt flag and clear register (AMOC_CMPINTF)

Offset Address: 0x0008 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved C1IF C C0IF C - WO WO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Reserved C1IF C0IF - RO RO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 18 Reserved -

17 C1IFC Comparator 1 output rising edge interrupt flag bit clear bit

0: Invalid 1: Clear

16 C0IFC Comparator 0 output rising edge interrupt flag bit clear bit

0: Invalid 1: Clear 15 ~ 2 Reserved -

1 C1IF Comparator 1 output rising edge interrupt flag (after passing through the

filter) 0: Comparator 1 output does not generate any interrupt 1: Comparator 1 output generates some interrupt request

0 C0IF Comparator 0 output rising edge interrupt flag (after passing through the

filter) 0: Comparator 0 output does not generate any interrupt 1: Comparator 0 output generates some interrupt request

22.5.4 Amplifier control register (AMOC_OPCON)

Offset Address: 0x000C Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Reserved OP0 GEN OP0GSEL[2:0] OP3 EN OP2 EN OP1 EN OP0 EN - RW RW RW RW RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 8 Reserved -

7 OP0GEN The internal gain enabling bit of the OP0P0 pin:

0: Disable 1: Enable

6 ~ 4 OP0GSEL[2:0] Op Amp 0 gain factor selection: 000: X1 001: X4 010: X6 011: X8 100: X12 101: X16 110: X24 111: X32

3 OP3EN Operational amplifier 3 enable control bit

0: Operational amplifier 3 is off 1: Operational amplifier 3 is turned on Note: When the operational amplifier is turned on, the corresponding input and output pins I/O must be configured as analog pins in advance!

2 OP2EN Operational amplifier 2 enable control bit

0: Operational amplifier 2 is off 1: Operational amplifier 2 is turned on Note: When the operational amplifier is turned on, the corresponding input and output pins I/O must be configured as analog pins in advance!

1 OP1EN Operational amplifier 1 enable control bit

0: Operational amplifier 1 is off 1: Operational amplifier 1 is turned on Note: When the operational amplifier is turned on, the corresponding input and output pins I/O must be configured as analog pins in advance!

0 OP0EN Operational amplifier 0 enable control bit

0: Operational amplifier 0 is off 1: Operational amplifier 0 is turned on Note1: When the operational amplifier is turned on, the corresponding input and output pins I/O must be configured as analog pins in advance! Note2: if OP0EN=1, OP0 must be used as OP; just when OP0EN = 0, OP0 can be used as Comparator.

1. Serial Communication Interface(UART/SPI/TWI/FIFO)

23.1 Universal Asynchronous Receiver/Transmitter (UART)

23.1.1 Introduction

Universal asynchronous receiver/transmitter, also known as UART, is a kind of asynchronous transceiver.

23.1.2 Main Feature

 Internal baud rate generator  Configurable stop bits - support for 1 or 2 stop bits Full duplex, asynchronous communications Enhancements include frame error detection and automatic address recognition  Parity checking  Baud rate detection  Supports hardware generation and detection of LIN bus synchronization discontinuity  Each UART configurable FIFO and support based on FIFO data transceiver

23.1.3 Function Description

23.1.3.1 UART Working Modes

UART has four working modes. The user must first initialize UARTx_CR, select mode, baud rate and stop bit before communicating. In all four modes, any write operation with UARTx_TDR as the target register will initiate a transfer after TEN is enabled. In mode 0, the reception is initiated by conditions RI = 0 and REN = 1. This generates a clock signal on the TXD pin and then shifts in 8-bit data on the RXD pin. In other modes, the reception is initiated by the starting bit of input (if RI = 0 and REN = 1). External transmitter communication begins with the transmission of the starting bit. Table23-1 UART Working Mode List SM1 SM0 Mode Type Baud rate Frame l th Starting bit Stop bit 9th bit 0 0 0 Synchronous half duplex PCLK/(48 or 12) 8-bit None None None 0 1 1 Asynchronous full duplex Overflow rate of internal baud rate generator/16 10-bit (or 11) 1 1 (or 2) None 1 0 2 Asynchronous full duplex PCLK/(256 or 128) 11-bit (or 12) 1 1 (or 2) 0, 1 1 1 3 Asynchronous full duplex Overflow rate of internal baud rate generator/16 11-bit (or 12) 1 1 (or 2) 0, 1 Mode 0: Synchronous, half duplex communication Mode 0 supports synchronous communication with external devices. The serial data is received and transmitted on the RXD pin, and the shift clock is sent by the TXD pin. SH33F2801 provides shift clock on the TXD pin, so this mode is a half duplex mode of serial communication. In this mode, 8 bits are transmitted and received per frame, and the LSB is received or transmitted first. The baud rate is programmable to either 1/12 or 1/4 of the system clock that is set by SMOD0 bit @UARTx_CR. When the SMOD0 bit is set to 0, the serial port operates at 1/48 of the PCLK clock. When the SMOD0 bit is set to 1, the serial port operates with 1/12 of the PCLK clock. The block diagram of the function block is shown below. Data is shifted in and out of the serial port through the RXD pin, and the shift clock is output by the TXD pin.

÷ ÷ PCLK SM2 TDR TC Figure23-1 Mode 0 Function Block Diagram After TEN@UARTx_CR is enabled, the UARTx_TDR register is empty and write operation can be performed. Write data and in the next PCLK clock TX control block starts transmitting. Data conversion occurs on the falling edge of the shift clock, and the contents of the shift register are shifted from left to right successively, with the empty bits being set to 0. When all 8 bits in the shift register are transmitted, the TX control block stops transmitting and then shifts the data from the UARTx_TDR register to the SHIFT register on the rising edge of the next PCLK clock. At this time, UARTx_TDR is empty again; TI @UARTx_FR is set by hardware. TI is the transmit interrupt flag, which reflects the state of the transmit register in real time. If being set, it indicates that the transmit register is empty. Since UART transmission has level one buffer, the first transmission can write two bytes of transmitted data successively. Figure23-2 Mode 0 Transmit Timing Diagram Write to TDR D0 D1 D2 D3 D4 D5 D6 D7 RXD TI Send Timing of Mode 0 TXD

Reception is initiated by the condition REN@UARTx_CR = 1 and RI@UARTx_FR = 0. Reception is initiated during the next PCLK clock, data is latched on the rising edge of the shift clock, and the contents of the receive conversion register are shifted to the left successively. When all 8 bits of data have been shifted to the shift register, RX control stops receiving and is set on the rising edge of the next PCLK clock until RDR is read by software, or RI is cleared Setting RIC to clear RI by software). RI is the receive interrupt flag, which reflects the state of the receive register in real time. If being set, the receive register is full. Since UART reception has one buffer, during the first time after reception is enabled, 2 bytes are received successively. In this case, the data in RDR needs to be taken away in time (which means the first data needs to be taken before the second data enters the RDR), otherwise the receiving process will pend and set the RXOV flag, REN needs to be re-enabled (write 0 first to turn off and then write 1 to turn on) to resume subsequent reception. Figure23-3 Mode 0 Receive Timing Diagram Mode 1: 8-bit UART, variable baud rate, asynchronous full duplex Mode 1 provides 10/11-bit full duplex asynchronous communication. The 10 bits consist of one starting bit (logic 0), 8 data bits (LSB first), and 1/2 stop bit(s) (logic 1). During reception, the 8 data bits are stored in UARTx_RDR and the stop bits are stored in RB8 @UARTx_CR. The baud rate in mode 1 is fixed at 1/16 of the internal baud rate generator overflow rate. The block diagram of the function block is shown below: SERIAL CONTROLLER TX CLOCK TX START TX SHIFT TI RI RX CLOCK LOAD RDR RX START RX SHIFT TXD PARIN LOAD CLOCK SOUT CLOCK SIN PAROUT RXD Read RDR Internal Data Bus Receive Shift Register Internal Data Bus 16÷ 16÷ 1-TO-0 DETE CTOR Write to TDR BIT DETE CTOR RDR Transmit Shift Register STOP START SAMPLE Serial Port Interrupt Baud rate Generator overflow According to BRT register TDR TC Figure23-4 Mode 1 Function Block Diagram RXD D0 D1 D2 D3 D4 D5 D6 D7 RI Receive Timing of Mode 0 TXD

After TEN@UARTx_CR is enabled, the UARTx_TDR register is empty and transmission can be performed. In fact, the transmission on the TXD pin is started from the PCLK clock after the next transition in the 16 division counter, so the bit time is synchronized with the 16 division counter. The starting bit is first shifted out on the TXD pin, followed by the 8-bit data bit. After data of all 8 bits in the transmit shift register has been transmitted, the stop bits are shifted out on the TXD pin and the TI flag is set at the end of the transmission of the stop bit. Figure23-5 Mode 1 Transmit Timing Diagram (STOP=1BIT) Reception is only allowed when REN is set. The serial port begins to receive serial data when the RXD pin detects a falling edge. To achieve this, the UART continuously samples RXD at a sampling rate of 16 times of the baud rate. When falling edge is detected, the 16 division counter is immediately reset, which helps the 16 division counter to synchronize with the serial data bits on the RXD pin. The 16 division counter divides the time of each bit into 16 states. In the 7th, 8th, and 9th states, the bit detector samples the level of the RXD pin. In order to suppress noise, the data is received only when at least 2 sample values out of the 3 state samples are the same. If the first bit received is not 0, it indicates that this is not the starting bit of a frame of data, then this bit is ignored, and the receiving circuit is reset, waiting for another falling edge on the RXD pin. If the starting bit is valid, it is shifted into the shift register and then other bits are shifted into the shift register. After 8 data bits and 1 stop shift are shifted in, the contents of the shift register are loaded into RDR and RB8 respectively, and RI is set, but the following conditions must be met: 1. RI = 0 2. UART mode without bit 9 functionality or the stop bit received = 1 If these conditions are met, then the stop bit is loaded into RB8, the 8 data bits are loaded into RDR, and RI is set. Otherwise the received frame will be lost and then continue to detect the next start bit. At the time, the receiver goes back to looking for another falling edge on the RxD pin. And the user should clear RI by software for further reception. User should read the data of RDR (or set RIC by software to clear RI), and then the next byte of data can be received normally, otherwise the newly received data in SHIFT will overwrite RDR, and RXOV error flag will be set. Figure23-6 Mode 1 Receive Timing Diagram (STOP=1BIT) Receive Timing of Mode 1 D0 D1 D2 D3 D4 D5 D6 D7 RxD Stop Start Bit Sample Shift CLK RI Write to TDR Shift CLK D0 D1 D2 D3 D4 D5 D6 D7 TxD Stop Start TI Send Timing of Mode 1

Mode 2: 9-bit UART, fixed baud rate, asynchronous full duplex This mode provides the 11/12 bits full duplex asynchronous communication. The 11 bit consists of one starting bit (logic 0), 8 data bits (LSB first), one programmable 9th data bit and a 1/2 stop bit(s) (logic 1). Mode 2 supports multiprocessor communication and hardware address recognition (see the Multiprocessor Communication part for details). At the time of data transmission, the 9th data bit (TB8@UARTx_CR) can be written 0 or 1, and the setting of this bit needs to be completed before writing in the corresponding UARTx_TDR. The 9th bit can be used as a data/address flag bit in multiprocessor communication, as well as a parity bit. When data is received, the 9th data bit is shifted into RB8 and the stop bit is not saved. If the RB8 bit is read using software, the reading needs to be done before reading the UARTx_RDR register. The baud rate is programmable to either 1/256 or 1/128 of PCLK by the SMOD@UARTx_CR bit. The block diagram of the function block is as follows: SERIAL CONTROLLER TX CLOCK TX START TX SHIFT TI RI RX CLOCK LOAD RDR RX START RX SHIFT TXD Serial Port Interrupt PARIN LOAD CLOCK SOUT CLOCK SIN PAROUT RXD Read RDR Internal Data Bus Receive Shift Register Internal Data Bus 16 16÷ 1-TO-0 DETECTOR Write to TDR BIT DETECTOR D8 RDR RB8 Transmit Shift Register STOP START SAMPLE 16÷ D8TB8 SMOD PCLK TDR TC Figure23-7 Mode 2 Function Block Diagram After TEN@UARTx_CR has been enabled, the UARTx_TDR register is empty, transmission be active, and TB8 is also loaded into the 9th bit of the transmit shift register. In fact the TXD transmission starts from the PCLK clock after the next transition in the 16 division counter, so this bit time is synchronized with the 16 division counter. The starting bit is first shifted out on the TXD pin, followed by 9 bits of data. After all 9 bits of data in the transmit conversion register have been transmitted, the stop bit is shifted out on the TXD pin and the TI flag is set at the end of the stop bit transmission. Figure23-8 Mode 2 Transmit Timing Diagram (STOP=1BIT) Write to TDR Shift CLK TI Send Timing of Mode 2 TXD D8 D0 D1 D2 D3 D4 D5 D6 D7 Start Stop

Reception is only allowed when REN is set. The serial port begins to receive serial data when the RXD pin detects a falling edge. To achieve this, the CPU continuously samples the RXD at a sampling rate of 16 times the baud rate. When falling edge is detected, the 16 division counter is immediately reset. This helps the 16 division counter to synchronize with the serial data bits on the RXD pin. The 16 division counter divides the time of each bit into 16 states. In the 7th, 8th, and 9th states, the bit detector samples the level of the RXD pin. In order to suppress noise, the data is received only when at least 2 sample values out of the 3 state samples are the same. If the first bit received is not 0, indicating that this is not the starting bit of a frame of data, then this bit is ignored, and the receiving circuit is reset, waiting for another falling edge on the RXD pin. If the start bit is valid, it is shifted into the shift register and then other bits are shifted into the shift register. After 9 data bits and 1 stop shift are shifted in, the contents of the shift register are loaded into RDR and RB8 respectively, and RI is set, but the following conditions must be met: 1. RI = 0 2. 9th bit mode is defined by user Or, SM2 = 1, the received 9th bit = 0, and the byte received by the previous byte is the address and conforms to the agreed slave address (multiprocessor communication mode) Or, parity mode (with priority higher than multiprocessor communication mode and user-defined 9th bit mode, see the Parity part for details) If these conditions are met, then the 9th bit is shifted into RB8, the 8-bit data is shifted into RDR, and RI is set. Otherwise the received frame will be lost and then continue to detect the next start bit. User should read RDR or clear RI Set RIC to clear RI by software), then the next byte of data can be received normally. Otherwise, data received in SHIFT will overwrite the untaken data in RDR. Figure23-9 Mode 2 Receive Timing Diagram (STOP=1BIT) Mode 3: 9-bit UART, variable baud rate, asynchronous full duplex Mode 3 uses the transmission protocol of mode 2 and the baud rate generation of mode 1. Shift CLK RxD Bit Sample D0 D1 D2 D3 D4 D5 D6 D7 D8 Start Stop RI Receive Timing of Mode 2

16÷ 16÷ 1-TO-0 DETE CTOR Write to TDR BIT DETE CTOR D8 RDR RB8 SAMPLE TXDPARIN LOAD CLOCK SOUT Internal Data Bus Transmit Shift Register START D8TB8 STOP Baud rate Generator overflow According to BRT register TDR TC Figure23-10 Mode 3 Function Block Diagram Description about TI, TC flags TI@UARTx_FR is the flag that the UARTx_TDR is empty. After writing data to UARTx_TDR, TI will be automatically cleared. However, it should be noted that when data is continuously transmitted, the first data is directly written to the transmit shift register, and then the second data is written to UARTx_TDR. Therefore, the TI flag will be cleared after the second data is written into UARTx_TDR. (As shown in Figure 22-11) TC@UARTx_FR is the end flag of continuous frames transmit. When sending continuous data frames, if UART TDR and SHIFT are empty at the same time, set TC, indicating that the current data sending is completed and no subsequent data sending is done. It generally means that a continuous data frame has been sent, so it is called the end of frame sending flag bit. Write TDR, or set TCC @UARTx_FR that can clear TC flag. The specific timing sequence is shown in the figure below. Note: SH33F2801 sends TC flag after the stop bit of the last byte is sent out. Figure23-11 TC Working Timing Diagram

23.1.3.2 Fine-tunable Baud Rate

UART has an internal baud rate generator, which is actually a 15-bit incremental counter. 15-bit timer \` To UARTOverflow PCLK1 According to BRT register BRT Baudrate Generator for UART SBRTEN=1 Figure23-12 Baud Rate Generator Function Block Diagram From the figure, it can be obtained that the overflow rate of the baud rate generator is: BRT PCLKrateoverflowSBRT = Therefore, the baud rate calculation formula of UART in each mode is as follows. In Mode 0, the baud rate can be programmed to be 1/48 or 1/12 of the APB clock, as determined by the SM2 bit. When SM2 is 0, the serial port operates at 1/48 of the PCLK clock. When SM2 is 1, the serial port operates at 1/12 of the PCLK clock. In mode 1 and mode 3, the baud rate can be fine-tuned with a precision of one PCLK clock. The formula is as follows: ( ) BFINESBRT PCLKBaudRate ++×= 116 For example: PCLK = 30MHz, the baud rate of 9600Hz needs to be obtained, SBRT and SFINE values are calculated as follows: 30000000/16/9600 = 195.3125 SBRT = 195 - 1 = 194 According to baud rate formula: 9600 = 30000000/(16 X 195 + BFINE) Obtains: BFINE = 5 The actual baud rate calculated via this fine-tuning method is 9598 with an error of 0.02%. In Mode 2, the baud rate is fixed at 1/256 or 1/128 of the PCLK clock, as determined by the SMOD bit @UARTx_CR. When the SMOD bit is 0, UART operates at 1/256 of the PCLK clock. When the SMOD bit is 1, UART operat es at 1/128 of the PCLK clock. ×= 2562 PCLKBaudRate SMOD

23.1.3.3 Multiprocessor Communication

Automatic (hardware) address recognition In mode 2 and mode 3, MULTIE is set (entering multiprocessor communication mode), and the UART running state is as follows: the stop bit is received, the 9th bit of RB8 is 1 (address byte flag), and the received data byte matches with the slave address of UART, UART will start receiving subsequent data bytes. Otherwise, continue to wait for the address to match. The 9th bit being 1 indicates that this byte is an address and not data. When the host wants to send a set of data to one of several slaves, the target slave address must be sent first. All slaves wait to receive the address byte. The feature of automatic address recognition is that only the slaves whose address matches can generate the interrupt flag of the subsequent received data, and the hardware completes the address comparison. A slave with a matching address can continue to receive data bytes and generate receive interrupt flags. A slave with a mismatched address is unaffected and will continue to wait to receive the address byte that matches it. The Automatic Address Recognition feature allows a master to selectively communicate with one or more slaves by invoking the Given Address. All of the slaves may be contacted by using the Broadcast address. There is a special function register UARTx_ADDR that contains the slave address (SADDR) and address mask (SAMR). The slave address is an 8-bit byte. SAMR is used to define whether the SADDR bits are valid or not. If a bit in the SAMR is 0, the corresponding bits in the SADDR are ignored. If a bit in the SAMR is set, the corresponding bits in SADDR will be used to generate the agreed address. This allows user to flexibly address multiple slaves without changing the slave address in the SADDR register. Table23-2 Automatic Address Recognition Examples Slave 1 Slave 2 SADDR 10100100 10100111 SAMR (bits being 0 are ignored) 11111010 11111001 Given address 10100x0x 10100xx1 Broadcast address (SADDR or 1111111x 11111111 The Given address for slave 1 and 2 differ in the LSB. For slave 1, it is ignore LSB, while for slave 2 LSB is 1. Therefore, when communicating only with slave 1, the host must send the address with the lowest bit of 0 (10100000). Similarly, the lowest bit of slave 1 is 0, and the lowest bit of slave 2 is ignored. Hence to communicate only with slave 2, the master has to transmit an address with bit 1 = 1 (1010 0011). If the master wishes to communicate with both slaves simultaneously, then the address must have bit 0 = 1 and bit 1 = 0. The bit 2 position is ignored for both the slaves. This allows two different addresses to select both slaves (1010 0001 and 1010 0101). The master can communicate with all the slaves simultaneously with the Broadcast Address. This address is formed from the logical OR of the SADDR and SADEN. The zeros in the result are defined as neglect. In most cases, the Broadcast Address is 0xFF; this address will be responded by all slaves. On reset, the SADDR and SADEN are initialized to 00h. The two results set Given Address and Broadcast Address to XXXXXXXX (all bits are ignored). This effectively removes the multiprocessor communications feature, since any selectivity is disabled. This ensures that the EUART will reply to any address, which it is compatible with the 80C51 microcontrollers that do not support automatic address recognition. So the user may implement multiprocessor communication by software recognition address according to the above mentioned method.

23.1.3.4 Frame Error Detection

UART has frame error detection function. After the error flag is set, it can only be cleared by writing 1 to the corresponding clear bit by software, although the subsequent received frames will not be automatically cleared if they have no error. The error flag does not trigger any interrupt, does not affect the serial port run, and is only used for software queries. Transmit collision If there is data in UARTx_TDR and the user software continues to write data to the UARTx_TDR register, the transmit collision bit TXCOL@UARTx_FR is set. If a collision occurs, the new data is ignored and cannot be written to the transmit buffer. Clearing this bit is achieved by writing 1 to TXCOLC@UARTx_FR. Receive overflow UART has RDR receiving data register and receiving shift register. When UARTx receives a byte (Data0), RI is set to 1. And before the data (Data0) in UARTx_RDR is read, the receiving shift is allowed to receive a new UARTx data (Data1). Then if there is another UARTx data (Data2), RXOV is set to 1 and the UARTx data (Data2) will be shift into the receiving shift register, so the UARTx data (Data1) is ignored. But the data of RDR is always kept. When the data in UARTx RDR is read, the data in the shift register is moved into UARTx RDR to avoid dislocation when the shift register receives a frame of complete data (including the start bit, data bit and stop bit). Therefore, if RXOV@UARTx_FR is set, it indicates that some data has been discarded, and it is uncertain how much data has been lost, which generally requires the user to re-transmit the packet. Clearing RXOV@UARTx_FR bit is achieved by writing 1 to RXOVC@UARTx_FR. Parity error If an incorrect parity bit is detected, the parity bit PE@UARTx_FR is set. Clearing this bit is achieved by writing 1 to PEC@UARTx_FR. Frame Error If an invalid (low) stop bit is detected, the frame error bit FE@UARTx_FR is set. Clearing this bit is achieved by writing 1 to FEC@UARTx_FR. Note: The TXD pin must be set to output high before sending.

23.1.3.5 Parity

Odd parity: The number of '1's in the parity bit and the transmitted data (binary representation) is odd. Even parity: The number of '1' in the parity bit and the transmitted data (binary representation) is even. When mode 0 and mode 1 are selected, there is no parity function. When mode 2 and mode 3 are selected, if the parity enable bit PCE@UARTx_CR is 1, the 9th bit TB9 will be used as the parity bit (priority is higher than the multiprocessor communication mode and the user-defined 9th bit mode). The data of this bit is generated by the shift register and automatically assigned to the 9th bit of the serial port transmission. The check mode selection is set by PS@UARTx_CR. The parity bit is automatically detected by the hardware. After transmission of each byte is completed, if a parity error occurs, the parity bit PE@UARTx_FR will be automatically set to 1. Clearing this bit is achieved by writing 1 to PEC@UARTx_FR by software.

23.1.3.6 LIN (Local Interconnect Network) Bus Mode

SH33F2801's LIN bus mode supports hardware generation and detection of synch breaks. The LIN mode is controlled by LINEN@UART_CR. In LIN mode, the TXD and RXD pins of UART are used as the LIN transmit and receive function pins. Mode 1 should be selected as UART mode. Figure23-13 LIN Bus Mode About LIN transmission, the transmitted byte is similar to normal UART. According to the LIN bus protocol, synch break (SBK@UART_CR) is sent first as the start of signal transmission on the LIN bus, then the software transmits 0x55 as the baud rate adaptive synch field data, and finally transmits the ident field to control the data communication on the bus. The data formats of the subsequent communication of host and slave are all 8-bit data (LSB), no parity bit. There is a checksum field at the end of the data frame. There are two types of checksum fields: the checksum calculated only based on the data byte is called traditional checksum, which can be used for LIN1.3 slave communication; the checksum calculated based on the data byte and identifier is called enhanced checksum, which can communicate with LIN2.0 slave. The host determines whether it has achieved its purpose based on the checksum, and then decides whether to initiate the LIN bus communication again. About LIN reception, there is synchronous interrupt detection circuit in the RXD interface of UART. When low level (BREAK CHARACTER) with length greater than 11 or 10 bits (set by SBDL@ UART_CR) is detected, and then high level (DELIMITER) with at least 1 bit is detected, this means that the synchronous interrupt detection is successful, and an LBD interrupt flag is generated. If the response interrupt enable bit LBDIE is enabled, the interrupt service routine is entered. When LBD is cleared by writing 1 to LBDC, the receive shift register and the receive buffer need to be cleared, and LINEN is turned off to receive the serial data that is subsequently shifted in. If the sync signal needs to be redetected, LINEN needs to be re-enabled.

23.1.3.7 Use FIFO to send and receive

FIFO module is added to UART mainly to reduce the impact of UART on CPU and avoid CPU being occupied by low-speed peripheral communication equipment. The FIFO function of UART is controlled by the switch. When the function is turned off, UART is the standard module. UART FIFO Function Sign Type Reset Value Description UARXFIFO W/R 0 UART RX FIFO function control bit 0: Standard UART 1: UART with Rx FIFO UATXFIFO W/R 0 UART TX FIFO function control bit 0: Standard UART 1: UART with Tx FIFO The mapping between UART and FIFO is configurable, and each FIFO can be mapped to any one of multiple UART. There is no error checking for multiple FIFO mapping to the same UART on the hardware, which needs to be avoided on the software. For the mapping between UART and FIFO, refer to the "FIFO Controller" section. When FIFO is not enabled, the UART is a standard serial transceiver with 1-byte-deep send and receive buffer (TDR/RDR). It’s an original standard SPI. After FIFO is enabled, TX FIFO and RX FIFO replace the TDR and RDR of the original UART, but some control bits and flag bits of the original UART are still valid. UART TX FIFO For TX FIFO, the MCU fills TX FIFO buffer, and at the same time, the SPI takes the data from TX FIFO. When TX FIFO counter gradually decreases and is less than the specified Trigger point, the trigger marker bit (TXTRIGF) will be set. The write width of TX FIFO is optional 8/16/32 bit. When 8-bit wide mode is selected, FIFO counter adds 1; when 16-bit wide mode is selected, FIFO counter adds 2 every time; when 32-bit wide mode is selected, FIFO counter adds 4 every time, that is, the basic counting unit of TX FIFO Counter is byte. The read bit width of TX FIFO is fixed to 8-bit, that is, the UART shift register fetches 1 byte from TX FIFO each time. If 9-bit UART mode is selected, the original control logic generates the 9th bit, independent of TX FIFO. For example, the 9-bit parity mode generates parity bits directly from TX SHIFT and adds them to the end of the data to send. If you are in 9-bit multi-machine communication mode or 9-bit custom mode, the 9-bit first writes TB8, and then the UART controller automatically adds it to the end of the data to send. UART RX FIFO For RX FIFO, the UART fills RX FIFO, and RX FIFO Counter gradually increases. When it is larger than the specified Trigger Level, the Trigger marker bit (RXTRIGF) will be set. RX FIFO bit width is optional 8/16/32 bit. When 8-bit read out is selected, FIFO Counter decreases by 1; when 16-bit wide mode is selected, FIFO counter decreases by 2 every time; when 32-bit wide mode is selected, FIFO counter decreases by 4 every time, that is, the basic counting unit of RX FIFO Counter is byte. For RX FIFO, there are two modes, 8bits mode and (8+3)bits mode, which can be set by RXMODE@FIFOx_CR. In the 8bits mode, store 8bits data into RX FIFO, the counter of FIFO adds 1. When the CPU reads RX FIFO, it only needs to set 8-bit read bit width.

When selecting (8+3)bits mode, UART stores 8 bits data into the buffer of FIFO and 3 bits high into 9 bits and two error flags, as shown in the table below: (8+3)bits RX FIFO Structure RX FIFO Bit Function

10 Frame Error Flag

9 Parity Error Flag

8 Ninth Bit(Parity Bit/ Multi-machine communication Bit/Self define Bit)

When RX FIFO enables, the three control state bits - RB8, PE, and FE - are still valid. PE and FE Follow to receive status updates based on UART, but not based on the results read from FIFO. But RB8 is different, each time FIFO data is updated, RB8 will also be updated accordingly, that is, RB8 time reflects the current operation of the data situation. Note: Both PE and FE are set by hardware and cleared by software, so if the CPU does not handle these two flags, the error sign will remain Reserved. In the (8+3)bits mode, in order to read out all the (8+3)bits data, RXMODE must be set and the read bit width of RX FIFO must be 16bits. Bit15-Bit11 are zero padding and FIFO Counter decreases by 1. However, if the read Bit width is set to 8bits, only the first 8bits of data will be read, and the last 3 bits will be discarded, and the FIFO Counter decreases by 1. Note: In addition to determining how many bits of data UART writes to FIFO, the RXMODE control Bit also determines the counting step written from UART to FIFO in (8+3)bits mode, and the counting step in (8+3)bits mode is 11 bits. Therefore, the Counter count only adds 1.

The Description of UART FIFO After FIFO is enabled, some function flags and some error flags will be affected in the interface interaction between FIFO and UART. Please refer to the table below. Table23-3 The difference of UART function and error flags when FIFO is on or off Function FIFO is off FIFO is on Transfer buffer(TDR) Transfer buffer(TDR) Invalid Receive buffer(RDR) Receive buffer(RDR) Invalid Transmission interrupt flag (TI) The initial state is 1. If TDR is empty, TI is set; if TDR is full, TI is cleared. Writing a Non-zero data to TDR can clear TI; if the data of TDR is shift to transmission shift register, TI is set. Invalid, but TXTRIG has the same function as SPTI. When TX FIFO counter is reduced to trigger level, the TXTRIGF flag is set. Setting TXTRIGFC can clear TXTRIG. Receive interrupt flag (RI) The initial state is 0. The interrupt RI is generated after the RDR buffers complete the transfer of one byte data (the receive register is full when receiving) Setting RIC can clear RI. Invalid, but RXTRIG has the same function as SPRI. When RX FIFO counter is increased to trigger level, the RXTRIGF flag is set. Setting RXTRIGFC can clear RXTRIG. Transmission completion mark (TC) The initial state is 1. When sending is complete, TDR is null and all bits in the shift Bit register has been shift. Setting TCC or writing TDR can clear TC. Valid When sending is complete, FIFO is null and all bits in the shift Bit register has been shift. Setting TCC or writing FIFO can clear TC. Transmission conflict flag(TXCOL) The data of TDR and the shift TDR are full when the user continues to write TDR, TXCOL will be set. New write data will be ignored if a conflict occurs. Setting TXCOLC can clear TXCOL. Invalid FIFO does not define similar functionality. It is generally believed that sending is controlled by software and can be avoided completely by program control. Receive overflow flag (RXOV) If the data of RDR is not read when the new data is received to write RDR, RXOV is set. The new data will be ignored if a conflict occurs. Setting RXOVC can clear RXOV. Invalid, but OVF has the same function as RXOV. RX FIFO is full, but there is a new received data, then the OVF flag is set and the new data is ignored in order to keep the FIFO the same. Setting OVFC can clear RXOV. Parity Error (PE) Set 1 when Parity Error occurs. Setting PEC can clear PE. Valid and the function is the same with standard UART. Frame Error (FE) Set 1 when invalid (low) stop bit is detected. Setting FEC can clear FE. Valid and the function is the same with standard UART.

23.1.3.8 Interrupt Control

The UART interrupts (TI, RI) are generated when UARTx_TDR is empty and UARTx_RDR is full. Note: When TEN is not enabled, and TIE is enabled, interrupt will be triggered to move the data to the transmit buffer, but the data will be sent after TEN is enabled. When a frame containing data is transmitted, and TI=1, the TC bit is set to 1 by hardware. The LBD interrupt occurs when the LIN bus function is enabled and is sent when break signal is detected on RXD. LBD LBDIE TC TCIE TI TIE RI RIE UART INTERRUPT Figure23-14 Interrupt Control Diagram When FIFO turns on, TI and RI interrupt sources are invalid because TDR and RDR are replaced, while TC and LDB interrupt sources are still valid. For interruption of FIFO, refer to the FIFO Controller section.

23.1.4 UART Register

UART Module Register List (Base Address: 0x4000 1800) Address Register Name Description 0x4000 1800 FR UART interrupt flag register 0x4000 1808 TDR UART transmit data register 0x4000 180C RDR UART receive data register 0x4000 1810 ADDR UART address configure register 0x4000 1814 BRT UART baud rate configure register 0x4000 1818 CR UART control register

23.1.4.1 UART interrupt flag register (UARTx_FR)

Offset Address: 0x0000 Reset Value: 0x0000 0006 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved LBD C PEC FEC RXO VC TXC OLC TCC Rese rved RIC - WO WO WO WO WO WO - WO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Reserved LBD PE FE RXO V TXC OL TC TI RI - RO RO RO RO RO RO RO RO 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 Bit Sign Description 31 ~ 24 Reserved -

23 LBDC LIN synchronous interval interrupt flag clear bit

0: No operation 1: Clears LBD

22 PEC UART parity error flag clear bit

0: No operation 1: Clears PE

21 FEC UART frame error flag clear bit

0: No operation 1: Clears FE

20 RXOVC UART receive overflow flag clear bit

0: No operation 1: Clears RXOV

19 TXCOLC UART transmit collision flag clear bit

0: No operation 1: Clears TXCOL

18 TCC UART all one frame data transmitting completion flag clear bit

0: No operation 1: Clears TC Note: TC is cleared via writing 1 to TCC. It can also be cleared via the operation sequence of first reading FR and then writing TDR.

16 RIC UART one byte data receive interrupt flag clear bit

0: No operation 1: Clears RI Note: RI is cleared via writing 1 to RIC. It can also be cleared via the read operation to RDR. 15 ~ 8 Reserved -

7 LBD LIN synchronous interval interrupt flag bit

0: Synchronous interval interrupt signal is not received 1: Synchronous interval interrupt signal is received Cleared via writing LBDC

6 PE UART parity error flag bit

0: Parity is right 1: Parity has error, and is set by hardware Note: Cleared via writing 1 to PEC

5 FE UART frame error flag bit

0: No frame error 1: Frame error occurs, set by hardware Note: Cleared via writing 1 to FEC

4 RXOV UART receive overflow flag bit

0: No receive overflow 1: Receive overflow occurs, set by hardware Note: Cleared via writing 1 to RXOVC

3 TXCOL UART transmit collision flag bit

0: No transmit collision 1: Transmit collision occurs, set by hardware Note: cleared via writing 1 to TXCOLC

2 TC UART all one frame data transmitting completion flag bit

0: All one frame data is being transmitted, no set 1: All one frame data transmitting is completed, set by hardware Note: TC is cleared via writing 1 to TCC. It can also be cleared via the operation sequence of writing TDR.

1 TI UART one byte data transmit interrupt flag bit

0: One byte data is being transmitted, no set 1: One byte data transmitting is completed, set by hardware Note: TI can only be cleared via write operation to TDR.

0 RI UART one byte data receive interrupt flag bit

0: One byte data is being received, no set 1: One byte data receiving is completed, set by hardware Note: RI is cleared via writing 1 to RIC. It can also be cleared via read operation to RDR.

23.1.4.2 UART transmit data register (UARTx_TDR)

Offset Address: 0x0008 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 FIFOTDH[31:9] RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 FIFOTDH[31:9] TB8 TDR[7:0] RW RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 9 FIFOTDH[31:9] UART FIFO transmit data register (Just be valid while FIFO is enabled)

8 TB8 The 9th bit of UART mode2/3

(Be used as FIFOTDH[8] while FIFO is enabled) 7 ~ 0 TDR[7:0] UART transmit data register (Be used as FIFOTDH[7:0] while FIFO is enabled)

23.1.4.3 UART receive data register (UARTx_RDR)

Offset Address: 0x000C Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 FIFORDH[31:9] RO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 FIFORDH[31:9] RB8 RDR[7:0] RO RO RO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 9 FIFORDH[31:9] UART FIFO receive data register FIFORDH[31:9] (Just be valid while FIFO is enabled)

8 RB8 The 9th bit of UART mode2/3

(Be used as FIFORDH[8] while FIFO is enabled) 7 ~ 0 RDR[7:0] UART receive data register (Be used as FIFORDH[7:0] while FIFO is enabled)

23.1.4.4 UART address configure register (UARTx_ADDR)

Offset Address: 0x0010 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 SMAR[7:0] SADDR[7:0] RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

31 ~ 16 Reserved - 15 ~ 8 SMAR[7:0] Bit mask register, which determines which bit of SADDR will be detected 7 ~ 0 SADDR[7:0] UART hardware address

23.1.4.5 UART baud rate configure register (UARTx_BRT)

Offset Address: 0x0014 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved BFINE[3:0] - RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Rese rved SBRT[14:0] - RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 20 Reserved - 19 ~ 16 BFINE[3:0] Baud rate generator fine-tuning data 14 ~ 0 SBRT[14:0] Baud rate generator adjusting data

23.1.4.6 UART control register (UARTx_CR)

Offset Address: 0x0018 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved UAT XFIF O UAR XFIF O Rese rved FER TNE G RNE G Rese rved Rese rved TEN REN LINE N - RW RW - RW RW RW - - RW RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 SBK SM[1:0] MULTIE[1:0] PS Rese rved SMO LBD L LBDI E TCIE TIE RIE SMO SBR TEN STO P RW RW RW RW - RW RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 27 Reserved -

26 UATXFIFO UART TX FIFO Enable Bit

0: Standard UART 1: UART with TX FIFO

25 UARXFIFO UART RX FIFO Enable Bit

0: Standard UART 1: UART with RX FIFO

24 Reserved -

23 FER Frame error receives allowed bits

0: Forbid stop bit confirmation check, any stop bit will set RI 1: Stop bit confirmation checks are allowed. Only a valid stop bit can set the RI

22 TNEG UART Send polarity control bit

0: Without reverse 1: Reverse

21 RNEG UART Receiving polarity control Bit

0: Without reverse 1: Reverse 20 ~ 19 Reserved -

18 TEN UART transmit function enable bit

0: Transmit function is disabled 1: Transmit function is enabled

17 REN UART receive function enable bit

0: Receive function is disabled 1: Receive function is enabled

16 LINEN LIN mode function enable bit

0: LIN mode is disabled 1: LIN mode is enabled

15 SBK LIN synchronous interval enable bit

0: Synchronous interval is not transmitted 1: Synchronous interval is transmitted, cleared automatically after the transmitting is completed 14 ~ 13 SM[1:0] UART serial mode control bit 00: Mode 0, synchronous mode, fixed baud rate 01: Mode 1, 8-bit asynchronous mode, variable baud rate 10: Mode 2, 9-bit asynchronous mode, fixed baud rate 11: Mode 3, 9-bit asynchronous mode, variable baud rate 12 ~ 11 MULTIE[1:0] The 9th bit function selection 00: Software customization 01: Multi - machine communication flag bit 1x: Parity check bit

10 PS Parity selection bit

0: Odd parity 1: Even parity

8 SMOD0 Mode 0 Baud rate control bit

0: In mode 0, the baud rate is 1/48 of the PCLK clock. 1: In mode 0, the baud rate is 1/12 of the PCLK clock.

7 LBDL Synchronous interval detection threshold length

0: Low level length is greater than 10 bit low level 1: Low level length is greater than 11 bit low level

6 LBDIE LIN break separator interrupt enable bit

0: LIN break separator interrupt function is disabled 1: LIN break separator interrupt function is enabled

5 TCIE All data transmit completion interrupt enable bit

0: Data transmit completion flag bit TC triggering interrupt function is disabled 1: Data transmit completion flag bit TC triggering interrupt function is enabled

4 TIE Single byte transmit interrupt enable bit

0: Transmit interrupt flag bit TI triggering interrupt is disabled 1: Transmit interrupt flag bit TI triggering interrupt is enabled

3 RIE Single byte receive interrupt enable bit

0: Receive interrupt flag bit RI triggering interrupt is disabled 1: Receive interrupt flag bit RI triggering interrupt is enabled

2 SMOD2 UART mode 2 baud rate control bit

0: In mode 2, baud rate is 1/256 of PCLK clock 1: In mode 2, baud rate is 1/128 of PCLK clock

1 SBRTEN UART baud rate generator enable control bit

0: Baud rate generator is disabled 1: Baud rate generator is enabled

0 STOP Stop bit number selection bit

0: 1 stop bit 1: 2 stop bits

23.2 Serial Peripheral Interface (SPI)

23.2.1 Introduction

The serial peripheral interface (SPI) is a kind of high-speed serial communication interface that allows MCU to perform full duplex, synchronous serial communication with peripherals (including other MCUs). The following figure shows a typical SPI bus network consisting of one master device and several slave peripherals. The master device connects all slave devices through three wires. The master device controls 4 parallel ports of the slave device /SS pin to select one of the slave devices for communication. MISO MOSI SCK SS Master VDD Port0.0 Port0.1 Port0.2 Port0.3 MISO MOSI SCK SS Slave MISO MOSI SCK SS Slave MISO MOSI SCK SS Slave MISO MOSI SCK SS Slave Figure23-15 SPI Bus Network Diagram

23.2.2 Main Features

 Full duplex, three-wire synchronous transmitting  Master & slave operation  8 programmable master clock frequencies  Serial clock with programmable polar phase  Optional data word width is 8, 16 and 32  Master mode fault error flag with MCU interrupt  Write collision flag protection  Can select LSB or MSB transmitting  configurable FIFO, support data transceiver based on FIFO

23.2.3 Function Description

23.2.3.1 Signal Description

 Main output slave input (MOSI) This signal connects the master device and the slave device. Data is serially transferred from the master device to the slave device through MOSI, with the master device outputting and the slave device inputting.  Master input slave output (MISO) This signal connects the slave device and the master device. Data is serially transferred from the slave device to the master device through MISO, with the slave device outputting, and the master device inputting. When SPI is configured as slave device not being selected (/SS pin is high level), MISO pin of the slave device is in high-resistance state.  SPI serial clock (SCK) The SCK signal is used to control the synchronous movement of input and output data on MOSI and MISO lines. One byte is transferred every 8 clock period on the wire. If the slave device is not selected (/SS pin is high), the SCK signal is ignored by this slave device.  Slave device select pin (/SS) Each slave peripheral is selected by a slave select pin (/SS pin), and when the pin signal is low level, indicating that this slave device is selected. The master device can select each slave device by controlling the port level connected to the slave /SS pin by software. Obviously, only one master device can drive the communication network. In order to prevent MISO bus collision, only one slave device is allowed to communicate with the master device at the same time. In master device mode, the /SS pin state is associated with the MODF flag bit in the SPI flag register SPIx_FR to prevent multiple masters from driving MOSI and SCK.

The /SS pin can be used as a normal port or other functions in the following cases: (1) The device is configured as a master device and the SSDIS bit in the SPIx_CR register of the SPI control register is set to 1. This configuration only exists when there is only one master device in the communication network, so the MODF flag bit in the SPI status register SPSTA will not be set to 1. (2) The device is configured as a slave device and the CPHA bit and the SSDIS bit of the SPI control register SPIx_CR are set to 1. This configuration exists in a communication network with only one master device and one slave device. Therefore, the device is always selected, and the master device does not need to control the /SS pin of the slave device to select it as the communication destination. Note: When CPHA = 0, SS ——— pin generates falling edge, indicating transmitting is initiated.

23.2.3.2 Baud Rate

In master mode, the SPI baud rate has eight selectable frequencies, which are 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024 divisions of the internal clock, which can be selected by setting the SPR[3:0] bit of the SPIx_CR register.

23.2.3.3 Principle Description

The detailed structure of the SPI module is shown in the following figure. Internal Bus Clock Divider /128 /16 /32 /64 Clock Select Clock Logic SPI Control DIR MSTR CPHA CPOL SSDIS SPR2 SPR1 SPR0 SPEN SPIF MODF WCOL RXOV - - - SPST A Pin Control Logic MOSI MISO SCK SS M S FCLK PERIPH Recieve Data Register SPI Interrupt Request 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Recieve Register Transmit Register SPI_TDR & SPI_RDR 8-bit Bus 1-bit Signal /256 /512 /1024 Figure23-16 SPI Module Block Diagram

23.2.3.4 Working Mode

SPI can be configured as one mode from the master mode or the slave mode. The configuration and initialization of the SPI module is done by setting the SPIx_CR register (it is recommended to configure each control mode bit first, and then enable SPEN@SPIx_CR). After the configuration is complete, data transfer is done by setting SPIx_CR, SPIx_TDR, SPIx_RDR (serial peripheral data register). During SPI communication, data is synchronously and serially shifted in and out. The serial clock line (SCK) keeps the movement and sampling of data on the two serial data lines (MOSI and MISO) synchronized. The slave device select line (/SS) can independently select the SPI slave device; if the slave device is not selected, it cannot participate in the activity on the SPI bus. When the SPI master transmits data to the slave via MOSI wire, the slave device transmits data to the master device via MISO wire in response, which enables simultaneous full duplex transfer of data transmitting and receiving at the same clock. Write operation is performed to the SPI data transmit register SPIx_TDR. When the shift register is empty, the transmit shift register will be written in. When there is data in the shift register, the transmit buffer SPIx_TDR will be written in. Reading the SPIx_RDR register will get the data in the receive buffer. Master MCU 8-bit Shift Register SPI Clock Generator MISO MOSI SCK SS VDD MISO MOSI SCK SS VSS Slave MCU 8-bit Shift Register Figure23-17 Full Duplex Master-slave Interconnection Diagram (CPHA=1) Master mode (1) Mode start-up The SPI master device controls the start-up of all data transfers on the SPI bus. When the MSTR bit in the SPIx_CR register is set to 1, SPI is operating in master mode and only one master device can initiate the transfer. (2) Transmit In SPI master mode, a byte of data is written to the SPI data register SPIx_TDR. If the transmit shift register is empty, the data will be written in the transmit shift buffer. If the transmit shift register is not empty, the data will be placed in the transmit buffer SPIx_TDR. When the transmit shift register has completed transmitting, the data is automatically moved from buffer SPIx_TDR to the shift register and SPTI interrupt is generated. If data is written to SPIx_TDR when the transmit buffer is full, the master SPI generates a WCOL signal to indicate that writing is too fast. However, the data in the transmit buffer and the transmit shift register is not affected and the transmitting is not interrupted. In addition, if the transmit shift register is not empty, the master device immediately shifts the data in the transmit shift register serially to the MOSI wire according to the SPI clock frequency on SCK. The SPTI bit in the SPIx_FR register is set to 1 when the transmit buffer SPIx_TDR is empty. If the SPTIE interrupt is enabled, an interrupt will be generated when the SPTI bit is set to 1. SPTI@SPIx_FR will be automatically cleared after SPIx_TDR is filled with data. (3) Receive When the master device transmits data to the slave device through the MOSI wire, the corresponding slave device also transmits the contents of its transmit shift register to the receive shift register of the master device through the MISO wire, thereby achieving full duplex operation. The data received from the slave device is stored in the receive shift register of the master device in the transfer direction of MSB or LSB priority. When a byte of data is completely shifted into the receive register, the data is automatically shifted into SPIx_RDR and SPRI interrupt is generated. The processor can obtain this data by reading the SPIx_RDR register. The receive interrupt flag bit SPRI is set to 1 when SPIx_RDR is full. When SPIx_RDR has its data read out and is empty, SPRI will be automatically cleared. If an overrun occurs (the received data is not taken away in time, SPIx_RDR and the receive shift register still have data, then attempt to start the next receiving), the RXOV bit is set to 1, indicating that data overrun occurs, and the receive shift register keeps its original data and the SPRI bit is set to 1, so that the SPI master device will not receive any data until the SPRI bit is cleared.

(1) Mode start-up When the MSTR bit in the SPIx_CR register is cleared, the SPI is operating in slave mode. The /SS pin of the slave device must be deasserted before data transfer and must be kept low until one byte of data has been transferred. (2) Transmit and Receive In the slave mode, the data is shifted in through the MOSI pin and out through the MISO pin according to the SCK signal controlled by the master device. A bit counter records the number of edges of SCK. When the receiving shift register shifts in 8-bit data (one byte), the transmit shift register starts to shift out 8-bit data (one byte). Data can be obtained by reading the SPIx_RDR register. If the SPRIE interrupt is enabled, an interrupt will be generated when SPRI is set to 1. The SPI slave device cannot initiate data transfer, so the SPI slave device must write the data to be transferred to the transmit register SPIx_TDR before the master device starts a new data transfer (when only one data is written in, it is directly written in the transmit shift register, and when two data is written in, it is stored in the transmit shift register and the transmit buffer SPIx_TDR, respectively). If the slave device does not write in data before the first start of transmitting, the slave device will transfer "0x00" bytes to the master device. If there is data in the transmit buffer SPIx_TDR when writing SPIx_TDR, the WCOL bit of the SPI slave device is set to 1 to indicate write SPIx_TDR collision. However, the data in the transmit buffer and the transmit shift register is not affected and the transfer is not interrupted.

23.2.3.5 Transfer Form

By setting the CPOL bit and the CPHA bit of the SPIx_CR register via software, user can select the four combinations of SPI clock polarity and phase. The CPOL bit defines the polarity of the clock, which means the level state at idle, and it has little effect on the SPI transmitting format. The CPHA bit defines the phase of the clock, which defines the edge of the clock that allows the data sampling shift. In the two devices of master-slave communication, the clock polarity phase settings should be the same. SPIEN (Internal) SCK (CPOL=0) SCK (CPOL=1) MOSI (from Master) bit6MSB bit5 bit4 bit3 bit2 bit1 LSB MISO (fr om Sl ave) bit6MSB bit5 bit4 bit3 bit2 bit1 LSB SS (to Slave) SCK Cycle Number 1 2 3 4 5 6 7 8 Capture Point Figure23-18 Data Transfer Form (CPHA = 0) Diagram If CPHA = 0, the first edge of SCK captures data, the slave must prepare the data before the first edge of SCK, so in slave mode, the falling edge slave device of the /SS pin starts transmitting data. The /SS pin must be pulled high after finishing transmitting one byte each time, and reset to low level before the next byte is transmitted, so when CPHA = 0, the SSDIS masking function has no effect. In addition, for this mode, the SPI slave mode has also added the SPSFF@SPIx_CR control bit. After the control bit is set, the first byte data also needs to be loaded by the falling edge of the /SS pin. From the second byte on, data begins to be loaded using the last CLK edge of the previous byte to achieve continuous transmitting.

SPIEN (Internal) SCK (CPOL=0) SCK (CPOL=1) MOSI (from Master) bit6MSB bit5 bit4 bit3 bit2 bit1 LSB MISO (fr om Sl ave) SCK Cycle Number 1 2 3 4 5 6 7 8 Capture Point bit6MSB bit5 bit4 bit3 bit2 bit1 LSB (to Slave)SS Figure23-19 Data Transfer Form (CPHA = 1) Diagram If CPHA = 1, the master device outputs data to the MOSI wire on the first edge of SCK, and the slave device takes the first edge of SCK as the start transmitting signal. User must complete the write operation on SPIx_TDR before the second edge of the first SCK. The /SS pin always keeps at low level during the transfer of each byte of data. This form of data transfer is the preferred form of communication between a master device and a slave device. Byte1 Byte2 Byte3MISO/MOSI Master SS Slave SS (CPHA = 0) Slave SS (CPHA = 1) Figure23-20 CPHA/NSS Timing Diagram Note: When SPI is used as slave mode and the CPOL bit of the SPIx_CR register is cleared, the SCK port must turn on the pull-up resistor before data transfer.

23.2.3.6 Data Word 8-bit, 16-bit Configurable

The data word length for a single transfer can be configured as 8-bit or 16-bit via the SPDATL bit in the SPIx_CR register. When using 16-bit word length, both the shift register and the buffer register are expanded to 16-bit mode, writing and reading to both SPIx_TDR and SPIx_RDR are 16-bit operations. The timing diagram is as follows: SPEN (Internal) SCK (CPOL=0) SCK (CPOL=1) MOSI (from Master) bit14MSB ... bit4 bit3 bit2 bit1 LSB MISO (from Slave) bit14MSB ... bit4 bit3 bit2 bit1 LSB SS (to Slave) SCK Cycle Number 1 2 ... 12 13 14 15 16 Capture Point Data Transfer Form (CPHA = 0) SPEN (Internal) SCK (CPOL=0) SCK (CPOL=1) MOSI (from Master) bit14MSB ... bit4 bit3 bit2 bit1 LSB MISO (fr om Sl ave) SCK Cycle Number 1 2 ... 12 13 14 15 16 Capture Point bit14MSB ... bit4 bit3 bit2 bit1 LSB (to Slave)SS Data Transfer Form (CPHA = 0)

23.2.3.7 SPSTA State Exception Case

The MODF, WCOL and RXOV flags in the SPIx_FR register indicate error cases in SPI communication: (1) Mode Fault (MODF) The mode fault error in SPI master mode indicates that the level state on the /SS pin is inconsistent with the actual device mode. After the MODF bit in the SPIx_FR register is set to 1, it indicates that the problem of multi-master collision exists in the system control. In this case, the SPI system is affected as follows: The SPI receive/error CPU interrupt request is generated. In the interrupt, the software needs to complete the following operations: disable SPI, switch to the slave mode, and can re-enable the SPI as required. When the /SS pin disable bit (SSDIS) in the SPIx_CR register is cleared and the /SS pin signal is low, the MODF flag is set to 1. However, for systems with only one master device, the /SS pin of the master device is pulled low, and that is definitely not the other master device trying to drive the network. In this case, to prevent MODF from being set to 1, the SSDIS bit in the SPIx_CR register can be set to 1, and the /SS pin can be used as a general purpose I/O port or other function pin. If the device needs to be the host to transmit data, it is needed first to check whether the SS signal level is high. If it is high level, re-enabling the host to start communication is allowed. User must clear the MODF bit by software, set the MSTR bit and the SPIEN bit in the SPIx_CR register and restart the main mode. (2) Write Collision (WCOL) Write collision will be caused by writing to the SPIx_TDR register during the data transmitting sequence, and the WCOL bit in the SPIx_FR register is set to 1. Setting WCOL bit to 1 will not cause an interrupt and the transmitting will not be aborted. The WCOL bit needs to be cleared by software. (3) Overrun Case (RXOV) The overrun case occurs when the master device or the slave device has not cleared the SPRI bit and the master device or the slave device attempts to send several more data bytes. In this case, the receive shift register keeps the original data, SPRI is set to 1, and also the SPI device does not receive data until SPRI is cleared. The interrupt is called continuously until the SPRI bit is cleared, and the transmitting will not be aborted. Setting the RXOV bit to 1 will not cause an interrupt and the RXOV bit needs to be cleared by software.

23.2.3.8 Use FIFO to send and receive

The purpose of adding FIFO to SPI is the same as that of UART. Since SPI communication rate is much higher than UART, the depth of FIFO should also be higher accordingly. SPI only supports FIFO2 (8-byte depth). SPI FIFO Function Sign Type Reset Description FIFOEN W/R 0 SPI FIFO function control bit 0: Standard SPI 1: SPI with FIFO Note: SPI FIFO always comes in pairs, so TX FIFO and RX FIFO are controlled by the one switch, FIFOEN. For the mapping between SPI and FIFO, refer to the "FIFO Controller" section. When FIFO is not enabled, the SPI is a standard serial transceiver with 1-byte-deep send and receive buffer (TDR/RDR). It’s an original standard SPI. After FIFO is enabled, TX FIFO and RX FIFO replace the TDR and RDR of the original SPI, but some control bits and flag bits of the original SPI are still valid. SPI TX FIFO For TX FIFO, the MCU fills TX FIFO buffer, and at the same time, the SPI takes the data from TX FIFO. When TX FIFO counter gradually decreases and is less than the specified Trigger point, the trigger marker bit (TXTRIGF) will be set. The write width of TX FIFO is optional 8/16/32 bit. When 8-bit wide mode is selected, FIFO counter adds 1; when 16-bit wide mode is selected, FIFO counter adds 2 every time; when 32-bit wide mode is selected, FIFO counter adds 4 every time, that is, the basic counting unit of TX FIFO Counter is byte. The read width of TX FIFO is optional 8/16/32 bit (corresponding to SPI's 8/16/32 bit width mode), that is, the SPI shift register takes 1, 2, or 4 bytes from TX FIFO each time, and the corresponding Counter decreases by 1, 2, or 4.

When SPI RX FIFO mapped to SPI, the mode of FIFO is fixed to 8 bits. For RX FIFO, the SPI fills RX FIFO, and RX FIFO Counter gradually increases. When it is larger than the specified Trigger Level, the Trigger marker bit (RXTRIGF) will be set. RX FIFO bit width is optional 8/16/32 bit. When 8-bit read out is selected, FIFO Counter decreases by 1; when 16-bit wide mode is selected, FIFO counter decreases by 2 every time; when 32-bit wide mode is selected, FIFO counter decreases by 4 every time, that is, the basic counting unit of RX FIFO Counter is byte. If SPI is 8/16/32 bit wide, the SPI receives 8, 16 or 32 bit data each time, and the corresponding FIFO Counter will increase by 1, 2 or 4. The Description of SPI FIFO After FIFO is enabled, some function flags and some error flags will be affected in the interface interaction between FIFO and SPI. Please refer to the table below. Table23-4 The difference of SPI function and error flags when FIFO is on or off Function FIFO is off FIFO is on Transfer buffer(TDR) Transfer buffer(TDR) Invalid Receive buffer(RDR) Receive buffer(RDR) Invalid Send interrupt flag(SPTI) The initial state is 0. If TDR is empty, SPTI is set; if TDR is full, SPTI is cleared. Writing a Non-zero data to TDR can clear SPTI; if the data of TDR is shift to SPI shift register, SPTI is set. Setting SPTC can clear SPTI. Invalid, but TXTRIG has the same function as SPTI. When TX FIFO counter is reduced to trigger level, the TXTRIGF flag is set. Setting TXTRIGFC can clear TXTRIG. Receive interrupt flag(SPRI) The initial state is 0. The SPI interrupt SPRI is generated after the SPIx_RDR buffers complete the transfer of one byte data (the receive register is full when receiving) Invalid, but RXTRIG has the same function as SPRI. When RX FIFO counter is increased to trigger level, the RXTRIGF flag is set. Setting RXTRIGFC can clear RXTRIG. Writing conflict(WCOL) If TDR is not empty when the user continues to write TDR, WCOL is set. The new data will be ignored if a conflict occurs. Setting WCOLC can clear WCOL. Invalid FIFO does not define similar functionality. It is generally believed that sending is controlled by software and can be avoided completely by program control. Receive overflow(RXOV) If the data of RDR is not read when the new data is received to write RDR, RXOV is set. The new data will be ignored if a conflict occurs. Setting RXOVC can clear RXOV. Invalid, but OVF has the same function as RXOV. RX FIFO is full, but there is a new received data, then the OVF flag is set and the new data is ignored in order to keep the FIFO the same. Setting OVFC can clear RXOV. Mode failure error(MODF) Setting this bit to 1 indicates that the level on the /SS pin is in a bus collision with the SPI multi-master mode. Setting MODFC can clear MODF. Valid and the function is the same with standard SPI.

23.2.3.9 Interrupt

Three SPI state flags, SPTI, SPRI & MODF, can generate a CPU interrupt request. Serial peripheral data transmitting and receiving flag: The SPI interrupt (SPTI, SPRI) is generated after the SPIx_TDR and SPIx_RDR buffers complete the transfer of one byte data (the transmit register is empty when transmitting and the receive register is full when receiving); Mode fault flag MODF: setting this bit to 1 indicates that the level on the /SS pin is in a bus collision with the SPI multi-master mode. The SSDIS bit being 0 and setting MODF to 1 will generate an SPI receiver/error CPU interrupt request. When SSDIS is set to 1, no MODF interrupt request is generated.

Figure23-21 SPI Interrupt Control Diagram After FIFO is turned on, because THE TDR and RDR of SPI are replaced, the SPTI and SPRI interrupt sources are invalid, while the MODF interrupt sources are still valid. For interruption of FIFO, refer to the FIFO Controller section.

23.2.4 SPI Registers

SPI Module Register List (Base Address: 0x4000 2400) Address Register Name Description 0x4000 2400 FR SPI interrupt flag register 0x4000 2404 TDR SPI transmit data register 0x4000 2408 RDR SPI receive data register 0x4000 240C CR SPI control register

23.2.4.1 SPI Interrupt Flag Register (SPIx_FR)

Offset Address: 0x0000 Reset Value: 0x0000 0002 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved WCOL C RXOV C MODF C Reserv ed SPTIC SPRIC - WO WO WO - WO WO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Reserved WCOL RXOV MODF BUSY SPTI SPRI - RO RO RO RO RO RO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Bit Sign Description 31 ~ 22 Reserved -

21 WCOLC Write collision flag clear bit

0: Invalid 1: Clear

20 RXOVC Receive overflow flag clear bit

0: Invalid 1: Clear

19 MODFC Mode fault flag clear bit

0: Invalid 1: Clear

17 SPTIC Reserved

16 SPRIC Reserved

15 ~ 6 Reserved -

5 WCOL Write collision flag bit

0: There is no write collision or write collision has been dealt with, cleared by writing 1 to WCOLC bit by software 1: Write collision is detected, set by hardware

4 RXOV Receive overflow flag bit

0: There is no receive overflow or receive overflow has been dealt with, cleared by writing 1 to RXOVC bit by software 1: Receive overflow is detected, set by hardware

3 MODF Mode fault flag bit

0: No fault, cleared by writing 1 to MODFC bit by software 1: NSS pin level is inconsistent with the SPI mode, set by hardware

2 BUSY Host BUSY status flag bit

0: The host is idle 1: The host is sending, BUSY

1 SPTI SPI one byte data transmit interrupt flag bit

0: Transmit data register TDR is in full state, cleared by writing 1 to SPTIC bit by software 1: Transmit data register TDR is in empty state, set by hardware

0 SPRI SPI one byte data transmit interrupt flag bit

0: Transmit data register RDR is in full state, cleared by writing 1 to SPRIC bit by software 1: Transmit data register RDR is in empty state, set by hardware

23.2.4.2 SPI Transmit Data Register (SPIx_TDR)

Offset Address: 0x0004 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 TDR[31:0] RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 TDR[31:0] RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 0 TDR[31:0] Transmit buffer register Is 32-bit transmit buffer register when SPDATL=2 Is 16-bit transmit buffer register when SPDATL=1 Is 8-bit transmit buffer register when SPDATL=0

23.2.4.3 SPI Receive Data Register (SPIx_RDR)

Offset Address: 0x0008 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 RDR[31:0] RO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 RDR[31:0] RO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

31 ~ 0 RDR[15:0] Receive buffer register Is 32-bit receive buffer register when SPDATL=2 Is 16-bit receive buffer register when SPDATL=1 Is 8-bit receive buffer register when SPDATL=0

23.2.4.4 SPI Control Register (SPIx_CR)

Offset Address: 0x000C Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved FIFO EN SPDATL[1:0] - RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 SPS FF SPIE N Rese rved Rese rved SPTI E SPRI E Rese rved DIR MST R CPH A CPO L SSDI S SPR[3:0] RW RW - - RW RW - RW RW RW RW RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 19 Reserved -

18 FIFOEN SPI RX FIFO Enable Bit

0: Standard SPI 1: SPI with FIFO Note: SPI FIFO always comes in TX/RX pairs with only one enable switch 17 ~ 16 SPDATL[1:0] Data word length selection bit 00: Send 8 bits of data each time 01: Send 16 bits of data each time 1x: Send 32 bits of data each time

15 SPSFF Slave fast transmit mode control bit (valid when CPHA=0)

0: Normal mode, the SS pin of the slave must be pulled high after each time the transfer of one data (8 or 16 bits) is complete. Before transmitting the next data, SS must be pulled low to load data into the shift register. 1: Fast mode, the first data transmitted by the slave needs to be triggered with the falling edge of SS, and the second data is loaded to the shift register using the last CLK of the previous data (note: will not be loaded if there is no data in the transmit buffer)

14 SPIEN SPI enable

0: SPI is disabled 1: SPI is enabled

12 Reserved -

11 SPTIE SPI transmit interrupt flag enable bit

0: Transmit interrupt flag bit SPTI is disabled to trigger interrupt 1: Transmit interrupt flag bit SPTI is enabled to trigger interrupt

10 SPRIE SPI receive interrupt flag enable bit

0: Receive interrupt flag bit SPRI is disabled to trigger interrupt 1: Receive interrupt flag bit SPRI is enabled to trigger interrupt

8 DIR Data transmit direction selection bit

0: MSB transmitting priority 1: LSB transmitting priority

7 MSTR SPI master and slave devices configure bit

0: Configures SPI as master device 1: Configures SPI as slave device

6 CPHA Clock phase control bit

0: The first edge of CK period collects data 1: The second edge of CK period collects data

5 CPOL Clock polarity control bit

0: CK is at low level in IDLE state 1: CK is at high level in IDLE state

4 SSDIS NSS pin control bit

0: In master/slave mode, NSS pin is turned on 1: In master/slave mode, NSS pin is turned off, no MODF interrupt request will be generated In slave mode, if CPHA=0, this bit has no effect 3 ~ 0 SPR[3:0] Clock division control bit 0000: PCLK /2 0001: PCLK /4 0010: PCLK /8 0011: PCLK /16 0100: PCLK /32 0101: PCLK /64 0110: PCLK /128 0111: PCLK /256 1000: PCLK /512 1001: PCLK /1024 Other: Reserved

23.3 Two-Wire Serial Interface (TWI)

23.3.1 Introduction

Two-wire serial interface (TWI) inherits and develops the I2C bus interface and is fully compatible with the I2C bus. It has the advantages of simple hardware implementation, convenient software design, reliable operation and low cost. TWI consists of a clock wire and a data wire, it is transmitting in bytes, and is compatible with the SMBus specification, automatically processing byte transfers and tracking serial communications. SCL/SDA is the signal wire of the TWI bus. SDA is a bidirectional data wire and SCL is a clock wire. To transmit data on the TWI bus, first transmit the highest bit (MSB), the host sends a start signal, and then the host transmits one or more bytes of data. After the data is transmitted, the host sends a stop signal to complete the simplest TWI transmitting. A typical TWI bus application is shown below, supporting up to 128 different devices for communication. SCL Master Device 1 SDA VDD= 5VVDD= 5V VDD= 5V VDD=5V Slave Device 1 Slave Device 2 Master Device 2 VDD= 5V Figure23-22 Typical TWI Bus Application Block Diagram

23.3.2 Main Features

 Two-wire mode  OD output (needs to be configured in GPIO), signal level is not affected by VDD, and will not affect VDD  Supports master mode and slave mode  Allow to transmit and receive  Supports arbitration function of multi-host communication  Has low level bus timeout judgement  Can wake up the system in sleep mode, does not support stop mode wake-up  Address is programmable, with multiple address mask bits, supports broadcast function  Supports standard mode and fast mode

23.3.3 Function Description

23.3.3.1 Bus Signal Timing

The initial state of the bus is bus idle, which means both SDA and SCL signal wire are at high level, all devices on the bus release the bus, and the respective pull-up resistors of the two signal wires pull the level high. In data transfer, transfer of each bit on the data wire requires a pulse on the clock wire. The data wire should remain stable when the clock is at high level and allow the wire line to change when the clock is at low level. However, the start condition and the stop condition are special, the former refers to the falling edge of the data wire during the high level time of the clock, and the latter refers to the rising edge of the data wire during the high level time of the clock. SDA SCL data line stable,data valid change of data allowed Figure23-23 Basic Bit Transfer Characteristics of TWI Bus

Figure23-24 Start Condition (Start Signal) and Stop Condition (Stop Signal) of TWI Bus In TWI bus, start condition and stop condition are all sent by the host. The host can initiate and terminate a transfer. Start a transfer when the host sends a start condition and end this transfer when a stop condition is sent. The bus is defined as a "busy" state between the start condition and the stop condition. Other hosts should not attempt to initiate a transfer. In the "busy" state, if the host sends the start condition again, it is defined as "repeated start condition", indicating that the host wants to start a new transfer without giving up the bus. After the repeated start condition is sent, the bus is still in the "busy" state until a stop condition occurs on the bus. Since the nature of the repeated starting condition and the starting condition are exactly the same, unless otherwise stated, starting condition will be used instead of those two. All data packets (including address packets) consist of 9 bits, including 1 byte and an acknowledge bit. The host is responsible for sending the clock, the start condition and the stop condition, and the receiver is responsible for giving the response signal. The receiver sends an "acknowledge (ACK)" signal by pulling the data line low at the ninth clock pulse; or a "not acknowledge (NACK)" signal by maintaining high level at the ninth pulse. When the receiver receives the last byte, or for some reason cannot continue to receive data, it should respond with a "not acknowledge (NACK)" signal. SDA SCL ACK SDA SCL NACK Figure23-25 ACK and NACK Signals When the slave does not respond to the host addressing signal for some reason (such as the slave is performing real-time processing and cannot respond to bus communication), it must return a NACK, and then the host generates a stop signal to end the bus's data transfer. If the slave responds to the host but cannot continue to receive more data after the data transfer is on for a period of time, it can notify the host by returning a NACK, and the host should issue a stop signal to end the continuous transfer of the data. When the host receives the last data byte when receiving data, it must send a NACK to the slave to inform the slave to stop data transfer, and then the slave releases the SDA wire to allow the host to generate a stop signal. Note: TWI is two-way data communication. When a node sends data through SDA, it requires other nodes to release the SDA wire, which means the SDA wire is in external pull-up state. In the TWI bus, transfers are performed bit by bit from high to low. A transfer usually includes a start condition, address + read/write, one or more data packets and a stop condition. Data formats that only contain start and stop conditions do not meet the communication rules. It is worth noting that the "wire and" structure provides convenience to the handshake signal between the host and the slave. When the host is relatively fast or the slave needs to handle other matters, the slave can pull down the clock wire to lengthen the low level time of the clock wire, thus reducing the communication frequency. The slave can stretch the low level period of the clock wire but does not affect the high level period of the clock wire. When the response signal is generated, SH33F2801 pulls down the SDA signal wire. During the time the interrupt flag bit is set, SH33F2801 pulls the SCL signal wire low and releases the SDA signal wire. After the interrupt processing is completed, the TWINT flag is cleared and the SCL wire is released.

START STOPSLA+R/W Data Byte 1 2 7 8 9 1 Addr MSB Addr LSB R/W ACK Data MSB Data LSB ACK 2 7 8 9 SDA SCL Figure23-26 Diagram of a Typical TWI Data Transfer Timing After the main controller completes one communication and wants to continue to occupy the bus for communication, and does not release the bus, the repeated start condition Rs needs to be used. It is both the end of the previous data transfer and the beginning of the next transfer. In special cases, if all communication on the TWI bus needs to be disabled, it can be done by blocking or turning off the bus. The specific operation is to lock SCL at low level with any device on the bus.

23.3.3.2 Clock Synchronization

When multiple hosts want to control the bus at the same time, the bus will determine whether the clock wire is at high or low level based on the "wire and" principle. For all hosts involved in the transfer, it is important to clearly define the start of each clock pulse. A high-to-low transition of the clock wire level will cause all devices participating in the transfer to start low level timing. Each device releases its clock wire when it reaches its own low level requirement, and enters a high level wait time before the clock wire goes high level; when all devices are fully counting low level time, the clock wire goes high level. All devices then begin timing high level, and the first device that fully counts high level time will pull the clock line wire, entering the next clock period. Figure23-27 Clock Synchronization Timing Diagram Note: When multiple masters simultaneously control the SCL wire, the “wire and” will cause the low level period of the SCL wire to be determined by the host with the longest low level time, while the high level period is determined by the host with the shortest high level time. SCL from Master A SCL from Master B SCL bus Line Masters Start Counting Low Period Masters Start Counting High Period TA low TA high TB low TB high

23.3.3.3 Bus Arbitration

The host can only start a transfer when the bus is in the "idle" state. Two or more hosts may simultaneously send a start condition within the minimum duration (tHOLD:STA). As a result, a normal start condition will be obtained on the bus, multiple hosts will start transmitting, and subsequent transfers need to be arbitrated. . Since the host sending the start condition cannot know whether other hosts are competing for the bus, it can only judge by the level detection of the SDA wire during the SCL high level period, which means the arbitration logic checks whether the logic 1 sent by each SDA actually appears on the bus, if there are other hosts transmitting low level and pulling the SDA line low, the host transmitting the high level will lose arbitration and must abandon the bus. This is the basic arbitration logic. Note: This is a "low level priority" arbitration principle that awards the bus to the master device that sends low level on SDA first. The host that has lost the arbitration will switch from the transmit state to the receive state and continue to transmit the clock pulse (on SCL) until the current transferred byte has been transmitted. Note: In addition to the master transmit mode, in the master receive mode, when the master returns a NACK signal (logic 1) to the slave, arbitration loss may occur. Since NACK appears at the end of the serial byte, the module will no longer send a clock pulse. Arbitration is performed bit by bit. Its first phase is to compare the address bits. If multiple hosts address the same device, they may successfully pass the address phase arbitration, and the arbitration will continue to compare the data bits (the host transmit mode), or response bits (the host receive mode). Because the address and data information on the bus is determined by the host that won the arbitration, no information is lost during the arbitration. If this host has the slave mode enabled at the same time, it should check whether the address on the wire matches itself after losing the arbitration in the address transmitting phase; if this is an access to itself, it should immediately switch to the slave mode and receive the information. In each transmitting, the “repeated start condition” on the wire still needs to be detected. When detecting that this is not the “repeated start condition” issued by itself, the current transmitting should be exited immediately. When a host sends a repeated start condition or a stop condition, another host may still be transmitting data, which causes an undetermined state (the specification requires that this repeated start condition or stop condition be retransmitted in the same position of frame format). In order to achieve this, it is defined that in the following three cases the bus is not performing arbitration: 1. Host 1 sends a repeated start condition, host 2 sends the data. 2. Host 1 sends a stop condition, host 2 sends data. 3. Host 1 sends a repeated start condition and host 2 sends a stop condition. In addition, arbitration only occurs between hosts, and slaves do not participate in arbitration. Figure23-28 Data Arbitration Timing Diagram DATA 1 DATA 2 SDA SCL S Transmitter 1 loses arbitration

23.3.3.4 Detailed Structure of TWI Communication Module

The following figure describes the detailed structure of TWI communication module. Figure23-29 TWI Module Structure Diagram Bus interface unit The bus interface unit includes data and addresses shift register (TWI_DR), start/stop condition controller, arbitration and bus timeout detection unit. The register TWI_DR stores the data or address to be transmitted and the data and address received. The start/stop condition controller is responsible for sending and detecting the start condition, the repeated start condition and the stop condition on the bus. If SH33F2801 has started a transfer as host, the arbitration unit will always detect if arbitration has occurred. When the arbitration is lost, the control unit can perform the appropriate action and generate the corresponding state code. When transmitting data/address, SH33F2801 must maintain data stability untile SCL jumps from low to high. When transmitting ACK/NACK, SH33F2801 generates TWINT interrupt after SCL jumps from low to high, and pulls SCL low when SCL jumps from high to low, releases SCL when TWINT interrupt is cleared. When SH33F2801 is transmitting ACK/NACK signal, if TWINT has been cleared and SCL is still at high level, SDA generates transition, and then TWINT interrupt will be generated again, with the state being 00H. The current communication of SH33F2801 is terminated. This state is consistent with the normal 00H status processing. When SH33F2801 is transmitting ACK/NACK signal, if TWINT is not cleared and SCL is still at high level, SDA generates transition, and then the state will be switched directly to 00H, and no interrupt will be generated again. When SH33F2801 enters this state as a slave, the current communication is terminated, and may generate STA starting the host transfer or re-accept the STA+ADR access to its own address. When SH33F2801 enters this state as a host, the current communication is terminated, and the generatable STA may start the host transfer or re-accept the STA+ADR access to its own address. SH33F2801 will not participate in the current transmitting after the current communication is terminated. If SH33F2801 exists as a host, enable the EFREE function to prevent from entering the logic dead zone. SH33F2801 stipulates that when the bus maintains a high level exceeding the system clock number defined by TFREE = Tsys * TWI_HOC * 256 (must ensure that TFREE is greater than tSCL/ 2 (tSCL is the period of the clock wire)) it is at the "idle" state, releasing the bus (here the "system clock" Tsys is actually the TWI module operating clock). This feature is only available for the process of one packet transmitting (8+1 bits). This function is available when SH33F2801 is in slave transmit mode and the first byte transmitted is at low level. The start condition (STA, RSTA) does not apply to this function. SH33F2801 generates an interrupt and the TFREE in the TWI_CR register will be set (if the control bit EFREE has been set). Note: When the TWI module operates at 30MHz, EFREE=1, TFREE is 255×256/30000=2.176ms at maximum, and 256/30000=0.00853ms at minimum. When EFREE=0, TFREE is fixed at 25000/30000=0.83ms. Bit Rate Register (TWI_BRT) Address Register (TWI_ADDR) Address Comparator Status Register (TWI_SR) Status Machine and Status Control Control Register (TWI_CR) START/ STOP Control Timeout/ Bus Free Detection Arbitration Detection Address/Data Shift Register (TWI_DR) ACK Bus Interface Unit Address Match Unit Control Unit Bit Rate Generator SCL SDA

If the clock wire SCL is pulled low by the slave, the communication will be temporarily suspended; there is no way for the host to pull the clock wire high. To solve this problem, the TWI protocol stipulates that when all devices participating in the transfer maintain the clock wire at low level for more than the number of clocks defined by N*Tsys (the value of N is determined by the CNT register), it is "bus timeout". TOUT in the register TWI_FR will be set (if control bit ETOT is set). The software resets the TWI module and releases the bus by changes of this flag bit. Frequency generation unit In master mode, the communication frequency can be set by the register TWI_CR’s CR[1:0] division factor and the TWI_BRT[7:0] register. The SCL frequency is fTWI / (16 + 2 * CR * TWI_BRT). Note: Here fTWI is the working clock of the TWI module, which is the APB bus clock. Address matching unit The address matching unit verifies whether the received address matches the 7-bit address in TWIADR. If the corresponding bit in the address mask bit TWIAMR is set to 1, this bit address doesn’t detect. If the general address enable bit GC is set, it will also check if it matches the general address 00H. When the addresses match, the control unit will generate the appropriate action and the corresponding state code. Control unit The control unit monitors the TWI bus and gives corresponding responds according to the setting of the control register TWI_CR. When the TWI bus has any event that requires attention from application layer, the TWI interrupt flag is set, indicating that the state code of the current event will be written to the state register TWI_STAT. The state register TWI_STAT only indicates the communication state information when the TWI communication interrupt is generated; in other cases, the state register is a state code indicating that there is no valid state code. The clock wire will remain at low level until the interrupt is cleared. The application software allows the TWI communication to continue after the task has been processed.

23.3.3.5 TWI Operation Modes

In specific application, the TWI module can be used as a master, a slave, or both master and slave. In slave mode, the TWI hardware looks up the slave address as well as the general address (GC = 1). If one of the addresses is detected, interrupt request is generated. If the processor wants to become the bus master, the hardware must wait until the bus is idle before entering master mode, so that slave operation is not aborted. If bus arbitration is lost in master mode, the TWI module enters a wait state (pure master), or immediately switches to slave mode and detects its own slave address (master slave) in the same serial transfer. The four basic operating modes of TWI:  Master transmit mode  Master receive mode  Slave transmit mode  Slave receive mode Detailed description about those four modes can be found below. The TWI communication of SH33F2801 is performed by the underlying driver circuit and the interrupt-based application software. All bus events, such as receiving a byte or sending a start condition, each generate an interrupt. So during byte transfer, the application software can perform other operations. It should be noted that in addition to the basic TWI communication interrupt (TWINT), it is sometimes necessary to turn on the bus timeout (TOUT) and the SCL high level timeout (TFREE) detection. In both cases, interrupt is also generated, and the three interrupt sources share the same interrupt entry, see the “TWI Interrupt” part for details. When the TWINT bit is set, it indicates that a TWI transmitting has been completed, waiting for the response of the application software, at that time the state register TWI_STAT contains the current state. The application software can determine which communication the TWI performs via the registers TWI_CR and TWI_STAT. The four main modes of TWI communication are described below, and all possible state codes are described. The following figures shall have the following abbreviations: S : start condition Rs: repeated start condition R : read control bit W : write control bit A : acknowledge bit Ā : no acknowledge bit DATA: 8-bit data P : stop condition SLA: slave address The circle in the figure is used to indicate that the interrupt flag has been set. The number in it indicates the state code in the current state register TWI_STAT.

Before TWINT is cleared, the TWI communication will be suspended and the application software must decide whether to continue the communication or terminate the current transfer. For each state code, the required software actions and subsequent transfer details are described.  Master transmit mode In the master transmit mode, the master sends a series of data to the slave. To enter the master transmit mode, a start condition followed by a slave address + write control word (SLA+W) address packet indicates entering the master transmit mode (MT). STO and TWINT are cleared via setting TWIEN and STA in the control register TWI_CR, the TWI logic will detect the TWI bus and issue a START condition (STA) when enabled. After the start condition (STA) is transferred, the communication interrupt (TWINT) is set, the state register (TWI_STAT) is 08H, and the interrupt service routine should write the slave address and the write control word (SLA+W) to the data register TWI_DR. Clear the TWINT flag before initiating the next transfer. After the slave address and the write control word are transferred and an "acknowledgement" message is received, the interrupt (TWINT) is set and there are several possible states in the state register TWI_STAT: 18H, 20H and 38H for the master mode, and 68H, 78H and B0H for the slave mode.

Figure23-30 Master Transmit Mode State Diagram S SLA + W Ack DATA Ack P S SLA + W SLA + R Nack P Nack P Ack or Nack Ack or Nack Ack Successfully transmitted to a slave receiver Next transfer started with a repeated start condition Not acknowledge received after the slave address Not acknowledge received after a data byte Arbitration lost in slave address or data byte Arbitration lost and addressed as slave Other Master Continue Other Master Continue To Corresponding state in slave mode

18 H 28 H

68 H / 78 H / B 0 H

Table23-5 Master Transmit Mode State Code State Code TWI Bus and Hardware Interface State Application Software Response The Next Action Performed by TWI Read/write Data Register TWI_DR Operation Control Bit Operation ST A ST O T W IN T AA 08H Has transmitted start condition Writes in SLA+W X 0 0 X Transmits SLA+W, receives ACK or NACK 10H Has transmitted repeated start condition Writes in SLA +W X 0 0 X Transmits SLA+W, receives ACK or NACK Writes in SLA +R X 0 0 X Transmits SLA+R, TWI will be switched to master 将receive mode 18H Has transmitted SLA+W; has received ACK Writes in data bytes 0 0 0 X Transmits data, receives ACK or NACK No TWI_DR action 1 0 0 X Transmits repeated start condition 0 1 0 X Transmits stop condition; clears STO flag 1 1 0 X Transmits stop condition, after which start condition is transmitted; STO is cleared 20H Has transmitted SLA+W; has received ACK Writes in data bytes 0 0 0 X Transmits data, receives ACK or NACK No TWI_DR action 1 0 0 X Transmits repeated start condition 0 1 0 X Transmits stop condition; clears STO flag 1 1 0 X Transmits stop condition, after which start condition is transmitted; STO is cleared 28H Has transmitted data in TWI_DR; has received ACK Writes in data bytes 0 0 0 X Transmits data, receives ACK or NACK No TWI_DR action 1 0 0 X Transmits repeated start condition 0 1 0 X Transmits stop condition; clears STO flag 1 1 0 X Transmits stop condition, after which start condition is transmitted; STO is cleared 30H Has transmitted data in TWI_DR; has received ACK Writes in data bytes 0 0 0 X Transmits data, receives ACK or NACK No TWI_DR action 1 0 0 X Transmits repeated start condition 0 1 0 X Transmits stop condition; clears STO flag 1 1 0 X Transmits stop condition, after which start condition is transmitted; STO is cleared 38H Loses arbitration bit in SLA+W or data transfer No TWI_DR action 0 0 0 X TWI bus is released; enters non-addressing slave mode 1 0 0 X Transmits start condition when the bus is idle

 Master Receive Mode In the master receive mode, the master receives a series of data from the slave. To enter the master receive mode, a start condition followed by a slave address + read control word (SLA+R) address packet indicates entering the master receive mode (MR). STO and TWINT are cleared via setting TWIEN and STA in the control register TWI_CR, the TWI logic will detect the TWI bus and issue a start condition (STA) when enabled. After the start condition (STA) is transferred, the communication interrupt (TWINT) is set, and the state register (TWI_STAT) is 08H. The interrupt service routine should write the slave address and the read control word (SLA+R) to the data register TWI_DR. Clear the TWINT flag before initiating the next transfer. After the slave address and the write control word are transferred and an "acknowledgement" message is received, the interrupt (TWINT) is set and there are several possible states in the state register TWI_STAT: 40H, 48H and 38H for the master mode, and 68H, 78H and B0H for the slave mode. Figure23-31 Master Receive Mode State Diagram S SLA + R Ack DATA Nack P S SLA + R SLA + W Nack P Ack or Nack Ack Ack Next transfer started with a repeated start condition Not acknowledge received after a data byte Arbitration lost in slave address or not acknowledged Arbitration lost and addressed as slave Other Master Continue Other Master Continue To Corresponding state in slave mode

40 H 58 H

38 H 38 H

Table23-6 Master Receive Mode State Code State Code TWI Bus and Hardware Interface State Application Software Response The Next Action Performed by TWI Read/write Data Register TWI_DR Operation Control Bit Operation ST A ST O TW INT AA 08H Has transmitted start condition Write in SLA+R X 0 0 X Transmits SLA+R, receives ACK or NACK 10H Has transmitted repeated start condition Write in SLA+R X 0 0 X Transmits SLA+R, receives ACK or NACK Write in SLA+W X 0 0 X Transmits SLA+W, TWI will be switched to master transmit mode 38H Loses arbitration when transmitting SLA+R or NACK No TWI_DR action 0 0 0 X TWI bus is released; enters non-addressing slave mode 1 0 0 X Transmits start condition when the bus is idle 40H Has transmitted SLA+R; has received ACK No TWI_DR action 0 0 0 0 Receives data, returns NACK 0 0 0 1 Receives data, returns ACK 48H Has transmitted SLA+R; has received ACK No TWI_DR action 1 0 0 X Transmits repeated start condition 0 1 0 X Transmits stop condition; clears STO flag 1 1 0 X Transmits stop condition, after which start condition is transmitted; STO is cleared 50H Data has been received; has responded ACK Reads data 0 0 0 0 Receives data, returns NACK 0 0 0 1 Receives data, returns ACK 58H Data has been received; has responded ACK Reads data 1 0 0 X Transmits repeated start condition 0 1 0 X Transmits stop condition; clears STO flag 1 1 0 X Transmits stop condition, after which start condition is transmitted; STO is cleared

 Slave transmit mode In the slave transmit mode, the slave sends a series of data to the master. To initialize the slave transmit mode, the control register TWI_CR and the address register TWI_ADDR must be initialized: TWIEN and AA in the control register TWI_CR are set, STA, STO, and TWINT are cleared; the address bit TWIADR prepares the corresponding address for SH33F2801. If GC is set, SH33F2801 will also respond to the general address (00H); otherwise it will not respond to the general address. After the TWIADR and TWI_CR are initialized, SH33F2801 will wait for the bus to respond to its own address or general address (if the GC is set). If the direction flag is "read", the TWI enters the slave transmit mode, otherwise it will enter the slave receive mode. After the address and read flag bits have been received, the interrupt flag (TWINT) is set and the state register TWI_STAT is valid. During transmitting, if the acknowledge enable bit "AA" is cleared, TWI will transmit the last byte and enter the C0H or C8H state depending on the acknowledge or no acknowledge message bit sent by the host receiver. The bus will switch to non-addressing slave mode and not respond to host transfer any more. Thus the host receiver will receive a string of "1"s. After the last byte has been transmitted, if the host still needs additional data (transmitting the "acknowledge" signal), it enters the C8H state. Figure23-32 Slave Transmit Mode State Diagram S SLA + R DATA Nack P or S Ack P or S Ack Receiving of the own slave address and transmitting of one or more data bytes Arbitration lost as master and addressed as slave transmitter Last data byte transmitted , Switched to not addressed slave ( AA = 0 ) A 8 H C 0 H B 0 H DATA B 8 H SH 33 F xxx Actions Other Device Actions C 8 H All ' 1 ' Ack Ack

Table23-7 Slave Transmit Mode State Code State Code TWI BUS AND HARDWARE INTERFACE STATE Application Software Response THE NEXT ACTION PERFORMED BY TWI Read/write Data Register TWI_DR Operation Control Bit Operation ST A ST O TW INT AA A8H Has received its own SLA+R; has responded ACK Writes in data bytes X 0 0 0 Transmits final data; waits for response from ACK or NACK X 0 0 1 Transmits data; waits for response from ACK or NACK B0H Loses arbitration when transmitting SLA+R/W as host, receives SLA+R from host; has responded to ACK Writes in data bytes X 0 0 0 Transmits final data; waits for response from ACK or NACK X 0 0 1 Transmits data; waits for response from ACK or NACK B8H Has transmitted TWI_DR data; has received response from ACK Writes in data bytes X 0 0 0 Transmits final data; waits for response from ACK or NACK X 0 0 1 Transmits data; waits for response from ACK or NACK C0H Has transmitted TWI_DR data; has received response from NACK No TWI_DR action 0 0 0 0 Switches to non-addressing slave mode; does not respond to its own address and general address 0 0 0 1 Switches to non-addressing slave mode; responds to its own address, and whether to respond to general address depends on the setting of GC in register TWI_ADDR 1 0 0 0 Switches to non-addressing slave mode; does not respond to its own address and general address; sends “start condition” when the bus is idle 1 0 0 1 Switches to non-addressing slave mode; responds to its own address, and whether to respond to general address depends on the setting of GC in register TWI_ADDR; sends “start condition” when the bus is idle C8H Has transmitted the last TWI_DR data (AA=0); has received response from ACK No TWI_DR action 0 0 0 0 Switches to non-addressing slave mode; does not respond to its own address and general address 0 0 0 1 Switches to non-addressing slave mode; responds to its own address, and whether to respond to general address depends on the setting of GC in register TWI_ADDR 1 0 0 0 Switches to non-addressing slave mode; does not respond to its own address and general address; sends “start condition” when the bus is idle 1 0 0 1 Switches to non-addressing slave mode; responds to its own address, and whether to respond to general address depends on the setting of GC in register TWI_ADDR; sends “start condition” when the bus is idle

 Slave receive mode In the slave receive mode, the slave receives a series of data from the master. To initialize the slave receive mode, the control register TWI_CR and the address register TWI_ADDR must be initialized: TWIEN and AA in the control register TWI_CR are set, STA, STO, and TWINT are cleared; the upper 7-bit of the address register TWIADR prepares the corresponding address for SH33F2801. If GC is set, SH33F2801 will also respond to the general address (00H); otherwise it will not respond to the general address. After TWI_ADDR and TWI_CR are initialized, SH33F2801 will wait for the bus to respond to its own address or general address (if GC is set). If the direction flag is 'write', TWI enters the slave receive mode, otherwise it will enter the slave transmit mode. After the address and write flag bits have been received, the interrupt flag (TWINT) is set and the state register TWI_STAT is valid. During transmitting, if the acknowledge enable bit "AA" is cleared, the TWI will receive the last byte and respond with a "no acknowledge" message. Responding with "no acknowledge" indicates that the current slave cannot receive more bytes. When AA=0, SH33F2801 cannot respond to access to its own address; however, it still monitors the bus state and can restore the response to the corresponding address to itself via AA=1. SH33F2801 can be temporarily isolated from the bus via AA=0. Figure23-33 Slave Receive Mode Diagram S SLA + W Ack DATA Ack P or S Nack P or S Ack Receiving of the own slave address and one or more data bytes , All are acknowledged Arbitration lost as master and addressed as slave receiver Last data byte received is not acknowledged 80 H Ack DATA 80 H SH 33 F xxx Actions Other Device Actions 88 H A 0 H General Call Ack DATA Ack P or S Nack P or S Receiving of general call address and one or more data bytes , All are acknowledged Arbitration lost as master and addressed as slave receiver by general call Last data byte received is not acknowledged 90 H Ack DATA 70 H 98 H A 0 H 68 H 60 H 78 H 90 H Ack

Table23-8 Slave Receive State Code State Code TWI BUS AND HARDWARE INTERFACE STATE Application Software Response THE NEXT ACTION PERFORMED BY TWI Read/write Data Register TWI_DR Operation Control Bit Operation ST A ST O TW INT AA 60H Has received its own SLA+W; has responded to ACK No TWI_DR action X 0 0 0 Receives data; transmits NACK response X 0 0 1 Receives data; transmits ACK response 68H Loses arbitration when transmitting SLA+R/W as host, receives SLA+W from host; has responded to ACK No TWI_DR action X 0 0 0 Receives data; transmits NACK response X 0 0 1 Receives data; transmits ACK response 70H Receives general address transmitted by the host; has responded to ACK No TWI_DR action X 0 0 0 Receives data; transmits NACK response X 0 0 1 Receives data; transmits ACK response 78H Loses arbitration when transmitting SLA+R/W as host, receives general address transmitted by the host; has responded to ACK No TWI_DR action X 0 0 0 Receives data; transmits NACK response X 0 0 1 Receives data; transmits ACK response 80H Is in already addressed state; has received data; has responded to ACK Reads data X 0 0 0 Receives data; transmits NACK response X 0 0 1 Receives data; transmits ACK response 88H Is in already-addressed state; has received data; has responded to NACK Reads data 0 0 0 0 Switches to non-addressing slave mode; does not respond to its own address and general address 0 0 0 1 Switches to non-addressing slave mode; responds to its own address, and whether to respond to general address depends on the setting of GC in register TWI_ADDR 1 0 0 0 Switches to non-addressing slave mode; does not respond to its own address and general address; sends “start condition” when the bus is idle 1 0 0 1 Switches to non-addressing slave mode; responds to its own address, and whether to respond to general address depends on the setting of GC in register TWI_ADDR; sends “start condition” when the bus is idle 90H Is in already-addressed state for general address; has received data; has responded to ACK Reads data X 0 0 0 Receives data; transmits NACK response X 0 0 1 Receives data; transmits ACK response

address; has received data; has responded to NACK Reads data 0 0 0 0 Switches to non-addressing slave mode; does not respond to its own address and general address 0 0 0 1 Switches to non-addressing slave mode; responds to its own address, and whether to respond to general address depends on the setting of GC in register TWI_ADDR 1 0 0 0 Switches to non-addressing slave mode; does not respond to its own address and general address; sends “start condition” when the bus is idle 1 0 0 1 Switches to non-addressing slave mode; responds to its own address, and whether to respond to general address depends on the setting of GC in register TWI_ADDR; sends “start condition” when the bus is idle A0H Receives stop condition or repeated start condition as slave No TWI_DR action 0 0 0 0 Switches to non-addressing slave mode; does not respond to its own address and general address 0 0 0 1 Switches to non-addressing slave mode; responds to its own address, and whether to respond to general address depends on the setting of GC in register TWI_ADDR 1 0 0 0 Switches to non-addressing slave mode; does not respond to its own address and general address; sends “start condition” when the bus is idle 1 0 0 1 Switches to non-addressing slave mode; responds to its own address, and whether to respond to general address depends on the setting of GC in register TWI_ADDR; sends “start condition” when the bus is idle

 Other modes In addition to the above state codes, there are two state codes without explicit TWI state. State 0F8H indicates that there is no corresponding state information due to the interrupt flag TWINT not being set. When the interrupt TWINT is not set, it is filled by 0F8H after clearing a state and before a new state is established. State 00H indicates that error has occurred in the TWI bus communication, which means illegal start condition or stop condition occurs in the transfer. For example, a start or stop condition occurs when transferring an address, data or responding to an ACK response. The 00H state is also generated when the bus disturbs the internal logic. When illegal state occurs, the interrupt flag bit TWINT is set. The normal communication can be resumed by setting STO and clearing the TWINT flag. SH33F2801 will enter the non-addressing slave mode and automatically clear the STO flag. The data wire and clock wire will be released and there will be no stop condition transmitted on the wire. Table23-9 Other Modes State Code State Code TWI BUS AND HARDWARE INTERFACE STATE Application Software Response THE NEXT ACTION PERFORMED BY TWI Read/write Data Register TWI_DR Operation Control Bit Operation ST A ST O TW INT AA F8H No valid state code; TWINT=0 No TWI_DR action No TWI_DR action Waits or deals with current transfer 00H There is an illegal start or stop condition transmitted in the master or addressing slave mode; interface causes internal logic confusion in TWI No TWI_DR action 0 1 0 X Only internal hardware is affected; releases the bus; switches to non-addressing slave mode; clears STO

23.3.3.6 Supporting Fast Mode 400kbps

The TWI module is compatible with two common transfer rates: standard mode 100kHz, fast mode 400kHz. The two transfer rates are obtained by the application software configuring the division factor CR[1:0] and the bit rate configure bit BRT[7:0].

23.3.3.7 Interrupt

Bus timeout flag TOUT, SCL high level timeout flag TFREE, TWI communication interrupt flag TWINT, any one of those three flags will cause TWI interrupt, the three share the interrupt vector, and the flags must be cleared by software. TOUT: Bus timeout flag. A bus timeout (event) occurs when the clock wire (SCL) low level exceeds N*Ttwi. The value of N is set by the CNT[1:0]@TWI_CR register bits. The bus timeout detection function is automatically turned on, as long as TWI works, this function is valid (cannot be turned off). But if the bus timeout (event) wants to cause a TWI interrupt, first the TOUT flag needs to be generated, and the generation of the TOUT flag is controlled by ETOT, with ETOT enabled, TOUT can be generated, then if the TWI total interrupt is enabled (TWINTE = 1), TWI interrupt is caused. Otherwise, if ETOT is not enabled or TWINTE is not enabled, no TWI interrupt will be generated. TFREE: SCL high timeout flag. An SCL high timeout (event) occurs when the clock wire (SCL) high level exceeds HOC *256*Ttwi. The HOC value is set by the HOC[7:0]@TWI_HOC register bits. The SCL high timeout detection function is automatically turned on, as long as the TWI works, this function is valid (cannot be turned off). But if the SCL high timeout (event) wants to cause a TWI interrupt, first the TFREE flag needs to be generated, and the generation of the TFREE flag is controlled by EFREE, with EFREE enabled, TFREE can be generated, then if the TWI total interrupt is enabled (TWINTE=1), TWI interrupt is caused. Otherwise, if EFREE is not enabled or TWINTE is not enabled, no TWI interrupt will be generated. TWINT: TWI communication interrupts flag, which is turned on when the TWI module is enabled. TWINT is set when the TWI state is changed. However, entering state F8 does not set TWINT because the interrupt service routine does not work in that case. When TWINT is set, the serial clock on the SCL wired expands with low level periods and the serial transfer is aborted. When SCL is high, the state of the TWINT flag is not affected. TWINTE: TWI total interrupt enable bit. When TWINTE is enabled and both ETOT and EFREE are on, any TOUT/TFREE/TWINT (interrupt) event will cause a TWI interrupt. If TWINTE is enabled by turning off the total interrupt, the application software can only perform TWI communication processing by query.

23.3.3.8 TWI Communication Service Program Development

The TWI module of SH33F2801 needs to be compatible with the user application to achieve a complete TWI communication protocol (communication protocols are different depending on the applications), ensuring maximum application flexibility. The user application is driven via the TWI interrupt without affecting the main flow and other controls. For details, please refer to the state diagram and state code of the four main modes for development. For the most basic cases of operations on the TCU/I2C interface peripherals of MCU, only the "Master Transfer Mode" needs to be referred for development. The operations that a complete TWI server must perform include: 1. The TWI module is initialized after reset, including configuring the slave address and general address bit (GC), enabling interrupts, setting the serial clock frequency, and so on. 2. The TWI interrupts service, state codes are identified and corresponding state service programs are entered according to branches. Timeout conditions also need to be handled to limit invalid bus or lost service program. 3. Multiple state service programs supporting 4 TWI operation modes. If one or more modes are not used, the corresponding state services can be ignored (as long as they are handled carefully, those states will not appear).

23.3.4 TWI Registers

TWI Module Register List (Base Address: 0x4000 2800) Address Register Name Description 0x4000 2800 FR TWI interrupt flag register 0x4000 2804 STAT TWI state register 0x4000 2808 HOC TWI high level timeout detection configure register 0x4000 280C BRT TWI bit rate configure register 0x4000 2810 DR TWI data register 0x4000 2814 ADDR TWI address configure register 0x4000 2818 CR TWI control register

23.3.4.1 TWI Interrupt Flag Register (TWI_FR)

Offset Address: 0x0000 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved TOUT C TFREE C Reserv ed TWINT C - WO WO - WO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Reserved TOUT TFREE Reserv ed TWINT - RO RO - RO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 20 Reserved -

19 TOUTC But timeout flag clear bit

0: Invalid 1: Clear

18 TFREEC SCL high level timeout flag clear bit

0: Invalid 1: Clear

16 TWINTC TWI one byte data transfer interrupt flag clear bit

0: Invalid 1: Clear

15 ~ 4 Reserved -

3 TOUT But timeout flag bit

0: No timeout flag occurs 1: Is set when the TWI bus low level exceeds N*Tsys. The value of N is determined by the CNT@TWI_CR register bits

2 TFREE SCL high level timeout flag bit

0: No timeout flag occurs 1: When participating in bus transfer, if the clock wire high level exceeds the number of system clocks defined by TFREE=Tsys* TWI_HOC *256, this is set by hardware

0 TWINT TWI one byte data transfer interrupt flag bit

0: No communication flag occurs 1: Single byte data transmitting is complete, this is set by hardware

23.3.4.2 TWI State Register (TWI_STAT)

Offset Address: 0x0004 Reset Value: 0x0000 00F8 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Reserved SR[4:0] Reserved - RO - 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 Bit Sign Description 31 ~ 8 Reserved - 7 ~ 3 SR[4:0] TWI serial communication state bit 2 ~ 0 Reserved -

23.3.4.3 TWI High Level Timeout Detection Configure Register (TWI_HOC)

Offset Address: 0x0008 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Reserved HOC[7:0] - RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 8 Reserved - 7 ~ 0 HOC[7:0] TWI SCL bus high level timeout detection configure bit

23.3.4.4 TWI Bit Rate Configure Register (TWI_BRT)

Offset Address: 0x000C Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Reserved BRT[7:0] - RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 8 Reserved - 7 ~ 0 BRT[7:0] TWI bit rate configure bit

23.3.4.5 TWI Data Register (TWI_DR)

Offset Address: 0x0010 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Reserved DR[7:0] - RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 8 Reserved - 7 ~ 0 DR[7:0] TWI data register

23.3.4.6 TWI Address Configure Register (TWI_ADDR)

Offset Address: 0x0014 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved TWIAMR[6:0] Reserv ed - RW - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Reserved ADDR[6:0] GC - RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

31 ~ 24 Reserved - 23 ~ 17 TWIAMR[6:0] TWI address mask bit Each bit of the TWIAMR can mask the corresponding address bit in the TWIADR address register. If the mask bit is set to 1, the address matching logic ignores the compare result of the input address bits with the corresponding address bits in TWIADR; if the mask bit is set to 0, the compare result of the corresponding bits is not ignored. 16 ~ 8 Reserved - 7 ~ 1 ADDR[6:0] TWI address configure bit

0 GC General address enable bit

0: responding to general address is disabled 1: responding to general address is enabled

23.3.4.7 TWI Control Register (TWI_CR)

Offset Address: 0x0018 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 TWIEN Reserved TWINT E ETOT EFREE CNT[1:0] CR[1:0] Reserv ed STA STO AA RW - RW RW RW RW RW - RW RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 16 Reserved -

15 TWIEN TWI enable bit

0: TWI is disabled 1: TWI is enabled 14 ~ 11 Reserved -

10 TWINTE TWI transmit receive interrupt flag enable bit

0: TWI interrupt flag bit TWINT is disabled to trigger interrupt 1: TWI interrupt flag bit TWINT is enabled to trigger interrupt

9 ETOT Bus timeout flag enable bit

0: TWI bus timeout is disabled to generate TOUT flag (cannot generate TOUT interrupt either) 1: TWI bus timeout is enabled to generate TOUT flag (TOUT is enabled to generate interrupt)

8 EFREE SCL high level timeout flag enable bit

0: SCL high level timeout is disabled to generate TFREE flag (cannot generate TFREE interrupt either) 1: SCL high level is enabled to generate TFREE flag (TFREE is enabled to generate interrupt) 7 ~ 6 CNT[1:0] Bus timeout count control bit 00: N=25000 01: N=50000 10: N=100000 11: N=200000 Value N is used in bus timeout function

5 ~ 4 CR[1:0] TWI division coefficient 00: 64 01: 16 10: 4 11: 1

2 STA Start bit

0: Does not send start condition 1: Sends start condition when the bus is idle Note: When STA=1, the start condition is sent and the main mode is entered. If it is already in the master mode, the repeated start condition is sent. When both STA and STO are set, if in the master mode, a stop condition is sent to the bus and then a start condition is sent. If the interface is in the slave mode, an internal stop condition is generated but not sent to the bus.

1 STO Stop bit

0: Does not send stop condition 1: Sends stop condition as a master; does not send stop condition to the bus as a slave, but the state is restored to the non-addressing slave state. The hardware will automatically clear this flag Note: In the master mode, when STO is 1, a stop condition is sent or it is recovered from the error state in the slave mode. When STO=1 in the master mode, stop condition is sent to the bus. When the bus detects a stop condition, STO is automatically cleared. In the slave mode, the STO bit is set to recover from the error state. In this case, no stop condition is sent to the bus. The hardware behaves as if it received a stop condition and switched to the non-addressing slave receive mode. The STO flag is automatically cleared by hardware.

0 AA Acknowledge flag bit

0: Responds with “no acknowledge” signal (SDA high level) 1: Responds with “acknowledge” signal (SDA low level)

23.4 FIFO Controller

23.4.1 Introduction

FIFO controller is used to match the speed difference between high-speed main system and low-speed peripheral communication interface. Through FIFO buffer, CPU interruption frequency can be reduced to ensure smooth communication data flow and improve the efficiency of the system. For duplex peripherals (full duplex or half duplex), Each group of FIFO consists of two completely independent FIFO modules, TX FIFO and RX FIFO. SH33F2801 has three groups of FIFO, all of which are duplex peripherals. The specific resources are as follow: FIFO0: 4-byte FIFO, TXFIFO 4×8bit, RXFIFO 4×(8+3)bit FIFO1: 4-byte FIFO, TXFIFO 4×8bit, RXFIFO 4×(8+3)bit FIFO2: 8-byte FIFO, TXFIFO 8×8bit, RXFIFO 8×(8+3)bit

23.4.2 Main Features

 TX FIFO 8 bit width (The depth of TX FIFO can be set 8/16/32-bit, FIFO counter±1/±2/±4)  RX FIFO 8 bit/(8+N)bit width, (8+N)bit just for UART module  Configurable FIFO depth (2N, N≥2), RX FIFO and TX FIFO can be configured separately  FIFO empty, non - empty, full flag  Support programmable trigger level:1/4,1/2,3/4  When an overflow occurs, the data is ignored  Flush mode, Reset read-write pointer  Providing data timeout signal

23.4.3 Function Description

23.4.3.1 Enable and Reset Signals

FIFO has a separate clock switch, which is controlled by RCC module. The FIFO register can be operated after the clock is enabled, and then the FIFO starts to work if the FIFO is enabled. The FIFO internal reset signal is used to reset the FIFO data, counter value and internal pointer, but it has no effect on the FIFO configuration register and flags.

23.4.3.2 FIFO Mapping

The mapping between FIFO and peripherals is configurable, and each FIFO can be mapped to any of multiple peripherals. However, there is no error checking for multiple FIFO mapping to the same peripheral on the hardware, which needs to be avoided by software. Setting the bits of TCMAP @FIFOx_CR and RXMAP @ FIFOx_CR, 4-byte FIFO can be mapped to UART0/1/2, 8-byte FIFO can be mapped to UART0/1/2 and SPI. Once configured, FIFO replaces the peripheral's original transceiver buffer (if any), but only affects the data interface. The transceiver control of the peripheral is still done by the peripheral module, and FIFO only participates in the reading and writing of data. For details on how to control FIFO in combination with peripherals, please refer to relevant chapters on peripheral modules with FIFO function. The mapping of the peripheral to FIFO is configured to operate in the peripheral module. Once a FIFO is mapped in a peripheral, the FIFO clock must enable first by software, and the hardware does not check this. Note that the following steps are required for a peripheral to configure FIFO:  Enable FIFO clock, enable FIFO, complete FIFO configuration;  mapping of FIFO and peripherals;  Enable FIFO function in the peripheral module and start using FIFO.

23.4.3.3 Trigger Level Define

 After reset, FIFO Counter is 0  when writing data and not read operation, counter+1  when data is read and not write operation, counter-1 Trigger Signal  Trigger Level can be configured to1/4 ,1/2 ,3/4  RX FIFO: When the counter value adds up to the programmable trigger point, generate trigger signal  TX FIFO: When the counter value decreases, it is equal to the programmable trigger point, generate trigger signal Trigger Level Sign Type Reset Value Description RXTRIG R/W 0 The trigger points for RX FIFO 00: RX FIFO >= 1/4 full 01: RX FIFO >= 1/2 full 10: RX FIFO >= 3/4 full 11: RX FIFO has a data TXTRIG R/W 0 The trigger points for TX FIFO 00: TX FIFO <= 1/4 full 01: TX FIFO <= 1/2 full 10: TX FIFO <= 3/4 full 11: TX FIFO empty

23.4.3.4 FIFO Read/write interface

The FIFO module data flow is one-way, In other words, for TX FIFO, data is written to FIFO from CPU, and data is fetched from FIFO by peripherals. For RX FIFO, data is written to the FIFO from a peripheral, and the CPU reads data from the FIFO. For a FIFO (whether TX or RX), the interface to the peripherals is defined (usually 8-bit, but sometimes 16-bit). The bit width of the interface to the CPU is configurable and can be configured with 8/16/32 bits. The CPU's data interface to read and write FIFO is a fixed address. Write/Read Data Width Sign Type Reset Value Description RXRDBITW W/R 0 RX FIFO Read Data Width(Note) 0: 8-bit 1: 16-bit 2: 32-bit 3: Reserved TXWRBITW W/R 0 TX FIFO Write Data Width 0: 8-bit 1: 16-bit 2: 32-bit 3: Reserved Note: For the 8+ N configurations, to read out the next N bit, it needs to be configured as a 16-bit read, where the high bit is supplemented with zero.

23.4.3.5 FIFO Status Description

 If FIFO counter is equal to the depth of FIFO, FULL flag is set  If FIFO counter = 0, EMPTY flag is set  If FIFO counter is not equal to 0, NON-EMPTY flag is set FIFO Status Sign Type Reset Value Description TXEMPTY R 0 When TX FIFO is empty, TXEMPTY =1 When TX FIFO has data, RXEMPTY =0 TXFULL R 0 When TX FIFO is full, TXFULL=1 RXEMPTY R 0 When RX FIFO is empty, RXEMPTY =1 When RX FIFO has data, RXEMPTY =0 RXFULL R 0 When RX FIFO is full, RXFULL=1

23.4.3.6 FIFO control process

For TX FIFO, the MCU fills TX FIFO buffer, and at the same time, the peripheral takes the data from TX FIFO. When TX FIFO counter gradually decreases and is less than the specified Trigger point, the trigger marker bit (TXTRIGF) will be set. The width of TX FIFO is optional 8/16/32 bit. When 8-bit wide mode is selected, FIFO counter adds 1; when 16-bit wide mode is selected, FIFO counter adds 2 every time; when 32-bit wide mode is selected, FIFO counter adds 4 every time, that is, the basic counting unit of TX FIFO Counter is byte. For example: TX FIFO Depth is 4 Bytes, Trigger Level is configured as 1/2, set TX FIFO bit width is 8-bit. When the MCU TX FIFO is full, it will not operate any more. When the peripheral transfer a byte, TX FIFO Counter decreases 1; when TX FIFO Counter decreases to 2 (1/2 FIFO Depth), the hardware will set TXTRIGF, and an interrupt (if enabled). That means MCU TX FIFO is half-full, the data needs to be put into THE TX FIFO. For RX FIFO, the peripheral fills RX FIFO, and RX FIFO Counter gradually increases. When it is larger than the specified Trigger Level, the Trigger marker bit (RXTRIGF) will be set. RX FIFO bit width is optional 8/16/32 bit. When 8-bit read out is selected, FIFO Counter decreases by 1; when 16-bit wide mode is selected, FIFO counter decreases by 2 every time; when 32-bit wide mode is selected, FIFO counter decreases by 4 every time, that is, the basic counting unit of RX FIFO Counter is byte. For example: RX FIFO Depth is 4 bytes, Trigger Level configuration for 1/2, set the RX FIFO read bits wide is eight bits, the RX module began to fill the RX FIFO, each filled with a data, RX FIFO Counter plus 1, when the RX FIFO Counter increased to 2 (1/2 FIFO the Depth), the hardware will setting RXTRIGF, and interrupt (if enabled), that means the RX FIFO is half full, need MCU read data from the RX FIFO.

23.4.3.7 FIFO Interrupt

Each group of FIFO has three interrupt sources and shares one interrupt entry. Each interrupt source has a separate enablement bit. The interrupt flag bit is cleared using a dedicated interrupt cleanup control bit. FIFO IRQ Sign Type Reset Value Description OVF R 0 RX FIFO is full, but there is a new received data, then the OVF flag is set and the new data is ignored in order to keep the FIFO the same. RXTRIGF R 0 When RX FIFO counter is accumulate to trigger level, the RXTRIGF flag is set. TXTRIGF R 0 When TX FIFO counter is reduced to trigger level, the TXTRIGF flag is set.

23.4.4 FIFO4L Register

FIFO4L Module Register List (Base Address: 0x4000 4400) Address Register Name Description 0x4000 4400 FR FIFO Interrupt and State Register 0x4000 4404 CR FIFO Control Register

23.4.4.1 FIFO Interrupt and State Register (FIFO4L_FR)

Offset Address: 0x0000 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved RXO VFC TXT RIGF C RXT RIGF C - WO WO WO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Reserved TXF ULL RXF ULL TXE MPT RXE MPT Rese rved RXO VF TXT RIGF RXT RIGF - RO RO RO RO - RO RO RO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 19 Reserved -

18 RXOVFC RX FIFO data overrun error flag clear bit

17 TXTRIGFC TX FIFO trigger level flag clear bit

16 RXTRIGFC RX FIFO trigger level flag clear bit

15 ~ 8 Reserved -

7 TXFULL TX FIFO full status flag

6 RXFULL RX FIFO full status flag

5 TXEMPT TX FIFO empty status flag

4 RXEMPT RX FIFO empty status flag

2 RXOVF RX FIFO data overrun error status flag

1 TXTRIGF TX FIFO trigger level flag

0 RXTRIGF RX FIFO trigger level flag

23.4.4.2 FIFO Control Register (FIFO4L_CR)

Offset Address: 0x0004 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved TXF EN RXF EN TXF RST RXF RST - RW RW RW1s RW1s 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 TXTRIG[1:0] RXTRIG[1:0] TXWRBITW[ 1:0] RXRDBITW[ 1:0] TXMAP[1:0] RXMAP[1:0] RXM ODE RXO VFIE TXT RIGI E RXT RIGI E RW RW RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 20 Reserved -

19 TXFEN TX FIFO Enable Bit

0: Disable 1: Enable Note: Every FIFO switch will automatically perform a Reset operation.

18 RXFEN RX FIFO Enable Bit

0: Disable 1: Enable Note: Every FIFO switch will automatically perform a Reset operation.

17 TXFRST TX FIFO Reset Control Bit

TXFRST is set to 1 that can reset TX FIFO, cleared by hardware

16 RXFRST RX FIFO Reset Control Bit

RXFRST is set to 1 that can reset RX FIFO, cleared by hardware 15 ~ 14 TXTRIG[1:0] TX FIFO Trigger Level configuration 00: TX FIFO <= 1/4 full 01: TX FIFO <= 1/2 full 10: TX FIFO <= 3/4 full 11: TX FIFO empty 13 ~ 12 RXTRIG[1:0] RX FIFO Trigger Level configuration 00: RX FIFO >= 1/4 full 01: RX FIFO >= 1/2 full 10: RX FIFO >= 3/4 full 11: RX FIFO has a data at least. 11 ~ 10 TXWRBITW[1:0] The depth of TX FIFO 0: 8 bits 1: 16 bits 2: 32bits 3: Reserved 9 ~ 8 RXRDBITW[1:0] The depth of RX FIFO 0: 8 bits 1: 16 bits 2: 32bits 3: Reserved 7 ~ 6 TXMAP[1:0] TX FIFO Peripheral selection bit 00: UART0 01: UART1 10: UART2 11: Reserved Note: 8-byte FIFO is suitable for SPI, but 4-byte FIFO is not suitable for SPI.

5 ~ 4 RXMAP[1:0] RX FIFO Peripheral selection bit 00: UART0 01: UART1 10: UART2 11: Reserved Note: 8-byte FIFO is suitable for SPI, but 4-byte FIFO is not suitable for SPI.

3 RXMODE RX FIFO width Selection bit

0: 8bits Mode 1: (8+N)bits Mode Note: When the FIFO is used for UART, this bit is valid; When the FIFO is used for SPI, this bit is invalid.

2 RXOVFIE RX FIFO overwrite error interrupt enable bit

0: Disable 1: Enable

1 TXTRIGIE TX FIFO trigger level enable bit

0: Disable 1: Enable

0 RXTRIGIE RX FIFO trigger level enable bit

0: Disable 1: Enable

23.4.5 FIFO8L Register

FIFO8L Module Register List (Base Address: 0x4000 4C00) Address Register Name Description 0x4000 4C00 FR FIFO interrupt and status register 0x4000 4C04 CR FIFO control register

23.4.5.1 FIFO Interrupt and Status Register (FIFO8L_FR)

Offset Address: 0x0000 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved RXO VFC TXT RIGF C RXT RIGF C - WO WO WO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Reserved TXF ULL RXF ULL TXE MPT RXE MPT Rese rved RXO VF TXT RIGF RXT RIGF - RO RO RO RO - RO RO RO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 19 Reserved - 15 ~ 8 Reserved -

23.4.5.2 FIFO Control Register (FIFO8L_CR)

Offset Address: 0x0004 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved TXF EN RXF EN TXF RST RXF RST - RW RW RW1s RW1s 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 TXTRIG[1:0] RXTRIG[1:0] TXWRBITW[ 1:0] RXRDBITW[ 1:0] TXMAP[1:0] RXMAP[1:0] RXM ODE RXO VFIE TXT RIGI E RXT RIGI E RW RW RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 20 Reserved - 0: Disable 1: Enable Note: Every FIFO switch will automatically perform a Reset operation. 0: Disable 1: Enable Note: Every FIFO switch will automatically perform a Reset operation. TXFRST is set to 1 that can reset TX FIFO, cleared by hardware RXFRST is set to 1 that can reset RX FIFO, cleared by hardware 15 ~ 14 TXTRIG[1:0] TX FIFO Trigger Level configuration 00: TX FIFO <= 1/4 full 01: TX FIFO <= 1/2 full 10: TX FIFO <= 3/4 full 11: TX FIFO empty 13 ~ 12 RXTRIG[1:0] RX FIFO Trigger Level configuration 00: RX FIFO >= 1/4 full 01: RX FIFO >= 1/2 full 10: RX FIFO >= 3/4 full 11: RX FIFO has a data at least. 11 ~ 10 TXWRBITW[1:0] The depth of TX FIFO 0: 8 bits 1: 16 bits 2: 32bits 3: Reserved 9 ~ 8 RXRDBITW[1:0] The depth of RX FIFO 0: 8 bits 1: 16 bits 2: 32bits 3: Reserved 7 ~ 6 TXMAP[1:0] TX FIFO Peripheral selection bit 00: UART0 01: UART1 10: UART2 11: SPI Note: 8-byte FIFO is suitable for SPI, but 4-byte FIFO is not suitable for SPI.

5 ~ 4 RXMAP[1:0] RX FIFO Peripheral selection bit 00: UART0 01: UART1 10: UART2 11: SPI Note: 8-byte FIFO is suitable for SPI, but 4-byte FIFO is not suitable for SPI. 0: 8bits Mode 1: (8+N)bits Mode Note: When the FIFO is used for UART, this bit is valid; When the FIFO is used for SPI, this bit is invalid. 0: Disable 1: Enable 0: Disable 1: Enable 0: Disable 1: Enable

1. CAN Controller

24.1 Overview

The CAN Controller implements a Full-CAN class, CAN serial bus interface controller for low/high speed applications, compliant with the CAN Specification Version 2.0 Part B. According to this specification, the CAN Controller fully supports the reception and transmission of extended frames with a 29-bit identifier as well as standard frames with an 11-bit identifier. The CAN Controller supports applications which require high speed (up to 1MBit/s) as well as low speed CAN operation with CAN master capability. The data transfer between CAN and the CPU is established by 15 message buffers, which can be individually configured as receive or transmit buffers. Every message buffer includes a status/control register which provides information about its current status and capabilities to configure the buffer. All message buffers are able to generate an interrupt upon the reception of a valid frame or the successful transmission of a frame. In addition, an interrupt on bus errors can be generated. An incoming message is only accepted if the message identifier passes one of two acceptance filtering masks. This filtering mask can be either configured to receive a single message ID per buffer or a group of IDs per receive buffer. One of the buffers uses a separate message filtering procedure. This provides the capability to establish a Basic-CAN path. Remote transmission requests can be processed fully automatically by automatic reconfiguration to a receiver after transmission or by automated transmit scheduling upon reception. A priority decoder allows every buffer to have one of 16 transmit priorities, including the highest or lowest absolute priority. This totals to 240 different transmit priorities. A 16-bit time stamp counter is provided to support real-time applications. The contents of this counter is captured into the message buffer RAM upon reception or transmission. The counter can be synchronized via the CAN network. This synchronization feature allows the counter to be reset after reception or transmission of a message in buffer 0.The CAN Controller has an APB peripheral bus interface. The CPU controls the CAN Controller by modifying the various registers in the CAN Controller register block. This includes CAN baud rate initialization, CAN pin logic level, and enabling/disabling of the CAN Controller. A set of diagnostic features, like loopback, listen only, and error identification support the development with the CAN Controller and provide a sophisticated error management tool.

24.2 Features

The CAN Controller implements the following features:  Compliant to CAN Specification 2.0.B  Standard data and remote frames  Extended data and remote frames  0 - 8 bytes data length  programmable bit rate up to 1 Mbit/sec  15 message buffers, each configurable as a receive or transmit buffer  Message buffers are 16-bit oriented as dual-port RAM  One buffer may be used as Basic-CAN path  Remote Frame support  Automatic transmission after reception of a Remote Transmission Request (RTR)  Auto receive after transmission of an RTR  Acceptance filtering  Two filtering capabilities: global acceptance mask and individual buffer identifiers  One of the buffers uses an independent acceptance filtering procedure  Programmable transmit priority  Interrupt capability  One interrupt vector for all message buffers (receive/transmit/error)  Each interrupt source can be enabled/disabled  16-bit counter with time stamp capability on successful message reception or transmission  Push-pull capability of the input/output pins  Diagnostic functions  Error identification  Loopback and listen-only features for test and initialization purposes

24.3 Functional Description

As shown in Figure24-1, the CAN Controller is separated into three blocks: the CAN Core, Interface Management, and a RAM containing the message buffers. Figure24-1 CAN Controller Block Diagam

24.3.1 CAN Signals

The external and internal CAN transceiver pins are described inTable24-1. Table24-1 CAN Signals

24.3.2 CAN Core

The CAN Core implements CAN protocol features including bit-stuffing, CRC calculation/checking and error management. It controls the transceiver logic and creates error signals according to the bus rules. In addition, it converts the data stream from the CPU (parallel data) to the serial CAN bus data.

24.3.3 Interface Management

Interface management is performed by the register block and the interface management processor. The register block provides the CAN Controller with control information from the CPU and in turn provides the CPU with status information from the CAN Controller. Additionally, it generates the interrupt to the CPU. The interface management processor is a state machine executing the CPU’s transmission and reception commands and controlling data transfers between the several message buffers and RX/TX shift registers.

24.3.4 Message Buffer RAM

Fifteen message buffers are memory mapped into RAM to transmit/receive data through the CAN bus. Eight 16-bit registers belong to each buffer. One of the registers contains control and status information about the message buffer configuration and the current state of the buffer. The other registers are used for the message identifier, a maximum of up to eight data bytes, and the time stamp information. During the receive process, the incoming message is stored at first in a hidden receive buffer until the message is valid. Then the buffer contents are copied into the first message buffer that accepts the ID of the received message.

24.3.5 Clock Generator

The CAN prescaler (PSC) is shown isFigure24-2. It divides the pclk input clock by the value defined in the CTIM register. The resulting clock is called time quanta clock and defines the length of one time quanta (tq).Please refer to “CAN Timing Register (CTIM)” for a detailed description of the CTIM register. Figure24-2 Bit Rate Generation NOTE:PSC is the value of the clock prescaler. TSEG1 and TSEG2 are the length of time segment 1 and 2 in tq. The resulting bus clock can be calculated by the equation: The values of PSC and TSEG 1 and 2 are specified by the contents of the registers PSC, TSEG1, and TSEG2, as follows: PSC = PSC[6:0] + 2 TSEG1 = TSEG1[3:0] + 1 TSEG2 = TSEG2[2:0] + 1

24.4 Message Transfer

The CAN Controller has access to 15 independent message buffers, memory mapped in RAM. One message buffer consists of eight 16-bit RAM locations and can be individually configured as a receive message buffer or as a transmit message buffer. A dedicated acceptance filtering procedure enables the user to configure each buffer to receive only a single message ID or a group of messages. One buffer uses an independent filtering procedure which provides the possibility to establish a Basic-CAN path. For reception of data or remote frames, the CAN Controller follows a “receive on first match” rule, which means that a given message is only received by one buffer - the first one that matches the received message ID. The transmission of a frame can be initiated by the user’s software writing to the transmit status and priority register. An alternate way to schedule a transmission is the automatic answer to remote frames. In the latter case, the CAN Controller will schedule transmission for every buffer set up to respond to remote frames with a given identifier and where the acceptance mask passes. This implies that a single remote frame is able to poll multiple matching buffers configured to respond to the triggering remote transmission request.The functionality outlined above will be explained thoroughly in the following sections.

24.5 Acceptance Filtering

Two 32-bit masks are used to filter unwanted messages from the CAN bus GMASK and BMASK. Figure24-3 shows the mask and the buffers controlled. Acceptance filtering of the incoming messages for buffers 0...13 is done by means of a global filtering mask (GMASK) and by the buffer ID of each buffer. The acceptance filtering of incoming messages for buffer 14 is done via a separate filtering mask (BMASK) and by the buffer ID of that buffer.

24.5.1 Filter for Buffers 0 to 13

Once a received object is waiting in the hidden buffer (see “Receive Buffer Structure”) to be copied into a buffer, the CAN Controller scans all buffers configured as receive buffers for a matching filtering mask. Buffers 0 to 13 are checked in ascending order beginning with buffer 0. The contents of the hidden buffer are copied into the first buffer with matching filtering mask. Figure24-3 Acceptance Filtering Structure Bits holding a “1” in the global filtering mask (GMASK) can be represented as a “don’t care” of the associated bit of each buffer identifier, regardless of whether the buffer identifier bit is “1” or “0”. This provides the capability to accept only a single ID per buffer or to accept a group of IDs. The following two examples illustrate the difference. EXAMPLE 1: ACCEPTANCE OF A SINGLE IDENTIFIER If the global mask is set to 0x00, the acceptance filtering of an incoming message is only determined by the individual buffer ID. This means that only one message ID is accepted per buffer. Figure24-4 Acceptance Of A Single Idenfitier

EXAMPLE 2: RECEPTION OF AN IDENTIFIER GROUP Bits in the global mask register set to ’1’ change the corresponding bit status within the buffer ID to “don’t care” (“X”). Therefore, all messages which match the non-“don’t care” bits are accepted. Figure24-5 Acceptance Of A Group Of Identifiers

24.5.2 Filter for Buffer 14

A separate filtering path is used for buffer 14. For this buffer, acceptance filtering is established by the buffer ID in conjunction with the basic filtering mask. This basic mask uses the same method as the global mask. Setting a bit to “1” changes the associated bit in the buffer ID to a “don’t care” bit. Therefore, the basic mask allows a large number of infrequent messages to be received by this buffer. NOTE:If the BMASK register is equal to the GMASK register, buffer 14 can be used the same way as buffers 0 to 13. Buffers 0 to 13 are scanned prior to buffer 14. Subsequently, buffer 14 will not be checked for a matching ID in case one of buffers 0 to 13 has already received an object.

24.5.3 BUFFLOCK Function

By setting the BUFFLOCK bit in the configuration register, the receiving buffer is automatically locked after reception of one valid frame. The buffer will be unlocked again after the CPU has read the data and has written RX_READY in the buffer status field. With this lock function the user has the capability to save several messages with the same identifier or same identifier group into more than one buffer. In this case, for example, a buffer with the second highest priority will receive a message, if the buffer with the highest priority has already received a message and is now locked (provided that both buffers use the same acceptance filtering mask). As shown inFigure24-6, several messages with the same ID are received while BUFFLOCK is enabled. The filtering mask of buffers 0, 1, 13, and 14 is set to accept this message. The first incoming frame will be received by buffer 0. As buffer 0 is now locked, the next frame will be received by buffer 1, and so on. If all matching receive buffers are full and locked, a further incoming message will not be received by any buffer. Figure24-6 Message Storage With Bufflock Enabled

24.5.4 Receive Structure

All received frames will first be buffered in a hidden receive buffer until the frame is valid. (The validation point for a received message is the penultimate bit of EOF.) The received identifier is then compared to every buffer ID together with the respective mask and the status. As soon as the validation point is reached, all contents of the hidden buffer are copied into the matching message buffer, as shown in Figure24-7. NOTE: The hidden receive buffer must not be accessed by the CPU while the CAN Controller is enabled. Write accesses are forbidden when the CAN Controller is enabled.

Figure24-7 Receive Buffer Staructure

24.5.5 Data Frame

The received data frame is stored in the first matching receive buffer, beginning with buffer 0. If the message is, for example, accepted by buffer 5 at the time the message will be copied, the RX request is cleared and CAN Controller does not try to match the frame to any further buffer. All contents of the hidden receive buffer are always copied into the respective receive buffer. This includes the received message ID as well as the received Data Length Code (DLC). NOTE: When some mask bits are set to “don’t care”, the received ID overwrites the message ID currently within the receive buffer. The DLC of the receiving buffer will be updated by the DLC of the received frame. The DLC of the received message is not compared with the DLC already present in the CNSTAT register of the message buffer. This implies that the DLC code of the CNSTAT register indicates how many data bytes actually belong to the latest received message.

24.5.6 Remote Frame

There are two ways remote frames are handled by the CAN Controller. Firstly, remote frames can be received like data frames by configuring the buffer to be RX_READY and setting the ID bits, including the RTR bit. In that case, the same procedure applies as described under “Data Frame”. Secondly, a remote frame can trigger one or more message buffers to transmit a data frame upon reception. This procedure is described under “Answering to Remote Frames”

24.5.7 Receive Timing

As soon as the CAN Controller receives a dominant bit on the CAN bus, the receive process is started. The received ID and data will be stored in the hidden receive buffer, if the global or basic acceptance filtering matches. After the reception of the data, the CAN Controller tries to match the buffer ID of buffers 0...14. The data will be copied into the buffer after the reception of the 6th EOF bit, as a message is valid at this time. The copy process of every frame, regardless of the length, takes at least 17 pclk cycles (see also “CPU Access to CAN Registers/Memory” ).Figure24-8 illustrates receive timing).

In order to indicate that a frame is waiting in the hidden buffer, the BUSY bit ST[0] of the selected buffer is set during the copy procedure. The BUSY bit will be cleared by the CAN Controller right after the data bytes are copied into the buffer. After the copy process is finished, the CAN Controller changes the status field to RX_FULL. In turn the CPU should change the status field to RX_READY when the data is processed. When a new object has been received by the same buffer, before the CPU changes the status to RX_READY, the CAN Controller will change the status to RX_OVERRUN to indicate that at least one frame has been overwritten by a new one. Table24-2 summarizes the current status and the resulting update from the CAN Controller. Table24-2 Writing To Buffer Status Code During RX_BUSY During the assertion of the BUSY bit, all writes to the receiving buffer are disabled, with the exception of the status field. If the status is changed while BUSY is active, the status is updated by the CAN Controller as shown in Table24-2.Buffer states are indicated and controlled by the ST[3:0] bits in the CNSTAT register. (See “Buffer Status/Control Register (CNSTAT)”. The various receive buffer states are explained in “RX Buffer States”.)

24.5.8 Receive Procedure

The user has to execute the following procedure to initialize a message buffer for the reception of a CAN message: 1. Configure the receive masks (GMASK or BMASK, respectively). 2. Configure the buffer ID. 3. Configure the message buffer status as RX_READY. In order to read out a received message the CPU has to execute the following steps (see Figure24-9). NOTE:The first step is only applicable if polling is used to get the status of the receive buffer. The first step can be omitted for an interrupt driven receive routine. 1. Read the status (CNSTAT) of the receive buffer. If status is RX_READY - no was message received - exit. If status is RX_BUSY - copy process from hidden receive buffer is not completed yet - read CNSTAT again. If a buffer is configured to RX_READY and its interrupt is enabled it will generate an interrupt as soon as the buffer has received a message and entered the RX_FULL state (see also “Interrupts”). In that case, the procedure described below should be followed. 2.The status may be read at this stage to indicate whether a new message has overwritten the originally received one, which triggered the interrupt. 3. Write RX_READY into CNSTAT. 4. Read the ID/data and object control (DLC/RTR) from the message buffer. 5. Read the buffer status again and check it is not RX_BUSYx. If it is, repeat this step until RX_BUSYx has gone away. 6.If the buffer status is RX_FULL or RX_OVERRUN, one or more new messages were copied. In that case, start over with step 2. 7.If status is still RX_READY (as set by the CPU at step 2), then clear the interrupt pending bit and exit.

Figure24-9 Buffer Read Routine (BUFFLOCK Disabled) When the BUFFLOCK function is enabled (see “BUFFLOCK Function”), it is not necessary to check for new messages received during the read process from the buffer, as this buffer is locked after the reception of the first valid frame. A read from a locked receive buffer can be performed as shown in Figure24-10. (For simplicity, only the applicable interrupt routine is shown.) 1.Read the ID/data and object control (DLC/RTR) from the message buffer. 2.Write RX_READY into CNSTAT. 3.Clear the interrupt pending bit and exit.

Figure24-10 Buffer Read Routine (BUFFLOCK Enabled)

24.5.9 RX Buffer States

As shown in Figure24-11, a receive procedure can start as soon as the user has set the buffer from the RX_NOT_ACTIVE state to the RX_READY state. The status section of CNSTAT register is set from 0000b to 0010b. When a message is received, the buffer is RX_BUSYx during the copy process from the hidden receive buffer into the message buffer. Afterwards this buffer is RX_FULL. Now the CPU can either read the buffer data and reset the buffer status to RX_READY, or a new frame will be received before the CPU reads the buffer. In the second case, the buffer state will automatically change to RX_OVERRUN to indicate that at least one message was lost. During the copy process, the buffer will again be RX_BUSYx for a short time, but in this case the CNSTAT status section will be 0101b, as the buffer was RX_FULL (0100b) before. After finally reading the last received message, the CPU can reset the buffer to RX_READY.

Figure24-11 Receive Buffer States

24.6 Transmit Structure

In order to transmit a CAN message, the user has to configure the message buffer by changing the buffer status to TX_NOT_ACTIVE. The buffer is configured for transmission if the ST[3]-bit of the buffer status code (CNSTAT) is set to ‘1’. In TX_NOT_ACTIVE status the buffer is ready to receive data from the CPU. After receiving all transmission data (ID, data bytes, DLC and PRI) the CPU can start the transmission by writing TX_ONCE into the buffer status register. During transmission, the status of the buffer is TX_BUSYx. After successful transmission, the CAN Controller resets the buffer status to TX_NOT_ACTIVE. When the transmission process fails, the buffer condition remains TX_BUSYx for re-transmission until the frame is successfully transmitted or the CPU cancels the transmission request.

24.6.1 Sending Remote Frames

In order to send a Remote Transmission Request (Remote Frame) to other CAN nodes, the user needs to set the RTR bit of the message identifier to “1” (see “Storage of Remote Messages”) and change the status of the message buffer to TX_ONCE. After this remote frame has been transmitted successfully, this message buffer will automatically enter the RX_READY state and is ready to receive the appropriate answer. Note that the mask’s RTR/XRTR bits need to be set to receive a data frame (RTR = 0) in a buffer which was configured to transmit a remote frame (RTR = 1).

24.6.2 Answering to Remote Frames

If the CPU writes TX_RTR in the buffer status register, the buffer waits for a remote frame. When a remote frame passes the acceptance filtering mask of one or more buffers, the buffer status changes to TX_ONCE_RTR, the buffer contents are transmitted, and afterwards, the CAN Controller writes TX_RTR in the status code register again.If the CPU writes TX_ONCE_RTR in the buffer status, the buffer contents are transmitted, and after successful transmission, the buffer goes into the “wait for Remote Frame” condition, TX_RTR.

24.6.3 Transmit Scheduling

After writing TX_ONCE in the buffer status, transmission begins and the BUSY bit is set. As soon as a buffer is in the TX_BUSY status, the buffer is no longer accessible for the CPU, except for the ST[3:1] bits of the CNSTAT register. With the beginning of the CRC field of the current frame, the CAN Controller looks for another buffer transmit request, and selects the buffer with the highest priority for the next transmission by changing the buffer state from TX_ONCE to TX_BUSY. This transmit request can be canceled by the CPU or can be overwritten by another transmit request of a buffer with a higher priority as long as the transmission of the next frame has not yet started. This means, between the beginning of the CRC field of the current frame and the transmission start of the next frame, two buffers, the current buffer and the buffer currently scheduled for the next transmission, are in BUSY status. In order to cancel the transmit request of the next frame, the CPU has to change the buffer state to TX_NOT_ACTIVE. When the transmit request has been overwritten by another request of a higher priority buffer, the CAN Controller changes the buffer state from TX_BUSY to TX_ONCE. Thus, the transmit request remains pending. 错误！未找到引用源。 further illustrates transmission timing. Figure24-12 Data Transmission

If transmission fails or arbitration is lost, transmission stops, and continues after the interrupting reception or error signaling has finished (seeFigure24-13). In that case, a new buffer select follows and transmission is executed again. NOTE:The canceled message can be delayed by a TX request of a buffer with a higher priority. When TX_BUSY is high, the user can not change the contents of the message buffer object. In all cases, writing to the BUSY bit will be ignored. Figure24-13 Lost Arbitration During Data Transmission

24.6.4 Transmit Priority

The CAN Controller is able to generate a stream of scheduled messages without releasing the bus between two messages so that performance can be optimized. It will arbitrate for the bus right after sending the previous message and will only release the bus in case of a lost arbitration. If more than one buffer is scheduled for transmission, the priority is built by the message buffer number and the priority code in the CNSTAT register. The 8-bit value of the priority is combined by the 4-bit TXPRI value and the 4-bit buffer number Figure24-14 Transmit Priority Coding EXAMPLE 3: TRANSMIT PRIORITY CONFIGURATION WHEN PRIORITY IS SET TO TXPRI = 0 FOR ALL BUFFERS Table24-3 Transmit Priority (TXPRIO=0) EXAMPLE 4: TRANSMIT PRIORITY CONFIGURATION WHEN TXPRI IS DIFFERENT THAN THE BUFFER NUMBER

Table24-4 Transmit Priority (TXPRIO NOT 0)

24.6.5 Transmit Procedure

The transmission of a CAN message has to be executed as follows (see also Figure24-15). 1. Configure CNSTAT status field as TX_NOT_ACTIVE. If the status is TX_BUSY, a previous transmit request is still pending and the user has no access to the data contents of the buffer. In that case, the user may choose to wait until the buffer becomes available again as shown. Other options are to exit from the update routine until the buffer data has been transmitted and an interrupt is generated, or the transmission is aborted due to an error. 2. Load buffer identifier and data registers.(For remote frames, the RTR bit of the identifier should be set and loading data bytes can be omitted.) 3. Configure CNSTAT status field to the desired value: TX ONCE: to trigger the transmission process of a single frame. TX_ONCE_RTR: to trigger the transmission of a single data frame and then wait for a received remote frame to trigger consecutive data frames. TX_RTR: to wait for a remote frame to trigger the transmission of a data frame. Writing TX_ONCE or TX_ONCE_RTR in the CNSTAT status field will set the internal transmit request for the CAN Controller. If a buffer is configured as TX_RTR and a remote frame is received, the data contents of the addressed buffer will be transmitted automatically without further CPU activity.

Figure24-15 Buffer Write Routine

24.6.6 TX Buffer States

Transmission can begin after the user has loaded the buffer registers (data, ID, DLC, PRI) and set the buffer status from TX_NOT_ACTIVE to TX_ONCE, TX_RTR, or TX_ONCE_RTR. When the CPU writes TX_ONCE, the buffer becomes TX_BUSY as soon as the CAN Controller has scheduled this buffer for the next transmission. After the frame is successfully transmitted, the buffer status is automatically reset to TX_NOT_ACTIVE when a data frame is transmitted or to RX_READY for a remote frame transmission. When the CPU configures the message buffer to TX_ONCE_RTR, the message buffer first transmits its data contents. During transmission, the buffer state is 1111b, as the CPU wrote 1110b into the status section of the CNSTAT register. After successful transmission, the buffer enters the TX_RTR state and waits for a remote frame. When the message buffer receives a remote frame, it goes back to the TX_ONCE_RTR state, transmits its data bytes, and returns to TX_RTR. If the CPU writes 1010b into the buffer status section, the message buffer enters the TX_RTR state, but does not send its data bytes before waiting for a remote frame. Figure24-16 illustrates the possible transmit buffer states.

Figure24-16 Transmit Buffer States

24.7 Interrupts

24.7.1 Conditions

The CAN Controller has access to one interrupt vector in the CPU. The interrupt process can be initiated from the following sources:  CAN data transfer (1) Reception of a valid data frame in the buffer (Buffer state changes from RX_READY to RX_FULL or RX_OVERRUN.) (2) Successful transmission of a data frame (Buffer state changes from TX_ONCE to TX_NOT_ACTIVE or RX_READY.) (3) Successful response to a remote frame (Buffer state changes from TX_ONCE_RTR to TX_RTR.) (4) Transmit scheduling (Buffer state changes from TX_RTR to TX_ONCE_RTR.)  CAN error conditions (1) •Detection of a CAN error (The CEIPND bit in the CIPND register is set as well as the corresponding bits in the error diagnostic register CEDIAG.) The receive/transmit interrupt access to every message buffer can be individually enabled/disabled in the CIEN register. The pending flags of the message buffer are located in the CIPND register (read only) and can be cleared by resetting the flags in the CICLR registers.

24.7.2 Highest Priority Interrupt Code

In order to reduce decoding time of the CIPND register, the buffer interrupt request with the highest priority is placed as interrupt status code into the IST[3:0] section of the CSTPND register. A detailed description of the CAN Controller interrupt registers is given in “Registers”. Each of the buffer interrupts as well as the error interrupt can be individually enabled or disabled in the CAN Interrupt Enable register (CIEN). As soon as an interrupt condition occurs, every interrupt request is indicated by a flag in the CAN Interrupt Pending register (CIPND). When the interrupt code logic for the currently highest priority interrupt request is enabled, this interrupt will be translated into the IST[3:0] bits of the CAN Status Pending register (CSTPND). An interrupt request can be cleared by setting the corresponding bit in the CAN Interrupt Clear register (CICLR) to ‘1’. Figure24-17 illustrates the CAN Controller interrupt management. Figure24-17 CAN Interrupt Management

The highest priority interrupt source is translated into bits IRQ and IST[3:0] as shown inTable24-5 Table24-5 Highest Priority Interrupt Code(ICEN=0xFFFF)  Usage Hints The code section IST[3:0] can for example be used within the interrupt handler as a displacement in order to jump to the relevant subroutine. The CAN Interrupt Code Enable (CICEN) register can for example be utilized in the CAN interrupt handler, if the user first wants to service all receive buffer interrupts and afterwards all transmit buffer interrupts. In such a case, the user can first enable only all receive buffer interrupts to be coded, scan, and service all pending interrupt requests in the order of their priority. Then, the user changes the CICEN register to disable all receive buffers, but enables all transmit buffers and services all pending transmit buffer interrupt requests according their priority.

24.8 Time Stamp Counter

The CAN Controller features a free-running, 16-bit timer (CTMR), incrementing every bit time recognized on the CAN bus. The value of this timer during the ACK slot is captured into the TSTP register of a message buffer after a successful transmission or reception of a message.Figure24-18 shows a simplified block diagram of the Time Stamp Counter. Figure24-18 Time Stamp Counter The timer can be synchronized over the CAN network by receiving or transmitting a message to/from buffer 0. In that case, the TSTP register of buffer 0 captures the current CTMR value during the ACK slot of a message (as above) and afterwards the CTMR is reset to 0x0000. Synchronization can be enabled or disabled via the CGCR.TSTAMP bit.

24.9 Memory Organization

The CAN Controller occupies 144 half-words (16 bits) in the memory address space. This space is separated into 15 * 8 + 8 (reserved) words for the message buffers and 14 + 2 (reserved) words for control and status. These 144 words are 32-bit aligned. (CPU APB access is 32-bit word only; the upper 16 bits are not used.) For a detailed CAN Controller memory map, please refer to “Memory Map”

24.9.1 CPU Access to CAN Registers/Memory

All memory locations occupied by the message buffers are shared by the CPU and the CAN Controller (dual-port RAM). The CAN Controller and CPU have nominal single cycle access to this memory, with the CPU having priority. However, if access contention occurs, access to the memory is altered for every cycle until the contention is resolved. This internal access arbitration is transparent for the user. If a buffer is busy during the reception of an object (copy process from the hidden receive buffer) or is scheduled for transmission, the CPU has no write access to the data contents of the buffer. Writes to the status/control byte and read access to the whole buffer are always enabled. All configuration and status registers can either be accessed by the CAN Controller or the CPU only. These registers provide single cycle fixed width access without any potential wait state.

24.9.2 Register Layout

All register descriptions within the next sections utilize the following layout. The upper word is always unused.

24.9.3 Message Buffer Organization

The message buffers are the communication interface between CAN and the CPU for the transmission and the reception of CAN frames. There are 15 message buffers located at fixed addresses in the RAM location. As shown in Table24-6, each buffer consists of 2 words reserved for the identifiers, 4 words reserved for up to 8 CAN data bytes, 1 word reserved for time stamp and 1 word for data length, transmit priority, and buffer status codes. Table24-6 Message Buffer Orgamization

24.9.4 Buffer Status/Control Register (CNSTAT)

The buffer status, the buffer priority and the data length code are controlled by manipulating the contents of the Buffer Status/Control Register. The CPU and CAN Controller have access to this register. ST[3:0] Buffer Status -- The CNSTAT register has a status section, which contains the status information of the buffer as shown in Table24-7. This section can be modified by the CAN Controller.

Table24-7 Buffer Status Section Of The CNSTAT Register 1.This condition indicates that the user wrote RX_NOT_ACTIVE to a buffer where the data copy process is still active. 2.RX_BUSYx indicates that copying is in progress at three possible times: - data is copied for the first time RX_READY -> RX_BUSY0 - data is copied for the second time RX_FULL -> RX_BUSY1 - data is copied for the third or more time RX_OVERRUN -> RX_BUSY2 3.This state indicates that the user wrote TX_NOT_ACTIVE to a transmit buffer which is scheduled for transmission or currently transmitting. 4.TX_BUSYx indicates that a buffer is scheduled for transmission or is actively transmitting; it can be one of two states: - a message is pending for transmission or is currently transmitting - an automated answer is pending for transmission or is currently transmitting 5.This condition does not occur. The ST[0] bit acts as a buffer busy indication. When the BUSY bit is set, any write access to the buffer is disabled with the exception of the lower byte of the CNTSTAT register. The CAN Controller sets this bit if the buffer data is currently being copied from the hidden buffer or if a message is scheduled for transmission or currently transmitting. The CAN Controller will always reset this bit on a status update. PRI[3:0] Transmit Priority Code -- The PRI[3:0] bits contain the user-defined transmit priority code for the message buffer.

DLC[3:0] Data Length Code -- The DLC[3:0] bits determine the number of data bytes within a received/transmitted frame. For transmission, these bits should be set according to the number of data bytes to be transmitted. In case of reception, these bits indicate the number of valid received data bytes available in the message buffer.Table24-8 shows the possible bit combinations for DLC[3:0] for data lengths from 0 to 8 bytes. Table24-8 Data Length Coding NOTE:The maximum number of data bytes received/transmitted is 8, even if the data length code is set to a value greater than 8. Thus, if the data length code is greater than or equal to 8 bytes, the bits DLC[2] to DLC[0] are ignored.

24.9.5 Storage of Standard Messages

During processing standard frames the Extended-Identifier-bit (IDE) is set to “0”. The bits ID1[3:0], ID0[15:0] are “don’t care” bits. Table24-9 Standard Frame With 8 Data Bytes

Identifier Extension -- IDE is set to “0” to indicate that the message is a standard frame using 11 identifier bits. If IDE is set to “1”, the object stored in the buffer is handled as an extended frame. RTR Remote Transmission Request -- RTR is set to “1” to indicate that the message is a remote frame. For a data frame the RTR bit is set to “0”. ID[10:0] The ID buffer bits ID10 to ID0 are used for the 11 standard frame identifier bits. Storage of Messages With Less Than 8 Data Bytes The data bytes, which are not used for data transfer, are “don’t care’”. If the object is transmitted, the data within these bytes will be ignored. If the object is received, the data within these bytes will be overwritten with invalid data.

24.9.6 Storage of Extended Messages

If the IDE bit is set to “1”, the buffer handles extended frames. The storage of the extended ID follows the descriptions inTable24-10. The SRR replaces the RTR bit for standard frames and should be transmitted as “1”. Table24-10 Extended Messages With 8 Data Bytes SRR Substitute Remote Request -- SRR only replaces the RTR bit, used in standard frames at this position. The SRR bit should be set to “1” by the user if the buffer is configured to transmit a message with an extended identifier. It will be received as monitored on the CAN bus. IDE Identifier Extension -- IDE is set to “0” to indicate that the message is a standard frame using 11 identifier bits. If IDE is set to “1”, the object stored in the buffer is handled as an extended frame. RTR Remote Transmission Request -- RTR is set to “1” to indicate that the message is a remote frame. For a data frame, the RTR bit is set to “0”. ID[28:0] The ID bits 28 to 0 are used to build the 29-bit identifier of an extended frame.

24.9.7 Storage of Remote Messages

During remote frame transfer, the buffer registers DATA[3:0] are “don’t care”. If a remote frame is transmitted, the contents of these registers are ignored. If a remote frame is received, the contents of these registers are overwritten with invalid data. The structure of a message buffer set up for a remote frame with extended identifier is shown in Table24-11. Table24-11 Extended Remote Frame SRR Substitute Remote Request -- SRR only replaces the RTR bit, used in standard frames at this position. The SRR bit should be set to “1” by the user. IDE Identifier Extension -- IDE is set to “0” to indicate that the message is a standard frame using 11 identifier bits. If IDE is set to “1”, the object stored in the buffer is handled as an extended frame. RTR Remote Transmission Request -- RTR is set to “1” to indicate that the message is a remote frame. For a data frame, the RTR bit is set to “0”. ID[28:0] ID bits 28 to 0 are used to build the 29-bit identifier of an extended frame.ID1 buffer bits ID28 to ID18 are used for the 11 standard frame identifier bits.

24.10 Register

CAN Module Register List (Base Address:0x4000 2C00) Address Register Name Description 0x4000 2C00 BUF0_CNTSTAT Buffer 0 Status/Control Register 0x4000 2C04 BUF0_TSTP Buffer 0 Time Stamp Counter 0x4000 2C08 BUF0_DATA3 Buffer 0 Data 3 Register 0x4000 2C0C BUF0_DATA2 Buffer 0 Data 2 Register 0x4000 2C10 BUF0_DATA1 Buffer 0 Data 1 Register 0x4000 2C14 BUF0_DATA0 Buffer 0 Data 0 Register 0x4000 2C18 BUF0_ID0 Buffer 0 Indentifier 0 Register 0x4000 2C1C BUF0_ID1 Buffer 0 Indentifier 1 Register 0x4000 2C20 BUF1_CNTSTAT Buffer 1 Status/Control Register 0x4000 2C24 BUF1_TSTP Buffer 1 Time Stamp Counter 0x4000 2C28 BUF1_DATA3 Buffer 1 Data 3 Register 0x4000 2C2C BUF1_DATA2 Buffer 1 Data 2 Register 0x4000 2C30 BUF1_DATA1 Buffer 1 Data 1 Register 0x4000 2C34 BUF1_DATA0 Buffer 1 Data 0 Register 0x4000 2C38 BUF1_ID0 Buffer 1 Indentifier 0 Register 0x4000 2C3C BUF1_ID1 Buffer 1 Indentifier 1 Register 0x4000 2C40 BUF2_CNTSTAT Buffer 2 Status/Control Register 0x4000 2C44 BUF2_TSTP Buffer 2 Time Stamp Counter 0x4000 2C48 BUF2_DATA3 Buffer 2 Data 3 Register 0x4000 2C4C BUF2_DATA2 Buffer 2 Data 2 Register 0x4000 2C50 BUF2_DATA1 Buffer 2 Data 1 Register 0x4000 2C54 BUF2_DATA0 Buffer 2 Data 0 Register 0x4000 2C58 BUF2_ID0 Buffer 2 Indentifier 0 Register 0x4000 2C5C BUF2_ID1 Buffer 2 Indentifier 1 Register 0x4000 2C60 BUF3_CNTSTAT Buffer 3 Status/Control Register 0x4000 2C64 BUF3_TSTP Buffer 3 Time Stamp Counter 0x4000 2C68 BUF3_DATA3 Buffer 3 Data 3 Register 0x4000 2C6C BUF3_DATA2 Buffer 3 Data 2 Register 0x4000 2C70 BUF3_DATA1 Buffer 3 Data 1 Register 0x4000 2C74 BUF3_DATA0 Buffer 3 Data 0 Register 0x4000 2C78 BUF3_ID0 Buffer 3 Indentifier 0 Register 0x4000 2C7C BUF3_ID1 Buffer 3 Indentifier 1 Register 0x4000 2C80 BUF4_CNTSTAT Buffer 4 Status/Control Register 0x4000 2C84 BUF4_TSTP Buffer 4 Time Stamp Counter 0x4000 2C88 BUF4_DATA3 Buffer 4 Data 3 Register 0x4000 2C8C BUF4_DATA2 Buffer 4 Data 2 Register 0x4000 2C90 BUF4_DATA1 Buffer 4 Data 1 Register 0x4000 2C94 BUF4_DATA0 Buffer 4 Data 0 Register 0x4000 2C98 BUF4_ID0 Buffer 4 Indentifier 0 Register 0x4000 2C9C BUF4_ID1 Buffer 4 Indentifier 1 Register 0x4000 2CA0 BUF5_CNTSTAT Buffer 5 Status/Control Register 0x4000 2CA4 BUF5_TSTP Buffer 5 Time Stamp Counter 0x4000 2CA8 BUF5_DATA3 Buffer 5 Data 3 Register 0x4000 2CAC BUF5_DATA2 Buffer 5 Data 2 Register 0x4000 2CB0 BUF5_DATA1 Buffer 5 Data 1 Register 0x4000 2CB4 BUF5_DATA0 Buffer 5 Data 0 Register 0x4000 2CB8 BUF5_ID0 Buffer 5 Indentifier 0 Register 0x4000 2CBC BUF5_ID1 Buffer 5 Indentifier 1 Register 0x4000 2CC0 BUF6_CNTSTAT Buffer 6 Status/Control Register 0x4000 2CC4 BUF6_TSTP Buffer 6 Time Stamp Counter 0x4000 2CC8 BUF6_DATA3 Buffer 6 Data 3 Register 0x4000 2CCC BUF6_DATA2 Buffer 6 Data 2 Register

0x4000 2CD0 BUF6_DATA1 Buffer 6 Data 1 Register 0x4000 2CD4 BUF6_DATA0 Buffer 6 Data 0 Register 0x4000 2CD8 BUF6_ID0 Buffer 6 Indentifier 0 Register 0x4000 2CDC BUF6_ID1 Buffer 6 Indentifier 1 Register 0x4000 2CE0 BUF7_CNTSTAT Buffer 7 Status/Control Register 0x4000 2CE4 BUF7_TSTP Buffer 7 Time Stamp Counter 0x4000 2CE8 BUF7_DATA3 Buffer 7 Data 3 Register 0x4000 2CEC BUF7_DATA2 Buffer 7 Data 2 Register 0x4000 2CF0 BUF7_DATA1 Buffer 7 Data 1 Register 0x4000 2CF4 BUF7_DATA0 Buffer 7 Data 0 Register 0x4000 2CF8 BUF7_ID0 Buffer 7 Indentifier 0 Register 0x4000 2CFC BUF7_ID1 Buffer 7 Indentifier 1 Register 0x4000 2D00 BUF8_CNTSTAT Buffer 8 Status/Control Register 0x4000 2D04 BUF8_TSTP Buffer 8 Time Stamp Counter 0x4000 2D08 BUF8_DATA3 Buffer 8 Data 3 Register 0x4000 2D0C BUF8_DATA2 Buffer 8 Data 2 Register 0x4000 2D10 BUF8_DATA1 Buffer 8 Data 1 Register 0x4000 2D14 BUF8_DATA0 Buffer 8 Data 0 Register 0x4000 2D18 BUF8_ID0 Buffer 8 Indentifier 0 Register 0x4000 2D1C BUF8_ID1 Buffer 8 Indentifier 1 Register 0x4000 2D20 BUF9_CNTSTAT Buffer 9 Status/Control Register 0x4000 2D24 BUF9_TSTP Buffer 9 Time Stamp Counter 0x4000 2D28 BUF9_DATA3 Buffer 9 Data 3 Register 0x4000 2D2C BUF9_DATA2 Buffer 9 Data 2 Register 0x4000 2D30 BUF9_DATA1 Buffer 9 Data 1 Register 0x4000 2D34 BUF9_DATA0 Buffer 9 Data 0 Register 0x4000 2D38 BUF9_ID0 Buffer 9 Indentifier 0 Register 0x4000 2D3C BUF9_ID1 Buffer 9 Indentifier 1 Register 0x4000 2D40 BUF10_CNTSTAT Buffer 10 Status/Control Register 0x4000 2D44 BUF10_TSTP Buffer 10 Time Stamp Counter 0x4000 2D48 BUF10_DATA3 Buffer 10 Data 3 Register 0x4000 2D4C BUF10_DATA2 Buffer 10 Data 2 Register 0x4000 2D50 BUF10_DATA1 Buffer 10 Data 1 Register 0x4000 2D54 BUF10_DATA0 Buffer 10 Data 0 Register 0x4000 2D58 BUF10_ID0 Buffer 10 Indentifier 0 Register 0x4000 2D5C BUF10_ID1 Buffer 10 Indentifier 1 Register 0x4000 2D60 BUF11_CNTSTAT Buffer 11 Status/Control Register 0x4000 2D64 BUF11_TSTP Buffer 11 Time Stamp Counter 0x4000 2D68 BUF11_DATA3 Buffer 11 Data 3 Register 0x4000 2D6C BUF11_DATA2 Buffer 11 Data 2 Register 0x4000 2D70 BUF11_DATA1 Buffer 11 Data 1 Register 0x4000 2D74 BUF11_DATA0 Buffer 11 Data 0 Register 0x4000 2D78 BUF11_ID0 Buffer 11 Indentifier 0 Register 0x4000 2D7C BUF11_ID1 Buffer 11 Indentifier 1 Register 0x4000 2D80 BUF12_CNTSTAT Buffer 12 Status/Control Register 0x4000 2D84 BUF12_TSTP Buffer 12 Time Stamp Counter 0x4000 2D88 BUF12_DATA3 Buffer 12 Data 3 Register 0x4000 2D8C BUF12_DATA2 Buffer 12 Data 2 Register 0x4000 2D90 BUF12_DATA1 Buffer 12 Data 1 Register 0x4000 2D94 BUF12_DATA0 Buffer 12 Data 0 Register 0x4000 2D98 BUF12_ID0 Buffer 12 Indentifier 0 Register 0x4000 2D9C BUF12_ID1 Buffer 12 Indentifier 1 Register 0x4000 2DA0 BUF13_CNTSTAT Buffer 13 Status/Control Register 0x4000 2DA4 BUF13_TSTP Buffer 13 Time Stamp Counter 0x4000 2DA8 BUF13_DATA3 Buffer 13 Data 3 Register 0x4000 2DAC BUF13_DATA2 Buffer 13 Data 2 Register 0x4000 2DB0 BUF13_DATA1 Buffer 13 Data 1 Register

0x4000 2DB4 BUF13_DATA0 Buffer 13 Data 0 Register 0x4000 2DB8 BUF13_ID0 Buffer 13 Indentifier 0 Register 0x4000 2DBC BUF13_ID1 Buffer 13 Indentifier 1 Register 0x4000 2DC0 BUF14_CNTSTAT Buffer 14 Status/Control Register 0x4000 2DC4 BUF14_TSTP Buffer 14 Time Stamp Counter 0x4000 2DC8 BUF14_DATA3 Buffer 14 Data 3 Register 0x4000 2DCC BUF14_DATA2 Buffer 14 Data 2 Register 0x4000 2DD0 BUF14_DATA1 Buffer 14 Data 1 Register 0x4000 2DD4 BUF14_DATA0 Buffer 14 Data 0 Register 0x4000 2DD8 BUF14_ID0 Buffer 14 Indentifier 0 Register 0x4000 2DDC BUF14_ID1 Buffer 14 Indentifier 1 Register 0x4000 2E00 CGCR CAN GlobalConfiguration Register 0x4000 2E04 CTIM CAN Timing Register 0x4000 2E08 GMSKX Global mask Register Extend 0x4000 2E0C GMSKB Global mask Register Base 0x4000 2E10 BMSKX Basic Mask Register Extend 0x4000 2E14 BMSKB Global mask Register Base 0x4000 2E18 CIEN CAN Interrupt Enable Register 0x4000 2E1C CIPND CAN Interrupt Pending Register 0x4000 2E20 CICLR CAN Interrupt Clear Register 0x4000 2E24 CICEN CAN Interrupt Code Enable Register 0x4000 2E28 CSTPND CAN Status Pending Register 0x4000 2E2C CANEC CAN Error Counter Register 0x4000 2E30 CEDIAG CAN Error Diagnostic Register 0x4000 2E34 CTMR CAN Timer Register

24.10.1 Buffer n Status/Control Register (CAN_BUFn_CNTSTAT)(n=0..14) Offset Address: 0x0000 :0x0020 :0x0040 :0x0060 :0x0080 :0x00A0 :0x00C0 :0x00E0 :0x0100 :0x0120 :0x0140 :0x0160 :0x0180 :0x01A0 :0x01C0 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 DLC[3:0] Reserved PRI[3:0] ST[3:0] RW - RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Name Description 31 ~ 16 Reserved - 15 ~ 12 DLC[3:0] Data Length Code 11 ~ 8 Reserved - 7 ~ 4 PRI[3:0] Transmit Priority Code 3 ~ 0 ST[3:0] Buffer Status, ( See Buffer Status/Control Register (CNSTAT))

24.10.2 Buffer n Time Stamp Counter (CAN_BUFn_TSTP)(n=0..14) Offset Address: 0x0004 :0x0024 :0x0044 :0x0064 :0x0084 :0x00A4 :0x00C4 :0x00E4 :0x0104 :0x0124 :0x0144 :0x0164 :0x0184 :0x01A4 :0x01C4 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 TSTP[15:0] RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Name Description 31 ~ 16 Reserved - 15 ~ 0 TSTP[15:0] Capture the current CTMR value 24.10.3 Buffer n Data 3 Register (CAN_BUFn_DATA3)(n=0..14) Offset Address: 0x0008 :0x0028 :0x0048 :0x0068 :0x0088 :0x00A8 :0x00C8 :0x00E8 :0x0108 :0x0128 :0x0148 :0x0168 :0x0188 :0x01A8 :0x01C8 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 DATAH[7:0] DATAL[7:0] RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

31 ~ 16 Reserved - 15 ~ 8 DATAH[7:0] Data 7 7 ~ 0 DATAL[7:0] Data 8 24.10.4 Buffer n Data 2 Register (CAN_BUFn_DATA2)(n=0..14) Offset Address: 0x000C :0x002C :0x004C :0x006C :0x008C :0x00AC :0x00CC :0x00EC :0x010C :0x012C :0x014C :0x016C :0x018C :0x01AC :0x01CC Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 DATAH[7:0] DATAL[7:0] RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Name Description 31 ~ 16 Reserved - 15 ~ 8 DATAH[7:0] Data 5 7 ~ 0 DATAL[7:0] Data 6

24.10.5 Buffer n Data 1 Register (CAN_BUFn_DATA1)(n=0..14) Offset Address: 0x0010 :0x0030 :0x0050 :0x0070 :0x0090 :0x00B0 :0x00D0 :0x00F0 :0x0110 :0x0130 :0x0150 :0x0170 :0x0190 :0x01B0 :0x01D0 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 DATAH[7:0] DATAL[7:0] RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Name Description 31 ~ 16 Reserved - 15 ~ 8 DATAH[7:0] Data 3 7 ~ 0 DATAL[7:0] Data 4 24.10.6 Buffer n Data 0Register (CAN_BUFn_DATA0)(n=0..14) Offset Address: 0x0014 :0x0034 :0x0054 :0x0074 :0x0094 :0x00B4 :0x00D4 :0x00F4 :0x0114 :0x0134 :0x0154 :0x0174 :0x0194 :0x01B4 :0x01D4 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 DATAH[7:0] DATAL[7:0] RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

31 ~ 16 Reserved - 15 ~ 8 DATAH[7:0] Data 1 7 ~ 0 DATAL[7:0] Data 2 24.10.7 Buffer n Indentifier 0 Register (CAN_BUFn_ID0)(n=0..14) Offset Address: 0x0018 :0x0038 :0x0058 :0x0078 :0x0098 :0x00B8 :0x00D8 :0x00F8 :0x0118 :0x0138 :0x0158 :0x0178 :0x0198 :0x01B8 :0x01D8 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 XID[14:0] XRT R RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Name Description 31 ~ 16 Reserved - 15 ~ 1 XID[14:0] IDBit(ID14~ID0) for extended frame

0 XRTR Remote Trnsmission Request for extended frame

24.10.8 Buffer n Indentifier 1Register (CAN_BUFn_ID1)(n=0..14) Offset Address: 0x001C :0x003C :0x005C :0x007C :0x009C :0x00BC :0x00DC :0x00FC :0x011C :0x013C :0x015C :0x017C :0x019C :0x01BC :0x01DC Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 IDXID[10:0] RTR SRR IDE XID[2:0] RW RW RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Name Description 31 ~ 16 Reserved - 15 ~ 5 IDXID[10:0] ID10~ID0 for standard frame or ID28~ID18 for extended frame

4 RTRSRR Substitue Remote Request for extend frame or RTR bit for standard

frame. The SRR bit should be set to ‘1’ by the user if the buffer is configured to transmit a message with an extended identifier. 3 IDE Indentifier Extension. 0:standard frame using 11 identifier bits 1:extended frame using 29 identifier bits 2 ~ 0 XID[2:0] IDBit(ID17~ID15) for extended frame

24.10.9 CAN Global Configuration Register (CAN_CGCR)

Offset Address: 0x0200 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Reserved EIT DIA GEN INTE RNA L LOO PBA CK IGN ACK LO DDI R TST PEN BUF FLO CK CTX CRX CAN EN - RW RW RW RW RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

31 ~ 12 Reserved -

11 EIT Error Interrupt Type

0：The EIPND bit is set on every error on the CAN bus 1：The EIPND bit is set only if the error state(CSTPND.NS) changes as aresult of incrementing either the receive or transmit error counter.

10 DIAGEN DIAGEN

0：Normal mode 1：Diagnostic features enabled Iincludes following functions: LO (Listen Only) IGNACK (Ignore Acknowledge) LOOPBACK (Loopback) INTERNAL (Internal Loopback)

9 INTERNAL Internal Mode

0：Normal Mode 1：Internal Mode. TX and RX are internally connected to each other.

8 LOOPBACK Loopback

0：No Loopback 1：Loopback enabled

7 IGNACK Ignore Acknowledge

0：Normal mode 1：The CAN Controller does not expect to receive a dominant ACK bit to indicated the validity of a transmitted message.

6 LO Listen Only

0：Transmit/Receive mode 1：Listen-only mode

5 DDIR Data Direction

0：data contents are stored with the first byte at the highest data address 1：data contents are stored with the first byte at the lowest data address

4 TSTPEN Time Sync Enable

0：Time synchronization disabled. The Time Stamp counter value is not reset upon reception or transmission of a message to/from a buffer. 1：Time synchronization enabled. The Time Stamp counter value is reset upon reception or transmission of a message to/from a buffer.

3 BUFFLOCK Buffer Lock

If this feature is enabled, a buffer will be locked upon a successful frame reception. The buffer will be unlocked again by writing RX_READY in the buffer status register i.e. after reading data. 0：lock function is disabled for all buffers 1：lock function is enabled for all buffers

2 CTX Control Transmit

0：dominant state is “0”, recessive state is “1” 1：dominant state is “1”, recessive state is “0”

1 CRX Control Receive

0：dominant state is “0”, recessive state is “1” 1：dominant state is “1”, recessive state is “0”

0 CANEN CAN Enable

0：CAN Controller is disabled 1：CAN Controller is enabled

24.10.10 CAN Timing Register (CAN_CTIM)

Offset Address: 0x0204 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 PSC[6:0] SJW[1:0] TSEG1[3:0] TSEG2[2:0] RW RW RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Name Description 31 ~ 16 Reserved - 15 ~ 9 PSC[6:0] Prescaler Configuration 0000000：2 0000001：3 0000010：4 1111101：127 1111110：128 1111111：128 8 ~ 7 SJW[1:0] Synchronization Jump Width 00：1tq 01：2tq 10：3tq 11：4tq *The settings of SJW must be configured less than or equal to TSEG1 and TSEG2. 6 ~ 3 TSEG1[3:0] Time Segment 1 0000：not recommended 0001：2tq 0010：3tq 0011：4tq 0100：5tq 0101：6tq 0110：7tq 0111：8tq 1000：9tq 1001：10tq 1010：11tq 1011：12tq 1100：13tq 1101：14tq 1110：15tq 1111：16tq 2 ~ 0 TSEG2[2:0] Time Segment 2 000：1tq 001：2tq 010：3tq 011：4tq 100：5tq 101：6tq 110：7tq 111：8tq

24.10.11 CAN Global Mask Register Extend (CAN_GMSKX)

Offset Address: 0x0208 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 XGM[14:0] XRT R RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Name Description 31 ~ 16 Reserved - 15 ~ 1 XGM[14:0] Global Mask Bit for ID14~ID0 of extended frame 0: incoming identifier bit must match the corresponding bit in the message buffer identifier register 1：accept “1” or “0”(“don’t care”) of the incoming ID bit independent from the corresponding bit in the message buffer ID registers. The corresponding ID bit in the message buffer will be overwritten by the incoming identifier bits.

0 XRTR Global Remote Mask Bit for extended frames

0：Must match 1：Don’t Care

24.10.12 CAN Global Mask Register Base (CAN_GMSKB)

Offset Address: 0x020C Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 GMXGM[28:18] RTR SRR IDE XGM[17:15] RW RW RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Name Description 31 ~ 16 Reserved - 15 ~ 5 GMXGM[28:18] Global Mask Bit ID28~ID18 of extended frame or ID10~ID0 of standard frame 0: incoming identifier bit must match the corresponding bit in the message buffer identifier register 1：accept “1” or “0”(“don’t care”) of the incoming ID bit independent from the corresponding bit in the message buffer ID registers. The corresponding ID bit in the message buffer will be overwritten by the incoming identifier bits.

4 RTRSRR Global Mask Bit for Standard Remote frames or SRR mask bit of extened

0：Must match 1：Don’t care

3 IDE Global Mask bit for Extemded frames

0：Must match 1：Don’t care 2 ~ 0 XGM[17:15] Global Mask bit ID17~ID15 of extended frame 0: incoming identifier bit must match the corresponding bit in the message buffer identifier register 1：accept “1” or “0”(“don’t care”) of the incoming ID bit independent from the corresponding bit in the message buffer ID registers. The corresponding ID bit in the message buffer will be overwritten by the incoming identifier bits.

24.10.13 CAN Basic Mask Register Extend (CAN_BMSKX)

Offset Address: 0x0210 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 XBM[14:0] XRT R RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Name Description 31 ~ 16 Reserved - 15 ~ 1 XBM[14:0] Mask bit for ID14~ID0 of extended frame (Buffer 14) 0: incoming identifier bit must match the corresponding bit in the message buffer identifier register 1：accept “1” or “0”(“don’t care”) of the incoming ID bit independent from the corresponding bit in the message buffer ID registers. The corresponding ID bit in the message buffer will be overwritten by the incoming identifier bits.

0 XRTR Mask bit for Extended Remote Frame (Buffer 14)

0：Must match 1：Don’t care

24.10.14 CAN Basic Mask Register Base (CAN_BMSKB)

Offset Address: 0x0214 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 BMXBM[28:18] RTR SRR IDE XBM[17:15] RW RW RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

31 ~ 16 Reserved - 15 ~ 5 BMXBM[28:18] Mask Bit for ID28~ID18 of extended frame or ID10~ID0 of standard frame (Buffer 14) 0: incoming identifier bit must match the corresponding bit in the message buffer identifier register 1：accept “1” or “0”(“don’t care”) of the incoming ID bit independent from the corresponding bit in the message buffer ID registers. The corresponding ID bit in the message buffer will be overwritten by the incoming identifier bits.

4 RTRSRR Mask Bit for Standard Remote Frames or SRR bit of extended

frame(Buffer 14) 0：Must match 1：Don’t care

3 IDE Mask Bit for Extended Frames (Buffer 14)

0：Must match 1：Don’t care 2 ~ 0 XBM[17:15] Mask Bit for ID 17~ID15 of extended frame(Buffer 14) 0: incoming identifier bit must match the corresponding bit in the message buffer identifier register 1：accept “1” or “0”(“don’t care”) of the incoming ID bit independent from the corresponding bit in the message buffer ID registers. The corresponding ID bit in the message buffer will be overwritten by the incoming identifier bits.

24.10.15 CAN Interrupt Enable Register (CAN_CIEN)

Offset Address: 0x0218 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 EIEN IEN1 IEN1 IEN1 IEN1 IEN1 IEN9 IEN8 IEN7 IEN6 IEN5 IEN4 IEN3 IEN2 IEN1 IEN0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Name Description 31 ~ 16 Reserved -

15 EIEN Error Interrupt Enable

0：The error interrupt is disabled and no error interrupt will be generated 1：The error interrupt is enabled and a change in REC/TEC will cause an interrupt to be generated.

14 IEN14 Buffer14 Interrupt Enable

0：Disable 1：Enable

13 IEN13 Buffer13 Interrupt Enable

0：Disable 1：Enable

12 IEN12 Buffer12 Interrupt Enable

0：Disable 1：Enable

11 IEN11 Buffer11 Interrupt Enable

0：Disable 1：Enable

10 IEN10 Buffer10 Interrupt Enable

0：Disable 1：Enable

9 IEN9 Buffer9 Interrupt Enable

0：Disable 1：Enable

8 IEN8 Buffer8 Interrupt Enable

0：Disable 1：Enable

7 IEN7 Buffer7 Interrupt Enable

0：Disable 1：Enable

6 IEN6 Buffer6 Interrupt Enable

0：Disable 1：Enable

5 IEN5 Buffer5 Interrupt Enable

0：Disable 1：Enable

4 IEN4 Buffer4 Interrupt Enable

0：Disable 1：Enable

3 IEN3 Buffer3 Interrupt Enable

0：Disable 1：Enable

2 IEN2 Buffer2 Interrupt Enable

0：Disable 1：Enable

1 IEN1 Buffer1 Interrupt Enable

0：Disable 1：Enable

0 IEN0 Buffer0 Interrupt Enable

0：Disable 1：Enable

24.10.16 CAN Interrupt Pending Register (CAN_CIPND)

Offset Address: 0x021C Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 EIPN D IPND IPND IPND IPND IPND IPND IPND IPND IPND IPND IPND IPND IPND IPND IPND RO RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

31 ~ 16 Reserved -

15 EIPND Error Interrupt Pending

0：CAN status is not changed 1：CAN status is changed

14 IPND14 Buffer 14 Interrupt Pending

0：No interrupt pending for this message buffer 1：Message buffer has generated an interrupt

13 IPND13 Buffer 13 Interrupt Pending

0：No interrupt pending for this message buffer 1：Message buffer has generated an interrupt

12 IPND12 Buffer 12 Interrupt Pending

0：No interrupt pending for this message buffer 1：Message buffer has generated an interrupt

11 IPND11 Buffer 11 Interrupt Pending

0：No interrupt pending for this message buffer 1：Message buffer has generated an interrupt

10 IPND10 Buffer 10 Interrupt Pending

0：No interrupt pending for this message buffer 1：Message buffer has generated an interrupt

9 IPND9 Buffer 9 Interrupt Pending

0：No interrupt pending for this message buffer 1：Message buffer has generated an interrupt

8 IPND8 Buffer 8 Interrupt Pending

0：No interrupt pending for this message buffer 1：Message buffer has generated an interrupt

7 IPND7 Buffer 7 Interrupt Pending

0：No interrupt pending for this message buffer 1：Message buffer has generated an interrupt

6 IPND6 Buffer 6 Interrupt Pending

0：No interrupt pending for this message buffer 1：Message buffer has generated an interrupt

5 IPND5 Buffer 5 Interrupt Pending

0：No interrupt pending for this message buffer 1：Message buffer has generated an interrupt

4 IPND4 Buffer 4 Interrupt Pending

0：No interrupt pending for this message buffer 1：Message buffer has generated an interrupt

3 IPND3 Buffer 3 Interrupt Pending

0：No interrupt pending for this message buffer 1：Message buffer has generated an interrupt

2 IPND2 Buffer 2 Interrupt Pending

0：No interrupt pending for this message buffer 1：Message buffer has generated an interrupt

1 IPND1 Buffer 1 Interrupt Pending

0：No interrupt pending for this message buffer 1：Message buffer has generated an interrupt

0 IPND0 Buffer 0 Interrupt Pending

0：No interrupt pending for this message buffer 1：Message buffer has generated an interrupt

24.10.17 CAN Interrupt Clear Register (CAN_CICLR)

Offset Address: 0x0220 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 EICL R ICLR ICLR ICLR ICLR ICLR ICLR ICLR ICLR ICLR ICLR ICLR ICLR ICLR ICLR ICLR WO RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Name Description 31 ~ 16 Reserved -

15 EICLR Error Interrupt Clear

0：The contents of the EIPND bit are unchanged 1：The contents of the EIPND bit are reset

14 ICLR14 Buffer 14 Interrupt Clear

0：The contents of the IPND bit are unchanged 1：The contents of the IPND bit are reset

13 ICLR13 Buffer 13 Interrupt Clear

0：The contents of the IPND bit are unchanged 1：The contents of the IPND bit are reset

12 ICLR12 Buffer 12 Interrupt Clear

0：The contents of the IPND bit are unchanged 1：The contents of the IPND bit are reset

11 ICLR11 Buffer 11 Interrupt Clear

0：The contents of the IPND bit are unchanged 1：The contents of the IPND bit are reset

10 ICLR10 Buffer 10 Interrupt Clear

0：The contents of the IPND bit are unchanged 1：The contents of the IPND bit are reset

9 ICLR9 Buffer 9 Interrupt Clear

0：The contents of the IPND bit are unchanged 1：The contents of the IPND bit are reset

8 ICLR8 Buffer 8 Interrupt Clear

0：The contents of the IPND bit are unchanged 1：The contents of the IPND bit are reset

7 ICLR7 Buffer 7 Interrupt Clear

0：The contents of the IPND bit are unchanged 1：The contents of the IPND bit are reset

6 ICLR6 Buffer 6 Interrupt Clear

0：The contents of the IPND bit are unchanged 1：The contents of the IPND bit are reset

5 ICLR5 Buffer 5 Interrupt Clear

0：The contents of the IPND bit are unchanged 1：The contents of the IPND bit are reset

4 ICLR4 Buffer 4 Interrupt Clear

0：The contents of the IPND bit are unchanged 1：The contents of the IPND bit are reset

3 ICLR3 Buffer 3 Interrupt Clear

0：The contents of the IPND bit are unchanged 1：The contents of the IPND bit are reset

2 ICLR2 Buffer 2 Interrupt Clear

0：The contents of the IPND bit are unchanged 1：The contents of the IPND bit are reset

1 ICLR1 Buffer 1 Interrupt Clear

0：The contents of the IPND bit are unchanged 1：The contents of the IPND bit are reset

0 ICLR0 Buffer 0 Interrupt Clear

0：The contents of the IPND bit are unchanged 1：The contents of the IPND bit are reset

24.10.18 CAN Interrupt Code Enable Register (CAN_CICEN)

Offset Address: 0x0224 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 EICE N ICEN ICEN ICEN ICEN ICEN ICEN ICEN ICEN ICEN ICEN ICEN ICEN ICEN ICEN ICEN RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Name Description 31 ~ 16 Reserved -

15 EICEN Error Interrupt Code Enable

0：Error interrupt pending is not indicated in the interrupt code. 1：Error interrupt pending is indicated in the interrupt code.

14 ICEN14 Buffer 14 Interrupt Code Enable

0：Buffer interrupt pending is not indicated in the interrupt code. 1：Buffer interrupt pending is indicated in the interrupt code.

13 ICEN13 Buffer 13 Interrupt Code Enable

0：Buffer interrupt pending is not indicated in the interrupt code. 1：Buffer interrupt pending is indicated in the interrupt code.

12 ICEN12 Buffer 12 Interrupt Code Enable

0：Buffer interrupt pending is not indicated in the interrupt code. 1：Buffer interrupt pending is indicated in the interrupt code.

11 ICEN11 Buffer 11 Interrupt Code Enable

0：Buffer interrupt pending is not indicated in the interrupt code. 1：Buffer interrupt pending is indicated in the interrupt code.

10 ICEN10 Buffer 10 Interrupt Code Enable

0：Buffer interrupt pending is not indicated in the interrupt code. 1：Buffer interrupt pending is indicated in the interrupt code.

9 ICEN9 Buffer 9 Interrupt Code Enable

0：Buffer interrupt pending is not indicated in the interrupt code. 1：Buffer interrupt pending is indicated in the interrupt code.

8 ICEN8 Buffer 8 Interrupt Code Enable

0：Buffer interrupt pending is not indicated in the interrupt code. 1：Buffer interrupt pending is indicated in the interrupt code.

7 ICEN7 Buffer 7 Interrupt Code Enable

0：Buffer interrupt pending is not indicated in the interrupt code. 1：Buffer interrupt pending is indicated in the interrupt code.

6 ICEN6 Buffer 6 Interrupt Code Enable

0：Buffer interrupt pending is not indicated in the interrupt code. 1：Buffer interrupt pending is indicated in the interrupt code.

5 ICEN5 Buffer 5 Interrupt Code Enable

0：Buffer interrupt pending is not indicated in the interrupt code. 1：Buffer interrupt pending is indicated in the interrupt code.

4 ICEN4 Buffer 4 Interrupt Code Enable

0：Buffer interrupt pending is not indicated in the interrupt code. 1：Buffer interrupt pending is indicated in the interrupt code.

3 ICEN3 Buffer 3 Interrupt Code Enable

0：Buffer interrupt pending is not indicated in the interrupt code. 1：Buffer interrupt pending is indicated in the interrupt code.

2 ICEN2 Buffer 2 Interrupt Code Enable

0：Buffer interrupt pending is not indicated in the interrupt code. 1：Buffer interrupt pending is indicated in the interrupt code.

1 ICEN1 Buffer 1 Interrupt Code Enable

0：Buffer interrupt pending is not indicated in the interrupt code. 1：Buffer interrupt pending is indicated in the interrupt code.

0 ICEN0 Buffer 0 Interrupt Code Enable

0：Buffer interrupt pending is not indicated in the interrupt code. 1：Buffer interrupt pending is indicated in the interrupt code.

24.10.19 CAN Status Pending Register (CAN_CSTPND)

Offset Address: 0x0228 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Reserved NS[2:0] IRQ IST[3:0] - RO RO RO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Name Description 31 ~ 8 Reserved - 7 ~ 5 NS[2:0] CAN Node Status 000：Not Active 010：Error Active 011：Error Warning Level 10X：Error Passive 11X：Bus Off

4 IRQ Interrupt Request

0：No Interrupt Request 1：Interrupt Request Occured

3 ~ 0 IST[3:0] Interrupt Code 0000：Error interrupt 0001：buff0 0010：buff1 0011：buff2 0100：buff3 0101：buff4 0110：buff5 0111：buff6 1000：buff7 1001：buff18 1010：buff19 1011：buff10 1100：buff11 1101：buff12 1110：buff13 1111：buff14

24.10.20 CAN Error Counter Register (CAN_CANEC)

Offset Address: 0x022C Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 REC[7:0] TEC[7:0] RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Name Description 31 ~ 16 Reserved - 15 ~ 8 REC[7:0] CAN Receive Error Counter 7 ~ 0 TEC[7:0] CAN Transmit Error Counter

24.10.21 CAN Error Diagnostic Register (CAN_CEDIAG)

Offset Address: 0x0230 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Rese rved DRIV E MON CRC ERR STU FF TXE EBID[5:0] EFID[3:0] - RO RO RO RO RO RO RO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

31 ~ 15 Reserved -

14 DRIVE Drive

This bit shows the output value on the CANTX pin at the time of the error.Note that a receiver will not drive the bus except during ACK and an active error flag.

13 MON Monitor

This bit shows the bus value on the CANRX pin as seen by the CAN Controller at the time of the error.

12 CRCERR CRC Error

0：No CRC error occurred 1：CRC error occurred

11 STUFF Stuff Error

0：No bit stuffing error 1：The bit stuffing rule was violated when the error occurred.

10 TXE Transmit Error

0：The CAN Controller was a receiver when the error occurred 1：The CAN Controller was an active transmitter when the error occurred 9 ~ 4 EBID[5:0] Error Bit Identifier The bit number starts with the value equal to the according frame field length minus one at the beginning of each field and is decremented with each CAN bit. 3 ~ 0 EFID[3:0] Error Field Indentifier 0000：ERROR 0001：ERROR DEL 0010：ERROR ECHO 0011：BUS IDLE 0100：ACK 0101：EOF 0110：INTERMISSION 0111：SUSPEND TRANSMISSION 1000：SOF 1001：ARBITRATION 1010：IDE 1011：EXTENDED ARBITRATION 1100：R0/R1 1101：DLC 1110：DATA 1111：CRC

24.10.22 CAN Timer Register (CAN_CTMR)

Offset Address: 0x0234 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 CTMR[15:0] RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Name Description 31 ~ 16 Reserved - 15 ~ 0 CTMR[15:0] The current value of the Time Stamp Counter.

1. Device Electronic Signature

25.1 Unique device ID register (96 bits)

The unique device identifier is ideally suited:  For use as serial numbers (for example, the product serial number meets the terminal application)  For use as security keys in order to increase the security of code in Flash memory while using and combining this unique ID with software cryptography primitives and protocols before programming the internal Flash memory  to activate secure boot processes, etc. The 96-bit unique device identifier provides a reference number which is unique for any device and in any context. These bits can never be altered by the user. The 96-bit unique device identifier can also be read in single bytes/half-words/words in different ways.

1. Debug Interface

26.1 Overview

SH33F2801 is built around a ARM Star core which contains hardware extensions for advanced debugging features. The debug extensions allow the core to be stopped either on a given instruction fetch (breakpoint) or data access (watchpoint). When stopped, the core’s internal state and the system’s external state may be examined. Once examination is complete, the core and the system may be restored and program execution resumed. SH33F2801 supports the SWJ debug interface. When the SH33F2801 microcontroller is connected to the debugger and starts debugging, the debugger will use the hardware debug module of the core for debugging operations. The ARM Star core provides integrated debug support on chip. It consists of the following parts:  SWJ-DP: Serial wire/JTAG debug port  AHP-AP: AHB access port  FPB: flash order breakpoint  DWT: Data watchpoint trigger For more information on the debug interface, please refer to the ARM official manual and ARM Development Toolset Technical Reference Manual.

26.2 SW Debug Interface(Serial Wire)

The SH33F2801 core integrates the Serial Wire Debug Port (SWJ-DP). It is an ARM standard CoreSight debug port that combines a SWDP (2-pin) interface.

• The Serial Wire Debug Port (SW-DP) provides a 2-pin (clock + data) interface to the AHP-AP port.

26.3 SW Debug Interface Pins

The two general-purpose I/O ports of SH33F2801 can be used as SWJ-DP interface pins. These pins are present in all packages. Table26-1 SW Debug Interface Pins SWJ-DP Interface Pin Name SW Debug Interface Pin Type Description SWDIO Input/output Serial wire data input/output PA7 SWCLK Input Serial wire clock PA8

26.4 Using Serial Interface and Releasing Unused Debug Pins as General Purpose I/O Ports

After reset (SYSRESET or PORESET), all 2 pins belonging to SW-DP are immediately initialized to dedicated pins that can be used by the debugger. However, the SH33F2801 microcontroller can use the SW interface as a GPIO port as alternate function. For details, please refer to the “SYSCFG” part. For user software design, it should be noted that after reset, these dedicated pins are still internal pull-up (SWDIO), internal pull-down (SWCLK), for a period of time until the user code releases these pins. When these pins are still configured as debug interfaces (SW), modifying the corresponding general-purpose I/O port configuration registers is invalid. Table26-2 SW_DP Pin Assignment SWJCFG[0] Pins Configured as Debugging Dedicated I/O Ports Assignment of SWJ Port Whether SW Debug Interface is Available in debug mode SWDIO SWCLK

0 SW-DP port Only for Debug Only for Debug Available

1 SW-DP port disabled Available for user

(Note1) Available for user (Note1) Available Note1: In this mode, SWDIO and SWCLK can be configured as general-purpose I/O under normal operating conditions, but they are still used to be debug interfaces in debug mode.

26.5 MCU Debug Module

MCU Debug module assists the debugger to provide the following functions:

• Low power mode
• Provides clock control of MCM, PCA, TIM, UART, SPI, TWI, CAN, IWDT and WDT during breakpoints

26.5.1 Debug Support for Low Power Mode

Low power mode can be entered by using WFI and WFE. MCU supports a variety of low-power modes that can turn off the CPU clock or reduce the CPU's power consumption respectively. However, in order to enable the user to debug the code in low power mode, FCLK and HCLK cannot be turned off during debugging, which means setting DBG_STOP=0. Therefore, after entering the low power mode in debug mode, FCLK and HCLK are working by default. If user needs to enter the real low power mode during debugging, DBG_STOP=1 can be set via the debugger or software. Note that DBG_STOP=0 only guarantees that the registers of each peripheral can be read after STOP in debug mode, but the peripheral's working clock is still off. In addition, HCLK is clocked by the internal HSI in this case.

26.5.2 Module Debug Support with Timing Function

When generating breakpoints, it is necessary to select the operating mode of the corresponding counters according to the different uses of each module. For modules like MCM, PCA, TIM, UART, SPI, TWI, CAN, IWDT, WWDT, when breakpoint is generated, user can select whether the counter of each module continues to count.

26.6 Debug MCU Configure Registers

SYSCFG Module Register List (Base Address: 0x4004 0800) Address Register Name Description 0x4004 0808 SAFR System configure register 0x4004 0810 DBGCR Debug interface control register

26.6.1 System Configure Register (SYSCFG_SAFR)

Offset Address: 0x0008 Reset Value: 0x0000 0000 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 LOCK[15:0] WO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Reserved IEN_C SM IEN_B OD IEN_E XTI0 Reserved SWJC FG OSCCFG[1:0] - RW RW RW - RW1t RW1t 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 16 LOCK[15:0] Operation unlock bits of this register These bits are write only, reading these bits returns 0x00. 0x5AA5: Unlocked Other: Locked Note: Writing to this register requires unlock control. Reading this register does not require unlocking. 15 ~ 8 Reserved -

7 IEN_CSM CSM causing NMI interrupt enable bit

6 IEN_BOD BOD causing NMI interrupt enable bit

5 IEN_EXTI0 EXTI0 causing NMI interrupt enable bit

4 ~ 3 Reserved - These bits can only be written by software (reading these bits will return undefined values) for configuring SWD and I/O ports which track alternate functions. To release part or all of the debug ports to general purpose I/O ports, the user software can set SWJCFG after reset. 0: SWD debug port can not be multiplexed as general purpose I/O. SWDIO and SWCLK are used as debug pins. 1: SWD turned off; SWDIO and SWCLK can be multiplexed as general purpose I/O in normal operation state, and they are still forced to be used as debug interfaces in debug mode state. Note: Once this control bit is set, it can only be modified by resetting. Users should carefully configure this bit, because some options will cause the SWD interface to be unusable, but they can be recovered through the SWD interface, while cooperating with the reset signal is required. 1 ~ 0 OSCCFG[1:0] XTAL1/XTAL2 pins alternate function definition 00: XTAL1/XTAL2 are used as GPIO (default) 01: External oscillator interface (crystal and ceramic) 10: XTAL1 is externally clocked, XTAL2 is used as GPIO 11: Reserved Note: Once this control bit is set, only reset can modify it.

26.6.2 Debug Interface Control Register (SYSCFG_DBGCR)

Offset Address: 0x0010 Reset Value: 0x0000 0080 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 LOCK[15:0] WO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 DBG_T WI DBG_ SPI DBG_ UART DBG_ MCM DBG_T IM DBG_ GPT DBG_ WWDT DBG_I WDT DBG_ QEI DBE_C AN Reserved DBG_ STOP Reserv ed RW RW RW RW RW RW RW RW RW RW - RW - 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 Bit Sign Description 31 ~ 16 LOCK[15:0] Operation unlock bits of this register (Control bit Lock register) These bits are write only, reading these bits returns 0x0000。 0x5AA5: Unlocked Other: Locked Note: Writing to this register requires unlock control. Reading this register does not require unlocking.

15 DBG_TWI TWI stops working when the core is halted

0: TWI stops working 1: TWI is still working normally

14 DBG_SPI SPI stops working when the core is halted

0: SPI stops working 1: SPI is still working normally

13 DBG_UART UART stops working when the core is halted

0: UART stops working 1: UART is still working normally

12 DBG_MCM MCM stops working when the core is halted

0: MCM stops working 1: MCM is still working normally

11 DBG_TIM TIM7-TIM8 modules stops working when the core is halted

0: TIM7-TIM8 modules stop working 1: TIM7-TIM8 modules are still working normally

10 DBG_PCA PCA stops working when the core is halted

0: PCA stops working 1: PCA is still working normally

9 DBG_WWDT Debug window watchdog stops working when the core is halted

0: Debug window watchdog stops working 1: Debug window watchdog is still working normally

8 DBG_IWDT Watchdog stops working when the core is halted

0: Watchdog counter stops working 1: Watchdog counter is still working normally

7 DBG_QEI QEI stops working when the core is halted

0: QEI stops working 1: QEI is still working normally

6 DBG_CAN CAN stops working when the core is halted

0: CAN stops working 1: CAN is still working normally 5 ~ 2 Reserved -

0: In stop mode, the system clock is held and is provided by the internal RC oscillator (including HCLK and FCLK). When exiting the stop mode, the software must reconfigure the clock system to start PLL, crystal oscillator, etc. (same operation as configuring this bit to 0) 1: In stop mode, the system clock is turned off and the clock controller disables all clocks (including HCLK and FCLK). When exiting from the stop mode, the configuration of the clock is the same as after the reset (the microcontroller is clocked by the 8MHz internal RC oscillator (HSI)). Therefore, the software must reconfigure the clock control system to start PLL, crystal oscillator, etc. Note: HCLK remains on when DBG_STOP=0, but the external device clock is masked, which means the peripheral module still enters STOP state. HCLK can maintain the connection of the debug interface, which means the debug tool can read the state information of CPU and peripherals before the stop.

1. Customer Options OP_IWDT: 0101: IWDT is controlled by software (default) Other: IWDT is always on and cannot be turned off OP_WDTPD: 0: IWDT is disabled in stop mode 1: IWDT is enabled in stop mode (default) OP_MCMPIN: MCM module PWM waveform output order: Pin Option PB6 PB5 PB4 PB3 PB2 PB1 000 (default) PWM no output

001 PWM0 PWM1 PWM2 PWM01 PWM11 PWM21

01 PWM21 PWM11 PWM01 PWM2 PWM1 PWM0

10 PWM0 PWM01 PWM1 PWM11 PWM2 PWM21

11 PWM21 PWM2 PWM11 PWM1 PWM01 PWM0

FLASH_BACKUP: 0: One Area Mode 1: Two Area Mode (Main Memory and Backup Memory) FLASH_SELECT: (Only when FLASH_BACKUP is on) 0: PC points to the address of Main Memory Block 1: PC points to the address of Backup Memory Block OP_ISP: 0: Enable ISP (default) 1: Disable ISP

1. Electrical Characteristics Absolute rating * *Note If the working conditions of the device exceed the range of the "absolute rating" in the left column, it will cause permanent damage to the device. The function is only guaranteed if the device is operating within the limits specified in the instructions. Working under the conditions listed in the limit parameters will affect the reliability for the operation of the device. DC electrical characteristics (VDD = 2.4 – 5.5V, TA = 25°C, unless otherwise indicated) Parameter Signal Minimum Value Typical Value Maximum Value Unit Condition Digital working voltage VDD 2.4 5.0 5.5 V 4MHz ≤ fsys ≤ 84MHz Working cuurent IOP1 - 20 35 mA fsys = 84MHz, PLL is on, VDD=5.0V, The PLL clock source uses crystal oscillator (8MHz). All output pins are not loaded and all input pins are not floating CPU is on (executes local loop jump), IWDT is on, LVR is on, and all peripheral clocks are turned off. IOP2 - 6 10 mA fsys = 8MHz, PLL is off, VDD=5.0V, internal RC oscillator is used. All output pins are not loaded and all input pins are not floating CPU is on (executes local loop jump), IWDT is on, LVR is on, and all peripheral clocks are turned off. IOP3 - 35 45 mA fsys = 84MHz, PLL is on, VDD=5.0V, The PLL clock source uses crystal oscillator (8MHz). All output pins are not loaded and all input pins are not floating CPU is on (executes local loop jump), IWDT is on, LVR is on, and all peripheral clocks are turned on. IOP4 - 8 12 mA fsys = 8MHz, PLL is off, VDD=5.0V, internal RC oscillator is used. All output pins are not loaded and all input pins are not floating CPU is on (executes local loop jump), IWDT is on, LVR is on, and all peripheral clocks are turned on. Standby current (sleep mode) ISB1 - 6 10 mA fsys = 8MHz, PLL is off, VDD=5.0V, internal RC oscillator is used. All output pins are not loaded and all input pins are not floating CPU is off (executes local loop jump), IWDT is off, LVR is on, and all peripheral clocks are turned off.

Standby current (stop mode) ISB2 - 10 20 µA HSE is off, PLL is off, VDD=5.0V, All output pins are not loaded and all input pins are not floating CPU is stopped (executes WFI to enter stop), IWDT is off, LVR is off, and all other functions are turned off. LVR current ILVR1 - 1 - µA LVR is on, LVR level = 4.1V/2.8V IWDT current IIWDT - - 1 uA All output pins are not loaded; independent watchdog is on VDD =5.0V Input low voltage 1 VIL1 GND 0.2 X VDD V I/O ports (all ports are Schmitt input) VDD = 2.4 - 5.5V Input high voltage 1 VIH1 0.8 X VDD - VDD V I/O ports (all ports are Schmitt input) VDD = 2.4 - 5.5V Input low voltage 2 VIL2 GND - 0.15 X VDD Only NRST pin VDD = 2.4 – 5.5V Input high voltage 2 VIH2 0.85 X VDD - VDD Only NRST pin VDD = 2.4 – 5.5V Input low voltage 3 VIL3 GND - 0.8 V For the pins of Table13-3 (input high-low window voltage 0.4V) VDD = 4.5 - 5.5V, TTL input function is on (Note4) GND - 0.15 X VDD V For the pins of Table13-3(input high-low window voltage 0.4V) VDD = 2.4 - 4.5V, TTL input function is on Input high voltage 3 VIH3 2.0 - VDD V For the pins of Table13-3 (input high-low window voltage 0.4V) VDD = 4.5 - 5.5V, TTL input function is on 0.25 X VDD+0.8 - VDD V For the pins of Table13-3 (input high-low window voltage 0.4V) VDD = 2.4 - 4.5V, TTL input function is on Input leakage current IIL -1 1 uA Input has no pull-up, VIN= VDD or GND Pull-up resistor 1* RPH1 - 30 - kΩ VDD =5.0V, VIN=GND Reset pin Pull-up resistor RRPH - 10 - kΩ VDD =5.0V, VIN=GND Output high voltage VOH VDD – 0.7 - - V I/O ports, IOH = -10mA, VDD = 5.0V Output low voltage VOL - - GND + 0.6 V I/O ports, IOL = 12mA, VDD = 5.0V Note: 1. "*" indicates that the data under typical values were measured at 5.0 V at 25 ° C unless otherwise stated. 2. The maximum current flowing through VDD must be less than 150mA. The maximum current flowing through GND must be less than 200mA. 3. Design guarantee, temperature is not included in actual test.

High-speed 12BIT analog-to-digital converter electrical characteristics (1LSB = VDD/4096) The conversion rate is up to 2MSPS.(VDD = 2.7V～5.5V, GND = 0V, TA = +25°C, unless otherwise stated) Parameter Signal Minimum Value Typical Value Maximum Value Unit Condition Working voltage range VAD 2.7 5.0 5.5 V Accuracy NR - 12 - bit VREF = 5.0V A/D input voltage VAIN GND - VREF V A/D equivalent input resistor RAIN 2 - - MΩ VIN = 5.0V External analog reference voltage VREF 2.5 - VDD V ADC sampling signal source recommended resistance ZAIN - 2.5 - kΩ Typical values are measured at 1 MSPS conversion rate with an error of 2LSB. See chapter 20.3.10 formula for details. - - 1 MΩ The lower the sampling rate, the larger the support resistance, measured at 1KSPS conversion rate and 1LSB error A/D conversion current IAD - 1.5 3 mA ADC module is working, VDD = 5.0V Differential nonlinearity error DLE - ±0.5 ±2 LSB VDD = 5.0V, VREF = VDD, ADC CLK = 40MHz Integral nonlinearity error ILE - ±1 ±3 LSB VDD = 5.0V, VREF = VDD, ADC CLK = 40MHz Full scale error EF - ±3 ±5 LSB VDD = 5.0V, VREF = VDD, ADC CLK = 40MHz Offset error EZ - ±3 ±7 LSB VDD = 5.0V, VREF = VDD, ADC CLK = 40MHz Total absolute error EAD - - ±8 LSB VDD = 5.0V, VREF = VDD, ADC CLK = 40MHz ADC operation clock fADC 1 - 40 MHz VDD = 5.0V, VREF = VDD - 30 VDD = 3.3V, VREF = VDD ADC sampling time tSAMP 0.125 - - µs VDD = 5.0V, VREF = VDD 0.2 - - VDD = 3.3V, VREF = VDD ADC conversion rate FCON - - 2 MSPS VDD = 5.0V, VREF = VDD - - 1.4 VDD = 3.3V, VREF = VDD Total conversion time TCON 16 - 159 tAD (1 tAD ～ 16 tAD)+tGAP + tCOMP

Comparator0/1 electrical characteristics (VDD = 2.7 - 5.5V, GND = 0V, TA = +25°C, unless otherwise stated) Parameter Signal Minimum Value Typical Value Maximum Value Unit Condition Input offset voltage VIO - 2 3 mV Input common mode voltage range VICM 0 - VDD - 1.2 V Small signal response time TRS1 - 1 2 µs VDD = 5V, CMPxN = 1.20V, CMPxP = 1.15V Step to 1.25V Big signal response time TRS2 - 0.3 0.5 µs VDD = 5V, CMPxN = 1V, CMPxP = 0V Step to 2V Comparator Schmidt window 1 VSMT1 - 0 - mV VDD = 5V, no Schmidt window, falling edge window Comparator Schmidt window 2 VSMT2 - 15 20 mV VDD = 5V, Schmidt window 10mV, falling edge window Comparator Schmidt window 3 VSMT3 - 30 40 mV VDD = 5V, Schmidt window 20mV, falling edge window Comparator Schmidt window 4 VSMT4 - 50 70 mV VDD = 5V, Schmidt window 50mV, falling edge window Internal inverting end reference source V N1 - - 1% VDD = 5V Amplifier0/1/2/3 electrical characteristics (VDD = 2.7 - 5.5V, GND = 0V, TA = +25°C, unless otherwise stated) Parameter Signal Minimum Value Typical Value Maximum Value Unit Condition Input offset voltage VIO - 2 3 mV TA = 25°C Input common mode voltage range VICM 0 - VDD - 1.2 V Temperature coefficient - 0.015% - VOUT = 2.5V, the change rate of the output voltage for every 1°C of temperature change Conversion rate SR 5 - - V/us Voltage follower mode Output voltage range VOUR 0.1 - VDD - 0.5 V Voltage suppression ratio SVR 65 80 - dB DC characteristics Common mode suppression ratio CMRR 60 80 - dB DC characteristics Gain bandwidth BW - 12 - MHz Voltage follower mode Internal gain coefficient accuracy Gain1 - 0.5% 1% - VDD=5V, Magnification of 1-16 times Gain2 - 1% 2% - VDD=5V, Magnification of 24 and 32 times

AC electrical characteristics (VDD = 2.4 - 5.5V, GND = 0V, TA = +25°C, unless otherwise stated) Parameter Signal Minimum Value Typical Value Maximum Value Unit Condition Reset pulse width tRESET 100 - - µs Low level valid Frequency accuracy (RC) | ∆ F|/ F - - 0.2 % Internal RC oscillator frequency accuracy: (average of 1024 periods) |FRC – 8MHz|/8MHz X 100% | ∆ F|/ F - - 0.5 % Internal RC oscillator frequency accuracy: (average of 1024 periods) |FRC – 8MHz|/8MHz X 100% Design guarantee, not tested in production.) | ∆ F|/ F - - 1 % Internal RC oscillator frequency accuracy: (average of 1024 periods) |FRC – 8MHz|/8MHz X 100% Design guarantee, not tested in production.) PLL characteristics (VDD = 2.4 - 5.5V, GND = 0V, TA = +25°C, unless otherwise stated) Parameter Signal Minimum Value Typical Value Maximum Value Unit Condition PLL input clock frequency fPLL_IN 4 - 16 MHz PLL input clock Duty DPLL_IN 40 - 60 % PLL output clock frequency fPLL_OUT 84 MHz PLL setup time TPLL 217 TOSC PLL frequency stability ±0.05 ±0.1 % (Average of 1024 periods VDD = 2.4 - 5.5V, TA = 25°C) FLASH characteristics (VDD = 2.4 - 5.5V, GND = 0V, TA = +25°C, unless otherwise stated) Parameter Signal Minimum Value Typical Value Maximu m Value Unit Condition Read operation time TREAD - 30 - ns 32-bit read Program operation time TPROG - 20 - us 32-bit write Sector erase time TSECTOR_ ERASE - 2 - ms Single sector Total erase time TTOTAL_E RASE - 10 - ms Program/erase times NEND Main Program block - 10 - - one thousand times EEPROM like block - 100 - - one thousand times Data retention life tRET 10 - - year

Brownout detection (BOD) electrical characteristics (VDD = 2.4 - 5.5V, GND = 0V, TA = +25°C, unless otherwise stated) Parameter Signal Minimum Value Typical Value Maximum Value Unit Condition BOD voltage range VBOD 2.8 - 4.3 V BOD threshold level |∆VBOD| - 100 - mV VBOD = 2.8V～4.3V BOD hysteresis window VSMTBD1 - 50 - mV VBOD = 2.8V～4.3V BOD debounce time TBOD - 60 - µs Low voltage reset (LVR) electrical characteristics (VDD = 2.4 - 5.5V, GND = 0V, TA = +25°C, unless otherwise stated) Parameter Signal Minimum Value Typical Value Maximum Value Unit Condition LVR voltage 1 VLVR1 4.0 4.1 4.2 V LVR1 enabled LVR voltage 2 VLVR2 2.7 2.8 2.9 V LVR2 enabled Auxiliary LVR VLVR - 2.3 - V LVR hysteresis window VSMTLV - 50 - mV LVR debounce time (equal to LVR reset width) TLVR - 60 - µs

1. Ordering Information Serial Number Package SH33F2801U/048UR TQFP48 SH33F2801P/032PR LQFP32

1. Package Information TQFP48 Dimensions Unit: inch/millimeter b D HD E HE 13 24 3748 See Detail F A A2A1 L c DETAIL F e Symbol Dimensions in inches Dimensions in mm MIN MAX MIN MAX A1 0.002 0.006 0.05 0.15 A2 0.035 0.041 0.9 1.05 D 0.270 0.281 6.85 7.15 E 0.270 0.281 6.85 7.15 HD 0.346 0.362 8.8 9.2 HE 0.346 0.362 8.8 9.2 b 0.005 0.011 0.15 0.27 e 0.020 TYP 0.500 TYP c 0.004 0.008 0.090 0.200 L 0.018 0.030 0.45 0.75 L1 0.033 0.045 0.85 1.15 θ2 0° 10° 0° 10° Notice: 1.Both package length and width do not include mold flash. 2.Tolerance is ±0.1mm if not specified. 3.Coplanarity:0.1mm max 4.Controlling dimension:mm

LQFP32 Dimensions Unit: inch/millimeter b A A2A1 32 25 9 16 See Detail F L c DETAIL F D HD E HE e Symbol Dimensions in inches Dimensions in mm MIN MAX MIN MAX A 0.057 0.065 1.45 1.65 A1 0.000 0.008 0.01 0.21 A2 0.051 0.059 1.30 1.50 D 0.268 0.281 6.80 7.15 E 0.268 0.281 6.80 7.15 HD 0.346 0.362 8.80 9.20 HE 0.346 0.362 8.80 9.20 b 0.010 0.018 0.25 0.45 e 0.031 TYP 0.8TYP c 0.004 0.009 0.09 0.22 L 0.016 0.031 0.40 0.78 L1 0.035 0.043 0.90 1.10 θ2 0° 10° 0° 10° Notice: 1.Both package length and width do not include mold flash. 2.Tolerance is ±0.1mm if not specified. 3.Coplanarity:0.1mm max 4.Controlling dimension:mm

1. Version Change Record Version Record Date 1.0 Original Version Dec. 2021

This manual is the property of Sino Wealth Electronic Ltd. and its affiliates ("Company"). This manual, including all of the Company's products ("Products") described herein, is owned by the Company according to relevant laws or treat ies. The Company reserves all rights under such laws and treaties, and does not grant you any license to use its patents, copyrights, trademarks and other intellectual property rights. Any technical information in this manual, including functional descriptions and schematic diagrams, shall not be construed as a license to use or exercise any intellectual property rights. The names and brands (if any) of the relevant third parties are quoted in this manual are the property of their respective owners, for identification purposes only. The Company does not make any warranty, expressed or implied, about this manual or any Product, including, but not limited to, implied warranties of merchantability and fitness for a particular purpose. The Company shall not be liable for any use of any of Product described in this manual out of its specifications or the Company’s standard. Except for the special Products specified in the applicable agreement, the Products are designed, developed and manufactured for general commercial, industrial, personal and/or domestic applications only. In particular, the Products are prohibited to be used in following fi elds, such as military, national defense, nuclear energy, medical treatment and others that may cause personal injury, death or environmental damage. Users shall take all actions to ensure that the Products are used and sold in accordance with applicable laws and regulations. The failure or malfunction of semiconductor products may occur. Users of the Products should therefore give thorough consideration to safety design, including redundancy, fire- prevention measures and etc., to prevent any accidents, fire or community damage that may ensue. Especially, the reference application circuit is not guaranteed to be suitable for the specific application of mass production. In the event that users breach the above statement, the Company shall not be liable in whole or in part, and users shall hereby release the Company and its -agents and/or distributors from any claim, damage or other liability; At the same time, users shall indemnify the Company and its agents and/or distributors against all claims, costs, damages and other liabilities, including claims for personal injury or death, arising out of any unintended use of the Product. The information in this manual is related to the Product only. The Company reserves the right to make changes, modifications or improvements to this manual, the Products and services described herein at any time without prior notice. Users are advised to contact our sales department before purchase. The Company has the final right to interpret this manual.

1. Catalogue

20.4.11 The ADC's channel length of hardware triggering register (Single resistance mode) (ADC_HARDCHLH)