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Technical content

Features

  • 3.3V High Precision PLL
  • Jitter Generation OC-192 Compliant
  • Surface Mount
  • Accepts up to 4 Inputs from an External MUX
  • Inputs Compatible with CMOS/LVDS/LVPECL
  • Frequency Translation up to 800 MHz
  • Alarm detection for Loss of Lock/ Loss of Reference condition
  • ROHS Compliant PLL

Data Sheet #: SG124_SFX-424G Page 2 Rev: 05 Date: 09/11/14 © Copyright 2014 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice All Rights Reserved. See website for latest revision. Not intended for life support applications. Specifications Table 2 Symbol Parameter Minimum Nominal Maximum Units Notes fIN Input Frequencies 8 k - 100 M Hz fOUT Output Frequencies (LVPECL) 19.44 M - 800 M Hz Output Frequencies (LVCMOS) 8 M - 130 M Hz Vcc Supply Voltage (3.3 V DC) 3.13 3.3 3.46 Volts ICC Supply Current - 60 - mA LVCMOS INPUT VIH 2 - VCC Volts VIL -0.3 - 0.8 Volts LVPECL INPUT VIH 1.49 - 2.72 Volts VIL 0.86 - 2.125 Volts LVCMOS OUTPUT (Option A) TYP. LVCMOS LVPECL OUTPUT (Option F) VOH 2.275 - V VOL - - 1.68 V TR/TF Rise/Fall Time @20% to 80% - 0.6 1.5 ns SYM Output Symmetry 45 55 % JGEN1 Jitter Generation RMS - 0.35 - ps 1.0 (12 kHz - 20 MHz) JGEN2 Jitter Generation RMS - 0.50 - ps 2.0 (12 kHz - 20 MHz) JTRAN Jitter Transfer - - 0.1 dB 3.0 APR Input Frequency Tracking ±40 - ppm TOP Operating Temperature F = -40 - 85 °C C = 0 - 70 °C SSB Phase Noise (for SFX-424G-DFF-A10Z only) 4.0 at 10Hz offset - -57 -45 dBc/Hz at 100Hz offset - -92 -80 dBc/Hz at 1kHz offset - -120 -110 dBc/Hz at 10kHz offset - -138 -135 dBc/Hz at 100kHz offset - -150 -145 dBc/Hz at 1MHz offset - -157 -147 dBc/Hz at 10MHz offset - -160 -150 dBc/Hz

0 OFF Phase Offset - 5 15 ns

The SFX-424G is a high precision frequency translator that translates up to four inputs from 8 kHz to 100MHz, to output frequencies between 8 MHz and 800 MHz. The SFX-424G supports all major FEC rates such as 15/14, 255/237 etc. SFX-424G is well suited for use in line cards, service termination cards and similar functions to provide reliable reference, phase locked, synchronization for TDM, PDH, SONET and SDH network equipment. The SFX-424G provides a jitter filtered, wander following output signal synchronized to a superior Stratum or peer input reference signal. The SFX-424G includes a lock detect alarm output. The PLL control voltage is brought out through a 470 kΩ resistor and can be used to determine when the pull range limits are reached. The LVPECL outputs may be put into the tri-state high impedance condition for external testing purposes by asserting a high signal to the Enable/Disable pin. Parts are assembled using high temperature solder to withstand surface mount reflow process. This product is compliant with all required ROHS specifications. Absolute Maximum Rating Table 1 Symbol Parameter Minimum Nominal Maximum Units Notes Vcc Power Supply Voltage (OptionD) -0.3 - 4.0 Volts VI Input Voltage -0.2 - Vcc +0.3V Volts Ts Storage Temperature (OptionF) -55 - 125 °C Storage Temperature (OptionA) -40 - 85 °C General Description NOTES: 1.0 155.52 MHz 2.0 156.25 MHz 4.0 For other models and frequencies, consult factory.

Data Sheet #: SG124_SFX-424G Page 3 Rev: 05 Date: 09/11/14 © Copyright 2014 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice All Rights Reserved. See website for latest revision. Not intended for life support applications. Pin Description Table 3 PIN # SYMBOL I/O Level Function 1 SEL0 I LVTTL Input Frequency Select .* 10kΩ Pull down resistor 2 SEL1 I LVTTL Input Frequency Select .* 10kΩ Pull down resistor

3 GND GND Supply Ground

4 Missing

5 VMON O Analog VCXO Control VoltageUnder locked conditions VMON should

be > 0.3V and <3.0V. The Input Frequency may be out of range if the voltage is outside of this voltage range.

6 OD I LVCMOS Output Disable

Disable = Logic 1 Enable = Logic 0 or No Connect

7 GND GND Supply Ground

8 FOUT O LVPECL or LVCMOS Frequency Output

9 CFOUT O LVPECL or GND Complementary Frequency Output

Note: For the LVCMOS Option, this connection is tied to GND

10 LD O LVCMOS Lock Detect

Locked = Logic 1 Loss of Signal = Logic 0

11 GND GND Supply Ground

12 GND GND Supply Ground

13 FIN I LVPECL or LVCMOS Input FrequencyNote: Input is AC coupled

for handling either LVCMOS or LVPECL input signals 14 VCC VCC Supply Power Supply Voltage (3.3V ±5%) Functional Block Diagram Figure 1 Frequency Divider Loop Filter OSC Frequency Divider F OUT (Pin 8) CF Out (Pin 9) F IN (Pin 13) SEL0 (Pin 1) SEL1 (Pin 2) V MON (Pin 5) OD ( Pin 6 ) LD (Pin 10) Microprocessor 470 kΩ 10 kΩ 0.01 µF 10 kΩ

Data Sheet #: SG124_SFX-424G Page 5 Rev: 05 Date: 09/11/14 © Copyright 2014 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice All Rights Reserved. See website for latest revision. Not intended for life support applications. Solder Profile Figure 5 120°C 150°C 180°C 260°C 220°C 360 Sec. Max. 120 S Max. 10 S 60 S Max. Time Temperature 260°C Meets IPC/JEDEC J-STD-020C

Data Sheet #: SG124_SFX-424G Page 6 Rev: 05 Date: 09/11/14 © Copyright 2014 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice All Rights Reserved. See website for latest revision. Not intended for life support applications.

Ordering Information

D = 3.3 V DC ±5% Output Logic A = L VCMOS F = Comp . L VPECL Te m perature Rang e C = 0˚C to 70˚C F = -4 0˚C to 85˚C D = 0˚C to 85˚C Input Logic A = L VCMOS F = L VPECL Number of Input Frequencies 1: 1 Input F requency 2: 2 Input F requencies 3: 3 Input F requencies 4: 4 Input F requencies Input Frequency (Options C - 3) See standard frequencies char t abo ve . * If the desired frequency is not listed, Please Consult a sales representative f or availabilty of additional frequencies . Output Frequency (Options L - A) See standard frequencies char t abo ve . * If the desired frequency is not listed, Please Consult a sales representative f or availabilty of additional frequencies . 8 kHz C 38.880 MHz X 16 kHz D 49.152 MHz Y 64 kHz E 204.80 MHz Z 1.024 MHz F 51.84 MHz 0 1.544 MHz H 61.44 MHz 1 2.048 MHz J 77.76 MHz 2 4.096 MHz K 82.944 MHz 3 8.192 MHz L 100.00 MHz 4 10.00 MHz M 139.2640 MHz 5 16.3840 MHz N 155.520 MHz 6 10.24 MHz O 166.6286 MHz 7 19.440 MHz P 622.080 MHz 8 20.480 MHz R 666.5143 MHz 9 26.00 MHz T 156.250 MHz A

32.768 MHz W Input Freq not listed S

2111 Comprehensive Drive

Aurora, Illinois 60505 Phone: 630-851-4722 Fax: 630- 851- 5040 www.conwin.com Revision Revision Date Note P00 6/30/06 Preliminary Release P01 2/6/07 Added Solder Profile P02 3/1/07 Added Mechanical Drawing P03 6/7/07 Updated Solder Profile P04 1/22/08 Updated Output Frequency Range P05 9/19/08 Added Input Frequency Range to Tbl. 2 00 12/09/08 Change from Preliminary to Release 01 06/17/09 Jitter Change 02 04/06/11 Standard Frequency Updates & Temp Range & Solder Profile update 03 05/10/11 Added phase noise example spec & edited Package Dimensions 04 09/02/14 Standard Frequency Updates 05 09/11/14 Updated Package and Footprint Drawings