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Technical content

Features

/g120 RoHS compliant /g120 Full compliance with ATM Forum UNI SONET OC-3 multimode fiber physical layer specification /g120 Full compliance with the optical performance require- ments of the FDDI PMD Standard /g120 Full compliance with the optical performance require- ments of 100Base-FX version of IEEE802.3u /g120 Industry standard Small Form Pluggable (SFP) pack- age /g120 LC duplex connector optical interface /g120 Operates with 62.5/125 μm and 50/125 μm multimode fiber /g120 Single +3.3 V power supply /g120 +3.3 V TTL LOS output /g120 Receiver outputs are squelch enabled /g120 Manufactured in an ISO 9001 certified facility /g120 Temperature range: 0 °C to +70° C HFBR-57E0LZ/PZ: -40 °C to +85 °C HFBR-57E0ALZ/APZ: /g120 Bail de-latch option

Applications

/g120 OC-3 SFP transceivers are designed for ATM LAN and WAN applications such as: ATM switches and routers SONET/SDH switch infrastructure /g120 Multimode fiber ATM backbone links /g120 Fast Ethernet HFBR-57E0LZ/ALZ/PZ/APZ Multimode Small Form Factor Pluggable Transceivers with LC connector for ATM, FDDI, Fast Ethernet and SONET OC-3/SDH STM-1 Data Sheet

as a figure of merit to assist the designer. Table 1. Regulatory Compliance 2200 V applied between electrical pins. transceiver without a chassis enclosure. to use normal ESD handling precautions. workbenches, and floor mats in ESD controlled areas. HFBR-57E0 exceeds typical industry standards. such fields due to their shielded design.

Figure 5. Recommended application configuration

4.7 K to

4.7 K to 10 K

Note: Inductors must have less than 1 ohm series resistance per MSA. Figure 6. MSA required power supply filter

Table 2. Pin Description

3 Tx Disable Transmitter Disable- Module disables on high or open

4 MOD-DEF2 Module Definition 2 - Two Wire Serial ID Interface 2

5 MOD-DEF1 Module Definition 1 - Two Wire Serial ID Interface 2

6 MOD-DEF0 Module Definition 0 - grounded in module 2

8 LOS Loss of Signal - high indicates loss of signal 3

10 V EER Receiver Ground

11 V EER Receiver Ground

12 RD- Inverse Received Data Out 4

13 RD+ Received Data Out 4

17 V EET Transmitter Ground

18 TD+ Transmitter Data In 6

19 TD- Inverse Transmitter Data In 6

  1. Pin 2 connected to internal ground.
  2. Mod-Def 0, 1, 2. are the module definition pins. They should be pulled up with a 4.7 K - 10 K /g58 resistor on the host board to a supply less than

Mod-Def 0 is grounded by the module to indicate that the module is present. Mod-Def 1 is clock line of two wire serial interface for optional serial ID. Mod-Def 2 is data line of two wire serial interface for optional serial ID.

  1. LOS (Loss of Signal) is an open collector/drain output which should be pulled up externally with a 4.7 - 10 K /g58/g3resistor on the host board to a

by the standard in use). Low indicates normal operation. In the low state, the output will be pulled to <0.8 V.

  1. RD-/+: These are the differential receiver outputs. They are ac coupled 100 /g58/g3differential lines which should be terminated with 100 /g58 dif-

lines will be between 400 and 2000 mV differential (200 - 1000 mV single ended) when properly terminated. supply current is 230 mA and the associated in-rush current will typically be no more than 30 mA above steady state after 500 nanoseconds.

  1. TD-/+: These are the differential transmitter inputs. They are ac coupled differential lines with 100 /g58 differential termination inside the module.

be used for best EMI performance. These levels are compatible with CML and LVPECL voltage swings.

Table 3. EEPROM Serial ID Memory Contents

16 C8 49 41, Note 4 A 79 Note 1 111 Note 5

17 C8 50 50, Note 4 P 80 Note 1 112 Note 5

  1. Addresses 68 - 83 specify a unique identifier.
  2. Addresses 84 - 91 specify the date code.
  3. Addresses 63 and 95 are check sums. Address 63 is the check sum for bytes 0 - 62 and address 95 is the check sum for bytes 64 - 94.
  4. Part number options LZ, PZ, ALZ, APZ, etc. Example: for “AP” option, hexes in addresses 49, 50, 51, 52 and 52 will be 41, 50 , 5A, 20 and 20
  5. Addresses 96-127 are vendor specific data.
  6. Addresses 5 and 6 specify compliance code. Address 5 with Hex 01 for OC-3 and address 6 with Hex 20 for Fast Ethernet.
  7. Address 11 specifies encoding code. Hex 03 for OC-3 and Hex 02 for Fast Ethernet.
  8. Address 12 specifies bit rate. Hex 02 for OC-3 and Hex 01 for Fast Ethernet.

Figure 7. Module Drawing

Figure 8. SFP host board mechanical layout

0.06 L A S B S

  1. PADS AND VIAS ARE CHASSIS GROUND
  2. THROUGH HOLES, PLATING OPTIONAL
  3. HATCHED AREA DENOTES COMPONENT

Figure 9. SFP Assembly Drawing DIMENSIONS ARE IN MILLIMETERS [INCHES].

Stresses in excess of the absolute maximum ratings can cause catastrophic damage to the device. Limits apply to each parameter in isolation, all other parameters having values within the recommended operating conditions. It should not be assumed that limiting values of more than one parameter can be applied to the product at the same time. Exposure to the absolute maximum ratings for extended periods can adversely affect device reliability. Parameter Symbol Minimum Typical Maximum Units Notes Storage Temperature T S -40 +100 °C Supply Voltage V CC -0.5 3.63 V Data Input Voltage V I -0.5 V CC V Differential Input Voltage (p-p) V D 2.4 V 1 Output Current I O 50 mA Recommended Operating Conditions Parameter Symbol Minimum Typical Maximum Units Notes Case Operating Temperature HFBR-57E0LZ/PZ HFBR-57E0ALZ/APZ T C TC -40 +70 +85 Supply Voltage V CC 2.97 3.3 3.63 V Data Input: Transmitter Differential Input Voltage (TD+/-) VI 0.5 0.8 2.4 V Data and Loss of Signal Output Load R L 50 /g58 2 Transmitter Electrical Characteristics HFBR-57E0LZ/PZ (TC = 0 ºC to +70 ºC, VCC = 2.97 V to 3.63 V) HFBR-57E0ALZ/APZ (TC = -40 ºC to +85 ºC, VCC = 2.97 V to 3.63 V) Parameter Symbol Minimum Typical Maximum Units Notes Supply Current I CC 165 210 mA 3 Power Dissipation P DISS 0.55 0.80 W 5a Transmitter Disable (TX Disable) High V IH 2.0 3.5 V Transmitter Disable (TX Disable) Low V IL 0 0.8 V Receiver Electrical Characteristics HFBR-57E0LZ/PZ (TC = 0 ºC to +70 ºC, VCC = 2.97 V to 3.63 V) HFBR-57E0ALZ/APZ (TC = -40 ºC to +85 ºC, VCC = 2.97 V to 3.63 V) Parameter Symbol Minimum Typical Maximum Units Notes Supply Current I CC 95 150 mA 4 Power Dissipation P DISS 0.35 0.55 W 5b Data Output: Receiver Differential Output Voltage (RD+/-) VO 0.4 2.0 V 6a6b Data Output Rise Time t r 0.35 2.2 ns 7 Data Output Fall Time t f 0.35 2.2 ns 7 Loss of Signal Output Voltage - Low LOSV OL 0.8 V 6a Loss of Signal Output Voltage - High LOSV OH 2.0 V 6a Power Supply Noise Rejection PSNR 50 mV

Notes: 1. This is the maximum voltage that can be applied across the Differential Transmitter Data Inputs to prevent damage to the inpu t ESD protec- tion circuit. 2. The data outputs are terminated with 50 /g58 . The Loss of Signal output is terminated with 50 /g58 connected to a pull-up resistor of 4.7 K/g58 tied to VCC. 3. The power supply current needed to operate the transmitter is provided to differential ECL circuitry. This circuitry maintain s a nearly constant current flow from the power supply. Constant current operation helps to prevent unwanted electrical noise from being generated and con- ducted or emitted to neighboring circuitry. 4. This is the receiver supply current measured in mA. 5a. The power dissipation of the transmitter is calculated as the sum of the products of supply voltage and current. 5b. The power dissipation of the receiver is calculated as the sum of the products of supply voltage and currents, minus the sum of the products of the output voltages and currents. 6a. Differential Output Voltage is internally ac coupled. The Loss of Signal low and high voltages are measured with load condition as mentioned in note 2. 6b. Data and Data-bar outputs are squelched at LOS assert level. When the received light drops below LOS assert point, it will force receiver data and data-bar to go to steady PECL levels High and Low respectively. 7. The data output rise and fall times are measured between 20% and 80% levels. Transmitter Optical Characteristics HFBR-57E0LZ/PZ(TC = 0 ºC to +70 ºC, VCC = 2.97 V to 3.63 V) HFBR-57E0ALZ/APZ (TC = -40 ºC to +85 ºC, VCC = 2.97 V to 3.63 V) Parameter Symbol Minimum Typical Maximum Units Notes Output Optical Power BOL 62.5/125 μm, NA = 0.275 Fiber EOL P O -19 -20 -15.7 -14 dBm avg 8 Output Optical Power BOL 50/125 μm, NA = 0.20 Fiber EOL PO -22.5 -23.5 -14 dBm avg 8 Transmitter Disable (High) P O(off ) -45 dBm Center Wavelength /g79C 1270 1308 1380 nm 21, Figure 3 Spectral Width - FWHM Spectral Width - RMS /g39/g79 147 nm 9, 21, Figure 3 Optical Rise Time t r 0.6 1.2 3.0 ns 10, 21, Figure 3 Optical Fall Time t f 0.6 2.0 3.0 ns 10, 21, Figure 3 Systematic Jitter Contributed by the Transmit- ter - OC-3 SJ 0.25 1.2 ns p-p 11a Duty Cycle Distortion Contributed by the Transmitter - FE DCD 0.20 0.6 ns p-p 11b Data Dependent Jitter Contributed by the Transmitter - FE DDJ 0.07 0.6 ns p-p 11c Random Jitter Contributed by the Transmitter OC-3 FE RJ 0.10 0.10 0.52 0.69 ns p-p 12a 12b Notes: 8. These optical power values are measured with the following conditions: The Beginning of Life (BOL) to the End of Life (EOL) optical power degradation is typically 1.5 dB per the industry convention for long wave- length LEDs. The actual degradation observed in Avago’s 1300 nm LED products is < 1 dB, as specified in this data sheet. Over the specified operating voltage and temperature ranges. With 25 MBd (12.5 MHz square-wave), input signal. At the end of one meter of noted optical fiber with cladding modes removed. The average power value can be converted to a peak power value by adding 3 dB. Higher output optical power transmitters are available on special request. Please consult with your local Avago sales representative for further details. 9. The relationship between Full Width Half Maximum and RMS values for Spectral Width is derived from the assumption of a Gauss ian shaped spectrum which results in a 2.35 X RMS = FWHM relationship. 10. The optical rise and fall times are measured from 10% to 90% when the transmitter is driven by a 25 MBd (12.5 MHz square -wave) input signal. The ANSI T1E1.2 committee has designated the possibility of defining an eye pattern mask for the transmitter optical output as an item for further study. Avago will incorporate this requirement into the specifications for these products if it is defined. The HFBR-57E0 products typically comply with the template requirements of CCITT (now ITU-T) G.957 Section 3.2.5, Figure 2 for the STM- 1 rate, excluding the optical receiver filter normally associated with single mode fiber measurements which is the likely source for the ANSI T1E1.2 committee to follow in this matter.

13b. This specification is intended to indicate the performance of the receiver section of the transceiver when Input Optical Power signal characteristics are present per the following definitions. The Input Optical Power dynamic range from the minimum level (with a window time-width) to the maximum level is the range over which the receiver is guaranteed to provide output data with a Bit Error Rate (BER) better than or equal to 2.5 x 10-10.

  • At the Beginning of Life (BOL)
  • Over the specified operating temperature and voltage ranges
  • Input symbol pattern is the FDDI test pattern defined in FDDI PMD Annex A.5 with 4B/5B NRZI encoded data that contains a duty cycle base-line wander effect of 50 kHz. This sequence causes a near worst case condition for inter-symbol interference.
  • Receiver data window time-width is 2.13 ns or greater and centered at mid-symbol. This worst case window time-width is the minimum allowed eye-opening presented to the FDDI PHY PM_Data indication input (PHY input) per the example in FDDI PMD Annex E. This minimum window time-width of 2.13 ns is based upon the worst case FDDI PMD Active Input Interface optical conditions for peak-to-peak DCD (1.0 ns), DDJ (1.2 ns) and RJ (0.76 ns) presented to the receiver. To test a receiver with the worst case FDDI PMD Active Input jitter condition requires exacting control over DCD, DDJ and RJ jitter compo nents that is difficult to implement with production test equipment. The receiver can be equivalently tested to the worst case FDDI PMD input jitter condi- tions and meet the minimum output data window time-width of 2.13 ns. This is accom plished by using a nearly ideal input optical signal (no DCD, insignificant DDJ and RJ) and measuring for a wider window time-width of 4.6 ns. This is possible due to the cumula tive effect of jitter components through their superposition (DCD and DDJ are directly additive and RJ components are rms additive). Specifically, when a nearly ideal input optical test signal is used and the maximum receiver peak-to-peak jitter contributions of DCD (0.4 ns), DDJ (1.0 ns), and RJ (2.14 ns) exist, the minimum the FDDI PMD Annex E minimum window time-width of 2.13 ns under worst case input jitter conditions to the Avago receiver.
  • Transmitter operating with an IDLE Line State pattern, 125 MBd (62.5 MHz square-wave), input signal to simulate any cross-talk present between the trans mit ter and receiver sections of the transceiver. 14a. All conditions of Note 13a apply except that the measurement is made at the center of the symbol with no window time- width. 14b. All conditions of Note 13b apply except that the measurement is made at the center of the symbol with no window time-width. 15a. Systematic Jitter contributed by the receiver is defined as the combination of Duty Cycle Distortion and Data Dependent Jitter. Systematic Jitter is measured at 50% threshold using a 155.52 MBd (77.5 MHz square- wave), 2 23-1 psuedorandom data pattern input signal. 15b Duty Cycle Distortion contributed by the receiver is measured at the 50% threshold of the electrical output signal using an IDLE Line State, 125 MBd (62.5 MHz square-wave), input signal. The input optical power level is -20 dBm average. 15c. Data Dependent Jitter contributed by the receiver is specified with the FDDI DDJ test pattern described in the FDDI PMD Annex A.5. The input optical power level is -20 dBm average. 16a. Random Jitter contributed by the receiver is specified with a 155.52 MBd (77.5 MHz square- wave) input signal. 16b. Random Jitter contributed by the receiver is specified with an IDLE Line State, 125 MBd (62.5 MHz square-wave), input signal. The input optical power level is at maximum “P IN MIN (W)” . See Application Information - Transceiver Jitter Section for further information. 17. This value is measured during the transition from low to high levels of input optical power. 18. This value is measured during the transition from high to low levels of input optical power. At Loss of Signal assert, the receiver outputs Data Out and Data Out Bar go to steady PECL levels High and Low respectively. 19. The Loss of Signal output shall be de-asserted within 100 μs after a step increase of the Input Optical Power. 20. Loss of Signal output shall be asserted within 350 μs after a step decrease in the Input Optical Power. At Loss of Signal Assert, the receiver outputs Data Out and Data Out Bar go to steady PECL levels High and Low respectively. 21. The HFBR-57E0 transceiver complies with the requirements for the trade-offs between center wavelength, spectral width, and r ise/fall times shown in Figure 3. This figure is derived from the FDDI PMD standard (ISO/IEC 9314-3 : 1990 and ANSI X3.166 - 1990) per the desc ription in ANSI T1E1.2 Revision 3. The interpretation of this figure is that values of Center Wavelength and Spectral Width must lie along the appropriate Optical Rise/Fall Time curve.

Ordering Information

1300 nm LED (Operating Case Temperature 0 to +70 °C) HFBR-57E0LZ Standard de-latch HFBR-57E0PZ Bail de-latch 1300 nm LED (Operating Case Temperature -40 °C to +85 °C) HFBR-57E0ALZ Standard de-latch HFBR-57E0APZ Bail de-latch EEPROM contents and/or label options HFBR-57E0LZ-YYY Standard de-latch, 0 to +70°C HFBR-57E0PZ-YYY Bail de-latch, 0 to +70°C HFBR-57E0ALZ-YYY Standard de-latch, -40°C to +85°C HFBR-57E0APZ-YYY Bail de-latch, -40°C to +85°C Where “YYY” is customer specific. Handling Precaution The HFBR-57E0xxZ is a pluggable module and is NOT designed for aqueous wash, IR reflow or wave soldering pro- cesses. For product information and a complete list of distributors, please go to our web site: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright © 2005-2011 Avago Technologies. All rights reserved. Obsoletes AV01-0456EN AV02-2810EN - Januaray 20, 2011