SDE2506

SDE2506 SIEMENS | Alldatasheet

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Nonvolatile Memory 1-Kbit E7-PROM SDE 2506 Preliminary DataMOS IC Features 7 @ Word-organized reprogrammable nonvolatile memory in n-channel floating-gate technology @ 128 x 8-bit organization e 5V supply voltage | e 3 lines processor interface | for data transfer and chip control | @ Data input (8 bits), address input (7 bits), control information input (1 bit) and [P-DIP@t data output are serial @ More than 10° reprogramming cycles per address e Data retention longer than 10 years (operating temperature range) @ Unlimited number of read-out operations without refresh e@ 5 ms erase/write cycle e@ Extended temperature range from — 40 to 110 °C http:/hvww.neonet viautoradio E-mail:juris@mailbox.neonet.lv fensd7t 710482 Riga , Latvia

(top view) vs]. Go stts | ce{]}2 7/]1P Yoo [3 6] NC. o[js s[je | Pin Definitions and Functions Pin Symbol Function

1 Veg Ground

2 CE CE =1 for data input/output, a

CE = 0 for reprogramming 3 a v, ss Tyev supply vottage stint

4 D Data input/output a

D = 1 erase, D = 0 write

6 Not connected i

7 Test input, at Vss

8 TG Test input, remains open

Mec | te 311 63 1 95 |127 | Row 2 | { 1 ! o Control 9 I 32 1 54 1 96 Logic <a) Ves ——— Block Diagram

Data Transfer and Chip Control Three lines having several functions each are required for data transfer between control processor and E7PROM memory. a) Data line D — bidirectional serial data transfer — serial address input — clocked input of a control information — direct control input b) Clock line ® — data input, address input and control bit input — data output — start read-out with takeover of data from memory in shift register or start data- change during reprogramming c) Chip enable line EC - chip reset and data input (active high) — chip enable (active low) Prior to activating the chip, the data, address and control information is clocked in via the bidirectional data bus. These data are maintained in the shift register during reprogramming and read-out up to the second clock pulse. The following data formats have to be input: a) Memory read-out: one 8-bit control word, consisting of — 7 address bits AO to A6 (at first AO being LSB) — 1 control bit, SB = “0”, after A6 b) Memory reprogramming (erasure and/or writing) 16-bit input information, consisting of — 8 bits DO to D7 new memory information (at first DO being LSB) - 7 bits AO to A6 address information (at first AO being LSB after D7) — 1 bit control information, SB = “1”, after A6 Memory Read-Out After data input and with SB = “0” the read-out operation of the selected word address is started by the transition of CE from “1” to “0”. The information being on the data line during chip enable is of no influence. With the first clock pulse after CE = “0” the data word is taken over from the selected memory address into the shift register. After termination of the first @ pulse the data output is in the low impedance state. With every following clock pulse another data bit is pushed to the output. Through the transition of CE from “0” to “1” the data line returns to the high impedance state.

In general, a full reprogramming operation consists of an erasure operation and a subsequent writing operation. During erase all bits of the selected word are set into the uniform “1” state, during writing “O” states are produced according to the information in the shift register. A reprogramming operation is started when after data input and due to chip activation an information SB = “1” is in the relevant cell. Whether an erase or a writing operation is then taking place depends on the information that is on data line D during chip enable. For erasure in state “1”, a “1” must be present at the data input during transition of CE to low. If, however, a writing process is to be started in state “O”, a “O” has to be present at the data line during chip enable. Afterwards, a start pulse at the clock input ® is required for the programming start. The control information has to remain stable at D until the leading edge of the start pulse is teached. The active data change starts with the trailing edge of this start pulse. The programming process is terminated by suppression of the chip enable, i.e. by CE. The reprogramming of a word is initiated with start and followed by an erase procedure. CE = "1” stops erasure. The control bit SB = “1” (in the shift register), which is also necessary for the write process, remains stable even after the termination of erasure. Thus, for writing the selected word, only the data line D has to be changed from “1” to “0”, the chip has to be enabled again by CE = “0” and the data change has to be started by the start pulse. An erase and a write process can also be executed separately. In order to obtain a safe “1” in all 8 bits of the selected memory address by the erase process, a data word is, however, to be entered with 8 times “1” before erasure. During the writing of a word which has not been erased before, the “0” states of the previous and the actual information are added. Test Mode - Total Erasure The test mode is activated, if the input TP (pin 7) is set from 0 V to 5 V = Vpp. To erase the entire memory, the test mode is to be turned on and the address 0 (AO to A6) together with the control bit SB = 1 is to be entered. The subsequent program sequence is identical to the erasure of address 0. As soon as the erase procedure has terminated due to CE changing from 0 to 1, the test mode is to be turned off. RESET A memory which has not been selected is automatically in reset state by state CE = “1”. All flipflops of the sequence control are reset. However, the information in the shift register is maintained and will only be changed by shifting the data. The reset state is also set in the case of the turning-on of the memory (power-on) by an on-chip circuit.

Parameter Limit Values Unit min. max. Supply voltage Voo -0.3 6 Vv Input voltage V, -0.3 6 Vv Power dissipation t Py | 40 ; mW Storage temperature Tstg 125 °C Junction temperature | T, 125 °C Thermal resistance system - air | Risa 100 | K/W Operating Range Supply voltage Voo 4.75 5.25 | Vv Ambient temperature Tp [7 40 110 | °C Characteristics Ty = 25°C Parameter Limit Values | Unit Test Condition min. | typ. | max.| Supply voltage Vo 475|/5 | 525|Vv Supply current Toe | fs | mA Vop = 5.25 V Inputs Input voltage A 08 |V (D, &, CE) Input voltage Vi Vv : (D, ®, CE) | Input current dy 10 pA | Vy =5.25V (D, &, CE)

Characteristics (cont'd) T, = 25°C Parameter Symbol Limit Values Unit = Test Condition min. | typ. | max. Data Output D (open drain) Loutput current | (05 [mA V,=08V H-output current Ty 10 pA Vy= 5.25 V Clock Pulse ® H-clock period | ty 25 | 60 us L-clock period jt 5 us Edge spacing | Ar 25 | bs CE toD | | i Edge spacing | tar 5 | HS CE to > | Data hold time tuo 2.5 us (before/after & trailing edge)) | : Data delay time | top 25 | HS (after © trailing edge) | j Rise time | t, 1 us / Fall time it 1 bps Chip erase duration | ler 5 | 20 ms Write duration tur 5 | 20 | ms Full erasure duration | feta 20 | 25 | ms

| | 0+5V | _t 10k8 I 2 z Vee D ovo io tp ob | Open 8 TG 6 Nc. | Vss Yec 10k2 ° ——h) | BC 259 | | | cE4 te Vv,

0 D Vss |

| D Vss Pe Application Circuit

cE ty te K 4 | | & f 1h A y7 8 1 2 iy 8 F h Kh ' AKT ps AT * too typ N ) )

0 RAs f ae ET EA |

¢ ¢ Adress and Control Bit Start Data | Transfer Tat = SUS: fp= Tp= 1 US typ = 25 us;f .=S us top = 2.5 us; f y= 2.5 us AT=25us be a Diagram Read

a — 2 CE | taxt | tant ’ | ° er ae cae] ps ! —— ae ° sB=1 es oe | ROOK KAKA Is | Start Write | Q OOK HAs K se -1 [ ¢ Data Input |_| writ | (Data, Adresses, Control Bit) Erase or Write | AT=25us | CE " , i | text |? py} ft | D | : | a | . . . | Data Input | Data, Adress | Control Bit Diagram Reprogramming