SDA6310 | DigiCamel IC Datasheet

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SDA6310 SIEMENS | Alldatasheet

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© Internal reference voltage source. @ Automatic gain control (AGC) with integrated AGC amplifier. @ Output for adjustable delayed tuner AGC. © Oscillator circuitry for VCO with external varicaps. @ Symmetrical demodulator output for inphase arm. ‘vp00sos1 @ Open collector counter output for measurement of oscillator frequency. P-DIP-20-1 @ Phase detector circuitry with offset adjust and turn off facility, including arm filters to suppress high frequency terms. @ Data separator for inphase and quadrature arm, output voltage levels TTL input compatible. Type Ordering Code Package SDA 6310 Q67000-A5088 P-DIP-20-1 The SDA 6310 is an integrated circuit for amplification and demodulation of QPSK-modulated signals. M™ 6235605 006354) 751 mw Semiconductor Group 38 08.93

(top view) P-DIP-20 cnoo[]1 4 2ofqace ono at|2 19[ ¥en w1f3 18[ vs | i2[]s a7[Jorabs : or ouT[|s 16 osc 1 i poorr(|6 1{ Josc 2 | pour 1[]7 14[ ]P0 ouT Dour 2[|s 13[ ]PDADJ imon 1] 9 121 Veer Mon 2[} 10 1] Feouster E0468 M@ 6235b05 0063542 698 a Semiconductor Group 39

Pin Definitions and Functions Pin No. [Symbol _| Function 1 [GNDD —_[ Digital GND

2 Analog GND

3 IN1 QPSK input 1

4 |in2” ~~" @PSK input 2, inverse polarity

5 DT OUT Delayed Tuner AGC output

6 Phase Detector off input

7 DOUT1 Data output 1

5 [IMON1 | Inphase monitor output? 40 [IMON2 _| Inphase monitor output 2 "1 Feet Counter frequency output

12 Vaer Reference Voltage Source

|PDADJ _| Phase Detector offset adjust input

14 Phase Detector output

16 Oscillator pin 2 _

16 Oscillator pin 1

17 DTADJ Delayed Tuner AGC adjust input

18 Analog supply voltage

19 Digital supply voltage

20 AGC Automatic Gain Control

M@@ 4235605 0063543 524 a Semiconductor Group 40

Pin No. Description _ 7 1 Digital GND (counter, data separator, automatic gain control unit).

2 Analog GND (AGC amplifier, oscillator, phase detector, reference voltage

source). Reference point for input signal, input filter, PLL loop filter and offset adjust, oscillator, and AGC voltage. Short connection to digital GND required. 3 QPSK input 1. 4 QPSK input 2, inverse polarity. 5 Delayed tuner AGC output, open collector.

6 Phase detector off input, high level switches the phase detector output to high

impedance state. 7 Data output 1, inphase arm. 8 | Data output 2, quadrature arm 9 | Inphase monitor output 1, inverse polarity. 10 Inphase monitor output 2. , "1 Counter frequency output, open collector output (fount = fear/256)-

12 Reference voltage source output, DC reference point for phase detector output,

phase detector offset adjust, and delayed tuner AGC adjust. 13 Phase detector offset adjust input. 14 | Phase detector output, PLL loop filter.

56 Oscillator pin 2, inverse polarity oO -

16 | Oscillator pin 1 (Oscillator pins 1 and 2 may be used as inputs to force the oscillator). 7 Delayed tuner AGC adjust input. {f no delayed tuner AGC is used, connect to digital supply voltage.

18 Analog supply voltage (AGC amplifier, oscillator, phase detector, reference

voltage source). . 19 Digital supply voltage (counter, data separator, automatic gain control unit). 20 | Automatic gain control filter pin, low voltage corresponds to maximum gain of | the QPSK input amplifier. ME 4235605 0063544 yoo = ‘Semiconductor Group 4

) | , GNDA level | Delayed Yeo | 2 Det Tuner 9 AGC AGC INt % 3 bal DTAD! ‘ opsk ” Input Amplifier | oT ouT } 5 6 . Phase Detector ost ee =. 6 [TTT TT 5 rs | al

7 L oto 4

Sep, ecu/TmL poaDs 8 8 Reference

9 Voltage ae 12

| COUNTER es04023 | Block Diagram mm 8235605 0063545 377 Semiconductor Group 42

Power Supply, Reference Voltage Source The SDA 6310 has separated power supplies for digital and analog parts. A temperature stable reference voltage source is used for the operating points. QPSK Input Amplifier, AGC The input amplifier is a variable gain amplifier with symmetrical input. The gain control voltage is. derived from a level detector at the amplifier output. If the input level exceeds an adjustable value, a sink current is generated which may be used to reduce the tuner output level. Oscillator The symmetrical oscillator contains a divider by 2 to generate the 0° and 90° signals used for the demodulation of the inphase and the quadrature component. For frequency measurement there is a counter output with carrier frequency divided by 256. Phase Detector There is an inphase and a quadrature arm consisting of AM demodulator and armfilter to suppress . high frequency terms. The demodulated and filtered inphase and quadrature components are passed to the data separator and the multiplier/adder circuitry. The muliplier/adder circuitry is used to produce a phase detector characteristic with 4 stable points. The phase detector offset current is adjustable, the output can be tumed off to high impedance state. The demodulated and filtered inphase component can be monitored at a symmetrical output. Data Separator 2 data streams are separated from the analog inphase and quadrature component signals and converted to TTL input compatible voltage levels. MH 4235605 00b354b 233 mI Semiconductor Group 43

T,=—40°C to 85 °C Parameter ~~ [symbol Limit Values Jost Remarks ‘nin [an fnaieg SND mor for OFSK np eC Delayed tuner AGC output ive. jo |132 |v Phase detector off input vy. jo —'|ra2—Ss[v Data output 1 -5 Data output2 Is -5 Inphase monitor output 1 ly -5 — Inphase monitor output 2 Io (|-5 ~ Reference voltage source mo | 1 mA __| except capacitive : | load current at | power on Phase detector offset : — adjust input Vio Vie v Phase detector output Vis _ Ve-15 Vv a Delayed tuner AGC adjust FE A input Vir Vie v Analog supply voltage [Me fo 32 |v Digital supply voltage Mo fo |s92 lv Storage temperature Ts Thermal resistance Rn amt -_ ESD-Voltage, HBM Veso 4 KV 100 pF, 15002 MH 4235605 0063547 177 Semiconductor Group 44

Absolute Maximum Ratings (cont'd) Parameter - Symbol Limit Values Remarks min. max. Operating Range Analog supply voltage Ve 108 [132 Vv Digital supply voltage ‘Vip 10.8 113.2 v Oscillator frequency fis1e | 70 [240 [MHz | QPSK carrier frequency Sas 35 '420 [MHz | Data rate DR. | 0 415 Data output load Cre 0 H10 | Reference source DC current hy oc ~25 [06 mA Reference source peak current le -5 inl mA Ambient temperature Ty 0 70 °C WM! 4235605 0063548 OOb Semiconductor Group 45

AC/DC-Characteristics (cont'd) Parameter Symbol! Limit Values Unit | Test Condition in [yp [mex Delayed Tuner AGC (DTAGC) Vi =2V, V5=5V DTAGCONcurrent [iso [3 |6 mA | Vay =Vy7 + 0.1 V® DTAGC OFF current | Is ocr 0.05 05 |mA |V~y=Vi,-02V DTAGC characteristic | A/jAVo0 20/30 45 | mAN | Vay = Vyr— 10 mV...Viy +10 mV DTAGC DC volt. range |V;, 10 Vio |v Frequency Response reference frequency 40.15 MHz high level upperlimit [fray [130 | 150 MHz [V;4=98 dBinV, - 1 { -3 dB IMON 1,2 high level lower limit | fins 25 | MHz | V;,=98dBNV, oe -3 dB IMON 1,2 low level upper limit Snax 130 180 MHz | Vs 4=52 dB, - | ~3 dB I MON 1,2 low level lower limit Sin .25 |30 |MHz | V;4=52dBV, : =3 dB MON 1,2 Input Amplifier fay = 118 MHz AGClow voltage | Vao., 05 1 15 |v V5 4= 52 dB AGC high voltage Vann = 2.7«(3.2-13.7 |V | Vy q=98 div Minimum input level Vs, em 4652 [ABV | Vy =0.2V Maximum inputlevel —Va.emax |98 | 105 |109 | dBiV | Vay=5V 2) Note 2 (see page 54) M@™® 8235605 0063550 7b4 mt Semiconductor Group 47

AC/DC-Characteristics (cont'd) Parameter Symbol | Limit Values | Unit_| Test Condition wi. [typ [ras Phase Detector (PD) PDGain PDG {700 950 11200 [par] | rad PD DC range Va 125 Ve [Vg- lV _ 15 | PD large signal i offset current hee |-30 0 |30_WA PD DC-offset current [hee |-30 0 [30 [WA |Vs4=0 PD offset adjust Tw |-90 |-30 WA |Vig=15V current range Tae |5 30 WA |Vig=4.5V PD offset adjust Ald WAV | Vig=25335V characteristic AVi3 PD offset adjust kQ input impedance | ; Leakage current ‘have 02 pA | Via=Vra Ve=Vie PD OFF | a _ PD source resistor iRe 300 | 400 __ kQ _ Input voltage PDOFF | Veorr [2.0 | vv i - input voltage PDON | Voon { os iv Lowinputcurent [fe [-10 |-06|0 [WA | Ve=0 High input current ‘Tew Jo [005 [1 [WA | Ve=Vie Monitor Output Monitor DG voltage [Ve=. |Vie~ | Vie |Ve- |V —_ Vo= [4 35 |3 fo Monitor AC voltage | Vyo.- |350 500 |650 | mVpp 3) Note 3 (see page 55) 4) Note 4 (see page 56) W® 6235605 0063551 &T0 Semiconductor Group 48

| 1 20 GNDO AGC ° 100 nF Lt 2 » 3yH GND A Yeo ° 100 nF | ‘onF ® But ‘psx Nt Yea — o Input Tr 100 e P | fo 4 7 } IN2 oTADs ° 40 nF Tir 5 6 10 nF | ° (a) orour = ast 4 | 1 7 he 101 ° POOFF = 0s fm | eet 7 % DouT1 — PDOUT | 10 F AAR | t [] 0x2 I ‘tur | 8 B L i OouT2 POADS S 10 pF MON 4 Veet our = 100 ls 10 1 ana | ITMON2 COUNTER = © uesos82% Ce Test Circuit M@™@ 8235605 0063553 473 Semiconductor Group 50

05°]? Ir - Miz ° ° 8 ° IN4 Ya o+12V - aa x6960 7 10k@ Y IN2 oTAD 4nF an poceeeee eee n--5

1 Tor H

5 16 1 = 9) 10 0F AkQ : ToT = ast 4 . ry ! | : ' ' 330 nH 7 3B 04 | 6 6 ! Ldall ' POOF = OSC 2 1 cH! tL oF { 7 % TOF Dour? = PDOUT IH [Jima []3.9%2 330F '

8 B TT tf :

DouT2 —POADJ \\ ° 1 MON 4 Veer : 100 nF Test Points rt ” 10ka o—"Iimow2 counrer c ons ° ves04825 Application Circuit 40.15 MHz M@™ 8235605 0063554 30T a ‘Semiconductor Group 51

| an } 502 2 9 i} PSK % Input GND A Yoo +12 a ° ° Miz ° ° 18 ° IN4 Ven 0 +12V < aa voxeo | L512 4 7 10k2 Y IN2 OTAQJ ink 1 J 6.8pr H s % LOE y100F akg ot | oTouT = ost 4 : | ' ‘ | 36 nH FR 8.804 H ‘ 100F i } PO OFF osc2 i} H ' 1k2 ' T 680F t Lriee---pe---- ed 10 pF 7 % | DouTt — PO OUT IH | _f ama []15K2 33 nF 8 102} Dour? —PDAD toy pe nF 9 12 ° TMON 4 Vege 100 nF Test Points ” ” 10ka ° IMON2 COUNTER = 0+5V ‘veso4676 Application Circuit 118 MHz @™® 8235605 0063555 24b Semiconductor Group 52

AGC Characteristic, Linearized Yeacn tat Vs sy 6 8 90 10 BAN Vout Yon ven04969 Load Characteristic Load Characteristic lay uA ACG Load Characteristic, Linearized lasm p+? 0 Ya 18 78 80 82 8 sa 90 92 9% 96 /HV -10 > eer é) Vyp Adjusted to Jpg = 0 at 86 dB/pV 004970 MM 8235605 0063556 142 Semiconductor Group 53

Delayed Tuner AGC Characteristic I mA Delayed Tuner AGC Characteristic, Linearized Tow V, 24.5 Logg Vo Yin 300 “m0 -100 0 wo 200 = 300 Vore Von uED04973 M@™® 8235605 0063557 019 Semiconductor Group 54

Definition of Phase Detector Gain (PDG) V4, 4= 50 Ving fy, y= 40.15 MHZ * THz = 40.15 MHz © af % Ys, 16° 300 Ving fara fs, 16° 80.3 MHZ R= 1kQ Ti Vy =0 = 12 1320 i va) = Vigra V2V)-- Steer cian fi Vp / tC) f f ; rad * iyi ye “Veh : ‘ Mt ' 1 1 1 2 3 4 1 diy Ma) 1 | ain R dr Dar | Vy-Vg=0 vue0o.972 Theorie: V(@) = V, sin@ sign (cos) - V, cos® sign (sind) PD-GainPDG = /0.5Vop/R a (not exact because of non ideal waveform) z 1 0.816 Vop Approximations: POG = 1.15 -/0.5Vpp/R — = j2n 1 2.56 Vims PDG = 1.09 | ——_Vims/R — = DG = 1.09, Jp Vins ag Rrad Application hint: PD-Gain is lower with data modulation on, typ. — 8 dB. M@™ 8235605 0063558 TSS a Semiconductor Group 55

PD OFF Input Characteristic (TTT TTT TT Witt Tt tt tt He ed pitt TPT Ty Pir ry Pee EEA ; 4} |-+- eT TP PP LT Pep AHR Lit T TPT ry rier rr mee SER Ae EERE EEE Ete EH EEE HEHE AGE CH BREE SSBB ESSA SRE 4 1.0 i -05 0: 05 mA Ie Low Input High Input Current Current ueDoK97 Note 5 Application Circuit for use of Internal Oscillator {not subject to production testing) Pin 15 Pin 16 ? ? Center Freq. [80.3 MHz [236 MHz | Remarks L 330nH [36nH | Coil loa | CQ 12pF —'|8.2pF _—_| Ceramic Capacitor Gq G CG 12pF 8.2pF __| Ceramic Capacitor Lt an | ’ Rp 2kQ 1k __| Resistor sous? — M@® 8235605 0063559 99, Semiconductor Group 56

Product Information

SDA6310 specifications and overview.

Summary

DSR QPSK-Demodulator

Description

DSR QPSK-Demodulator

Source title SDA6310 Datasheet(PDF) - Siemens Semiconductor Group

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