SDA6102X

SDA6102X SIEMENS | Alldatasheet

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TV-SAT-PLL with I?C-Bus SDA 6102X : and Four Chip Addresses * Preliminary Data Bipolar IC : Features | z @ 1-chip system for MPU control (I?C-bus) - @ 4 programmable chip addresses @ Short pull-in time for quick channel switch-over and te optimized loop stability ie @ 5 high-current switch outputs (20 mA) - @ Software-compatible with SDA 3302 series VPS 08119 ; @ Oxis Ill-technology t P-DSO-16 x Type Ordering Code | Package _ SDA 6102X Q67000-A5016 | P-DSO-16 (SMD) . Combined with a VCO (tuner), the SDA 6102X device, with for hard-switched chip addresses, forms : a digitally programmable phase-locked loop for use in satellite indoor units. It is compatible with the . standard SDA 3202-2 device used in television sets with frequency synthesis tuning. With a : 4.43-MHz quartz crystal, the PLL permits precise setting of the frequency of the tuner oscillator up 5 to 2.27 GHz in increments of 69.2 kHz. Higher frequencies (up to 2.4 GHz) are possible at the 2 expense of coarser frequency resolution. The tuning process is controlled by a microprocessor via 3 an I?C-bus. The I°C-bus noise immunity has been improved by a factor of 10 compared to the SDA 3302-2, and the new crystal oscillator generates a sinusoidal signal, suppressing the higher- order harmonics, which reduces the moire noise considerably. 34 10.92

pocdi] 6 bouo 5 o1cg2} *5pOGND ‘ 02 cj3) = 4 pO TVSAT - SDA 4 BD TVSAT i scicgqs} 12-0, 2 P4og6é} = 1 fo Po P3c7 10 FO CAU P2048 9foP1 UEPOKOM j * i } | Pin Configuration (top view) Pin Definitions and Functions ; Pin No. T ‘Symbol! Function . 1 | PD Input active filter / charge pump output 2 i Qi Quartz crystal €

3 Q2 Quartz crystal :

4 SDA Data input / output for I?C bus $

5 SCL Clock input for I2C bus =

6 P4 Port output (open collector) 3

7 P3 | Port output (open collector) a

8 p2 | Port output (open collector) 9 !Pq Port output (open collector)

10 Teau Address switch input -

1 PO Port output (open collector) .

12 Vs Supply voltage -

13 TVSAT Non-inverting signal input :

14 TVSAT | Inverting signal input -

15 GND | Ground :

16 Output active filter . Semiconductor Group 35

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Be So | > i Za = i FS Bh ' : Sm ia Tie ef 2 =| |= = . Bl |S 8) sca . a ~ = ry > - ol + uo BN 5 e |F a - HFS Block Diagram - Semiconductor Group 36

Circuit Description : Tuning Section (refer to block diagram) a TVSAT, The tuner signal is capacitively coupled as a differential signal at the TVSAT/TVSAT } TVSAT __ inputs. Alternatively, the tuner signal is capacitively coupled at the TVSAT-input and the 5 TVSAT input is decoupled to ground using a capacitor of low series inductance. Pa The signal subsequently passes through an asynchronous divider with a fixed ratio of ~ P =8, an adjustable divider with ratio N = 256 through 32767, and is then compared in 2 a digital frequency/phase detector to a reference frequency fper = 8.65 KHz. s Q1,Q2 This frequency is derived from a balanced, low-impedance 4.43 MHz crystal oscillator (pin Q1, Q2) by dividing its output signal by Q = 512. The phase detector has two outputs UP and DOWN that drive the two current sources | + and | — of a charge pump. If the negative edge of the divided VCO-signal appears - prior to the negative edge of the reference signal, the | + current source pulses for the i duration of the phase difference. In the reserve case the | — current source pulses. ; PD, UD _ If the two signals are in phase, the charge pump output (PD) goes into the high- : impedance state (PLL is locked). An active low-pass filter integrates the current pulses a to generate the tuning voltage for the VCO (internal amplifier, external output transistor at UD and external RC-circuity). The charge pump output is also switched into the high- impedance state when the control bit TO = 1. Here it should be noted, however, that the tuning voltage can alter over a long period in the high-impedance state as a result of . selfdischarge in the peripheral circuity. UD may be switched off by the control bit OS to . allow external adjustments. 3 By means of a control bit 5I the pump current can be switched between two values by : software. This programmability permits alteration of the control response of the PLL in 3 the locked-in state. In this way different VCO gains in the different TV-bands can be : compensated, for example. : outputs and can be used for direct band selection. The test bit T1 = 1 switches the test é signals faer (4.43 MHz/512) and Cy (divided input signal) to P3 and P4 respectively. . CAU Four different chip addresses can be set by appropriate connection of pin CAU. 3 7C- Bus Interface Data are exchanged between the processor and the PLL on the I?C-bus. SCL, SDA The clock is generated by the processor (input SCL), while pin SDA works as an input . or output depending on the direction of the data (open collector; external pull-up s resistor). . Both inputs have hysteresis and a low-pass characteristic, which enhances the noise - immunity of the I?C-bus. - The data from the processor pass through an I?C-bus control. Depending on their - function the data are subsequently stored in registers. If the bus is free, both lines will be - in the marking state (SDA, SCL are high). Each telegram begins with the start condition and ends with the stop condition. Start condtion: SDA goes low, while SCL remains high. . Semiconductor Group 37

SIEMENS SDA 6102X ° Stop condition: SDA goes high, while SCL remains high. All further information transfer : takes place during SCL = low, and the data is forwarded to the control logic on the * positive clock edge. i The table ,,bit allocation’ should be referred to in the following paragraph. 3 All telegrams are transmitted byte-by-byte, followed by a ninth clock pulse, during which 3 the control logic returns the SDA-line to low (acknowledge condition). The first byte is 3 comprised of seven address bits. These are used by the processor to select the PLL i from several peripheral components (chip select). The eighth bit is always low. ~ In the data portion of the telegram the first bit of the first or third data byte determines e whether a divider ratio or control information is to follow. In each case the second byte : of the same data type or a stop condition has to follow the first byte. Vs, GND When the supply voltage is applied, a power-on reset circuit prevents the PLL from setting the SDA-line to low, which would block the bus. i Semiconductor Group 38

Circuit Description (cont'd) . Bit Allocation i MSB A = Acknowledge 3 Address byte 1 1 i} 0 i?) MA1 MAO i} A , 7 ee } ¥ Bye ver 0 ni4 nid ni2 nit nto no ne A : Byer n? 6S mt ene | + Ss oT TO 1 1 1 08 A . re ; F ji i : Beast PA PS) P2 PY XOX POX : Divider Ratio N = 16384 x n14 + 8192 x n13 + 4096 x N12 + 2048 x n11 + 1024 x n10 + 512 x n9 + 256 x n8 + +128 x n7 + 64x n6 + 32xn5+16xn4+8xn3+4xn2+2xn1+n0 . Port Switching : PO...P4=1 Open-collector output is active. : Pump Current Programming : 5l=4 High current : UD Disable 3 oS=1 UD is disabled < Test Mode : T1,T0=0,0 Normal operation T1=1 P3 = free, P4 = Cy To=0 Tristate: charge pump output PD is in high-impedance state. Chip Address Switching : MA1 MAO Voltage at CAU : a) 1 open-circuit . 1 4 | 9.1) Me | : Semiconductor Group 39

———— Addressing ———————ACK-—1. Byte—/-ACKe/—2. Byte FA CK—3 Byte ACK 4, By tePACKY 3 UW Od od ed rd ds : TWA LAL LL AL AA : { START? 2 3 4 5S 6 7 86 9 1 86 9 1 6 9 41 8 9 1 8 9STOP : vue : SS ee ; Pulse Diagram ‘ Telegram Examples Start-Addr-DR1-DR2-CW1-CW2-Stop Start = start condition . Start-Addr-CW1-CW2-DR1-DR2-Stop Addr = address : Start-Addr-DR1-DR2-CW1-Stop DR1_ = divider ratio 1st byte Fy Start-Addr-CW1-CW2-DR1-Stop DR2_ = divider ratio 2nd byte - Start-Addr-DR1-DR2-Stop CW1 = control word 1st byte a Start-Addr-CW1-CW2-Stop CW2 = control word 2nd byte £ Start-Addr-DR1-Stop Stop = stop condition ’ Start-Addr-CW1-Stop B Semiconductor Group 40

Absolute Maximum Ratings : Parameter l Symbol Limit Values Unit | Remarks : min. max. 3 Supply voltage | Vs -0.3 16 Vv | : Output PD VA -0.3 Vs Vo . Crystal oscillator pins Q1,Q2 | V2 '-0.3 Vs Vv p Bus input/output SDA ‘Vs -0.3 6 Vv . Bus input SCL Vs 1-03 \\6 Vv Port outputs PO ... P4 Ve '-0.3 16 iv Chip address switch CAU Vio -0.3 Vs v . Signal inputs TVSAT, TVSAT | V3 -0.3 ‘0.3 Vv for V;=0V a Output active filter UD Vig io 0.3 | Vs Vv “ Bus output SDA Tay -1 5 mA _— open collector a Port outputs PO ... P4 Te -1 20 mA pen collector Total port output current Dy 25 mA Junction temperature | T, 125 c . Storage temperature Tag -40 125 c x Thermal resistance Ring 125 K/W | S (junction to ambient) | | | Operating Range : Supply voltage : "Vg +45 55 lv 7 : Ambient temperature Ts -20 80 c < Input frequency fia 2400 | MHz (at 25 ‘C) 5 Crystal frequency 7 fo - 4.69 MHz a Programmable divider factor N 256 32767 Semiconductor Group 44

AC/DC-Characteristics : Parameter Symbol Limit Values Unit | Test Condition | Test : | min. | typ. | max. | Circuit 3 Supply current iIs 45 59 mA |%=5V 1 : Crystal oscillator ‘fe | 4.43 MHz | series capacitance18 pF | 1 - frequency | i Saat = 4-43 MHZ : Oscillator amplitude (voltage across 2.6 v 2 crystal)” Margin from 1st (fundamental) to 20 dB 2nd and 3rd harmonics* Signal Input TVSAT/TVSAT i Sensitivity inmVrms|ay, | —10/ 3/315 [dBm | f,)= 500 MHz... 2.4 GHz |2 : into 50 Q 71 1 : Port Outputs PO ... P4 (switch with open collector) H-input current Tex 10 HA |V4=13.5V 3 L-output voltage Vou 05 |V | =20mA 3 . The sum of the currents in ports PO to P4 may not exceed | 3 25 mA. | : Phase-Detector Output PD (V, = 5 V) é Pump current Tn +90 4220/4300 |pA |5!=high; V,=2V 4 . Pump current Tay +22 |+50 |+75 pA |5l=low; V,=2V 4 $ Tristate current Tyz [-5 jo | +5 nA |T1=1;V,=2V 4 : Output voltage Viv 1.0 | 25 1V 4 3 Active Filter Output UD (Test mode TO = 1; PD = tristate) Output current —Iy, | 500 HA [Vp=0.8Vil,=90HA 4 Output voltage Vie 1100 =mVv |v. =0V 4 - Chip Address Switch CAU . input current | Tion | }50 ~T pa Viou = 5 V 6 - input current {Lio | 150A 6 ; * Design note only: no 100% final inspection - Semiconductor Group 42

AC/DC Characteristics (cont'd) : T, = — 20 to 80 C; V5= 4.5 to 5.5 V i a _ i Parameter Symbol Limit Values Unit | Test Condition Test i Bus Input SCL, SDA § H-input voltage Vas 55 OV 5 : L-input voltage Van 15 Vv 15 s H-input current Tan Van = Ve 5 L-input current ala BA i Vg = OV 5 Bus Output SDA (open collector) “ H-output current Ton 10 [pA | V4 = 5.5 V 5 a L-output voltage | Vaow 0.4 | Vila =3.mA \\5 : Edges SCL, SDA ° Rise time ta 1+ [us 5 Fall time ‘te ! 03 |us . 5 Shift Clock SCL < Frequency Ifs 0 | “T4100 | kHz | 5 ; . H-pulse width ts ‘4 i us {5 7 L-pulse width to 47 us 5 £ Start 1 Set-up time Teusta 47 us 5 4 Stop a —— - a Set up time t susto ‘us 15 Data Transfer z Set-up time | sunar [0.25 | us! / 5 : Hold time Typoat | 0 | ns 5 - Input hysteresis SCL, SDA* 300 | | mV - ee _— po Low-pass cutoff frequency SCL, SDA* 500 ‘kHz - * Design note only: no 100% final inspection - Semiconductor Group 43

SIEMENS SDA 6102X : — SSS - 1 Vs SV . ! P 2p, []5x0 ; 18 pF spa 16 f eer i

443 Miz 3| 6102 Counter :

GND f= Fpge 512 i *.no cable | 3 . Qt 18 pF + ; 443MHzSS 2 Qo : Test Circuit 1 . | Signal- Power a generator 6 db meter . 502 x }atfenuator ® 1 son $ +5V SV Signal- ae Ga []sks | | generator i - | 502 + attenuator * 6 Frequency | : ts nF 1h counter i * : + ze f = fg /B*N) : *...no cable GND - UESOSO44 . Test Circuit 2 : Semiconductor Group 44

502 ‘ Mo Is : 6 : UESOKO6S: i Test Circuit 3 _ - : My O44 2 1 : 2kQ 12kQ 48kQ > 6 ly 9k8 36 ka : Vig : 40kQ i UESO4046 . Test Circuit 4 : Semiconductor Group 45

SIEMENS SDA 6102X : taur i - 3 SDA i tow. fHiGH tr te tsusto 4 SUSTAY | i } - | | | i scl | | UE 1292 | tHosTa _t [suoat tHDoaT i Test Circuit 5 3 tsusta Set-up time (start) THpsTa Hold time (start) THIGH H-pulse width (clock) tow L-pulse width (clock) . T supat Setup time (data transfer) 7 tT yppaT Hold time (data transfer) : t susto Set-up time (stop) 3 feur Bus free time 3 te Fall time 3 te Rise time ’ All times related to 10 % and 90 % values z % | ; Veau Tau | 10 | Vise. Vopa fi i souk | : ' | & H e wr : = UES04048 : es06067 . Test Circuit 6 i Semiconductor Group 46

OO | : | es TUNER Ky | : \\ fosc nF : | 1n *4) 4.43 MHz i 4 Hb 36 36 10 k2 | | fn ' 4.43MHz SS 1p * BY qT T “TL 1nF zzra[] 73" i § Q2 1 TVSAT TVSATQ Ye . —_ PD GND | i | 22k2 490 nF scl sl : i SDA 6102 X SOA + from 5 | vo SDA uC CAU PO P1P2 P3 P4 i "4) This configuration of the coupling capacitors crysral oscillator improves the balance of the ~ and thus reduces crosstalk 4nF 1 : ues04049 I : Application Circuit. Q Semiconductor Group 47

Loop Filter : G G ‘ |— ; “Lad. UE 1295 i Application Circuit 7 : Calculation of loop filter . Loop bandwidth: — @_ = V(Ip x Kyco) / (C, x P x NY : Attenuation: a=0.5xOgxRxC, . P = prescaler a N = programmable divider : Ip = pump current : Kyco = tuner slope B R,C, = loop filter $ Example : P= 8, N= 11520, Ip = 50 pA; Kyco = 18.7 MHZ/V, R = 22 kQ, 3 C, = 180 nF; @p = 237 Hz, f, = 38 Hz, a = 0.67 Note: The high-impedance port outputs and CAU can be decoupled from external noise with a : capacitor of 1 nF. z It is important to keep to the I?C-bus specification concerning maximum capacitance and ° impedance. : Semiconductor Group 48

SIEMENS SDA 6102X . Sensivity at TVSAT/TVSAT Input : (typical at 25 ‘C) x Bm vxaavse i 0/224 GOW La GUE : Wi) specification Range YUYGEE ‘ orm v YLMHMVGW4aY0 YU : | : me ” -EEEEECEENG ia -50/0.7 a | 2 400 600 800 1000 1200 1400 1600 1800 2000 2200 2400 MHz 2600 I?C-Bus Noise Immunity . Sinusoidal Noise Pulses are Applied viaa ‘ Coupling Capacitance of 33 pF to the SCL- and SDA-Inputs 3

6 UE 1305

Yes | | | r to £ 1 5 | | Minimum Possible Noise Immunity : met tet Hy : H ] fl i ‘ . z A | yoy | : 0 a 2 3 4 5 6 7 8 9 10 1 «12 13 MHz 15 —- - Semiconductor Group 49