SDA5649X

SDA5649 SIEMENS | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 26

Technical content

Features

• Single-chip receiver for PDC data, broadcast either – in Broadcast Data Service Packet (BDSP) 8/30/2 according to CCIR teletext system B, or – in dedicated line no. 16 of the vertical blanking interval (VPS)
• Reception of Unified Date and Time (UDT), Network Identification code (NIC), and Short Program Label (SPL) broadcast in BDSP 8/30/1
• Reception of bytes no.38 through 45 of teletext header row containing clock time
• Low external components count
• On-chip data and sync slicer
• I2C-Bus interface for communication with external microcontroller
• Selection of PDC/VPS operating mode software controlled by I 2C-Bus register
• Pin and software compatible to PDC/VPS Decoder SDA 5648
• Supply voltage: 5 V± 10 %
• Video input signal level: 0.7 Vpp to 1.4 Vpp
• Technology: CMOS
• Package: P-DIP-14-3 and P-DSO-20-1
• Operating temperature range: 0 to 70°C Semiconductor Group 44 12.94 SDA 5649 SDA 5649X Functional Description The CMOS circuit SDA 5649 is intended for use in video cassette recorders to retrieve control data of the PDC system from the data lines broadcast during the vertical blanking interval of a standard video signal. The SDA 5649 is devised to handle PDC data transported either in Broadcast Data Service Packet (BDSP) 8/30 format 2 (bytes no. 13 through 25) of CCIR teletext system B or in the dedicated data line no. 16 in the case of VPS. Type Ordering Code Package SDA 5649 Q67100-H5156 P-DIP-14-3 SDA 5649X Q67106-H5157 P-DSO-20-1 Tape & Reel

Furthermore it is able to receive the Unified Date and Time (UDT) information transmitted in bytes no. 15 through 21, the Network Identification code (NIC) carried in bytes no. 13 and 14, and the Short Program Label carried in bytes no. 22 through 25 of packet 8/30 format 1. For reception of clock time when no BDSP 8/30/1 is present the SDA 5649 can be enabled to extract bytes no. 38 through 45 of the teletext header row. All operating modes (PDC/VPS) are selected by a control register which can be written to via the I 2C-Bus interface. Pin Configuration (top view) P-DIP-14-3 P-DSO-20-1

Pin Definitions and Functions Pin No. P-DIP-14-3 Pin No. P-DSO-20-1 Symbol Function

1 VSS Ground (0 V)

1 VSSA Analog ground (0 V)

2 VSSD Digital ground (0 V)

3 N.C. Not connected 2 4 SCL Serial clock input of I2C-Bus. 3 5 SDA Serial data input of I2C-Bus. 4 6 CS0 Chip select input determining the I2C-Bus addresses: 20H / 21H , when pulled low 22H / 23H , when pulled high. 5 7 VCS Video Composite Sync output from sync slicer used for PLL based clock generation. 8 N.C. Not connected 6 9 DAVN Data available output active low, when PDC/VPS data is received. 7 10 EHB Output signaling the presence of the first field active high. 8 11 TI Test input; activates test mode when pulled high. connect to ground for operating mode. 9 12 PD1 Phase detector/charge pump output of data PLL (DAPLL). 13 N.C. Not connected 10 14 PD2/ VCO2 Connector of the loop filter for the SYSPLL. 11 15 VCO1 Input to the voltage controlled oscillator #1 of the DAPLL. 12 16 IREF Reference current input for the on-chip analog circuit. 13 17 CVBS Composite video signal input. 18 N.C. Not connected 14 VDD Positive supply voltage (+ 5 V nom.).

19 VDDD Positive supply voltage for the digital circuits

(+ 5 V nom.).

20 VDDA Positive supply voltage for the analog circuits

(+ 5 V nom.).

Referring to the functional block diagram of the PDC / VPS decoder, the composite video signal with negative going sync pulses is coupled to the pin CVBS through a capacitor which is used for clamping the bottom of the sync pulses to an internally fixed level. The signal is passed on to the slicer, an analogue circuitry separating the sync and the data parts of the CVBS signal, thus yielding the digital composite sync signal VCS and a digital data signal for further processing by comparing those signals to internally generated slicing levels. The output of the sync separator is forwarded, on one hand, to the output pin VCS, and on the other hand, to the clock generator and the Timing block. The VCS signal represents a key signal that is used for deriving a system clock signal by means of a PLL and all other timing signal. The output of the sync separator is forwarded, on one hand, to the output pin VCS, and on the other hand, to the clock generator and the Timing block. The VCS signal represents a key signal that is used for deriving a system clock signal by means of a PLL and all other timing signal. The data slicer separates the data signal from the CVBS signal by comparing the video voltage to an internally generated slicing level which is found by averaging the data signal during TV line no. 16 in the VPS mode or by averaging the data signal during the clock run-in period of the teletext lines during the data entry window (DEW) in PDC mode. The clock generator delivers the system clock needed for the basic timing as well as for the regeneration of the dataclock. It is based on two phase locked loops (PLL’s) all parts of which are integrated on chip with the exception of the loop filter components. Each of the PLL’s is composed of a voltage controlled relaxation oscillator (VCO), a phase/frequency detector (PFD), and a charge pump which converts the digital output signals of the PFD to an analogue current. That current is transformed to a control voltage for the VCO by the off-chip loop filter. The generated VCO frequencies are 10 MHz and 13.875 MHz for VPS mode and PDC mode, respectively. All signals necessary for the control of sync and data slicing as well as for the data acquisition are generated by the Timing block. Depending on the selected operating mode, either teletext lines carrying 8/30 packages or the dedicated TV line no. 16 are acquired. In PDC mode, only teletext rows 8/30 containing Broadcast Data Service Package (BDSP) information are acquired. The relevant bytes of 8/30 format 1 (8/30/1) and 8/30 format 2 (8/30/2) are extracted. The 8/30/1-bytes are stored in the acquisition register in a transparent way without any bit manipulation, whereas the Hamming coded bytes of packet 8/30/2 are Hamming-checked and bytes with one bit error are corrected. The storage of error free or corrected 8/30/2-data bytes in the transfer register to theI 2C-Bus is signalled by the DAVN output going low. In VPS mode, the extracted data bits of TV line no. 16 are checked for biphase errors. With no biphase errors encountered, the acquired bytes are stored in the transfer register to theI2C-Bus. That transfer is signalled by a H/L transition of the DAVN output, as well. In both operating modes data are updated when a new data line has been received, provided that the chip is not accessed via theI2C-Bus at the same time. A micro controller can read the stored bytes via theI2C-Bus interface at any time. However, one must be aware that the storage of new data from the acquisition interface is inhibited as long as the PDC decoder is being accessed via theI 2C-Bus.

The I2C-Bus interface implemented on the PDC decoder is a slave transmitter/receiver, i.e., both reading from and writing to the PDC / VPS decoder is possible. The clock line SCL is controlled only by the bus master usually being a micro controller, whereas the SDA line is controlled either by the master or by the slave. A data transfer can only be initiated by the bus master when the bus is free, i.e., both SDA and SCL lines are in a high state. As a general rule for theI 2C-Bus, the SDA line changes state only when the SCL line is low. The only exception to that rule are the Start Condition and the Stop Condition. Further Details are given below. The following abbreviations are used: START : Start Condition generated by master AS : Ackknowledge by slave AM : Ackknowledge by master NAM : No Ackknowledge by master STOP : Stop Condition generated by master Chip Address There are two pairs of chip addresses, which are selected by the CS0-input pin according to the following table: Write Mode For writing to the PDC decoder, the following format has to be used. Data Transfer (Write Mode) Step1: In order to start a data transfer the master generates a Start Condition on the bus by pulling the SDA line low while the SCL line is held high. Step 2: The bus master puts the chip address on the SDA line during the next eight SCL pulses. Step 3: The master releases the SDA line during the ninth clock pulse. Thus the slave can generate an acknowledge (AS) by pulling the SDA line to a low level. Step 4: The controller transmits the data byte to set the Control register. Step 5: The slave acknowledges the reception of the byte. Step 6: The master concludes the data communication by generating a Stop Condition. The write mode is used to set theI2C-Bus control register which determines the operating mode: CS0 Input Write Mode Read Mode Low 20 (hex) 21 (hex) High 22 (hex) 23 (hex) START Chipadress Write Mode AS Byte Set Control Register AS STOP

Default: All bits are set to 0 on power-up. Bits 3 through 7 are used for test purposes and must not be changed for normal operation by user software! Bit 0: Determines, which kind of data is accessed via theI2C-Bus when PDC mode is active. Bit 1: Determines the operating mode. Bit 2: Determines whether BDSP 8/30/1-data or header row data is accessible. Read Mode For reading from the PDC decoder, the following format has to be used. The contents of up to 13 registers (bytes) can be read starting with byte 1 bit 7 (refer to the table Order of Data Output on theI2C-Bus and … ) depending on the selected operating mode. Bit Number 76543210 T4 T3 T2 T1 T0 HDT PDC/ VPS FOR1/ FOR2 Value BDSP 8/ 30/ 2 data accessible BDSP 8/ 30/ 1 or header row data accessible (refer to description of Bit 2) Value VPS mode active PDC mode active Value BDSP 8/30/1 data accessible Bytes no.38 through 45 of the header row containing clock time accessible START Chipaddress Read Mode AS 1st Byte AM … Last Byte NAM STOP

Data Transfer (Read Mode) Step1: To start a data transfer the master generates a Start Condition on the bus by pulling the SDA line low while the SCL line is held high. The byte address counter in the decoder is reset and points to the first byte to be output. Step 2: The bus master puts the chip address on the SDA line during the next eight SCL pulses. Step 3: The master releases the SDA line during the ninth clock pulse. Thus the slave can generate an acknowledge (AS) by pulling the SDA line to a low level. At this moment, the slave switches to transmitting mode. Step 4: During the next eight clock pulses the slave puts the addressed data byte onto the SDA line. Step 5: The reception of the byte is acknowledged by the master device which, in turn, pulls down the SDA line during the next SCL clock pulse. By acknowledging a byte, the master prompts the slave to increment its internal address counter and to provide the output of the next data byte. Step 6: Steps no. 4 and no. 5 are repeated, until the desired amount of bytes have been read. Step 7: The last byte is output by the slave since it will not be acknowledged by the master. Step 8: To conclude the read operation, the master doesn’t acknowledge the last byte to be received. A No Acknowledge by the master (NAM) causes the slave to switch from transmitting to receiving mode. Note that the master can prematurely cease any reading operation by not acknowledging a byte. Step 9: The master gains control over the SDA line and concludes the data transfer by generating a Stop Condition on the bus, i. e., by producing a low/high transition on the SDA line while the SCL line is in a high state. With the SDA and the SCL lines being both in a high state, theI 2C-Bus is free and ready for another data transfer to be started.

Order of Data Output on theI2C-Bus and Bit Allocation of the 3 Different Operating Modes I2C-Bus PDC Packet 8/30 VPS Mode Format 1 Format 2 Byte 1 bit 7 byte 15 bit 0 byte 16 bit 0 byte 17 bit 0 byte 11 bit 0 Byte 2 bit 7 byte 16 bit 0 byte 18 bit 0 byte 19 bit 0 byte 12 bit 0 Byte 3 bit 7 byte 17 bit 0 byte 20 bit 0 byte 21 bit 0 byte 13 bit 0 Byte 4 bit 7 byte 18 bit 0 byte 22 bit 0 byte 23 bit 0 byte 14 bit 0 t 1) Message bit numbers according to EBU specification of PDC system. 2) Transmission bit number

Order of Data Output on theI2C-Bus and Bit Allocation of the 3 Different Operating Modes (cont’d) I2C-Bus PDC Packet 8/30 VPS Mode Format 1 Format 2 Byte 5 bit 7 byte 19 bit 0 byte 14 bit 0 byte 15 bit 0 byte 5 bit 0 Byte 6 bit 7 byte 20 bit 0 byte 24 bit 0 byte 25 bit 0 byte 15 bit 0 Byte 7 bit 7 byte 21 bit 0 byte 13 bit 0 – set to “1” – set to “1” – set to “1” – set to “1” – set to “1” – set to “1” – set to “1” – set to “1” – set to “1” – set to “1” – set to “1” – set to “1” Byte 8 bit7 byte 13 bit 0 Byte 9 bit7 byte 14 bit 0

I 2C-Bus PDC Packet 8/30 VPS Mode Format 1 Format 2

Order of Data Output on theI2C-Bus and Bit Allocation for the Header Time Mode I2C-Bus Header Time Mode Byte 1 bit 7 byte 38 bit 0 Byte 2 bit 7 byte 39 bit 0 Byte 3 bit 7 byte 40 bit 0 Byte 4 bit 7 byte 41 bit 0 t 1) Message bit numbers according to EBU specification of PDC system. 2) Transmission bit number.

Order of Data Output on theI2C-Bus and Bit Allocation for the Header Time Mode (cont’d) I2C-Bus Header Time Mode Byte 5 bit 7 byte 42 bit 0 Byte 6 bit 7 byte 43 bit 0 Byte 7 bit 7 byte 44 bit 0 Byte 8 bit 7 byte 45 bit 0 t 1) Message bit numbers according to EBU specification of PDC system. 2) Transmission bit number

Description of DAVN and EHB Outputs DAVN (Data Valid active low) EHB (First Field active high) In test mode (i.e. TI = high), both DAVN and EHB are controlled by the CS0 pin and reproduce the state of the CS0 input. Signal Output VPS Mode PDC Mode 8/30/2 Mode 8/30/1 Mode Header Time DAVN H/L-transition (set low) in line 16 when valid VPS data is received in the line carrying valid 8/30/2 data in the line carrying valid 8/30/1 data in the line carrying valid header row X/0 data L/H-transition (set high) at the start of line 16 at the beginning of the next field i.e.,at the start of the next data entry window always set high on power-up or duringI 2C-Bus accesses when the bus master doesn’t acknowledge in order to generate the stop condition EHB L/H-transition at the beginning of the first field H/L-transition at the beginning of the second field

Electrical Characteristics

TA = 25°C Parameter Symbol Limit Values Unit Test Conditionmin. typ. max. Ambient temperature TA 07 0 °C in operation Storage temperature Tstg – 40 125 °C by storage Total power dissipation Ptot 300 mW Power dissipation per outputPDQ 10 mW Input voltage VIM – 0.3 6 V Supply voltage VDD – 0.3 6 V Thermal resistance Rth SU 80 K/W Operating Range Supply voltage VDD 4.5 5 5.5 V Supply current IDD 51 5 m A Ambient temperature rangeTA 07 0 °C Characteristics TA = 25°C Parameter Symbol Limit Values Unit Test Conditionmin. typ. max. Input Signals SDA, SCL, CS0 H-input voltage VIH 0.7× VDD VDD V L-input voltage VIL 0 0.3 × VDD V Input capacitance C I 10 pF Input current IIM 10 µA Input Signal TI H-input voltage VIH 0.9× VDD VDD V L-input voltage VIL 0 0.1 × VDD V Input capacitance C I 10 pF Input current IIM 10 µA

(pos. Video, neg. Sync) Video input signal level VCVBS 0.7 1.0 2.0 V Synchron signal amplitudeVSYNC 0.15 0.3 1.0 V Data amplitude VDAT 0.25 0.5 1.0 V Coupling capacitor C C 33 nF H-input current IIH 10 µA VI =5V L-input current IIL – 1000 – 400 – 100 µA VI =0V Source impedance RS 250 Ω Leakage resistance at coupling capacitor RC 0.91 1 1.2 M Ω Output Signals DAVN, EHB, VCS H-output voltage VQH VDD – 0.5 V IQ = – 100µA L-output voltage VQL 0.4 V IQ = 1.6 mA Output Signals SDA (Open-Drain-Stage) L-output voltage VQL 0.4 V IQ = 3.0 mA Permissible output voltage 5.5 V PLL-Loop Filter Components (see application circuit) Resistance at PD2/VCO2 R1 6.8 k Ω Resistance at VCO1 R2 1200 k Ω Attenuation resistance R3 6.8 k Ω Resistance at PD2/VCO2 R5 1200 k Ω Integration capacitor C 1 2.2 nF Integration capacitor C 3 33 nF VCO – Frequence Range Adjustment Resistance at IREF (for bias current adjustment) R4 100 k Ω Characteristics (cont’d) TA = 25°C Parameter Symbol Limit Values Unit Test Conditionmin. typ. max.

All values referred toVIH andVIL levels. Parameter Symbol Limit Values Unit min. max. Clock frequency fSCL 0 100 kHz Inactive time prior to new transmission start-uptBUF 4.7 µs Hold time during start condition tHD;STA 4.0 µs Low-period of clock tLOW 4.7 µs High-period of clock tHIGH 4.0 µs Set-up time for data tSU;DAT 250 ns Rise time for SDA and SCL signal tTLH 1 µs Fall time for SDA and SCL signal tTHL 300 ns Set-up time for SCL clock during stop conditiontSU;STO 4.7 µs

I2C-Bus Signals During Write Operations

I2C-Bus Signals During Read Operations

Position of Teletext and VPS Data Lines within the Vertical Blanking Interval (shown for first field) Definition of Voltage Levels for VPS Data Line

BDSP 8/30 Format 1 Bit Allocation This corresponds to the coding adopted in CCIR teletext system B BDSP 8/30 format 1. NB: The received bytes are output on theI2C-Bus in a transparent way, i.e., on a bit-first-in-first-out basis. No bit manipulation is performed on the chip in this operating mode. Concerning bytes no. 16 through 21: When evaluating the numbers, note that each 4-bit-digit has been incremented by one prior to transmission, and the least significant bits are transmitted first. Byte No. Bit No. Contents 01234567 13 Network Identification 1. Byte 14 Network Identification 2. Byte

15 Weight Weight Sign Time Offset Code

–2 2 –1 2 0 21 22 23 0

16 MJD Digit

1111 Modified Julian Date (MJD)

1. Byte

17 MJD Digit

1. Byte

18 MJD Digit

Modified Julian Date (MJD) 3. Byte

19 UTC Hours

Universal Time Coordinated (UTC) 1. Byte

20 UTC Minutes

Universal Time Coordinated 2. Byte

21 UTC Seconds

Universal Time Coordinated 3. Byte 22 Short Program Label 1. Byte 23 Short Program Label 2. Byte 24 Short Program Label 3. Byte 25 Short Program Label 4. Byte

Structure of the Teletext Data Packet 8/30 Format 2

BDSP 8/30 Format 2 Bit Allocation The four message bits of byte 13 are used as follows: byte 13 bit 0 – LCI b 1 ) label channel identifier 1 – LCI b2 ) 2 – LUF label update flag 3 – reserved but as yet undefined The message bits of bytes 14 – 25 are used in a way similar to the coding of the label in the dedicated television line as follows: byte 14 bit 0 PCS b 1 ) status of byte 20 bit 0 PIL b 15 )

1 PCS b 2 ) analogue sound 1 PIL b 16 )

2 PIL b 17 ) minute

2 ) reserved but yet 3 PIL b 18 ) 3 ) undefined byte 21 bit 0 PIL b 19 )

1 PIL b 20 )

byte 15 bit 0 CNI b1 )

1 CNI b 2 ) country 2 CNI b 5 )

2 CNI b 3 ) 3 CNI b 6 ) country

3 CNI b 4 ) byte 22 bit 0 CNI b 7 )

1 CNI b 8 )

byte 16 bit 0 CNI b9 ) network (or

1 CNI b 10 ) program provider) 2 CNI b 11 )

3 CNI b 12 )

2 PIL b 1 ) byte 23 bit 0 CNI b 13 ) network (or

3 PIL b 2 ) 1 CNI b 14 ) program

byte 17 bit 0 PIL b3 ) day 2 CNI b 15 ) provider)

1 PIL b 4 ) 3 CNI b 16 )

2 PIL b 5 )

byte 24 bit 0 PTY b1 )

3 PIL b 6 ) 1 PTY b 2 )

byte 18 bit 0 PIL b7 ) month 2 PTY b 3 )

1 PIL b 8 ) 3 PTY b 4 ) program

2 PIL b 9 ) byte 25 bit 0 PTY b 5 ) type

1 PTY b 6 )

3 PIL b 10 ) 2 PTY b 7 )

byte 19 bit 0 PIL b11 ) 3 PTY b 8 )

1 PIL b 12 ) hour

2 PIL b 13 )

3 PIL b 14 )

Data Format of the Program Delivery Data in the Dedicated TV Line Time Parameter→ PCS CNI CNI PIL CNI PTY Byte No.→ 1 2 3 & 4 5 6 to 10 11 12 13 14 15 Parameter bits bi, I =→ 12341234 91 01 2 3 4 5 6 7 8 91 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 05 6 7 81 1 1 2 1 3 1 4 1 5 1 61 2 3 4 5 6 7 8 Transmission bit No.→ 01234567 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 Bits b1 and b2: 00 don’t know 01 mono 10 stereo 11 dual sound Bits b 3 and b4 are reserved M L ML M L ML M L M L M L M L Content→ Clock run-in Start code Not relevant to PDC Reserved for enhancement of VPS Not relevant to PDC Net. or prog. prov. bin. Day binary Month binary Hour binary Minute binary Country binary Network or program provider binary Program type binary Reserved code values for receiver control (service codes) Timer control code Abbreviations:CNI = Country and Network Identification PCS = Program Control Status PIL = Program Identification Label PTY = Program Type M = Most-significant bit L = Least-significant bit A = Bit value is that of the current PTY code N = Bit value is that of the current CNI code P = Bit value is that of the current PIL code 