SDA5273C-2CP

SDA5275P SIEMENS | Alldatasheet

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ICs for Consumer Electronics MEGATEXT and MEGATEXT PLUS ICs SDA 5273 / SDA 5275 SDA 5273-2 / SDA 5275-2

Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. Characteristics The listed characteristics are ensured over the operating range of the integrated circuit. Typical characteristics specify mean values expected over the production spread. If not otherwise specified, typical characteristics apply at T A = 25 C and the given supply voltage. Operating Range In the operating range the functions given in the circuit description are fulfilled. For detailed technical information about “Processing Guidelines” and “Quality Assurance” for ICs, see our “Short Form Catalog”. MEGATEXT â and MEGATEXT PLUS ICs SDA 5273 / SDA 5275 SDA 5273-2 / SDA 5275-2 Revision History: 1997-09-01 Previous Releases: 11.96 Page Subjects (changes since last revision)

20 Now also covers SDA 5275-2 and SDA 5273-2 versions;

Reset/chip initialization update Published by Siemens AG, Bereich Halbleiter, Marketing-Kommunikation, Balanstraße 73, 81541 München © Siemens AG 1997. All Rights Reserved. As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Ger- many or the Siemens Companies and Representatives worldwide (see address list). Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Siemens Office, Semiconductor Group. Siemens AG is an approved CECC manufacturer. Packing Please use the recycling operators known to you. We can also help you - get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. Edition 1997-09-01

Semiconductor Group 3 1997-09-01 Contents Page

1 Features

2 Electrical Characteristics

3 Diagrams

4 Package Outlines

Ò is a registered trademark of Siemens AG

Ò and MEGATEXT PLUS ICs Preliminary Data CMOS IC SDA 5273 / 75 SDA 5273-2 / 75-2 P-LCC-68-1 P-SDIP-52-1 l Single chip teletext IC l Analog CVBS-input with onchip clamping circuitry l Slicer l Supports level 1, 2.5 and 3.5 ETSI teletext standard l Stores up to 14 teletext pages on chip l Stores up to 2048 teletext pages with external

16 M memory

l SDA 5275: full level 2.5 processing l Analog RGB-output l 41 latin script languages l 10 character size l Parallel display attributes l 64 from 4096 colors selectable l Enhanced flash modes l Dynamically redefinable character set (DRCS, PCS) l Pixel graphics l Fullscreen display (64 32 or 80 24 character positions) l Horizontal and vertical scrolling l Graphic cursors l 4:3 and 16:9 display l Multinorm display (50/60/100/120 Hz) l RISC-processor l Firmware downloadable l I C / 3 wire UART-interface (1 Mbit/s) l Independent clocks for acquisition and display l Tools for greatly simplified software development l 24-Kbyte on-chip reconfigurable DRAM l 44160-bit character ROM l One external crystal for all standards Type Ordering Code Package SDA 5273 / 75 P on request P-LCC-68-1 SDA 5273 / 75 S on request P-SDIP-52-1 SDA 5273-2 / 75-2P on request P-LCC-68-1 SDA 5273-2 / 75-2S on request P-SDIP-52-1 SDA 5273C / 73-2C P on request P-LCC-68-1 SDA 5273C / 73-2C S on request P-SDIP-52-1 Semiconductor Group 4 1997-09-01

Semiconductor Group 5 1997-09-01 Pin Configuration (top view) UEP04657 V DD TM GPO OUT HS VS/VCS I CVBS I SDA SCL CORQ BLAN B G R RGB-GND CASQ 260 11A 10A OICLK- TCSQ/FLD XIN X NTQ CEN 1SSV WEQ RASQ V SSA 2 V SS2 V BB V SS3 V SS4 A ADDV 1SSAV 2DDV 3DDV REFV 4DDV RES /N.C. P-SDIP-52-1

Semiconductor Group 6 1997-09-01

1.1 Pin Definitions and Functions

Pin No. P-SDIP-52-1 Symbol Function

1 CLK-IO System clock input/output

2 TCSQ/FLD Composite sync output/ field output

3 VS/VCS Vertical sync input/output

4 HS Horizontal sync input/output

5 XOUT 20.5-MHz crystal oscillator output 6 XIN 20.5-MHz crystal oscillator input

7 GPO General purpose output

8 TM Testpin, leave open or connect to

V SS

9 CVBS CVBS-video signal input

V DD1 + 5 V digital supply V DDA + 5 V analog supply V SSA1 Analog ground V DD2 + 5 V digital supply

14 RES Chip reset

V DD3 + 5 V digital supply V REF + 3 V reference voltage input V DD4 + 5 V digital supply

18 A8 External DRAM-address

19 A7 External DRAM-address

20 A6 External DRAM-address

21 A5 External DRAM-address

22 A4 External DRAM-address

23 A3 External DRAM-address

24 A2 External DRAM-address

25 A1 External DRAM-address

26 A0 External DRAM-address

27 A9 External DRAM-address

28 A10 External DRAM-address

29 A11 External DRAM-address

30 RASQ Row address strobe (DRAM)

31 WEQ Write enable (DRAM)

32 D1 External DRAM-data

Semiconductor Group 7 1997-09-01 (cont’d) Depends on version. Please refer to the respective Delta Specification. Pin No. P-SDIP-52-1 Symbol Function

33 D0 External DRAM-data

34 D2 External DRAM-data

35 D3 External DRAM-data

V SS4

0 V digital supply

37 CASQ Column address strobe

V SS3 V BB Substrate bias voltage N.C. V SS2 V SSA2 Analog ground

42 RGB-GND RGB-ground

V SS1

44 R Analog red display output

45 G Analog green display output

46 B Analog blue display output

47 BLAN Blanking signal open drain output

48 CORQ Contrast reduction open drain output

49 SCL

I C Bus clock port

50 SDA Bidirectional

I C Bus data port 51 I CEN I 2C Bus enable 52 INTQ Interrupt request output to ext. controller

Semiconductor Group 8 1997-09-01 Pin Configuration (top view) UEP05514 27A7 A10 A11 RASQ WEQ 42 43 6162636465666768123456789 CVBS GPO XOUT VS/VCS I SDA CORQ BLAN B CASQ N.C. N.C. V N.C. N.C. RES N.C. N.C. N.C. N.C. G V

2 CEN

V SS1 SS3 SS4 HS R SCL TM XIN TCSQ/FLD CLK-IO INTQ RGB-GND SSA2V BB SS2 V V V DD1 SSA1V VDD2 N.C. 23REFV /N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. P-LCC-68-1

Semiconductor Group 9 1997-09-01

1.2 Pin Definitions and Functions

Pin No. P-LCC-68-1 Symbol Function 1 INTQ Interrupt request output to ext. controller

2 CLK-IO System clock input/output

3 TCSQ/FLD Composite sync output/ field output

4 VS/VCS Vertical sync input/output

5 HS Horizontal sync input/output

6 XOUT 20.5-MHz crystal oscillator output 7 XIN 20.5-MHz crystal oscillator input

8 GPO General purpose output

9 TM Testpin, leave open or connect

10 CVBS CVBS-video signal input

12 VDDA + 5 V analog supply

13 VSSA1 Analog ground

14 N.C. Not connected 15 N.C. Not connected VDD2 + 5 V digital supply

17 RES Chip reset

18 N.C. Not connected 19 N.C. Not connected 20 N.C. Not connected VDD3 + 5 V digital supply 22 N.C. Not connected VREF + 3 V reference voltage input 24 N.C. Not connected VDD4 + 5 V digital supply

26 A8 External DRAM-address

27 A7 External DRAM-address

28 A6 External DRAM-address

29 A5 External DRAM-address

30 A4 External DRAM-address

31 A3 External DRAM-address

32 A2 External DRAM-address

Semiconductor Group 10 1997-09-01

1.2 Pin Definitions and Functions (cont’d)

1) Depends on version. Please refer to the respective Delta Specification. Pin No. P-LCC-68-1 Symbol Function

33 A1 External DRAM-address

34 A0 External DRAM-address

35 A9 External DRAM-address

36 A10 External DRAM-address

37 A11 External DRAM-address

38 RASQ Row address strobe (DRAM)

39 WEQ Write enable (DRAM)

40 D1 External DRAM-data

41 D0 External DRAM-data

42 D2 External DRAM-data

43 D3 External DRAM-data

45 CASQ Column address strobe

46 N.C. Not connected 47 N.C. Not connected 48 N.C. Not connected VSS3 0 V digital supply 50 N.C. Not connected 51 N.C. Not connected 52 N.C. Not connected 53 N.C. Not connected 54 N.C. Not connected VSS2 0 V digital supply 56 VBB Substrate bias voltage N.C.1) 57 N.C. Not connected VSSA2 Analog ground

59 RGB-GND RGB-ground

61 R Analog red display output

62 G Analog green display output

63 B Analog blue display output

Semiconductor Group 11 1997-09-01 Pin No. P-LCC-68-1 Symbol Function

64 BLAN Blanking signal open drain output

65 CORQ Contrast reduction open drain output

66 SCL Bidirectional

67 SDA Bidirectional I2C Bus data port

68 I 2CEN I2C Bus enable

Semiconductor Group 12 1997-09-01 Parameter Symbol Limit Values Unit Test Condition min. typ. max. Supply voltage VDD 0 6.0 V Ambient temperature TA 07 0 °C Storage temperature Tstg – 20 125 °C Power consumption Ptot 1.8 W Electrostatic discharge 2000 V 100 pF, 1 k W HBM according to MIL-standard 883 method 3015.7 Characteristics TA = 0 to 70 °C Parameter Symbol Limit Values Unit Test Condition min. typ. max. Supply Voltages VDDD 4.7 5.0 5.3 V VDDA 4.7 5.0 5.3 V VDDD = VDDA ! Supply Currents IDDD 200 mA 20 pF load per pin IDDA 60 mA Inputs Tristate of Outputs: I2CEN, HS, VS, GPO, RES, D0-D3 H-input voltage VIH 2.0 VDDD V L-input voltage VIL – 1.0 0.8 V Input capacitance C I 7p F Input leakage current IL 10 mA VIH = 5.5 V Input current RES IIH 100 mA VIH = 5.5 V

Semiconductor Group 13 1997-09-01 Characteristics (cont‘d) TA = 0 to 70 °C Parameter Symbol Limit Values Unit Test Condition min. typ. max. Outputs TTL-Outputs: A0-A11, D0-D3, RASQ, CASQ, WEQ, HS, VS, GPO, INTQ, TCSQ H-output voltage VOH 2.4 VDDD V– IOH = 0.2 mA L-output voltage VOL 0 0.4 V IOL = 1.6 mA Load capacitance C L 50 pF Transition period tr, tf 15 ns Open Drain Outputs: BLAN, CORQ Sink current IOL 5 mA low level output L-output voltage VOL 0.4 V IOL = 2 mA H-output voltage VOH VDDD V BLAN = 1: display MEGATEXT RGB-outputs BLAN = 0; display other source CORQ= 1; switch contrast reduction OFF CORQ= 0; switch contrast reduction ON Sourcefollower Output: CVBS at pin TCSQ DC-offset to CVBS-input 1.2 V Gain G 0.9 Output current IO 0.9 mA CVBS = 1 V, TCSQ = 0 V Output impedance RO 200 W CVBS = 1 V Edge response tr 1 ms 10 to 90 %, 1 Vpp, C L = 50 pF Sync Timing: HS, VS, TCSQ Sync Output Waveforms Pulse width HS tWH 2 ms Pulse width VS tWH 1 line VCS-waveform see diagram 6a, b TCSQ-waveform see diagram 6a, b

Semiconductor Group 14 1997-09-01 Characteristics (cont’d) TA = 0 to 70 °C Parameter Symbol Limit Values Unit Test Condition min. typ. max. Output Timing: HS, VS, TCSQ Hold and delay time with respect to 24-MHz system clock output: Delay time tOD 20 ns see diagram 2 Hold time tOH 0n s see diagram 2 Hold and delay time with respect to 24-MHz external system clock input: Delay time not specified Hold time not specified Input Timing: HS, VS No synchronous input mode specified! Clock Input/Output (see diagram 1) Clock Input H-input voltage VIH 2.0 VDDD V L-input voltage VIL – 1.0 0.8 V Input capacitance C I 7p F Input leakage current Il 10 mA VIH = 5.5 V Period T c 40 24-MHz clock Tc 35 27-MHz clock Transition time tCR , tCL 3n s Symmetry ratio tCH /tC 0.43 0.57 Clock Output H-output voltage VOH 2.4 VDDD V– IOH = 0.2 mA L-output voltage VOL 0 0.4 V IOL = 1.6 mA Load capacitance C L 50 pF Period T C 41.7 ns 20.5-MHz crystal Transition time tCR , tCF 5n s Symmetry ratio tCH /tC 0.3 0.5 ns

Semiconductor Group 15 1997-09-01 Characteristics (cont’d) For modes with external clock MEGATEXT may only be operated in freerun mode as sync master. HS may not be used as an input in these cases. The RGB-output voltage is proportional to VREF . TA = 0 to 70 °C Parameter Symbol Limit Values Unit Test Condition min. typ. max. RGB-Outputs VREF = 3 V no resistive load RGB-GND = 0 V Pin capacitance C P 7V Output voltage range 0 2.2 V RGB-amplitude 1.1 1.25 1.55 V R83: RGB-GAIN (4:0) = 1F H DC-offset voltage 0.7 0.8 1.0 V R83: RGB-LEVL (2:0) = 7 Clamp level 0 V DAC-resolution 4 bit Diff. non-linearity – 0.5 0.5 LSB R83: RGB-GAIN (4:0) = 1F H RGB-LEVL (2:0) = 0 Int. non-linearity – 0.5 0.5 LSB Output tracking – 0.5 0.5 LSB Output resistance RO 270 W 3-dB bandwidth 10 MHz C L = 50 pF Bus Connection: SDA, SCL, I2CEN (see diagram 4) Inputs: SDA, SCL H-input voltage VIH 3.0 VDDD V L-input voltage VIL – 1.0 1.5 V Input capacitance C I 7p F Input leakage current IL 10 mA VIH = 5.5 V VDD = 0 V … 5.5 V 2P R O C L

Semiconductor Group 16 1997-09-01 Characteristics (cont’d) TA = 0 to 70 °C Parameter Symbol Limit Values Unit Test Condition min. typ. max. Open Drain Outputs: SDA, SCL L-output voltage VOL 0 0.4 V IOL = 3 mA Sink current IOL 10 mA I2C-Mode Timing MEGATEXT is an I2C-slave transmitter/receiver. The Siemens I2C Bus specification applies. SCL-frequency fSCL 0 100 kHz I2CEN = high Transition time tr, tf 2 ms Bus capacitance C BUS 400 pF Bus free before start tBUF 4.7 ms Hold time start tHSTA 4.0 ms L-time clock tLOW 4.0 ms H-time clock tHIGH 4.0 ms Set-up time start tSUSTA 4.0 ms Hold time SDA tHDDAT 0 ms Set-up time SDA tSUDAT 250 ns Set-up time SDA at stop tSUSTO 4.0 ms Output fall time tFO 0.2 ms 3 V to 1 V M3L-Mode Timing The MEGATEXT M3L-Bus is specified in accordance with the standard USART-interface of micro controller SDA 30C162. SCL-frequency fSCL 0 1.0 MHz 20.48-MHz crystal L-time clock tL 400 ns H-time clock tH 400 ns SCL-load capacitance C SCL 200 pF Set-up time SDA-input to SCL-falling edge tDSL 100 ns Hold time SDA-input from SCL-falling edge tDHH 400 ns

Semiconductor Group 17 1997-09-01 Characteristics (cont’d) TA = 0 to 70 °C Parameter Symbol Limit Values Unit Test Condition min. typ. max. M3L-Mode Timing (cont’d) Set-up time SDA to I2CEN- rising edge tIM 400 ns Set up time I2CEN to SDA- falling edge tIS 400 ns I2CEN-high time tIH 1000 ns Delay from SCL-falling edge until SDA-open drain output stage changes impedance tDO 400 600 ns L-SDA level output impedance 100 W The resulting delay of SDA-output data is the sum of the open drain stage plus the time determined by the bus capacitance and the external pullup resistor or the impedance of the internal open drain pulldown transistor respectively. Wait condition I2CEN = 0 To force the M3L-master to interrupt the transmission sequence until MEGATEXT is ready for more data, MEGATEXT can force down SCL after the transmission of a complete byte. At that time the bus master has to switch its SCL-output to high impedance and check the state of SCL afterwards.During SCL check I2CEN has to be low. Delay from SCL-rising edge to SCL forced low for WAIT- condition tDWAIT 500 750 ns An internal pullup transistor restores SCL high level at the end of the WAIT-condition. SCL-pullup time at the end of WAIT tRWAIT 70 100 ns Reference Voltage: V REF Voltage level VREF 2.8 3.0 3.5 V Input leakage current Il – 10 10 mA VREF = 3 V VREF influences the DAC-range, the CVBS-output at pin TCSQ and the CVBS-ADC range.

Semiconductor Group 18 1997-09-01 Characteristics (cont’d) The center frequency of the MEGATEXT horizontal PLL is proportional to the crystal frequency. In PAL-mode the centre frequency is 15.625 kHz for the typical crystal frequency of 20.48 MHz. Deviations from the typical crystal frequency will shift the range of the horizontal frequencies where the PLL is able to lock. TA = 0 to 70 °C Parameter Symbol Limit Values Unit Test Condition min. typ. max. CVBS-Input and ADC (V REF = 3 V) Input leakage current Il – 1.0 1.0 mA CVBS = 2 V Input capacitance C P 45 pF Ext. coupling capacitanceC CPL 100 nF Sensitivity of clamp level to current leakage/injection – 15 15 mV/ mA Il = 2 mA C CPL = 100 nF ADC-range 1.7 2.0 V VREF = 3 V CVBS-sync amplitude 0.1 V Crystal Oscillator: XIN, XOUT Bias resistance between XIN, XOUT RXbias 60 120 180 k W Small signal voltage gainG V 8 13 100 kHz, 50 mVpp Feedback capacitance C FB 4.0 pF Pin capacitance C P 7.0 pF Crystal Nominal frequency fO 20.48 MHz Effect of temperature and accuracy of adjustment df/fO – 5 % + 5 % Temperature range TA 07 0 °C Resonant impedance ZR 40 W Equivalent parallel CC L 15 pF Crystal load 0.1 mW Ext. capacitors C 1,2 15 pF

Semiconductor Group 19 1997-09-01 Characteristics (cont’d) TA = 0 to 70 °C Parameter Symbol Limit Values Unit Test Condition min. typ. max. DRAM-Interface (see diagram 5) The external DRAM is operated in page mode. The timing of the DRAM-interface signals are specified below. Cycle time tWC 420 500 550 ns Address hold time from RAStRAH 25 ns Address hold time from CAStCAH 60 ns Address set-up time from RAS tASR 5n s Address set-up time from CAS tASC 5n s L-time RAS tRASP 280 ns L-time CAS tCASL 70 ns H-time RAS tRP 140 ns H-time CAS tCP 70 ns Refresh period 20 ms Write Cycle L-time WE tWEL 210 ns Data set-up time to CAS tDS 100 ns WE set-up time to CAS tRCS 0n s Data hold time from CAS tDH 55 ns Data hold time from WE tOHZ 10 ns Read Cycle H-time WE (output enable)tOEL 210 ns Access time from CAS tCAC 60 ns Data hold time of DRAM tOFF 40 ns

Semiconductor Group 20 1997-09-01 Characteristics (cont’d) TA = 0 to 70 °C Parameter Symbol Limit Values Unit Test Condition min. typ. max. Reset/Chip Initialization A power-on reset or a reset pulse at pin RES lead to a hardware reset and a software initialization of registers and internal DRAM. During initialization bus transfers are not allowed. At / after power-on a reset pulse at pin RES is necessary. RES may return to 0 after the supply voltage reached its lower limit for chip function (4.7 V). This may be achieved by a capacitor C between RES and VDD and by a resistor R between RES and VSS . The dimensions of R and C depend on the worst case rise time of VDD . Initialization time after power- on or falling edge of RES tINIT 25 ms VDD greater 4.7 V If the supply voltage drops below VDD min, the IC has to be reset by pin RES. Pulse width RES 100 ns High level at pin RES causes chip reset. In rare cases, the IC may remain in a permanent reset state after power up, depending on the applicational context. After power up, the software should check proper operation. In case the Megatext does not react properly, power supply should be switched off for at least 3 s. After that, power supply can be switched on again. Other Items Horizontal frequency pull-in range of CVBS-PLL: 15 15.625 16.2 kHz PAL

20.48 MHz crystal

15.2 15.748 16.3 kHz NTSC Horizontal frequency pull-in range of display-PLL: 15 15.625 16.2 kHz

Semiconductor Group 21 1997-09-01 2.0 V 1.5 V 0.8 V UET04662 ODt 2.4 V 1.5 V 0.8 V 2.4 V 0.8 V VS HS tOH OH t tOD Wt CLK_OUT

Semiconductor Group 22 1997-09-01 Timing Diagram 3a I2C-Bus Mode UET04815 SCL SDA CENI2 tBUF tHIGH tLOWft V IL IHV V IL IH V V IL IH V BUFt tSUSTA SUDATt tHDDAT SUSTOt

Semiconductor Group 23 1997-09-01 Timing Diagram 3b M3L-Bus Mode UET04816 SCL ISt SDA CENI2 SCL Wait Condition tBUF tHIGH tLOWftt r tIM DSt DHHtt DHH DSLt tDO WAIT tDWAIT RWAITt V IH ILV V OL OLV V IL IHV V IL IH V V IL IH V BUFt

Semiconductor Group 24 1997-09-01 Timing Diagram 4a DRAM-Page Mode Write Cycle Data from SDA 527x Column Address t RASQ CASQ tCP ASRt ASCt tCASL D0... WEQ A11 A0... Row Address tRP t WEt RAH DSt t RASP CAH t CP CASLt UET04663 OHZ Column Address DHt WELt WCt Data from SDA 527x DSt tDH t

Semiconductor Group 25 1997-09-01 Timing Diagram 4b DRAM-Page Mode Read Cycle Data from RAM Column Address CAH RAH CASQ RASQ t t ASB CP ASCt tCASL t WEQ D0... A11 A0... Row Address tRP t OEt tCAC t RASPt CP CASLt UET04664 Column Address t tOFF OEL RCt Data from RAM CACt tOFF

Semiconductor Group 26 1997-09-01 Timing Diagram 5a VCS and TCS in PAL Freerun Mode UED04865 04 . 7 0 2.35 32 34.35 27.3 32 59.3 64 t[m s] ]sm[t ]sm[t 622 623 624 625 1 2 3 4 5 6 310 311 312 313 314 315 316 317 318 319 123 456 (6)(5)(4)(3)(2)(1) 309 310 311 312 1 2 3 4 5 6 VCS VCS TCS TCS TCS Interlaced Interlaced Non- Interlaced -312/312 Lines -313/312 Lines -626/624 Lines Main Pulse Equalizing Pulse Line Sync Pulse Timing with Tolerances 100 ns 654321625624623622 319318317316315314313312311310

Semiconductor Group 27 1997-09-01 Timing Diagram 5b VCS and TCS in NTSC Freerun Mode Interlaced Interlaced Non- Interlaced -262/262 Lines -263/262 Lines -526/524 Lines TCS TCS TCS VCS VCS 0 4.7 63.6 63.631.827.10 34.12.3 63.60 Main Pulse Equalizing Pulse Line Sync Pulse UED04872 58.9 31.8 522 (259) 523 (260) 524 (261) 525 (262) 1 2 3 4 5 6 t[ s] t[ s] t[ s] 260 261 262 263 264 (1) 265 (2) 266 (3) 267 (4) 268 (5) 269 (6) 259 (260) (521) (523) 260 (261) (522) (524) 261 (262) (523) (525) 262 (263) (524) (526) (1) (2) (3) (4) (5) (6) 522 (259) 523 (260) 524 (261) 525 (262) 1 2 3 4 5 6 260 261 262 263 264 (1) 265 (2) 266 (3) 267 (4) 268 (5) 269 (6) m m m

Semiconductor Group 28 1997-09-01 Application Circuit UES04659 RASQ WEQ CVBS GPO XOUT VS I SDA SCL CORQ BLAN B V RESET G V V V SS1 SSA2 SS4 SDA 527x nF 220 V DD ZD 220 nF nF100 DDV V SS 4.7 kW W150 150 W Wk 4.7 V DD Blank Reduction DDV 22 pF HS HS INTQ SCL G B TTL VS TTL CVBS CEN2I 270 W

1.15 Vpp

W Ref.

2 Vpp

20.48 MHz

R TCSQ TTL RSDA Contrast Wk 100 RGB-GND BBV SS2V N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. CASQ DRAM A10 A11 DD4 V DD1 V DDA V SSA1 V DD2 V DD3 V REF N.C. N.C. N.C. N.C. N.C. N.C. N.C. kW 220 Fn SS3V 22 pF

Semiconductor Group 29 1997-09-01 0.81 max1.27 0.43 ±0.1 0.18M 68xDA-B 20.32 0.1 5.08 max 3.5 ±0.2 0.5 min 0.2 1.2 x 45˚ 23.3 ±0.3 24.21 ±0.07 25.28 -0.26

0.38 M DA-B 34x

D 1680.5 x 45˚ 3 x 24.21 ±0.071) 25.28 -0.26 1.1 x 45˚ Index Marking 1) Does not include plastic or metal protrusions of 0.15 max per side P-LCC-68-1 (SMD) (Plastic Leaded Chip Carrier) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. Dimensions in mmSMD = Surface Mounted Device

Semiconductor Group 30 1997-09-01 46.1 0.25 14.02 15.24 1.78 0.46 52 27 12 6 1.3 max 0.5 min 3.43 4.83 max -0.3 ±0.25 -0.4 ±0.05 ±0.1 0.25 max +1.7 Index Marking +0.715.24 M0.25 52x Plastic Package, P-SDIP-52-1 (Plastic Dual In-Line Package) GPD05262 Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. Dimensions in mmSMD = Surface Mounted Device