SDA5231-2 SIEMENS | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 18
Technical content
Features
@ Crystal-stable data clock regeneration for a bit fate of 6.9375 MHz Oo @ Separation and regeneration of teletext infor- we mation So et) @ Separation of the horizontal and vertical syn- ISS <9 1) wn} chronization signals ri | ye” © Phase-locked coupling of 6-MHz oscillator ft with comp. video Py ‘VPD os0s7 ®@ Optional adjustment to 1 V or 2.5 V comp. vid- | P-DIP-28 © Processing of externally separated teletext data | © Output of negative and positive synchronous ! signals to television set | Type Ordering Code Package SDA 5231-2 Q 67000-A5006 P-DIP-28 : The SDA 5231-2 has been designed to separate teletext signals from TV signals for a | microcontroller-operated 12C bus concept. The video processor meets the requirements | for teletext data clock regeneration and synchronization of the TV set during teletext ' operation. At the same time, the video signals (CVBS) provided by the television set are ' evaluated for the teletext decoder. | Functional Description i The SDA 5231-2 is used in an I?C bus controlled teletext system. Its function is the \\ processing of the teletext informations, the system clock generation and the switching of HV synchronization signals. The SDA 5231-2 can also be used to process the data line 16 (VPS). 1 04,92
' 1 ___CSSTEMENS AKTIENGESELLSCHAF — 1-77-07-13 a) Signal Processing The analog signal is processed at the amplitude filter (clamping of the video input signal and separation of the sync. impulse) and by means of the data slicing level. The data slicer compensates the attenuation of the data signal due to mistuning and a non linear frequency response the IF-amplifier. As in case of sync. impulse separation, an adaptive circuit is used for separating the data, i.e. the clipping level is always in the middle of the sync. impulse and/or the data signal, independent of the signal amplitude. Both the clipping level and the control voltage for the AGC (Automatic Gain Control) are generated while bit synchronization takes place at the beginning of the teletext line and are stored until the teletext line has been fully scanned. b) Synchronization of Data Clock Clock synchronization is obtained by means of a phase detector + a phaseshifter. A control voltage proportional to the phase difference between the free running oscillator and the incoming data bits is generated by the phase detector. A small time constant is used during bit synchronization, for the rest of the time a 10 times larger constant is used. c) Generation of 6-MHz System Clock The teletext processor generates a picture pixel raster from the 6-MHz system clock. Thus, synchronization of the 6-MHz clock with the CVBS line frequency is necessary for any mixed-mode with teletext. By shortening all sync. impulses to approximately 2,s, interference from synchronization frame pulses can be avoided by means of a mono flop. The SANDCASTLE derived from the 6-MHz clock signal is synchronized in a phase- locked loop to the shortened sync. impulse. A shorter time constant is used during synchronization: If the CVBS signal is noisy or during after-hours operation, 2 points are important: Data acquisition has to be stopped, and the 6-MHz VCO must oscillate with its nominal frequency. For this purpose the teletext processor controls the VCS. signal and switches off the signal component PL of the SANDCASTLE signal, if the CVBS signal is noisy or does not exist. d) Operating-Mode Switch Operation System Clock Usage Mode Syne. to CVBS Pin 28 = NC CVBS. i.e. sub-titles Tes cves interlace/non-interlace mode scs Pin 1 =NC scs Slave-Mode i.e. external synchronization Siemens Aktiengesellschaft 2
SIEMENS AKTLENGESELLSCHAF 1-77-07-13 Block Diagram ' A 0 - 1 | 8 oH Td [es a
1 SEA |
& is) a a “t Siemens Aktiengesellschaft 3
{top view) sttv[]1 Cj 2e[ | TCS) Sts vit (}2 211] eves rrr []3 26[] BLACK Rea []6 asf] ves cur []s 26[] CMONO zero []6 23[] RHONO expa (]7 22{] SAND mm (Je aif] Putz ceo[]9 20] ] veor ver []10 if] punt xtat [| 1e[] veo ru(|e vl] Fe Guo []13 rol] %s me []« 15[] 110 seers Siemens Aktiengesellschaft 4
Pin Definitions and Functions Pin No. Function Description 1 | STTV Sync.-output Sync.-Output: positive or negative synchronous signal to synchronize the TV set. Connection of load resistor to pin 1 (1.2 ka) against Vs = negative synchronous signal. Connection of load resistor to pin 1 against ground = positive synchronous signal.
2 VIL Level CVBS Input Level Selection: with LOW the gain is
‘selection adjusted to a 1 V level and with an open input to | 2.5 V level.
3 RFF RF-filter RF-Level Stabilizer: capacitor for filter time constant
4 RFA RF-amplitude RF-Level Stabilizer: capacitor for internal
amplitude-dependent control voltage.
5 CLIP — [Clipping level__| input capacitor for Clipping Level of adapted
6 ZERO | Zero level Input capacitor for Zero Level of adapted
7 TEXDA | External Data input for External Teletext Data (already
teletext data separated)
8 TIM Time Capacitor for Time Characteristics of adapted
| characteristics _ | Data Separation 9 cPD Clock phase Clock Phase Detector: connection for input detector capacitor
10 Ver Video tape Video Tape Recorder Mode: switch-over to short
recorder mode _| horizontal hold-time constant aa XTAL | Crystal 13.875-MHz Crystal Connection: frequency for j double teletext data rate 12 Filter Connection for 6.9375-MHz data clock ws Ground 0)
14 TTC-output TTC Output
15 TTD TTD-output TTD Output
16 Vs Vs Supply Voltage +
17 F6 F6-output F6 Output: 6-MHz clock (signal with negligible
| harmonic wave) 18 vco | VCO-output 6-MHz VCO Output for frequency-determining resonant circuit
19 PLL1 PLL-low-pass- PLL-Low-Pass-Filter with small time-constant by
filter async. operation (filter 2) Siemens Aktiengesellschaft 5
i * SRE D Ml 6235605 0044157 586 MESIEG | 5 SDA 5231-2 ITEM a | ENS AKTIENGESELLSCHAF T-77-07-13 i Pin Definitions and Functions (cont'd) | Pin No. | Symbol | Function Description | 20 vCOl | VCO-input 6-MHz VCO input for frequency-determining resonat circuit at PLL2 PLL-low-pass- PLL-Low-Pass-Filter with bigger time-constant for filter standard operation
22 SAND | Sandcastle pulse | Sandcastle Pulse
23 [RMONO|R-Monofiop | Chronology Resistor of the monoflops
24 CMONO | C-Monoflop Chronology Capacitor of the monofiops
25 ves | VCS-output VCS-Output: synchronous signal separated from comp. video
26 BLACK | Black level input | Black Level Input Capacitor for the adapted
capacitor ‘synchronous pulse separator
27 CVBS_ | CVBS-input CVBS Input Signal via coupling capacitor with 1 V
signal level when pin 2 is connected to ground 28 Tes! TCS-, (SCS)- Synchronous Signal-Input TCS during text play- SCS input back (or SCS, when pin 1 is open) Siemens Aktiengesellschaft 6
SLE D MM 4235605 OO441456 4Ybe MBSIEG SDA 5231-2 SIEMENS AKTIENGESELLSCHAF Absolute Maximum Ratings Ta= 25°C (all voltages are referred to Vss) Parameter jem a Limit Values __| Unit [min. [max. | Supply volage [Vow [fev Storage temperature range T 39 [-40 [15 c Output current VCS stew | [5 ma Output current TTD ree ee CO Thermal resistance 50 KW system-air Operating Range Supa ogo [ves es [ise Ambient temperature in operation [m lo _|~ —id| c Siemens Aktiengeselischaft 7
SLE D @@ 8235605 0044159 359 MBSIEG SDA 5231-2 SIEMENS AKTIENGESELLSCHAF EE T=77-07-13 Characteristics | Ta= 25°C; Vs=12V 410% ' Parameter Symbol Limit Values Unit i CVBS Input, pin 27 i Input signal level Pin 2 to ground Va 1.4 v : Pin 2 open Var 35 v { Synchronous signal amplitude [Veron [01 | 1 Vv Teletext data level Pin 2 to ground Varo [03 0.46 = | 0.7 v Pin 2 open Vario |0.75 115 j1.75)—|V Generator resistor jr [| | 250 a Adaptation to CVBS Level Input voltage Var= 1 V when Ven | v Ver= 2.5 V when Varn (2.0 v Input current la i) 150 pA Io ) 13 mA Teletext Data Transition times ee 45 ns Max. permissible capacitative load | C sss 40 pF Data clock signal TTC 25 45 v Time deviation with respect to TTD [me (-20— fo 20 [ns DC voltage at outputs Viatsis [| 4 [| 7 Siemens Aktiengeselischaft 8
S5lE D @®@ 8235605 OO44Lb0 070 MBSIEG SDA 5231-2 STEMENS AKTIENGES SCHAF —_SEETENS AKTIENGESELLSCHAF — 7_77.97-13 Characteristics (cont'd) Parameter Symbol Limit Values Unit min. typ. | ma Synchronous Pulse Separation VCS (Signal at teletext decoder) Output voltage a a) 0.4 Vv ~ Ven 24 5.5 Vv Output current Test in 05 mA 1 25H 1.5 mA Delay with respect to CVBS sync. [ra 05 is Sync Output Driver (Signal at TV set) Output voltage | TCS operation a 0.45 Vv Comp. video operation Vi 1 Vv Positive synchronous signal DC voltage load resistor to ground 1.4 v Output current “hh Is | mA Negative synchronous signal DC voltage load resistor to Vs Vins v 6-MHz Clock F6 F6-output signal War 1 2 3 Vv (negligible harmonic content) Transition times [ener [20 [40 ns Max. permissible capacitative load | C 1719 40 po OC voltage at output Virsa [es | v Synchronisation Selection SVS Input current during TCS operation Vzs = 0... 6.1 V 12 40 70 100 BA cves» <I \\15 pA CVBS V2 =10...Vs Tz -5 5 HA TCS Operation Input voltage a “ Load resistor at pin 1 Vea 0 0.8 Vv Load resistor at pin 1 V 28H 2 [8-1 v Siemens Aktiengesellschaft 9
SLE D MM 8235605 OO44LLL TO? MMSIEG > SDA 5231-2 HAF ——— SIENENS AKTIENGESELLSC T-77-07-13 Characteristics (cont'd) Parameter Pr Fe Unit SCS Operation Input voltage Pin 1 open Va 0 v Pin 1 open Ven 3.5 v Line synchronous pulse width TCS operation te 2 us SCS operation tp 3 BS VCR Operation Input voltage during VCR operation Visor. 0 08 Vv Standard operation Viowsn = 2 Vs Vv : Sandcastle Pulse Input Phase locked mode Input voltage PL Vaan 3 v input voltage PL Vzanst 55 v PL-low-time for free-wheeling ms: oscillator Reset pulse for data separation Input voltage CBB. V zene 05 Vv Input voltage CBB V zon 5.5 Vv Input for External Data (current source driving) Internal data processing Input current?) Ir -10 100 nA Voltage Vr I7=— 10 to+ 100 pA External data processing Input current for low 2 In -175 -40 25 pA for high 2 Im -1000 |—500 — 325 nA Voltage v7 7 8 v 17=—25to- 1000 pA 1) Remarks: Test circuit 1
2 Test circuit 2
Siemens Aktiengeselischaft 10
SLE D M@® 8235605
605 OO44Lb2 943 MBSIEG SDA 5231-2
— SCHAF _ SIEMENS AKTIENGESELL 4-77-07-13 Test Circuits Test Circuit 1 SDA 5231-2 Pin 28 fe esto During CVBS operation the output current of pin 28 shall not exceed 15 yA (the pin 12 of the decoder SDA 5242-3 is high-impedance connected) Test Circuit 2 SDA 5231-2 Pin7 esooont The output current of pin 7 cannot be higher than 10 uA if the processing of the teletext da- ta (wich is in CVBS) must occur. Siemens Aktiengeselischaft 11
SLE D MH A235605 OO44LEI S47 MBSIEG SDA 5231-2 HAF — ppemens AKTIENGESELLSCHAF 497 97 43 Test Circuit 3 fo fe z z vo tt 2 a = sf IE ° 5 Rm ®@ HS BY Hf a” 7 2 "7 [eH |. 4 5 ° se - te zl =f ~—F o oH ° @ io. g ov Siemens Aktiengeselischaft 12
SLE D MM 8235605 OO44LbY 7Lb MBSIEG SDA 5231-2 ————— SIEMENS AKTIENGESELLSCHAF — 1-77-07-13 Application Circuit Crystal Ba 2638 af Ese 9 e & 3 nei i s | | t+ : ec # | i i 2 2 3 | |. | . | =f y lee Fi is 2 FS JHH rn PT rs e i aL, z 2 5 $ ES . E ge] < > His RH HF oF cr ape g ” ea i TLS. ° °F es § 5 Siemens Aktiengesellschaft 13
SiE D M@@ 6235605 0044165 b52 MBSIEG A 5231- SIEMENS AKTIENGESELLSCHAF SDA 8231-2 oo T-77-07-13 Application Circuit Ceramic Resonator G G H I ag eed a oe a offs _— | +-0 sontcaste 22y I any = |. ore 5 a a Cr SDA 5231-2 SpH Pye a>2 12 3 se Ss 6 8 Sync. © = ottck) SpF int” [enopF [zane HopFfioope a [Je £ , Prefer | ei p SS ns75Mne cow ff, 1 ti cram Resonator for Loop Filter Components. Standard Application Optimized PLL Behaviour a 1 pF 10 yr Ce 470F 1 pF Cs 220 nF 330 nF Ca 470F 33 nF R 1ka 500 2 Re 3.3ka 3.3 ka Siemens Aktiengeselischatt 14
SLE D M@™ 6235605 OO441bb 559 MESIEG SDA 5231-2 SIEMENS AKTIENGESELLSCHAF ~ T-77-07-13 Application Circuit LC-Tank-Circuit G & ii e% oe ant _ ee ee ee _— es ee rer — —— a ox 22pF ro! ves oF q, En ue [| or, em ee MO ma 6 SDA 5231-2 Poe 15H a>20 t203 6 5 6 7 8 9 on we Bou me Bot for Toner | “Pek |_| poe [ro f * zz | oi 4 > BaISMHe ft, t™ wows Loop Filter Components Standard Application Optimized PLL Behaviour fon 47 uF 47 uF C2 47 nF 4.7 uF C3 47 nF 2.2 ur Ca 47 nF 220 nF Ri 822 82a Re 3,3 ka 390 2 Siemens Aktiengeselischaft 15
SLE D @® 8235605 0044167 425 MBSIEG SDA 5231-2 _ STEMENS AKTIENGESELLSCHAF T-77-07-13 Application Circuit with SDA 5241 os me lf El . | ee ae ¢ BSBSGASS HES VISTI VIWTAS/S [ | TT 2 ° a a neal fs F 2! a ae | ey = yl] 4] 5] m «| wf ol el UE | Tar y ef a] 8] 2] yy | & S| ul ‘S| 3 z| i cS ef Bis * fe = 7 al 3 a 3 Q ¢ 8 : 2. Siemens Aktiengeselischatt 16
SLE D @® 8235605 00441648 361 MBSIEG SDA 5231-2 SIEMENS AKTIENGESELLSCHAF . — — — T+77-07-13 Pulse Diagrams a Video Pin 27 0 aT vcs Pin 25 as 52 ¢ ry 7 output | H Monoflop ‘SCS Operation 00S 2530 qa io Sandcastle 5 a5 BS wv e ia Phase Detector i Current at —f| > bin ‘ve | 152530 §(5 Operation f TS 5) Pin 28 0 AT t— Begin in CCT i ° 5 ‘0 ps eooeas Siemens Aktiengeselischaft 17
SLE D MM 8235605 0044169 2T& MSIEG SDA 5231-2 SIEMENS AKTIENGESELLSCHAF ~ — T-77-07-13 Pin 28 i SDA 5231-2 We RV Vv +78V © 70pa VY i 7 | [A | os | sync- from Amp. Filter Driver . TCS Operation: Vog< 6.1V vesoner : PINT SDA 5231-2 M from Oata ° Separation Lo] [] © 2a Register h External Data Processing: J)> 25 yA ueso0n78 Siemens Aktiengesellschaft 18