SDA3202 | DigiCamel IC Datasheet

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SDA3202 SIEMENS | Alldatasheet

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1.3 GHz PLL with I2C Bus

®@ Low Current Consumption © Cost-Effective and Space-Saving Design Message Transmission Via I2C Bus ¢ Prescaler Output Frequency is Free from © 4 Software-Controlled Outputs Interference Radiation Pin Configuration Pin Definitions Pin Function

1 PD Input for Active Filter/Output for

2 ai Crystal : ‘ "8 3 a2 Crystal 2 v 4 SDA Data 1/0 for 2C Bus 3 16 5 SCL Clock Input for 2G Bus ‘ 1s 6 P7 Port Output (Open Collector) 5 14 7 P6 Port Output (Open Collector) 6 13 8 PS Port Output (Open Collector) 7 12 9 P4 Port Qutput (Open Collector) 8 11 10 P3 Port Output (Current Sink) 9 10 "1 P2 Port Output (Current Sink)

12 Pi Port Output (Current Sink)

0-12 13 PO Port Output (Current Sink)

14 Vs Supply Voltage

: 15 UHF/VHF Signal Input

16 REF Amplifier-Reference Input

17 GND Ground

18 Vo Output of Active Filter

Combined with a VCO (tuner), the SDA 3203 comprises a digital programmable phase-locked loop for televi- sion devices designed to use the PLL frequency synthesis tuning principle. The PLL provides a cyrstal-stable frequency for tuner oscillators between 16 . . . 1300 MHz in the 62.5 KHz raster. By including an external prescaler 1/2, the component can also be used for synthesizing applications of controlled via an I2C bus by the microprocessor. ©Siemens Components, Inc. 7-42 May 1988

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Circuit Description P4...P7 The open collector outputs P4, PS, P6, P7 can be used for a variety of different Tuning Section (refer to block diagram) applications. UHF/VHF The tuner signal is capacitively coupled ntert the UNE/VHF input and subsequently > ou interface amplified. SCL, SDA An asynchronous bidirectional data bus REF ‘The reference input REF should be dis- is used for data transfer between the abled by a capacitor of low series induc- processor and the PLL. As a rule, the tance. The amplified signal passes Clock pulse is supplied by the processor through an asynchronous divider with a (input SCL), while pin SDA operates as fixed ratio of P = 8 and an adjustable input or output depending on the direc- divider N = 256...32767. Subsequent to tion of data flow (open collector, external this process, the signal is compared in a pull-up resistor). digital frequency phase detector with a The data from the processor pass reference frequency frer = 7.8125 kHz. through an !2C bus control. Depending Q1,Q2 This frequency has been derived from a (on their function, the data are subse. 4 MHz crystal oscillator (pin Q1, Q2) by quently fled in registers (lstch 0-3). I. dividing its output signal by Q = 512. the bus is free, both lines will be in the The phase 4 4 two outputs marking state (SDA, SCL are HIGH). UP and DOWN which control the two Each tele. begins with the start conde current sources + and I~ of a charge ming, into Low, while papal ple orp SCL remains in High. All additional infor- VCO signal ete mation transfer takes place during SCL signal appeere prior to the negative = Low and the data is forwarded to the source I+ will pulsate for the duration of Conv tA ham to tan, atte the phase difference. However, during SCL is in High, the message io wie the reversed soquonce of the negative since the PLL acknowledges a top con to pulsate. " - PD, Vp I both signals are in phase, the charge ogc akeanar® “80 reer to table pump output PD changes into the high ° impedance state (PLL in lock). An active All messages are transmitted byte-by- low pass fiter (internal amplifier, external byte, followed by a 9, clock pulse, while output transistor at Vp, and RC combina the control retums the SDA line to Low tion) integrates the current pulses as the (acknowledge conditions). The first byte tuning voltage for the VCO. is. comprised of 7 adress it, Those are With the te 5 tthe u processor to select the PLL can be switched between two values per recat Teens aketioe software. Through this switch-over, the - is always Low control characteristics of the PLL during In the data portion of the message the 1. lock-in can be changed, Le. varying tuner bit of the 1. or 3. data byte determines charactoristics in the various TV bands whether a divider ratio or a control infor- can be adjusted. Nene ist to follow. In each case, the 2. PO...P3 The software-controllable ts PO, 8 or tae came data tYPe OF @ stop con- Pre pe and Po can drive extemal PRE dition has to follow the 1. byte. transistors (intemal current limit) which Vg,GND When the supply voltage is injected, a operate as band selection switch. Power on Reset circuit prevents the PLL from setting the SDA line at Low which would disable the bus. 7-44

Characteristics Vs = 5V; Ta = 25°C (Continued) | ote ee | ee ee Charge Pump Current | coretgcnta [| f | am | sae | sem | | Charge Pump Current [csmtmvne | | tse | em | om | m | |_OutputVottage Locked | vu | os | 5 [| 2s Tv | Vig = 0.8V; I14 = 90 pA |_Outputvotiage. Vu=ov [ve [| 6 | [ [1 | mw | per de Pe te te Vs. v Input Current Vs = Vs le. 8 HA Vsu = OV Is. 6 BA Van = 5.5V Va 6 v lau = 2mA Vat 6 v | Risetme Tw UT ce ts | | rartme Te UT he TT ts Ts | | Frequency fs Te tke | | Heusewietn | tenn [6 | 4 fT Ts | | uPucewisth | tsrow | 6 | 4 | fT as | | Setuptime | tousme | 6 | 4 | Ts | | Hotime | tsa | oe | 4 fT Ts | | Setuptime | testo | 6 | 4 | fT ws | | BusFreetime | tue =f ce Cf ls Ts | Data Transfer | Setuptime | tuoar_ [| 6 | os [Ts | [_Hodtime | toner | oe | oo TCTs 7-46

Measurement Circult 1 ‘ % ty ve " ttm mt ° Cryatal Onctator CxS to Reterence Ober ar pF Cd HA 0 fue ° GND 0-2 Measurement Circult 2 Calibration of Signal Generator | = 50a Device soa Measurement of Input Sensitivity “sv Sn Signal 7 Generator |_o po 150 GND ove Test mode: T1 = High * no cable Measurement Circuit 3 Measurement Circuit 4 vg pao pore ye 28 pene 7-47

vik . exo jaro] [Joana Jon [sun wt Ve Measurement Circuit 6a tsusta Set-up time (start) 12C Bus Time Diagram usta Hold time (start) = wich H-pulse width (clock) tiow _L:pulse width (clock) = tsupat Set-up time (Data transfer) tuopaT —_- Hold time (Data transfer) tsusto Set-up time (Stop) sa tgur Bus free time lnser te Fall time ta Rise time [=] [=] Above times are referenced to Vi and Vi, values Measurement Circuit 6b pora[ sna [sno [oun a[]sra [sue [pore su, gaa son __“100 ws Ms jis rte pun a ono 7-48

’ i SDA 3202 Application Circuit fe P fone 1 [}e eins 18pF ™ = Po Me % SDA 3202 ‘SCL f fee | po pi pzeam espe mt gomyc ace || Gq G (4 ea Computation for Loop Filter Example for Channel! 47 1h X Kvco P = 8;N = 11520; lp = 100 pA; Loop bandwidth: won = «=> Kyco = 18.7 MHZ/V;R = 22 kn; Cy = 180 nF; wp = 336 Hz; Attenuation: $= 0.5 X wR XxX RX Cy fy = 54 Hz; € = 0.67 P = Prescaler N = Progr. divider Standard dimensioning: Co = C1/5 7 Ip = Pump current Kyco = Tuner slope R, Cy = Loop filter 7-48

Description of Function, Application and Circuit Logic Allocation msB A = Acknowledge Adress byte Prog. divider 0 ni4 n13 mi2ntt n10 79 n8 A byte 1 Pon byte 2 Control info 1 51 1 To 1 1 1 t) A byte 1 byte 2 Divider ratio: N= 16384 x n14 + 8192 x n13 + 4096 x 12 + 2048 X n11 + 1024 x N10 + 512 X nO + 256 X NB + 128 X n7 + 64 X n6 + 32Xn5 + 16x Nd + 8X NB +4 x N2+2X M1 + 10 Band selection: P3...P0 = 1 Current sink is active Port outputs: P7...P4= 1 Open collector output is active ‘Switch-over of pump current: sl =1 High current <._° Test Mode: 1,70 =0,0 Normal operation "1 =1 P6 = trer: P7 = Cy TO =1 Tristate charge pump 7-50

Aa sing + K-11. ByteFCII=2.Byhe—HACHY—3 Byte FACIL Byte HACKY UW 1 dd ea es TUT PE AAA AA AAS smat1 203 6 5 6 78 9 1 8 9 1 6 9 1 8 9 4 8 9STOP c Samples none Start-Adr-Tv1-Tv2-St1-St2-Stop é ‘Start-Adr-St1-St2-Tv1-Tv2-Stop ‘Start-Adr-Tv1-Tv2-Stt-Stop Start-Adr-St1-St2-Tv1-Stop ‘ Start-Adr-Tv1-Tv2-Stop . Start-Adr-St1-St2-Stop . ‘Start-Adr-Tv1-Stop Start-Adr-St1-Stop Start = start condition Adr —-=addressing wi = divider ratio 1. byte Tv2 = divider ratio 2. byte st = control word 1. byte sta = control word 2. byte Stop _ =stop condition

Ordering Information

967000:704 7-51

Product Information

SDA3202 specifications and overview.

Summary

1.3 GHZ PLL WITH I2C BUS

Description

1.3 GHZ PLL WITH I2C BUS

Source title SDA3202 Datasheet(PDF) - Siemens Semiconductor Group

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