SDA3112

SDA3112 SIEMENS | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 10

Technical content

Features

• No need for an external integrator Noise free telegram transmission « Integration time constant controlled by software * Microprocessor compatible Maximum ratings Supply voltage Vs | -0.3 to 7.5 v Inputs Q1,Q2, het vr ~0.3 to Vs v IFO, CPL, PLE vw 0.3 to Vs +0.5 v PLE vi 0.310 7.8 v FF vi O3toVst05 |v > Outputs | PD Vo 0.3 to Vs v uD Vo | 0310.33 v _ Tow 7 mA Lock Ig -1to5 mA Internal pull-up A. =3 k@ Junction temperature y, 140 °c Storage temperature range Tag 55 to 150 °c Thermal resistance (system-air) Rinsa | 80 KW Operating range Supply voltage range Vs 451055 v Input frequency tele 32 MHz Divider ratio N 1024 to 16383 Resistance for Lie R, 80 kQ Ler (V5 -0.8)R | Tuning voltage range Vo 0.3 to 33 v open collector | Ambient temperature range Tam | otogs °C 7-32

if . SDA 3112 Characteristics (V; = 5 V + 0.5 V; Tam» = 0 to 70°C) min typ max : Supply current Is 15 22 35 mA Crystal frequency Series C= 18 pf ta 4 MHz Signal inputs F/F input voltage Vien | 3.92 Vs +012, V Vaeu 3.8 Vs v Input current Ie 50 oA Vie=5V Input sensitivity at sine push-pullitriggering ; f=32 MHz Vig 120 1200 | mp5 Inputs (IFO, CPL, PLE) Upper threshold voltage Ven 24 Vv Lower threshold voltage Vow 0.8 v Input current Ven=5V Ton 8 BA Vg, = 0.4 V Tou —550 | yA Ve. = 0.8 V de -500 | uA Band select outputs (BS1. . . .BS5) Reverse current In 10 pA Vay =15V Current drain ay 05 3 mA 2VSV3S15V Tuning section PD, UD, /,.;, LOCK Charge pump current ig +250 +550 [| pA loump= 10 Ing i= 120 kD; Ve=5V Tuning voltage Vist 0.3 v Tsu 1.5 mA Reverse current Tsw 20 pA Vis = 33 V Reference current Ia 30 40 pA ext.2=120 kQ Output voltage Vien 45 v int. RL =3kQ Tian™—100 pA Tiap = 100 pA Voor 07 Vv IFO, PLE Set-up time for release Ne 2 Bs data No 2 Bs Hold time for: release tue 2 us data to 2 BS CPL H pulse width ton 2 us L pulse width tov 2 | us 7-33

Circuit description — Triggered by the ECI inputs F/F a switchable 32/33 counter operates as a 14 bit synchronous prescaler in the dual modulus method by combining it with a5 and 9 bit programmable synchronous counter. In this combination the 5 bit counter controls the switch-over from 32 to 33 (block diagram 1). Dividing ratios of N= 1024 to 16383 are possible. The 18 bit deep shift register latch is subdivided Into 14 bits for storing the dividing ratio N, as well as 1 bit forselecting the pump current and 3 bits for controlling the 5 band selection outputs. The telegram is inserted over the serial data input IFO with the H-L slope of the shift clock CPL, when the enable input is set at H. Beginning with LSB, the complement of the dividing ratio is in- serted in binary code, then the select bit 2 for the pump current and the band selection control bits 2%, 2", 2'7 (please refer to enclosed table). An integrated control circuit checks the world length (18 bit) of the data telegram. The 18 bit latch accepts the data from the shift register during the L state of the enable input PLE. A4MHzcrystal controlled clock oscillator has been integrated in the IC. An internal reference divider divides the output signal of the crystal oscillator (fosc = 4 MHz) by 2048 resulting in 1.953125 kHz (reference signal), providing a frequency resolution of 125 kHz by means of the asynchronous per- manent prescaler (dividing factor 1:64). . In a digital phase detector the divided VCO input signal is compared with the reference signal. If the falling slope of the VCO input signal appears before the falling slope of the reference signal, the output DOWN of the phase detector will be in the H state for the duration of the phase dif- ference. However, if above signal sequence is reversed, the output UP will be in the H state instead. The outputs UP/DOWN control the two current sources 1+ and |— (charge pump). In case both outputs are in the L state, the charge pump output will bein the high impedance mode (TRI-STATE). Information with respect to either the H or L state will be provided at the LOCK output by the logical “NOR?” of the outputs UP/DOWN. The output current of the charge pump (source current = drain current) is adjusted by an external resistor between pin /res and Vcc. In addition, this output current can be generated by the control bit forthe pump current at the same value or at a value increased by a factor of 10 (refer to enclos- ed table). ‘ The current pulses generated by the charge pump are integrated into the tuning voltage by means of an active low pass filter (on-chip loop amplifier and external RC circuit). The de output signal of the low pass filter is available at Vp and is used as tuning voltage for the VCO. In order to pro- vide tuning voltages higher than Vcc = 5 V, the output stage of the amplifier consists of a transistor with an open collector. The external collector resistor can be connected to voltages up to 33 V. To switch voltages higher than Vs = 5 V, the band selection outputs (BS1, BS2, BS3, BS4, BSS) in- clude current drains with open collectors. It is therefore possible to directly connect transistors operating as band selection switches without the use of current limiting resistors (please refer to enclosed application current). 7-34

Pin No. Symbol Function

1 Qi Crystal

2 . | Q2 _ | Crystal

3 BS1 Standard switchover output

4 BS2 Band selection output BS

5 BS3 Band selection output VHF

6 BS4 Band selection output UHF

7 BS5 Band selection output I/II

8 PLE Release input for shift register

9 GND Ground

10 CPL Shift clock pulse input

12 LOCK Lock output

13 PD Amplifier input/charge pump output i

14 Trot Current adjustment for charge pump

15 Vo Tuning voltage output

16 F Signal input

7 F Signal input

18 Vs Supply voltage

TxK. P = prescaler Loop bandwidth: \\/ -—“S2 aw, N = programmable divider ratlo C:xPXN lp | = pumpcurrent - Svco = tuner voltage characteristic Attenuation 1/2 XWp_ XR XC E Ry Cy = loop filter Example for channel 47: P=64 N=11520 [,—=200pA Svco=18.7 MHZ/V R=33kQ C,=330nF @p=124Hz fp 20Hz §=0.675 Standard dimensioning: C2 ~ C1/5 Block diagram 4 i Gynt Vs GNO 18pF Lock R Filter, i i \\ atl Jaz i po) 33k 330nF || 1963125 Hz \\ 32V | «| s e) 22K | : £ | [9 > {vo t 132133 g t 2 os Pe s|J oy Bag o O . [}r20K8 Lm f 18 bit SR'+ memory with BS decoder CPL PLE IFO 5 ee Interface to pP a 2 g 3 3 7-36

‘Truth Table “IFO” bit 24 Pump Current fp L Iret H 10 X het “FO” bit Band selection outputs (L = conducting, H = blocking) 2 2" 2” BS1 BS2 BS3 BS4 BSS L L L L L L L H L L H L L H H H L H L L H L H L L H H L H H H H H L L H L L L H H L H H L H H H H H L H H L H L H H H H H H H H Pulse diagram CPL jl J Muy mM iA lI | l al mpg 1 rit Linh | ro_ J J Lil { HUHLHHH LLU LHHACHEL LSB MSBi | | | ( ‘N= 1930 | tet UHE be | Crt 2 282425 217 First bit Lost bit 7-37

Set-up and hold times. 90% 0% IFO 10% 10% tp tap 90%: 0% PLE fe Ne ton 90% aH pv. CPL Vv O6V- O8V 04), tek 7-38

q SDA 3112 a Test and measurement circuits * bus inputs

8 PLE CPLIFO

nit few — {poss f a v Tyan lu = | separa "~ 20K82 []roxse Signal i inputs v Ww push-pull tt ; 10K Q © O O Test circult 2 ig Test circuit 1 []aone PIN --- Vie t3h867 3.4567 B Prera) y Band selection 8 1 (| [] 08 Test circuit 3 7-39

• i SDA 3112 Test and measurement circuits owl [Janse 19] lw AE ” 1) PINT oMHz ES “Ty PIN2 "8pF Q soya O) O Crystal oscillator Test circuit 4 95v Tee! [}r20Ks

10 Iret SkQ Te

9 9 9 \\ 4 Vu Q 3V 2 []3«2 Y _— = z if Ua z []z2Kn y by (A Ys rm "4 DOWN 30kQ| 3k inputs /outpu! rel I VP sontet oe 2 va ty Vig it 2 PIN'S Ed Test circuit 5 7-40

a ! SDA 3112 a SSSSFSSSSSSeeEeeEEEEe Application circuit Design proposal Ry = 120 kQ (I, = 35/350 pA) . Ry = 22 kQ, Ro... R4 = 22 kQ Loop filter: R = 33 kQ, C, = 330 nF, C, = 47 nF Post filter (in the tuner): Ry = 10 kQ, C; = 47 nF cd fa : . ‘ (] ul Vs3 Vs - 9 4 ii ? hve [Ja 18pF []a ‘ ay Q2z oF [Feet Filte : PD Lock R IFO G PLL IC Serial inter- SDA 3112 PLE face to pi Vial CPL = GND oVs al] BdI/ 11 7-44