SDA2546-5 SIEMENS | Alldatasheet
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Technical content
Features
l Word-organized reprogrammable nonvolatile memory in n-channel floating-gate technology (E2PROM) l 512 · 8-bit organization l Supply voltage 5 V l Serial 2-line bus for data input and output (I2C Bus) l Reprogramming mode, 10 ms erase/write cycle l Reprogramming by means of on-chip control (without external control) l The end of the programming cycle can be checked l Data retention in excess of 10 years l More than 104 reprogramming cycles per address Type Ordering Code Package SDA 2546-5 Q67100-H5096 P-DIP-8-1 Semiconductor Group 29 07.94
Control Functions of the I2C Bus The device is controlled by the controller (master) via I2C Bus in two operating modes: real cycle, and reprogramming cycle, including erase and write to a memory address. In both operating modes, the controller, as transmitter, has to provide 3 bytes to the bus after the start condition. Each byte has to be followed by an acknowledge bit. During a memory read, at least eight additional clock pulses are required to accept the data from the memory, before the stop condition may follow. In the programming case, the active programming process is only started by the stop condition after data input,see figure 3. The chip select word includes the chip select bit CS. Thus is possible to parallel two memory devices. Chip select is obtained when the control bits logically correspond to the condition selected at the select input CS. The most significant bits A8 and A9 are inputs with the chip select words CS/E. Checking the End of the Programming Cycle and Breaking off the Programming Cycle Addressing the chip by the input of CS/E during active reprogramming terminates the programming cycle. If the chip is addressed by entering CS/A, this will be ignored. Only when the programming cycle has terminated will the chip react on CS/A. With this procedure the end of the programming cycle can be checked,see figure 3. Memory Read After the input of the two control words CS/E and WA, the resetting of the start condition and the input of a third control word CS/A, the memory is set ready to read. During acknowledge clock no. 9, the memory information is transferred in parallel to the internal data register. Subsequent to the falling edge of the acknowledge clock, the data output is low-impedance and the first data bit can be sampled,see figure 4. With each shift clock, an additional bit reaches the output. After reading a byte, the internal address counter is automatically incremented through the master receiver acknowledge, so that any number of memory locations can be read one after the other. At address 512, an overflow to address 0 is not initiated. With the stop condition, the data output returns to high-impedance mode. The internal sequence control of the memory component is reset from the read to the quiescent with the stop condition.
The reprogramming cycle of a memory word comprises an erase and a subsequent write process. During erase, all eight bits of the selected word are set into "1" state. During the write process, "0" states are generated according to the information in the internal data register, i.e. according to the third input control word. After the 27th and the last clock of the control word input, the active programming process is started by the stop condition. The active reprogramming process is executed under on-chip control and can be terminated by addressing the device via SCL and SDA. The time required for reprogramming depends on component deviation and data patterns. Therefore, with rated supply voltage the erase/write process is max. 20 ms, or typically, 10 ms. For the input of a data word without write request (write request is defined as data bit in the data register set to "0"), the write process is suppressed and the programming time is shortened. During a subsequent programming of an already erased memory address, the erase process is suppressed again, so that the reprogramming time is also shortened. Switch-On and Chip Reset After the supply voltage VCC has been connected, the data output will be in the high impedance mode. As a rule, the first operating mode to be entered should be the read process of a word address. Subsequent to the data output and to the stop condition, the internal control logic is reset. In case of a subsequent active programming operation, however, the stop condition will not reset the control logic. Chip Erase To erase the entire memory the control word CS/E is entered, the address register is loaded with address 0 and the data register with FF (hex), respectively. Immediately prior to generating the stop condition, the input TP2 is connected from 0 to 5 V. The subsequent stop condition initiates the chip erase. As soon as the erase procedure has terminated, TP2 is again connected to 0 V.
(top view) Pin Definitions and Functions Pin No. Symbol Function
1 VSS Ground
2 CS Chip select
3 TP1 to
4 TP2 0 V normal function, TP2 = 5 V condition
for the erase of the complete memory
5 SDA Data line
6 SCL Clock line
7 TP3 open
Parameter Symbol Limit Values Unit min. max. Supply voltage VCC – 0.3 6 V Input voltage VI – 0.3 6 V Power dissipation PD 130 mW Storage temperature Tstg – 40 125 ˚C Thermal resistance (system-air) R th SA 100 K/W Junction temperature Tj 85 ˚C Operating Range Supply voltage VCC 4.75 5.25 V Ambient temperature TA 07 0 ˚ C
TA = 25 ˚C Parameter Symbol Limit Values Unit Test Condition min. typ. max. Supply voltage VCC 4.75 5.0 5.25 V Supply current ICC 20 mA VCC = 5.25 V Inputs Input voltages SDA/SCL VIL 1.5 V Input voltages SDA/SCL VIH 3.0 VCC V Input currents SDA/SCL IIH 10 mA VIH =VCC Outputs Output current SDA IQL 3.0 mA VQL = 0.4 V Leakage current SDA IQH 10 mA VQH =VCC max Inputs Input voltages CS/TP1/TP2 VIL 0.2 V Input voltages CS/TP1/TP2 VIH 4.5 VCC V Input currents CS/TP1/TP2 IIH 100 mA VCC = 5.25 V Clock frequency fSCL 100 kHz Reprogramming duration tPROG 10 20 ms erase and write Input capacity C I 10 pF Total erase tGL 20 ms TP2 = 5 V
Parameter Symbol Limit Values Unit min. max. Minimum time the bus must be free before a new transmission can start tBUF 4.7 ms Start condition hold time tHD; STA 4.0 ms Clock low period tLOW 4.7 ms Clock high period tHIGH 4.0 ms Start condition set-up time, only valid for repeated start code tSU; STA 4.7 ms Data set-up time tSU; DAT 250 ns Rise time of both the SDA- and SCL-line tR 1 ms Fall time of both the SDA- and SCL-line tF 300 ns Stop condition set-up time tSU; SPO 4.7 ms Note that a transmitter must internally provide at least a hold time to bridge the undefined region (max. 300 ns) of the falling edge of SCL. All values refer toVIH andVIL level.
Clock No. 123456789 (Acknowledge) CS/E CS/A WA DE DA 10100A 8 C S 00 1010––C S 10 A7 A6 A5 A4 A3 A2 A1 A0 0 D7 D6 D5 D4 D3 D2 D1 D0 0 D7 D6 D5 D4 D3 D2 D1 D0 0/1 through memory through memory through memory through memory through master CS/E Chip select for data input into memory (with the word-address-bit A8) CS/A Chip select for data output out of memory WA Memory word address DE Data word for memory DA Data word read out of memory D0 to D7 Data bits ST Start condition SP Stop condition As Acknowledge bit from memory Am Acknowledge bit from master CS Chip select bits A0 to A8 Memory word address bits