SD6022A

SD6022A SHOUDING | Alldatasheet

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e e Th e lo w Ad a inc l co m wh i op e op e co m lo w Th e S O e e ssccrriippttiioo n e w voltage st a ptive Cur r l udes an e m parator, s w i ch providi n e ration over e rates in st a m pensation. o w as 2.2V. mA from a e O T-23-6L pa c n n a compac t ep-up DC/ D r ent Mode e rror amplif w itch pass e n g a stabl e a wide ran g a ble wavef o o perate fro m n 5V supply. is availab c kage. t , high effici D C convert e PWM co n ier, ramp g e lement an d e and hig h g e of load c o rms witho u m an input v n generate le in a l o ency, and e r with an n trol loop, g enerator, d driver in h efficient c urrents. It u t external v oltage as 8V up to o w profile Step-up DC/DC Converter Ver1.0 www.sdw-tw.com FFeeaattuu r r  2.2 V  18V  Up t o  No E  Sma AApppplliicc a a  PD A  DS C  LCD  RF- T  MP3  Port a  Wire r r eess V Start-up In p at 700mA f r o 88% Effici E xternal MO ll SOT-23-6 a a ttiioonnss A C Panel T ags a ble Instru m less Equip m p ut Voltage r om 5V Inp u ency SFET Requ L Package m ent m ent u t ired

The SD6022A is guaranteed to meet per TTyyppiiccaall AApppplliiccaattiioonn CCiirrccuuiitt * The Output voltage is set by R1 and R2: V OUT PPiinn AAssssiiggnnmmeenntt aanndd FFuunnccttiioonn PIN NAME FUNCTION

1 AGND Analog Ground

2 SW Switch Node For Output

3 VDD Output Vo ltage Sense Input

4 EN ON/OFF Control (High Enable)

5 FB Feedback

6 PGND Power Ground

AAbbssoolluuttee MMaaxxiimmuumm RRaattiinnggss ((NNoottee 11))  Package Thermal Resistance (SOT-23-6L) θ JA NNoottee 11:: Stresses beyond those listed Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. NNoottee22:: formance specifications from 0°C to 70°C. Specifications over the –40°C to 85°C operating temperature range are assured by des ign, characterization and correlation with statistical process controls. SW EN FB VDD AGND PGND C3 100 uF Electrolytic Capacito r 47uF L 10 uH D SK521 47uF C 4 220uF Electrolytic Capacito r DC+ 2.5V ~ 5V VOUT 5V ~ 18V SD6022A Ver1.0 www.sdw-tw.com

EElleeccttrriiccaall CChhaarraacctteerriissttiiccss Operating Conditions: T A =25°C, V IN =5V, V OUT =18V, R1=430K, R2=30K, unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V START Start-up Voltage I OUT = 1mA 2.2 V V HOLD Hold-up Voltage I OUT = 1mA 1.7 V V DD Operating VDD Range VDD Pin Voltage 2.5 5 V I Q Supply Current (Quiescent) V IN =2.5V 692 μA V IN =3.6V 630 μA I OFF Supply Current (Shutdown) V EN =0V 52 μA V FB Feedback Reference Voltage 1.188 1.212 1.236 V I FB FB Pin Bias Current 100 nA V ENH EN High Threshold V EN Rising 1 V V ENL EN Low Threshold 0.6 V I EN EN Input Current V EN (H),V EN =2V 8 μA V EN (L),V EN =0.5V 0.15 μA F OSC Switching Frequency I OUT = 500mA 800 KHz ΔF OSC Frequency Change V DD =3V→5V 20 KHz DC Maximum Duty 90 % R SW SW ON Resistance 300 mΩ Note: The EN pin shall be tied to VDD pin and inhibit to act the ON/OFF state whenever the VDD pin voltage may reach to 5.5V or above. Ver1.0 www.sdw-tw.com

TTyyppiiccaall PPeerrffoorrmmaannccee CChhaarraacctteerriissttiiccss Operating Conditions: T A =25°C, R1=430K, R2=30K, unless otherwise specified. Ver1.0 www.sdw-tw.com

=5V, V OUT =18V, I LOAD =0.5A) Start Up IN =5V, V OUT =18V, I LOAD =0.5A) EN 2V/div VOUT 10V/div M 25ms SD6022A Step-up DC/DC Converter Ver1.0 www.sdw-tw.com

PPiinn IInnffoorrmmaattiioonn AAGGNNDD ((PPiinn 11)):: Analog Ground. SSWW ((PPiinn 22)):: Switch Pin. Connect inductor between SW and VIN. Keep these PCB trace lengths as short and wide as possible to reduce EMI and voltage overshoot. VVDDDD ((PPiinn 33)):: Output Voltage Sense Input. The NMOS switch gate drive is derived from the greater of V OUT and V IN EN (Pin 4): Logic Controlled Shutdown Input. EN=High: Normal free running operation. EN=Low: Shutdown. FFBB ((PPiinn 55)):: Feedback Input to the g m Error Amplifier. Connect resistor divider tap to this pin. PPGGNNDD ((PPiinn 66)):: Power Ground. BBlloocckk DDiiaaggrraamm FB VDD SW GND EN 1,6 SD6022A Ver1.0 www.sdw-tw.com

AApppplliiccaattiioonn IInnffoorrmmaattiioonn Inductor Selection For most applications, the value of t he inductor will fall in the range of 1 H to 4.7 H. Its value is chosen based on the desired ripple current. Large value inductors lower ripple current and small value inductors result in higher ripple currents. Higher V IN or V OUT also increases the ripple current as shown in equation .A reasonable starting point for setting ripple current is ΔI L The DC current rating of the inductor should be at least equal to the maximum load current plus half the ripple current to prevent core saturation. Thus, a 2.16A rated inductor should be enough for most applications (1.8A + 0.36A). For better efficiency, choose a low DC-resistance inductor. Different core materials and shapes will change the size/current and pr ice/current relationship of an inductor. Toroid or shielded pot cores in ferrite or perm alloy materials are small and don’t radiate much energy, but generally cost more than powdered iron core inductors with similar electrical characteristics. The choice of which style inductor to use often depends more on the price vs. size requirements and any radiated field/EMI requirements than on what VOUT requires to operate. Output and Input Capacitor Selection In continuous mode, the source current of the top MOSFET is a square wave of duty cycle V OUT IN To prevent large voltage transients, a low ESR in put capacitor sized for the maximum RMS current must be used. The maximum RMS capacitor current is given by: This formula has a maximum at V IN = 2V OUT , where I RMS = I OUT /2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note that the capacitor manufacturer’s ripple current ratings are often based on 2000 hours of life. This makes it advisable to further derate the c apacitor, or choose a capacitor ra ted at a higher temperature than required. Always consult the manufacturer if there is any question. The selection of C OUT is driven by the required effective se ries resistance (ESR).Typically, once the ESR requirement for C OUT has been met, the RMS current rating generally far exceeds the I RIPPLE(P-P) requirement. The output ripple ΔV OUT is determined by: Where f = operating frequency, C OUT = output capacitance and ΔI L = ripple current in the inductor. For a fixed output voltage, the output rippl e is highest at maximum input voltage since ΔI L increases with input voltage. Aluminum elec trolytic and dry tantal um capacitors are both available in surface mount configurations. In the case of tantalum, it is critical that the capacitors are surge tested for use in switching power supplies. An excellent choice is the AVX TPS series of surface mount tantalum. These are specially constructed and tested for low ESR. Ver1.0 www.sdw-tw.com

operation of the SD6022A. Check t Efficiency Considerations The efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine w hat is limiting the efficiency and which change would produce the most improvemen t. Efficiency can be expr essed as: Efficiency = Although all dissipative elements in the circuit produce losses, two main sources usually account for most of the losses: V IN quiescent current and I R losses. The V IN quiescent current loss dominates the efficiency loss at very low load currents whereas the I R loss dominates the efficiency loss at medium to high load currents. In a typical effici ency plot, the efficiency curve at very low load currents can be misleading since the actual power lost is of no consequence. 1. The V IN quiescent current is due to two components: the DC bias current as given in the electrical characteristics and the internal main switch and sy nchronous switch gate charge currents. The gate charge current results from switching the gate capac itance of the internal power MOSFET switches. Each time the gate is switched from high to low to high again, a packet of charge ΔQ moves from V IN to ground. The resulting ΔQ/Δt is the current out of V IN that is typically larger than the DC bias current. In continuous mode, I GATECHG = f (QT+QB) where QT and QB are the gate charges of the internal top and bottom switches. Both the DC bias and gate charge losses are proportional to V IN and thus their effects will be more pronounced at higher supply voltages. 2. I R losses are calculated from the resist ances of the internal switches, R SW and external inductor RL. In continuous mode the average output current flowing through inductor L is “chopped” between the main switch and the synchronous switch. Thus, the series resistance looking into the SW pin is a function of both top and bottom MOSFET R DS(ON) and the duty cycle (DC) as follows: R SW R DS(ON)TOP x DC + R DS(ON)BOT x (1-DC) The R DS(ON) for both the top and bottom MOSFETs can be obtained from the Typical Performance Characteristics curves. Thus, to obtain I R losses, simply add R SW to R L and multiply the result by the square of the average output current. Other losses including C IN and C OUT ESR dissipative losses and inductor core losses generally account for less than 2% of the total loss. Board Layout Suggestions When laying out the printed circ uit board, the following checklis t should be used to ensure proper he following in your layout: 1. The power traces, consisting of the GND trace, the SW trac e and the VIN trace should be kept short, direct and wide. 2. Put the input capacitor as close as possible to the device pins (VIN and GND). 3. SW node is with high frequency voltage swing and should be kept small area. Keep analog components away from SW node to prevent stray capacitive noise pick-up. 4. Connect all analog grounds to a command node and then connect the command node to the power ground behind the output capacitors. Ver1.0 www.sdw-tw.com

PPaacckkaaggiinngg IInnffoorrmmaattiioonn Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max A 1.050 1.250 0.041 0.049 A1 0.000 0.100 0.000 0.004 A2 1.050 1.150 0.041 0.045 b 0.300 0.500 0.012 0.020 c 0.100 0.200 0.004 0.008 D 2.820 3.020 0.111 0.119 E 1.500 1.700 0.059 0.067 E1 2.650 2.950 0.104 0.116 e 0.950(BSC) 0.037(BSC) e1 1.800 2.000 0.071 0.079 L 0.300 0.600 0.012 0.024 θ 0° 8° 0° 8° SD6022A Step-up DC/DC Converter Ver1.0 www.sdw-tw.com