SD411 CALOGIC | Alldatasheet
Document overview
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Technical content
N-Channel Enhancement Mode Dual DMOS FET SD411
FEATURES
- • Normally "OFF" Configuration
- • Tight Matching Characteristics
- • Pin Compatible to Industry Standard Dual JFETs with Addition of Substrate Bias Pin
APPLICATIONS
- • Wideband Differential Amplifiers
- • Cascode Amplifiers
- • High Intercept Point Balanced Mixers
- • Oscillators
- • High Speed Analog Comparators
DESCRIPTION
The SD411 is constructed utilizing Calogic’s high speed lateral DMOS techniques featuring tight matching characteristics between each FET. This device is an excellent choice for instrumentation, communication, RF and Video designs. ORDERING INFOMATION Part Package Temperature Range SD411 TO-78 Herme tic Package -55 oC to +150oC XSD411 Sorted Chips in Carriers -55 oC to +150oC PIN CONFIGURATION CORPORATION S1C TO-78 4 5 BOTTOM VIEW SOURCE 1 DRAIN 1 GATE 1 CASE/BODY SOURCE 2 DRAIN 2 GATE 2 CD2
ABSOLUTE MAXIMUM RATINGS (TA = 25oC unless otherwise noted) Tj Operating Junction TL Lead Temperature (1/16’ from mounting ELECTRICAL CHARACTERISTICS (TA = +25oC per side unless otherwise noted) SYMBOL CHARACTERISTIC MIN TYP MAX UNITS TEST CONDITIONS STATIC BV DS Drain Source Breakdown Voltage 20 V ID = 10 nA, VGS = VBS = -5V BV SD Source-Drain Breakdown Voltage 10 IS = 10 nA, VGD = VBD = -5V BV DB Drain-Body Breakdown Voltage 25 ID = 10 nA, VGB = 0 Source Open BV SB Source-Body Breakdown Voltage 15 IS = 10µA, VGB = 0 Drain Open IDSX Drain-Source Leakage Current 0.7 10 nA VDS = 20V, VGS = VBS = -5V IGBS Gate-Body Leakage Current 1.0 µA VGS = 25V, VDB = VSB = 0 VGS(th) Gate-Source Threshold Voltage 0.5 1.0 2.0 V ID = 1.0µA, VDS = VGS , VSB = 0 rDS(ON) Drain-Source ON Resistance (1) 70 ohms ID = 1.0mA, VGS = 5.0V, VSB = 0 DYNAMIC gfs Common-Source Forward Transconductance(1) 10 12 mS VDS = 10V, ID = 20mA, VSB = 0 f = 1KHZ C iss Common-Source Input Capacitance 3.5 pF VDS = 10V, VGS = VBS = 0 f = 1MHZ C oss Common-Source Output Capacitance 1.2 C rss Common Source Reverse Transfer Capacitance 0.3 C (gs + sb) Source Node Capacitance 4.5 MATCH | VGS1 - VGS2 | Differential Gate Source Voltage 25 mV VDS = 10V ID = 5.0mA VSB = 0Δ| VGS1 - VDS2 | ΔT Differential Drift 25 µV/ oC TA = -55oC to +125C o NOTE 1: Pulse Test, 80sec, 1% Duty Cycle