SCT2650 SCT | Alldatasheet
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Rev. 1.1 For more information www.silicontent.com © 2019 Silicon Content Technology Co., Ltd. All Rights Reserved 1 Product Folder Links: SCT2650 芯洲科技 Silicon Content Technology 4.5V-60V Vin, 5A, High Efficiency Step-down DCDC Converter with Programmable Frequency
FEATURES
Wide Input Range: 4.5V-60V Up to 5A Continuous Output Current 0.8V ±1% Feedback Reference Voltage Integrated 80mΩ High-Side MOSFET Low Quiescent Current: 175uA Pulse Skipping Mode (PSM) in light load 130ns Minimum On-time 4ms Internal Soft-start Time Adjustable Frequency 100KHz to 1.2MHz External Clock Synchronization Precision Enable Threshold for Programmable Input Voltage Under-Voltage Lock Out Protection (UVLO) Threshold and Hysteresis Low Dropout Mode Operation Derivable Inverting Voltage Regulator Over-voltage and Over-Temperature Protection Available in an ESOP-8 Package
APPLICATIONS
12-V, 24-V, 48-V Industry and Telecom Power System Industrial Automation and Motor Control Vehicle Accessories
DESCRIPTION
The SCT 2650 is 5A buck converter with wide input voltage, ranging from 4.5V to 60V, which integrates an 80mΩ high-side MOSFET. The SCT2650, adopting the peak current mode control, supports the Pulse Skipping Modulation (PSM) which assists the converter on achieving high efficiency at light load or standby condition. The SCT 2650 features programmable switching frequency from 100 kHz to 1.2MHz with an external resistor, which provides the flexibility to optimize either efficiency or external component size. The converter supports external clock synchronization with a frequency band from 100kHz to 1.2MHz. The SCT2650 allows power conversion from high input voltage to low output voltage with a minimum 1 30ns on-time of high- side MOSFET. The device offers fixed 4ms soft start to prevent inrush current during the startup of output voltage ramping. The SCT2650 features external loop compensation to provide the flexibility to optimize either loop stability or loop response. The SCT 2650 provides cycle-by-cycle current limit, thermal shutdown protection, output over -voltage protection and input voltage under -voltage protection. The device is available in an 8-pin ESOP-8 package. TYPICAL APPLICATION BOOT VIN EN RT/CLK SW GND COMP FB VIN C1 C2 C3 VOUT 4.5V-60V, Asyncronous Buck Converter Efficiency, Vin=24V, Fsw=500KHz 100 0.001 0.01 0.1 1 Efficiency(%) Output Current(A) Vout=3.3V Vout=5V Vout=12V
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REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Revision 1.0: Production Revision 1.1: Update IEN_H in EC and system UVLO calculation formula by EN pin resistor divider DEVICE ORDER INFORMATION PART NUMBER PACKAGE MARKING PACKAGE DISCRIPTION SCT2650STE 2650 ESOP-8 1) For Tape & Reel, Add Suffix R (e.g. SCT2650STER) ABSOLUTE MAXIMUM RATINGS Over operating free-air temperature unless otherwise noted(1) PIN CONFIGURATION DESCRIPTION MIN MAX UNIT SW GND 4 5 8BOOT VIN EN RT/CLK COMP FB Thermal Pad Figure 1. 8-Lead Plastic ESOP function outside of its Recommended Operation Conditions. from BOOT pin to SW pin. Bootstrap capacitor is charged when SW voltage is low. from VIN pin to high frequency bypass capacitor and GND must be as short as possible. automatically returns to resistor programmed frequency. FB voltage to the internal reference value of 0.8V typical. COMP 6 Error amplifier output. Connect to frequency loop compensation network.
For more information www.silicontent.com © 2019 Silicon Content Technology Co., Ltd. All Rights Reserved 3 Product Folder Links: SCT2650 GND 7 Ground SW 8 Regulator switching output. Connect SW to an external power inductor Thermal Pad 9 Heat dissipation path of die. Electrically connect ion to GND pin. Must be connected to ground plane on PCB for proper operation and optimized thermal performance. RECOMMENDED OPERATING CONDITIONS Over operating free-air temperature range unless otherwise noted PARAMETER DEFINITION MIN MAX UNIT VIN Input voltage range 4.5 60 V VOUT Output voltage range 0.8 57 V TJ Operating junction temperature -40 150 °C ESD RATINGS PARAMETER DEFINITION MIN MAX UNIT VESD Human Body Model(HBM), per ANSI-JEDEC-JS-001-2014 specification, all pins(1) -1 +1 kV Charged Device Model(CDM), per ANSI-JEDEC-JS-002- 2014 specification, all pins(2) -0.5 +0.5 kV (1) JEDEC document JEP155 states that 500V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250V CDM allows safe manufacturing with a standard ESD control process. THERMAL INFORMATION PARAMETER THERMAL METRIC ESOP-8L UNIT 𝜃𝑗𝑎 Junction-to-ambient thermal resistance (standard board) 42 °C/W 𝜓𝑗𝑡 Junction-to-top characterization parameter 5.9
ELECTRICAL CHARACTERISTICS
VIN=24V, TJ=-40°C~125°C, typical value is tested under 25°C. SYMBOL PARAMETER TEST CONDITION MIN TYP MAX UNIT Power Supply VIN Operating input voltage 4.5 60 V VIN_UVLO Input UVLO Threshold VIN rising 4.2 4.4 V Hysteresis 320 mV ISHDN Shutdown current from VIN pin EN=0, no load 2 5 μA IQ Quiescent current from VIN pin EN floating, no load, non- switching, BOOT-SW=5V 175 μA Power MOSFETs RDSON_H High-side MOSFET on-resistance VBOOT-VSW=5V 80 mΩ Reference and Control Loop VREF Reference voltage of FB 0.792 0.8 0.808 V GEA Error amplifier trans-conductance -2μA<ICOMP<2μA, VCOMP=1V 300 μS ICOMP_SRC EA maximum source current VFB=VREF-100mV, VCOMP=1V 30 μA
4 For more information www.silicontent.com © 2019 Silicon Content Technology Co., Ltd. All Rights Reserved Product Folder Links: SCT2650 SYMBOL PARAMETER TEST CONDITION MIN TYP MAX UNIT ICOMP_SNK EA maximum sink current VFB=VREF+100mV, VCOMP=1V 30 μA VCOMP_H COMP high clamp 2.25 V VCOMP_L COMP low clamp 0.47 V Current Limit and Over Current Protection ILIM_HS High-side power MOSFET peak current limit threshold 6.8 8 9.2 A Enable and Soft Startup VEN_H Enable high threshold 1.2 V VEN_L Enable low threshold 1.05 V IEN_L Enable pin pull-up current EN=1V 1 μA IEN_H Enable pin pull-up current EN=1.5V 4 uA TSS Soft start time 4 ms Switching Frequency and External Clock Synchronization FRANGE_RT Frequency range using RT mode 100 1200 kHz FSW Switching frequency RRT=200 kΩ(1%) 450 500 550 kHz tON_MIN Minimum on-time VIN=24V 130 ns Protection VOVP Feedback overvoltage with respect to VFB/VREF rising 110 % reference voltage VFB/VREF falling 105 % VBOOTUV BOOT-SW UVLO threshold BOOT-SW falling 2.52 V Hysteresis 230 mV TSD Thermal shutdown threshold * TJ rising 172 °C Hysteresis 12 °C *Derived from bench characterization
Figure 8. Functional Block Diagram
For more information www.silicontent.com © 2019 Silicon Content Technology Co., Ltd. All Rights Reserved 7 Product Folder Links: SCT2650 OPERATION Overview The SCT2650 is a 4.5V-60V input, 5A output, buck converter with integrated 80mΩ Rdson high-side power MOSFET. It implements constant frequency peak current mode control to regulate output voltage, providing excellent line and load transient response and simplifying the external loop compensation design. The switching frequency is programmable from 100kHz to 1.2MHz with two setting modes, resistor setting frequency mode and the clock synchronization mode, to optimizes either the power efficiency or the external components’ sizes. The SCT2650 features an internal 4ms soft -start time to avoid large inrush current and output voltage overshoot during startup. The device also supports monolithic startup with pre-biased output condition. The seamless mode-transition between PWM mode and PSM mode operations ensure high efficiency over wide load current range. The quiescent current is typically 175uA under no load or sleep mode condition to achieve high efficiency at light load. The SCT2650 has a default input start-up voltage of 4.2V with 320mV hysteresis. The EN pin is a high-voltage pin with a precision threshold that can be used to adjust the input voltage lockout thresholds with two external resistors to meet accurate higher UVLO system requirements. Floating EN pin enables the device with the internal pull-up current to the pin. Connecting EN pin to VIN directly starts up the device automatically. The SCT2650 full protection features include the input under-voltage lockout, the output over-voltage protection, over current protection with cycle-by-cycle current limiting, output hard short protection and thermal shutdown protection. Peak Current Mode Control The SCT2650 employs fixed frequency peak current mode control. An internal clock initiates turn ing on the integrated high-side power MOSFET Q1 in each cycle, then inductor current rises linearly. When the current through high-side MOSFET reaches the threshold level set by the COMP voltage of the internal error amplifier, the integrated high-side MOSFET is turned off. The error amplifier serves the COMP node by comparing the voltage of the FB pin with an internal 0.8V reference voltage. When the load current increases, a reduction in the feedback voltage relative to the reference raises COMP voltage till the average inductor current matches the increased load current. This feedback loop well regulates the output voltage to the reference. The device also integrates an internal slope compensation circuitry to prevent sub- harmonic oscillation when duty cycle is greater than 50% for a fixed frequency peak current mode control. The SCT2650 operates in Pulse Skipping Mode (PSM) with light load current to improve efficiency. When the load current decreases, an increment in the feedback voltage lead s COMP voltage drop. When COMP falls to a low clamp threshold (470mV typically), device enter s PSM. The output voltage decays due to output cap acitor discharging during skipping period. Once FB voltage drops lower than the reference voltage, and the COMP voltage rises above low clamp threshold . Then high -side power MOSFET turns on in next clock pulse. After several switching cycles with typical 200mA peak inductor current, COMP voltage drops and is clamped again and pulse skipping mode repeats if the output continues light loaded. This control scheme helps achieving higher efficiency by skipping cycles to reduce switching power loss and gate drive charging loss. The controller consumption quiescent current is 175uA during skipping period with no switching to improve efficiency further. Enable and Under Voltage Lockout Threshold The SCT2650 is enabled when the VIN pin voltage rises above 4.2V and the EN pin voltage exceeds the enable threshold of 1.2V. The device is disabled when the VIN pin voltage falls below 3.9V or when the EN pin voltage is below 1.05V. An internal 1uA pull up current source to EN pin allows the device enable when EN pin floats. EN pin is a high voltage pin that can be connected to VIN directly to start up the device. For a higher system UVLO threshold, connect an external resistor divider (R1 and R2) shown in Figure 9 from VIN to EN. The UVLO rising and falling threshold can be calculated by Equation 1 and Equation 2 respectively.
For more information www.silicontent.com © 2019 Silicon Content Technology Co., Ltd. All Rights Reserved 9 Product Folder Links: SCT2650 In applications where both resistor setting frequency mode and clock synchronization mode are needed, the device can be configured as shown in Figure 10. Before an external clock is present, the device works in resistor setting frequency mode. When an external clock present s, the device automatically transitions from resistor setting mode to external clock synchronization mode. An internal phase locked loop PLL locks internal clock frequency onto the external clock with in typical 85us. The converter transitions from the clock synchronization mode to the resistor setting frequency mode when the external clock disappears. Bootstrap Voltage Regulator and Low Drop-out Operation An external bootstrap capacitor between BOOT pin and SW pin powers the floating gate driver to high-side power MOSFET. The bootstrap capacitor voltage is charged from an integrated voltage regulator when high -side power MOSFET is off and the external low-side diode conducts . The recommended value of the BOOT capacitor is 0.1 μF. The UVLO of high -side MOSFET gate driver has rising threshold of 2.52V and hysteresis of 230mV. When the device operates with high duty cycle or extremely light load , bootstrap capacitor may be not recharged in considerable long time. The voltage at bootstrap capacitor is insufficient to drive high-side MOSFET fully on. When the voltage across bootstrap capacitor drops below 2.29V, BOOT UVLO occurs. The converter forces turning on an integrated low-side MOSFET periodically to refresh the voltage of bootstrap capacitor to guarantee the converter’s operation over a wide duty range. During the condition of ultra-low voltage difference from the input to the output, SCT2650 operates in Low Drop-Out LDO mode. High-side MOSFET remains turning on as long as the BOOT pin to SW pin voltage is higher than BOOT UVLO threshold 2.52V. When the voltage from BOOT to SW drops below 2.29 V, the high-side MOSFET turns off and low-side MOSFET turns on to recharge bootstrap capacitor periodically in the following several switching cycles. Low-side MOSFET only turns on for 100ns in each refresh cycle to minimize the output voltage ripple . Low-side MOSFET may tur n on for several time s till the bootstrap voltage is charged to higher than 2. 52V for high-side MOSFET working normally. The effective duty cycle of the converter during LDO operation can be approaching to 100%. During slowing power up and power down application, the output voltage can closely track the input voltage ramping down thanks to LDO operation mode. As the input voltage is reduced to near the output voltage, i.e. during slowing power-up and power-down application, the off-time of the high side MOSFET starts to approach the minimum value. Without LDO operation mode, beyond this point the switching may become erratic and/or the output voltage will fall out of regulation. To avoid this problem, the SCT2650 LDO mode automatically reduces the switching frequency to increase the effective duty cycle and maintain regulation. Over Current Limit The SCT2650 implements over current protection with fold back current limit. The SCT2650 cycle-by-cycle limits high-side MOSFET peak current to avoid inductor current running away during unexpected overload or output hard short condition. When overload or hard short happens, the converter cannot provide output current to satisfy loading requirement. The inductor current is clamped at over current limitation. Thus , the output voltage drops below regulated voltage with FB voltage less than internal reference voltage continuously. The COMP pin voltage ramps up to high clamp voltage 2.25V typical. The SCT2650 implements frequency foldback to protect the converter in unexpected overload or output hard short condition at higher switching frequencies and input voltages. The oscillator frequency is divided by 1, 2, 4, and 8 as the FB pin voltage falls from 0.8 V to 0 V. The SCT2650 uses a digital frequency foldback to enable synchronization to an external clock during normal start-up and fault conditions. During short-circuit events, the inductor current can exceed the peak current limit because of the high input voltage and the minimum on-time. When the output voltage is forced low by the shorted load, the inductor current decreases slowly during the switch off -time. The frequency foldback effectively increases the off -time by increasing the period of the switching cycle prov iding more time for the inductor current to ramp down. With a maximum frequency foldback ratio of 8, there is a maximum frequency at which the inductor current can be controlled by frequency foldback protection. Equation 5 calculates the maximum switching frequency at which the
10 For more information www.silicontent.com © 2019 Silicon Content Technology Co., Ltd. All Rights Reserved Product Folder Links: SCT2650 inductor current remains under control when V OUT is forced to V OUT_SHORT. The selected operating frequency must not exceed the calculated value. 𝑓𝑠𝑤(max 𝑠𝑘𝑖𝑝) = 𝑓𝐷𝐼𝑉 𝑡𝑚𝑖𝑛_𝑂𝑁 × (𝐼𝐿𝐼𝑀𝐼𝑇 × 𝑅𝐷𝐶 + 𝑉𝑂𝑈𝑇_𝑆𝐻𝑂𝑅𝑇 + 𝑉𝑑 𝑉𝐼𝑁_𝑀𝐴𝑋 − 𝐼𝐿𝐼𝑀𝐼𝑇 × 𝑅𝐷𝑆(𝑜𝑛) + 𝑉𝑑 ) (5) where ILIMIT: Limited average current RDC: Inductor DC resistance VIN_MAX: Maximum input voltage VOUT_SHORT: Output voltage during short Vd: Diode voltage drop RDS(on): Integrated high side FET on resistance Tmin_ON: Controllable minimum on time fDIV: Frequency divide equals (1,2,4 or 8) Over voltage Protection The SCT2650 implements the Over-voltage Protection OVP circuitry to minimize output voltage overshoot during load transient, recovering from output fault condition or light load transient. The overvoltage comparator in OVP circuit compares the FB pin voltage to the internal reference voltage. When FB voltage exceeds 110% of internal 0.8V reference voltage, the high-side MOSFET turns off to avoid output voltage continue to increase. When the FB pin voltage falls below 105% of the 0.8V reference voltage, the high-side MOSFET can turn on again. Thermal Shutdown The SCT2650 protects the device from the damage during excessive heat and power dissipation conditions. Once the junction temperature exceeds 172°C, the internal thermal sensor stops power MOSFETs switching. When the junction temperature falls below 160°C, the device restarts with internal soft start phase.
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APPLICATION INFORMATION
VIN=4.5V~60V 5.5uH 4.7uF 4.7uF 0.1uF 200K 47uF 47uF 20K 4.7nF 31.6K 10.2K C12 0.1uF VOUT=3.3V IOUT=5A 4.7uF C13 Optional Optional 4.7uF C10 47uF C11 47uF 76.8K 309K Figure 11. SCT2650 Design Example, 3.3V Output with Programmable UVLO
R5 and R 6 in typical application schematic . Table 1. R5, R6Value for Common Output Voltage is selected to achieve both small solution size and high efficiency operation. equation 7, or determined from Figure 7. Table 2. RFSW Value for Common Switching Frequencies
200 KHz 500 KΩ
330 KHz 301 KΩ
500 KHz 200 KΩ
(stop or disable). Use Equation 8 and Equation 9 to calculate the values 309 kΩ and 76.8 kΩ of R1 and R2 resistors.
For more information www.silicontent.com © 2019 Silicon Content Technology Co., Ltd. All Rights Reserved 13 Product Folder Links: SCT2650 Inductor Selection There are several factors should be considered in selecting inductor such as inductance, saturation current, the RMS current and DC resistance(DCR). Larger inductance results in less inductor current ripple and therefore leads to lower output voltage ripple. However, the larger value inductor always corresponds to a bigger physical size, higher series resistance, and lower saturation current. A good rule for determining the inductance to use is to allow the inductor peak-to-peak ripple current to be approximately 20%~40% of the maximum output current. The peak-to-peak ripple current in the inductor ILPP can be calculated as in Equation 10. 𝐼𝐿𝑃𝑃 = 𝑉𝑂𝑈𝑇 ∗ (𝑉𝐼𝑁 − 𝑉𝑂𝑈𝑇) 𝑉𝐼𝑁 ∗ 𝐿 ∗ 𝑓𝑆𝑊 (10) Where ILPP is the inductor peak-to-peak current L is the inductance of inductor fSW is the switching frequency VOUT is the output voltage VIN is the input voltage Since the inductor-current ripple increases with the input voltage, so the maximum input voltage in application is always used to calculate the minimum inductance required. Use Equation 11 to calculate the inductance value. 𝐿𝑀𝐼𝑁 = 𝑉𝑂𝑈𝑇 𝑓𝑆𝑊 ∗ 𝐿𝐼𝑅 ∗ 𝐼𝑂𝑈𝑇(𝑚𝑎𝑥) ∗ (1 − 𝑉𝑂𝑈𝑇 𝑉𝐼𝑁(𝑚𝑎𝑥) ) (11) Where LMIN is the minimum inductance required fsw is the switching frequency VOUT is the output voltage VIN(max) is the maximum input voltage IOUT(max) is the maximum DC load current LIR is coefficient of ILPP to IOUT The total current flowing through the inductor is the inductor ripple current plus the output current. When selecting an inductor, choose its rated current especially the saturation current larger than its peak operation current and RMS current also not be exceeded. Therefore, the peak switching current of inductor , I LPEAK and I LRMS can be calculated as in equation 12 and equation 13. 𝐼𝐿𝑃𝐸𝐴𝐾 = 𝐼𝑂𝑈𝑇 + 𝐼𝐿𝑃𝑃 2 (12) 𝐼𝐿𝑅𝑀𝑆 = √(𝐼𝑂𝑈𝑇 )2 + 1 12 ∗ (𝐼𝐿𝑃𝑃 )2 (13) Where ILPEAK is the inductor peak current IOUT is the DC load current ILPP is the inductor peak-to-peak current ILRMS is the inductor RMS current In overloading or load transient conditions, the inductor peak current can increase up to the switch current limit of the device which is typically 8A. The most conservative approach is to choose an inductor with a saturation current rating greater than 8A. Because of the maximum I LPEAK limited by device, the maximum output current that the SCT2650 can deliver also depends on the inductor current ripple. Thus, the maximum desired output current also
14 For more information www.silicontent.com © 2019 Silicon Content Technology Co., Ltd. All Rights Reserved Product Folder Links: SCT2650 affects the selection of inductance. The smaller inductor results in larger inductor current ripple leading to a lower maximum output current. Diode Selection The SCT2650 requires an external catch diode between the SW pin and GND. The selected diode must have a reverse voltage rating equal to or greater than VIN(max). The peak current rating of the diode must be greater than the maximum inductor current. Schottky diodes a re typically a good choice for the catch diode due to their low forward voltage. The lower the forward voltage of the diode, the higher the efficiency of the regulator. Typically, diodes with higher voltage and current ratings have higher forward voltages. A diode with a minimum of 60-V reverse voltage is preferred to allow input voltage transients up to the rated voltage of the SCT2650. For the example design, the B560C-13-F Schottky diode is selected for its lower forward voltage and good thermal characteristics compared to smaller devices. The typical forward voltage of the B560C-13-F is 0.7 volts at 5 A. The diode must also be selected with an appropriate power rating. The diode conducts the output current during the off-time of the internal power switch . The off -time of the internal switch is a function of the maximum input voltage, the output voltage, and the switching frequency. The output current during the off -time is multiplied by the forward voltage of the diode to calculate the instantaneous condu ction losses of the diode. At higher switching frequencies, the ac losses of the diode need to be taken into account. The ac losses of the diode are due to the charging and discharging of the junction capacitance and reverse recovery charge. Equation 14 is used to calculate the total power dissipation, including conduction losses and ac losses of the diode. The B560C-13-F diode has a junction capacitance of 300 pF. Using Equation 14, the total loss in the diode at the maximum input voltage is 3.53 W. If the power supply spends a significant amount of time at light load currents or in sleep mode, consider using a diode which has a low leakage current and slightly higher forward voltage drop. 𝑃𝐷 = (𝑉𝐼𝑁_𝑀𝐴𝑋 − 𝑉𝑂𝑈𝑇) × 𝐼𝑂𝑈𝑇 × 𝑉𝑑 𝑉𝐼𝑁_𝑀𝐴𝑋 + 𝐶𝑗 × 𝑓𝑆𝑊 × (𝑉𝐼𝑁 + 𝑉𝑑)2 (14) Input Capacitor Selection The input current to the step-down DCDC converter is discontinuous, therefore it requires a capacitor to supply the AC current to the step-down DCDC converter while maintaining the DC input voltage. Use capacitors with low ESR for better performance. Ceramic capacitors with X5R or X7R dielectrics are usually suggested because of their low ESR and small temperature coefficients, and it is strongly recommended to use another lower value capacitor (e.g. 0.1uF) with small package size (0603) to filter high frequency switching noise. Place the small size capacitor as close to VIN and GND pins as possible. The voltage rating of the input capacitor must be greater than the maximum input voltage. And the capacitor must also have a ripple current rating greater than the maximum input current ripple. The RMS current in the input capacitor can be calculated using Equation 15. ICINRMS = IOUT ∗ √VOUT VIN ∗ (1 − VOUT VIN ) (15) The worst case condition occurs at VIN=2*VOUT, where: ICINRMS = 0.5 ∗ IOUT (16) For simplification, choose an input capacitor with an RMS current rating greater than half of the maximum load current.
For more information www.silicontent.com © 2019 Silicon Content Technology Co., Ltd. All Rights Reserved 15 Product Folder Links: SCT2650 When selecting ceramic capacitors, it needs to consider t he effective value of a capacitor decreasing as the DC bias voltage across a capacitor increasing. The input capacitance value determines the input ripple voltage of the regulator. The input voltage rippl e can be calculated using Equation 17 and the maximum input voltage ripple occurs at 50% duty cycle. ∆VIN = IOUT fSW ∗ CIN ∗ VOUT VIN ∗ (1 − VOUT VIN ) (17) For this example, four 4.7μF, X7R ceramic capacitors rated for 100 V in parallel are used. And a 0.1 μF for high- frequency filtering capacitor is placed as close as possible to the device pins. Bootstrap Capacitor Selection A 0.1μF ceramic capacito r must be connected between BOOT pin and SW pin for proper operation. A ceramic capacitor with X5R or be tter grade dielectric is recommended. The capacitor should have a 10 V or higher voltage rating. Output Capacitor Selection The selection of output capacitor will affect output voltage ripple in steady state and load transient performance. The output ripple is essentially composed of two parts. One is caused by the inductor current ripple going through the Equivalent Series Resistance ESR of the output capacitors and the other is caused by the inductor current ripple charging and discharging the output capacitors. To achieve small output voltage ripple, choose a low-ESR output capacitor like ceramic capacitor. For ceramic capacitors, the capacitance dominates the output ripple. For simplification, the output voltage ripple can be estimated by Equation 18 desired. ∆VOUT = 𝑉𝑂𝑈𝑇 ∗ (𝑉𝐼𝑁 − 𝑉𝑂𝑈𝑇) 8 ∗ 𝑓𝑆𝑊 2 ∗ 𝐿 ∗ 𝐶𝑂𝑈𝑇 ∗ 𝑉𝐼𝑁 (18) Where ΔVOUTis the output voltage ripple fSW is the switching frequency L is the inductance of inductor COUT is the output capacitance VOUT is the output voltage VINis the input voltage Due to capacitor’s degrading under DC bias, the bias voltage can significantly reduce capacitance. Ceramic capacitors can lo se most of their capacitance at rated voltage. Therefore, leave margin on the voltage rating to ensure adequate effective capacitance. Typically, four 47μF ceramic output capacitors work for most applications. Compensation Components The SCT2650 employs peak current mode control for easy compensation and fast transient response. An external network comprising resister R4, ceramic capacitors C7 and optional C6 connected to the COMP pin is used for the loop compensation. The equation 19 shows the close-loop small signal transfer function. 𝐻(𝑆) = [𝐴𝐸𝐴 ∗ 1 + 𝑆 2𝜋∗𝑓𝑍1 (1 + 𝑆 2𝜋∗𝑓𝑃1 ) ∗ (1 + 𝑆 2𝜋∗𝑓𝑃3 ] ∗ [𝐺𝐼𝑆𝑁𝑆 ∗ 𝑉𝑂𝑈𝑇 𝐼𝑂𝑈𝑇 1 + 𝑆 2𝜋∗𝑓𝑍2 1 + 𝑆 2𝜋∗𝑓𝑃2 ] ∗ 𝑉𝐹𝐵 𝑉𝑂𝑈𝑇 (19) where AEA is error amplifier voltage gain GISNS is COMP to SW current trans-conductance, 17A/V typically
16 For more information www.silicontent.com © 2019 Silicon Content Technology Co., Ltd. All Rights Reserved Product Folder Links: SCT2650 The DC voltage gain of the loop is given by equation 20. 𝐴𝑉𝐷𝐶 = 𝐴𝐸𝐴 ∗ 𝐺𝐼𝑆𝑁𝑆 ∗ 𝑉𝐹𝐵 𝐼𝑂𝑈𝑇 (20) The system has two noteworthy poles: one is due to the compensation capacitor C7 and the error amplifier output resistor. The other is caused by the output capacitor and the load resistor. These poles as located at: 𝑓𝑃1 = 1 2𝜋 ∗ 𝑅𝑂𝐸𝐴 ∗ 𝐶7 = 𝐺𝐸𝐴 2𝜋 ∗ 𝐴𝐸𝐴 ∗ 𝐶7 (21) 𝑓𝑃2 = 1 2𝜋 ∗ 𝑅𝐿𝑂𝐴𝐷 ∗ 𝐶𝑂𝑈𝑇 = 𝐼𝑂𝑈𝑇 2𝜋 ∗ 𝑉𝑂𝑈𝑇 ∗ 𝐶𝑂𝑈𝑇 (22) where ROEA is error amplifier output resistor GEA is Error amplifier trans-conductance, 300uS typically RLOAD is equivalent load resistor The system has one zero of importance from R4 and C7. fz1 is used to counteract the fp2, and fz1 located at: f𝑍1 = 1 2𝜋 ∗ 𝐶7 ∗ 𝑅4 (23) The system may have another important zero if the output capacitor has a large capacitance or a high ESR value. The zero, due to the ESR and the capacitance of the output capacitor is calculated by Equation 24. f𝑍2 = 1 2𝜋 ∗ 𝐶𝑂𝑈𝑇 ∗ 𝐸𝑆𝑅 (24) In this case, a third pole set by the optional compensation capacitor C6 and the compe nsation resistor R4 is used to compensates the effect of the ESR zero. This pole is calculated by Equation 25. f𝑃3 = 1 2𝜋 ∗ 𝐶6 ∗ 𝑅4 (25) The crossover frequency of converter is shown in Equation 26. f𝐶 = 𝑉𝐹𝐵 𝑉𝑂𝑈𝑇 ∗ 𝐺𝐸𝐴 ∗ 𝐺𝐼𝑆𝑁𝑆 ∗ 𝑅4 2𝜋 ∗ 𝐶𝑂𝑈𝑇 (26) The system crossover frequency, where the feedback loop has unity gain, is important. A lower crossover frequency results in slower line and load transient response. A higher crossover frequency could cause the system unstable. A recommended rule of thumb is to set the crossover frequency to be approximately 1/10 of switching frequency. The following steps can be followed to calculate the external compensation components. Calculate the compensation resistor R4 with Equation 27 once crossover frequency is selected. 𝑅4 = 𝑉𝑂𝑈𝑇 𝑉𝐹𝐵 ∗ 2𝜋 ∗ 𝐶𝑂𝑈𝑇 ∗ 𝑓𝐶 𝐺𝐸𝐴 ∗ 𝐺𝐼𝑆𝑁𝑆 (27) Then calculate C7 by placing a compensation zero at or before the output stage pole. 𝐶7 = 𝑅𝐿𝑂𝐴𝐷 ∗ 𝐶𝑂𝑈𝑇 𝑅4 (28) Determine if the optional compensation capacitor C6 is required. G enerally, it is required if the ESR zero f Z2 is located less than half of the switching fr equency. Then fp3 can be used to cancel fz2 . C6 can be calculated with Equation 29. 𝐶6 = 𝐶𝑂𝑈𝑇 × 𝐸𝑆𝑅 (29)
For more information www.silicontent.com © 2019 Silicon Content Technology Co., Ltd. All Rights Reserved 17 Product Folder Links: SCT2650 Table 3 lists typical values of compensation components for some standard output voltages with various output ceramic capacitors and inductors. The values of the compensation components have been optimized for fast transient responses and good stability. F or the conditions not list in Table 3, customers can use Equation 2 7- Equation 29 to optimize the compensation components. Table 3: Compensation Values for Typical Output Voltage/Capacitor Combinations at fsw=500KHz Vout L1 COUT R4 C7 C6 2.5V 4.7uH 4*47uF 16.9K 4.7nF 68pF (optional) 3.3V 5.5uH 4*47uF 20K 4.7 nF 47pF (optional) 5V 7.8uH 4*47uF 33.2K 3.3nF 22pF (optional) 12V 10uH 4*47uF 53.6K 1nF 220pF 24V 15uH 4*47uF 105k 1nF 220pF
amplifiers requiring a negative power supply. Figure 12. SCT2650 Inverting Power Supply
- Power grounding scheme is very critical because of carrying power, the rmal, and glitch/bouncing noise
distributed evenly on PCB. Sufficiently placing ground area will optimize thermal and not causing over heat area.
- Place a low ESR ceramic capacitor as close to VIN pin and the ground as possible to reduce parasitic effect.
- Freewheeling diode should be place as close to SW pin and the ground as possible to reduce parasitic effect.
- For operation at full rated load, the top side ground area must provide adequate heat dissipating area. Make
sure top switching loop with power have lower impendence of grounding.
- The bottom layer is a large ground plane connected to the ground plane on top layer by vias. The power pad
is of concern, plugging or tenting can be used to achieve a repeatable process.
- Output inductor and freewheeling diode should be placed close to the SW pin. The switching area of the PCB
conductor minimized to prevent excessive capacitive coupling.
- The RT/CLK terminal is sensitive to noise so the RT resistor should be located as close as possible to the IC
and routed with minimal lengths of trace.
- UVLO adjust and RT resistors, loop compensation and feedback components should connect to small signal
ground which must return to the GND pin without any interleaving with power ground.
- Route BOOT capacitor trace on the other layer than top layer to provide wide path for topside ground.
- For achieving better thermal performance, a four-layer layout is strongly recommended.
Figure 25. PCB Layout Example
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PACKAGE INFORMATION
SOP8/PP(95x130) Package Outline Dimensions Symbol Dimensions in Millimeters Dimensions in Inches Min. Max. Min. Max. A 1.300 1.700 0.051 0.067 A1 0.000 0.100 0.000 0.004 A2 1.350 1.550 0.053 0.061 b 0.330 0.510 0.013 0.020 c 0.170 0.250 0.007 0.010 D 4.700 5.100 0.185 0.201 D1 3.050 3.250 0.120 0.128 E 3.800 4.000 0.150 0.157 E1 5.800 6.200 0.228 0.244 E2 2.160 2.360 0.085 0.093 e 1.270(BSC) 0.050(BSC) L 0.400 1.270 0.016 0.050 0° 8° 0° 8° NOTE: 1. Drawing proposed to be made a JEDEC package outline MO-220 variation. 2. Drawing not to scale. 3. All linear dimensions are in millimeters. 4. Thermal pad shall be soldered on the board. 5. Dimensions of exposed pad on bottom of package do not include mold flash. 6. Contact PCB board fabrication for minimum solder mask web tolerances between the pins.
For more information www.silicontent.com © 2019 Silicon Content Technology Co., Ltd. All Rights Reserved 23 Product Folder Links: SCT2650 T APE AND REEL INFORMATION Orderable Device Package Type Pins SPQ SCT2650STER ESOP 8 4000