SCG51

SCG51 CONNOR-WINFIELD | Alldatasheet

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Technical content

Features

• 3.3V High Precision PLL  Tri-State Capability  Active Low Alarm  Guaranteed Free Run ±20ppm  1 sec. Acquisition Time  1 CMOS Output  3 LVPECL Outputs SCG51 Synchronous Clock Generators PLL 211 1 Comprehensive Drive Aurora, Illinois 60505 Phone: 630- 851- 4722 Fax: 630- 851- 5040 www.conwin.com Bulletin SG079 Page 1 of 14 Revision 00 Date 08 Sept 04 Issued By MBatts

Data Sheet #: SG079 Page 2 of 14 Rev: 00 Date: 09/08/04 © Copyright 2004 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Parameter Specifications Notes Input Logic CMOS Input Frequency Range 8 kHz - 176 MHz Alarms Active Low, Combined LOR/LOL VCXO Output Logic Type LVPECL (3x) Reference Output Logic Type CMOS (1x) General Description The SCG51 Series is a phase locked loop generating LVPECL outputs from an intrinsically low jitter voltage controlled crystal oscillator. The LVPECL and CMOS outputs may be disabled. The unit has an acquisition time of about 1 second and it is tolerant of different reference duty cycles. Further features include a combined LOL/LOR alarm output for Loss-of-Reference (LOR) and Loss-of-Lock (LOL). During the LOR alarm, the SCG51 will also enter a Free Run state, which will guarantee a 20 ppm accurate output. Additionally the Free Run mode may be entered manually. The alarms and reference output may be put into the tri-state high impedance condition for external testing purposes. The maximum package dimensions are 1.35” x 1.0” x 0.40” on a 6 layer FR4 board with castellated pins. Parts are assembled using high temperature solder to withstand 63/37 alloy, 180° C surface mount reflow processes. Functional Block Diagram Figure 1 Divider Divider Alarm Detection Analog Filter Free Run Control Buffer/ Divider VCXO Alarm Output (Pin 1) Force Free Run (Pin 19) Reference Input (Pin 2) Tri-State / Enable (Pin 20) (Pin 11) (Pin 12) (Pin 9) (Pin 10) (Pin 5) (Pin 6) (Pin 15) 10 kΩ 10 kΩ 33 Ω

Data Sheet #: SG079 Page 3 of 14 Rev: 00 Date: 09/08/04 © Copyright 2004 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice NOTES: 1.0: Requires external regulation and filter (22uF , 330 pF) 2.0: Offset change between Reference Input and Reference Output over temperature range. Operating Specifications Table 2 Symbol Parameter Minimum Nominal Maximum Units Notes Vcc Power Supply Voltage 3.135 3.3 3.465 Volts 1.0 Icc Power Supply Current - 260 - mA To T emperature Range 0 - 70 °C Ffr Free Run Accuracy -20 - 20 ppm Fcap Capture/pull-in range -25 - 25 ppm Fbw Jitter Filter Bandwidth - - 15 Hz TDEV Time Deviation - 70 - ps MTIE Maximum Time Interval Error - 800 - ps Static Offset - - 37 ns Dynamic Offset Range (0°- 70°) -20 - 20 ns 2.0 Dynamic Offset Range (25°- 70°) -15 - 15 ns 2.0 Φgain Phase Gain - - 0.2 dB@~0.5Hz Tjtol Input Jitter T olerance - - 31.25 µs taq Typical Acquisition Time Data Acquisition from a cold power-up: Phase lock within 12ns: 6 sec. Phase lock settled: 25 sec. Alarm time: 1 sec. Acquisition from Free Run: Phase lock within 12ns: 6 sec. Phase lock settled: 25 sec. Alarm time: 1 sec. Frequency lock with a 20PPM reference frequency step: Typically 0.5s. Absolute Maximum Rating Table 1 Symbol Parameter Minimum Nominal Maximum Units Notes Vcc Power Supply Voltage -0.3 3.8 Volts V1 Input Voltage -0.5 5.5 Volts Ts Storage Temperature -40 85 deg. C

Data Sheet #: SG079 Page 4 of 14 Rev: 00 Date: 09/08/04 © Copyright 2004 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Output Jitter Specifications Table 6 Jitter BW 10 Hz - 20 MHz SONET Jitter BW 12 kHz - 20 MHz Frequency (MHz) pS (RMS) m UI pS (RMS) m UI 155.52 (PECL) 10(typical) 1.55 (typical) 1 (max) 0.156 (max) 77.76 (PECL) 10(typical) 0.77 (typical) 1 (max) 0.077 (max) 77.76 (CMOS) 15(typical) 1.16 (typical) 3 (max),0.4 (typical) 0.467 (max) LVPECL Output Characteristics Table 5 Symbol Parameter Minimum Nominal Maximum Units Notes fOUT Available LVPECL Output Frequencies 4.86 155.52 MHz 3 VOH High Level LVPECL Voltage V CC-1.085 - V CC-0.88 V VOL Low Level LVPECL Voltage V CC-1.83 - V CC-1.62 V CL Output Capacitance 3 pF TSKEW Differential Output Skew 280 ps TR/TF Rise/Fall Time (20%-80%) 0.35 1 ns DC Positive Duty Cycle 45 55 % ISAVINGS Current Savings per Unloaded PECL Pair 20 mA CMOS Input And Output Characteristics Table 4 Symbol Parameter Minimum Nominal Maximum Units Notes fOUT Available CMOS Output Frequencies 8 k 155.52 M Hz 3 VIH High Level Input Voltage 2 5.5 V VIL Low Level Input Voltage 0 0.8 V TIO I/O to Output Valid 10 nS CO Output Capacitance 10 pF VHO High Level Output Voltage loh = 04mA 2.4 Vcc Min. VIO Low Level Output Voltage lo1 = 6mA 0.5 Vcc Max. TIR Input Reference Signal Pulse Width 12.5 nS DC Positive Duty Cycle 40 60 % 4 NOTES: 3.0: Refer to the available frequency combination tab le in the Ordering Information Section on page 8. 4.0: If the CMOS output is an even divide of Y 0, then its duty cycle will be ~50%.

Data Sheet #: SG079 Page 5 of 14 Rev: 00 Date: 09/08/04 © Copyright 2004 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Pin Description Table 7 Pin # Connection Description

1 Alarm Output Active Low, Combined LOR/LOL Alarm Output

2 Reference Input CMOS Reference Frequency Input

3 TDO JTAG pin that is used only by Connor-Winfield for programming. Do not connect

4 N/C No Connection

5 Y2 Positive Differential LVPECL Output

6 Y2 Negative Differential LVPECL Output

7 V CC 3.3V Supply Voltage.

8 GND Power Ground

9 Y1 Positive Differential LVPECL Output

10 Y1 Negative Differential LVPECL Output

11 Y0 Positive Differential LVPECL Output

12 Y0 Negative Differential LVPECL Output

13 GND Power Ground

14 V CC 3.3V Supply Voltage.

15 Y3 CMOS Reference Output

16 TDI JTAG pin that is used only by Connor-Winfield for programming. Do not connect 17 TCK JTAG pin that is used only by Connor-Winfield for programming. Do not connect 18 TMS JTAG pin that is used only by Connor-Winfield for programming. Do not connect

19 Force Free Run Force output frequency to Free Run (FR = 1, Default = 0)

20 Tri-State/Enable Enable = 0, Disable = 1 for VCXO Ouputs, Default = 0 (for No Connect)

V CC GND Alarm Output Force Free Run TMS TCK TDI V CC GND Tri-State/Enable

Data Sheet #: SG079 Page 6 of 14 Rev: 00 Date: 09/08/04 © Copyright 2004 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Phase Detector (Internal Signal) External Reference (Selected Input A or B) Internal Reference (Internal Signal) 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Start-up Region 1 1 Alarm Output (LOR + LOL) Loss of Reference Condition Alarm Timing Figure 8 AlarmTiming Legend Use for all alarm timing diagrams Table 7 Start-up Region 8 kHz Reference Input < 31.25 µsec > 31.25 µsec 31.25 µsec2 4 Minimum pulse width = 62.5 µsec During Start-up, The LOL Alarm will pulse during the first few seconds of operation

Data Sheet #: SG079 Page 10 of 14 Rev: 00 Date: 09/08/04 © Copyright 2004 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Recommended PECL Termination Figure 16 50Ω SCG51 LVPECL OUTPUT Q QN Vcc GND 50Ω Transmission Line

3.3 VDC

82Ω 50Ω Transmission Line LVPECL INPUT D DN Vcc GND Q QN Vcc GND LVPECL INPUT D DN Vcc GND 50Ω 130Ω 82Ω D DN Vcc GND 50Ω Transmission Line 50Ω Transmission Line Q QN Vcc GND Vcc - 2 VDC Vcc - 2 VDC 100Ω 50Ω Transmission Line 50Ω Transmission Line 130Ω 150Ω 150Ω If PECL outputs do not drive a long line (< 0.5”), a single 150Ω termination resistor to ground may be used for each pin.

Data Sheet #: SG079 Page 12 of 14 Rev: 00 Date: 09/08/04 © Copyright 2004 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Solder Profile Figure 18 Temp 100 150 200 250 12345678 Time(minutes) (C˚) Recommended Reflow Profile Peak Temp:217C˚ MaxRiseSlope:1.5C˚/Sec Time Above150C˚:100Sec

Data Sheet #: SG079 Page 13 of 14 Rev: 00 Date: 09/08/04 © Copyright 2004 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice

Ordering Information

Please contact Connor-Winfield for other frequencies that may be available. SCG51- G A A B B Reference Input Frequency PECL Output Frequency for Y0 & Y0 and Internal VCXO PECL Output Frequency for Y 1 & Y1 PECL Output Frequency for Y 2 & Y2 CMOS Output Frequency for Y A = 155.52 MHz B = 77.76 MHz C = 38.88 MHz D = 9.72 MHz E = 4.86 MHz F = 19.44 MHz G = 8 kHz H = 128 MHz N = No Output (High-Z) * Other Y3 frequencies may be available. Please contact a sale representative for availability . Currently Available Internal VCXO Frequencies

155.56 MHZ Y0 Y1 Y2 Y3* Y0 Y1 Y2 Y3*

7 7 . 7 6 M H z ÷ 1÷ 1÷ 1 H i g h - Z÷ 1÷ 8÷ 8÷ 4 ÷ 1 High-Z High-Z ÷ 4 ÷ 1 High-Z ÷ 16 ÷ 4 ÷ 1 ÷ 1 High-Z ÷ 4 ÷ 1 ÷ 1 ÷ 16 ÷ 4 ÷ 1 ÷ 2 High-Z ÷ 4 ÷ 1 ÷ 2 ÷ 16 ÷ 4 ÷ 1 ÷ 4 High-Z ÷ 4 ÷ 1 ÷ 4 ÷ 16 ÷ 4 ÷ 1 ÷ 8 High-Z ÷ 4 ÷ 1 ÷ 8 ÷ 16 ÷ 4 ÷ 1 High-Z ÷ 1 ÷ 4 ÷ 1 High-Z High-Z ÷ 1 ÷ 1÷ 1÷ 1÷ 4 ÷ 1÷ 1 H i g h - Z ÷ 1 ÷ 1÷ 2÷ 1÷ 4 ÷ 1÷ 2 H i g h - Z ÷ 1 ÷ 1÷ 4÷ 1÷ 4 ÷ 1÷ 1 H i g h - Z ÷ 2 ÷ 1÷ 8÷ 1÷ 4 ÷ 1÷ 2 H i g h - Z ÷ 2 ÷ 1 High-Z ÷ 2 ÷ 4 ÷ 1 High-Z High-Z ÷ 2 ÷ 1÷ 8÷ 2÷ 4 ÷ 1÷ 4 H i g h - Z ÷ 1 ÷ 1 High-Z ÷ 4 ÷ 4 ÷ 1 ÷ 8 High-Z ÷ 1 ÷ 1÷ 1÷ 4÷ 4 ÷ 1÷ 4 H i g h - Z ÷ 2 ÷ 1÷ 2÷ 4÷ 4 ÷ 1÷ 8 H i g h - Z ÷ 2 ÷ 1÷ 8÷ 4÷ 4 ÷ 1 H i g h - Z H i g h - Z ÷ 8 ÷ 1 High-Z ÷ 8 ÷ 4 ÷ 1 ÷ 4 High-Z ÷ 8 ÷ 1÷ 2÷ 8÷ 4 ÷ 1÷ 8 H i g h - Z ÷ 8 Available Output Frequencies Based on Internal VCXO Available Output Frequencies Based on Internal VCXO (Continued)

Aurora, Illinois 60505 Phone: 630-851-4722 Fax: 630- 851- 5040 www.conwin.com Revision Revision Date Note 00 9/8/04 Final Release