SCG4521

SCG4521 CONNOR-WINFIELD | Alldatasheet

Document overview

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• PDF pages: 16

Technical content

Features

• Dual 19.44 MHz Input References
• Primary 155.52 MHz LVPECL Outputs with Disable Function
• Secondary 51.84 MHz CMOS Output
• Phase Locked Output Frequency Control
• Intrinsically Low Jitter Crystal Oscillator
• LOR & LOL Alarm
• Force Free Run Function
• Automatic Free Run operation on loss of both References A & B
• Input Duty Cycle Tolerant
• 3.3V dc Power Supply
• Small Size: 1 Square Inch SCG4521 Synchronous Clock Generators PLL

2111 Comprehensive Drive

Aurora, Illinois 60505 Phone: 630-851-4722 Fax: 630-851-5040 www.conwin.com Bulletin SG036 Page 1 of 16 Revision A02 Date 25 Oct 01 Issued By MBatts

Advance Data Sheet #: SG036 Page 2 of 16 Rev: A02 Date: 10/25/01 © Copyright 2001 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice

8 KHz PHASE

Q QN 1 / N ALARM LOW JITTER

155.52 MHz

The SCG4521 is a mixed-signal phase locked loop generating LVPECL outputs from an intrinsically low jitter, voltage controlled, crystal oscillator. The LVPECL outputs may be disabled. The SCG4521 can lock to one of two external references, which is selectable using the SEL AB input select pin. The unit has a fast acquisition time of about 1.5 seconds and it is tolerant of different reference duty cycles. The SCG4521 provides two types of output logic. The primary output is a differential LVPECL output at 155.52 MHz. The secondary output is a CMOS output at 51.84 MHz that is derived from the LVPECL output. Both outputs are phase aligned to the selected input reference. The SCG4521 includes an alarm output that indicates deviations from normal operation. If a Loss- of-Reference (LOR) or Loss-of-Lock (LOL) is detected the alarm with indicate the need for a reference rearrangement. If both references A and B are absent the module will enter Free Run operation. The FR status pin will indicate that the module is in Free Run operation. Frequency stability during Free Run operation is guaranteed to ±20 ppm. Additionally the Free Run mode may be entered manually. The package dimensions are 1” x 1” x .45” on a 6 layer FR4 board with castellated pins. Parts are assembled using high temperature solder to withstand 63/37 alloys, 180°C surface mount reflow processes. Package Outline Figure 1 Block Diagram Figure 2

Advance Data Sheet #: SG036 Page 3 of 16 Rev: A02 Date: 10/25/01 © Copyright 2001 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice NOTES: 1.0 Operation of the device at these or any other condition beyond those listed under Operating Specifications is not implied. Exposure to Absolute Maximum Rating conditions for extended periods of time may affect device reliability. 2.0 Requires external regulation and supply decoupling. (22 uF , 330 pF) 3.0 3db loop response. 4.0 From a 20 PPM step in reference frequency at 25°C @ 3.3V 5.0 50-ohm load biased to 1.3 volts. 6.0 Jitter based on SONET OC-48 bandwidth. (12KHz to 20 MHz) 7.0 Entry into Free Run doesn’t meet requirement for initial 2.33 seconds of self-timing. 7.1 If the selected reference is removed system response to the ALARM must be less than 10µs. Absolute Maximum Rating Table 1 Symbol Parameter Minimum Nominal Maximum Units Notes Vcc Power Supply Voltage -0.5 - +4.0 Volts 1.0 Vi Input Voltage -0.5 - +5.5 Volts 1.0 Ts Storage Temperature -65.0 - +100 °C 1.0 Operating Specifications Table 2 Symbol Parameter Minimum Nominal Maximum Units Notes Vcc Power Supply Voltage 3.135 3.3 3.465 Volts 2.0 Icc Power Supply Current 170 250 320 mA 5.0 To Temperature Range 0 - 70 °C FREF External Reference Frequency 19.44 MHz Ffr Free Run Frequency -20 - 20 ppm FLV LVPECL Differential Output Frequency 155.52 MHz FCM CMOS Output Frequency 51.84 MHz Fcap Capture/pull-in range -25 - 25 ppm Fbw Jitter Filter Bandwidth - - 10 Hz 3.0 Tjtol Input Jitter Tolerance - - 6.25 µs Taq Acquisition Time - 1 - s 4.0 Trf Output Rise and Fall Time (20% 80%) 100 225 350 ps 5.0 LVDC LVPECL Output Duty Cycle 40 60 % CMDC CMOS Output Duty Cycle 40 60 % LVS LVPECL Output Jitter (OC-48) <1 psRMS 6.0 CMS CMOS Output Jitter 3 5 psRMS 6.0 MTIEsr MTIE at Synchronization Rearrangement GR-253-CORE.1999 R5-136 7.0, 7.1

Advance Data Sheet #: SG036 Page 4 of 16 Rev: A02 Date: 10/25/01 © Copyright 2001 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice NOTES: A Active FR Free Run Mode NA Not Active RA Locked to Reference A RB Locked to Reference B U Unstable (due to conditions shown, switch to active reference or Free Run) X Don ’t care Input And Output Characteristics Table 3 Symbol Parameter Minimum Nominal Maximum Units Notes CMOS Input and Output Characteristics Vih High Level Input Voltage 2.0 - 5.5 V Vil Low Level Input Voltage 0.0 - 0.8 V Tio I/O to Output Valid - - 10 ns Cl Output Capacitance - - 10 pF Voh High Level Output Voltage 2.4 - - V Vol Low Level Output Voltage - - 0.4 V Tir Input Reference Pulse Width 12.5 - - ns PECL Output Characteristics Voh High Level PECL Voltage 2.27 2.34 2.52 V Vol Low Level PECL Voltage 1.49 1.51 1.68 V Cl Output Capacitance - - 10 pF Tskew Differential Output Skew - 50 - ps Input Selection / Output Response Table 4 INPUTS OUTPUTS NOTE RESET ENABLE SEL AB REFA REFB FR FR status ALARM Q QN 1 0 XXXX 1 X X X F R X 1 XXXX X X 0 1 0 0 XXX1 1 X X X F R 00 0 A A 0 0 0 X X R A 00 1 A A 0 0 0 X X R B 00 0 N A A 0 0 1 X X U 00 1 N A A 0 0 0 X X R B 00 1 A N A 0 0 1 X X U 00 0 A N A 0 0 0 X X R A

00 X N A N A 0 1 1 X X F R

Advance Data Sheet #: SG036 Page 6 of 16 Rev: A02 Date: 10/25/01 © Copyright 2001 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Typical MTIE at Synchronization Rearrangement. Reference B Equal to Inverse of Reference A, No Modulation. Figure 5

Advance Data Sheet #: SG036 Page 7 of 16 Rev: A02 Date: 10/25/01 © Copyright 2001 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Pin Description Table 5 Pin # Pin Name Pin Information Note 1 ENABLE VCXO Enable. (Enable = 0, Disable = 1) 9.0 2 TCK No Connection, Internal Factory Programming Input. 8.0 3 TDO No Connection, Internal Factory Programming Input. 8.0 4 REF A CMOS Reference Frequency Input. (19.44 MHz) 5 SEL AB Input Reference Select Pin. (REFA = 0, REFB = 1) 9.0 6 RESET RESET. (RESET = 1) 9.0 7 REF B CMOS Reference Frequency Input. (19.44 MHz) 8V ee Ground. 9F R status Free Run Status. (FR = 1) 10 V cc Supply Voltage relative to ground. 11 CMOS Output CMOS Output (51.84 MHz) 12 ALARM Loss of Reference / Lock alarm. (Alarm = 1) 13 FR Force Free Run. (Phase Lock = 0, Free Run = 1) 9.0 14 TDI No Connection, Internal Factory Programming Input. 8.0 15 TMS No Connection, Internal Factory Programming Input. 8.0 16 QN LVPECL Complementary Output. 17 V ee Ground. 18 Q LVPECL Output. Circuit Board Footprint Recommendations Figure 6 NOTES

8.0 Do not connect pin

9.0 Input pulled to ground

Advance Data Sheet #: SG036 Page 10 of 16 Rev: A02 Date: 10/25/01 © Copyright 2001 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Switch from A to B when B is out of range Figure 11 Ref A Ref B Alarm SEL A/B Switch from A to B when B is out of range New Reference Qualification time Out of Range In Range Alarm Blanked

Advance Data Sheet #: SG036 Page 11 of 16 Rev: A02 Date: 10/25/01 © Copyright 2001 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Recommended PECL Termination Figure 12 SCGxxx LVPECL OUTPUT Q QN Vcc GND

50 OHM Transmission Line

3.3 VDC

D DN Vcc GND Vcc - 2 VDC Q QN Vcc GND LVPECL INPUT D DN Vcc GND 130 D DN Vcc GND Q QN Vcc GND Vcc - 2 VDC 100

50 OHM Transmis sion Line

If PECL outputs do not drive a long line (< 0.5 ”), a single 150 Ω termination resistor to ground may be used for each pin.

Advance Data Sheet #: SG036 Page 12 of 16 Rev: A02 Date: 10/25/01 © Copyright 2001 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Tape and Reel Packaging Figure 13

Advance Data Sheet #: SG036 Page 13 of 16 Rev: A02 Date: 10/25/01 © Copyright 2001 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Solder Profile Figure 14 Temp 100 150 200 250 12345678 Time(minutes) (C˚) Recommended Reflow Profile Peak Temp:217C˚ MaxRiseSlope:1.5C˚/Sec Time Above150C˚:100Sec

Advance Data Sheet #: SG036 Page 14 of 16 Rev: A02 Date: 10/25/01 © Copyright 2001 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice

Advance Data Sheet #: SG036 Page 15 of 16 Rev: A02 Date: 10/25/01 © Copyright 2001 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice

Data Sheet #: SG036 Page 16 of 16 Rev: A02 Date: 10/25/01 © Copyright 2001 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Revision Revision Date Note A00 9/4/01 Advance Information Release A01 10/9/01 Changed PECL phase noise spec and max current spec. A02 10/25/01 Added input reference frequency to table 2