SC9270C SILAN | Alldatasheet
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Semiconductors/G3 SC9270C/D /G3 HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD /G3 Rev: 1.1 2001.04.27 DTMF RECEIVER
DESCRIPTION
The SC9270C/D is a complete DTMF receiver integrating both the bandsplit filter and digital decoder functions. The filter section uses switched capacitor techniques for high- and low-group filters and dial-tone rejection. Digital counting techniques are employed in the decoder to detect and decode all 16 DTMF tone-pairs into a 4-bit code. External component count is minimized by on-chip provision of a differential input amplifier, clock-oscillator and latched 3-state bus interface.
FEATURES
*Complete receiver in an 18-pin package *Excellent performance *CMOS, single 5 volt operation, *Widely operating voltage: 1.2V ~ 5.25V *Minimum board area *Central office quality *Low power consumption *Power-Down mode (SC9270D only) *Inhibit-mode (SC9270D only) DIP-18 /G3
APPLICATIONS
*Paging systems *Repeater systems / Mobile radio *Credit card systems *Remote control *Personal computers PIN CONFIGURATIONS SC9270C IN+ IN- GS VREF IC* IC* OSCI OSCO Q1 VDD St/GT ESt StD VSS TOE * Connect to VSS SC9270D IN+ IN- GS VREF INH PWDN OSCI OSCO Q1 VDD St/GT ESt StD VSS TOE
Figure 1. block diagram Note: 1. Absolute maximum ratings are those values beyond which damage to the device may occur.
- Unless otherwise specified, all voltages are referenced to ground.
- Power dissipation temperature derating: -12 mV / from 65°C to 85°C
Note: 1. Voltages are with respect to ground(Vss), unless otherwise stated. 2 .Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
Semiconductors/G3 SC9270C/D /G3 HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD /G3 Rev: 1.1 2001.04.27 DC ELECTRICAL CHARACTERISTICS Parameter Symbol Conditions Min Typ Max Unit SUPPLY Operating Supply Voltage V DD -- 1.2 -- 5.25 V Operating Supply Current I CC -- -- 3.0 7.0 mA Power Consumption P O f=3.579MHz; VDD =5V -- 15 35 mW Standby Current I S PWDN pin = VDD -- -- 100 mA INPUTS Low Level Input Voltage V IL -- -- -- 1.5 V High Level Input Voltage V IH - - 3 . 5 - -- -V Input Leakage Current I IH/IIL VIN=V SS or VDD -- 0.1 -- mA Pull up(Source) Current I SO TOE(Pin 10)=0V -- 7.5 15 mA Input Impedance (IN+, IN-) R IN @1kHz -- 10 -- M W Steering Threshold Voltage V TSt -- -- 2.35 -- V OUTPUTS Low Level Output Voltage V OL No load -- 0.03 -- V High Level Output Voltage V OH No load -- 4.97 -- mA Output Low(Sink) Current I OL VOUT =0.4V 1.0 2.5 -- mA Output High(Source) Current I OH VOUT =4.6V 0.4 0.8 -- mA VREF Output Voltage V REF No load 2.4 -- 2.7 V VREF Output Resistance R OR -- -- 10 -- kW OPERATING CHARACTERISTICS Gain Setting Amplifier Parameter Symbol Conditions Min Typ Max Unit Input Leakage Current I IN VSS <V IN <V DD -- –100 -- nA Input Resistance R IN -- -- 10 -- M W Input Offset Voltage V OS -- -- –25 -- mV Power Supply Rejection PSRR 1kHz -- 60 -- dB Common Mode Rejection CMRR -3.0V < V IN < 3 . 0 V - -6 0 - -d B DC Open Loop Voltage Gain A VOL -- -- 65 -- dB Open Loop Unity Gain Bandwidth fC -- -- 1.5 -- MHz Output Voltage Swing V O R L‡100kW to VSS -- 4.5 -- V PP Tolerable capacitive load(GS) C L -- -- 100 -- PF Tolerable resistive load(GS) R L -- -- 50 -- kW Common Mode Range V CM No load -- 3.0 -- V PP Notes : 1. All voltages referenced to VDD unless otherwise noted. 2. VDD =5 . 0 V ,VSS =0 V ,TA = 25°C .
Semiconductors/G3 SC9270C/D /G3 HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD /G3 Rev: 1.1 2001.04.27 AC CHARACTERISTICS (All voltage referenced to Vss otherwise noted; VDD =5.0V, VSS =0V, TA=25°C, fCLK =3.579545 MHz, using test circuit of figure 2 & 3. Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing) Parameter Symbo l Test Conditions Min Typ Max Unit SIGNAL CONDITIONS Valid Input Signal Levels (each tone of composite signal) Positive Twist Accept -- Note:2,3,6,9,11 -- 10 -- dB Negative Twist Accept -- Note:2,3,6,9,11 -- 10 -- dB Frequency Deviation Accept Limit -- Note:2,3,5,9,11 -- ±1.5%±2Hz -- Frequency Deviation Reject Limit -- Note:2,3,5,11 ±3.5 -- -- Thrid Tone Tolerance -- Note:2,3,4,5,9,13 -18.5 -- dB Noise Tolerance -- Note:2,3,4,5,7,9,10 -- -12 dB Dial Tone Tolerance -- Note:2,3,4,5,8,9,11 -- +18 -- dB TIMING Tone Present Detection Time t DP Refer to Fig. 4. Note:12 5 14 16 ms Tone Absent Detection Time t DA Refer to Fig. 4. Note:12 0.5 4 8.5 ms Tone Duration Accept t REC User adjustable -- -- 40 ms Tone Duration Reject t REC User adjustable 20 -- -- ms Interdigit Pause Accept t ID User adjustable -- -- 40 ms Interdigit Pause Reject t DO User adjustable 20 -- -- ms OUTPUTS Propagation Delay (St to Q) t PQ TOE=V DD -- 8 11 ms Propagation Delay (St to StD) t PSED TOE=V DD -- 12 -- ms Output Data Set Up (Q to Std) t QSED TOE=V DD -- 4.5 -- ms Propagation Delay (TOE to Q Enable) tPTE R L=10kW ,C L=50pf -- 50 -- ns Propagation Delay (TOE to Q Disable) tPTD R L=10kW ,C L=50pf -- 300 -- ns CLOCK Crystal/Clock Frequency f C -- 3.5759 3.5759 3.581 MHz Clock Input Rise Time t LHCL Ext. clock -- -- 110 ns Clock Input Fall Time t HLCL Ext. clock -- -- 110 ns Clock Input Duty Time DC CL Ext. clock 40 50 60 % Capacitive Load (OSCO) C LO -- -- -- 30 pf Notes: 1. dBm = decibels above or below a reference power of 1mW into a 600 Ohm load. 2. Digit sequences consists of all 16 DTMF tones.
Semiconductors/G3 SC9270C/D /G3 HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD /G3 Rev: 1.1 2001.04.27 PIN DESCRIPTION Pin No. Pin Name I/O Description
1 IN+ I Non-Inverting input
2 IN- I Inverting input
Connections to the front-end differential amplifier. 3G S - - Gain select. Gives access to output of front-end differential amplifier for connection of feedback resistor. 4V REF O Reference voltage output, nominally VDD /2. May be used to bias the inputs at mid-rail (see application diagram). 5I N H I Inhibit (input) logic high inhibit the detection of 1633Hz internal built-in pull down resistor. (SC9270D only). (For SC9270C, this pin must be tied to VSS ) 6P W D N I Power down (input). Active high power down the device and inhibit the oscillator internal built-in pull down resistor. (SC9270D only). (For SC9270C, this pin must be tied to V SS )
7 OSC1 I Clock Input
8 OSC2 O Clock Output
3.579545MHz crystal connected between these pins completes internal oscillator. 9V SS -- Negative power supply, normally connected to 0V.
10 TOE I
3-state data output enable. Logic high enables the outputs Q1-Q4. This pin is Internally pulled up. 11~14 Q1 ~ Q4 O 3-state data outputs. When enabled by TOE, provide the code corresponding to the last valid tone-pair received (see Table 1). When TOE is logic low, the data outputs are high impedance.
15 StD O
Delayed steering output. Presents a logic high when a received tone-pair has been registered and the output latch updated; returns to logic low when the voltage on St/GT falls below VTSt.
16 ESt O
Early steering output. Presents a logic high immediately when the digital algorithm detects a recognizable tone-pair (signal condition). Any momentary loss of signal condition will cause ESt to return to a logic low.
17 St/GT I/O
Steering input/guard time output (bi-directional). A voltage greater than VTSt detected at St causes the device to register the detected tone-pair and update the output latch. A voltage less than VTSt frees the device to accept a new tone- pair. The GT output acts to reset the external steering time-constant; its state is a function of ESt and the voltage on St. 18 V DD -- Positive power supply.
Figure 4. Timing diagram A. Short tone bursts: detected. Tone duration is invalid. C. End of tone #n is detected and validated. D. 3 State outputs disabled (high impedance). E. Tone #n + 1 is detected. Tone duration is valid. tone #n + 1 does not negister at outputs. G. End of tone #n + 1 is detected and validated. Vin: DTMF composite input signal. tID: Minimum time between valid DTMF signals. tDP : Time to detect the presence of valid DTMF signals. tDP : Time to detect the absence of valid DTMF signals. tGTP : Guard Time, Tone present. tGTP : Guard Time, Tone absent.
Semiconductors/G3 SC9270C/D /G3 HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD /G3 Rev: 1.1 2001.04.27 FUNCTION DESCRIPTIONS The SC9270C/D monolithic DTMF receiver offers small size, low power consumption and high performance. Its architecture consists of a bandsplit filter section, which separates the high and low tones of receiver pair, followed by a digital counting section which verifies the frequency and duration of the received tones before passing the corresponding code to the output bus. 1. FILTER SECTION Separation of the low-group and high-group tones is achieved by applying the dual tone signal to the inputs of two filters a sixth order for the high group and an eighth order for the low group. The bandwidths of which correspond to the bands enclosing the low-group and high-group tones (see table 1). The filter section also in corporates notches at 350Hz and 440 Hz for exceptional dial-tone rejection. Each filter output is followed by a second-order switched- capacitor section which smooth the signals prior to limiting. Limiting is performed by high-gain comparators which are provided with hysteresis to prevent detection of unwanted low-level signals and noise; the outputs of the comparators provide full-rail logic swings at the frequencies of the incoming tones. Flow Fhigh KEY TOE Q4 Q3 Q2 Q1 697 1209 1 H 0 0 0 1 697 1336 2 H 0 0 1 0 697 1477 3 H 0 0 1 1 770 1209 4 H 0 1 0 0 770 1336 5 H 0 1 0 1 770 1477 6 H 0 1 1 0 852 1209 7 H 0 1 1 1 852 1336 8 H 1 0 0 0 852 1477 9 H 1 0 0 1 941 1336 0 H 1 0 1 0 941 1209 * H 1 0 1 1 941 1477 # H 1 1 0 0 697 1633 A H 1 1 0 1 770 1633 B H 1 1 1 0 852 1633 C H 1 1 1 1 941 1633 D H 0 0 0 0 -- -- ANY L Z Z Z Z L=LOGIC LOW, H=LOGIC HIGH, Z=HIGH IMPEDANCE Table 1: Function decode table
allows the designer to tailor performance to meet a wide variety of system requirements. drop - outs would be required. Design information for guard-time adjustment is shown in Fig.7. Figure 7. Guard time adjustment
(VREF ) which is used to bias the inputs at mid-rail. VREF biasing the input at 1/2VDD . Fig.8 shows the differential configuration, which permits the adjustment of gain with the feedback resistor R5. Figure 8. Differential input configuration
- POWER – DOWN AND INHIBIT MODE
stops the oscillator and the functions of the filters. will remain the same as the previous detected code (see table 2).
Semiconductors/G3 SC9270C/D /G3 HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD /G3 Rev: 1.1 2001.04.27 6. CRYSTAL OSCILLATOR The internal clock circuit is completed with the addition of an external 3.579545MHz crystal and is normally connected as shown in Figure 2. However, it is possible to configure several SC9270C/D devices employing only a single oscillator crystal. The oscillator output of the first device in the chain is coupled through a 30pF capacitor to the oscillator input (OSCI) of the next device. Subsequent devices are connected in a similar fashion. Refer to Figure 9 for details. The problems associated with unbalanced loading are not a concern with the arrangement shown, ie: precision balancing capacitors are not required. C C X-tal OSCO OSCI OSCI OSCO c=30pF X-tal=3.579545MHz To OSCI of next SC9270C/D Figure 9 Oscillator Connection PACKAGE OUTLINE DIP-18-300-2.54 UNIT: mm 6.40 2.54 3.51 5.083.30 7.62 0.25 15 degree 0.46 22.95 1.50 /G3