SC9256

SC9256 SILAN | Alldatasheet

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/G3 HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD /G3 REV: 1.0 2002.01.30. PLL FOR DTS

DESCRIPTION

The SC9256 is phase-locked loop (PLL) LSIs for digital tuning systems (DTS) with built in 2 modulus prescalers. All functions ate controlled through 3 serial bus lines. These LSIs are used to configure high-performance digital tuning system.

FEATURES

• Optimal for configuring digital tuning systems in high-fi tuners and car stereos. * built-in prescalers. Operate at input frequency ranging from 30~150 MHz during FMIN input (with 2 modulus prescaler) and at 0.5~40MHz during AMIN input (with 2 modulus prescaler or direct dividing). * 16 bit programmable counter, dual parallel output phase comparator, crystal oscillator and reference counter. * 3.6MHz, 4.5MHz, 7.2MHz or 10.8MHz crystal oscillators can be used. * 15 possible reference frequencies. ( When using 4.5MHz crystal) * Built-in 20 bit general-purpose counter for such uses as measuring intermediate frequencies (IF IN1 and IFIN2) * High-precision (±0.55~±7.15µs) PLL phase error detection. * Numerous general-purpose I/O pins for such uses as peripheral circuit control. * 3 N-channel open-drain output ports (OFF withstanding voltage:12V) for such uses as control signal output. DIP-16-300-2.54 SOP-16-300-1.27 * Standby mode function (turns off FM, AM and IF amps) to save current consumption. * All functions controlled through 3 serial bus lines. * CMOS structure with operating power supply range of V DD =5.0±0.5V.

ORDERING INFORMATION

SC9256 DIP-16-300-2.54 SC9256S SOP-16-300-1.27 PIN CONFIGURATION SC9256 XT XT PERIOD CLOCK DATA OT-1 OT-2 OT-3 DO2/OT-4 DO1 I/O-5/IF IN1 GND I/O-6/IFIN2 FM IN AM IN VDD

/G3 HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD /G3 REV: 1.0 2002.01.30. BLOCK DIAGRAM 1/2 2 MODULUS PERSCALER 4bit SWALLOW COUNTER 12bit PROGRAMMABLE COUNTER OSC CIRCUIT REFERENCE COUNTER MAX 24bit SHIFT REGISTER 24bit REGISTER ADDRESS DECODER 24bit REGISTER OUTPUT PORT 20bit BINARY COUNTER UNIVERSAL COUNTER CONTROL POWER ON RESET RESET PHASE COMPARATOR TRI-STATE BUFFER TRI-STATE BUFFER UNLOCK OT4 I/O PORT XT 1ms AMP AMP AMP FM L PSC VDD GND HFFM H 4 12 FM LF MODE 41ms OSC

8 TEST

ABSOLUTE MAXIMUM RATINGS (Ta=25°C) Characteristic Symbol Value Unit Supply Voltage V CC -0.3~6.0 V Input Voltage V IN -0.3~VDD +0.3 V N-ch Open-Drain Off withstanding Voltage V OFF 13 V Power Dissipation P D 300(200) mW Operating Temperature T OPR -40~85 °C Storage Temperature T STG -65~150 °C ( ): Flat package

/G3 HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD /G3 REV: 1.0 2002.01.30. ELECTRICAL CHARACTERISTICS (unless otherwise specified, Ta= -40~85°C, VDD =4.5~5.58V.) Characteristic Symbol Test Condition/Pin Min Typ. Max Unit Operating Power Supply Voltage VDD1 PLL operation (normal operating) 4.5 5.0 5.5 V Operating Power Supply Current IDD1 VDD =5.0V, XT=10.8MHz, FMIN=150MHz -- 7 15 mA Stand-by mode Crystal Oscillation Frequency Supply Voltage VDD2 PLL OFF (Operating crystal oscillation) 4.0 5.0 5.5 V Operating Power Supply Current IDD2 VDD =5.0V, XT =10.8MHz PLL OFF -- 0.8 1.5 mA Operating Power Supply Current IDD3 VDD =5.0V, XT stop, PLL OFF -- 120 240 µA Operating frequency range Crystal Oscillation Frequency fXT Connect crystal resonator to XT-XT terminal 3.6 ~ 10.8 MHz FM IN (FMH ,F ML)f FM FM H, FM L mode, VIN=0.2Vp-p 30 ~ 130 MHz FM IN (FML)f FML FM L mode, VIN=0.3Vp-p 30 ~ 150 MHz AM IN (HF) f HF HF mode, VIN=0.2Vp-p 1 ~ 40 MHz AM IN (LF) f LF LF mode, VIN=0.2Vp-p 0.5 ~ 20 MHz IFIN1,I FIN2 fIF VIN=0.2Vp-p 0.1 ~ 15 MHz SC IN fSC VIH=0.7VDD ,VIL=0.3VDD , square wave input. -- ~ 100 kHz Operating input amplitude range FM IN (FMH ,F ML) VFM FM H, FM L mode, fIN=30~130MHz 0.2 ~ V DD -0.5 Vp-p FM IN (FML)V FML FM L mode, fIN=30~150MHz 0.3 ~ V DD -0.5 Vp-p AM IN (HF) V HF HF mode, fIN=1~40MHz 0.2 ~ V DD -0.5 Vp-p AM IN (LF) V LF LF mode, fIN=0.5~20MHz 0.2 ~ V DD -0.5 Vp-p IFIN1,I FIN2 VIF FIN=0.1~15MHz 0.2 ~ V DD -0.5 Vp-p OT1~OT4 N-ch open drain Output Current “L” level I OL1 VOL =1.0V 5.0 10.0 -- mA OFF-leak Current I OEF VOFF =12V -- --- 2.0 µA (To be continued)

/G3 HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD /G3 REV: 1.0 2002.01.30. (Continued) Characteristic Symbol Test Condition/Pin Min Typ. Max Unit I/O-5~I/O-9, SCIN “H” level V IH1 0.7VDD ~V DDInput Voltage “L” level V IL1 0 ~ 0.3V DD V “H” level I IH VIH=5V -- -- 2.0Input Current “L” level I IL VIL=0V -- -- -2.0 µA “H” level I OH4 VOH =4.0V (expect SCIN) -2.0 -4.0 --Output Current “L” level I OL4 VOL =1.0V (expect SCIN)2 . 0 4 . 0- - mA PERIOD, CLOCK, DATA “H” level V IH2 0.8VDD ~V DDInput Voltage “L” level V IL2 0 ~ 0.2V DD V “H” level I IH VIH=5V -- -- 2.0Input Current “L” level I IL VIL=0V -- -- -2.0 µA “H” level I OH5 VOH =4.0V (DATA) -1.0 -3.0 --Output Current “L” level I OL5 VOL =1.0V (DATA) 1.0 3.0 -- mA DO1, DO2 “H” level I OH3 VOH =4.0V -2.0 -4.0 --Input Current “L” level I OL3 VOL =1.0V 2.0 4.0 -- mA Tri-State Lead Current I TL VTLH =5V, VTLL=0V -- -- ±1.0 µA XT “H” level I OH2 VOH =4.0V -0.1 -0.3 --Output Current “L” level I OL2 VOL =1.0V 0.1 0.3 -- mA Input feedback resistance “H” level Rf1 FMIN, AMIN, IFIN (Ta=25°C) 350 700 1400 Input Feedback Resistance “L” level Rf2 XT- XT (Ta=25°C) 500 1000 4000 kΩ PIN DESCRIPTION Pin No. Symbol Pin name Description Circuit diagram 1X T 2 XT Crystal oscillator pins Connects 3.6MHz, 4.5MHz, 7.2MHz or 10.8MHz crystal oscillator to supply reference frequency and internal clock XT XT VDD (To be continued)

/G3 HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD /G3 REV: 1.0 2002.01.30. (Continued) Pin No. Symbol Pin name Description Circuit diagram

3 PERIOD Period signal input

4 CLOCK Clock signal input

Serial I/O ports. These pins transfer data to and from the controller to set divisions and dividing modes, and to control the general-purpose counter and general-purpose I/O ports. Schmitt input DATA VDD Schmitt input CLOCK,PERIOD 6O T - 1 7O T - 2 8O T - 3 General-purpose output ports N channel open drain port pins, for such uses as control signal output. These pins are set to the OFF state when power is turned on. N-channel open drain

10 AMIN

11 FMIN

These pins input FM and AM band local oscillator signals by capacitor coupling. FM IN and AM IN operate at low amplitude. VDD I/O- 6/IFIN2 I/O-5 /IFIN1 General-purpose I/O ports/General- purpose counter frequency measurement input General-purpose I/O port input /output pins. Can be switched for use as input pins to measure general purpose counter frequencies. The frequency measurement function has such uses as measuring inter- mediate frequencies (IF). These pins feature built-in amps. Data are input by capacitor coupling. FM IN and AM IN operate at low amplitude. (note) Pins are set for input when power is turned on. VDD

15 DO1

16 DO2/OT-4

output (General- purpose output ports) These pins are for phase comparator tri-state output. DO1 and DO2 are output in parallel. VDD

12 GND

Power supply pinsApplies 5.0V±10%

/G3 HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD /G3 REV: 1.0 2002.01.30. FUNCTION DESCRIPTION Serial I/O ports As the block diagram shows, the functions are controlled by setting data in the 48 bits contained in each of the 2 sets of 24 bit registers. Each bit of data in these register is transferred through the serial ports between the controller and the DATA, CLOCK and PERIOD pins. Each serial transfer consists of a total of 32 bits, with 8 address bits and 24 data bits. Since all functions are controlled in units of registers, the explanation in this manual focuses on the 8 bit address and functions of each register. These registers consist of 24 bits and are selected by an 8 bit address. A list of the address assignment for each register is given below under register assignments. Register Address Contents of 24 bits No. of bit Input register 1 D0H PLL divisor setting Reference frequency setting PLL input and mode setting Crystal oscillator selection total 24 Input register 2 D2H General=purpose counter control (including lock detection bit control) I/O port and general-purpose counter switching bits I/O-5/CLK pin switching bit DO pin control Test bit I/O port control (also used as general-purpose counter input selection bits) Output data total 24 Output register 1 D1H General-purpose counter numeric data Not used total 24 Output register 2 D3H Lock detection data I/O port control data Output data Input data (undefined during output port selection) Not used total 24 When the PERIOD signal falls, the input data are latched in register 1 or register 2 and the function is performed. When the CLOCK signal falls for 9 time, the output data are latched in parallel in the output registers. The data are subsequently output serially from the data pin.

/G3 HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD /G3 REV: 1.0 2002.01.30. REGISTER ASSIGMENTS P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 R0 R1 R2 R3 MODE FM OSC1 OSC2 Programmable counter data Reference frequency code data Programmable counter mode Crystal oscillator selection bits G0 G1 -- IF1 IF2 O4C DOHZ RESET START XT -- -- M5 M6 O1 O2 O3 O4 -- -- O5 -- O6TEST Address=D0H LSB LSB Address=D2H (*2) Gate time select I/O port and general-purpose counter switching bits CLK bit DOHZ bit RESET bit START bit TEST bit Also used as general-purpose counter input selection bits I/O port control Output port output data Input registers f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 f15 f16 f17 f18 f19 BUSY OVER "0" "0" General-purpose counter data ENA- BLE UN LOCK PE1 PE2 PE3 "0" "0" "0" "0" 0 0 0 M5 M6 O1 O2 O3 O4 0 0 I5 0I 6"0" Address=D1H LSB Address=D3H Input registers Not used Lock detection data Not used I/O port control data Output data Input data When power is turned on, the input registers are set as shown below. 000000000 00000000000 0 000 Address=D0H LSB Address=D2H Input registers (*1) MSB Note: 1. Data are undefined. 2. Set data to “0” for test bit.

/G3 HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD /G3 REV: 1.0 2002.01.30. Serial transfer format The serial transfer format consists of 8 address bits and 24 data bits (Fig. 1). Addresses D0H~D3H are used. Start t3 t4 t5 t6 t7 End t1 t2 9 clock signal fall LSB MSB 8a d d r e s sb i t s 24 data bits (24bit register) PERIOD CLOCK DATA MSB LSB Fig.1

• Serial data transfer serial data are transferred in sync with the clock signal. In the idle state, the PERIOD, CLOCK and DATA pin lines are all set to “H” level. When the period signal is at “L” level, the falling of the clock signal initiates serial data transfer. Data transfer ceases when the period signal is set to “L” level when the clock signal is at “H” level. Once serial data transfer has begun, however, no more than 8 falls of the clock signal can occur during the time the period signal is at “L” level. Since the receiving side receives the serial data as valid data when the clock signal rises, it is effective for the sending side to produce output in sync with the clock signal fall. To receive serial data from the output registers (D1H, D3H), set the serial data output to high impedance after the 8 bit address is output but before the next clock signal falls. Data reception subsequently continues until the period signal becomes “L” level; data transfer ends just before the period signal rises. Therefore, the data pin must have an open-drain or tristate interface. Note: 1. when power is turned on, some internal circuit have undefined states. To set internal circuit states, execute a dummy data transfer before performing regular data transfer. 2. times t1~t8 have the following value: t1≥1.0µs t2≥1.0µs t3≥0.3µs t4≥0.3µs t5≥0.3µs t6≥1.0µs t7≥1.0µs t8≥0.3µs 3. Asterisks represent numbers taken from addresses, as in D*H.

/G3 HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD /G3 REV: 1.0 2002.01.30. Crystal oscillator pins (XT, XT ) As fig.2 shows, the clock necessary for internal operation is produced by connecting a crystal oscillator between capacitors. Use the crystal oscillator selection bit to select an oscillating frequency of 3.6MHz, 4.5MHz, 7.2MHz or 10.8MHz which matches that of the crystal oscillator used. LSB MSB Address D0H OSC1 OSC2 OSC1 OSC2 OSCILLATOR FREQUENCY 3.6MHz 4.5MHz 7.2MHz 10.8MHz Divider XT XT C CX'tal C=30pF Typ. Fig.2 Note: set to 3.6MHz (OSC1=”0” and OSC2=”0”) when power is turned on. The crystal is not oscillating at this time because the system is in standby mode. Reference counter (Reference frequency divider) The reference counter section consists of a crystal oscillator and a counter. A crystal oscillator frequency of 3.6MHZ, 7.2MHZ or 10.8MHZ can be selected .A maximum of 15 reference frequencies can be generated. 1. Setting reference frequency The reference frequency is set using bits R0~R3. LSB MSB Address D0H R3R2 R0 R1 R2 R3 0000 0001 0100 1100 0010 1010 0110 1110 REFERENCE FREQUENCY R0 R1 R2 R3 0001 1001 0101 1101 0011 1011 0111 1111

0.5 KHz

2.5 KHz

3.125 KHz

*3.90654 KHz 5K H z

6.25 KHz

*7.8125 KHz REFERENCE FREQUENCY 9K H z

10 KHz

12.5 KHz

25 KHz

50 KHz

100 KHz

Standby mode (*1) R1R0 /G3

/G3 HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD /G3 REV: 1.0 2002.01.30. Note: 1. Reference frequencies marked with an asterisk “*”can only be generated with a 4.5MHZ crystal oscillator. 2. (*1)Standby mode Standby mode occurs when bits R0,R1,R2,and R3 are all set to “1”.In standby mode, the programmable counter stops, and FM, AM and IF IN(when selected IFIN) are set to “amp off” state (pins at “L” level). This saves current consumption when the radio is turned off. The DO pins become high impedance during standby mode. During standby mode, the I/O ports (I/O-5~I/O-6) and output ports (OT1~OT4) can be controlled and the crystal oscillator can be turned on and off. 3.The system is set to standby mode when power is turned on. At this time, the crystal oscillator is not oscillating and the I/O ports are set to input mode. /G3 Programmable counter The programmable counter section consists of a 1/2 prescaler, a 2 modulus prescaler and a 4bit +12bit programmable binary counter. 1. Setting programmable counter 16 bits of divisor data and 2 bits, which indicate the dividing mode, are set in the programmable counter. (1) Setting dividing mode The FM and MODE bits are used to select the input pin and the dividing mode (pulses wallow mode or direct dividing mode). There are 4 possible choices, shown in the table below .Select one based on the frequency band used. LSB MSB Address D0H FM MODE MODE FM MODE LF HF FM L FM H DIVIDING MODE Direct dividing mode Pulse swallow mode 1/2 + pulse swallow mode TYPICAL RECEIVING BAND LW,MW,SWL SWH FM FM INPUT FREQUENCY RANGE 0.5 ~ 20MHz 1~4 0 M H z 30 ~ 130MHz 30 ~ 150MHz 30 ~ 130MHz INPUT PIN AM IN FM IN FREQUENCY n /G3 (2) Setting divisor The divisor for the programmable counter is set as binary data in bits P0~P15.

• Pulse swallow mode (16 bits) LSB MSB Address D0H P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 20 215 Divisor setting range (pulse swallow mode):n=210H~FFFH (528~65535) (Note) With the 1/2+pulse swallow mode, the actual divisor is twice the programmed value.

/G3 HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD /G3 REV: 1.0 2002.01.30.

• Direct dividing mode (12 bits) LSB MSB Address D0H P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 211 P0 P1 P2 P3 Don't care Divisor setting range (direct dividing mode):n=10H~FFFH(16~4095) With the direct dividing mode, data p0~p3 are don’t-care and bit p4 is the LSB. 2. Prescaler and programmable counter circuit configuration (1) Pulse swallow mode circuit configuration 1/2 2 modulus prescaler 4bit swallow counter 12bit programmable counter FM,MODE Preset To phase comparator PSC P4-P15 P0-P3 FM L FM H Prescaler section FM IN AM IN HF Fig.3 This circuit consists of a 2 modulus prescaler, a 4 bit swallow counter and a 12bit programmable counter. During FM IN(FMIN mode),a 1/2 prescaler is added to the preceding step. (2)Direct dividing method circuit configuration AM IN 12bit program counter Amp P4-P15 To phase comparator Preset Fig.4 With the direct dividing mode, the prescaler section is bypassed and the 12bit programmable counter is used. (3) Both FMIN and AM IN have built-in amps. Data are input by capacitor coupling. FMIN and AM IN operate at low amplitude. General-purpose counter The general-purpose counter is a 20bit counter. It has such uses as counting AM/FM band intermediate frequencies (IF) and detecting auto-stop signals during auto-search tuning. General-purpose counter pins can also be used as I/O ports. 1. General-purpose counter control bits (1) Bits G0 and G1 … Used for selecting the general-purpose counter gate time.

/G3 HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD /G3 REV: 1.0 2002.01.30. G0 G1 LSB MSB Address D2H G0 G1 GATE TIME CYCLE MEASUREMENT PULSE 1ms 4ms 16ms 64ms

150 KHz

900 KHz

Crystal oscillator frequency (2) Bits SC,IF1 and IF2 …I/O port and general-purpose counter switching bits. (*) The functions of the following pins are switched by data. LSB MSB Address D2H IF1 IF2 IF1 I/O-5/IFIN1 IFIN1 I/O-5 IF2 I/O-6/IFIN2 IFIN2 I/O-6 (3)Bits M5 sets the state for pin I/O-5/IFIN1; M6, for pin I/O-6/IFIN2. These operations are valid when bits SC, IF1 and IF2 are all set to 1. LSB MSB Address D2H M5 M6 PIN STATES (When bits sc, IF1 and IF2 are all set to "1") IFIN1 IFIN2 0 0 (*) 1 1 0 INPUT pulled down INPUT enabled INPUT pulled down INPUT pulled down INPUT enabled INPUT pulled down M6M5 Note: Bits marked with an asterisk “(*)” are don’t care (4)Bits f0~f9…The general-purpose counter results can be read in binary from bits f0~f9 of the output register (D1H). LSB MSB Address D1H f12 f14f13f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f15 f16 f17 f18 f19 OVER BUSY "0" "0" 20 219 General-purpose counter data (5) OVER and BUSY bits…Detect the operating state of the general-purpose counter.

/G3 HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD /G3 REV: 1.0 2002.01.30. Address D1H MSB BUSYOVER "0" "0" General-purpose counter option monitor bit General-purpose counter overflow detection bit General-purpose counter busy Counted value in general- purpose counter/G130 220 -1 General-purpose counter ended counting Counted value in general- purpose counter/G131 220 (Overflow state) BIT DATA = "1" BIT DATA = "0" Note: When using the general-purpose counter, before referring to the contents of the general-purpose counter result bit (f0~f9), confirm that the busy bit is “0” (counting is ended) and the OVER bit is “0” (general-purpose counter data are normal). (6)START bit…When the data are set to “1”, the general-purpose counter is reset then counting begins. LSB MSB Address D2H start Counting continues uninterrupted. Counting begins after general - purpose counter is reset. 2. General-purpose counter circuit configuration The general-purpose counter section consists of input amps, a gate time control circuit and a 20 bit binary counter. OVERAmp IFIN1 IFIN2 20bit binary counterOverflow detection Gate time control circuit Cycle measurement pulse Gate SC IN (CMOS input) SC IF1 IF2 START G0 G1 BUSY fXT f0-f19 Fig.5 3. General-purpose counter measurement timing

/G3 HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD /G3 REV: 1.0 2002.01.30. START bit set to "1" End PERIOD IFIN1 OR IFIN2 BUSY bit Gate Binary counter input Clock pulse to be measured Frequency measurement timing chart Note: 1. IFIN1 and IFIN2 input have built-in amps. Data are input by capacitor coupling. FMIN and AM IN operate at low amplitude. General-purpose I/O ports These LSIs feature general-purpose output and I/O ports which are controlled through the serial ports. Input/output form port Input/output configuration Output port Dedicated: 4 ports N channel open-drain output I/O ports Dedicated: 1 port, Maximum: 5 ports CMOS input/output 1. General-purpose output ports (OT-1~OT-4) Pins OT-1~OT-4 are general-purpose dedicated output ports. They have such uses as control signal output. They are configured for N channel open-drain output and have an off withstanding voltage of 12V. The data set in bits O1~O4 of the input register (D2H) are output in parallel from their correspond dedicated output port pins OT-1~OT-4. SC9256 do not have dedicated output port OT-4, but setting the input register (D2H) CLK (O4C) bit to “1” converts pin DO2 into output port OT-4 (configured for CMOS output). The data set in bits O1~O4 of the input register (D2H) can also be read from the DATA pins as output register (D3H) serial data O1~O4.

/G3 HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD /G3 REV: 1.0 2002.01.30. (1) SC9256 LSB MSB Address D2H O3 O1~O4 PIN OUTPUT STATE OT-1~OT-3 High impedance (N channel open drain output =off) "L" level (N channel open drain output =on) O4O2O1 OT-4 (*1) "L" Level (*1) "H" Level (*1) O4C O4C DO2/OT-4PIN DO2 (Phase comparator output) OT-4 (General-purpose output port) (2)output register… The data set in bits O1~O4 of the input register can read as serial data O1~O4 from the output register (D3H). LSB MSB Address D2H O3 O4O2O1 LSB MSB Address D3H O3 O4O2O1 Input register Output register2. General-purpose I/O ports (I/O-5~I/O-6) Pins I/O-5~ I/O-6 are general-purpose I/O ports used for control signal input and output. They are configured for CMOS input and output. These I/O ports are set for input or output using bits M5~M6 of the input register (D2H). Setting M5~M6 to “0” sets these ports for input. Data which are input in parallel from I/O-5~I/O-6 are latched in the internal register on the ninth fall of the serial clock signal. These data can then be read as serial data I5~I6 from the DATA pins. Data which are set in bits O5~O6 of the input register (D2H) are output in parallel from their corresponding general-purpose I/O port pin I/O-5~I/O6. These operations are valid when bits SC, IF1, IF2 and CLK are all set to “0”.

/G3 HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD /G3 REV: 1.0 2002.01.30. (1) SC9256 LSB MSB Address D2H IF1 "0" IF2 "0" M5 M6 M5, M6 PIN INPUT /OUTPUT STATE (When IF1 and IF2 are "0") I/O -5, I/O -6 "L" Level "H" Level

• Setting data for output ports LSB MSB Address D2H IF1 "0" IF2 "0" CLK "0" "1" O5, O6 PIN OUTPUT STATE (When IF1 and IF2 are "0") I/O -5, I/O -6 "L"level "H"level O6O5M6 "1" (2)OUTPUT register…data which are set in bits M5~M6 of the input register (D2H) can be read as serial data M5~M6 from the output register (D3H). LSB MSB Address D2H LSB MSB Address D3H Input register Output register XT -- -- M5 M6

000 M 5 M 6

/G3 HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD /G3 REV: 1.0 2002.01.30. LSB MSB Address D3H Input registerI6I5000 I/O-5 I/O-6 Input data INPUT PORTS (I/O-5 ~ I/O-6) BIT DATA (I5-I6) "L" level "H" level Note: 1. When pins I/O-5~I/O-6 are used for output, the data in I5~I6 of the output register(D3H) are undefined.. 2. When power is turned on, input register (D2H) I/O port control bits M5~M6 and output data bits O5~O6 are set to “0”. General-purpose I/O ports are set as input ports. Pins which are used both as general-purpose I/O ports and for general-purpose counter input are set for I/O port input. The output state of general-purpose output ports is set to high impedance (N channel open drain output =off). 3. Pin I/O-5 and I/O-6 also serve as general-purpose counter input pins. Therefore, bits IF1 and IF2 of input register 2 must be set to “0” when these pins are used as I/O ports. Phase comparator The phase comparator outputs the phase error after comparing the phase difference of the reference frequency signal supplied by the reference counter and the divided output from the programmable counter. The frequencies and phase differences of these two signals are then equalized by passing them through low-pass filters. These signals then control the VCO. The filter constants can be customized for FM and AM bands since the signals are output in parallel from the phase comparator then pass through the two tristate buffer pins, DO1 and DO2. phase comparator FM VCO AM VCO Programmable counter output Reference frequency signal R S VDD VDD DO1 DO2 L.P.F L.P.F Fig.7

/G3 HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD /G3 REV: 1.0 2002.01.30. R S DO Low level floating High level DO Output Timing Chart Fig.8 DO Tr1 Tr2 R LC VCC To VCO varactor diode Typical low-pass filter constants (FM band reference values) C=0.33 /Gad F R1=10K /Ga1 R2=8.2K/Ga1 R3=330 /Ga1 R L=10K /Ga1 Standard Tr1:2SC1815 Tr2:2SK246 Typical Active Low-Pass Filter Circuit Fig.9 The figures above show the DO output timing chart and a typical active low-pass filter circuit featuring a Darlington connection between the FET and transistor. The filter circuit shown above is just one example. Actual circuits should be designed based on the band composition and the properties desired from the system. Pin DO2 can be switched for use as pin OT-4. Lock detection bits The lock detection bits detect locked states in the PLL system. These systems have an unlock detection bit (unlock bit) which is used to detect, using the reference frequency cycle, the phase difference between the reference frequency and divided output of programmable counter. These systems also have phase error detection bits ( bits PE1~PE3), which are capable of more precise detection (±0.55µs~±7.15µs). 1. Unlock detection bit (UNLOCK) This bit detects, using the reference frequency cycle, the phase difference between the reference frequency and the divided output of the programmable counter. When there is no lock, that is, when the reference frequency and the divided output of the programmable counter are not the same, unlock F/F is set. Unlock F/F is reset every time the input register (D2H) unlock reset bit (RESET) is set to “1”. After unlock F/F has been reset in this way, locked state can detected by checking the unlock detection bit (UNLOCK) of the output register (D3H). After unlock F/F has been reset, the unlock detection bit must be checked after a time interval exceeding that of the reference frequency cycle has elapsed. This is because the reference frequency cycle inputs the lock detection strobe to unlock F/F. If the time interval is short, the correct locked state cannot be detected. Therefore, the output register (D3H) has a lock enable bit (ENABLE). This bit is reset every time the input register (D2H) reset bit is set to “1”, and set to “1” through the lock detection timing. That is, the locked state is correctly detected when the lock enable bit (ENABLE) is “1”.

/G3 HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD /G3 REV: 1.0 2002.01.30. "H" level High impedance "L" level Reference frequency Programmable counter output DO output Phase comparator Lock detection strobe Unlock is reset (RESET) Unlock F/F (UNLOCK) Lock enable (ENABLE) Phase error detection Counts phase difference. Fig.10 LSB MSB Address D2H LSB MSB Address D3H Input register Output register ENA- BLE UN LOCK RESET Setting data to "1" resets unlock detection bit and lock enable bit. PLL lock detection enabled PLL lock detection in waiting state P L Li nu n l o c k e ds t a t e ( * ) P L Li nl o c k e ds t a t e Note: The asterisk (*) indicates an error state of over 180° phase difference relative to the reference frequency 2. Phase error detection bits (PE1~PE3) The unlock bit detects, using the reference frequency cycle, the phase difference between the reference frequency and the divided output of the programmable counter. The phase error detection bits (bits PE1~PE3) are capable of precise phase error detection of±0.55µs~±7.15µs using the reference frequency cycle.( If the UNLOCK bit is set to “1” and the phase difference relative to the reference frequency is over 180°,b i t s PE1~PE3 cannot correctly detect the phase error. Therefore, bits PE1~PE3 are normally used when the UNLOCK bit is set to “0”.) Bits PE1~PE3 detect phase error normally when the phase difference is -180°~180° relative to the reference frequency cycle.

/G3 HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD /G3 REV: 1.0 2002.01.30. LSB MSB Address D3H PE1 PE2 PE3 PE1 PE2 PE3 000 001 010 011 100 11 0 110 111 PHASE ERROR (PE) PE< /G66 0.55/Gad s /G66 0.55/Gad s/G3/G130 PE< /G66 1.65/Gad s /G66 1.65/Gad s /G130 PE< /G66 2.75/Gad s /G66 2.75/Gad s/G3/G130 PE< /G66 3.85/Gad s /G66 3.85/Gad s/G3/G130 PE< /G66 4.95/Gad s /G66 4.95/Gad s/G3/G130 PE< /G66 6.05/Gad s /G66 6.05/Gad s/G3/G130 PE< /G66 7.15/Gad s /G66 7.15/Gad s/G3/G130 PE The phase error data can be read from the output register (D3H) as serial data PE1~PE3. Following is a typical lock detection operation. It shows the operation flow from locked state to frequency change with a phase error greater than±6.05µs. Frequency change WAIT Phase error detection start Reset bit 1 WAIT Time interval exceeding that of reference frequcncy cycle ENABLE=1? UNLOCK bit =0? Check phase error detection bits PE1,PE2 and PE3 PE1=1,PE2=0,PE3=1? Phase error=greater than/G66 4.95/Gad s and less than/G3/G66 6.05/Gad s YES YES (Lock) YES NO NO NO (UNLOCK) Fig.11

/G3 HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD /G3 REV: 1.0 2002.01.30. Other Control Bits 1. CLK and C5 bits…Control bits which switch the function for the OT-4/DO2 pin. The O4C bit controls switching of the DO2 pin and OT-4 pin. When bits R0~R3 of the input register (D0H) are set to “1” (standby mode). LSB MSB Address D2H O4C XT O4C XT DO2/OT-4 PIN STATE DO2 output OT-4 output CRYSTAL OSCILLATOR CIRCUIT STATE Oscillator circuit on Oscillator circuit off Oscillator circuit off Oscillator circuit on When one of bit R0~R3 of the input register (D0H) is set to “0” (not standby mode) LSB MSB Address D2H O4C XT O4C XT DO2/OT-4 PIN STATE DO2 output OT-4 output CRYSTAL OSCILLATOR CIRCUIT STATE Oscillator circuit on 2. DOHZ bit…controls the DO2 pin output state. LSB MSB Address D2H DOHZ phase comparison error output DO2 output fixed at high impedance 3. TEST bit… Data should normally be set to “0”. LSB MSB Address D2H TEST "0"

/G3 HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD /G3 REV: 1.0 2002.01.30. ELECTRICAL CHARACTERISTICS CURVE 1414 1000 500 200 106 0.1 0.2 0.5 1 2 5 20 10 50 100 AMIN(LF) Frequency Characteristics INPUT LEVEL (mVrms) INPUT FREQUENCY (MHz) 1414 1000 500 200 106 0.1 0.2 0.5 1 2 5 20 10 50 100 AMIN(HF) Frequency Characteristics INPUT LEVEL (mVrms) INPUT FREQUENCY (MHz) 1414 1000 500 200 106 02 0 FMIN(LF) Frequency Characteristics INPUT LEVEL (mVrms) INPUT FREQUENCY (MHz) 40 60 80 100 120 140 160 180 200 1414 1000 500 200 106 IFIN(LF) Frequency Characteristics INPUT LEVEL (mVrms) INPUT FREQUENCY (MHz) 0.05 0.1 0.2 0.5 1 2 5 10 50 15 20 (Note) Operating Guarantee Range Standard Characteristics(VDD =5 V , T a= 2 5/G107 ) (Note) Operating Guarantee Range FM IN:FMH FM IN:FML Standard Characteristics(VDD =5 V , T a= 2 5/G107 )

/G3 HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD /G3 REV: 1.0 2002.01.30. APPLICATION CIRCUIT SC9256 Micro- Controller PERIOD CLOCK DATA CX ' t a l VCC AM VCO AM VCO 5Vtyp. Varator Diode AM IF signal FM IF signal 0.001/Gad F 0.01/Gad F 4.7/Gad F0 . 1 /Gad F Output Port 0.01/Gad F C 0.01/Gad F

/G3 HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD /G3 REV: 1.0 2002.01.30. PACKAGE OUTLINE DIP-16-300-2.54 UNIT: mm 6.35 /G66 0.25 2.54 4.36MAX3.00MIN 7.62(300) 15 degree 0.5/G66 0.1 19.55/G66 0.3 1.52 0.25 /G66 0.05 0.5MIN 1.27MAX SOP-16-300-1.27 UNIT:mm 7.80 /G66 0.40 5.30 /G66 0.30 7.62(300) 10.15/G66 0.25 8.89 1.27 0.45/G66 0.10 0.15 2.25MAX +0.05 -0.02 /G3 /G3