SC6579 SILAN | Alldatasheet

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/G3 HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD /G3 Rev: 1.0 2001.12.30 /G3 PIN CONFIGURATION SC6579 QUAL RDDA Vref MUX VDDA VSSA CIN SCOUT RDCL T57 VDDD OSCI VSSD TEST MODE OSCO DIP-16 SOP-16 RADIO DATA SYSTEM (RDS) DEMODULATOR

DESCRIPTION

The integrated CMOS circuit SC6579 is an RDS demodulator. It recovers the additional inaudible RDS information which is transmitted by FM radio broadcasting. The data signal RDDA and the clock signal RDCL are p rovided as outputs for further processing by a suitable decoder (microcomputer).

FEATURES

  • Anti-aliasing filter (2nd order)
  • Integrated 57 kHz band-pass filter (8th order)
  • Reconstruction filter (2nd order)
  • Clocked comparator with automatic offset compensation
  • 57 kHz carrier regeneration
  • Synchronous demodulator for 57 kHz modulated RDS signals
  • Selectable 4.332/8.664 MHz crystal oscillator with variable dividers
  • Clock regeneration with lock on bi-phase data rate
  • Bi-phase symbol decoder with integrate and dump functions
  • Differential decoder
  • Signal quality detector
  • Subcarrier output.

ORDERING INFORMATION

SC6579 DIP16-300-2.54 SC6579S SOP-16-225-1.27

/G3 HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD /G3 Rev: 1.0 2001.12.30 /G3 BLOCK DIAGRAM Via pin MODE two different crystal frequencies can be used. MODE CRYSTAL CLOCK LOW 4.332 MHz HIGH 8.664 MHz ABSOLUTE MAXIMUM RATINGS (Ta=25 °C) Characteristic Symbol Value Unit Analog Supply Voltage (pin 5) V DDA 0~ 6 V Digital Supply Voltage (pin 12) V DDD 0~ 6 V Voltage on All Pins; Grounds Excluded V n -0.5 ~ V DD + 0.5 V Storage Temperature T stg -40 ~+150 °C Operating Ambient Temperature T amb -40 ~+85 °C ±300 note 1 V Electrostatic Handling for All Pins Except Pins 9 and 10 VESD +1500 ~-3000 note 2 V Notes /G2d61. Equivalent to discharging a 200 pF capacitor via a 0 Ω series resistor. 2. Equivalent to discharging a 100 pF capacitor via a 1.5 kΩ series resistor. anti- aliasing filter 57kHz bandpass (8th order) reconstruction filter oscillator and divider quality bit generator clocked comparator costas loop variable and fixed divider bi-phase symbol decoder differential decoder reference voltage clock regeneration and sync test logic and output selector switch MPX signal MUX 330pF SCOUT 560pF CIN +5V V DDA 0.1/GadF Vref 2.2 /GadF VSSA V SC6579 91 0 1 1 MODE TEST V SSD

15 T57

2 RDDA

0.1/GadF 82pF47pF 4.332/8.664MHz 2.2K /Ga1 +5V

/G3 HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD /G3 Rev: 1.0 2001.12.30 /G3

ELECTRICAL CHARACTERISTICS

(VDDA =V DDD =5 V; T amb =25°C and measurements taken in Fig.1; unless otherwise specified.) Comparator input (pin 7) Minimum Input Level (RMS value) V i(rms) f = 57 kHz -- 1 10 mV Input Resistance R i 70 110 150 /G1c2 kΩ Oscillator input (pin 13) HIGH-level Input Voltage V IH V DDD = 5.0 V 4.0 -- -- V LOW-level Input Voltage V IL V DDD = 5.0 V -- -- 1.0 V Input Current I I V DDD = 5.5 V -- -- ±/f031 µA /G2c4To be continued/G2c5 Parameter Symbol Test condition Min. Typ. Max. Unit Analog Supply Voltage (pin 5) V DDA 3.6 5.0 5.5 V Digital Supply Voltage (pin 12) V DDD 3.6 5.0 5.5 V Total Supply Current I tot I 5 +I12 /f02d 6 /f02d m A Reference Voltage (pin 3) V ref V DDA = 5 V /f02d 2.5 /f02d V MPX input (signal before the capacitor on pin 4) RDS Amplitude (RMS value) V i MPX (rms) ∆ f ±1.2 kHz RDS; ∆ f ±3.5 kHz ARI; see Fig.5 1 -- -- mV f = 5±2 kHz 200 -- -- mV Maximum Input Signal Capability (peak-to-peak value) Vi MPX (p-p) Input Resistance R4-6 f = 0 to 100kHz 40 -- -- /G1c2kΩ /G1c2 Signal Gain G8-4 f = 57 kHz 17 20 23 dB 57 kHz band-pass filter Center Frequency f c T amb = -40 to +85 °C 56.5 57.0 57.5 kHz -3 dB Bandwidth B 2.5 3.0 3.5 kHz ∆ f =±7 kHz 31 -- -- dB f < 45 kHz 40 -- -- dB f < 20 kHz 50 -- -- dB Stop Band Gain G f > 70 kHz 40 -- -- dB Output Resistance (pin 8) R o(8) f = 57 kHz -- 26 -- Ω

/G3 HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD /G3 Rev: 1.0 2001.12.30 /G3 (Continued) Note1. The signal T57 has a phase lead of 123° (±180°) relative to the ARI carrier at output SCOUT. Parameter Symbol Test condition Min. Typ. Max. Unit Digital demodulator and outputs QUAL, RDDA, T57, OSCO and RDCL (pins 1, 2, 14, 15 and 16) HIGH-level output voltage V OH I Q = -20 mA; V DDD = 4.5 V 4.4 -- -- V LOW-level output voltage V OL I Q = 3.2 mA; V DDD = 5.5 V -- -- 0.4 V Nominal Clock Frequency RDCL f RDCL -- 1187.5 -- Hz Jitter of RDCL ∆ tRDCL -- -- 18 µs Nominal Subcarrier Frequency T57 f T57 note 1 -- 57.0 -- kHz Output Current OSCO (pin 14) VDDD = 4.5 V; VO = 0.4 V 5.9 -- -- mA Output Current QUAL, RDDA, T57, RDCL (pins 1, 2, 15 and 16) IO VDDD = 4.5 V; VO = 4.1 V -5.3 -- -- mA

4.332 MHz crystal parameters

XTAL Frequency f 0 -- 4.332 -- MHz Maximum Permitted Tolerance ∆ fmax ±50 10 -6 Adjustment Tolerance of f0 ∆ fo Load Capacitance C L -- 30 -- pF Resonance Resistance R xtal -- -- 60 Ω

8.664 MHz crystal parameters

XTAL Frequency f 0 -- 8.664 -- MHz Maximum Permitted Tolerance ∆ fmax -- ±50 -- 10 -6 Adjustment Tolerance of f0 ∆ fo Load Capacitance C L -- 30 -- /f020pF Resonance Resistance R xtal -- -- 60 Ω /G1c2

/G3 HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD /G3 Rev: 1.0 2001.12.30 /G3 PIN DESCRIPTION Pin no. Symbol Function

1 QUAL Quality indication output

2 RDDA RDS data output

3 V ref Reference voltage output (0.5 V DDA )

4 MUX Multiplex signal input

5 V DDA +5 V supply voltage for analog part

6 V SSA Ground for analog part (0V)

7 CIN Subcarrier input to comparator

8 SCOUT Subcarrier output of reconstruction filter

9 MODE Oscillator mode/test control input

10 TEST Test enable input

11 V SSD Ground for digital part (0V)

12 V DDD +5 V supply voltage for digital part

13 OSCI Oscillator input

14 OSCO Oscillator output

15 T57 57 kHz clock signal output

16 RDCL RDS clock output

SYMBOL PARAMETER MIN. TYP. MAX. UNIT VDDA Analog Supply Voltage (pin 5) 3.6 5.0 5.5 V VDDD Digital Supply Voltage (pin 12) 3.6 5.0 5.5 V Itot Total Supply Current -- 6 -- mA Vi(rms) RDS Input Amplitude (RMS value; pin 4) 1 -- -- mV VOH HIGH-level Output Voltage for Signals RDDA, RDCL, QUAL and T57 4.4 -- -- V VOL LOW-level Output Voltage for Signals RDDA, RDCL, QUAL and T57 -- -- 0.4 V Tamb Operating Ambient Temperature -40 -- +85 °C FUNCTION DESCRIPTION The SC6579 is a demodulator circuit for RDS applications. It contains a 57 kHz bandpass filter and a digital demodulator to regenerate the RDS data stream out of the multiplex signal (MPX).

/G3 HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD /G3 Rev: 1.0 2001.12.30 /G3 Filter part The MUX signal is band-limited by a second-order anti-aliasing-filter and fed through a 57 kHz band-pass filter (8th order band-pass filter with 3 kHz bandwidth) to separate the RDS signals. This filter uses switched capacitor technique and is clocked by a clock frequency of 541.5 kHz derived from the 4.332/8.664 MHz crystal oscillator. Then the signal is fed to the reconstruction filter to smooth the sampled and filtered RDS signal before it is output on pin 8. The signal is AC-coupled to the comparator (pin 7). The comparator is clocked with a frequency of 228 kHz (synchronized by the 57 kHz of the demodulator). Digital part The synchronous demodulator (Costa’s loop circuit) with carrier regeneration demodulates the internal coupled, digitized signal. The suppressed carrier is recovered from the two sidebands (Costa’s loop). The demodulated signal is low-pass-filtered in such a way that the overall pulse shape (transmitter and receiver) approaches a cosinusoidal form in conjunction with the following Integrate and dump circuit. The data-spectrum shaping is split into two equal parts and handled in the transmitter and in the receiver. Ideally, the data filtering should be equal in both of these parts. The overall data-channel-spectrum shaping of the transmitter and the receiver is approximately 100% roll-off. The integrate and dump circuit performs an integration over a clock period. This results in a demodulated and valid RDS signal in form of bi-phase symbols being output from the integrate and dump circuit. The final stages of RDS data processing are the bi-phase symbol decoding and the differential decoding. After synchronization by data clock RDCL (pin 16) data appears on the RDDA output (pin 2). The output of the bi-phase symbol decoder is evaluated by a special circuit to provide an indication of good data (QUAL = HIGH) or corrupt data (QUAL = LOW). Timing Fixed and variable dividers are applied to the 4.332/8.664 MHz crystal oscillator to generate the 1.1875 kHz RDS clock RDCL, which is synchronized by the incoming data. Which ever clock edge is considered (positive or negative going edge) the data will remain valid for 399 µs after the clock transition. The timing of data change is 4 µs before a clock change. Which clock transition (positive or negative going clock) the data change occurs in, depends on the lock conditions and is arbitrary (bit slip). During poor reception it is possible that faults in phase occur, then the clock signal stays uninterrupted, and data is constant for 1.5 clock periods. Normally, faults in phase do not occur on a cyclic basis. If however, faults in phase occur in this way, the minimum spacing between two possible faults in phase depends on the data being transmitted. The minimum spacing cannot be less than 16 clock periods. The quality bit changes only at the time of a data change.

/G3 HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD /G3 Rev: 1.0 2001.12.30 /G3 TYPICAL RDS SENSITIVITY (BLOCK) 100 correct blocks (%) -1 11 0 Vi(RDS signal, RMS value) (mV) (1) RDS + ARI (BK) (2) RDS only (1) (2) TIMING DIAGRAM RDCL RDDA, QUAL 4/Gads 842/Gads 421/Gads 4/Gads MEH163

/G3 HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD /G3 Rev: 1.0 2001.12.30 /G3 APPLICATION CIRCUIT 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 MCU SC6579 560pF 0.1/GadF VDDA 330pF MPX signal 2.2/GadF RDDA RDCL VDDD 4.332/8.664MHz 47pF 82pF 0.1/GadF

/G3 HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD /G3 Rev: 1.0 2001.12.30 /G3 PACKAGE OUTLINE DIP-16-300-2.54 UNIT: mm 2.54 3.86 4.36 MAX3.00 MIN 7.62 /G14/G18/G3/G47/G48/G4a/G55/G48/G48 19.55 1.52 6.35/G660.25 0.46/G660.08 0.25/G660.05 +0.2 -0.3 0.99 +0.3 -01.27 MAX 1.52+0.3 SOP-16-225-1.27 UNIT:mm 5.0 10.15 1.27 6.0/G660.4 +0.25 -0.20 0.40/G660.10 +0.40 -0.200.50/G660.20

1.80 MAX

3.90/G660.3 0.20+0.05 -0.02 8.89 /G3