SC63C0316 SILAN | Alldatasheet
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HANGZHOU SILAN MICROELECTRONICS CO.,LTD REV:1.0 2004.08.03 Http: www.silan.com.cn Page 1 of 24 AUDIO CONTROL SYSTEM WITH BUILTIN 4BIT MCU
DESCRIPTION
The SC63C0316 singlechip CMOS microcontroller is designed for very high performance. With an upto14digit LCD direct drive capability, 4channel A/D converter, 8bit timer/counter, PLL frequency synthesizer. The SC63C0316 offers you an excellent design solution for a wide variety of applications, especially those requiring DTS support. Up to 56 pins of the 80pin QFP package can be dedicated to I/O. Eight vectored interrupts provide fast responseto internal and external events. In addition, the SC63C0316's advanced CMOS technology ensures low power consumption and a wide operating voltage range.
FEATURES
- 512nibble RAM * 16Kbyte ROM I/O Pins * Input only: 4 pins * Output only: 28 pins * I/O: 24 pins LCD Controller/Driver * Maximum 14digit LCD direct drive capability * 28 segment x 4 common signals * Display modes: Static, 1/2 duty (1/2 bias) 1/3 duty (1/2 or 1/3 bias), 1/4 duty (1/3 bias) 8Bit Basic Timer * Programmable interval timer functions * Watchdog timer function 8Bit Timer/Counter * Programmable 8bit timer * External event counter * Arbitrary clock frequency output * External clock signal divider * Serial I/O interface clock generator 8Bit Serial I/O Interface * 8bit transmit/receive mode * 8bit receive m ode * Data direction selectable (LSBfirst or MSBfirst) * Internal or external clock source QFP8014×200.8
ORDERING INFORMATION
SC63C0316 QFP8014 x 200.8 A/D Converter * 4channels with 8bit resolution Bit Sequential Carrier Buffer * Support 16bit serial data transfer in arbitrary format PLL Frequency Synthesizer * Level = 300 mVpp (min) * AMVCO range = 0.5 MHz to 30 MHz * FMVCO range = 30 MHz to 150 MHz 16Bit Intermediate Frequency (IF) Counter * Level = 300 mVpp (min) * AMIF range = 100 kHz to 1 MHz * FMIF range =5MHz to 15 MHz Watch Timer * Time interval generation 0.5 s, 3.9 ms at 32.768 kHz * Frequency outputs to BUZ pin * Clock source generation for LCD Interrupts * Four internal vectored interrupts * Four external vectored interrupts * Two quasiinterrupts MemoryMapped I/O Structure * Data memory bank 15
HANGZHOU SILAN MICROELECTRONICS CO.,LTD REV:1.0 2004.08.03 Http: www.silan.com.cn Page 2 of 24 Three PowerDown Modes * Idle: Only CPU clock stops * Stop1: Main syste m or subsyste m clock stops * Stop2: Main system and subsystem clock stop * CE low: PLL and IFC stop Oscillation Sources * Crystal or ceramic oscillator for main syste m clock * Crystal for subsystem clock * Main syste m clock frequency: 4.5 MHz (Typ) * Subsystem clock frequency: 32.768 kHz (Typ) * CPU clock divider circuit (by 4, 8, or 64) Instruction Execution Times * 0.9, 1.8, 14.2 µ s at 4.5 MHz * 122 µ s at 32.768 kHz (subsystem) Operating Temperature * – 40 °C to 85 °C Operating Voltage Range * 1.8 V to 5.5 V at 3MHz * PLL/IFC operation: 2.5V to 3.5V or 4.0V to 5.5V
APPLICATIONS
- Auto audio system * Other audio syste m BLOCK DIAGRAM ABSOLUTE MAXIMUM RATINGS (Ta mb=25°C) Characteristics Symbol Value Unit Supply Voltage VDD 0.3 6.5 V VI1 0.3 VDD +0.3 Input Voltage VI2 0.3 VDD +0.3 V Output Voltage VO 0.3 VDD +0.3 V 15 Output Current High IOH 30 mA (To be continued)
HANGZHOU SILAN MICROELECTRONICS CO.,LTD REV:1.0 2004.08.03 Http: www.silan.com.cn Page 3 of 24 (Continued) Characteristics Symbol Value Unit +30˄Peak value˅ Output Current Low IOL +100˄Peak value˅ mA Operating Temperature Ta mb 40 ~ 85 °C Storage Temperature Tstg 65~150 °C DC CHARACTERISTICS (Ta mb=40°C to +85°C, VDD=3.5V to 6.0V) (To be continued) Characteristics Symbol Test condition Min. Typ. Max. Unit VIH1 All input pi ns except those specified below for VIH2VIH4 0.7VDD VDD VIH2 Port 0, 1, 6, 7, and RESET 0.8VDD VDD Ports 4, 5, 7 and 8 with pullup resistors assigned 0.7VDD VDD VIH3 Ports 4, 5, 7 and 8 are open drain 0.7VDD 9 Input High Voltage VIH4 Xin, Xout and Xtin VDD 0.5 VDD V VIL1 All input pins except those specified below for CIL2Vil3 0.3VDD VIL2 Ports 0, 1, 6, 7, 9, 10 and RESET 0.2VDD Input Low Voltage VIL3 Xin, Xout and XTin 0.4 V VDD=4.5V to 6.0V, I OH=1m A, Ports 0, 210 VDD 1.0 VOH1 IOH=100µ A VDD 0.5 VDD=4.5V to 6.0V, IOH=100µ A, Ports 1113 only VDD 2.0 Output High Voltage VOH2 IOH=30µ A VDD 1.0 VDD=4.5V to 6.0V, IOL=1.6mA, Ports 4,5,7 and 8only 0.8 2 IOL=1.6mA, Ports 0,2,3,6,9,10, EO1, and Eo2 only 0.4VOL1 IOL=400µ A, Ports 0, 2, 3, 6, 9, 10, EO1 and EO2 only 0.2 VDD=4.5V to 6.0V, IOL=100µ A, Port 11, 12 and 13 only Output Low Voltage VOL2 IOL=50µ A V Input High Leakage Current ILIH1 VI=VDD, all input pins except RESET and those specified below for ILIH2ILIH3
HANGZHOU SILAN MICROELECTRONICS CO.,LTD REV:1.0 2004.08.03 Http: www.silan.com.cn Page 4 of 24 (Continued) Characteristics Symbol Test condition Min. Typ. Max. Unit ILIH2 VI=VDD, Xin, Xout, Xtin only 25 µ A Input High Leakage Current ILIH3 VI=9V, Ports 4,5,7 and 8 are opendrain 20 µ A ILIL1 VI=0V, all input pins except Xin, Xout, XTin and RESET Input Low Leakage Current ILIL2 VI=0V, Xin, Xout, and XTin only 20 µ A ILOH1 VO=VDD, all output pins except for ports 4, 5, 7 and 8 Output High Leak age Current ILOH2 VO= 9 V , P o r t s 4 , 5 , 7 a n d 8 a r e opendrain µ A Output Low Leakage Current VI= 0 V ; VDD=5V±10%, Port 03, 6, 9, and 10 (except P1.3) 15 46 80 RL1 VDD=3V±10%, 30 90 200 VO=VDD 2 V , V DD=5V±10%, Ports 4, 5, 7 and 8 only 15 40 70 RL2 VDD=3V±10%, 10 60 VI=0V; VDD=5V±10%, RESET 100 230 400 Pullup Resistor RL3 VDD=3V±10%, 200 490 800 kΩ LCD Drive Voltage VLCD 2.5 VDD V LCD Voltage Dividing Resistor RLCD 50 100 140 kΩ VDD=5V±10%, 3 6 COM Output Impedance RCOM VDD=3V±10%, 10 15 kΩ VDD=5V±10%, 3 20 SEG Output Impedance RSEG VDD=3V±10%, 10 60 kΩ IDD1 (2) VDD=5V±10%,(3), 4.5MHz crystal oscillator, C1=C2=22pF, CE high; PLL operates 12 25 Idle mode; V DD=5V±10%, 4.5MHz crystal oscillator, CPU clock =fxx/4, CE low; PLL stops. 1.4 1.8 IDD2 VDD=3V±10%, CPU clock =fxx/64 0.23 1.0 mA IDD3 (4) VDD=3V±10%, 32kH z crystal oscillator, CE low; PLL stops. 25 120 Supply Current (1) IDD4 (5) Idle mode; VDD=3V±10%, 32kHz crystal oscillator. 20 30 µ A
HANGZHOU SILAN MICROELECTRONICS CO.,LTD REV:1.0 2004.08.03 Http: www.silan.com.cn Page 5 of 24 DC CHARACTERISTICS (concluded) (Ta mb=40°C to +85°C, VDD=2.7V to 6.0V) NOTES: 1. Currents in the following circuits are not included; onchip pullup resistors, output port drive currents, internal LCD voltage dividing resistors and A/D converter. 2. IDD1 and IDD7 are guaranteed in Ta mb = – 20 °C to + 85 °C 3. Data includes power consumption for subsystem clock oscillation. 4. For highspeed controller operation, the power control register (PCON) must be set to 0011B. 5. For lowspeed controller operation, the power control register (PCON) must be set to 0000B. 6. When the system clock control register, SCMOD, is set to 1001B, main system clock oscillation stops and the subsystem clock is used. MAIN SYSTEM OSCILLATOR CHARACTERISTICS (Ta mb=40°C to +85°C, VDD=2.7V to 6.0V) Oscillator Characteristics Test condition Min Typ Max Units Oscillation frequency (1) 0.4 5.0 MHz Ceramic Oscillator Stabilization time (2) Stabilization occurs when VDD is equal to the mini mum oscillator voltage range 4 ms Oscillation frequency (1) 0.4 4.5 6.0 MHz Crystal Oscillator Stabilization (2) ms XIN input frequency (1) 0.4 4.5 MHz External Clock XIN input high and low level width 111 1250 ns NOTES: 1. Oscillation frequency and Xin input frequency data are for oscillator characteristics only. 2. Stabilization time is the interval required for oscillator stabilization after a poweron occurs, or when Stop mode is terminated. Characteristics Symbol Test condition Min. Typ. Max. Unit Stop 1 mode; XTin=0V VDD=5V±10%, CPU clock=fxx/4, CE low; PLL stops 0.6 5 IDD5 VDD=3V±10%, CPU clock=fxx/64 0.2 3 µ A VDD=5V±10%, 4.5MHz crystal oscillator, CPU clock=fxx/4, CE low; PLL stops 4.2 8 IDD6 VDD=3V±10%, CPU clock=fxx/64 0.7 1.2 mA Supply Current (cont) IDD7 (2) Stop 2 mode; Xtin=0V, VDD=5V±10%, CPU clock=fxx/4, CE low; PLL stops 0.12 2.0 µ A
HANGZHOU SILAN MICROELECTRONICS CO.,LTD REV:1.0 2004.08.03 Http: www.silan.com.cn Page 6 of 24 SUBSYSTEM CLOCK OSCILLATOR CHARACTERISTICS Oscillator Characteristics Test condition Min Typ Max Units Oscillation frequency(1) 32 32.768 35 kHz Crystal Oscillator Stabilization time (2) s XTIN input frequency (1) 32 100 kHz External clock XTIN input high and low level width (tXH, tXL) 5 15 µ s Note:1. Oscillation frequency and XTIN input frequency data are for oscillator characteristics only. 2. Stabilization time is the interval required for oscillator stabilization after a poweron occurs. PIN CONFIGURATIONS 68697071727374757677787980 37363534333231302928272625 3 P4.1/SO P4.2/SI P4.3/CLO P5.0/ADC0 P5.1/ADC1 P5.2/ADC2 P6.0/KS0 P6.1/KS1 SDAT/P6.2/KS2 SCLK/P6.3/KS3 VDD/VDD0 VSS/VSS0 XOUT XIN VPP/TEST XTIN XTOUT RESET/RESET FMIF AMIF VSS1 VCOAM VCOFM P2.3 P2.2 P2.1 P2.0 SEG27/P13.3 SEG26/P13.2 SEG25/P13.1 SEG24/P13.0 SEG23/P12.3 SEG22/P12.2 SEG21/P12.1 COM1 COM2 COM3 SEG0/P7.0 SEG1/P7.1 SEG2/P7.2 SEG3/P7.3 SEG4/P8.0 SEG5/P8.1 SEG6/P8.2 SEG7/P8.3 SEG8/P9.0 SEG9/P9.1 P4.0/SCK PI.3/INT4 P1.2/INT2 P1.0/INT0 P1.1/INT1 P0.3/BUZ P0.2/TCL0 P0.1/TCLO0 P0.0/BTCO P3.3 P3.2 P3.1 P3.0 SC63C0316 P5.3/ADC3 BIAS VLC1 VLC2 COM0 VLC0 403938 SEG10/P9.2 SEG11/P9.3 SEG12/P10.0 SEG20/P12.0 SEG19/P11.3 SEG18/P11.2 SEG17/P11.1 SEG16/P11.0 SEG15/P10.3 SEG14/P10.2 SEG13/P10.1 656667 CE VDD1
HANGZHOU SILAN MICROELECTRONICS CO.,LTD REV:1.0 2004.08.03 Http: www.silan.com.cn Page 7 of 24 PIN DESCRIPTION Pin No. Symbol Description P0.0 P0.1 P0.2 P0.3 4bit I/O port. 1bit or 4bit read, write, and test are possible. Pullup resistors can be configured by software. P1.0 P1.1 P1.2 P1.3 4bit input port. 1bit or 4bit read and test are possible. Pullup resistors can be configured by software. 5659 6871 P2.0~ P2.3 P3.0~P3.3 4bit I/O ports. 1bit, 4bit or 8bit read, write and test are possible. Pullup resistors can be configured by software. Ports 2 and 3 can be paired to support 8bit data transfer. P4.0 P4.1 P4.2 P4.3 4bit I/O ports. 1bit, 4bit or 8bit read, write and test are possible. Pullup resistors can be configured by software. P5.0 P5.1 P5.2 P5.3 Ports 4 and 5 can be paired to support 8bit data transfer. P6.0 P6.1 P6.2 P6.3 4bit I/O port. 1bit, 4bit or 8bit read, write and test are possible. Pullup resistors can be configured by software. P7.0 P7.1 P7.2 P7.3 1bit or 4bit output port. Alternatively used for LCD segment output. P8.0 P8.1 P8.2 P8.3 1bit or 4bit output port. Alternatively used for LCD segment output. P9.0 P9.1 P9.2 P9.3 1bit or 4bit output port. Alternatively used for LCD segment output. P10.0 P10.1 P10.2 P10.3 1bit or 4bit output port. Alternatively used for LCD segment output. (To be continued)
HANGZHOU SILAN MICROELECTRONICS CO.,LTD REV:1.0 2004.08.03 Http: www.silan.com.cn Page 8 of 24 (Continued) Pin No. Symbol Description P11.0 P11.1 P11.2 P11.3 1bit or 4bit output port. Alternatively used for LCD segment output. P12.0 P12.1 P12.2 P12.3 1bit or 4bit output port. Alternatively used for LCD segment output. P13.0 P13.1 P13.2 P13.3 1bit or 4bit output port. Alternatively used for LCD segment output. 2427 COM0COM3 Common signal output for LCD display
20 BIAS LCD power control
LCD power supply. Voltage dividing resistors are assignable by software
12 VDD0 Main power supply
13 VSS0 Main Ground
19 RESET Syste m reset pin
Crystal, or ceramic oscillator pin for main system clock. (For external clock input, use XIN and input XIN’ s reverse phase to XOUT) XTOUT XTIN Crystal oscillator pin for subsystem clock. (For external clock input, use XTIN and input XTIN’ s reverse phase to XTOUT)
16 TEST Test signal input (must be connected to VSS for normal operation)
Input pin for checking device power. Normal operation is high level and PLL/IFC operation is stopped at low level. VCOFM VCOAM External VCOFM/AM signal inputs.
66 EO PLL’ s phase error output
FM/AM intermediate frequency signal inputs.
65 VDD1 PLL/IFC power supply
62 VSS1 PLL/IFC ground
72 BTCO Basic timer overflow output signal
73 TCLO0 Timer/counter 0 clock output signal
74 TCL0 External clock input for timer/counter 0
75 BUZ
2,4,8 or 16 kHz frequency output for buzzer sound for 4.19 MHz main system clock or 32.768 kHz subsystem clock (To be continued)
INT0 is synchronized with system clock. 78 INT2 Quasiinterrupt with detection of rising edge signal. 79 INT4 External interrupt input with detection of rising or falling edges.
80 SCK SIO interface clock signal
1 SI SIO interface data input signal
2 SO SIO interface data output signal
3 CLO CPU clock output
47 ADC0ADC3 ADC input ports. 2855 SEG0SEG27 LCD segment signal output. Figure 1. Interrupt Control Circuit Diagram
- The quasiinterrupt INT2 is only used for testing incoming signals.
contains a global disable bit, IME, which disables all interrupt at once. instructions, all interrupts must first be disabled by a DI instruction. will have high priority. Therefore, the firstrequested interrupt cannot be superseded by any other interrupt. Table 2. Interrupt Priority Register Settings 0 0 0 Process all interrupt requests at default priority settings. 0 0 1 INTB and INT4 at highest priority. 0 1 0 INT0 at highest priority. 0 1 1 INT1 at highest priority. 1 0 0 INTS at highest priority. 1 0 1 INTT0 at highest priority. 1 1 0 INTCE at highest priority. 1 1 1 INTIF at highest priority.
HANGZHOU SILAN MICROELECTRONICS CO.,LTD REV:1.0 2004.08.03 Http: www.silan.com.cn Page 12 of 24 Interrupt execute flowchart A vectored interrupt is generated when the following flags and register settings, corresponding to the specific interrupt (INTn) are set to logic one: — Interrupt enable flag (IEx) — Interrupt master enable flag (IME) — Interrupt request flag (IRQx) — Interrupt status flags (IS0, IS1) — Interrupt priority register (IPR) If all conditions are satisfied for the execution of a requested service routine, the start address of the interrupt is loaded into the program counter and the program starts executing the service routine from this address. Figure 4 Interrupt execution flowchart Interrupt is generated (INT xx) Request flag (IRQx) 1 IEx=1? Generate corresponding vector interrupt and release powerdown mode IME=1? IS1,0=0,0? IS1,0=0,1? Highpriorityinterrupt IS1, 0=1, 0 Store contents of PC and PSW in the stack area; set PC contens to corresponding vector address Are both interrupt sources of shared vector address used? Reset corresponding IRQx flag Jump to interrupt start address Retain value until IEx=1No No Retain value until IME=1 Retain vaule until interrupt service routine is completed IS1, 0=0, 1 IRQx flag vaule remains 1 Jump to interrupt start address Verify interrupt source and clear IRQx with a BTSTZ instruction Yes Yes No No No Yes Yes Yes Yes No
HANGZHOU SILAN MICROELECTRONICS CO.,LTD REV:1.0 2004.08.03 Http: www.silan.com.cn Page 13 of 24 EXTERNAL INTERRUPTS The external interrupt mode registers IMOD0 and IMOD1 are used to control the triggering edge of the input signal at INT0 and INT1, respectively. The INT4 interrupt is an exception because its input signal generates an interrupt request on both rising and falling edges. When a sampling clock rate of fxx/64 is used for INT0, an interrupt request flag must be cleared before 16 machine cycles have elapsed. Since the INT0 pin has a clockdriven noise filtering circuit built into it, please take the following precautions when you use it: — To trigger an interrupt, the input signal width at INT0 must be at least two times wider than the pulse width of the clock selected by IMOD0. This is true even when the INT0 pin is used for generalpurpose input. — Because the INT0 input sampling clock does not operate during Stop or Idle mode, you cannot use INT0 to release powerdown mode. EXTERNAL INTERRUPT MODE REGISTER The external interrupt 2 (INT2) mode register, IMOD2, is used to select INT2 and KSn pins as interrupt input. If a rising edge is detected at the INT2 pin, or when a falling edge is detected at any one of the pins (KS0– KS3), the IRQ2 flag is set to "1" and a release signal for powerdown mode is generated. If one or more of the pins which are configured as key Interrupt (KS0– KS7) are in Low input or Low output state, the key Interrupt can not be occured. Figure 5. Rising Edge Detection Circuit IMOD2 Falling Edge Detection Circuit Clock Selector IRQ2 INT2 P6.3/KS3 P6.2/KS2 P6.1/KS1 P6.0/KS0 Note: To generate a key interrupt on a falling edge at KS0KS3, all KS0KS3 pins must be configured to input mode. I/O PORTS The SC63C0316 has 14 ports. There are total of 4 input pins, 28 output pins, 16 configurable I/O pins, and 8 nchannel opendrain I/O pins, for a maximum number of 56 I/O pins. Pin addresses for all ports except ports 713 are mapped in bank 15 of the RAM. Ports 713 pin addresses are in bank 1 of the RAM. The contents of I/O port pin latches can be read, written, or tested at the corresponding address using bit manipulation instructions.
pin is set to output mode. PM flags are addressable by 8bit write instructions only. disabled, even though the pin's pullup is enabled by a corresponding PUMOD bit setting. automatically disconnecting all softwareassignable port pullup resistors. Table 4. PullUp Resistor Mode Register (PUMOD) Organization Table 5. Port Mode Group Flags (8Bit W) when set to “ 0” , the output pin is configured to pushpull mode. Table 6. Nchannel open drain mode register (PNE) setting
operation is initiated. ADATA is addressable by 8bit read instructions only. analog data input source. Bit 3 in the ADMOD register is always "0". Table 7. A/D Converter Mode Register Settings (1, 4Bit R/W) NOTE: If ADMOD.2– ADMOD.0 = 0, disable analog input channel selection. very high frequency (VHF) signals to a fixed frequency using a phase difference comparison system. Figure 8. PLL Frequency Synthesizer Block Diagram
HANGZHOU SILAN MICROELECTRONICS CO.,LTD REV:1.0 2004.08.03 Http: www.silan.com.cn Page 17 of 24 PHASE DETECTOR, CHARGE PUMP, AND UNLOCK DETECTOR The phase comparator compares the phase difference between divided frequency (fN) output from the programmable divider and the reference frequency (fr) output from the reference frequency generator. The charge pump outputs the phase comparator's output from error output pins EO. The relation between the error output pin output, divided frequency fN, and reference frequency fr is shown below: fr > fN = Low level output fr < fN = High level output fr = fN = Floating level When PLL operation is started by setting PLMOD register, PLL unlock flag (ULFG) in the PLL flag register (PLLREG) has unlock state information between the reference frequency and divided frequency. The unlock detector detects the unlock state of the PLL frequency synthesizer. The unlock flag in the PLLREG register is set to "1" in unlock state. If ULFG = "0", the PLL lock state is selected. PLLREG ULFG CEFG IFCFG 0 ULFG is set continuously at a period of reference frequency f r by unlock detector. You must therefore read ULFG flag in the PLLREG register at periods longer than 1/f r of the reference frequency. ULFG is reset when it is read. PLLREG register can be read by 1bit or 4bit RAM control register instructions. PLL operation is decided by CE (chip enable) pin state. The PLL frequency synthesizer is disabled and the error output pin is set to floating state while the CE pin is low. When CE pin is high level, PLL is operating normally. The chip enable flag (CEFG) in the PLLREG register has information about CE pin state. When the CE pin changes its low state to high, CEFG flag is set to logic one and CE reset operation occurs. When the CE pin changes its high state to low, CEFG flag is set to logic zero and CE interrupt is generated. INTERMEDIATE FREQUENCY COUNTER The SC63C0316 uses an intermediate frequency counter (IFC) to count the frequency of the AM or FM signal at FMIF or AMIF pin. The IFC block consists of a 1/2 divider, gate control circuit, IFC mode register (IFMOD) and a 16bit binary counter. During gate time, the 16bit IFC counts the input frequency at the FMIF or AMIF pins. The FMIF or AMIF pin input signal for the 16bit counter is selected by IFMOD register. The 16bit binary counter (IFCNT1– IFCNT0) can be read by 8bit RAM control instructions only. When the FMIF pin input signal is selected, the signal is divided by 2. When the AMIF pin input signal is directly connected to the IFC, it is not divided. By setting the IFMOD register, the gate is opened for 1ms, 4ms, or 8ms periods. During the open period of the gate, input frequency is counted by the 16bit counter. When the gate is closed, the counting operation is complete, and an interrupt is generated.
dividing resistors is cut off, regardless of the current LMOD.3 value. Table 9. LCD Control Register (LCON) Organization (4Bit W) LCON.3 0 Always set to logic zero. LCON.2 0 Always set to logic zero.
0 Port 6 input enable
1 Port 6 input disable
0 LCD output low, cut off current to dividing resistor
When LMOD.3=” 0” : turn display off. When LMOD.3=” 1” : COM and SEG output in display mode.
0 LCD display off LCD display off LCD display off
segment output. This is also referred to as the 'frame frequency. subsystem clock is used as the watch timer source. Table 11. LCD Clock Signal (LCDCK) Frame Frequency NOTES: 'fw' is the watch timer clock frequency of 32.768 kHz.
Table 13. LCD Mode Control Register (LMOD) Organization (8Bit W) 0 Internal voltage dividing resistor. 1 External voltage dividing resistor; internal voltage dividing resistors are off. NOTE:'x' means 'don't care'. The common signal output pin selection (COM pin selection) varies according to the selected duty cycle.
HANGZHOU SILAN MICROELECTRONICS CO.,LTD REV:1.0 2004.08.03 Http: www.silan.com.cn Page 24 of 24 PACKAGE OUTLINE QFP8014×200.8 UNIT: mm 14.0±0.2 17.9±0.4 0.8±0.2 12.0 16.3±0.4 HANDLING MOS DEVICES: Electrostatic charges can exist in many things. All of our MOS devices are internally protected against electrostatic discharge but they can be damaged if the following precautions are not taken:
- Persons at a work bench should be earthed via a wrist strap.
- Equipment cases should be earthed.
- All tools used during assembly, including soldering tools and solder baths, must be earthed.
- MOS devices should be packed for dispatch in antistatic/conductive containers.