SC132E6 SIEMENS | Alldatasheet

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© Advanced 0.8 micron (drawn gate-length) ACMOSSH Megalogic ° technology SC xE6: Sub-Micron ASICs © 0.28 ns speed (2 inout NAND, . fanout = 2) »Made In Europe« * Slew rate control option ® High packing density featuring over Continuing development of the proven Megalogic process now enables 300,000 available gates Siemens to offer their proven channelless gate-array architecture with © Full workstation support sub-micron transistors. {e.9.Cadence, Mentor, Valid, Dasix) * Reduced design turnaround time Offering a 30 % speed improvement over its 1 micron predecessor, due to cell preplacement and delay the SCxE6 family’s enhanced packing density, coupled with the new Siemens calculation Lagic Design System CAD tools, offers the gate-array performance needed toe Fy ly hierarchical design flow revolutionize your system design. capability All»Made in Europes of course! * Alternately sourced by Toshiba

Electrical Characteristics Series Design Flow Absolute Maximum Ratings Design Automation - The Key to Success —— ore rv The SCxE6 gate-array family is fully supported by “Parameter | Symbol [ums Unt ADVANCAD, a highly sophisticated CAD system for the roar ety wolage \\ ae i _ . fra 03 M development of VLSI ASICs. ADVANCAD Is based on vonage eta odie industry standard software packages supplemented with Son oleae cone [io an “et 03 | | __ the Siemens Logic Design System (SLDS), available for 0C-output current by 1) | ma use on popular engineering workstations. DC-cutput diode current | lox -20...20 ) ms Storage temperature Tap -65... 150 j °C SLDS -Workstation Support Junction temperature The Siemens Logic Design System (SLDS), used in Sad is a aa aes 150 —L°C _ conjunction with industry standard workstation CAD fy See maie DE aesenieaticn \\/O-ceis im dara aneees packages, offers the user an ASIC design system without Recommended Operating Conditions parallel. Powerful enough to permit cell preplacement, Recommended Operating ¢ = accurate enough to correctly calculate the effects of Parameter Symbol | Min. [ Max. | Unit parasitic wiring capacitance, even before netlist transfer DC- Supply Voltage 1 i to the “back-end” design environment. This may reduce (Veg OV) {1) | Yoo las }55 |v the turnaround time of your design significantly. Input voltage vi 0 i Vo LV And flexible enough to interlace to your existing CAD Output voltage Vo 0 Voe v environment’ Input tiae and fall times tt 0 6 ns Junction temperature (2) | 7) 0 725 sc 12) Extended temperature mings an request Cus! f up tothe Ps shown Macro Cells _Development steps Customer | Customer | Customer High Speed ROM/Low Power ROM ¢ Product idea/ercumt design eee om | woe © Configuration B4-1024 words; 2-32 BH * Comeaion tore. (aon and own * Capacity max. 16 Kbit/ Block sign manual and cel library aan, @ Reac Access Time 10/14 ns typical —————— ike ‘Single Port RAM a © Logic simulation foundry © Configuration 8-256 words; 4-36 bit Vimolonemion © Capacity max. 4.5 Kbit’ Block 2 Layout genemmon ¢ Read Access Time 6 ns typical © Logic simulation including | | | oT —_o 9s ees witing delays { _THole Pon RAM a spree ot * Configuration 16-64 words; 4-34 bi simulation results © Capacity max, 2.3 Keit/ Block = - # Read Access Time 5.ns typical : ee non | Siemans OT : Design Centre mask generation Basic Cell Delay vs Fanout —— _|Pesk = = (SCXE6 Vio =5Y, I, = 25°C with estimated wiring lengths) —e_ Water fabrication Siemens Propagation Delay Ins) * Assembly IC Fabrication

20 Tasting

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Part Number Gate Estimated Maximum max $C33 E6 33000 13000 158 | 144 sc41 £6 41000 17000 174 | 160 $C54 E6 54000 22000 198 184 S70 £6 70000 28000 | 222 | 208 $C 108 £6 108000 43000 } 270 | 256 $C132 £6 132000 53000 294 280 (256) $C177 £6 | 177000 71000 334 320 (256) $C236 6 | 235000 94000 382 368 (256) $0302 E6 | 302000 120000 430 416 (256) Noten « Raw-gales 2 Boved on 40 ® array nlirahion Actual ehlzalior wwrint, decenng co cel lypes used ~ a 2 Acditionat 1/0 pags may be contiquied a8 Voc! V ys. subject 19 numer ers ditve of output Outliers 4. Tester bmdation at 25 % 1/0. Standard Packaging Spectrum P-LCC-28 + ~ | P-LOC~44 + + + + } P-MQFP-80 + + + or | P-MOFP-100 + + + + P-MQFP-208 4 ' ‘ o | P-MOFP-240 or o | o | o | o P-MOFP-304 or o | of or or M-QUAD-160") or or or or or or o | oF or M-QUAD-208*) or or or or or or M-QUAD-240*) o | oor or or or M-QUAD-304") | or or or C-PGA-64-D + 1 + + | CPGAT2ZD | + | 4+ 1 1 + C-PGA-88-D 4 + + + | of or + | + C-PGA132-D + + + + o | of C-PGA-144-D 4 + + C-PGA-299-D } or or | or oO + + c-PGa-301-0 | | | or or +=avlable T= i preparation of = on request U=cavityup O= cavity down Please enquire tor amy tyoe not shown *) M-QUAD is a Dadamark o@ned by Oke Worldwide Design Support Additional Information available: Oesign Centres: Munich Milan SCxE6 call catalogue Stuttgart London* SLDS manual Hanover Zurich" Packaging catalogue “PAppiceton Suppor Dusseldort Santa Clara Siemens Aktiengeselischaft