SBX1601A SONY | Alldatasheet
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| Sony SBX1601A | Serlal Interface/Transmission Encoder eee Description Package Outline Unit: mm The SBX1601A is a hybrid IC encoder that converts the parallel data into serial form for the purpose of a7 sm FGA interface or transmission of digital video or audio data. “ The encoding format employed conforms to SMPTE i 714.224 tentative standard, FB Features Sy | All circuitry necessary for conversion from parallel Thame de, ates format data into serial data are included. This allows for a 7 simple usage of this serial transmission encoder with only a few external components. Other related IC's include SBX1602A serial RS transmission decoder (including cable equalizer and SPIN Ruts i > serial to parallel conversion) and CXA1389AQ coaxial — a cable driver, - yo BO-O-O-O-S OS OG ---- - i) 1. Structure Hybrid IC 3 ® 2. Applications BOTTOM @ : ® vIeW @ © Encoder for 100 to 270 Mbps Serial data. ® en) © Examples of application: ® ) Serial Interface/Transmission for (0) —) y 4fsc PAL 177Mbps com/ | hd 4iscNTSC 143Mbps. ‘ ae 3. Functions @ Parallel to serial conversion © Scrambler: Modulo-2 division by G (X)=(X°+X*+1) (X+1) ® PLL for serial clock generation © PLL lock detection ® SYNC word or Timing Reference Signal (or TRS) required in Parallel incoming data (Hex). Sbit 10bit 1st word FF 3FF 2nd word 00 000 3rd word 00 000 4th word (4fsc only) 00 000 (8bit TRS is internally converted to that of 10 bit), Note) The words composing the SYNC word given above shall not appear during data words, This limitation includes 00 and FF in 8 bit use and 000 through 003 and 3FC through 3FF in 10 bit use, ony reserves the ght to change product and epeciicadone wihoxt pret natice, Ths information dove not corey any licgnse by cpleation o are devioenSany canoat oaumne reopoveaiy io ary potions ering culel Reuse fees create. -337- £907234°6 ~ ST
SONY SOx" 601A [tem | Symbol | Rats | Unt | [ve | | v | sweet ye Fouputcurent «it~ | 30 | [Alowable power dssipaion | Po | 20 | W | 5. Recommended Operating Conditions [tem | Symbol | Aaings | Unt | Supply voltage Supply voltage Note) 4.81052 Note) Above conditions are for TTL input. Voltages are given with respect to the GND potential. -398-
- Block Diagram Ep S 3 “8 a CP Ata | \\ | N—® xia te— & | Hs Tee
5 J | s Des
j Se: rE Bis a oe 3 C] JS ise k@ = elle to ' OU T-8s “ES Fh 38s Pp oF LRP et o=:- gs <P-8 xia =@) 38 ©) xsa < TT i : 2p a 3 @g = S) O-O : 5 a & 3 -939-
- Pin Description Pin a Deseri Relenel——cemamcion —| mete | ‘ 1 : ' H | | | | “ i; | | : PLL lock detection. | O j | , Turns to H during | : | j PLL lock. At unlock H H t becomes irregular. 1,usT | Atfreerun(TN1H) | of; | j tums to L. H i H | -1.0 | lv | L 40| Vv & = ! | vee | | ae | I || Clock output frequency divided to | 1/10 VCO output. Utilized to check PCK Ge) VCO free run frequency. H ~08 v i L -16 v ve eo ve ere ve Sx Input parallel data is converted to serial. Moreover. az scramble, to @ C2) | NAZI converted data is differentially 3 output. ° utp H -16 v o L -2.4 Vv sy vee -340-
ee | ae fe Ream | Min. | Typ. [Max. [Unit } C23) “ Power supply for sas - buffers: Ce) a3 29 | Veo ZS lle Give 45V for TTL = input or -5V for ECL os “ x vez 6 | DX 7 | DsY 8 | D8X 9 | vey Parallel input ports: 10 | D7X 09 is MSB 11| D7Y Gert a ir 12 | D6X Y Is for return. 13 | D6Y 14 | D5X ForTTLinput H v 15 | D5Y (Voo=+5V) L O08) Vv 16 | D4X 17 | D4Y 18 | D3X ForECLinput H v 19 | D3Y (Vee=0V) L -1.6| V 20 | D2x 21 | O2Y 22 | DIX 23 | DIY 24 | DOX 25 | DOY -341-
Mm 8382383 000552? 124 MMSONY SONY ‘SBX:601A Symbol Equivalent circuit Description | VO inp | a. Un eo | a | x | Selection of VCO GC] oscillation range: | H: High range i 1 28 | RSE wo) 140 to 270MHz L: Low range 100 to 145MHz H 04 v 10x 10% t -ao| ¥ vee vee jets Parallel clock input (PCX) and its return Ge) cr (PCy): te rd For ECL input -1.0 v Gp (Veo=0V) L -16| V ° ForTTLinput H 2.0 v Pcy ‘ (Voo=+5V) L 08 | Vv vee -5V power supply —5V power supply -342-
M™ 6342343 0005528 Ob0 MMSONY ma eeeSSSSSsSSSSSSS SONY SBX1601A eee SSCA bol Equivalent circuit Description Bojer] cette | mtn [0 | Adjustment of VCO free run frequency: The closer this pin is to Vee, the lower 33] FV the frequency. To 39 v *o = adjust, TN1 pin shall ¥ be connected to mi eiiao GND. td a ~ Phase comparator out/VCO input: TAP £ 3 Connect to a trap 3.2 v = inorder to attenuate jitter. vee oo
32 Test node:
zx AtH: Input disabled v TN1 (VCO free run condition). we At L: Input through. ~45| Vv ver -343-
mm 8382383 0005529 TT? MMSONY Sn SONY SBX160"A 8. Electrical Characteristics 8-1, DC Characteristics (Vee=-5V, Ta=25°C ) [tem | Symbol Test conditions Test circuit Fig.] Min. | Typ. | Max. | Unit | le | Veze-8¥ woes [_LéO | | ma Supply current2 | Ico | Veo=+5V * [7 || ma | Veo=GND. a input votage Vi. | Pin used PCX, PCY, DnX, DnY Veo=+5V p20] | fv Vi Pn ed POX PCY, Dr On [a Input current |_| Pin used PCX, PCY, OnX,OnY| — Fig. 8-5 |__| | [sto [a0 | ; [atv | Pin used RSE Fig. 8-9 ee Pin used TN1 Fig. 8-8 fps |v Pin used PCK [fos |v Output voltage Pin used LST roe? Lo] | tv | Pin used SX, SY [fs [fv | Fre2209 [Tea -344-
MM 4382383 0005530 719 MNSONY SONY sexieoia SONW stor 8-2. AC Characteristics PLL [tem [Symboi[Testconditions[TestcireutFig.| Min. | Typ. | Max. | Unit | ee et tee frequency [thaws | Figae | |__| 140 | we | VCO Max. oscilation| twa | oo [150 [| ae | frequency 2 | tana _| a ee [ter _| tsignal-a7oMz a RSEs"H" a ee i f signal=177MH mipain range aes Fst Ee a [furs | RSE="U ee EN a Tested through PCK (Pin 36): 1/10 of serial clock. -345-
M@® 4382383 0005531 655 MESONY a SONY ‘SBXI601A SONY Switching Characteristics (Vee=-5V, Ta=25°C) tem ‘Symbol Test conditions Test circuit Fig. [ Min. [ Typ. | Max. | Unit | fall time tt | Re=tka p | ta [| nsec | rise time tr __| Pins used $x, SY [07 | | nseo | SF KT 80% A KT 20% tf Fig. 8-1. Definition of tr, tf Timing Relation of Input Clock and Data (Vee=-5V, Ta=25°C) [tem [Symbol] —_Testoonaons[Toosreut Fi] win [Typ | Max | Unt | [Gaayine | ww [RoR ee ec ke 2 Pie 2 >} > eam < PCK i | H 50 % re Fig. 8-2. Definition of td, tw -346-
MH 8382383 0005532 591 MMSONY a SONY SeK'ODIA SONY sexs : i af i ? 5 a 2 H rene | peel lary toy Tir rey 8 @-GODO—SHIDOBHIOO-O ear EE¥as scassass 2 3 . > . 2 [' s ib aed ir? 3 Log WE
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ob alt*hy Ee Bier § oHE ll “ba EL e iach 5 a 2 EE: Bee MH # 257s FA PET i $ tte s : Hath. i 3 att i 3 -iPs 5 C) Het] 5 § AG Pan ru i is EF setae : ' z ° TA Ty EF # a Pattee oe. st ale 3 7g FI ag gto 3: PPaal ° “Ure aé ropes Pree resusnyanesassnssigy [Dee BR OO-SSOPEPORSEOOESSSSSSO— Gi i cece Eeee i sbgg * D : a3! = 36 g %¢ -347-
M™ 8382383 0005533 42a MESONY a SONY SOXI601A 463% EEE | HEEEE oo] ree ra sexicora OF SBXi6014 " e2| oy 4 sy” ” oa43 ae vemos = P, lal 7 mor we) em ah "ot ™ Rh = . oy oe Fig. 8-4. Fig. 8-5. Po sev a a a Si stor ter wos HEE EE |o “ome HE EE SBX16014 " ” aa saxisoia od Fo paeros * =H = Bh = Fig. 8-6. Fig. 8-7. -348-
M@™ 8382383 0005534 364 MESONY SONY woreora Hitt HET YE |P mess “ET” coxseosan Gm sexseorn x 62 oy rx 1) wd = Ie if =e ” Rh =p ey s BA Fig. 8-8. Fig. 8-9. et t ener ‘ i a pes 00 00 HETTE jo. r ax ” Ora In at "eg a ttm es Set Rh =| “ Fig. 8-10. -349-
wa 8382383 0005535 2TO0 MMESONY SONY SBX1601A 9. Description of Operation SBX1601A internally generates a clock which is 10 times higher in frequency as that of parallel and locked to the input parallel clock in terms of a built-in PLL and converts input parallel data into serial data. To facilitate clock extraction at the receiving end, serial data is being scrambled. To eliminate data polarity it is then converted to NAZI and output in differential form. There is also a PLL lock detection circuit which enables the serial output circuit only when it is locked. 9-1 Phase Relation between Input Parallel Clock and Data The phase relation between the parallel clock and data is shown in Fig. 9-1. Both clock and data are differentially input. Parallel clock and data are input so that the rising edge of PCX be at the center of the data. A clock of almost the same phase as PCX is generated inside the IC to latch data inside the IC. PCX (Input) NL ONFNLSY I PCK (Output) NON Fig. 9-1. Phase relation between clock and data 9-2. Input Circuit Requirements Parallel clock and data can be given either by ECL or TTL logic. With ECL input every X or Y input can be used directly as an input for an ECL line receiver. To use with TTL input, Vcc (Pin 29) shall be connected to +5V. A fixed blas of +1.4V* shall be applied to PCY and DnY (n=0 to 9). TTL signals and its parallel clock shall be provided through 1 K ohm resistors to each “X” input. Those 1k resistors are effective to minimize the influence of the TTL input signals to the jitter characteristics of the serial output signal. For 8 bit data, maintain unused LSBs to logical “0" state. (* The fixed bias value can be higher, for example 2.5V in case of CMOS input). SBX1601A vec PCX PCY DSX DSY Dox DOY +5V .#1,4V (for TTL) 1K 1K 1K > jh. #25V (for CMOS) Parallel Parallel \\ clock data J TTL level Parallel signal Fig. 9-2. Usage with TTL level Input -350-
M@™ §342383 O00553b 137 MMSONY SONY SBXI601A 9-3. Clock Generation Fig. 9-3. shows a block diagram of PLL, PLL lock detection and the serial output contro! . When TN1 (pin 35) is ‘set to “H" (connected to GND), the parallel clock input is disabled inside the IC. VCO turns to free run condition and adjustment of the free run frequency becomes possible through FV (pin 33). Reducing the value of the resistance put between FV and Vee lowers VCO oscillation frequency. Monitoring oscillation frequency is made through PCK (pin 36) which gives 1/10 frequency of VCO output. When PLL is locked, the phase of the PCK output coincides with that of the PCX input within a tolerance given. C-R time constant connected to TN1 serve to turn off the paralleled clock temporarily in order to avoid mislock problem. When supply voltage goes below -4.3V approximately, the input parallel clock is automatically shut off to set VCO free run frequency. The selection of VCO oscillation frequency range is made by RSE (pin 28): “H" stands at 140 to 270MHz and at “L", at 100 to 145MHz. TAP (Pin 33) is the output of the phase comparator. To minimize jitter component, a trap circuit consisting of a series resonant circuit turned at the parallel clock frequency in use is necessary. PGX PCY TNI TRP FV RSE PCK cm Oo Oo QO Oo OD oO Vn A ° Phase v 1/10 “O° tst O<} Q sx O p NAZ to oP Pin sy g q onversion| Serial clock Fig. 9-3, PLL and serial output control block 9-4, PLL Lock Detection LST signal is generated by latching the incoming parallel clock with the internal parallel clock which Is 1/10 of the VCO frequency. LST serves as the PLL lock detection signal. The LST also controls serial output. If parallel clock input is disabled by means of TN1, LST turns to "L” and serial output tums to OFF condition (SX (3): “H", SY (4): "L") as described in the preceding section. The involvement of LST in the control of serial output makes it possible to switch off the serial output signal at will by forcing the state of the input parallel clock to “L". -851-
mm 8382383 000553? O73 MESONY SONY SOX*601A 9-5. Sync Word Detection To convert serial data back to parallel the receiving side, it is necessary to insert into the serial data some sort of timing reference signat which provides means of identifying each of the parallel data word. In the SMPTE digital interface format, it is called TRS (Timing Reference Signal). TRS consists of following 3 words, 3FF, 000, 000 in the incoming order. For details refer to SMPTE docs 125M and 114.224. 9-6. TRS Generation for 8 bit Data Although the basic system works for 10 bit data, 8 bit data can be accepted using the upper 8 bits of SBX1601A maintaining the lower 2 bits at logical “L” states as shown in Fig. 9-4, SBX1601A ~@ DIX DIY DOX DOY 10K 8 bit parallel data VEE Fig. 9-4, Usage of 8 bit data (ECL level) Since the 8 bit TRS signal FF,00,00 is converted to 3FC,000,000 by the above agreement, within this particular chip the conversion algorithm of 8 bit TRS to that of 10 bit is made in such a way that when two contiguous 000 words are detected at the parallel input the 2 LSBs of the preceding words are set to “1"s , which results in 3FF, 000, 000 as shown in Fig. 9-5. Order of input 30} (D1 1 MSB 001 1 001 fai 1 001 Qo 1 001 Input data i) 1 001 Oo 001 G0} 1 001 1 0} 1 0 i Ay “0: 6} 0 0 0 fit Input parallel data Parallel data after conversion Fig. 9-5. Conversion from 8 bit TRS to 10 bit TRS Note) If more than 3 consecutive words of 000 in D1 standard, or 4 consecutive words 000 in D2 standards, occur at the parallel input it does not meet the SMPTE 114.224 proposed standard thus no proper operation is possible. -352-
Mi 4382383 0005538 TOT MSONY SONY SBX160°A 9-7. Scrambler Fig. 9-6 (a) shows a basic scrambler block showing the modulo-2 division by X® + X* +1. Fig. 9-6 (b) shows the actual form of the serambler which is equivalent to (a) but fully pipelined. Fig. 9-6 (a). X9+X4+1 scrambler Fig. 9-6 (b). Actual X9+X4+1 scrambler 9-8. NRZ to NRZI Conversion To eliminate the signal polarity of scrambled data, conversion from NRZ to NRZI is employed. Thanks to the nature of NRZI code, maintenance of the polarity of signal becomes unnecessary in design and manufacturing of equipment. Further, if a differential output is used as two separate signal sources, their spurious radiation components tend to cancel out or lower to each other. X94 X44 1 | | Fig. 9-7. NRZ to NRZI conversion -353-
MH 8382383 0005539 Wb MESONY SONY ‘SBX1601A 9-9. VCO Frequency Adjustment VCO free-run frequency is adjusted generally at room temperature after the temperature of the IC reaches a steady state (5 to 10 minuteS-after power supply is ON). First, set VCO to free-run condition either by connecting TTN1 node to ground or by maintaining parallel clock input (PCX) at logical “L” state. While monitoring PCK (Pin 36) output, adjust the frequency within +:1% of the desired parallel clock in terms of the variable resistor (VR1) shown in Fig. 9-8. SBX1601A FV TRP ™1 PCK Frequency Monitor a [i exyeney Mon C1 O Free run 10uF ina test SW VR1 oK Lif 1K 22K Fig. 9-8. VCO control area 9-10. Compensation on VCO Temperature Characteristics ‘A diode-connected transistor Q1 shown in Fig. 9-8. is effective to improve some residual frequency variation along the temperature change. Typical characteristics of the VCO are given in Fig. 9-9 (a) and 9-9 (b). 9-11. Jitter Trap Since the internally generated serial clock is locked to the incoming parallel clock, there exists periodic jitter components which are generated from the phase comparison process of the PLL. A serial resonant circult (trap) connected between TAP (Pin 34) and Vee tuned at the parallel clock frequency reduces effectively the fundamental component of the jitter well below the specification ( +0.25nsec). Recommended values of C1 and L1 are given in Table 9-1. -354-
MB 8382383 0005540 bba MMSONY SONY S8x:60!A cer) | t80_ | aa | 300 Table 9-1. Recommended values of the trap circuit An Important remark in a practical implementation is that TRP node is an input of a very sensitive voltage-frequency converter (VCO) which can be easily disturbed by any pick-up noise. Hence, the trap circuit should be carefully located and be kept as short as possible from the pin 34 in order to avoid a noise problem. 10. Recommended Circult Fig. 10-1 (a) and 10-1 (b) show recommended circuit for ECL input and that of TTL respectively. -855-
M@ 63482383 OOO5541 ST4Y MSONY SONY SBX1601A RSE : “H" . 65 TA 280.00 ee a a 777A 8 se0.00 LLLL AL | | oor LLLAx | | | woo ZLLVLZ | fT | FV pin voltage (V) Test voltage from Vee pin Fig. 9-9 (a). VCO oscillation frequency vs. FV pin voltage (High Rate) 450 s 25 RSE: “L” 8 110.00 wy ay, [ 0.90 1.00 1.10 1.20 1,30 FV pin voltage (V) Test voltage trom Vee pin Fig. 9-9 (b). VCO oscillation frequency vs. FV pin voltage (Low Rate) -356-
M@ =43423483 0005542 430 MMSONY SONY SBKIEO"A 30 2at = 2a [pe eg 19 i 25 [—— Low pull in 7 3 1.6 |= Low ull in > => 23 14 “15 5 25 45 65 85 “15 5 25 45 65 85 Ambient temperature (°C) Ambient temperature (°C) {a) at 270 Mb/sec (RSE=“H”) (b) at 177 Mb/sec (RSE=“H”) 18 - ; i | ry 16 j—— gy 1S ft & 1s 14 Freeun | | 14 eee 13 ar sn irs i ri a ae ‘2 | Low pull inp 12 [= Low pull in it it 10 “15 5 25 45 65 85 715 Ss 25 45 65 85 ‘Ambient temperature (°C) ‘Ambient tomperature (°C) (c) at 143 Mb/sec (RSE="H”) (d) at 143 Mb/sec (RSE=“L”) Fig. 9-10. Typical characteristics of pull-in range and free-run frequencies -857-
MH 8382383 OO0SS43 377 MESONY t L Ll ‘i ote ee i , rs a i ix H 3 vd ¥ * Be 3 ® & Os is) x oS = O48 = ¥© cy E is BO i Or < 50 nm S 3 £ Ors oO: z@ 3 Lg x o x x: x@ 2 x a i ©) FA * ©8 g© Ox #© a 3 a o8 x z Py > ™ Fo * = Fy § & 2 #8 8 @ 3 z 3 (ied se2v0 19g 139 -358-
ME 8382383 0005544 203 MESONY SONY SO6DTA t | toi age : i i : nF id Et ft [a : z\\ 5 5 O8 i bo s O8 EO fos z € 2 & Be 3© 2 3 id < 2© A 54 - | |2 8 <5 “TI 8 1 Fy x . e i ee sal g | t ie Fy SEeeerne: -859-
MH 8342383 OOO5S4S L4YT MSONY SONY ‘SBX1601A 11, Markings Markings and their meanings are as shown below. SBX1601A O O O TYPE NO. LOT NO. r} JAPAN Pin 4 marking Country of origin -360-