SAME70Q20

SAME70 ATMEL | Alldatasheet

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Features

 Core ̶ ARM Cortex-M7 running at up to 300 MHz(1) ̶ 16 Kbytes of ICache and 16 Kbytes of DCache with Error Code Correction (ECC) ̶ Simple- and double-precision HW Floating Point Unit (FPU) ̶ Memory Protection Unit (MPU) with 16 zones ̶ DSP Instructions, Thumb®-2 Instruction Set ̶ Embedded Trace Module (ETM) with instruction trace stream, including Trace Port Interface Unit (TPIU)  Memories ̶ Up to 2048 Kbytes embedded Flash with unique identifier and user signature for user-defined data ̶ Up to 384 Kbytes embedded Multi-port SRAM ̶ Tightly Coupled Memory (TCM) interface with four configurations (disabled, 2 x

32 Kbytes, 2 x 64 Kbytes, 2 x 128 Kbytes)

̶ 16 Kbytes ROM with embedded Boot Loader routines (UART0, USB) and IAP routines ̶ 16-bit Static Memory Controller (SMC) with support for SRAM, PSRAM, LCD module, NOR and NAND Flash with on-the-fly scrambling ̶ 16-bit SDRAM Controller (SDRAMC) interfacing up to 256 MB and with on-the-fly scrambling  System ̶ Embedded voltage regulator for single-supply operation ̶ Power-on-Reset (POR), Brown-out Detector (BOD) and Dual Watchdog for safe operation SAM E70 Atmel | SMART ARM-based Flash MCU DATASHEET

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 ̶ Quartz or ceramic resonator oscillators: 3 to 20 MHz main oscillator with failure detection, 12 MHz or 16 MHz needed for USB operations. Optional low-power 32.768 kHz for RTC or device clock ̶ RTC with Gregorian calendar mode, waveform generation in low-power modes ̶ RTC counter calibration circuitry compensates for 32.768 kHz crystal frequency variations ̶ 32-bit low-power Real-time Timer (RTT) ̶ High-precision 4/8/12 MHz internal RC oscillator with 4 MHz default frequency for device startup. In-application trimming access for frequency adjustment. 8/12 MHz are factory-trimmed. ̶ 32.768 kHz crystal oscillator or embedded 32 kHz (typical) RC oscillator as source of low-power mode device clock (SLCK) ̶ One 500 MHz PLL for system clock, one 480 MHz PLL for USB high-speed operations ̶ Temperature Sensor ̶ One dual-port 24-channel central DMA Controller (XDMAC)  Low-Power Features ̶ Low-power Sleep, Wait and Backup modes, with typical power consumption down to 1.1 µA in Backup mode with RTC, RTT and wake-up logic enabled ̶ Ultra-low-power RTC and RTT ̶ 1 Kbyte of backup RAM (BRAM) with dedicated regulator  Peripherals ̶ One Ethernet MAC (GMAC) 10/100 Mbps in MII mode and RMII with dedicated DMA. IEEE1588 PTP frames and 802.3az Energy-efficiency support. Ethernet AVB support with IEEE802.1AS Time-stamping and IEEE802.1Qav credit-based traffic-shaping hardware support. ̶ USB 2.0 Device/Mini Host High-speed (USBHS) at 480 Mbps, 4-Kbyte FIFO, up to 10 bidirectional endpoints, dedicated DMA ̶ 12-bit ITU-R BT. 601/656 Image Sensor Interface (ISI) ̶ Two master Controller Area Networks (MCAN) with Flexible Data Rate (CAN-FD) with SRAM-based mailboxes, time- and event-triggered transmission ̶ Three USARTs. USART0/1/2 support LIN mode, ISO7816, IrDA ®, RS-485, SPI, Manchester and Modem modes; USART1 supports LON mode. ̶ Five 2-wire UARTs with SleepWalking support ̶ Three Two-Wire Interfaces (TWIHS) (I2C-compatible) with SleepWalking support ̶ Quad I/O Serial Peripheral Interface (QSPI) interfacing up to 256 MB Flash and with eXecute-In-Place and on- the-fly scrambling ̶ Two Serial Peripheral Interfaces (SPI) ̶ One Serial Synchronous Controller (SSC) with I2S and TDM support ̶ Two Inter-IC Sound Controllers (I2SC) ̶ One High-speed Multimedia Card Interface (HSMCI) (SDIO/SD Card/e.MMC) ̶ Four Three-Channel 16-bit Timer/Counters (TC) with Capture, Waveform, Compare and PWM modes, constant on time. Quadrature decoder logic and 2-bit Gray Up/Down Counter for stepper motor ̶ Two 4-channel 16-bit PWMs with complementary outputs, Dead Time Generator and eight fault inputs per PWM for motor control, two external triggers to manage power factor correction (PFC), DC-DC and lighting control. ̶ Two Analog Front-End Controllers (AFEC), each supporting up to 12 channels with differential input mode and programmable gain stage, allowing dual sample-and-hold at up to 2 Msps. Gain and offset error autotest feature. ̶ One 2-channel 12-bit 1Msps-per-channel Digital-to-Analog Controller (DAC) with differential and oversampling modes ̶ One Analog Comparator (ACC) with flexible input selection, selectable input hysteresis  Cryptography ̶ True Random Number Generator (TRNG) ̶ AES: 256-, 192-, 128-bit Key Algorithm, Compliant with FIPS PUB-197 Specifications ̶ Integrity Check Monitor (ICM). Supports Secure Hash Algorithm SHA1, SHA224 and SHA256.

3SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16  I/O ̶ Up to 114 I/O lines with external interrupt capability (edge- or level-sensitivity), debouncing, glitch filtering and On-die Series Resistor Termination ̶ Five Parallel Input/Output Controllers (PIO)  Voltage ̶ Single supply voltage from 1.7V to 3.6V  Packages ̶ LQFP144, 144-lead LQFP, 20 x 20 mm, pitch 0.5 mm ̶ LFBGA144, 144-ball LFBGA, 10 x 10 mm, pitch 0.8 mm ̶ UFBGA144, 144-ball UFBGA, 6 x 6 mm, pitch 0.4 mm(2) ̶ LQFP100, 100-lead LQFP, 14 x 14 mm, pitch 0.5 mm ̶ TFBGA100, 100-ball TFBGA, 9 x 9 mm, pitch 0.8 mm ̶ LQFP64, 64-lead LQFP, 10 x 10 mm, pitch 0.5 mm Notes: 1. 300 MHz is at [-40 °C : +105°C], 1.2V or with the internal regulator. 2. Contact your local Atmel sales representative for availability.

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 1. Description The Atmel | SMART SAM E70 devices are members of a family of Flash microcon trollers based on the high- performance 32-bit ARM Cortex-M7 processor with Floati ng Point Unit (FPU). These devices operate at up to 300 MHz and feature up to 2048 Kbytes of Flash and up to 384 Kbytes of multi-port SRAM. The on-chip SRAM can be configured as Tightly Coupled Memory (TCM) or system memory. A multi-port access to the SRAM guarantees a minimum access latency. The peripheral set includes an Ethernet MAC (GMAC) supporting AVB, IEEE1588, 802.1Qbb, 802.3az, 802.1AS and 802.1Qav, a high-speed USB Device port and a high-speed USB Host port sharing an embedded transceiver, an Image Sensor Interface (ISI), a high-speed Mult imedia Card Interface (HSMCI) for SDIO/SD/e.MMC, an External Bus Interface (EBI) featuring an SDRAM Controller, and a Static Memory Controller providing connection to SRAM, PSRAM, NOR Flash, LCD mo dule and NAND Flash. Additional peripherals include three Universal Synchronous Asynchronous Receiver Transmitters (USART) , five Universal Asynchronous Receiver Transmitters (UART), three Two-wire Interf aces (TWI) supporting the I 2C protocol, one Quad I/O Seri al Peripheral Interface (QSPI), two Serial Peripheral Interfac es (SPI), one Serial Synchronous Co ntroller (SSC) supporting I2S and TDM protocols, two Inter-IC Sound Controllers (I2SC), as well as two enhanced Pulse Width Modulators (PWM), twelve general-purpose 16-bit timers with stepper motor and quadrature decoder logic support, two Controller Area Networks with Flexible Data Rate (CAN-FD), one ultr a low-power Real-Time Timer (RTT), one ultra low-power Real-Time Clock (RTC), dual Analog Front-End (AFE) including a 12-bit Analog-to-Digital Converter (ADC), a Programmable Gain Amplifier (PGA), dual Sample-and-Hold and a digital averaging with up to 16-bit resolution, dual-channel 12-bit Digital-to-Analog C onverter (DAC) and one Analog Comparat or, as well as high-performance crypto-processors Advanced Encryption Standard (AES), Secure Hash Algorithm (SHA) and True Random Number Generator (TRNG). The SAM E70 devices have three software-selectable low-power modes: Sleep, Wait and Backup. In Sleep mode, the processor is stopped while all other functions can be kept runni ng. In Wait mode, all clocks and functions are stopped but some peripherals can be configured to wake up the system based on predefined conditions. This feature, called SleepWalking™, performs a partial asynchro nous wake-up, thus allowing the processor to wake up only when needed. In Backup mode, RTT, RTC and wake-u p logic are running. Optionally a 1-Kbyte low-power SRAM can be retained. To optimize power consumption, the clock system has been designed to support different clock frequencies for selected peripherals. Moreover, the processor and bus clock frequency can be modified without affecting processing on, for example, the USB, U(S)ART, AFE and Timer Counter. The SAM E70 devices also feature an event system that allows peripherals to receive, react to and send events in Active and Sleep modes without processor intervention. The SAM E70 devices are high-performance general-purpo se microcontrollers with a rich set of connectivity peripherals and large memory integration. This enab les the SAM E70 to sustain a wide range of applications including consumer, industrial control, and PC peripherals. SAM E70 devices operate from 1.7V to 3.6V and are pin-to-pin compatible with the SAM4E (100-pin and 144-pin versions), except for USB signals. The Atmel application note “Migrating the SAM4E to SAM E70 Microcontroller” (reference 44034) is available on www.atmel.com to ease migration from SAM4E devices to SAM E70 devices.

5SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 2. Configuration Summary The SAM E70 devices differ in memory size, package and features. Table 2-1 summarizes the different configurations. Table 2-1. Configuration Summary Feature SAME70Q21 SAME70Q20 SAME70Q19 SAME70N21 SAME70N20 SAME70N19 SAME70J21 SAME70J20 SAME70J19 Flash (Kbytes) 2048 1024 512 2048 1024 512 2048 1024 512 Flash Page Size (bytes) 512 Flash Pages 4096 2048 1024 4096 2048 1024 4096 2048 1024 Flash Lock Region Size (Kbytes) 16 Flash Lock Bits 128 64 32 128 64 32 128 64 32 Multi-port SRAM (Kbytes) 384 256 384 256 384 256 Cache(I/D) (Kbytes) 16/16 Package LQFP144 LFBGA144 UFBGA144 LQFP144 LFBGA144 UFBGA144 LQFP144 LFBGA144 UFBGA144 LQFP100 TFBGA100 LQFP100 TFBGA100 LQFP100 TFBGA100 LQFP64 LQFP64 LQFP64 Number of PIOs 114 75 44 External Bus Interface 16-bit data, 4 chip selects, 24-bit address – – SDRAM Interface Yes – – Central DMA 24 24 24 12-bit ADC 24 ch.(2) 10 ch.(2) 5 ch.(2) 12-bit DAC 2 ch. 2 ch. 1 ch. Timer Counter Channels 12 Timer Counter Channels I/O 36 9 3 USART/UART 3/5(1) 3/5(1) 0/5 QSPI Yes Yes SPI mode only SPI0 Yes Yes No

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 Notes: 1. LON support on USART1 only. 2. One channel is reserved for internal temperature sensor. SPI1 Yes No No USART SPI 3(1) 3(1) 0 TWIHS 332 HSMCI 1 port 4 bits 1 port 4 bits CAN 2 ports 2 ports 1 port GMAC MII, RMII MII, RMII RMII ISI 12-bit 12-bit 8-bit SSC Yes Yes Yes I2SC 210 USB High-speed High-speed Full-speed Analog Comparator Yes Yes Yes Embedded Trace Macrocell (ETM) Yes Yes Yes Table 2-1. Configuration Summary (Continued) Feature SAME70Q21 SAME70Q20 SAME70Q19 SAME70N21 SAME70N20 SAME70N19 SAME70J21 SAME70J20 SAME70J19

7SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 3. Block Diagram See Table 2-1 for detailed configurations of memory size, package and features of the SAM E70 devices. Figure 3-1. SAM E70 144-pin Block Diagram 12-layer Bus Matrix fMAX 150 MHz XDMA PCK0..2 XIN32 XOUT32ERASE VDDCORE VDDIO VDDOUT Voltage Regulator TST WKUP0..13 VDDIO XIN XOUT VDDPLL RTCOUT0RTCOUT1 SM MMMSSS S S M M M M M S System Controller SM In-Circuit Emulator MPU Cortex-M7 Processor fMAX 300 MHz NVIC FPU TPIU ETM

16 Kbytes ICache + ECC16 Kbytes DCache + ECC

Serial Wire Debug/JTAG Boundary Scan TRACECLK TRACED0..3 TMS/SWDIO NRST PIOA/B/C/D/E 24-channel XDMA ROM Boot Program Multi-port SRAM Flash

2048 Kbytes

1024 Kbytes

512 Kbytes

Static Memory Controller (SMC) SDRAM Controller (SDRAMC) NAND Flash Logic QSPI XIP DMA ISI GMAC MII/RMII 5 x UART 3 x TWIHS 3 x USART 2 x PWM 2 x 12-bit AFE ACC 12-bit DACPIO SSC HSMCI 2 x SPI 4 x TC XDMA DMA Peripheral Bridge URXD0..4 UTXD0..4 VREFN CANRX0..1 CANTX0..1 RXD0..2 SCK0..2 RTS0..2 TXD0..2 CTS0..2 DSR0..2, DTR0..2 RI0..2, DCD0..2 PIODCCLK PIODCEN1..2PIODC0..7 TF TK TD RD RK RF MCDA0..3 MCCDA MCCK SPIx_NPCS0..3 SPIx_MISO SPIx_MOSI SPIx_SPCK PWMCx_PWMH0..3 PWMCx_PWML0..3 PWMCx_PWMFI0..2PWMCx_PWMEXTRG0..1 AFEx_ADTRG AFEx_AD0..11 DAC0..1 DATRG TWD0..2 TWCK0..2 2 x MCAN GTXCK, GRXCK, GREFCK GCRS, GCOL, GCRSDV GMDC, GMDIO GTSUCOMP GRX0..3, GTX0..3 GRXER, GRXDV GTXER, GTXDV ISI_D[11:0] ISI_PCK, ISI_MCK ISI_HSYNC, ISI_VSYNC HSDP HSDM QMISO/QIO1 QMOSI/QIO0 QSCK, QCS QIO2..3 A[23:0], D[15:0] A21/NANDALE A22/NANDCLE NANDOE, NANDWE A0/NLB, NUB NWAIT, NCS0..3, NRD, NWE A16/SDBA0, A17/SDBA1 RAS, CAS, DQM0..1, SDCK, SDCKE, SDA10 DMA DMA Temp Sensor TIOB0..11 TCLK0..11 TIOA0..11 XDMAXDMAXDMAXDMAXDMAXDMAXDMAXDMAXDMA XDMA FIFO XDMA TRNGAES ICM/SHA DMA VREFP Backup RAM

1 Kbyte

0–256 Kbytes 128–384 Kbytes 0–256 Kbytes 2 x I2SC I2SCx_DI I2SCx_MCK I2SCx_CK I2SCx_WS XDMA I2SCx_DO PMC 4/8/12 MHz RC Oscillator RSTC SM POR SUPC RTTRTC WDT UPLL PLLA 3-20 MHz Crystal Oscillator 32 kHz Crystal Oscillator 32 kHz RC Oscillator Immediate Clear 256-bit SRAM (GPBR) Backup RSWDT

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 4. Signal Description Table 4-1 gives details on signal names classified by peripheral. Table 4-1. Signal Description List Signal Name Function Type Active Level Voltage Reference Comments Power Supplies VDDIO Peripherals I/O Lines Power Supply Power – – – VDDIN Voltage Regulator Input, ADC, DAC and Analog Comparator Power Supply(1) Power – – – VDDOUT Voltage Regulator Output Power – – – VDDPLL PLLA Power Supply Power – – – VDDPLLUSB USB PLL and Oscillator Power Supply Power – – – VDDCORE Powers the core, the embedded memories and the peripherals Power – – – GND, GNDPLL, GNDPLLUSB, GNDANA, GNDUTMI Ground Ground – – – VDDUTMII USB Transceiver Power Supply Power – – – VDDUTMIC USB Core Power Supply Power – – – GNDUTMI USB Ground Ground – – – Clocks, Oscillators and PLLs XIN Main Oscillator Input Input – VDDIO XOUT Main Oscillator Output Output – – XIN32 Slow Clock Oscillator Input Input – – XOUT32 Slow Clock Oscillator Output Output – – PCK0–PCK2 Programmable Clock Output Output – PCK3 is TRACE clock PCK4 is used for UART/USART baud rate PCK5 is used for CAN PCK6 is used for TC Real Time Clock RTCOUT0 Programmable RTC Waveform Output Output – VDDIO RTCOUT1 Programmable RTC Waveform Output Output – –

9SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 Serial Wire Debug/JTAG Boundary Scan SWCLK/TCK Serial Wire Clock / Test Clock (Boundary scan mode only) Input – VDDIO TDI Test Data In (Boundary scan mode only) Input – – TDO/TRACESWO Test Data Out (Boundary scan mode only) Output – – SWDIO/TMS Serial Wire Input/Output / Test Mode Select (Boundary scan mode only) I/O / Input – – JTAGSEL JTAG Selection Input High – Trace Debug Port TRACECLK Trace Clock Output – VDDIO TRACECLK is PCK3 TRACED0–TRACED3 Trace Data Output – Flash Memory ERASE Flash and NVM Configuration Bits Erase Command Input High VDDIO – Reset/Test NRST Synchronous Microcontroller Reset I/O Low VDDIO TST Test Select Input – – Universal Asynchronous Receiver Transceiver - UART(x=[0:4]) URXDx UART Receive Data Input – – USPCK = PCK4 can be used to generate the baud rateUTXDx UART Transmit Data Output – – PIO Controller - PIOA - PIOB - PIOC - PIOD - PIOE PA0–PA31 Parallel IO Controller A I/O – VDDIO PB0–PB9, PB12–PB13 Parallel IO Controller B I/O – – PC0– PC31 Parallel IO Controller C I/O – – PD0–PD31 Parallel IO Controller D I/O – – – PE0–PE5 Parallel IO Controller E I/O – – – PIO Controller - Parallel Capture Mode PIODC0–PIODC7 Parallel Capture Mode Data Input – VDDIO PIODCCLK Parallel Capture Mode Clock Input – – PIODCEN1–PIODCEN2 Parallel Capture Mode Enable Input – – External Bus Interface D[15:0] Data Bus I/O – – – A[23:0] Address Bus Output – – – NWAIT External Wait Signal Input Low – – Table 4-1. Signal Descrip tion List (Continued) Signal Name Function Type Active Level Voltage Reference Comments

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 Static Memory Controller - SMC NCS0–NCS3 Chip Select Lines Output Low – – NRD Read Signal Output Low – – NWE Write Enable Output Low – – NWR0–NWR1 Write Signal Output Low – – NBS0–NBS1 Byte Mask Signal Outp ut Low – Used also for SDRAMC NAND Flash Logic NANDOE NAND Flash Output Enable Output Low – – NANDWE NAND Flash Write Enable Output Low – – SDR-SDRAM Controller Logic SDCK SDRAM Clock Output – – – SDCKE SDRAM Clock Enable Output – – – SDCS SDRAM Controller Chip Select Output – – – BA0–BA1 Bank Select Output – – – SDWE SDRAM Write Enable Output – – – RAS–CAS Row and Column Signal Output – – – SDA10 SDRAM Address 10 Line Output – – – High Speed Multimedia Card Interface - HSMCI MCCK Multimedia Card Clock I/O – – – MCCDA Multimedia Card Slot A Command I/O – – – MCDA0–MCDA3 Multimedia Card Slot A Data I/O – – – Universal Synchronous Asynchronous Receiver Transmitter USART(x=[0:2]) SCKx USARTx Serial Clock I/O – – USPCK = PCK4 can be used to generate the baud rate TXDx USARTx Transmit Data I/O – – RXDx USARTx Receive Data Input – – RTSx USARTx Request To Send Output – – CTSx USARTx Clear To Send Input – – DTRx USARTx Data Terminal Ready Output – – DSRx USARTx Data Set Ready Input – – DCDx USARTx Data Carrier Detect Input – – RIx USARTx Ring Indicator Input – – LONCOL1 LON Collision Detection Input – – Synchronous Serial Controller - SSC TD SSC Transmit Data Output – – – RD SSC Receive Data Input – – – TK SSC Transmit Clock I/O – – – Table 4-1. Signal Descrip tion List (Continued) Signal Name Function Type Active Level Voltage Reference Comments

11SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 RK SSC Receive Clock I/O – – – TF SSC Transmit Frame Sync I/O – – – RF SSC Receive Frame Sync I/O – – – Inter-IC Sound Controller - I2SC[1..0] I2SCx_MCK Master Clock Output – VDDIO – I2SCx_CK Serial Clock I/O – VDDIO – I2SCx_WS I2S Word Select I/O – VDDIO – I2SCx_DI Serial Data Input Input – VDDIO – I2SCx_DO Serial Data Output Output – VDDIO – Image Sensor Interface - ISI ISI_D0–ISI_D11 Image Sensor Data Input – – – ISI_MCK Image sensor Reference clock. No dedicated signal, PCK1 can be used. Output – – – ISI_HSYNC Image Sensor Horizontal Synchro Input – – – ISI_VSYNC Image Sensor Vertical Synchro Input – – – ISI_PCK Image Sensor Data clock Input – – – Timer/Counter - TC(x=[0:11]) TCLKx TC Channel x External Clock Input Input – – TCPCK = PCK6 can be used as an input clockTIOAx TC Channel x I/O Line A I/O – – TIOBx TC Channel x I/O Line B I/O – – Pulse Width Modulation Controller- PWMC(x=[0..1]) PWMCx_PWMH0– PWMCx_PWMH3 Waveform Output High for Channel 0–3 Output – – – PWMCx_PWML0– PWMCx_PWML3 Waveform Output Low for Channel 0–3 Output – – Only output in complementary mode when dead time insertion is enabled. PWMCx_PWMFI0– PWMCx_PWMFI2 Fault Input Input – – – PWMCx_PWMEXTRG0– PWMCx_PWMEXTRG1 External Trigger Input Input – – – Serial Peripheral Interface - SPI(x=[0..1]) SPIx_MISO Master In Slave Out I/O – – – SPIx_MOSI Master Out Slave In I/O – – – SPIx_SPCK SPI Serial Clock I/O – – – SPIx_NPCS0 SPI Peripheral Chip Select 0 I/O Low – – Table 4-1. Signal Descrip tion List (Continued) Signal Name Function Type Active Level Voltage Reference Comments

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 SPIx_NPCS1– SPIx_NPCS3 SPI Peripheral Chip Select Output Low – – Quad IO SPI - QSPI QSCK QSPI Serial Clock Output – – – QCS QSPI Chip Select Output – – – QIO0–QIO3 QSPI I/O QIO0 is QMOSI Master Out Slave In QIO1 is QMISO Master In Slave Out I/O – – – Two-Wire Interface - TWIHS(x=0..2) TWDx TWIx Two-wire Serial Data I/O – – – TWCKx TWIx Two-wire Serial Clock I/O – – – Analog VREFP ADC, DAC and Analog Comparator Positive Reference Analog – – – VREFN ADC, DAC and Analog Comparator Negative Reference Must be connected to GND or GNDANA. Analog – – – 12-bit Analog Front End - (x=[0..1]) AFEx_AD0–AFEx_AD11 Analog Inputs Analog, Digital –– – AFEx_ADTRG ADC Trigger Input – VDDIO – 12-bit Digital-to-Analog Converter - DAC DAC0–DAC1 Analog Output Analog, Digital –– – DATRG DAC Trigger Input – VDDIO – Fast Flash Programming Interface - FFPI PGMEN0–PGMEN1 Programming Enabling Input – VDDIO – PGMM0–PGMM3 Programming Mode Input – VDDIO PGMD0–PGMD15 Programming Data I/O – – PGMRDY Programming Ready Output High – PGMNVALID Data Direction Output Low – PGMNOE Programming Read Input Low – PGMNCMD Programming Command Input Low – USB High Speed - USBHS HSDM USB High Speed Data - Analog, Digital VDDUTMII HSDP USB High Speed Data + – – VBG Bias Voltage Reference for USB Analog – – – Table 4-1. Signal Descrip tion List (Continued) Signal Name Function Type Active Level Voltage Reference Comments

13SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 Note: 1. Refer to Section 6.5 “Active Mode” for restrictions on the voltage range of analog cells. Ethernet MAC 10/100 - GMAC GREFCK Reference Clock Input – – RMII only GTXCK Transmit Clock Input – – MII only GRXCK Receive Clock Input – – MII only GTXEN Transmit Enable Output – – – GTX0 - GTX3 Transmit Data Output – – GTX0–GTX1 only in RMII GTXER Transmit Coding Error Output – – MII only GRXDV Receive Data Valid Input – – MII only GRX0 - GRX3 Receive Data Input – – GRX0–GRX1 only in RMII GRXER Receive Error Input – – – GCRS Carrier Sense Input – – MII only GCOL Collision Detected Input – – MII only GMDC Management Data Clock Output – – – GMDIO Management Data Input/Output I/O – – – GTSUCOMP TSU timer comparison valid Output – – – Controller Area Network - CAN (x=[0:1]) CANRXx CAN Receive Input – – CANRX1 is available on PD28 for 100-pin only CANRX1 is available on PC12 for 144-pin only CANTXx CAN Transmit Output – – CANPCK = PCK5 can be used Table 4-1. Signal Descrip tion List (Continued) Signal Name Function Type Active Level Voltage Reference Comments

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 5. Package and Pinout In the tables that follow, the column “Reset State” indicates the reset state of the line with mnemonics. Indicates whether the PIO Line resets in I/O mode or in peripheral mode. If “PIO” is mentioned, the PIO line is maintained in a static state as soon as the reset is released. As a result, the bit corresponding to the PIO line in the register PIO_PSR (Peripheral Status Register) resets low. If a signal name is mentioned in the “Reset State” column , the PIO line is assigned to this function and the corresponding bit in PIO_PSR resets high. This is the ca se of pins controlling memories, in particular the address lines, which require the pin to be driven as soon as the reset is released. Indicates whether the signal is input or output state. Indicates whether Pull-Up, Pull-Down or nothing is enabled.  “ST” Indicates if Schmitt Trigger is enabled.

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 16 5.2 144-lead Package Pinout Table 5-1. 144-lead Package Pinout LQFP Pin LFBGA Ball UFBGA Ball Power Rail I/O Type Primary Alternate PIO Peripheral A PIO Peripheral B PIO Peripheral C PIO Peripheral D Reset State Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir Signal, Dir, PU, PD, HiZ, ST

102 C11 E11 VDDIO GPIO_AD PA0 I/O WKUP0(1) I PWMC0_PWMH0 O TIOA0 I/O A17/BA1 O I2SC0_MCK – PIO, I, PU, ST

99 D12 F11 VDDIO GPIO_AD PA1 I/O WKUP1(1) I PWMC0_PWML0 O TIOB0 I/O A18 O I2SC0_CK – PIO, I, PU, ST

93 E12 G12 VDDIO GPIO PA2 I/O WKUP2(1) I PWMC0_PWMH1 O – – DATRG I – – PIO, I, PU, ST

91 F12 G11 VDDIO GPIO_AD PA3 I/O PIODC0(2) I TWD0 I/O LONCOL1 I PCK2 O – – PIO, I, PU, ST

77 K12 L12 VDDIO GPIO PA4 I/O WKUP3/PIODC1(3) I TWCK0 O TCLK0 I UTXD1 O – – PIO, I, PU, ST

73 M11 N13 VDDIO GPIO_AD PA5 I/O WKUP4/PIODC2(3) I PWMC1_PWML3 O ISI_D4 I URXD1 I – – PIO, I, PU, ST

114 B9 B11 VDDIO GPIO_AD PA6 I/O – – – – PCK0 O UTXD1 O – – PIO, I, PU, ST

35 L2 N1 VDDIO CLOCK PA7 I/O XIN32(4) I – – PWMC0_PWMH3 O – – – – PIO, HiZ

36 M2 N2 VDDIO CLOCK PA8 I/O XOUT32(4) O PWMC1_PWMH3 O AFE0_ADTRG I – – – – PIO, HiZ

75 M12 L11 VDDIO GPIO_AD PA9 I/O WKUP6/PIODC3(3) I URXD0 I ISI_D3 I PWMC0_PWMFI0 I – – PIO, I, PU, ST

66 L9 M10 VDDIO GPIO_AD PA10 I/O PIODC4(2) I UTXD0 O PWMC0_PWMEXTRG0 I RD I – – PIO, I, PU, ST

64 J9 N10 VDDIO GPIO_AD PA11 I/O WKUP7/PIODC5(3) I QCS O PWMC0_PWMH0 O PWMC1_PWML0 O – – PIO, I, PU, ST

68 L10 N11 VDDIO GPIO_AD PA12 I/O PIODC6(2) I QIO1 I/O PWMC0_PWMH1 O PWMC1_PWMH0 O – – PIO, I, PU, ST

42 M3 M4 VDDIO GPIO_AD PA13 I/O PIODC7(2) I QIO0 I/O PWMC0_PWMH2 O PWMC1_PWML1 O – – PIO, I, PU, ST

51 K6 M6 VDDIO GPIO_CLK PA14 I/O WKUP8/PIODCEN1(3) I QSCK O PWMC0_PWMH3 O PWMC1_PWMH1 O – – PIO, I, PU, ST

49 L5 N6 VDDIO GPIO_AD PA15 I/O – – D14 I/O TIOA1 I/O PWMC0_PWML3 O I2SC0_WS – PIO, I, PU, ST

45 K5 L4 VDDIO GPIO_AD PA16 I/O – – D15 I/O TIOB1 I/O PWMC0_PWML2 O I2SC0_DI – PIO, I, PU, ST

25 J1 J4 VDDIO GPIO_AD PA17 I/O AFE0_AD6(5) I QIO2 I/O PCK1 O PWMC0_PWMH3 O – – PIO, I, PU, ST

24 H2 J3 VDDIO GPIO_AD PA18 I/O AFE0_AD7(5) I PWMC1_PWMEXTRG1 I PCK2 O A14 O – – PIO, I, PU, ST

23 H1 J2 VDDIO GPIO_AD PA19 I/O AFE0_AD8/WKUP9(6) I – – PWMC0_PWML0 O A15 O I2SC1_MCK – PIO, I, PU, ST

22 H3 J1 VDDIO GPIO_AD PA20 I/O AFE0_AD9/WKUP10(6) I – – PWMC0_PWML1 O A16/BA0 O I2SC1_CK – PIO, I, PU, ST

32 K2 M1 VDDIO GPIO_AD PA21 I/O AFE0_AD1/

PIODCEN2(8) I RXD1 I PCK1 O PWMC1_PWMFI0 I – – PIO, I, PU, ST

37 K3 M2 VDDIO GPIO_AD PA22 I/O PIODCCLK(2) I RK I/O PWMC0_PWMEXTRG1 I NCS2 O – – PIO, I, PU, ST

46 L4 N5 VDDIO GPIO_AD PA23 I/O – – SCK1 I/O PWMC0_PWMH0 O A19 O PWMC1_PWML2 O PIO, I, PU, ST

56 L7 N8 VDDIO GPIO_AD PA24 I/O – – RTS1 O PWMC0_PWMH1 O A20 O ISI_PCK I PIO, I, PU, ST

59 K8 L8 VDDIO GPIO_AD PA25 I/O – – CTS1 I PWMC0_PWMH2 O A23 O MCCK O PIO, I, PU, ST

62 J8 M9 VDDIO GPIO PA26 I/O – – DCD1 I TIOA2 O MCDA2 I/O PWMC1_PWMFI1 I PIO, I, PU, ST

70 J10 N12 VDDIO GPIO_AD PA27 I/O – – DTR1 O TIOB2 I/O MCDA3 I/O ISI_D7 I PIO, I, PU, ST

112 C9 C11 VDDIO GPIO PA28 I/O – – DSR1 I TCLK1 I MCCDA I/O PWMC1_PWMFI2 I PIO, I, PU, ST

129 A6 A7 VDDIO GPIO PA29 I/O – – RI1 I TCLK2 I – – – – PIO, I, PU, ST

116 A10 A11 VDDIO GPIO PA30 I/O WKUP11(1) I PWMC0_PWML2 O PWMC1_PWMEXTRG0 I MCDA0 I/O I2SC0_DO – PIO, I, PU, ST

17SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

118 C8 C10 VDDIO GPIO_AD PA31 I/O – – SPI0_NPCS1 I/O PCK2 O MCDA1 I/O PWMC1_PWMH2 O PIO, I, PU, ST

21 H4 H2 VDDIO GPIO PB0 I/O AFE0_AD10/

RTCOUT0(7) I PWMC0_PWMH0 O – – RXD0 I TF I/O PIO, I, PU, ST

20 G3 H1 VDDIO GPIO PB1 I/O AFE1_AD0/

RTCOUT1(7) I PWMC0_PWMH1 O GTSUCOMP O TXD0 I/O TK I/O PIO, I, PU, ST

26 J2 K1 VDDIO GPIO PB2 I/O AFE0_AD5(5) I CANTX0 O – – CTS0 I SPI0_NPCS0 I/O PIO, I, PU, ST

31 J3 L1 VDDIO GPIO_AD PB3 I/O AFE0_AD2/WKUP12(6) I CANRX0 I PCK2 O RTS0 O ISI_D2 I PIO, I, PU, ST

105 A12 C13 VDDIO GPIO_MLB PB4 I/O TDI(9) I TWD1 I/O PWMC0_PWMH2 O – – TXD1 I/O PIO, I, PD, ST

109 C10 C12 VDDIO GPIO_MLB PB5 I/O TDO/TRACESWO/

WKUP13(9) O TWCK1 O PWMC0_PWML0 O – – TD O O, PU

79 J11 K11 VDDIO GPIO PB6 I/O SWDIO/TMS(9) I – – – – – – – – PIO,I,ST

89 F9 H13 VDDIO GPIO PB7 I/O SWCLK/TCK(9) I – – – – – – – – PIO,I,ST

141 A3 B2 VDDIO CLOCK PB8 I/O XOUT(10) O – – – – – – – – PIO, HiZ

142 A2 A2 VDDIO CLOCK PB9 I/O XIN(10) I – – – – – – – – PIO, HiZ

87 G12 J10 VDDIO GPIO PB12 I/O ERASE(9) I PWMC0_PWML1 O GTSUCOMP O – – PCK0 O PIO, I, PD, ST

144 B2 A1 VDDIO GPIO_AD PB13 I/O DAC0(11) O PWMC0_PWML2 O PCK0 O SCK0 I/O – – PIO, I, PU, ST

11 E4 F2 VDDIO GPIO_AD PC0 I/O AFE1_AD9(5) I D0 I/O PWMC0_PWML0 O – – – – PIO, I, PU, ST

38 J4 M3 VDDIO GPIO_AD PC1 I/O – – D1 I/O PWMC0_PWML1 O – – – – PIO, I, PU, ST

39 K4 N3 VDDIO GPIO_AD PC2 I/O – – D2 I/O PWMC0_PWML2 O – – – – PIO, I, PU, ST

40 L3 N4 VDDIO GPIO_AD PC3 I/O – – D3 I/O PWMC0_PWML3 O – – – – PIO, I, PU, ST

41 J5 L3 VDDIO GPIO_AD PC4 I/O – – D4 I/O – – – – – – PIO, I, PU, ST

58 L8 M8 VDDIO GPIO_AD PC5 I/O – – D5 I/O TIOA6 I/O – – – – PIO, I, PU, ST

54 K7 L7 VDDIO GPIO_AD PC6 I/O – – D6 I/O TIOB6 I/O – – – – PIO, I, PU, ST

48 M4 L5 VDDIO GPIO_AD PC7 I/O – – D7 I/O TCLK6 I – – – – PIO, I, PU, ST

82 J12 K13 VDDIO GPIO_AD PC8 I/O – – NWR0/NWE O TIOA7 I/O – – – – PIO, I, PU, ST

86 G11 J11 VDDIO GPIO_AD PC9 I/O – – NANDOE O TIOB7 I/O – – – – PIO, I, PU, ST

90 F10 H12 VDDIO GPIO_AD PC10 I/O – – NANDWE O TCLK7 I – – – – PIO, I, PU, ST

94 F11 F13 VDDIO GPIO_AD PC11 I/O – – NRD O TIOA8 I/O – – – – PIO, I, PU, ST

17 F4 G2 VDDIO GPIO_AD PC12 I/O AFE1_AD3(5) I NCS3 O TIOB8 I/O CANRX1 I – – PIO, I, PU, ST

19 G2 H3 VDDIO GPIO_AD PC13 I/O AFE1_AD1(5) I NWAIT I PWMC0_PWMH3 O SDA10 O – – PIO, I, PU, ST

97 E10 F12 VDDIO GPIO_AD PC14 I/O – – NCS0 O TCLK8 I CANTX1 O – – PIO, I, PU, ST

18 G1 H4 VDDIO GPIO_AD PC15 I/O AFE1_AD2(5) I NCS1/SDCS O PWMC0_PWML3 O – – – – PIO, I, PU, ST

100 D11 E12 VDDIO GPIO_AD PC16 I/O – – A21/NANDALE O – – – – – – PIO, I, PU, ST

103 B12 E10 VDDIO GPIO_AD PC17 I/O – – A22/NANDCLE O – – – – – – PIO, I, PU, ST

111 B10 B12 VDDIO GPIO_AD PC18 I/O – – A0/NBS0 O PWMC0_PWML1 O – – – – PIO, I, PU, ST

Table 5-1. 144-lead Packag e Pinout (Continued) LQFP Pin LFBGA Ball UFBGA Ball Power Rail I/O Type Primary Alternate PIO Peripheral A PIO Peripheral B PIO Peripheral C PIO Peripheral D Reset State Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir Signal, Dir, PU, PD, HiZ, ST

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

117 D8 B10 VDDIO GPIO_AD PC19 I/O – – A1 O PWMC0_PWMH2 O – – – – PIO, I, PU, ST

120 A9 C9 VDDIO GPIO_AD PC20 I/O – – A2 O PWMC0_PWML2 O – – – – PIO, I, PU, ST

122 A7 A9 VDDIO GPIO_AD PC21 I/O – – A3 O PWMC0_PWMH3 O – – – – PIO, I, PU, ST

124 C7 A8 VDDIO GPIO_AD PC22 I/O – – A4 O PWMC0_PWML3 O – – – – PIO, I, PU, ST

127 C6 C7 VDDIO GPIO_AD PC23 I/O – – A5 O TIOA3 I/O – – – – PIO, I, PU, ST

130 B6 D7 VDDIO GPIO_AD PC24 I/O – – A6 O TIOB3 I/O SPI1_SPCK O – – PIO, I, PU, ST

133 C5 C6 VDDIO GPIO_AD PC25 I/O – – A7 O TCLK3 I SPI1_NPCS0 I/O – – PIO, I, PU, ST

13 F2 F4 VDDIO GPIO_AD PC26 I/O AFE1_AD7(5) I A8 O TIOA4 I/O SPI1_MISO I – – PIO, I, PU, ST

12 E2 F3 VDDIO GPIO_AD PC27 I/O AFE1_AD8(5) I A9 O TIOB4 I/O SPI1_MOSI O – – PIO, I, PU, ST

76 L12 L13 VDDIO GPIO_AD PC28 I/O – – A10 O TCLK4 I SPI1_NPCS1 I/O – – PIO, I, PU, ST

16 F3 G1 VDDIO GPIO_AD PC29 I/O AFE1_AD4(5) I A11 O TIOA5 I/O SPI1_NPCS2 O – – PIO, I, PU, ST

15 F1 G3 VDDIO GPIO_AD PC30 I/O AFE1_AD5(5) I A12 O TIOB5 I/O SPI1_NPCS3 O – – PIO, I, PU, ST

14 E1 G4 VDDIO GPIO_AD PC31 I/O AFE1_AD6(5) I A13 O TCLK5 I – – – – PIO, I, PU, ST

1 D4 B1 VDDIO GPIO_AD PD0 I/O DAC1(11) I GTXCK I PWMC1_PWML0 O SPI1_NPCS1 I/O DCD0 I PIO, I, PU, ST

132 B5 B6 VDDIO GPIO PD1 I/O – – GTXEN O PWMC1_PWMH0 O SPI1_NPCS2 I/O DTR0 O PIO, I, PU, ST

131 A5 A6 VDDIO GPIO PD2 I/O – – GTX0 O PWMC1_PWML1 O SPI1_NPCS3 I/O DSR0 I PIO, I, PU, ST

128 B7 B7 VDDIO GPIO PD3 I/O – – GTX1 O PWMC1_PWMH1 O UTXD4 O RI0 I PIO, I, PU, ST

126 D6 C8 VDDIO GPIO_CLK PD4 I/O – – GRXDV I PWMC1_PWML2 O TRACED0 O DCD2 I PIO, I, PU, ST

125 D7 B8 VDDIO GPIO_CLK PD5 I/O – – GRX0 I PWMC1_PWMH2 O TRACED1 O DTR2 O PIO, I, PU, ST

121 A8 B9 VDDIO GPIO_CLK PD6 I/O – – GRX1 I PWMC1_PWML3 O TRACED2 O DSR2 I PIO, I, PU, ST

119 B8 A10 VDDIO GPIO_CLK PD7 I/O – – GRXER I PWMC1_PWMH3 O TRACED3 O RI2 I PIO, I, PU, ST

113 E9 A12 VDDIO GPIO_CLK PD8 I/O – – GMDC O PWMC0_PWMFI1 I – – TRACECLK O PIO, I, PU, ST

110 D9 A13 VDDIO GPIO_CLK PD9 I/O – – GMDIO I/O PWMC0_PWMFI2 I AFE1_ADTRG I – – PIO, I, PU, ST

101 C12 D13 VDDIO GPIO_MLB PD10 I/O – – GCRS I PWMC0_PWML0 O TD O – – PIO, I, PD, ST

98 E11 E13 VDDIO GPIO_AD PD11 I/O – – GRX2 I PWMC0_PWMH0 O GTSUCOMP O ISI_D5 I PIO, I, PU, ST

92 G10 G13 VDDIO GPIO_AD PD12 I/O – – GRX3 I CANTX1 O SPI0_NPCS2 O ISI_D6 I PIO, I, PU, ST

88 G9 H11 VDDIO GPIO_CLK PD13 I/O – – GCOL I – – SDA10 O – – PIO, I, PU, ST

84 H10 J12 VDDIO GPIO_AD PD14 I/O – – GRXCK I – – SDCKE O – – PIO, I, PU, ST

106 A11 D11 VDDIO GPIO_AD PD15 I/O – – GTX2 O RXD2 I NWR1/NBS1 O – – PIO, I, PU, ST

78 K11 K10 VDDIO GPIO_AD PD16 I/O – – GTX3 O TXD2 I/O RAS O – – PIO, I, PU, ST

74 L11 M13 VDDIO GPIO_AD PD17 I/O – – GTXER O SCK2 I/O CAS O – – PIO, I, PU, ST

69 M10 M11 VDDIO GPIO_AD PD18 I/O – – NCS1/SDCS O RTS2 O URXD4 I – – PIO, I, PU, ST

67 M9 L10 VDDIO GPIO_AD PD19 I/O – – NCS3 O CTS2 I UTXD4 O – – PIO, I, PU, ST

Table 5-1. 144-lead Packag e Pinout (Continued) LQFP Pin LFBGA Ball UFBGA Ball Power Rail I/O Type Primary Alternate PIO Peripheral A PIO Peripheral B PIO Peripheral C PIO Peripheral D Reset State Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir Signal, Dir, PU, PD, HiZ, ST

19SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

65 K9 K9 VDDIO GPIO PD20 I/O – – PWMC0_PWMH0 O SPI0_MISO I/O GTSUCOMP O – – PIO, I, PU, ST

63 H9 L9 VDDIO GPIO_AD PD21 I/O – – PWMC0_PWMH1 O SPI0_MOSI I/O TIOA11 I/O ISI_D1 I PIO, I, PU, ST

60 M8 N9 VDDIO GPIO_AD PD22 I/O – – PWMC0_PWMH2 O SPI0_SPCK O TIOB11 I/O ISI_D0 I PIO, I, PU, ST

57 M7 N7 VDDIO GPIO_CLK PD23 I/O – – PWMC0_PWMH3 O – – SDCK O – – PIO, I, PU, ST

55 M6 K7 VDDIO GPIO_AD PD24 I/O – – PWMC0_PWML0 O RF I/O TCLK11 I ISI_HSYNC I PIO, I, PU, ST

52 M5 L6 VDDIO GPIO_AD PD25 I/O – – PWMC0_PWML1 O SPI0_NPCS1 I/O URXD2 I ISI_VSYNC I PIO, I, PU, ST

53 L6 M7 VDDIO GPIO PD26 I/O – – PWMC0_PWML2 O TD O UTXD2 O UTXD1 O PIO, I, PU, ST

47 J6 M5 VDDIO GPIO_AD PD27 I/O – – PWMC0_PWML3 O SPI0_NPCS3 O TWD2 O ISI_D8 I PIO, I, PU, ST

71 K10 M12 VDDIO GPIO_AD PD28 I/O WKUP5(1) I URXD3 I CANRX1 I TWCK2 O ISI_D9 I PIO, I, PU, ST

108 D10 B13 VDDIO GPIO_AD PD29 I/O – – – – – – SDWE O – – PIO, I, PU, ST

34 M1 L2 VDDIO GPIO_AD PD30 I/O AFE0_AD0(5) I UTXD3 0 – – – – ISI_D10 I PIO, I, PU, ST

2 D3 C3 VDDIO GPIO_AD PD31 I/O – – QIO3 I/O UTXD3 O PCK2 O ISI_D11 I PIO, I, PU, ST

4 C2 C2 VDDIO GPIO_AD PE0 I/O AFE1_AD11(5) I D8 I/O TIOA9 I/O I2SC1_WS – – – PIO, I, PU, ST

6 A1 D2 VDDIO GPIO_AD PE1 I/O – – D9 I/O TIOB9 I/O I2SC1_DO – – – PIO, I, PU, ST

7 B1 D1 VDDIO GPIO_AD PE2 I/O – – D10 I/O TCLK9 I I2SC1_DI – – – PIO, I, PU, ST

10 E3 F1 VDDIO GPIO_AD PE3 I/O AFE1_AD10(5) I D11 I/O TIOA10 I/O – – – – PIO, I, PU, ST

27 K1 K2 VDDIO GPIO_AD PE4 I/O AFE0_AD4(5) I D12 I/O TIOB10 I/O – – – – PIO, I, PU, ST

28 L1 K3 VDDIO GPIO_AD PE5 I/O AFE0_AD3(5) I D13 I/O TCLK10 I/O – – – – PIO, I, PU, ST

83 H12 K12 VDDIO RST NRST I/O – – – – – – – – – – I, PU

85 H11 J13 VDDIO TEST TST I – – – – – – – – – – I, PD

30,43,72, 80,96 G8, H6, H7 D6, F10, K6 VDDIO Power VDDIO – – – – – – – – – – – –

104 B11 D12 VDDIO TEST JTAGSEL I – – – – – – – – – – I, PD

29,33,50, 81,107 E8, H5, H8 D5, G10,

136 B4 A5 VDDUTMII USBHS HSDM I/O – – – – – – – – – – –

137 A4 A4 VDDUTMII USBHS HSDP I/O – – – – – – – – – – –

Table 5-1. 144-lead Packag e Pinout (Continued) LQFP Pin LFBGA Ball UFBGA Ball Power Rail I/O Type Primary Alternate PIO Peripheral A PIO Peripheral B PIO Peripheral C PIO Peripheral D Reset State Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir Signal, Dir, PU, PD, HiZ, ST

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 Notes: 1. WKUPx can be used if the PIO Controller defines the I/O line as "input". 2. To select this extr a function, refer to Section 32.5.14 “Parallel Capture Mode”. 4. Refer to Section 22.4.2 “Slow Clock Generator”. 5. To select this extr a function, refer to Section 50.5.1 “I/O Lines”. the I/O line as "input". to select RTCOUTx. “Parallel Capture Mode”. 9. Refer to the System I/O Configuration Register in Section 18. “Bus Matrix (MATRIX)”. 10. Refer to Section 30.5.3 “3 to 20 MHz Crystal or Ceramic Resonator-based Oscillator”. Register”. 44,61,95, 115,135,138 F5, F6, G4, G5, G6, G7 C5, D3, D10, H10, K4, K8 Table 5-1. 144-lead Packag e Pinout (Continued) LQFP Pin LFBGA Ball UFBGA Ball Power Rail I/O Type Primary Alternate PIO Peripheral A PIO Peripheral B PIO Peripheral C PIO Peripheral D Reset State Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir Signal, Dir, PU, PD, HiZ, ST

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 22 5.4 100-lead Package Pinout Table 5-2. 100-lead Package Pinout LQFP Pin TFBGA Ball Power Rail I/O Type Primary Alternate PIO Peripheral A PIO Peripheral B PIO Peripheral C PIO Peripheral D Reset State Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir Signal, Dir, PU, PD, HiZ, ST

72 D8 VDDIO GPIO_AD PA0 I/O WKUP0(1) I PWMC0_PWMH0 O TIOA0 I/O A17/BA1 O I2SC0_MCK – PIO, I, PU, ST

70 C10 VDDIO GPIO_AD PA1 I/O WKUP1(1) I PWMC0_PWML0 O TIOB0 I/O A18 O I2SC0_CK – PIO, I, PU, ST

66 D10 VDDIO GPIO PA2 I/O WKUP2(1) I PWMC0_PWMH1 O – – DATRG I – – PIO, I, PU, ST

64 F9 VDDIO GPIO_AD PA3 I/O PIODC0(2) I TWD0 I/O LONCOL1 I PCK2 O – – PIO, I, PU, ST

55 H10 VDDIO GPIO PA4 I/O WKUP3/PIODC1(3) I TWCK0 O TCLK0 I UTXD1 O – – PIO, I, PU, ST

52 H9 VDDIO GPIO_AD PA5 I/O WKUP4/PIODC2(3) I PWMC1_PWML3 O ISI_D4 I URXD1 I – – PIO, I, PU, ST

24 J2 VDDIO CLOCK PA7 I/O XIN32(4) I – – PWMC0_PWMH3 – – – – – PIO, HiZ

25 K2 VDDIO CLOCK PA8 I/O XOUT32(4) O PWMC1_PWMH3 O AFE0_ADTRG I – – – – PIO, HiZ

54 J9 VDDIO GPIO_AD PA9 I/O WKUP6/PIODC3(3) I URXD0 I ISI_D3 I PWMC0_PWMFI0 I – – PIO, I, PU, ST

46 K9 VDDIO GPIO_AD PA10 I/O PIODC4(2) I UTXD0 O PWMC0_PWMEXTRG0 I RD I – – PIO, I, PU, ST

44 J8 VDDIO GPIO_AD PA11 I/O WKUP7/PIODC5(3) I QCS O PWMC0_PWMH0 O PWMC1_PWML0 O – – PIO, I, PU, ST

48 K10 VDDIO GPIO_AD PA12 I/O PIODC6(2) I QIO1 I/O PWMC0_PWMH1 O PWMC1_PWMH0 O – – PIO, I, PU, ST

27 G5 VDDIO GPIO_AD PA13 I/O PIODC7(2) I QIO0 I/O PWMC0_PWMH2 O PWMC1_PWML1 O – – PIO, I, PU, ST

34 H6 VDDIO GPIO_CLK PA14 I/O WKUP8/PIODCEN1(3) I QSCK O PWMC0_PWMH3 O PWMC1_PWMH1 O – – PIO, I, PU, ST

33 J6 VDDIO GPIO_AD PA15 I/O – – D14 I/O TIOA1 I/O PWMC0_PWML3 O I2SC0_WS – PIO, I, PU, ST

30 J5 VDDIO GPIO_AD PA16 I/O – – D15 I/O TIOB1 I/O PWMC0_PWML2 O I2SC0_DI – PIO, I, PU, ST

16 G1 VDDIO GPIO_AD PA17 I/O AFE0_AD6(5) I QIO2 I/O PCK1 O PWMC0_PWMH3 O – – PIO, I, PU, ST

15 G2 VDDIO GPIO_AD PA18 I/O AFE0_AD7(5) I PWMC1_PWMEXTRG1 I PCK2 O A14 O – – PIO, I, PU, ST

14 F1 VDDIO GPIO_AD PA19 I/O AFE0_AD8/WKUP9(6) I – – PWMC0_PWML0 O A15 O I2SC1_MCK – PIO, I, PU, ST

13 F2 VDDIO GPIO_AD PA20 I/O AFE0_AD9/WKUP10(6) I – – PWMC0_PWML1 O A16/BA0 O I2SC1_CK – PIO, I, PU, ST

21 J1 VDDIO GPIO_AD PA21 I/O AFE0_AD1/

PIODCEN2(8) I RXD1 I PCK1 O PWMC1_PWMFI0 I – – PIO, I, PU, ST

26 J3 VDDIO GPIO_AD PA22 I/O PIODCCLK(2) I RK I/O PWMC0_PWMEXTRG1 I NCS2 O – – PIO, I, PU, ST

31 K5 VDDIO GPIO_AD PA23 I/O – – SCK1 I/O PWMC0_PWMH0 O A19 O PWMC1_PWML2 O PIO, I, PU, ST

38 K7 VDDIO GPIO_AD PA24 I/O – – RTS1 O PWMC0_PWMH1 O A20 O ISI_PCK I PIO, I, PU, ST

40 H7 VDDIO GPIO_AD PA25 I/O – – CTS1 I PWMC0_PWMH2 O A23 O MCCK O PIO, I, PU, ST

42 K8 VDDIO GPIO PA26 I/O – – DCD1 I TIOA2 O MCDA2 I/O PWMC1_PWMFI1 I PIO, I, PU, ST

50 H8 VDDIO GPIO_AD PA27 I/O – – DTR1 O TIOB2 I/O MCDA3 I/O ISI_D7 I PIO, I, PU, ST

79 A9 VDDIO GPIO PA28 I/O – – DSR1 I TCLK1 I MCCDA I/O PWMC1_PWMFI2 I PIO, I, PU, ST

82 C7 VDDIO GPIO PA30 I/O WKUP11(1) I PWMC0_PWML2 O PWMC1_PWMEXTRG0 I MCDA0 I/O I2SC0_DO – PIO, I, PU, ST

83 A7 VDDIO GPIO_AD PA31 I/O – – SPI0_NPCS1 I/O PCK2 O MCDA1 I/O PWMC1_PWMH2 O PIO, I, PU, ST

23SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

12 E1 VDDIO GPIO PB0 I/O AFE0_AD10/

RTCOUT0(7) I PWMC0_PWMH0 O – – RXD0 I TF I/O PIO, I, PU, ST

11 E2 VDDIO GPIO PB1 I/O AFE1_AD0/

RTCOUT1(7) I PWMC0_PWMH1 O – O TXD0 I/O TK I/O PIO, I, PU, ST

17 H1 VDDIO GPIO PB2 I/O AFE0_AD5(5) I CANTX0 O – – CTS0 I SPI0_NPCS0 I/O PIO, I, PU, ST

20 H2 VDDIO GPIO_AD PB3 I/O AFE0_AD2/WKUP12(6) I CANRX0 I PCK2 O RTS0 O ISI_D2 I PIO, I, PU, ST

74 B9 VDDIO GPIO_MLB PB4 I/O TDI(9) I TWD1 I/O PWMC0_PWMH2 O – – TXD1 I/O PIO, I, PD, ST

77 C8 VDDIO GPIO_MLB PB5 I/O TDO/TRACESWO/

WKUP13(9) O TWCK1 O PWMC0_PWML0 O – – TD O O, PU

57 G8 VDDIO GPIO PB6 I/O SWDIO/TMS(9) I – – – – – – – – PIO,I,ST

63 E9 VDDIO GPIO PB7 I/O SWCLK/TCK(9) I – – – – – – – – PIO,I,ST

98 A2 VDDIO CLOCK PB8 I/O XOUT(10) O – – – – – – – – PIO, HiZ

99 A1 VDDIO CLOCK PB9 I/O XIN(10) I – – – – – – – – PIO, HiZ

61 F8 VDDIO GPIO PB12 I/O ERASE(9) I PWMC0_PWML1 O GTSUCOMP O – – PCK0 O PIO, I, PD, ST

100 B2 VDDIO GPIO_AD PB13 I/O DAC0(11) O PWMC0_PWML2 O PCK0 O SCK0 I/O – – PIO, I, PU, ST

1 C1 VDDIO GPIO_AD PD0 I/O DAC1(11) I GTXCK I PWMC1_PWML0 O SPI1_NPCS1 I/O DCD0 I PIO, I, PU, ST

92 D2 VDDIO GPIO PD1 I/O – – GTXEN O PWMC1_PWMH0 O SPI1_NPCS2 I/O DTR0 O PIO, I, PU, ST

91 E3 VDDIO GPIO PD2 I/O – – GTX0 O PWMC1_PWML1 O SPI1_NPCS3 I/O DSR0 I PIO, I, PU, ST

89 B5 VDDIO GPIO PD3 I/O – – GTX1 O PWMC1_PWMH1 O UTXD4 O RI0 I PIO, I, PU, ST

88 A5 VDDIO GPIO_CLK PD4 I/O – – GRXDV I PWMC1_PWML2 O TRACED0 O DCD2 I PIO, I, PU, ST

87 D5 VDDIO GPIO_CLK PD5 I/O – – GRX0 I PWMC1_PWMH2 O TRACED1 O DTR2 O PIO, I, PU, ST

85 B6 VDDIO GPIO_CLK PD6 I/O – – GRX1 I PWMC1_PWML3 O TRACED2 O DSR2 I PIO, I, PU, ST

84 A6 VDDIO GPIO_CLK PD7 I/O – – GRXER I PWMC1_PWMH3 O TRACED3 O RI2 I PIO, I, PU, ST

80 B7 VDDIO GPIO_CLK PD8 I/O – – GMDC O PWMC0_PWMFI1 I – – TRACECLK O PIO, I, PU, ST

78 B8 VDDIO GPIO_CLK PD9 I/O – – GMDIO I/O PWMC0_PWMFI2 I AFE1_ADTRG I – – PIO, I, PU, ST

71 C9 VDDIO GPIO_MLB PD10 I/O – – GCRS I PWMC0_PWML0 O TD O – – PIO, I, PD, ST

69 D9 VDDIO GPIO_AD PD11 I/O – – GRX2 I PWMC0_PWMH0 O GTSUCOMP O ISI_D5 I PIO, I, PU, ST

65 E10 VDDIO GPIO_AD PD12 I/O – – GRX3 I CANTX1 O SPI0_NPCS2 O ISI_D6 I PIO, I, PU, ST

62 E8 VDDIO GPIO_AD PD13 I/O – – GCOL I – – SDA10 O – – PIO, I, PU, ST

59 F10 VDDIO GPIO_AD PD14 I/O – – GRXCK I – – SDCKE O – – PIO, I, PU, ST

75 B10 VDDIO GPIO_AD PD15 I/O – – GTX2 O RXD2 I NWR1/NBS1 O – – PIO, I, PU, ST

56 G9 VDDIO GPIO_AD PD16 I/O – – GTX3 O TXD2 I/O RAS O – – PIO, I, PU, ST

53 J10 VDDIO GPIO_AD PD17 I/O – – GTXER O SCK2 I/O CAS O – – PIO, I, PU, ST

49 K6 VDDIO GPIO_AD PD18 I/O – – NCS1/SDCS O RTS2 O URXD4 I – – PIO, I, PU, ST

47 K4 VDDIO GPIO_AD PD19 I/O – – NCS3 O CTS2 I UTXD4 O – – PIO, I, PU, ST

Table 5-2. 100-lead Package Pinout LQFP Pin TFBGA Ball Power Rail I/O Type Primary Alternate PIO Peripheral A PIO Peripheral B PIO Peripheral C PIO Peripheral D Reset State Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir Signal, Dir, PU, PD, HiZ, ST

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

45 K3 VDDIO GPIO PD20 I/O – – PWMC0_PWMH0 O SPI0_MISO I/O GTSUCOMP O – – PIO, I, PU, ST

43 H5 VDDIO GPIO_AD PD21 I/O – – PWMC0_PWMH1 O SPI0_MOSI I/O TIOA11 I/O ISI_D1 I PIO, I, PU, ST

41 J4 VDDIO GPIO_AD PD22 I/O – – PWMC0_PWMH2 O SPI0_SPCK O TIOB11 I/O ISI_D0 I PIO, I, PU, ST

37 G4 VDDIO GPIO_AD PD24 I/O – – PWMC0_PWML0 O RF I/O TCLK11 I ISI_HSYNC I PIO, I, PU, ST

35 H3 VDDIO GPIO_AD PD25 I/O – – PWMC0_PWML1 O SPI0_NPCS1 I/O URXD2 I ISI_VSYNC I PIO, I, PU, ST

36 G3 VDDIO GPIO PD26 I/O – – PWMC0_PWML2 O TD O UTXD2 O UTXD1 O PIO, I, PU, ST

32 H4 VDDIO GPIO_AD PD27 I/O – – PWMC0_PWML3 O SPI0_NPCS3 O TWD2 O ISI_D8 I PIO, I, PU, ST

51 J7 VDDIO GPIO_AD PD28 I/O WKUP5(1) I URXD3 I CANRX1 I TWCK2 O ISI_D9 I PIO, I, PU, ST

23 K1 VDDIO GPIO_AD PD30 I/O AFE0_AD0(5) I UTXD3 0 – – – – ISI_D10 I PIO, I, PU, ST

2 B1 VDDIO GPIO_AD PD31 I/O – – QIO3 I/O UTXD3 O PCK2 O ISI_D11 I PIO, I, PU, ST

58 G10 VDDIO RST NRST I/O – – – – – – – – – – I, PU

19, 28, 68, C5, F3,

73 A10 VDDIO TEST JTAGSEL I – – – – – – – – – – I, PD

18, 22, 39, C6, D6, 3, 7, 8, 10, 29, 67 E7, F4, Table 5-2. 100-lead Package Pinout LQFP Pin TFBGA Ball Power Rail I/O Type Primary Alternate PIO Peripheral A PIO Peripheral B PIO Peripheral C PIO Peripheral D Reset State Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir Signal, Dir, PU, PD, HiZ, ST

25SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 Notes: 1. WKUPx can be used if the PIO Controller defines the I/O line as "input". 2. To select this extra function, refer to Section 32.5.14 “Parallel Capture Mode”. 4. Refer to Section 22.4.2 “Slow Clock Generator”. 5. To select this extra function, refer to Section 50.5.1 “I/O Lines” used if the PIO controller defines the I/O line as "input". 26.5.8 “Waveform Generation” to select RTCOUTx. PIODCEN2, refer to Section 32.5.14 “Parallel Capture Mode”. 9. Refer to the System I/O Configuration Register in Section 18. “Bus Matrix (MATRIX)”. 10. Refer to Section 30.5.3 “3 to 20 MHz Crystal or Ceramic Resonator-based Oscillator”. “DACC Channel Enable Register”.

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 5.5 64-lead Package 5.5.1 64-pin LQFP Package Outline Figure 5-6. Orientation of the 64-pin LQFP Package 161

27SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 5.6 64-lead Package Pinout Table 5-3. 64-lead LQ FP Package Pinout LQFP Pin Power Rail I/O Type Primary Alternate PIO Peripheral A PIO Peripheral B PIO Peripheral C PIO Peripheral D Reset State Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir Signal, Dir, PU, PD, HiZ, ST

40 VDDIO GPIO_AD PA3 I/O PIODC0(1) I (2)TWD0 I/O LONCOL1 I PCK2 O – – PIO, I, PU, ST

34 VDDIO GPIO PA4 I/O WKUP3/PIODC1(2) I TWCK0 O TCLK0 I UTXD1 O – – PIO, I, PU, ST

32 VDDIO GPIO_AD PA5 I/O WKUP4/PIODC2(2) I PWMC1_PWML3 O ISI_D4 I URXD1 I – – PIO, I, PU, ST

15 VDDIO CLOCK PA7 I/O XIN32(3) I – – PWMC0_PWMH3 – – – – – PIO, HiZ

16 VDDIO CLOCK PA8 I/O XOUT32(3) O PWMC1_PWMH3 O AFE0_ADTRG I – – – – PIO, HiZ

33 VDDIO GPIO_AD PA9 I/O WKUP6/PIODC3(2) I URXD0 I ISI_D3 I PWMC0_PWMFI0 I – – PIO, I, PU, ST

28 VDDIO GPIO_AD PA10 I/O PIODC4(1) I UTXD0 O PWMC0_PWMEXTRG0 I RD I – – PIO, I, PU, ST

27 VDDIO GPIO_AD PA11 I/O WKUP7/PIODC5(2) I QCS O PWMC0_PWMH0 O PWMC1_PWML0 O – – PIO, I, PU, ST

29 VDDIO GPIO_AD PA12 I/O PIODC6(1) I QIO1 I/O PWMC0_PWMH1 O PWMC1_PWMH0 O – – PIO, I, PU, ST

18 VDDIO GPIO_AD PA13 I/O PIODC7(1) I QIO0 I/O PWMC0_PWMH2 O PWMC1_PWML1 O – – PIO, I, PU, ST

19 VDDIO GPIO_CLK PA14 I/O WKUP8/PIODCEN1(2) I QSCK O PWMC0_PWMH3 O PWMC1_PWMH1 O – – PIO, I, PU, ST

12 VDDIO GPIO_AD PA21 I/O AFE0_AD1/

PIODCEN2(7) I RXD1 I PCK1 O PWMC1_PWMFI0 I – – PIO, I, PU, ST

17 VDDIO GPIO_AD PA22 I/O PIODCCLK(1) I RK I/O PWMC0_PWMEXTRG1 I NCS2 O – – PIO, I, PU, ST

23 VDDIO GPIO_AD PA24 I/O – – RTS1 O PWMC0_PWMH1 O A20 O ISI_PCK I PIO, I, PU, ST

30 VDDIO GPIO_AD PA27 I/O – – DTR1 O TIOB2 I/O MCDA3 I/O ISI_D7 I PIO, I, PU, ST

8 VDDIO GPIO PB0 I/O AFE0_AD10/

RTCOUT0(6) I PWMC0_PWMH0 O – – RXD0 I TF I/O PIO, I, PU, ST

7 VDDIO GPIO PB1 I/O AFE1_AD0/

RTCOUT1(6) I PWMC0_PWMH1 O GTSUCOMP O TXD0 I/O TK I/O PIO, I, PU, ST

9 VDDIO GPIO PB2 I/O AFE0_AD5(4) I CANTX0 O – – CTS0 I SPI0_NPCS0 I/O PIO, I, PU, ST

11 VDDIO GPIO_AD PB3 I/O AFE0_AD2/WKUP12(6) I CANRX0 I PCK2 O RTS0 O ISI_D2 I PIO, I, PU, ST

46 VDDIO GPIO_MLB PB4 I/O TDI(8) I TWD1 I/O PWMC0_PWMH2 O – – TXD1 I/O PIO, I, PD, ST

47 VDDIO GPIO_MLB PB5 I/O TDO/TRACESWO/

WKUP13(8) O TWCK1 O PWMC0_PWML0 O – – TD O O, PU

35 VDDIO GPIO PB6 I/O SWDIO/TMS(8) I – – – – – – – – PIO,I,ST

39 VDDIO GPIO PB7 I/O SWCLK/TCK(8) I – – – – – – – – PIO,I,ST

62 VDDIO CLOCK PB8 I/O XOUT(9) O – – – – – – – – PIO, HiZ

63 VDDIO CLOCK PB9 I/O XIN(9) I – – – – – – – – PIO, HiZ

38 VDDIO GPIO PB12 I/O ERASE(8) I PWMC0_PWML1 O GTSUCOMP O – – PCK0 O PIO, I, PD, ST

1 VDDIO GPIO_AD PD0 I/O DAC1(10) I GTXCK I PWMC1_PWML0 O SPI1_NPCS1 I/O DCD0 I PIO, I, PU, ST

57 VDDIO GPIO PD1 I/O – – GTXEN O PWMC1_PWMH0 O SPI1_NPCS2 I/O DTR0 O PIO, I, PU, ST

56 VDDIO GPIO PD2 I/O – – GTX0 O PWMC1_PWML1 O SPI1_NPCS3 I/O DSR0 I PIO, I, PU, ST

55 VDDIO GPIO PD3 I/O – – GTX1 O PWMC1_PWMH1 O UTXD4 O RI0 I PIO, I, PU, ST

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

54 VDDIO GPIO_CLK PD4 I/O – – GRXDV I PWMC1_PWML2 O TRACED0 O DCD2 I PIO, I, PU, ST

53 VDDIO GPIO_CLK PD5 I/O – – GRX0 I PWMC1_PWMH2 O TRACED1 O DTR2 O PIO, I, PU, ST

51 VDDIO GPIO_CLK PD6 I/O – – GRX1 I PWMC1_PWML3 O TRACED2 O DSR2 I PIO, I, PU, ST

50 VDDIO GPIO_CLK PD7 I/O – – GRXER I PWMC1_PWMH3 O TRACED3 O RI2 I PIO, I, PU, ST

49 VDDIO GPIO_CLK PD8 I/O – – GMDC O PWMC0_PWMFI1 I – – TRACECLK O PIO, I, PU, ST

48 VDDIO GPIO_CLK PD9 I/O – – GMDIO I/O PWMC0_PWMFI2 I AFE1_ADTRG I – – PIO, I, PU, ST

44 VDDIO GPIO_MLB PD10 I/O – – GCRS I PWMC0_PWML0 O TD O – – PIO, I, PD, ST

43 VDDIO GPIO_AD PD11 I/O – – GRX2 I PWMC0_PWMH0 O GTSUCOMP O ISI_D5 I PIO, I, PU, ST

41 VDDIO GPIO_AD PD12 I/O – – GRX3 I CANTX1 O SPI0_NPCS2 O ISI_D6 I PIO, I, PU, ST

26 VDDIO GPIO_AD PD21 I/O – – PWMC0_PWMH1 O SPI0_MOSI I/O TIOA11 I/O ISI_D1 I PIO, I, PU, ST

25 VDDIO GPIO_AD PD22 I/O – – PWMC0_PWMH2 O SPI0_SPCK O TIOB11 I/O ISI_D0 I PIO, I, PU, ST

22 VDDIO GPIO_AD PD24 I/O – – PWMC0_PWML0 O RF I/O TCLK11 I ISI_HSYNC I PIO, I, PU, ST

20 VDDIO GPIO_AD PD25 I/O – – PWMC0_PWML1 O SPI0_NPCS1 I/O URXD2 I ISI_VSYNC I PIO, I, PU, ST

21 VDDIO GPIO PD26 I/O – – PWMC0_PWML2 O TD O UTXD2 O UTXD1 O PIO, I, PU, ST

2 VDDIO GPIO_AD PD31 I/O – – QIO3 I/O UTXD3 O PCK2 O ISI_D11 I PIO, I, PU, ST

36 VDDIO RST NRST I/O – – – – – – – – – – PIO, I, PU

Table 5-3. 64-lead LQFP P ackage Pinout (Continued) LQFP Pin Power Rail I/O Type Primary Alternate PIO Peripheral A PIO Peripheral B PIO Peripheral C PIO Peripheral D Reset State Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir Signal, Dir, PU, PD, HiZ, ST

29SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 Notes: 1. To select this extra function, refer to Section 32.5.14 “Parallel Capture Mode”. 3. Refer to Section 22.4.2 “Slow Clock Generator”. 4. To select this extra function, refer to Section 50.5.1 “I/O Lines”. used if the PIO controller defines the I/O line as "input". 26.5.8 “Waveform Generation” to select RTCOUTx. PIODCEN2, refer to Section 32.5.14 “Parallel Capture Mode”. 8. Refer to the System I/O Configuration Register in Section 18. “Bus Matrix (MATRIX)”. 9. Refer to Section 30.5.3 “3 to 20 MHz Crystal or Ceramic Resonator-based Oscillator”. “DACC Channel Enable Register”.

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 6. Power Considerations

6.1 Power Supplies

Table 6-1 defines the power supply rails of the SAM E70 and the estimated power consumption at typical voltage.

6.2 Power Constraints

The following power constraints apply to SAM E70 devices. Deviating from these constraints may lead to unpredictable results. ̶ VDDIN and VDDIO must have the same level ̶ VDDIN and VDDIO must always be higher than or equal to VDDCORE ̶ VDDCORE, VDDPLL and VDDUTMIC voltage levels must not vary by more than 0.6V. ̶ For the USB to be operational, VDDUTMII, VDDPLLUSB, VDDIN and VDDIO must be higher than or equal to 3.0V. Table 6-1. Power Supplies Name Associated Ground Powers VDDCORE GND Core, embedded memories and peripherals VDDIO GND Peripheral I/O lines (Input/Output Buffers), backup part, 1 Kbytes of backup SRAM, 32 kHz crystal oscillator, oscillator pads. For USB operations, VDDIO voltage range must be between 3.0V and 3.6V. VDDIN GND, GNDANA Voltage regulator input. Supplies also the ADC, DAC and analog voltage comparator. VDDPLL GND, GNDPLL PLLA and the fast RC oscillator VDDPLLUSB GND, GNDPLLUSB UTMI PLL and the 3 to 20 MHz oscillator. For USB operations, VDDPLLUSB must be between 3.0V and 3.6V. VDDUTMII GNDUTMI USB transceiver interface. Must be connected to VDDIO. For USB operations, VDDUTMII voltage range must be between 3.0V and 3.6V. VDDUTMIC GNDUTMI USB transceiver core

31SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

6.2.1 Power-up

VDDIO and VDDIN must rise simultaneously, prio r to VDDCORE, VDDPLL and VD DUTMIC rising. This is respected if VDDCORE, VDDPLL and VDDUTMIC are supplied by the embedded voltage regulator. If VDDCORE is powered by an external voltage regulator, VDDIO and VDDIN must reach their minimum operating voltage before VDDCORE has reached VDDCOREmin. The minimum slope for VDDCORE is defined by: If VDDCORE rises at the same time as VDDIO and VDDIN, the rising slope of VDDIO and VDDIN must be higher than or equal to 2.4V/ms. Refer to Table 56-9 “VDDIO Power-On Reset Characteristics“. In order to prevent any overcurrent at power-up, it is required that ADVREFP rises simultaneously with VDDIO and VDDIN. Figure 6-1. Power-up Sequence VDDCOREmin VT+–() tRES()⁄ Supply (V) Time (t) VDDIO VDDIN VDDPLLUSB VDDUTMII VDDCORE VDDPLL VDDUTMIC VDDx(min) VT+ VDDy(min) tRST

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

6.2.2 Power-down

If VDDCORE, VDDPLL and VDDUTMI C are not supplied by the embedded voltage regulator, VDDIO, VDDIN, VDDPLLUSB and VDDUTMII should fall simultaneously, prior to VDDCORE, VDDPLL and VDDUTMIC falling. The VDDCORE falling slope must not be faster than 20V/ms. In order to prevent any overcurrent at power-down, it is required that ADVREFP falls simultaneously with VDDIO and VDDIN. Figure 6-2. Power-down Sequence

6.3 Voltage Regulator

The SAM E70 embeds a voltage regulator that is managed by the Supply Controller. For adequate input and output power suppl y decoupling/bypassing, refer to Table 56-4 “1.2V Voltage Regulator Characteristics“.

6.4 Backup SRAM Power Switch

The SAM E70 embeds a power switch to supply the 1 Kbyte of backup SRAM. It is activated only when VDDCORE is switched off to ensure retention of the contents of the backup SRAM. When VDDCORE is switched on, the backup SRAM is powered with VDDCORE. To save the power consumption of the backup SRAM, t he user can disable the backup SRAM power switch by clearing the bit SRAMON in the Supply Controller Mode Register (SUPC_MR). By defau lt, after VDDIO rises, the backup SRAM power switch is enabled.

6.5 Active Mode

Active mode is the normal running mode with the core clock running from the fast RC oscillator, the main crystal oscillator or the PLLA. The Power Management Controller can be used to adapt the core, bus and peripheral frequencies and to enable and/or disable the peripheral clocks. Supply (V) Time (t) VDDIO VDDIN VDDPLLUSB VDDUTMII VDDCORE VDDPLL VDDUTMIC VDDx(min) VDDy(min)

33SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

6.6 Low-power Modes

The SAM E70 features low-power modes:  Backup mode  Wait mode  Sleep mode

6.6.1 Backup Mode

The purpose of Backup mode is to achieve the lowest power consumption possible in a system which is performing periodic wake-ups to perform tasks but not requiring fast startup time. The Supply Controller, zero-power power-on reset, RTT, RTC, backup SRAM, ba ckup registers and 32 kHz oscillator (RC or crystal oscillator selected by software in the Supply Controller) are running. The regulator and the core supply are off. Backup mode is based on the Cortex-M7 Deep Sleep mode with the voltage regulator disabled. Wake-up from Backup mode is done through WKUP0–13 pi ns, the supply monitor (SM), the RTT, or an RTC wake-up event. Backup mode is entered by using bit VROFF in the Su pply Controller Control R egister (SUPC_CR) and the SLEEPDEEP bit in the Cortex-M7 System Control Register set to 1. Refer to information on Power Management in the ARM Cortex-M7 documentation available at www.arm.com. To enter Backup mode, follow the steps below: 1. Set the SLEEPDEEP bit of the Cortex-M7 processor. 2. Set the VROFF bit of SUPC_CR. Exit from Backup mode occurs as a result of one of the following enabled wake-up events:  WKUP0–13 pins (level transition, configurable debouncing)  Supply Monitor alarm  RTC alarm  RTT alarm

6.6.2 Wait Mode

The purpose of Wait mode is to achieve very low power consumption while maintaining the whole device in a powered state for a startup time of less than 10 µs. In Wait mode, the clocks of the core, peripherals and memories are stopped. However, the core, peripherals and memories power supplies are still powered. Wait mode is entered when the bit WAITMODE is set in CKGR_MOR and the field FLPM is configured to 00 or 01 in the PMC Fast Startup Mode register (PMC_FSMR). The Cortex-M is able to handle external events or internal events in order to wake up the core. This is done by configuring the external lines WKUP0–13 as fast startup wake-up pins (refer to Section 6.8 “Fast Startup”). RTC or RTT alarms or USB wake-up events can be used to wake up the processor. Resume from Wait mode is also achieved when a debug request occurs and the bit CDBGPWRUPREQ is set in the processor. To enter Wait mode, follow the steps below: 1. Select the 4/8/12 MHz fast RC oscillator as Main Clock. 2. Configure the FLPM field in the PMC_FSMR. 3. Set Flash Wait State at 0. 4. Set HCLK = MCK by configuring MDIV to 0 in the PMC Master Clock register (PMC_MCKR). 5. Set the WAITMODE bit in the PMC Clock Gene rator Main Oscillator register (CKGR_MOR). 6. Wait for MCKRDY = 1 in the PMC Status register (PMC_SR).

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 Note: Internal main clock resynchronization cycles are necessary between writing the MOSCRCEN bit and the entry in Wait mode. Depending on the user application, waiting for MOSCRCEN bit to be cleared is recommended to ensure that the core will not execute undesired instructions.

6.6.3 Sleep Mode

The purpose of sleep mode is to optimize power consumption of the device versus response time. In this mode, only the core clock is stopped. The peripheral clocks can be enabled. The current consumption in this mode is application-dependent. This mode is entered using the instruction Wait for Interrupt (WFI). Processor wake-up is triggered by an interrupt if the WFI instruction of the Cortex-M processor is used.

35SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

6.6.4 Low-Power Mode Summary Table

The modes detailed above are the main low-power modes. Each part can be set to on or off separately and wake up sources can be individually configured. Table 6-2 below shows a summary of the configurations of the low-power modes. Table 6-2. Low-power Mode Configuration Summary Mode SUPC, 32 kHz Oscillator, RTC, RTT Backup SRAM (BRAM), Backup Registers (GPBR), POR (Backup Area) Regulator Core Memory Peripherals Mode Entry Configuration Potential Wake-Up Sources Core at Wake-Up PIO State while in Low Power Mode PIO State at Wake-Up Wake-up Time(2) Backup Mode ON OFF OFF (Not powered) SUPC_CR.VROFF = 1 SLEEPDEEP(1) = 1 WKUP0–13 pins Supply Monitor RTC alarm RTT alarm Reset Previous state maintained PIOA, PIOB, PIOC, PIOD & PIOE inputs with pull-ups < 2 ms Wait Mode w/Flash in Deep Power- down Mode ON ON Powered (Not clocked) PMC_MCKR.MDIV = 0 CKGR_MOR.WAITMODE =1 SLEEPDEEP (1) = 0 PMC_FSMR.LPM = 1 PMC_FSMR.FLPM = 1 WKUP0–13 pins RTC RTT USBHS Processor debug(6) GMAC Wake on LAN event Wake-up from CAN (7) Clocked back(3) Previous state maintained Unchanged < 10 µs Wait Mode w/Flash in Standby Mode ON ON Powered (Not clocked) PMC_MCKR.MDIV = 0 CKGR_MOR.WAITMODE =1 SLEEPDEEP (1) = 0 PMC_FSMR.LPM = 1 PMC_FSMR.FLPM = 0 WKUP0–13 pins RTC RTT USBHS Processor debug(6) GMAC Wake on LAN Wake-up from CAN (7) Clocked back(3) Previous state maintained Unchanged < 10 µs Sleep Mode ON ON Powered(4) (Not clocked) WFI SLEEPDEEP(1) = 0 PMC_FSMR.LPM = 0 Any enabled Interrupt Clocked back Previous state maintained Unchanged (5)

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 Notes: 1. The bit SLEEPDEEP is in the Co rtex-M7 System Control Register. 2. When considering wake-up time, the time required to start the PLL is not taken into account. Once started, the device works with the 4/8/12 MHz fast RC oscillator. The user has to add the PLL start-up time if it is needed in the system. The wake-up time is defined as the time taken for wake up until the first instruction is fetched. 3. HCLK = MCK. The user may need to revert back to the previous clock configuration. 4. Depends on MCK frequency. 5. In this mode, the core is supplied and not clocked. Some peripherals can be clocked. 6. Resume from Wait mode if a debug request occurs (CDBGPWRUPREQ is set in the processor). 7. CAN wakeup requires the use of any WKUP0–13 pin.

6.7 Wake-up Sources

Wake-up events allow the device to exit Backup mode. When a wake-up event is dete cted, the Supply Controller performs a sequence which automatically reenables the core power supply and the SRAM power supply, if they are not already enabled.

6.8 Fast Startup

The SAM E70 allows the processor to restart in a few mi croseconds while the processor is in Wait mode or in Sleep mode. A fast startup can occur upon detection of a low level on any of the following wake-up sources:  WKUP0 to WKUP13 pins  Supply Monitor  RTC alarm  RTT alarm  USBHS interrupt line (WAKEUP)  Processor debug request (CDBGPWRUPREQ)  GMAC wake on LAN event Note: CAN wakeup requires the use of any WKUP0–13 pin. The fast restart circuitry is fully asynchronous and provides a fast start-up signal to the Power Management Controller. As soon as the fast start-up signal is asserted, the PMC automatica lly restarts the embedded 4/8/12 MHz Fast RC oscillator, switches the master clock on this 4 MHz clock and re-enables the processor clock.

37SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 7. Input/Output Lines The SAM E70 features both general purpose I/Os (GPIO) and system I/Os. GPIOs can have alternate functionality due to multiplexing capabilities of th e PIO controllers. The same PIO line can be used, whether in I/O mode or by the multiplexed peripherals. System I/Os include pins such as test pins, oscillators, erase or analog inputs.

7.1 General-Purpose I/O Lines

General-purpose (GPIO) lines are managed by PIO Contro llers. All I/Os have several input or output modes such as pull-up or pull-down, input Schmitt triggers, multi-drive (open-drain), glitch filters, debouncing or input change interrupt. Programming of these modes is performed independently for each I/O line through the PIO controller user interface. For more details, refer to Section 32. “Parallel Input/Output Controller (PIO)”. The input/output buffers of the PIO lines are supplied through VDDIO power supply rail. The SAM E70 embeds high-speed pads able to handle the high-speed clocks for HSMCI, SPI and QSPI (MCK/2). Refer to the Section 56. “Electrical Characteristics” for more details. Typical pull-up and pull-down value is 100 kΩ for all I/Os. Each I/O line also embeds an R SERIAL (On-die Serial Resistor), (see Figure 7-1 below). It consists of an internal series resistor termination scheme for impedance matchi ng between the driver output (SAM E70) and the PCB trace impedance preventing signal reflection. The series resistor helps to reduce IO s switching current (di/dt) thereby reducing in turn, EMI. It also decreases overshoot and undershoot (rin ging) due to inductance of interconnect between devices or between boards. Finally, RSERIAL helps diminish signal integrity issues. Figure 7-1. On-Die Termination PCB Trace Z0 ~ 50 Ohms Receiver Driver with RSERIAL ZOUT ~ 10 Ohms Z0 ~ ZOUT + RODT On-die Serial Resistor

36 Ohms typ

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

7.2 System I/O Lines

System I/O lines are pins used by oscillators, test mode, re set, JTAG and other features. Table 7-1 lists the SAM E70 system I/O lines shared with PIO lines. These pins are software-configurable as general-purpose I/Os or system pins. At star tup, the default function of these pins is always used. Notes: 1. If PB12 is used as PIO input in us er applications, a low level must be ensured at startup to prevent Flash erase before the user application sets PB12 into PIO mode, 2. Refer to Section 22.4.2 “Slow Clock Generator”. 3. Refer to Section 30.5.3 “3 to 20 MHz Crystal or Ceramic Resonator-based Oscillator”.

7.2.1 Serial Wire Debug Port (SW-DP) Pins

The SW-DP pins SWCLK and SWDIO are commonly provided on a standard 20-pin JTAG connector defined by ARM. For more details about voltage reference and reset state, refer to Table 4-1 “Signal Description List“. At startup, SW-DP pins are configured in SW-DP m ode to allow connection with debugging probe. For more details, refer to Section 15. “Debug and Test Features”. SW-DP pins can be used as standard I/Os to provide users more general input/output pins when the debug port is not needed in the end application. Mode selection between SW-DP mode (System IO mode) and general IO mode is performed through the AHB Matrix Special Function Registers (MATRIX_SFR). Configuration of the pad for pull- up, triggers, debouncing and glitch filters is possible regardless of the mode. The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level. It integrates a permanent pull-down resistor of about 15 kΩ to GND, so that it can be left unconnected for normal operations. The JTAG Debug Port TDI, TDO, TMS and TCK is inacti ve. It is provided for Boundary Scan Manufacturing Test purpose only.

7.2.2 Embedded Trace Module (ETM) Pins

The Embedded Trace Module (ETM) depends on the Trace Port Interface Unit (TPIU) to export data out of the system. The TPUI features the following pins: ̶ TRACECLK is always exported to enable synchronization with the data. ̶ TRACED0–TRACED3 is the instruction trace stream. Table 7-1. System I/O Configuration Pin List. CCFG_SYSIO Bit Number Default Function After Reset Other Function Constraints for Normal Start Configuration

12 ERASE PB12 Low Level at

startup(1) In Matrix User Interface Registers (Refer to the System I/O Configuration Register in Section 18. “Bus Matrix (MATRIX)”)

7 TCK/SWCLK PB7 –

6 TMS/SWDIO PB6 –

5 TDO/TRACESWO PB5 –

4 TDI PB4 –

– PA7 XIN32 – (2) – PA8 XOUT32 – – PB9 XIN – (3) – PB8 XOUT –

39SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

7.3 NRST Pin

The NRST pin is bidirectional. It is handled by the on-chip Reset Controller (RSTC) and can be driven low to provide a reset signal to the external components or asserted low externally to reset the microcontroller. It resets the core and the peripherals, with the exception of the Backup area (RTC, RTT, Backup SRAM and Supply Controller). The NRST pin integrates a permanent pull-up resistor to VDDIO of about 100 kΩ. By default, the pin is configured as an input.

7.4 ERASE Pin

The ERASE pin is used to reinitialize the Flash content and some of its NVM bi ts to an erased state (all bits read as logic level 1). The ERASE pin and the ROM code ensu re an in-situ reprogrammability of the Flash content without the use of a debug tool. When the security bit is activated, the ERASE pin provides the capability to reprogram the Flash cont ent. The ERASE pin integr ates a pull-down resistor of about 100 k Ω to GND, so that it can be left unconnected for normal operations. This pin is debounced by SLCK to improve the glitch tolerance. To avoid unexpected erase at power-up, a minimum ERASE pin assertion time is required. This time is defined in Table 56-52 “Flash Characteristics“. The ERASE pin is a system I/O pin that can be used as a standard I/O. At startup, this system I/O pin defaults to the ERASE function. To avoid unexpected erase at power -up due to glitches, a minimum ERASE pin assertion time is required. This time is defined in Table 56-52 “Flash Characteristics“. The erase operation cannot be performed when the system is in Wait mode. If the ERASE pin is used as a standa rd I/O in Input or Outp ut mode, note the following considerations and behavior:  I/O Input mode: at startup of the device, the logic level of the pin must be low to prevent unwanted erasing until the user application has reconfigured this system I/O pin to a standard I/O pin.  I/O Output mode: asserting the pin to low does not erase the Flash During software application development, a faulty software may put the device into a deadlock. This may be due to:  programming an incorrect clock switching sequence  using this system I/O pin as a standard I/O pin  entering Wait mode without any wake-up events programmed The only way to recover normal behavior is to erase the Flash by following the steps below: 1. Apply a logic "1" level on the ERASE pin. 2. Apply a logic "0" level on the NRST pin. 3. Power-down then power-up the device. 4. Maintain the ERASE pin to logic "0" level for at least the minimum assertion time after releasing the NRST pin to logic "1" level.

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 8. Interconnect The system architecture is based on the ARM Cortex-M7 processor connecte d to the main AHB Bus Matrix, the embedded Flash, the multi-port SRAM and the ROM. The 32-bit AHBP interface is a single 32-bit wide interface that accesses the peripherals connected on the main Bus Matrix. It is used only for data access. Instruction fetches are never performed on the AHBP interface. The bus, AHBP or AXIM, accessing the peripheral memory area [0x40000000 to 0x60000000] is selected in the AHBP control register. The 32-bit AHBS interface provides system access to the ITCM, D1TCM, and D0TCM. It is connected on the main Bus Matrix and allows the XDMA to transfer from memory or peripherals to the instruction or data TCMs. The 64-bit AXIM interface is a single 64-bit wide interf ace connected through two ports of the AXI Bridge to the main AHB Bus Matrix and to two ports of the multi-port SRAM. The AXIM interface allows: ̶ Instruction fetches ̶ Data cache linefills and evictions ̶ Non-cacheable normal-type memory data accesses ̶ Device and strongly-ordered type data accesses, generally to peripherals The interleaved multi-port SRAM optimizes the Cortex-M7 accesses to the internal SRAM. The interconnect of the other masters and slaves is described in Section 18. “Bus Matrix (MATRIX)”. Figure 8-1 shows the connections of the different Cortex-M7 ports. Figure 8-1. Interconnect Block Diagram 12-layer AHB Bus Matrix fMAX 150 MHz In-Circuit Emulator MPU Cortex-M7 Processor fMAX 300 MHz NVIC FPU TPIU ETM

16 Kbytes

M MMS AXIMAHBP S AHBS AXI Bridge ROM Multi-Port SRAM Flash ITCM DTCM TCM SRAM System SRAM 64-bit 32-bit 32-bit 2 x 32-bit 64-bit 32-bit32-bit 32-bit 32-bit

41SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 9. Product Mapping Figure 9-1. SAM E70 Product Mapping Address memory space Code 0x00000000 Internal SRAM 0x20000000 Peripherals 0x40000000 Memories 0x60000000 QSPI MEM 0x80000000 0xA0000000 USBHS RAM 0xA0100000 Reserved 0xA0200000 System 0xE0000000 0xFFFFFFFF Code ITCM or Boot Memory 0x00000000 Internal Flash 0x00400000 ROM 0x00800000 Reserved 0x00C00000 0x1FFFFFFF Internal SRAM DTCM 0x20000000 SRAM 0x20400000 Reserved 0x20C00000 0x3FFFFFFF Peripherals HSMCI 0x40000000 SSC 0x40004000 SPI0 0x40008000 TC0 TC0 0x4000C000 TC0 TC1 +0x40 TC0 TC2 +0x80 TC1 TC3 0x40010000 TC1 TC4 +0x40 TC1 TC5 +0x80 TC2 TC6 0x40014000 TC2 TC7 +0x40 TC2 TC8 +0x80 TWIHS0 0x40018000 TWIHS1 0x4001C000 PWM0 0x40020000 USART0 0x40024000 USART1 0x40028000 USART2 0x4002C000 MCAN0 0x40030000 MCAN1 0x40034000 USBHS 0x40038000 AFEC0 0x4003C000 DACC 0x40040000 ACC 0x40044000 ICM 0x40048000 ISI 0x4004C000 GMAC 0x40050000 TC3 TC9 0x40054000 TC3 TC10 +0x40 TC3 TC11 +0x80 SPI1 0x40058000 PWM1 0x4005C000 TWIHS2 0x40060000 AFEC1 0x40064000 Reserved 0x40068000 AES 0x4006C000 TRNG 0x40070000 BRAM 0x40074000 XDMAC 0x40078000 QSPI 0x4007C000 SMC 0x40080000 SDRAMC 0x40084000 MATRIX 0x40088000 UTMI 0x40090000 PMC 0x400E0600 UART0 0x400E0800 CHIPID 0x400E0940 UART1 0x400E0A00 EFC 0x400E0C00 PIOA 0x400E0E00 PIOB 0x400E1000 PIOC 0x400E1200 PIOD 0x400E1400 PIOE 0x400E1600 0x400E1800 memories EBI Chip Select 0 0x60000000 EBI Chip Select 1 0x61000000 EBI Chip Select 2 0x62000000 EBI Chip Select 3 0x63000000 SDRAM Chip Select 0x70000000 0x7FFFFFFF offset ID (+ : wired-or) peripheralblock I2SC0 I2SC1 0x400E0400 0x4008C000 Peripherals SYSC RSTC 0x400E1800 SYSC SUPC +0x10 SYSC RTT +0x30 SYSC WDT0 +0x50 SYSC RTC +0x60 SYSC GPBR +0x90 SYSC WDT1 +0x100 UART2 0x400E1A00 UART3 0x400E1C00 UART4 0x400E1E00 Reserved 0x400E2000 0x5FFFFFFF Peripherals Reserved

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 10. Memories

10.1 Embedded Memories

10.1.1 Internal SRAM

SAM E70 devices embed 384 Kbytes or 256 Kbytes of high-speed SRAM. The SRAM is accessible over the system Cortex-M bus at address 0x2040 0000. SAM E70 devices embed a Multi-Port SRAM with four ports to optimize the bandwidth and latency. The priorities, defined in the Bus Matrix for each SRAM port slave are propagated, for each request, up to the SRAM slaves. The Bus Matrix supports four priority levels: Normal, Bandwidth-sensitive, Latency-sensitive and Latency-critical in order to increase the overall processor performance while securing the high-priority latency-critical requests from the peripherals. The SRAM controller manages interleaved addressing of SRAM blocks to minimize acce ss latencies. It uses Bus Matrix priorities to give the priority to the most urgent request. The less urgent request is performed no later than the next cycle. Two SRAM slave ports are dedicated to the Cortex-M7 while two ports are shared by the AHB masters.

10.1.2 Tightly Coupled Memory (TCM) Interface

SAM E70 devices embed Tightly Coupled Memory (TCM) running at processor speed.  ITCM is a single 64-bit interface, based at 0x0000 0000 (code region).  DTCM is composed of dual 32-bit interfaces interleaved, based at 0x2000 0000 (data region). ICTM and DTCM are enabled/disabled in the ITCMR and DTCMR registers in ARM SCB. DTCM is enabled by default at reset. ITCM is disabled by default at reset. There are four TCM configurations controlled by software. When enabl ed, ITCM is located at 0x0000 0000, overlapping ROM or Flash depending on the general-purpose NVM bit 1 (GPNVM). The configuration is done with GPNVM bits [8:7]. Accesses made to TCM regions when the relevant TCM is disabled and accesses made to the Code and SRAM region above the TCM size limit are performed on the AHB matrix, i.e., on internal Flash or on ROM depending on remap GPNVM bit. Accesses made to the SRAM above the size limit will not generate aborts. The Memory Protection Unit (MPU) can to be used to protect these areas.

10.1.3 Internal ROM

The SAM E70 embeds an Internal ROM for the SAM Boot Assistant (SAM-BA ®), In Application Programming functions (IAP) and Fast Flash Programming Interface (FFPI). At any time, the ROM is mapped at address 0x0080 0000. The ROM may also be mapped at 0x00000000 depending on GPNVM bit setting and ITCM use. Table 10-1. TCM Configurations in Kbytes ITCM DTCM SRAM for 384K RAM-based SRAM for 256K RAM-based GPNVM Bits [8:7] 0 0 384 256 0 32 32 320 192 1 64 64 256 128 2 128 128 128 0 3

43SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

10.1.4 Backup SRAM

The SAM E70 embeds 1 Kbytes of backup SRAM located at 0x4007 4000. The backup SRAM is accessible in 32-bit words only. Byte or half-word accesses are not supported. The backup SRAM is supplied by VDDCORE in Normal mode. In Backup mode, the backup SRAM supply is automatica lly switched to VDDIO through the backup SRAM power switch when VDDCORE falls. For more details, see Section 6.4 “Backup SRAM Power Switch”.

10.1.5 Flash Memories

SAM E70 devices embed 512 Kbytes, 1024 Kbytes or 2 Mbytes of internal Flash mapped at address 0x40 0000. The devices feature a Quad SPI (QSPI) interface, mapped at address 0x80000000, that extends the Flash size by adding an external SPI or QSPI Flash. When accessed by the Cortex-M7 processor for program ming operations, the QSPI and internal Flash address spaces must be defined in the Cortex-M7 memory protection unit (MPU) with the attribute 'Device' or 'Strongly Ordered'. For fetch or read operations , the attribute ‘Normal memory’ must be set to benefit from the internal cache. Refer to the ARM Cortex-M7 Technical Reference Manual (ARM DDI 0489) available on www.arm.com. Some precautions must be taken when the accesses are performed by the central DMA. Refer to Section 21. “Enhanced Embedded Flash Controller (EEFC)” and Section 41. “Quad SPI Interface (QSPI)”.

10.1.5.1 Embedded Flash Overview

The memory is organized in sectors. Each sector has a size of 128 Kbytes. The first sector is divided into 3 smaller sectors. The three smaller sectors are organized in 2 sectors of 8 Kbytes and 1 sector of 112 Kbytes. Refer to Figure 10-1 below. Figure 10-1. Global Flash Organization Each sector is organized in pages of 512 bytes. For sector 0: 0x000 Small Sector 08 Kbytes Small Sector 18 Kbytes Larger Sector 112 Kbytes Sector 1128 Kbytes

128 Kbytes Sector n

Address Sector size Sector Name

45SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 The memory has one additional reprogrammable page that can be used as page signature by the user. It is accessible through specific modes, for erase, write and read operations. Erase pin assertion will not erase the User Signature page. Erase memory by page is possible only in a sector of 8 Kbytes. EWP and EWPL commands can be only used in 8-Kbyte sectors.

10.1.5.2 Enhanced Embedd ed Flash Controller

Each Enhanced Embedded Flash Controller manages accesses performed by the masters of the system. It enables reading the Flash and writing the write buffer. It also contains a User Interface, mapped on the APB. The Enhanced Embedded Flash Controller ensures the interface of the Flash block. It manages the programming, erasing, locking and unlocking sequences of the Flash using a full set of commands. One of the commands return s the embedded Flash descripto r definition that informs the system about the Flash organization, thus making the software generic.

10.1.5.3 Flash Speed

The user must set the number of wait states depending on the system frequency. For more details, refer to the Embedded Flash Characteristics in Section 56. “Electrical Characteristics”.

10.1.5.4 Lock Regions

Several lock bits are used to protect write and erase oper ations on lock regions. A lock region is composed of several consecutive pages, and each lock region has its associated lock bit. Asserting the ERASE pin clears the lock bits, thus unlocking the entire Flash.

10.1.5.5 Security Bit Feature

The SAM E70 features a security bit based on the GPNVM bit 0. When securi ty is enabled, any access to the Flash, SRAM, core registers and internal peripherals, either through the SW-DP, the ETM interface or the Fast Flash Programming Interface, is blocked. This ensures the confidentiality of the code programmed in the Flash. This security bit can only be enabled through the command “Set General-purpose NVM Bit 0” of the EEFC User Interface. Disabling the security bit ca n only be achieved by asserting the ERASE pin at 1, and after a full Flash erase is performed. When the security bit is deactivated, all accesses to the Flash, SRAM, Core registers, Internal Peripherals are permitted.

10.1.5.6 Unique Identifier

The device contains a unique identifi er of 2 pages of 512 bytes. These 2 pages are read-only and cannot be erased even by the ERASE pin. The sequence to read the unique identifier area is described in Section 21.4.3.8 “Unique Identifier Area”. The mapping is as follows: ̶ Bytes [0..15]: 128 bits for unique identifier ̶ Bytes[16..1023]: Reserved

10.1.5.7 User Signature

Each device contains a user signature of 512 bytes that is available to the user. The user signature can be used to store information such as trimming, keys, etc., that the user does not want to be er ased by asserting the ERASE pin or by software ERASE command. Read, write and erase of this area is allowed. Table 10-2. Flash Lock Bits Flash Size (Kbytes) Number of Lock Bits Lock Region Size 2048 128 16 Kbytes 1024 64 16 Kbytes 512 32 16 Kbytes

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

10.1.5.8 Fast Flash Programming Interface

The Fast Flash Programming Interface allows programming the device through a multiplexed fully-handshaked parallel port. It allows gang programming with market-standard industrial programmers. The FFPI supports read, page program, page erase, full erase, lock, unlock and protect commands. The Fast Flash Programming Interface is enabled and the Fast Programming Mode is entered when TST and PA3 and PA4 are tied low. Table 10-3. FFPI on PIO Controller A (PIOA) I/O Line System Function PD10 PGMEN0 PD11 PGMEN1 PB0 PGMM0 PB1 PGMM1 PB2 PGMM2 PB3 PGMM3 PA3 PGMNCMD PA4 PGMRDY PA5 PGMNOE PA21 PGMNVALID PA7 PGMD0 PA8 PGMD1 PA9 PGMD2 PA10 PGMD3 PA11 PGMD4 PA12 PGMD5 PA13 PGMD6 PA14 PGMD7 PD0 PGMD8 PD1 PGMD9 PD2 PGMD10 PD3 PGMD11 PD4 PGMD12 PD5 PGMD13 PD6 PGMD14 PD7 PGMD15

47SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

10.1.5.9 SAM-BA Boot

The SAM-BA Boot is a default boot program which provides an easy way to program in-situ the on-chip Flash memory. The SAM-BA Boot Assistant supports serial communication via the UART0 and USB. The SAM-BA Boot provides an interface with SAM-BA computer application. The SAM-BA Boot is in ROM at address 0x0 when the bit GPNVM1 is set to 0.

10.1.5.10 General-purpose NVM (GPNVM) Bits

All SAM E70 devices feature nine general-purpose NVM (GPNV M) bits that can be cleared or set, respectively, through the “Clear GPNVM Bit” and “Set GPNVM Bit” commands of the EEFC User Interface. The bit GPNVM0 is the security bit. The bit GPNVM1 is used to select the Boot mode (Boot always at 0x00) on ROM or Flash.

10.1.6 Boot Strategies

The system always boots at address 0x0. To ensure maximum boot possi bilities, the memory layout can be changed using GPNVM bits. A GPNVM bit is used to boot either on the ROM (default) or from the Flash. The GPNVM bit can be cleared or set, respectively, through the commands “Clear General-purpose NVM Bit” and “Set General-purpose NVM Bit” of the EEFC User Interface. Setting the bit GPNVM1 selects boot from the Flash. Clearing it selects boot from the ROM. Asserting ERASE sets the bit GPNVM1 and thus selects boot from ROM.

10.2 External Memories

The SAM E70 features one External Bus Interface to provide an interface to a wide range of external memories and to any parallel peripheral. Table 10-4. General-purpose Non volatile Memory Bits GPNVM Bit Function

0 Security bit

0: ROM (default) 1: Flash 5:2 Free

6 Reserved

8:7 TCM configuration 00: 0 Kbytes DTCM + 0 Kbytes ITCM (default) 01: 32 Kbytes DTCM + 32 Kbytes ITCM 10: 64 Kbytes DTCM + 64 Kbytes ITCM 11: 128 Kbytes DTCM + 128 Kbytes ITCM Note: After programming, a user reboot must be done.

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 11. Event System The events generated by peripherals (source) are designed to be directly routed to peripherals (destination) using these events without processor intervention. The trigger source can be programmed in the destination peripheral.

11.1 Embedded Characteristics

 Timers, PWM, IOs and peripherals generate event triggers which are directly routed to destination peripherals such as AFEC or DACC to start measurement/conversion without processor intervention.  UART, USART, QSPI, SPI, TWI, PWM, HSMCI, AES, AFEC, DACC, PIO, TC (Capture mode) also generate event triggers directly connected to the DMA Controller for data transfer without processor intervention.  Parallel capture logic is directly embedded in the PIO and generates trigger events to the DMA Controller to capture data without processor intervention.  PWM safety events (faults) are in combinational form and directly routed from event generators (AFEC, ACC, PMC, TC) to the PWM module.  PWM output comparators (OCx) generate events directly connected to the TC.  PMC safety event (clock failure detection) can be programmed to switch the MCK on reliable main RC internal clock without processor intervention.

49SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

11.2 Real-time Event Mapping

Table 11-1. Real-time Event Mapping List Function Application Description Event Source Event Destination Safety General-purpose Automatic switch to reliable main RC oscillator in case of main crystal clock failure(1) Power Management Controller (PMC) PMC General-purpose, motor control, power factor correction (PFC) Puts the PWM outputs in Safe mode in case of main crystal clock failure(1)(2) PMC Pulse Width Modulation 0 and 1 (PWM0 and PWM1) Motor control, PFC Puts the PWM outputs in Safe mode (overcurrent detection, etc.)(2)(3) Analog Comparator Controller (ACC) PWM0 and PWM1 Motor control, PFC Puts the PWM outputs in Safe mode (overspeed, overcurrent detection, etc.)(2)(4) Analog Front-End Controller (AFEC0) PWM0 and PWM1 AFEC1 PWM0 and PWM1 Motor control Puts the PWM outputs in Safe mode (overspeed detection through timer quadrature decoder)(2)(6) Timer Counter Block 0 PWM0 Timer Counter Block 1 PWM1 General-purpose, motor control, power factor correction (PFC) Puts the PWM outputs in Safe mode (general-purpose fault inputs)(2) PIO PA9, PD8, PD9 PWM0 PIO PA21, PA26, PA28 PWM1 Security General-purpose Immediate GPBR clear (asynchronous) on tamper detection through WKUP0/1 IO pins (5) PIO WKUP0/1 GPBR Measurement trigger Power factor correction (DC-DC, lighting, etc.) Duty cycle output waveform correction Trigger source selection in PWM(7)(8) ACC PWM0 PIO PA10, PA22 PWM0 ACC PWM1 PIO PA30, PA18 PWM1 General-purpose Trigger source selection in AFEC (9) PIO AFE0_ADTRG AFEC0 TC0 TIOA0 AFEC0 TC0 TIOA1 AFEC0 TC0 TIOA2 AFEC0 ACC AFEC0 Motor control ADC-PWM synchronization(12)(14) Trigger source selection in AFEC(9) PWM0 Event Line 0 and 1 AFEC0 General-purpose Trigger source selection in AFEC (9) PIO AFE1_ADTRG AFEC1 TC1 TIOA3 AFEC1 TC1 TIOA4 AFEC1 TC1 TIOA5 AFEC1 ACC AFEC1 Motor control ADC-PWM synchronization(12)(14) Trigger source selection in AFEC(9) PWM1 Event Line 0 and 1 AFEC1 General-purpose Temperature sensor Low-speed measurement (10)(11) RTC RTCOUT0 AFEC0 and AFEC1

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 Notes: 1. Refer to Section 31.15 “Main Clock Failure Detection”. 3. Refer to Section 52.6.4 “Fault Mode”. 4. Refer to Section 50.5.7 “Fault Output”. Register x”. 6. Refer to Section 48.6.18 “Fault Mode”. 7. Refer to Section 49.7.49 “PWM External Trigger Register”. 8. Refer to Section 49.6.5 “PWM External Trigger Mode”. 10. Refer to Section 50.5.4 “Temperature Sensor”. Conversion trigger General-purpose Trigger source selection in DACC (Digital-to-Analog Converter Controller)(13) TC0 TIOA0, TIOA1, TIOA2 DACC PIO DATRG DACC PWM0 Event Line 0 and 1(14) DACC PWM1 Event Line 0 and 1(14) DACC Image capture Low-cost image sensor Direct image transfer from sensor to system memory via DMA(15) PA22, PA14, PA21 DMA Delay measurement Motor control Propagation delay of external components (IOs, power transistor bridge driver, etc.)(16)(17) PWM0 Comparator Output OC0 TC TIOA0 and TIOB0 PWM0 Comparator Output OC1 TC TIOA1 and TIOB1 PWM0 Comparator Output OC2 TC TIOA2 and TIOB2 PWM1 Comparator Output OC0 TC TIOA3 and TIOB3 PWM1 Comparator Output OC1 TC TIOA4 and TIOB4 PWM1 Comparator Output OC2 TC TIOA5 and TIOB5 PWM0 Comparator Output OC0 TC TIOA6 and TIOB6 PWM0 Comparator Output OC1 TC TIOA7 and TIOB7 PWM0 Comparator Output OC2 TC TIOA8 and TIOB8 PWM1 Comparator Output OC0 TC TIOA9 and TIOB9 PWM1 Comparator Output OC1 TC TIOA10 and TIOB10 Audio clock recovery from Ethernet Audio GMAC GTSUCOMP signal adaptation via TC (TC_EMR.TRIGSRCB) in order to drive the clock reference of the external PLL for the audio clock GMAC GTSUCOMP TC TIOB11 Direct Memory Access General-purpose Peripheral trigger event generation to transfer data to/from system memory(18) USART, UART, TWIHS, SPI, QSPI, AFEC, TC (Capture), SSC, HSMCI, DAC, AES, PWM, PIO, I2SC XDMA Table 11-1. Real-time Event Mapping List (Continued) Function Application Description Event Source Event Destination

51SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 11. Refer to Section 26.5.8 “Waveform Generation”. 12. Refer to Section 49.7.36 “PWM Comparison x Value Register”. 13. Refer to Section 51.7.3 “DACC Trigger Register”. 15. Refer to Section 32.5.14 “Parallel Capture Mode”. 17. Refer to Section 48.6.14 “Synchronization with PWM”. 18. Refer to Section 35. “DMA Controller (XDMAC)”.

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 12. System Controller The System Controller is a set of perip herals that handles key elements of the system, such as power, resets, clocks, time, interrupts, watchdog, etc.

12.1 System Controller and Peripherals Mapping

Refer to Section 9. “Product Mapping”.

12.2 Power-on-Reset, Brow nout and Supply Monitor

The SAM E70 embeds three features to monitor, warn and/or reset the chip:  Power-on-Reset on VDDIO  Power-on-Reset on VDDCORE  Brownout Detector on VDDCORE  Supply Monitor on VDDIO

12.2.1 Power-on-Reset

The Power-on-Reset monitors VDDIO and VDDCORE. It is always activated and moni tors voltage at start up but also during power down. If VDDIO or VDDCORE goes below the threshold voltage, the entire chip is reset. For more information, refer to Section 56. “Electrical Characteristics”.

12.2.2 Brownout Detector on VDDCORE

The Brownout Detector monitors VDDCORE. It is active by default. It can be deactivated by software through the Supply Controller (SUPC_MR). It is especially recommended to disable it during low-power modes such as wait or sleep modes. If VDDCORE goes below the threshold voltage, the reset of the core is asserted. For more information, refer to Section 22. “Supply Controller (SUPC)” and Section 56. “Electrical Characteristics”.

12.2.3 Supply Monitor on VDDIO

The Supply Monitor monitors VDDIO. It is not active by default. It can be activated by software and is fully programmable with 16 steps for the threshold (between 1.6V to 3.4V). It is controlled by the Supply Controller (SUPC). A sample mode is possible. It allows to divide the supply monitor power consumption by a factor of up to 2048. For more information, refer to Section 22. “Supply Controller (SUPC)” and Section 56. “Electrical Characteristics”.

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12.3 Reset Controller

The Reset Controller is based on two Power-on-Reset cells, one on VDDIO and one on VDDCORE, and a Supply Monitor on VDDIO. The Reset Controller returns the source of the last reset to the software. This may be a general reset, a wake-up reset, a software reset, a user reset or a watchdog reset. The Reset Controller controls the internal resets of the system and the pin input/output. It can shape a reset signal for the external devices, simplifying the connection of a push-button on the NRST pin to implement a manual reset. The configuration of the Reset Controller is saved as supplied on VDDIO.

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 13. Peripherals

13.1 Peripheral Identifiers

Table 13-1 defines the peripheral identifiers of the SAM E70. A peripheral identifier is required for the control of the peripheral interrupt with the Nested Vectored Interrupt Controller and control of the peripheral clock with the Power Management Controller. Table 13-1. Peripheral Identifiers Instance ID Instance Name NVIC Interrupt PMC Clock Control Description

0 SUPC X – Supply Controller

1 RSTC X – Reset Controller

2 RTC X – Real Time Clock

3 RTT X – Real Time Timer

4 WDT X – Watchdog Timer

5 PMC X – Power Management Controller

6 EFC X – Enhanced Embedded Flash Controller

7 UART0 X X Universal Asynchronous Receiver/Transmitter

8 UART1 X X Universal Asynchronous Receiver/Transmitter

9 SMC – X Static Memory Controller

10 PIOA X X Parallel I/O Controller A

11 PIOB X X Parallel I/O Controller B

12 PIOC X X Parallel I/O Controller C

13 USART0 X X Universal Synchronous/Asynchronous

14 USART1 X X Universal Synchronous/Asynchronous

15 USART2 X X Universal Synchronous/Asynchronous

16 PIOD X X Parallel I/O Controller D

17 PIOE X X Parallel I/O Controller E

18 HSMCI X X Multimedia Card Interface

19 TWIHS0 X X Two-wire Interface

20 TWIHS1 X X Two-wire Interface

21 SPI0 X X Serial Peripheral Interface

22 SSC X X Synchronous Serial Controller

23 TC0 X X 16-bit Timer Counter Channel 0

24 TC1 X X 16-bit Timer Counter Channel 1

25 TC2 X X 16-bit Timer Counter Channel 2

26 TC3 X X 16-bit Timer Counter Channel 3

27 TC4 X X 16-bit Timer Counter Channel 4

28 TC5 X X 16-bit Timer Counter Channel 5

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29 AFEC0 X X Analog Front-End Controller

30 DACC X X Digital-to-Analog Converter

31 PWM0 X X Pulse Width Modulation Controller

32 ICM X X Integrity Check Monitor

33 ACC X X Analog Comparator Controller

34 USBHS X X USB Host / Device Controller

35 MCAN0 X X CAN IRQ Line 0

36 MCAN0 INT1 – CAN IRQ Line 1

37 MCAN1 X X CAN IRQ Line 0

38 MCAN1 INT1 – CAN IRQ Line 1

39 GMAC X X Ethernet MAC

40 AFEC1 X X Analog Front End Controller

41 TWIHS2 X X Two-wire Interface

42 SPI1 X X Serial Peripheral Interface

43 QSPI X X Quad I/O Serial Peripheral Interface

44 UART2 X X Universal Asynchronous Receiver/Transmitter

45 UART3 X X Universal Asynchronous Receiver/Transmitter

46 UART4 X X Universal Asynchronous Receiver/Transmitter

47 TC6 X X 16-bit Timer Counter Channel 6

48 TC7 X X 16-bit Timer Counter Channel 7

49 TC8 X X 16-bit Timer Counter Channel 8

50 TC9 X X 16-bit Timer Counter Channel 9

51 TC10 X X 16-bit Timer Counter Channel 10

52 TC11 X X 16-bit Timer Counter Channel 11

53 – – – Reserved 54 – – – Reserved 55 – – – Reserved

56 AES X X Advanced Encryption Standard

57 TRNG X X True Random Number Generator

58 XDMAC X X DMA Controller

59 ISI X X Image Sensor Interface

60 PWM1 X X Pulse Width Modulation Controller

61 ARM FPU – ARM Floating Point Unit interrupt associated with OFC,

UFC, IOC, DZC and IDC bits

62 SDRAMC X – SDRAM Controller

63 RSWDT X – Reinforced Safety Watchdog Timer

64 ARM CCW – ARM Cache ECC Warning

Table 13-1. Peripheral Identifiers (Continued) Instance ID Instance Name NVIC Interrupt PMC Clock Control Description

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65 ARM CCF – ARM Cache ECC Fault

66 GMAC Q1 –

GMAC Queue 1 Interrupt signal toggled on a DMA write to the first word of each DMA data buffer associated with queue 1

67 GMAC Q2 –

GMAC Queue 2 Interrupt signal toggled on a DMA write to the first word of each DMA data buffer associated with queue 2

68 ARM IXC – Floating Point Unit Interrupt IXC associated with FPU

69 I2SC0 X X Inter-IC Sound Controller

70 I2SC1 X X Inter-IC Sound Controller

Table 13-1. Peripheral Identifiers (Continued) Instance ID Instance Name NVIC Interrupt PMC Clock Control Description

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13.2 Peripheral Signal Multiplexing on I/O Lines

̶ two PIO controllers on 64-pin versions (PIOA and PIOB) ̶ three PIO controllers on the 100-pin version (PIOA, PIOB and PIOD) ̶ five PIO controllers on the 144-pin version (PIOA, PIOB, PIOC, PIOD and PIOE), that multiplex the I/O lines of the peripheral set. The SAM E70 PIO Controllers control up to 32 lines. Each line can be assigned to one of four peripheral functions: A, B, C or D. For more information on multiplexed signals, refer to Section 5. “Package and Pinout”.

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 14. ARM Cortex-M7 Processor

14.1 Description

The ARM Cortex-M7 processor implements the ARMv7-M ar chitecture and runs 32-bit ARM instructions, 16-bit and 32-bit Thumb instructions. The double-precision Floating-Point Unit (FPU) supports the ARMv7 VFPv5 architecture. It is tightly integrated to the ARM Cortex-M7 processor pipeline. It provides trapless ex ecution and is optimized for scalar operation. It can generate an Undefined instruction exception on vector instructions that enables the programmer to emulate vector capability in software. Note: Refer to ARM reference documents Cortex-M7 Processor User Guide (ARM DUI 0644) and Cortex-M7 Technical Reference Manual (ARM DDI 0489), available on www.arm.com.

14.1.1 System-Level Interface

The ARM Cortex-M7 processor provides multiple interfaces using AMBA technology to provide high-speed, low- latency memory accesses. It supports unaligned data ac cesses and implements atomic bit manipulation that enables faster peripheral controls, system spinlocks and thread-safe Boolean data handling. The ARM Cortex-M7 processor has a Memory Protection Un it (MPU) that provides fine-grain memory control, enabling applications to utilize multiple privilege levels, separating and protecting code, data and stack on a task- by-task basis. Such requirements are becoming critical in many embedded applications such as automotive.

14.1.2 Integrated Configurable Debug

The ARM Cortex-M7 processor implements a complete hardware debug solution. This provides high system visibility of the processor and memory through a 2-pi n Serial Wire Debug (SWD) port that is ideal for microcontrollers and other small package devices. For system trace, the processor integrates an Instrumentation Trace Macrocell (ITM) alongside data watchpoints and a profiling unit. To enable simple and cost-effective profiling of the system events these generate, a Serial Wire Viewer (SWV) can export a stream of software-generated messages, data trace, and profiling information through a single pin. The Embedded Trace Macrocell (ETM) delivers unrivalled instruction trace capture in an area far smaller than traditional trace units, enabling many low-cost MCUs to implement full instruction trace for the first time. The Flash Patch and Breakpoint Unit (FPB) provides up to eight hardware breakpoint comparators that debuggers can use. The comparators in the FPB also provide remap functions of up to eight words in the program code in the CODE memory region. This enables applications stored on a non-erasable, ROM-based microcontroller to be patched if a small programmable memory, for example Flash, is available in th e device. During initialization, the application in ROM detects, from the programmable memory, whether a patch is required. If a patch is required, the application programs the FPB to remap a number of addresses. When those addresses are accessed, the accesses are redirected to a remap table specified in the FPB configuration, which means the program in the non- modifiable ROM can be patched.

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14.2 Embedded Characteristics

 ARM Cortex-M7 with 16 KB of instruction cache and 16 KB of data cache  ARMv7-M Thumb instruction set combines high-code density with 32-bit performance  Tightly Coupled Memory (TCM) interfaces: ̶ 64-bit ITCM interface ̶ 2 x 32-bit DTCM interfaces  Memory Protection Unit (MPU): up to 16 protected memory regions for safety/critical applications  Dedicated low-latency AHB-Lite peripheral (AHBP) interface  Dedicated AHB slave (AHBS) interface for system access to TCMs  Low-latency interrupt processing achieved by a Nested Vectored Interrupt Controller (NVIC) closely integrated with the processor  DSP extensions for efficient signal processing and complex algorithm execution  IEEE Standard 754-2008 Floating Point Unit (FPU)  Hardware integer divide instructions  Extensive debug and trace capabilities: ̶ Serial Wire Debug and Serial Wire Trace reduce the number of pins required for debugging, tracing, and code profiling

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14.3 Block Diagram

Figure 14-1. ARM Cortex-M7 Processor Top-level Diagram Cortex-M7 Processor Cortex-M7 Breakpoint Unit ATB Instruction ATB Data External PPB ATB Instrumentation Memory Protection Unit ETM-M7 and Trace Unit Instrumentation Trace Processor ROM Table PPB ROM Table External Memory System AXIM FPU NVIC AHBD D0TCM D1TCM ITCM AHBS AHBP Interrupts Debugger Peripherals Memory DMA Processor Core Macrocell Data Watchpoint

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14.4 Programmer’s Model

This section describes the ARM Cort ex-M7 programmer’s model. In addition to the individual core register descriptions, it contains information about the proce ssor modes and privilege levels for software execution and stacks.

14.4.1 Processor Modes and Privilege Levels for Software Execution

The processor modes are:  Thread mode Used to execute application software. The processor enters Thread mode when it comes out of reset.  Handler mode Used to handle exceptions. The processor returns to Thread mode when it has finished exception processing. The privilege levels for software execution are:  Unprivileged The software: ̶ Has limited access to the MSR and MRS instructions, and cannot use the CPS instruction ̶ Cannot access the System Timer, NVIC, or System Control Block ̶ Might have a restricted access to memory or peripherals. Unprivileged software executes at the unprivileged level.  Privileged The software can use all the instructions and has access to all resources. Privileged software executes at the privileged level. In Thread mode, the Control Register controls whether the software exec ution is privileged or unprivileged, see “Control Register” . In Handler mode, software execution is always privileged. Only privileged software can write to the Control Register to change the privilege level for software execution in Thread mode. Unprivileged software can use the SVC instruction to make a supervisor call to transfer control to privileged software.

14.4.2 Stacks

The processor uses a full descending st ack. This means the stack pointer hol ds the address of the last stacked item in memory When the processor pushes a new item onto the stack, it decrement s the stack pointer and then writes the item to the new memory location. The processor implements two stacks, the main stack and the process stack, with a pointer for each held in independent registers, see “Stack Pointer” . In Thread mode, the Control Register controls whether the processor uses the main stack or the process stack, see “Control Register” . In Handler mode, the processor always uses the main stack. The options for processor operations are: Note: 1. See “Control Register” . Table 14-1. Summary of Processor Mode, Execution Privilege Level, and Stack Use Options Processor Mode Used to Execute Privilege Level for Software Execution Stack Used Thread Applications Privileged or unprivileged (1) Main stack or process stack(1) Handler Exception handlers Always privileged Main stack

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14.4.2.1 Processor Core Registers

Figure 14-2. Processor Core Registers Notes: 1. Describes access type during program execution in Thread mode and Handler mode. Debug access can differ. 2. An entry of Either means privileged and unprivileged software can access the register. SP (R13) LR (R14) PC (R15) R10 R11 R12 Low registers High registers MSP‡PSP‡ PSR PRIMASK FAULTMASK BASEPRI CONTROL General-purpose registers Stack Pointer Link Register Program Counter Program status register Exception mask registers CONTROL register Special registers ‡Banked version of SP Table 14-2. Processor Core Registers Register Name Access (1) Required Privilege(2) Reset General-purpose registers R 0–R12 Read/Write Either Unknown Stack Pointer MSP Read/Write Privileged See Section 14.4.4 Stack Pointer PSP Read/Write Either Unknown Link Register LR Read/Write Either 0xFFFFFFFF Program Counter PC Read/Write Either See Section 14.4.6.1 Program Status Register PSR Read/Write Privileged 0x01000000 Application Program Status Register APSR Read/Write Either 0x00000000 Interrupt Program Status Register IPSR Read-only Privileged 0x00000000 Execution Program Status Register EPSR Read-only Privileged 0x01000000 Priority Mask Register PRIMASK Read/Write Privileged 0x00000000 Fault Mask Register FAULTMASK Read/Write Privileged 0x00000000 Base Priority Mask Register BASEPRI Read/Write Privileged 0x00000000 Control Register CONTROL Read/Write Privileged 0x00000000

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14.4.3 General-purpose Registers

R0–R12 are 32-bit general-purpose registers for data operations.

14.4.4 Stack Pointer

The Stack Pointer (SP) is register R13. In Thread mode, bit[1] of the Control Register indicates the stack pointer to use:  0 = Main Stack Pointer (MSP). This is the reset value.  1 = Process Stack Pointer (PSP). On reset, the processor loads the MSP with the value from address 0x00000000.

14.4.5 Link Register

The Link Register (LR) is register R14. It stores the return information for subroutines, function calls, and exceptions. On reset, the processor loads the LR value 0xFFFFFFFF.

14.4.6 Program Counter

The Program Counter (PC) is register R15. It contains the current program address. On reset, the processor loads the PC with the value of the reset vector, which is at address 0x00000004. Bit[0] of the value is loaded into the EPSR T-bit at reset and must be 1.

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14.4.6.1 Program Status Register

Name: PSR Access: Read/Write The Program Status Register (PSR) combines:

• Application Program Status Register (APSR)  Interrupt Program Status Register (IPSR)  Execution Program Status Register (EPSR). These registers are mutually exclusive bitfields in the 32-bit PSR. The PSR accesses these registers individually or as a combination of any two or all three registers, using the register name as an argument to the MSR or MRS instructions. For example: R ead of all the registers using PSR with the MRS instruction  Write to the APSR N, Z, C, V and Q bits using APSR_nzcvq with the MSR instruction. The PSR combinations and attributes are: Notes: 1. The processor ignores writes to the IPSR bits. 2. Reads of the EPSR bits return zero, and the processor ignores writes to these bits. For more information about how to access the program status registers, see description of instructions “MRS” and “MSR” in the relevant ARM documentation. 31 30 29 28 27 26 25 24 NZCVQ I CI/IT T 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 ICI/IT – ISR_NUMBER 76543210 ISR_NUMBER Name Access Combination PSR Read/Write(1)(2) APSR, EPSR, and IPSR IEPSR Read-only EPSR and IPSR IAPSR Read/Write (1) APSR and IPSR EAPSR Read/Write (2) APSR and EPSR

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14.4.6.2 Application Program Status Register

Name: APSR Access: Read/Write The APSR contains the current state of the condition flags from previous instruction executions.

• N: Negative Flag 0: Operation result was positive, zero, greater than, or equal 1: Operation result was negative or less than.
• Z: Zero Flag 0: Operation result was not zero 1: Operation result was zero.
• C: Carry or Borrow Flag Carry or borrow flag: 0: Add operation did not result in a carry bit or subtract operation resulted in a borrow bit 1: Add operation resulted in a carry bit or subtract operation did not result in a borrow bit.
• V: Overflow Flag 0: Operation did not result in an overflow 1: Operation resulted in an overflow.
• Q: DSP Overflow and Saturation Flag Sticky saturation flag: 0: Indicates that saturation has not occurred since reset or since the bit was last cleared to zero 1: Indicates when an SSAT or USAT instruction results in saturation. This bit is cleared to zero by software using an MRS instruction.
• GE[19:16]: Greater Than or Equal Flags For more information, see description of the “SEL” instruction in the relevant ARM documentation. 31 30 29 28 27 26 25 24 NZCVQ – 23 22 21 20 19 18 17 16 – GE[3:0] 15 14 13 12 11 10 9 8 76543210

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14.4.6.3 Interrupt Program Status Register

Name: IPSR Access: Read/Write The IPSR contains the exception type number of the current Interrupt Service Routine (ISR).

• ISR_NUMBER: Number of the Current Exception 0 = Thread mode 1 = Reserved 2 = NMI 3 = Hard fault 4 = Memory management fault 5 = Bus fault 6 = Usage fault 7–10 = Reserved 11 = SVCall 12 = Reserved for Debug 13 = Reserved 14 = PendSV 15 = SysTick 16 = IRQ0 ... 75 = IRQ72 For more information, see “Exception Types” in the relevant ARM documentation. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 – ISR_NUMBER 76543210 ISR_NUMBER

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14.4.6.4 Execution Progr am Status Register

Name: EPSR Access: Read/Write The EPSR contains the Thumb state bit, and the execution state bits for either the If-Then (IT) instruction, or the Interrupt- ible-Continuable Instruction (ICI) field for an interrupted load multiple or store multiple instruction. Attempts to read the EPSR directly through application software using the MSR instruction always return zero. Attempts to write the EPSR using the MSR instruction in the application software are ignored. Fault handlers can examine the EPSR value in the stacked PSR to indicate the operation that is at fault. For more information, see “Exception Entry and Return” in the relevant ARM documentation.

• ICI: Interruptible-continuable Instruction When an interrupt occurs during the execution of an LDM, STM, PUSH, POP, VLDM, VSTM, VPUSH, or VPOP instruction, the processor: – Stops the load multiple or store multiple instruction operation temporarily – Stores the next register operand in the multiple operation to EPSR bits[15:12]. After servicing the interrupt, the processor: –R e t u r ns to the register pointed to by bits[15:12] –R e sumes the execution of the multiple load or store instruction. When the EPSR holds the ICI execution state, bits[26:25,11:10] are zero.
• IT: If-Then Instruction Indicates the execution state bits of the IT instruction. The If-Then block contains up to four instructions following an IT instruction. Each instruction in the block is conditional. The conditions for the instructions are either all the same, or some can be the inverse of others. For more information, see description of the “IT” instruction in the relevant ARM documentation.
• T: Thumb State The ARM Cortex-M7 processor only supports the execution of instructions in Thumb state. The following can clear the T bit to 0: –I n structions BLX, BX and POP{PC} –R es toration from the stacked xPSR value on an exception return – Bit[0] of the vector v alue on an exception entry or reset. Attempting to execute instructions when the T bit is 0 results in a fault or lockup. For more information, see description of the “Lockup” instruction in the relevant ARM documentation. 31 30 29 28 27 26 25 24 –I CI/IT T 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 ICI/IT – 76543210

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14.4.6.5 Exception Mask Registers

The exception mask registers disable the handling of exce ptions by the processor. Disable exceptions where they might impact on timing critical tasks. To access the exception mask registers use the MSR and MRS instructions, or the CPS instruction to change the value of PRIMASK or FAULTMASK. For more information, see descriptions of the “MRS”, “MSR” and “CPS” instructions in the relevant ARM documentation.

14.4.6.6 Priority Mask Register

Name: PRIMASK Access: Read/Write The PRIMASK register prevents the activation of all exceptions with a configurable priority.

• P R I M A S K 0: No effect. 1: Prevents the activation of all exceptions with a configurable priority. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 – PRIMASK

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14.4.6.7 Fault Mask Register

Name: FAULTMASK Access: Read/Write The FAULTMASK register prevents the activation of all exceptions except for Non-Maskable Interrupt (NMI). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 – FAULTMASK

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• FAULTMASK 0: No effect. 1: Prevents the activation of all exceptions except for NMI. The processor clears the FAULTMASK bit to 0 on exit from any exception handler except the NMI handler.

14.4.6.8 Base Priority Mask Register

Name: BASEPRI Access: Read/Write The BASEPRI register defines the minimum priority for exception processing. When BASEPRI is set to a nonzero value, it prevents the activation of all exceptions with same or lower priority level as the BASEPRI value.

• BASEPRI Priority mask bits: 0: No effect Nonzero: Defines the base priority for exception processing The processor does not process any exception with a priority value greater than or equal to BASEPRI. This field is similar to the priority fields in the interrupt priority registers. The processor implements only bits[7:4] of this field, bits[3:0] read as zero and ignore writes. See “Interrupt Priority Registers” in the relevant ARM documentation. Remember that higher priority field values correspond to lower exception priorities. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 BASEPRI

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14.4.6.9 Control Register

Name: CONTROL Access: Read/Write The Control Register controls the stack used and the privilege level for software execution when the processor is in Thread mode and indicates whether the FPU state is active.

• FPCA: Floating-point Context Active Indicates whether the floating-point context is currently active: 0: No floating-point context active. 1: Floating-point context active. The ARM Cortex-M7 uses this bit to determine whether to preserve the floating-point state when processing an exception.
• SPSEL: Active Stack Pointer Defines the current stack: 0: MSP is the current stack pointer. 1: PSP is the current stack pointer. In Handler mode, this bit reads as zero and ignores writes. The ARM Cortex-M7 updates this bit automatically on exception return.
• nPRIV: Thread Mode Privilege Level Defines the Thread mode privilege level: 0: Privileged. 1: Unprivileged. Handler mode always uses the MSP, so the processor ignores explicit writes to the active stack pointer bit of the Control Register when in Handler mode. The exception entry and return mechanisms update the Control Register based on the EXC_RETURN value. In an OS environment, ARM recommends that threads running in Thread mode use the process stack, and the kernel and exception handlers use the main stack. By default, the Thread mode uses the MSP. To switch the stack pointer used in Thread mode to the PSP, either:
• Use the MSR instruction to set the Active stack pointer bit to 1, or
• Perform an exception return to Thread mode with the appropriate EXC_RETURN value. Note: When changing the stack pointer, the software must use an I SB instruction immediately after the MSR instruction. This ensures that instructions after the ISB execute using the new stack pointer. For more information, see description of the “ISB” instruction in the relevant ARM documentation. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 – FPCA SPSEL nPRIV

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14.4.6.10 Exceptions and Interrupts

The ARM Cortex-M7 processor supports interrupts an d system exceptions. Th e processor and the Nested Vectored Interrupt Controller (NVIC) prioritize and handle all exceptions. An exception changes the normal flow of software control. The processor uses the Handler mode to handle all exceptions except for reset. See “Exception Entry” and “Exception Return” in the relevant ARM documentation for more information. The NVIC registers control interrupt handling. See “Nested Vectored Interrupt Controller (NVIC)” in the relevant ARM documentation for more information.

14.4.6.11 Data Types

The processor supports the following data types:  32-bit words  16-bit halfwords  8-bit bytes  32-bit single-precision floating point numbers  64-bit double-precision floating point numbers  The processor manages all data memory accesses as little-endian. Instruction memory and Private Peripheral Bus (PPB) accesses are always little-endian. See “Memory Regions, Types and Attributes” in the relevant ARM documentation for more information.

14.4.6.12 Cortex Microcontroller Software Interface Standard (CMSIS)

For an ARM Cortex-M7 microcontroller system, the Cortex Microcontroller Software Interface Standard (CMSIS) defines:  A common way to: ̶ Access peripheral registers ̶ Define exception vectors  The names of: ̶ The registers of the core peripherals ̶ The core exception vectors  A device-independent interface for RTOS kernels, including a debug channel. The CMSIS includes address definitions and data struct ures for the core peripherals in the ARM Cortex-M7 processor. The CMSIS simplifies the software deve lopment by enabling the reuse of template code and the combination of CMSIS-compliant software components from various middleware vendors. Software vendors can expand the CMSIS to include their peripheral definitions and access functions for those peripherals. This document includes the register names defined by the CMSIS, and gives short descriptions of the CMSIS functions that address the processor core and the core peripherals. Note: This document uses the register shor t names defined by the CMSIS. In a few cases, these differ from the architectural short names that might be used in other documents. More information about the CMSIS can be found in the relevant ARM documentation.

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14.5 ARM Cortex-M7 Configuration

Table 14-3 gives the configuration for the ARM Cortex-M7 processor. For more details, refer to the ARM documentation referenced in Section 14.1 Table 14-3. ARM Cortex-M7 Configuration Features Configuration Debug Comparator set Full comparator set: 4 DWT and 8 FPB comparators ETM support Instruction ETM interface Internal Trace support (ITM) ITM and DWT trace functionality implemented CTI and WIC Not embedded TCM ITCM max size 128 KB DTCM max size 128 KB Cache Cache size 16 KB for instruction cache, 16 KB for data cache Number of sets 256 for instruction cache, 128 for data cache Number of ways 2 for instruction cache, 4 for data cache Number of words per cache line 8 words (32 bytes) ECC on Cache Embedded NVIC IRQ number 72 IRQ priority levels 8 MPU Number of regions 16 FPU FPU precision Single and double precision AHB Port AHBP addressing size 512 MB

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 15. Debug and Test Features

15.1 Description

The device features a number of complementary debug and test capabilities. The Serial Wire Debug Port (SW-DP) is used for standard debugging functions, such as downloading code and single-stepping through programs. It also embeds a serial wire trace.

15.2 Embedded Characteristics

 Debug access to all memory and registers in the system, including Cortex-M register bank, when the core is running, halted, or held in reset.  Serial Wire Debug Port (SW-DP) debug access  Flash Patch and Breakpoint (FPB) unit for implementing breakpoints and code patches  Data Watchpoint and Trace (DWT) unit for implementing watchpoints, data tracing, and system profiling  Instrumentation Trace Macrocell (ITM) for support of printf style debugging  6-pin Embedded Trace Macrocell (ETM) for instruction trace stream, including CoreSight™ Trace Port Interface Unit (TPIU)  IEEE1149.1 JTAG Boundary scan on All Digital Pins

15.3 Associated Documents

The SAM E70 implements the standard ARM CoreSight macrocell. For information on CoreSight, the following reference documents are available from the ARM web site: ̶ Cortex-M7 User Guide Reference Manual (ARM DUI 0644) ̶ Cortex-M7 Technical Reference Manual (ARM DDI 0489) ̶ CoreSight Technology System Design Guide (ARM DGI 0012) ̶ CoreSight Components Technical Reference Manual (ARM DDI 0314) ̶ ARM Debug Interface v5 Architecture Specification (Doc. ARM IHI 0031) ̶ ARMv7-M Architecture Reference Manual (ARM DDI 0403)

75SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

15.4 Debug and Test Block Diagram

Figure 15-1. Debug and Test Block Diagram

15.5 Debug and Test Pin Description

(TAP) Serial Wire Debug Port Reset and Test POR Embedded Trace Macrocell PIO TRACED0–3 Cortex-M7 PCK3 TRACECLK Table 15-1. Debug and Test Signal List Signal Name Function Type Active Level Reset/Test NRST Microcontroller Reset Input/Output Low TST Test Select Input – Serial Wire Debug Port/JTAG Boundary Scan TCK/SWCLK Test Clock/Se rial Wire Clock Input – TDI Test Data In Input – TDO/TRACESWO Test Data Out/Trac e Asynchronous Data Out Output – TMS/SWDIO Test Mode Select/Serial Wire Input/Output Input – JTAGSEL JTAG Selection Input High Trace Debug Port TRACECLK Trace Clock Output – TRACED0–3 Trace Data Output –

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

15.6 Application Examples

15.6.1 Debug Environment

Figure 15-2 shows a complete debug environment example. The SW-DP interface is used for standard debugging functions, such as downloading code and single-stepping through the program and viewing core and peripheral registers. Figure 15-2. Application Debug Environment Example SAM x7 Host Debugger PC Cortex-M7-based Application Board Serial Wire Debug Port Connector Serial Wire Debug Port Emulator/Probe

77SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

15.6.2 Test Environment

Figure 15-3 shows a test environment example (JTAG Boundary scan). Test vectors are sent and interpreted by the tester. In this example, the “boa rd in test” is designed using a number of JTAG-compliant devices. These devices can be connected to form a single scan chain. Figure 15-3. Application Test Environment Example Chip 2Chip n Chip 1SAM x7 Cortex-M7-based Application Board In Test JTAG Connector Tester Test Adaptor JTAG Probe

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

15.7 Functional Description

15.7.1 Test Pin

The TST pin is used for JTAG Boundary Scan Manufacturing Test or Fast Flash Programming mode. The TST pin integrates a permanent pull-down resistor of about 15 kΩ to GND, so that it can be left unconnected for normal operations. To enable Fast Flash Programming mode, refer to Section 17. “Fast Flas h Programming Interface (FFPI)”.

15.7.2 Debug Architecture

Figure 15-4 shows the debug architecture used. The Cortex-M7 embeds six functional units for debug:  Serial Wire Debug Port (SW-DP) debug access  FPB (Flash Patch Breakpoint)  DWT (Data Watchpoint and Trace)  ITM (Instrumentation Trace Macrocell)  6-pin Embedded Trace Macrocell (ETM) for instruction trace stream, including CoreSight Trace Port Interface Unit (TPIU)  IEEE1149.1 JTAG Boundary scan on all digital pins The debug architecture information that follows is mainly dedicated to developers of SW-DP Emulators/Probes and debugging tool vendors for Cortex-M7-based microcontrollers. For further details on SW-DP, see the Cortex - M7 Technical Reference Manual. Figure 15-4. Debug Architecture

15.7.3 Serial Wire Debug Port (SW-DP) Pins

The SW-DP pins SWCLK and SWDIO are commonly provided on a standard 20-pin JTAG connector defined by ARM. For more details on voltage reference and reset state, refer to Section 4. “Signal Description”. At startup, SW-DP pins are configured in SW-DP mode to allow connection with debugging probe. SW-DP pins can be used as standard I/Os to provide users more general input/output pins when the debug port is not needed in the end application. Mode selection between SW-DP mode (System I/O mode) and general I/O mode is performed through the AHB Matrix Chip Configuration registers (CCFG_SYSIO). Configuration of the pad for pull-up, triggers, debouncing and glitch filters is possible regardless of the mode.

4 Watchpoints

6 Breakpoints

Instrumentation Trace Macrocell Serial Wire Debug Serial Wire Debug Port Serial Wire Output Trace Instruction Trace Time Stamping Embedded Trace Macrocell Trace Port

79SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level. It integrates a permanent pull-down resistor of about 15 kΩ to GND, so that it can be left unconnected for normal operations. The JTAG debug ports TDI, TDO, TMS and TCK are inactive. They are provided for Boundary Scan Manufacturing Test purposes only. By default the SW-DP is active; TDO/TRACESWO can be used for trace. SW-DP is selected when JTAGSEL is low. It is not possible to switch directly between SW-DP and JTAG boundary scan operations. A chip reset must be performed after JTAGSEL is changed. Table 15-2. SW-DP Pin List Pin Name JTAG Boundary Scan Serial Wire Debug Port TMS/SWDIO TMS SWDIO TCK/SWCLK TCK SWCLK TDI TDI – TDO/TRACESWO TDO TRACES WO (optional: trace)

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

15.7.4 Embedded Trace Module (ETM) Pins

The Embedded Trace Module (ETM) uses the Trace Port Interface Unit (TPIU) to export data out of the system. The TPUI features the pins:  TRACECLK–always exported to enable synchronization back with the data. PCK3 is used internally.  TRACED0–3–the instruction trace stream.

15.7.5 Flash Patch Breakpoint (FPB)

The FPB implements hardware breakpoints.

15.7.6 Data Watchpoint and Trace (DWT)

The DWT contains four comparators which can be configured to generate:  PC sampling packets at set intervals  PC or Data watchpoint packets  Watchpoint event to halt core The DWT contains counters for:  Clock cycle (CYCCNT)  Folded instructions  Load Store Unit (LSU) operations  Sleep cycles  CPI (all instruction cycles except for the first cycle)  Interrupt overhead

15.7.7 Instrumentation Trace Macrocell (ITM)

The ITM is an application driven trace source that supports printf style debugging to trace Operating System (OS) and application events , and emits diagnostic system information. The ITM emits trace information as packets which can be generated by three different sources with several priority levels:  Software trace: Software can write directly to ITM stimulus registers. This can be done using the “printf” function. For more information, refer to Section 15.7.5 “Flash Patch Breakpoint (FPB)”.  Hardware trace: The ITM emits packets generated by the DWT.  Time stamping: Timestamps are emitted relative to packets. The ITM contains a 21-bit counter to generate the timestamp.

15.7.7.1 How to Configure the ITM

The following example describes how to output trace data in asynchronous trace mode. 2. Enable the write accesses into the ITM registers by writing “0xC5ACCE55” into the Lock Access Register (Address: 0xE0000FB0) 3. Write 0x00010015 into th e Trace Control register: ̶ Enable ITM. ̶ Enable Synchronization packets. ̶ Enable SWO behavior. ̶ Fix the ATB ID to 1. 4. Write 0x1 into the Trace Enable register: ̶ Enable the Stimulus port 0. 5. Write 0x1 into the Trace Privilege register:

81SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 ̶ Stimulus port 0 only accessed in privileged mode (Clearing a bit in this register will result in the corresponding stimulus port being accessible in user mode.) 6. Write into the Stimulus port 0 regist er: TPIU (Trace Port Interface Unit) The TPIU acts as a bridge between the on-chip trace data and the Instruction Trace Macrocell (ITM). The TPIU formats and transmits trace data off-chip at frequencies asynchronous to the core.

15.7.7.2 Asynchronous Mode

The TPIU is configured in asynchronous mode, trace data are output using the single TRACESWO pin. The TRACESWO signal is multiplexed with the TDO signal. As a consequence, asynchronous trace mode is only available when the Serial Wire Debug mode is selected. Two encoding formats are available for the single pin output:  Manchester encoded stream. This is the reset value.  NRZ_based UART byte structure

15.7.7.3 How to Configure the TPIU

This example only concerns the asynchronous trace mode. 1. Set the TRCENA bit to 1 into the Debug Exception and Monitor Register (0xE000EDFC) to enable the use of trace and debug blocks. 2. Write 0x2 into the Selected Pin Protocol Register. ̶ Select the Serial Wire output – NRZ 3. Write 0x100 into the Formatter and Flush Control Register. 4. Set the suitable clock prescaler value into the Async Clo ck Prescaler Register to scale the baud rate of the asynchronous output (this can be done automatically by the debugging tool). 15.7.8 IEEE1149.1 JT AG Boundary Scan IEEE1149.1 JTAG Boundary Scan allows pin-level access independent of the device packaging technology. IEEE1149.1 JTAG Boundary Scan is enabled when TST is tied to high, PD0 tied to low, and JTAGSEL tied to high during power-up. These pins must be maintained in their respective states for the duration of the boundary scan operation. The SAMPLE, EXTEST and BYPASS functions are implemented. In Serial Wire Debug mode, the ARM processor responds with a non-JTAG chip ID that id entifies the processor. Th is is not IEEE1149.1 JTAG- compliant. It is not possible to switch directly between JTAG Boun dary Scan and SWJ Debug Port operations. A chip reset must be performed after JTAGSEL is changed. A Boundary Scan Descriptor Language (BSDL) file to set up the test is provided on www.atmel.com.

15.7.8.1 JTAG Boundary Scan Register

The Boundary Scan Register (BSR) contains a number of bits which corres pond to active pins and associated control signals. Each input/output pin corresponds to a 3-bit register in the BSR. The OUTPUT bit contains data that can be forced on the pad. The INPUT bit facilitates th e observability of data applied to t he pad. The CONTROL bit selects the direction of the pad. For more information, refer to BDSL files available on www.atmel.com.

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

15.7.9 ID Code Register

Access: Read-only

• VERSION[31:28]: Pr oduct Version Number Set to 0x0.
• PART NUMBER[27:12]: Product Part Number
• MANUFACTURER IDENTITY[11:1] Set to 0x01F.
• Bit[0] Required by IEEE Std. 1149.1. Set to 0x1. 31 30 29 28 27 26 25 24 VERSION PART NUMBER 23 22 21 20 19 18 17 16 PART NUMBER 15 14 13 12 11 10 9 8 PART NUMBER MANUFACTURER IDENTITY 76543210 MANUFACTURER IDENTITY 1 PART NUMBER 0x5B3D JTAG ID Code 0x05B3_D03F

83SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 16. SAM-BA Boot Program

16.1 Description

The SAM-BA Boot Program integrates an array of programs permitting download and/or upload into the different memories of the product.

16.2 Embedded Characteristics

 Default Boot Program  Interface with SAM-BA Graphic User Interface  SAM-BA Boot ̶ Supports several communication media  Serial Communication on UART0  USB device port communication up to 1Mbyte/s ̶ USB Requirements  External crystal or external clock with frequency of 12 MHz or 16 MHz

16.3 Hardware and Software Constraints

 SAM-BA Boot uses the first 2048 bytes of the SRAM for variables and stacks. The remaining available bytes can be used for user code.  USB Requirements ̶ External crystal or external clock(1) with frequency of 12 MHz or 16 MHz  UART0 requirements: None. If no accurate external clock source is available, the internal 12 MHz RC meets RS232 standards. Note: 1. Must be 2500 ppm and 1.8V square wave signal. Table 16-1. Pins Driven during Boot Program Execution Peripheral Pin PIO Line UART0 URXD0 PA9 UART0 UTXD0 PA10

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

16.4 Flow Diagram

The boot program implements the algorithm in Figure 16-1. Figure 16-1. Boot Program Algorithm Flow Diagram The SAM-BA boot program looks for a source clock, either from the embedded main oscillator with external crystal (main oscillator enabled) or from a supported frequency signal applied to the XIN pin (Main oscillator in bypass mode). If a clock is supplied by one of the two sources, the boot program checks that the frequency is one of the supported external frequencies. If the frequency is supported, USB activation is allowed. If no clock is supplied, or if a clock is supplied but the frequency is not a su pported external frequency, the internal 12 MHz RC oscillator is used as the main clock. In this ca se, the USB is not activated due to the frequency drift of the 12 MHz RC oscillator.

16.5 Device Initialization

Initialization by the boot program follows the steps described below: 1. Stack setup. 2. Embedded Flash Controller setup. 3. External clock (crystal or external clock on XIN) detection. 4. External crystal or clock with supported frequency supplied. 1. If yes, USB activation is allowed. 2. If no, USB activation is not allowed. The internal 12 MHz RC oscillator is used. 5. Master clock switch to main oscillator. 6. C variable initialization. 7. PLLA setup: PLLA is initializ ed to generate a 48 MHz clock. 8. Watchdog disable. 9. Initialization of UART0 (115200 bauds, 8, N, 1). 10. Initialization of the USB Device Port (only if USB activation is allowed—see Step 4.). 11. Wait for one of the following events: 1. Check if USB device enumeration has occurred. 2. Check if characters have been received in UART0. 12. Jump to SAM-BA Monitor (see Section 16.6 ”SAM-BA Monitor”) Device Setup Character # received from UART0? Run SAM-BA Monitor USB Enumeration Successful ? Yes Run SAM-BA Monitor Yes No No

85SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

16.6 SAM-BA Monitor

Once the communication interface is identified, the monitor runs in an infinite loop, waiting for different commands as shown in Table 16-2.  Mode commands: ̶ Normal mode configures SAM-BA Monitor to send/receive data in binary format ̶ Terminal mode configures SAM-BA Monitor to send/receive data in ASCII format  Write commands: Write a byte (O), a halfword (H) or a word (W) to the target ̶ Address: Address in hexadecimal ̶ Value: Byte, halfword or word to write in hexadecimal  Read commands: Read a byte (o), a halfword (h) or a word (w) from the target ̶ Address: Address in hexadecimal ̶ Output: The byte, halfword or word read in hexadecimal  Send a file (S): Send a file to a specified address ̶ Address: Address in hexadecimal Note: There is a time-out on this command which is reached when the prompt ‘>’ appears before the end of the command execution.  Receive a file (R): Receive data into a file from a specified address ̶ Address: Address in hexadecimal ̶ NbOfBytes: Number of bytes in hexadecimal to receive  Go (G): Jump to a specified address and execute the code ̶ Address: Address to jump in hexadecimal  Get Version (V): Return the SAM-BA boot version Note: In Terminal mode, when the requested command is perfo rmed, SAM-BA Monitor adds the following prompt sequence to its answer: <LF>+<CR>+'>'. Table 16-2. Commands Available through the SAM-BA Boot Command Action Argument(s) Example N Set Normal mode No argument N# T Set Terminal mode No argument T# O Write a byte Address, Value# O200001,CA# o Read a byte Address,# o200001,# H Write a half word Address, Value# H200002,CAFE# h Read a half word Address,# h200002,# W Write a word Address, Value# W200000,CAFEDECA# w Read a word Address,# w200000,# S Send a file Address,# S200000,# R Receive a file Address, NbOfBytes# R200000,1234# G Go Address# G200200# V Display version No argument V#

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

16.6.1 UART0 Serial Port

Communication is performed through the UART0 initialized to 115200 Baud, 8, n, 1. The Send and Receive File commands use the Xmodem protocol to communicate. Any terminal performing this protocol can be used to send the application file to the target. The size of the binary file to send depends on the SRAM size embedded in the product. In all cases, the size of the binary file must be smaller than the SRAM size because the Xmodem protocol requires some SRAM memory to work. See Section 16.3 ”Hardware and Software Constraints”

16.6.2 Xmodem Protocol

The Xmodem protocol supported is the 128-byte length block. This protocol uses a two-character CRC-16 to guarantee detection of a maximum bit error. The Xmodem protocol with CRC is accu rate if both sender and receiver report successful transmission. Each block of the transfer has the following format: <SOH><blk #><255-blk #><--128 data bytes--><checksum> in which: ̶ <SOH> = 01 hex ̶ <blk #> = binary number, starts at 01, increments by 1, and wraps 0FFH to 00H (not to 01) ̶ <255-blk #> = 1’s complement of the blk#. ̶ <checksum> = 2 bytes CRC16 Figure 16-2 shows a transmission using this protocol. Figure 16-2. Xmodem Transfer Example Host Device SOH 01 FE Data[128] CRC CRC C ACK SOH 02 FD Data[128] CRC CRC ACK SOH 03 FC Data[100] CRC CRC ACK EOT ACK

87SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

16.6.3 USB Device Port

The device uses the USB communication device class (CDC) drivers to take advantage of the installed PC RS-232 software to talk over the US B. The CDC class is implement ed in all releas es of Windows ®, beginning with Windows 98SE. The CDC document, available at www.usb.org, describes a way to implement devices such as ISDN modems and virtual COM ports. The Vendor ID (VID) is the Atmel vendor ID 0x03EB. The product ID (PID) is 0x6124. These references are used by the host operating system to mount the correct dr iver. On Windows systems, the INF files contain the correspondence between vendor ID and product ID. For more details on VID/PID for end product/systems, refer to the Vendor ID form available from the USB Implementers Forum found at http://www.usb.org/.

16.6.3.1 Enumeration Process

The USB protocol is a master/slave pr otocol. This is the host t hat starts the enumeration sending requests to the device through the control endpoint. The device handles standard requests as defined in the USB Specification. The device also handles some class requests defined in the CDC class. . Unhandled requests are STALLed.

16.6.3.2 Communication Endpoints

There are two communication endpoints. Endpoint 0 is used for the enumeration process. Endpoint 1 is a 64-byte Bulk OUT endpoint. Endpoint 2 is a 64- byte Bulk IN endpoint. SAM-BA Boot commands are sent by the host through endpoint 1. If required, the message is split by the host into several data payloads by the host driver. If the command requires a response, the host can send IN transactions to pick up the response. WARNING Unauthorized use of assigned or unassigned USB Vendor ID Numbers and associated Product ID Numbers is strictly prohibited. Table 16-3. Handled Standard Requests Request Definition GET_DESCRIPTOR Returns the current device configuration value. SET_ADDRESS Sets the device address for all future device access. SET_CONFIGURATION Sets the device configuration. GET_CONFIGURATION Returns the current device configuration value. GET_STATUS Returns status fo r the specified recipient. SET_FEATURE Set or Enable a specific feature. CLEAR_FEATURE Clear or Disable a specific feature. Table 16-4. Handled Class Requests Request Definition SET_LINE_CODING Configures DTE rate, stop bits, parity and number of character bits. GET_LINE_CODING Requests current DTE rate, stop bits, parity and number of character bits. SET_CONTROL_LINE_STATE RS-232 signal used to tell the DCE device the DTE device is now present.

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

16.6.4 In Application Programming (IAP) Feature

The IAP feature is a function located in ROM that can be called by any software application. When called, this function sends the desired FLASH co mmand to the EEFC and waits for the Flash to be ready (looping while the FRDY bit is not set in the MC_FSR register). Since this function is executed from ROM, this allows Flash programming (such as sector write) to be done by code running in Flash. The IAP function entry point is retrieved by reading the NMI vector in ROM (0x00800008). This function takes two arguments as parameters:  the index of the Flash bank to be programmed: 0 for EEFC0, 1 for EEFC1. For devices with only one bank, this parameter has no effect and can be either 0 or 1, only EEFC0 will be accessed.  the command to be sent to the EEFC Command register. This function returns the value of the EEFC_FSR register. An example of IAP software code follows: // Example: How to write data in page 200 of the flash memory using ROM IAP function flash_page_num = 200 flash_cmd = 0 flash_status = 0 eefc_index = 0 (0 for EEFC0, 1 for EEFC1) // Initialize the function pointer (retrieve function address from NMI vector)*/ iap_function_address = 0x00800008 // Fill the flash page buffer at address 200 with the data to be written for i=0, i < page_size, i++ do flash_sector_200_address[i] = your_data[i] // Prepare the command to be sent to the EEFC Command register: key, page number and write command flash_cmd = (0x5A << 24) | (flash_page_num << 8) | flash_write_command; // Call the IAP function with the right parameters and retrieve the status in flash_status after completion flash_status = iap_function (eefc_index, flash_cmd);

89SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 17. Fast Flash Programming Interface (FFPI)

17.1 Description

The Fast Flash Programming Interface (FFPI) provides parallel high-volume programming using a standard gang programmer. The parallel interface is fully handshaked and the device is considered to be a standard EEPROM. Additionally, the parallel protocol offers an optimized access to all the embedded Flash functionalities. Although the Fast Flash Programming mode is a dedicated mode for high volu me programming, this mode is not designed for in-situ programming.

17.2 Embedded Characteristics

 Programming Mode for High-volume Flash Programming Using Gang Programmer ̶ Offers Read and Write Access to the Flash Memory Plane ̶ Enables Control of Lock Bits and General-purpose NVM Bits ̶ Enables Security Bit Activation ̶ Disabled Once Security Bit is Set  Parallel Fast Flash Programming Interface ̶ Provides an 16-bit Parallel Interface to Program the Embedded Flash ̶ Full Handshake Protocol

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

17.3 Parallel Fast Flash Programming

17.3.1 Device Configuration

In Fast Flash Programming mode, the device is in a specific test mode. Only a certain set of pins is significant. The rest of the PIOs are used as inputs with a pull-up. The crystal osc illator is in bypass mode. Other pins must be left unconnected. Figure 17-1. 16-bit Parallel Programming Interface NCMD PGMNCMD RDY PGMRDY NOE PGMNOE NVALID PGMNVALID MODE[3:0] PGMM[3:0] DATA[15:0] PGMD[15:0] XIN TSTVDDIO PGMEN0 PGMEN1 External Clock VDDIO VDDCORE VDDIO VDDPLL GND VDDIO Table 17-1. Signal Description List Signal Name Function Type Active Level Comments Power VDDIO I/O Lines Power Supply Power – – VDDCORE Core Power Supply Power – – VDDPLL PLL Power Supply Power – – GND Ground Ground – – Clocks XIN Main Clock Input Input – – Test TST Test Mode Select Input High Must be connected to VDDIO PGMEN0 Test Mode Select Input High Must be connected to VDDIO PGMEN1 Test Mode Select Input High Must be connected to VDDIO PIO PGMNCMD Valid command available Input Low Pulled-up input at reset PGMRDY 0: Device is busy 1: Device is ready for a new command Output High Pulled-up input at reset PGMNOE Output Enable (active high) Input Low Pulled-up input at reset

91SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

17.3.2 Signal Names

Depending on the MODE settings, DATA is latched in different internal registers. When MODE is equal to CMDE, then a new command (strobe d on DATA[15:0] signals) is stored in the command register. PGMNVALID 0: DATA[15:0] is in input mode 1: DATA[15:0] is in output mode Output Low Pulled-up input at reset PGMM[3:0] Specifies DATA type (see Table 17-2) Input – Pulled-up input at reset PGMD[15:0] Bi-directional data bus Input/Output – Pulled-up input at reset Table 17-1. Signal Description List (Continued) Signal Name Function Type Active Level Comments Table 17-2. Mode Coding MODE[3:0] Symbol Data

0000 CMDE Command Register

0001 ADDR0 Address Register LSBs

0010 ADDR1 –

0011 ADDR2 –

0100 ADDR3 Address Register MSBs

0101 DATA Data Register

Table 17-3. Command Bit Coding DATA[15:0] Symbol Command Executed 0x0011 READ Read Flash 0x0012 WP Write Page Flash 0x0022 WPL Write Page and Lock Flash 0x0032 EWP Erase Page and Write Page 0x0042 EWPL Erase Page and Write Page then Lock 0x0013 EA Erase All 0x0014 SLB Set Lock Bit 0x0024 CLB Clear Lock Bit 0x0015 GLB Get Lock Bit 0x0034 SGPB Set General Purpose NVM bit 0x0044 CGPB Clear General Purpose NVM bit 0x0025 GGPB Get General Purpose NVM bit 0x0054 SSE Set Security Bit 0x0035 GSE Get Security Bit 0x001F WRAM Write Memory 0x001E GVE Get Version

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

17.3.3 Entering Parallel Programming Mode

The following algorithm puts the device in Parallel Programming mode: 1. Apply the supplies as described in Table 17-1. 2. If an external clock is available, apply it to XIN within the VDDCORE POR reset time-out period, as defined in the section “Electrical Characteristics”. 3. Wait for the end of this reset period. 4. Start a read or write handshaking.

17.3.4 Programmer Handshaking

A handshake is defined for read and write operations. When the device is ready to start a new operation (RDY signal set), the programmer starts the handshake by clearing the NCMD signal. The handshaking is completed once the NCMD signal is high and RDY is high.

17.3.4.1 Write Handshaking

For details on the write handshaking sequence, refer to Figure 17-2 and Table 17-4. Figure 17-2. Parallel Programming Timing, Write Sequence NCMD RDY NOE NVALID DATA[15:0] MODE[3:0] Table 17-4. Write Handshake Step Programmer Action Device Action Data I/O

1 Sets MODE and DATA signals Waits for NCMD low Input

2 Clears NCMD signal Latch es MODE and DATA Input

3 Waits for RDY low Clears RDY signal Input

4 Releases MODE and DATA signals Executes command and polls NCMD high Input

5 Sets NCMD signal Executes command and polls NCMD high Input

6 Waits for RDY high Sets RDY Input

93SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

17.3.4.2 Read Handshaking

For details on the read handshaking sequence, refer to Figure 17-3 and Table 17-5. Figure 17-3. Parallel Programming Timing, Read Sequence

17.3.5 Device Operations

Several commands on the Flash memory are available. These commands are summarized in Table 17-3. Each command is driven by the programmer through the paral lel interface running several read/write handshaking sequences. When a new command is executed, the previous one is automatically achieved. Thus, chaining a read command after a write automatically flushes the load buffer in the Flash. NCMD RDY NOE NVALID DATA[15:0] MODE[3:0] ADDR Adress IN Z Data OUT XI N Table 17-5. Read Handshake Step Programmer Action Device Action DATA I/O

2 Clears NCMD signal Latch MODE and DATA Input

4 Sets DATA signal in tristate Waits for NOE Low Input

5 Clears NOE signal – Tristate

6 Waits for NVALID low Sets DATA bus in output mode and outputs

the flash contents. Output 7 – Clears NVALID signal Output

8 Reads value on DATA Bus Waits for NOE high Output

9 Sets NOE signal – Output

10 Waits for NVALID high Sets DATA bus in input mode X

11 Sets DATA in output mode Sets NVALID signal Input

12 Sets NCMD signal Waits for NCMD high Input

13 Waits for RDY high Sets RDY signal Input

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

17.3.5.1 Flash Read Command

This command is used to read the contents of the Flash memory. The read command can start at any valid address in the memory plane and is optimized for cons ecutive reads. Read handshaki ng can be chained; an internal address buffer is automatically increased.

17.3.5.2 Flash Write Command

This command is used to write the Flash contents. The Flash memory plane is organized into several pages. Data to be written are stored in a load buffer that corresponds to a Flash memory page. The load buffer is automatically flushed to the Flash:  before access to any page other than the current one  when a new command is validated (MODE = CMDE) The Write Page command (WP) is optimized for consecutive writes. Write handshak ing can be chained; an internal address buffer is automatically increased. Table 17-6. Read Command Step Handshake Sequence MODE[3:0] DATA[15:0]

1 Write handshaking CMDE READ

2 Write handshaking ADDR0 Memory Address LSB

3 Write handshaking ADDR1 Memory Address

4 Read handshaking DATA *Memory Address++

5 Read handshaking DATA *Memory Address++

n Write handshaking ADDR0 Memory Address LSB n+1 Write handshaking ADDR1 Memory Address n+2 Read handshaking DATA *Memory Address++ n+3 Read handshaking DATA *Memory Address++ Table 17-7. Write Command Step Handshake Sequence MODE[3:0] DATA[15:0]

1 Write handshaking CMDE WP or WPL or EWP or EWPL

4 Write handshaking DATA *Memory Address++

5 Write handshaking DATA *Memory Address++

n Write handshaking ADDR0 Memory Address LSB n+1 Write handshaking ADDR1 Memory Address n+2 Write handshaking DATA *Memory Address++ n+3 Write handshaking DATA *Memory Address++

95SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 The Flash command Write Page and Lock (WPL) is equivalent to the Flash Wr ite Command. However, the lock bit is automatically set at the end of the Flash write operation. As a lock region is composed of several pages, the programmer writes to the first pages of the lock region using Flash write commands and writes to the last page of the lock region using a Flash write and lock command. The Flash command Erase Page and Write (EWP) is equivalent to the Flash Write Command. However, before programming the load buffer, the page is erased. The Flash command Erase Page and Write the Lock (EWPL) combines EWP and WPL commands.

17.3.5.3 Flash Full Erase Command

This command is used to erase the Flash memory planes. All lock regions must be unlocked before the Full Erase command by using the CLB command. Otherwise, the erase command is aborted and no page is erased.

17.3.5.4 Flash Lock Commands

Lock bits can be set using WPL or EWPL commands. They can also be set by using the Set Lock command (SLB) . With this command, several lock bits can be activated. A Bit Mask is provided as argument to the command. When bit 0 of the bit mask is set, then the first lock bit is activated. In the same way, the Clear Lock command (CLB) is used to clear lock bits. Lock bits can be read using Get Lock Bit command (GLB). The nth lock bit is active when the bit n of the bit mask is set. Table 17-8. Full Erase Command Step Handshake Sequence MODE[3:0] DATA[15:0]

1 Write handshaking CMDE EA

2 Write handshaking DATA 0

Table 17-9. Set and Clear Lock Bit Command Step Handshake Sequence MODE[3:0] DATA[15:0]

1 Write handshaking CMDE SLB or CLB

2 Write handshaking DATA Bit Mask

Table 17-10. Get Lock Bit Command Step Handshake Sequence MODE[3:0] DATA[15:0]

1 Write handshaking CMDE GLB

2 Read handshaking DATA

0 = Lock bit is cleared 1 = Lock bit is set

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

17.3.5.5 Flash General- purpose NVM Commands

General-purpose NVM bits (GP NV M bits) can be set using the Set GPNVM command (SGPB) . This command also activates GP NVM bits. A bit mask is provided as argument to the command. When bit 0 of the bit mask is set, then the first GP NVM bit is activated. In the same way, the Clear GPNVM command (CGPB) is used to clear general-purpose NVM bits. The general- purpose NVM bit is deactivated when the corresponding bit in the pattern value is set to 1. General-purpose NVM bits can be read using the Get GPNVM Bit command (GGPB). The n th GP NVM bit is active when bit n of the bit mask is set.

17.3.5.6 Flash Security Bit Command

A security bit can be set using the Set Security Bit command (SSE). Once the security bit is active, the Fast Flash programming is disabled. No other command can be run. An event on the Erase pin can erase the security bit once the contents of the Flash have been erased. Once the security bit is set, it is not possible to access FFP I. The only way to erase the security bit is to erase the Flash. To erase the Flash, perform the following steps: 1. Power-off the chip. 2. Power-on the chip with TST = 0. 3. Assert the ERASE pin for at least the ERASE pin assertion time as defined in the section “Electrical Characteristics”. 4. Power-off the chip. Return to FFPI mode to check that the Flash is erased. Table 17-11. Set/Clear GP NVM Command Step Handshake Sequence MODE[3:0] DATA[15:0]

1 Write handshaking CMDE SGPB or CGPB

2 Write handshaking DATA GP NVM bit pattern value

Table 17-12. Get GP NVM Bit Command Step Handshake Sequence MODE[3:0] DATA[15:0]

1 Write handshaking CMDE GGPB

0 = GP NVM bit is cleared 1 = GP NVM bit is set Table 17-13. Set Security Bit Command Step Handshake Sequence MODE[3:0] DATA[15:0]

1 Write handshaking CMDE SSE

97SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

17.3.5.7 Memory Write Command

This command is used to perform a write access to any memory location. The Memory Write command (WRAM) is optimized for consecutive writes. Write handshaking can be chained; an internal address buffer is automatically increased.

17.3.5.8 Get Version Command

The Get Version (GVE) command retrieves the version of the FFPI interface. Table 17-14. Write Command Step Handshake Sequence MODE[3:0] DATA[15:0]

1 Write handshaking CMDE WRAM

n Write handshaking ADDR0 Memory Address LSB n+1 Write handshaking ADDR1 Memory Address n+2 Write handshaking DATA *Memory Address++ n+3 Write handshaking DATA *Memory Address++ Table 17-15. Get Version Command Step Handshake Sequence MODE[3:0] DATA[15:0]

1 Write handshaking CMDE GVE

2 Read handshaking DATA Version

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 18. Bus Matrix (MATRIX)

18.1 Description

The Bus Matrix (MATRIX) implements a multi-layer AHB, based on the AHB-Lite protocol, that enables parallel access paths between multiple AHB masters and slaves in a system, thus increasing the overall bandwidth. The Bus Matrix interconnects 12 AHB masters to 9 AHB slaves. The normal latency to connect a master to a slave is one cycle. The exception is the default master of the accessed slave which is connected directly (zero cycle latency). The Bus Matrix user interface is compliant with ARM Advanced Peripheral Bus.

18.2 Embedded Characteristics

 12 Masters  9 Slaves  One Decoder for Each Master  Several Possible Boot Memories for Each Master before Remap  One Remap Function for Each Master  Support for Long Bursts of 32, 64, 128 and up to the 256-beat Word Burst AHB Limit  Enhanced Programmable Mixed Arbitration for Each Slave ̶ Round-Robin ̶ Fixed Priority  Programmable Default Master for Each Slave ̶ No Default Master ̶ Last Accessed Default Master ̶ Fixed Default Master  Deterministic Maximum Access Latency for Masters  Zero or One Cycle Arbitration Latency for the First Access of a Burst  Bus Lock Forwarding to Slaves  Master Number Forwarding to Slaves  One Special Function Register for Each Slave (not dedicated)  Register Write Protection

99SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

18.2.1 Matrix Masters

The Bus Matrix manages the masters listed in Table 18-1 . Each master can perform an access to an available slave concurrently with other masters. lists the available masters. Each master has its own specifically-defined decoder. To simplify addressing, all the masters have the same decodings.

18.2.2 Matrix Slaves

The Bus Matrix manages the slaves listed in Table 18-2. Each slave has its own arbiter, providing a different arbitration per slave. Table 18-1. Bus Matrix Masters Master Index Name 0C o r t e x - M 7 1C o r t e x - M 7

2 Cortex-M7 Peripheral Port

3 Integrated Check Monitor

4, 5 XDMAC 6I S I D M A

7 Reserved

9 Ethernet MAC DMA

10 CAN0 DMA

11 CAN1 DMA

Table 18-2. Bus Matrix Slaves Slave Index Name

0 Internal SRAM

1 Internal SRAM

2 Internal ROM

3 Internal Flash

4 USB High Speed Dual Port RAM (DPR)

5 External Bus Interface

6 QSPI

7 Peripheral Bridge

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 100

18.2.3 Master to Slave Access

Table 18-3 provides valid paths for master to slave accesses. The paths shown as “-” are forbidden or not wired. Note: 1. The connection of the Cortex-M7 processor to the SRAM is defined in the sections “Interconnect” and “Memories”, sub- section “Embedded Memories”, of this datasheet. Table 18-3. Master to Slave Access M a s t e r s 0123456789 1 0 1 1 Slaves Cortex- Cortex- Cortex- Periph. Port ICM Central DMA IF0 Central DMA IF1 ISI DMA Reserved USB DMA GMAC DMA CAN0 DMA CAN1 DMA

1 Internal SRAM – – – – – X X – X X X X

3 Internal Flash X – – X – X – – X X – –

Interface –X–XXXX–XXXX

7 P e r i p h e r a l B r i d g e –XX––X––––––

(AHBS)(1)

101SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

18.3 Functional Description

18.3.1 Memory Mapping

The Bus Matrix provides one decoder for every AHB master interface. The decoder offers each AHB master several memory mappings. Each memory area may be assigned to several slaves. Thus booting at the same address while using different AHB slaves (i.e., external RAM, internal ROM or internal Flash, etc.) is possible. The Bus Matrix user interface provides the Master Remap Control Register (MATRIX_MRCR) that performs remap action for every master independently.

18.3.2 Special Bus Granting Mechanism

The Bus Matrix provides some speculative bus granting te chniques in order to anticipate access requests from masters. This technique reduces latency at the first access of a burst, or for a single transfer, as long as the slave is free from any other master access. Bus granting sets a different default master for every slave. At the end of the current access, if no other request is pending, the slave remains connected to its associated default master. A slave can be associated with three kinds of default masters:  No default master  Last access master  Fixed default master To change from one type of default master to another, t he Bus Matrix user interf ace provides the Slave Configuration registers, one for every slave, that set a default master for each slave. The Slave Configuration register contains the fields DEFMSTR_TYPE and FIXED_DEFMSTR. The 2-bit DEFMSTR_TYPE field selects the default master type (no default, last access master, fixed default master), whereas the 4-bit FIXED_DEFMSTR field selects a fixed default master provided that DEFMSTR_TYPE is set to fixed default master. Refer to Section 18.4.2 ”Bus Matrix Slave Configuration Registers”.

18.3.2.1 No Default Master

After the end of the current access, if no other request is pending, the slave is disconnected from all masters. This configuration incurs one latency cl ock cycle for the first access of a bur st after bus Idle. Arbitration without default master may be used for masters that perform significant bursts or several transfers with no Idle in between, or if the slave bus bandwidth is widely used by one or more masters. This configuration provides no bene fit on access latency or bandwidth when reaching maximum slave bus throughput whatever the number of requesting masters.

18.3.2.2 Last Access Master

After the end of the current access, if no other request is pending, the slav e remains connected to the last master that performed an access request. This allows the Bus Matrix to remove the one latency cycle for the last master that accessed the slave. Other non privileged masters still get one latency clock cycl e if they want to access the same slave. This technique is useful for masters that mainly perform single accesses or short bursts with some Idle cycles in between. This configuration provides no bene fit on access latency or bandwidth when reaching maximum slave bus throughput whatever is the number of requesting masters.

18.3.2.3 Fixed Default Master

At the end of the current access, if no other request is pending, the slave connects to its fixed default master. Unlike the last access master, the fixed default master does not change unless the user modifies it by software (FIXED_DEFMSTR field of the related MATRIX_SCFG). This allows the Bus Matrix arbiters to remove the one la tency clock cycle for the fixed default master of the slave. All requests attempted by the fixed default master do not cause any arbitration latency, whereas other non-

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 102 privileged masters will get one latency cy cle. This technique is useful for a master that mainly performs single accesses or short bursts with Idle cycles in between. This configuration provides no bene fit on access latency or bandwidth when reaching maximum slave bus throughput, regardless of the number of requesting masters.

18.3.3 Arbitration

The Bus Matrix provides an arbitration technique that reduces latency when conflicting cases occur; for example. when two or more masters try to access the same slave at the same time. One arbiter per AHB slave is provided, so that each slave is arbitrated differently. The Bus Matrix provides the user with two arbitration types for each slave: 1. Round-robin Arbitr ation (default) 2. Fixed Priority Arbitration Each algorithm may be complemented by selecting a default master configuration for each slave.

18.3.3.1 Arbitration Rules

Each arbiter has the ability to arbitrate between requests from two or more masters. To avoid burst breaking and to provide maximum throughput for slave interfaces, arbitration should take place during the following cycles: 1. Idle cycle s: When a slave is not connected to any master or is connected to a master which is not cur- rently accessing it. 2. Single cycles: When a slave is performing a single access. 3. End of Burst cycles: When the current cycle is the last cycle of a burst transfer. For a defined length burst, predicted end of burst matches the size of the transfer but is managed differently for undefined length burst. See Section ”Undefined Length Burst Arbitration” 4. Slot cycle limit: When the slot cycle counter has reached the limit value indicating that the current master access is too long and must be broken. See Section ”Slot Cycle Limit Arbitration” Undefined Length Burst Arbitration In order to prevent slave handling during undefined length bursts, the user can trigger the re-arbitration before the end of the incremental bursts. The re-arbitration period can be selected from the following Undefined Length Burst Type (ULBT) possibilities: 1. Unlimited: no predetermined end of bur st is generated. This value enables 1-Kbyte burst lengths. 2. 1-beat bursts: predetermin ed end of burst is generated at each single transfer during the INCR transfer. 3. 4-beat bursts: predetermined end of burst is generated at the end of each 4-beat boundary during INCR transfer. 4. 8-beat bursts: predetermined end of burst is generated at the end of each 8-beat boundary during INCR transfer. 5. 16-beat bursts: predetermined end of burst is generat ed at the end of each 16-beat boundary during INCR transfer. 6. 32-beat bursts: predetermined end of burst is generat ed at the end of each 32-beat boundary during INCR transfer. 7. 64-beat bursts: predetermined end of burst is generat ed at the end of each 64-beat boundary during INCR transfer. 8. 128-beat bursts: predetermined end of burst is generated at the end of each 128 -beat boundary during INCR transfer. The use of undefined length16-beat bursts, or less, is discouraged since this decreases the overall bus bandwidth due to arbitration and slave latencies at each first access of a burst.

103SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 If the master does not permanently and continuously request the same slave or has an intrinsically limited average throughput, the ULBT should be left at its default unlimited value, knowing that the AHB specification natively limits all word bursts to 256 beats and double-word bursts to 128 beats because of its 1-Kbyte address boundaries. Unless duly needed, the ULBT should be left at its default value of 0 for power saving. This selection is made through the ULBT field of the Master Configuration Registers (MATRIX_MCFG). Slot Cycle Limit Arbitration The Bus Matrix contains specific logic to break long accesses, such as very long bursts on a very slow slave (e.g., an external low speed memory). At each arbitration time, a counter is loaded with the value previously written in the SLOT_CYCLE field of the related Slave Configuration Register (MATRIX_SCFG) and decreased at each clock cycle. When the counter elapses, the arbiter has the ability to re-arbitrate at the end of the current AHB bus access cycle. Unless a master has a very tight access latency constraint, which could lead to data overflow or underflow due to a badly undersized internal FIFO with respect to its throughput, the Slot Cycle Limit should be disabled (SLOT_CYCLE = 0) or set to its default maximum value in order not to inefficiently break long bursts performed by some Atmel masters. In most cases, this feature is not needed and should be disabled for power saving. WARNING: This feature does not prevent a slave from locking its access indefinitely.

18.3.3.2 Arbitration Priority Scheme

The Bus Matrix arbitration scheme is organized in priority pools. Round-robin priority is used in the highest and lowest pr iority pools, whereas fixed level priority is used between priority pools and in the intermediate priority pools. For each slave, each master is assigned to one of the slave priority pools through the priority registers for slaves (MxPR fields of MATRIX_PRAS and MATRIX_PRBS). When evaluating master requests, this programmed priority level always takes precedence. After reset, all the masters except those of the Cortex-M7 belong to the lowest priority pool (MxPR = 0) and are therefore granted bus access in a true round-robin order. The highest priority pool must be spec ifically reserved for masters requiring very low access latency. If more than one master belongs to this pool, they will be granted bus access in a biased round-robin manner which allows tight and deterministic maximum access lat ency from AHB bus requests. In the worst case, any currently occurring high-priority master request will be granted after the current bus mast er access has ended and other high priority pool master requests, if any, have been granted once each. The lowest priority pool shares the remaining bus bandwidth between AHB Masters. Intermediate priority pools allow fine priority tuning. Typi cally, a moderately latency-critical master or a bandwidth- only critical master will use su ch a priority level. The higher the priority level (MxPR value), the higher the master priority. All combinations of MxPR values are allowed for all masters and slaves. For example, some masters might be assigned the highest priority pool (round-robin), and rema ining masters the lowest priority pool (round-robin), with no master for intermediate fix priority levels. If more than one master r equests the slave bus, re gardless of the respective mast ers priorities, no master will be granted the slave bus for two consecutive runs. A master can only get back-to-back grants so long as it is the only requesting master. Fixed Priority Arbitration The fixed priority arbitration algorithm is the first an d only arbitration algorithm applied between masters from distinct priority pools. It is also us ed in priority pools other than the highest and lowest priority pools (intermediate priority pools).

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 104 Fixed priority arbitration is used by the Bus Matrix arbite rs to dispatch the requests from different masters to the same slave by using the fixed priority defined by the user. If requests from two or more masters are active at the same time, the master with the highest pr iority number is serviced first. If requests from two or more masters with the same priority are active at the same time, the master with the highest number is serviced first. For each slave, the priority of each master is defined in the MxPR field in the Priority Registers, MATRIX_PRAS and MATRIX_PRBS. Round-Robin Arbitration Round-robin arbitration is only used in the highest and lowest priority pools. It allows the Bus Matrix arbiters to properly dispatch requests from different masters to the same slave. If two or more master requests are active at the same time in the priority pool, they are serviced in a round-robin increasing master number order.

18.3.4 System I/O Configuration

The System I/O Configuration register (CCFG_SYSIO) configures I/O lines in Syst em I/O mode (such as JTAG, ERASE, USB, etc.) or as general purpose I/O lines. Enabling or disabling the corresponding I/O lines in peripheral mode or in PIO mode (PIO_PER or PIO_PDR registers) in the PIO controller as no effect. However, the direction (input or output), pull-up, pull-down and other mode control is still managed by the PIO controller.

18.3.5 SMC NAND Flash Chip Select Configuration

The SMC Nand Flash Chip Select Configuration Register (CCFG_SMCNFCS) manages the chip select signal (NCSx) and its assignment to NAND Flash. Each NCSx may or may not be individually assigned to NAND Flash. When the NCSx is assigned to NAND Flash, the signals NANDOE and NANDWE are used for the NCSx signals selected.

105SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

18.3.6 Register Write Protection

To prevent any single software error from corrupting MATRIX behavior, certain registers in the address space can be write-protected by setting the WPEN bit in the Write Protection Mode Register (MATRIX_WPMR). If a write access to a write-protected r egister is detected, the WPVS flag in the Write Protection Status Register (MATRIX_WPSR) is set and the field WPVSRC indicates the register in which th e write access has been attempted. The WPVS flag is reset by writing the Bus Matrix Write Protect Mode Register (MATRIX_WPMR) with the appropriate access key WPKEY. The following registers can be write-protected:  Bus Matrix Master Configuration Registers  Bus Matrix Slave Configuration Registers  Bus Matrix Priority Registers A For Slaves  Bus Matrix Priority Registers B For Slaves  Bus Matrix Master Remap Control Register

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 106

18.4 Bus Matrix (MATRI X) User Interface

Table 18-4. Register Mapping Offset Register Name Access Reset 0x0000 Master Configuration Register 0 MATRIX_MCFG0 Read/Write 0x00000001 0x0004 Master Configuration Register 1 MATRIX_MCFG1 Read/Write 0x00000000 0x0008 Master Configuration Register 2 MATRIX_MCFG2 Read/Write 0x00000000 0x000C Master Configuration Register 3 MATRIX_MCFG3 Read/Write 0x00000000 0x0010 Master Configuration Register 4 MATRIX_MCFG4 Read/Write 0x00000000 0x0014 Master Configuration Register 5 MATRIX_MCFG5 Read/Write 0x00000000 0x0018 Master Configuration Register 6 MATRIX_MCFG6 Read/Write 0x00000000 0x001C Reserved – – – 0x0020 Master Configuration Register 8 MATRIX_MCFG8 Read/Write 0x00000000 0x0024 Master Configuration Register 9 MATRIX_MCFG9 Read/Write 0x00000000 0x0028 Master Configuration Register 10 MATRIX_MCFG10 Read/Write 0x00000000 0x002C Master Configuration Register 11 MATRIX_MCFG11 Read/Write 0x00000000 0x0030–0x003C Reserved – – – 0x0040 Slave Configuration Register 0 MATRIX_SCFG0 Read/Write 0x000001FF 0x0044 Slave Configuration Register 1 MATRIX_SCFG1 Read/Write 0x000001FF 0x0048 Slave Configuration Register 2 MATRIX_SCFG2 Read/Write 0x000001FF 0x004C Slave Configuration Register 3 MATRIX_SCFG3 Read/Write 0x000001FF 0x0050 Slave Configuration Register 4 MATRIX_SCFG4 Read/Write 0x000001FF 0x0054 Slave Configuration Register 5 MATRIX_SCFG5 Read/Write 0x000001FF 0x0058 Slave Configuration Register 6 MATRIX_SCFG6 Read/Write 0x000001FF 0x005C Slave Configuration Register 7 MATRIX_SCFG7 Read/Write 0x000001FF 0x0060 Slave Configuration Register 8 MATRIX_SCFG8 Read/Write 0x000001FF 0x0064–0x007C Reserved – – – 0x0080 Priority Register A for Slave 0 MATRIX_PRAS0 Read/Write 0x00000222 (1) 0x0084 Priority Register B for Slave 0 MATRIX_PRBS0 Read/Write 0x00000000 (1) 0x0088 Priority Register A for Slave 1 MATRIX_PRAS1 Read/Write 0x00000222 (1) 0x008C Priority Register B for Slave 1 MATRIX_PRBS1 Read/Write 0x00000000 (1) 0x0090 Priority Register A for Slave 2 MATRIX_PRAS2 Read/Write 0x00000222 (1) 0x0094 Priority Register B for Slave 2 MATRIX_PRBS2 Read/Write 0x00000000 (1) 0x0098 Priority Register A for Slave 3 MATRIX_PRAS3 Read/Write 0x00000222 (1) 0x009C Priority Register B for Slave 3 MATRIX_PRBS3 Read/Write 0x00000000 (1) 0x00A0 Priority Register A for Slave 4 MATRIX_PRAS4 Read/Write 0x00000222 (1) 0x00A4 Priority Register B for Slave 4 MATRIX_PRBS4 Read/Write 0x00000000 (1) 0x00A8 Priority Register A for Slave 5 MATRIX_PRAS5 Read/Write 0x00000222 (1) 0x00AC Priority Register B for Slave 5 MATRIX_PRBS5 Read/Write 0x00000000 (1)

107SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 Notes: 1. Values in the Bus Matrix Priority Registers are product-dependent. 0x00B0 Priority Register A for Slave 6 MATRIX_PRAS6 Read/Write 0x00000222 (1) 0x00B4 Priority Register B for Slave 6 MATRIX_PRBS6 Read/Write 0x00000000 (1) 0x00B8 Priority Register A for Slave 7 MATRIX_PRAS7 Read/Write 0x00000222 (1) 0x00BC Priority Register B for Slave 7 MATRIX_PRBS7 Read/Write 0x00000000 (1) 0x00C0 Priority Register A for Slave 8 MATRIX_PRAS8 Read/Write 0x00000222 (1) 0x00C4 Priority Register B for Slave 8 MATRIX_PRBS8 Read/Write 0x00000000 (1) 0x00C8–0x00FC Reserved – – – 0x0100 Master Remap Control Register MATRIX_MRCR Read/Write 0x00000000 0x0104–0x010C Reserved – – – 0x0110 CAN0 Configuration Register CCFG_CAN0 Read/Write 0x2040019D 0x0114 System I/O and CAN1 Configurat ion Register CCFG_SYSIO Read/Write 0x20400000 0x0118–0x0120 Reserved – – – 0x0124 SMC NAND Flash Chip Select Configuration Register CCFG_SMCNFCS Read/Write 0x00000000 0x0128–0x01E0 Reserved – – – 0x01E4 Write Protection Mode Register MATRIX_WPMR Read/Write 0x00000000 0x01E8 Write Protection Status Register MATRIX_WPSR Read-only 0x00000000 0x01EC–0x01FC Reserved – – – Table 18-4. Register Mapping (Continued) Offset Register Name Access Reset

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 108

18.4.1 Bus Matrix Master Configuration Registers

Name: MATRIX_MCFG0..MATRIX_MCFG11 Address: 0x40088000 [0], 0x40088004 [1], 0x40088008 [ 2], 0x4008800C [3], 0x40088010 [4], 0x40088014 [5], 0x40088018 [6], 0x40088020 [8], 0x40088024 [9], 0x40088028 [10], 0x4008802C [11] Access: Read/Write This register can only be written if the WPEN bit is cleared in the Write Protection Mode Register.

• ULBT: Undefined Length Burst Type Note: Unless duly needed, the ULBT should be left at its default ‘0’ value for power saving. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 Value Name Description 0U N L T D _ L E N G T H Unlimited Length Burst—No predicted en d of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts. This value should not be used in the very particular case of a master capable of performing back-to- back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. 1 SINGLE_ACCESS Single Access—The undefined length burst is treated as a succession of single accesses, allowing re- arbitration at each beat of the INCR burst or bursts sequence. 2 4BEAT_BURST 4-beat Burst—The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. 3 8BEAT_BURST 8-beat Burst—The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. 4 16BEAT_BURST 16-beat Burst—The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. 5 32BEAT_BURST 32-beat Burst —The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. 6 64BEAT_BURST 64-beat Burst—The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. 7 128BEAT_BURST 128-beat Burst—The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.

109SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

18.4.2 Bus Matrix Slave Configuration Registers

Name: MATRIX_SCFG0..MATRIX_SCFG8 Address: 0x40088040[0], 0x40088044 [1], 0x40088048 [2], 0x4008804C [3], 0x40088050 [4], 0x40088054 [5], 0x40088058 [6], 0x4008805C [7], 0x40088060 [8] Access: Read/Write This register can only be written if the WPEN bit is cleared in the Write Protection Mode Register.

• SLOT_CYCLE: Maximum Bus Gr ant Duration for Masters When SLOT_CYCLE AHB clock cycles have elapsed since the last arbitration, a new arbitration takes place to let another master access this slave. If another master is requesting the slave bus, then the current master burst is broken. If SLOT_CYCLE = 0, the slot cycle limit feature is disabled and bursts always complete unless broken according to the ULBT. This limit has been placed in order to enforce arbitration so as to meet potential latency constraints of masters waiting for slave access. This limit must not be too small. Unreasonably small values break every burst and the Bus Matrix arbitrates without per- forming any data transfer. The default maximum value is usually an optimal conservative choice. In most cases, this feature is not needed and should be disabled for power saving. See “Slot Cycle Limit Arbitration” for details.
• DEFMSTR_TYPE: Default Master Type
• FIXED_DEFMSTR: Fixed Default Master Number of the Default Master for this slave. Only used if DEFMSTR_TYPE is 2. Specifying the number of a master which is not connected to the selected slave is equivalent to setting DEFMSTR_TYPE to 0. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 – – FIXED_DEFMSTR DEFMSTR_TYPE 15 14 13 12 11 10 9 8 7654321 0 SLOT_CYCLE Value Name Description 0N O N E No Default Master—At the end of the current slave ac cess, if no other master request is pending, the slave is disconnected from all masters. This results in a one clock cycle latency for the first access of a burst transfer or for a single access. 1L A S T Last Default Master—At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it. This results in not having one clock cycle latency when the last master tries to access the slave again.

2 FIXED

Fixed Default Master—At the end of the current slav e access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field. This results in not having one clock cycle latency when the fixed master tries to access the slave again.

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 110

18.4.3 Bus Matrix Priority Registers A For Slaves

Name: MATRIX_PRAS0..MATRIX_PRAS8 Address: 0x40088080 [0], 0x40088088 [1], 0x40088090 [2], 0x40088098 [3], 0x400880A0 [4], 0x400880A8 [5], 0x400880B0 [6], 0x400880B8 [7], 0x400880C0 [8] Access: Read/Write This register can only be written if the WPE bit is cleared in the Write Protection Mode Register .

• MxPR: Master x Priority Fixed priority of Master x for accessing the selected slave. The higher the number, the higher the priority. All the masters programmed with the same MxPR value for the slave make up a priority pool. Round-robin arbitration is used in the lowest (MxPR = 0) and highest (MxPR = 3) priority pools. Fixed priority is used in intermediate priority pools (MxPR = 1) and (MxPR = 2). See “Arbitration Priority Scheme” for details. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 –– M 5PR –– M 4PR 15 14 13 12 11 10 9 8 –– M 3PR –– M 2PR 76543210 –– M 1PR –– M 0PR

111SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

18.4.4 Bus Matrix Priority Registers B For Slaves

Name: MATRIX_PRBS0..MATRIX_PRBS8 Address: 0x40088084 [0], 0x4008808C [1], 0x40088094 [2], 0x4008809C [3], 0x400880A4 [4], 0x400880AC [5], 0x400880B4 [6], 0x400880BC [7], 0x400880C4 [8] Access: Read/Write This register can only be written if the WPE bit is cleared in the Write Protection Mode Register .

• MxPR: Master x Priority Fixed priority of Master x for accessing the selected slave. The higher the number, the higher the priority. All the masters programmed with the same MxPR value for the slave make up a priority pool. Round-robin arbitration is used in the lowest (MxPR = 0) and highest (MxPR = 3) priority pools. Fixed priority is used in intermediate priority pools (MxPR = 1) and (MxPR = 2). See “Arbitration Priority Scheme” for details. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 – – M11PR – – M10PR 76543210 –– M 9PR –– M 8PR

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 112

18.4.5 Bus Matrix Master Remap Control Register

Name: MATRIX_MRCR Address: 0x40088100 Access: Read/Write This register can only be written if the WPEN bit is cleared in the Write Protection Mode Register.

• RCBx: Remap Command Bit for Master x 0: Disables remapped address decoding for the selected Master. 1: Enables remapped address decoding for the selected Master. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 –––– R CB11 R CB10 R CB9 R CB8 76543210 – RCB6 RCB5 RCB4 RCB3 RCB2 RCB1 RCB0

113SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

18.4.6 CAN0 Configuration Register

Name: CCFG_CAN0 Address: 0x40088110 Access: Read/Write

• Reserved: Do not change the reset value
• CAN0DMABA: CAN0 DMA Base Address Gives the 16-bit MSB of the CAN0 DMA base address. The 16-bit LSB must be programmed into CAN0 user interface. Default address is 0x20400000. 31 302 92 82 72 6 2 52 4 CAN0DMABA 23 22 21 20 19 18 17 16 CAN0DMABA 15 14 13 12 11 10 9 8 76543 21 0 Reserved

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 114

18.4.7 System I/O and CAN1 Configuration Register

Name: CCFG_SYSIO Address: 0x40088114 Access: Read/Write

• SYSIO4: PB4 or TDI Assignment 0: TDI function selected. 1: PB4 function selected.
• SYSIO5: PB5 or TDO/TRACESWO Assignment 0: TDO/TRACESWO function selected. 1: PB5 function selected.
• SYSIO6: PB6 or TMS/SWDIO Assignment 0: TMS/SWDIO function selected. 1: PB6 function selected.
• SYSIO7: PB7 or TCK/SWCLK Assignment 0: TCK/SWCLK function selected. 1: PB7 function selected.
• SYSIO12: PB12 or ERASE Assignment 0: ERASE function selected. 1: PB12 function selected.
• CAN1DMABA: CAN1 DMA Base Address Give the 16-bit MSB of the CAN1 DMA base address. The 16-bit LSB must be programmed into CAN1 User interface. Default address is 0x20400000. 31 302 92 82 72 6 2 52 4 CAN1DMABA 23 22 21 20 19 18 17 16 CAN1DMABA 15 14 13 12 11 10 9 8 76543 21 0 SYSIO7 SYSIO6 SYSIO5 SYSIO4 – – – –

115SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

18.4.8 SMC NAND Flash Chip Select Configuration Register

Name: CCFG_SMCNFCS Address: 0x40088124 Access: Read/Write

• SMC_NFCS0: SMC NAND Flash Chip Select 0 Assignment 0: NCS0 is not assigned to a NAND Flash (NANDOE and NANWE not used for NCS0). 1: NCS0 is assigned to a NAND Flash (NANDOE and NANWE used for NCS0).
• SMC_NFCS1: SMC NAND Flash Chip Select 1 Assignment 0: NCS1 is not assigned to a NAND Flash (NANDOE and NANWE not used for NCS1). 1: NCS1 is assigned to a NAND Flash (NANDOE and NANWE used for NCS1). WARNING: This must not be used if SDRAMEN is set.
• SMC_NFCS2: SMC NAND Flash Chip Select 2 Assignment 0: NCS2 is not assigned to a NAND Flash (NANDOE and NANWE not used for NCS2). 1: NCS2 is assigned to a NAND Flash (NANDOE and NANWE used for NCS2).
• SMC_NFCS3: SMC NAND Flash Chip Select 3 Assignment 0: NCS3 is not assigned to a NAND Flash (NANDOE and NANWE not used for NCS3). 1: NCS3 is assigned to a NAND Flash (NANDOE and NANWE used for NCS3).
• SDRAMEN: SDRAM Enable 0: NCS1 is not assigned to SDRAM. 1: NCS1 is assigned to SDRAM. WARNING: This must not be used if SMC_NFCS1 is set. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 – – – SDRAMEN SMC_NFCS3 SMC_NFCS2 SMC_NFCS1 SMC_NFCS0

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 116

18.4.9 Write Protection Mode Register

Name: MATRIX_WPMR Address: 0x400881E4 Access: Read/Write

• WPEN: Write Protection Enable 0: Disables the write protection if WPKEY corresponds to 0x4D4154 (“MAT” in ASCII). 1: Enables the write protection if WPKEY corresponds to 0x4D4154 (“MAT” in ASCII). See Section 18.3.6 ”Register Write Protection” for the list of registers that can be write-protected.
• WPKEY: Write Protection Key 31 30 29 28 27 26 25 24 WPKEY 23 22 21 20 19 18 17 16 WPKEY 15 14 13 12 11 10 9 8 WPKEY 76543210 Value Name Description 0x4D4154 PASSWD Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0.

117SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

18.4.10 Write Protection Status Register

Name: MATRIX_WPSR Address: 0x400881E8 Access: Read-only

• WPVS: Write Protection Violation Status 0: No write protection violation has occurred since the last write of the MATRIX_WPMR. 1: A write protection violation has occurred since the last write of the MATRIX_WPMR. If this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field WPVSRC.
• WPVSRC: Write Protection Violation Source When WPVS = 1, WPVSRC indicates the register address offset at which a write access has been attempted. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WPVSRC 15 14 13 12 11 10 9 8 WPVSRC 76543210

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 118 19. USB Transmitter Macr ocell Interface (UTMI)

19.1 Description

The USB Transmitter Macrocell Interf ace (UTMI) registers manage specific aspects of the integrated USB transmitter macrocell functionality not controlled in USB sections.

19.2 Embedded Characteristics

 32-bit UTMI Registers Control Product-specific Behavior

119SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

19.3 USB Transmitter Macrocell Interface (UTMI) User Interface

Table 19-1. Register Mapping Offset Register Name Access Reset 0x00-0x0C Reserved – – – 0x10 OHCI Interrupt Configuration Register UTMI_OHCIICR Read/Write 0x0 0x14–0x2C Reserved – – – 0x30 UTMI Clock Trimming Register UTMI_CKTRIM Read/Write 0x00010000 0x34–0x3C Reserved – – – 0x40-0xFC Reserved – – –

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 120

19.3.1 OHCI Interrupt Configuration Register

Name: UTMI_OHCIICR Address: 0x400E0410 Access: Read/Write

• RESx: USB PORTx Reset 0: Resets USB port. 1: Usable USB port.
• ARIE: OHCI Asynchronous Resume Interrupt Enable 0: Interrupt disabled. 1: Interrupt enabled.
• APPSTART: Reserved 0: Must write 0.
• UDPPUDIS: USB Device Pull-up Disable 0: USB device pull-up connection is enabled. 1: USB device pull-up connection is disabled. 31 302 92 82 72 62 52 4 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543 210 –– A PPSTART A RIE ––– R ES0

121SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

19.3.2 UTMI Clock Trimming Register

Name: UTMI_CKTRIM Address: 0x400E0430 Access: Read/Write

• FREQ: UTMI Refere nce Clock Frequency 31 302 92 82 72 62 52 4 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543 210 Value Name Description

0 XTAL12 12 MHz reference clock

1 XTAL16 16 MHz reference clock

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 122 20. Chip Identifier (CHIPID)

20.1 Description

Chip Identifier (CHIPID) registers are used to recognize the device and its revision. These registers provide the sizes and types of the on-chip memories, as well as the set of embedded peripherals. Two CHIPID registers are embedded: Chip ID Regist er (CHIPID_CIDR) and Chip ID Extension Register (CHIPID_EXID). Both registers contain a hard-wired value that is read-only. The CHIPID_CIDR register contains the following fields:  VERSION: Identifies the revision of the silicon  EPROC: Indicates the embedded ARM processor  NVPTYP and NVPSIZ: Identify the type of embedded non-volatile memory and the size  SRAMSIZ: Indicates the size of the embedded SRAM  ARCH: Identifies the set of embedded peripherals  EXT: Shows the use of the extension identifier register The CHIPID_EXID register is device-dependent and reads 0 if CHIPID_CIDR.EXT = 0.

20.2 Embedded Characteristics

 Chip ID Registers ̶ Identification of the Device Revision, Sizes of the Embedded Memories, Set of Peripherals, Embedded Processor Table 20-1. Chip ID Registers Chip Name CHIPID_CIDR CHIPID_EXID SAME70Q21 0xA102_0E00 0x00000002 SAME70Q20 0xA102_0C00 0x00000002 SAME70Q19 0xA10D_0A00 0x00000002 SAME70N21 0xA102_0E00 0x00000001 SAME70N20 0xA102_0C00 0x00000001 SAME70N19 0xA10D_0A00 0x00000001 SAME70J21 0xA102_0E00 0x00000000 SAME70J20 0xA102_0C00 0x00000000 SAME70J19 0xA10D_0A00 0x00000000 SAMS70Q21 0xA112_0E00 0x00000002 SAMS70Q20 0xA112_0C00 0x00000002 SAMS70Q19 0xA11D_0A00 0x00000002 SAMS70N21 0xA112_0E00 0x00000001 SAMS70N20 0xA112_0C00 0x00000001 SAMS70N19 0xA11D_0A00 0x00000001 SAMS70J21 0xA1120_E00 0x00000000 SAMS70J20 0xA112_0C00 0x00000000 SAMS70J19 0xA11D_0A00 0x00000000 SAMV71Q21 0xA122_0E00 0x00000002 SAMV71Q20 0xA122_0C00 0x00000002

123SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 SAMV71Q19 0xA12D_0A00 0x00000002 SAMV71N21 0xA122_0E00 0x00000001 SAMV71N20 0xA122_0C00 0x00000001 SAMV71N19 0xA12D_0A00 0x00000001 SAMV71J21 0xA122_0E00 0x00000000 SAMV71J20 0xA122_0C00 0x00000000 SAMV71J19 0xA12D_0A00 0x00000000 SAMV70Q20 0xA132_0C00 0x00000002 SAMV70Q19 0xA13D_0A00 0x00000002 SAMV70N20 0xA132_0C00 0x00000001 SAMV70N19 0xA13D_0A00 0x00000001 SAMV70J20 0xA1320_C00 0x00000000 SAMV70J19 0xA13D_0A00 0x00000000 Table 20-1. Chip ID Registers (Continued) Chip Name CHIPID_CIDR CHIPID_EXID

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 124

20.3 Chip Identifier (CHIPID) User Interface

Table 20-2. Register Mapping Offset Register Name Access Reset 0x0 Chip ID Register CHIPID_CIDR Read-only – 0x4 Chip ID Extension Register CHIPID_EXID Read-only –

125SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

20.3.1 Chip ID Register

Name: CHIPID_CIDR Address: 0x400E0940 Access: Read-only

• VERSION: Version of the Device Current version of the device.
• EPROC: Embedded Processor
• NVPSIZ: Nonvolatile Program Memory Size 31 30 29 28 27 26 25 24 EXT NVPTYP ARCH 23 22 21 20 19 18 17 16 ARCH SRAMSIZ 15 14 13 12 11 10 9 8 NVPSIZ2 NVPSIZ 76543210 EPROC VERSION Value Name Description

0 SAM x7 Cortex-M7

1 ARM946ES ARM946ES

2 ARM7TDMI ARM7TDMI

3 CM3 Cortex-M3

4 ARM920T ARM920T

5 ARM926EJS ARM926EJS

6 CA5 Cortex-A5

7 CM4 Cortex-M4

18 K 8 K b y t e s

4– R e s e r v e d 5 64K 64 Kbytes 6– R e s e r v e d 7 128K 128 Kbytes 8 160K 160 Kbytes 9 256K 256 Kbytes 10 512K 512 Kbytes

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 126

• NVPSIZ2: Second Nonvolatile Program Memory Size
• SRAMSIZ: Internal SRAM Size 11 – Reserved 12 1024K 1024 Kbytes 13 – Reserved 14 2048K 2048 Kbytes 15 – Reserved Value Name Description 0N O N E N o n e

4– R e s e r v e d 5 64K 64 Kbytes 6– R e s e r v e d 7 128K 128 Kbytes 8– R e s e r v e d 9 256K 256 Kbytes 10 512K 512 Kbytes 11 – Reserved 12 1024K 1024 Kbytes 13 – Reserved 14 2048K 2048 Kbytes 15 – Reserved Value Name Description 0 48K 48 Kbytes 1 192K 192 Kbytes 2 384K 384 Kbytes

36 K 6 K b y t e s

54 K 4 K b y t e s

88 K 8 K b y t e s

127SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

• ARCH: Architecture Identifier
• NVPTYP: Nonvolatile Program Memory Type
• EXT: Extension Flag 0: Chip ID has a single register definition without extension. 1: An extended Chip ID exists. 12 128K 128 Kbytes 13 256K 256 Kbytes 14 96K 96 Kbytes 15 512K 512 Kbytes Value Name Description 0x10 SAM E70 SAM E70 0x11 SAM S70 SAM S70 0x12 SAM V71 SAM V71 0x13 SAM V70 SAM V70 Value Name Description 0R O M R O M

1 ROMLESS ROMless or on-chip Flash

2 FLASH Embedded Flash Memory

3 ROM_FLASH

ROM and Embedded Flash Memory  NVPSIZ is ROM size  NVPSIZ2 is Flash size

4 SRAM SRAM emulating ROM

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 128

20.3.2 Chip ID Extension Register

Name: CHIPID_EXID Address: 0x400E0944 Access: Read-only

• EXID: Chip ID Extension This field is cleared if CHIPID_CIDR.EXT = 0. 31 30 29 28 27 26 25 24 EXID 23 22 21 20 19 18 17 16 EXID 15 14 13 12 11 10 9 8 EXID 76543210 EXID

129SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 21. Enhanced Embedded Flash Controller (EEFC)

21.1 Description

The Enhanced Embedded Flash Controller (EEFC) provides the interface of the Flash block with the 32-bit internal bus. Its 128-bit wide memory interface increases performance. It also manages the programming, erasing, locking and unlocking sequences of the Flash using a full set of commands. One of the commands returns the embedded Flash descriptor definition that informs the system about the Flash organization, thus making the software generic.

21.2 Embedded Characteristics

 Increases Performance in Thumb-2 Mode with 128-bit-wide Memory Interface up to 150 MHz  Code Loop Optimization  128 Lock Bits, Each Protecting a Lock Region  9 General-purpose GPNVM Bits  One-by-one Lock Bit Programming  Commands Protected by a Keyword  Erase the Entire Flash  Erase by Plane  Erase by Sector  Erase by Page  Provides Unique Identifier  Provides 512-byte User Signature Area  Supports Erasing before Programming  Locking and Unlocking Operations  ECC Single and Multiple Error Flags Report  Supports Read of the Calibration Bits  Register Write Protection

21.3 Product Dependencies

21.3.1 Power Management

The Enhanced Embedded Flash Controller (EEFC) is continuously clocked. The Power Management Controller has no effect on its behavior.

21.3.2 Interrupt Sources

The EEFC interrupt line is connected to the interrupt controller. Using the EEFC interrupt requires the interrupt controller to be programmed first. The EEFC interrupt is generated only if the value of bit EEFC_FMR.FRDY is 1. Table 21-1. Peripheral IDs Instance ID EFC 6

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 130

21.4 Functional Description

21.4.1 Embedded Flash Organization

The embedded Flash interfaces directly with the internal bus. The embedded Flash is composed of:  One memory plane organized in several pages of the same size for the code  A separate 2 x 512-byte memory area which includes the unique chip identifier  A separate 512-byte memory area for the user signature  Two 128-bit read buffers used for code read optimization  One 128-bit read buffer used for data read optimization  One write buffer that manages page programming. The write buffer size is equal to the page size. This buffer is write-only and accessible all along the 1 Mbyte address space, so that each word can be written to its final address.  Several lock bits used to protect write/erase operation on several pages (lock region). A lock bit is associated with a lock region composed of several pages in the memory plane.  Several bits that may be set and cleared through the EEFC interface, called general-purpose non-volatile memory bits (GPNVM bits) The embedded Flash size, the page size, the organization of lock regions and the defin ition of GPNVM bits are specific to the device. The EEFC returns a descriptor of the Flash controller after a ‘Get Flash Descriptor’ command has been issued by the application (see Section 21.4.3.1 ”Get Flash Descriptor Command”).

131SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 Figure 21-1. Flash Memory Areas @FBA+0x000User Signature Area Unique Identifier Area Unique Identifier Code Area @FBA+0x1FF @FBA+0x000 @FBA+0x3FF @FBA+0x000 Write “Start Unique Identifier” (Flash Command STUI) Write “Start User Signature” (Flash Command STUS) @FBA+0x010 @FBA+0x010 Write “Stop Unique Identifier” (Flash Command SPUI) Write “Stop User signature” (Flash Command SPUS) FBA = Flash Base Address

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 132 Figure 21-2. Organization of Embedded Flash for Code Start Address Page 0 Lock Region 0 Lock Region 1 Memory Plane Page (m-1) Lock Region (n-1) Page (n*m-1)Start Address + Flash size -1 Lock Bit 0 Lock Bit 1 Lock Bit (n-1)

133SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

21.4.2 Read Operations

An optimized controller manages embedded Flash reads, thus increasing performance when the processor is running in Thumb-2 mode by means of the 128-bit-wide memory interface. The Flash memory is accessible through 8-, 16- and 32-bit reads. As the Flash block size is smaller than the address s pace reserved for the internal memory area, the embedded Flash wraps around the address space and appears to be repeated within it. The read operations can be performed with or without wait states. Wait states must be programmed in the field FWS in the Flash Mode register (EEFC_FMR). Defining FWS as 0 enables the single-cycle access of the embedded Flash. For more details, refer to the section Section 56. ”Electrical Characteristics” of this datasheet.

21.4.2.1 Code Read Optimization

Code read optimization is enabled if the bit EEFC_FMR.SCOD is cleared. A system of 2 x 128-bit buffers is added in order to optimize sequential code fetch. Note: Immediate consecutive code read accesses are not mandatory to benefit from this optimization. The sequential code read optimization is enabled by default. If the bit EEFC_FMR.SCOD is set to 1, these buffers are disabled and the sequential code read is no longer optimized. Figure 21-3. Code Read Optimization for FWS = 0 Note: When FWS is equal to 0, all the accesses are performed in a single-cycle access. Another system of 2 x 128-bit buffers is added in order to optimize loop code fetch. Refer to Section 21.4.2.2 ”Code Loop Optimization” for more details. Flash Access Buffer 0 (128 bits) Master Clock ARM Request (32-bit) XXX Data to ARM Bytes 0–15 Bytes 16–31 Bytes 32–47 Bytes 0–15 Buffer 1 (128 bits) Bytes 32–47 Bytes 0–3 Bytes 4–7 Bytes 8–11 Bytes 12–15 Bytes 16–19 Bytes 20–23 Bytes 24–27XXX XXX Bytes 16–31 Bytes 28–31 anticipation of @16-31

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 134 Figure 21-4. Code Read Optimization for FWS = 3 Note: When FWS is between 1 and 3, in case of sequential reads, the first access takes (FWS + 1) cycles. The following accesses take only one cycle.

21.4.2.2 Code Loop Optimization

Code loop optimization is enabled when the bit EEFC_FMR.CLOE is set to 1. When a backward jump is inserted in the code, the pipeline of the sequential optimization is broken and becomes inefficient. In this case, the loop code read optimization takes over from the sequential code read optimization to prevent the insertion of wait states. The loop code read optimization is enabled by default. In EEFC_FMR, if the bit CLOE is reset to 0 or the bit SCOD is set to 1, these buffers are disabled and the loop code read is not optimized. When code loop optimization is enabled, if inner loop body instructions L 0 to Ln are positioned from the 128-bit Flash memory cell M b0 to the memory cell M p1, after recognition of a first backw ard branch, the first two Flash memory cells Mb0 and Mb1 targeted by this branch are cached for fast access from the processor at the next loop iteration. Then by combining the sequential prefetch (described in Section 21.4.2.1 ”Code Read Optimization”) through the loop body with the fast read access to the loop entry cache, the entire loop can be iterated with no wait state. Figure 21-5 illustrates code loop optimization. Figure 21-5. Code Loop Optimization Flash Access Buffer 0 (128 bits) Master Clock ARM Request (32-bit) Data to ARM Buffer 1 (128 bits) 0–3 XXX XXX Bytes 16–31 @ 0 @+4 @+8 Bytes 0–15 Bytes 16–31 Bytes 32–47 Bytes 48–6 Bytes 0–15 4–7 8–11 12–15 @+12 @+16 @+20 24–27 28–31 32–35 36–3916–19 20–23 40–43 44–47 Bytes 32–47 48–51 anticipation of @16-31 anticipation of @32-47 wait 3 cycles before 128-bit data is stable @0/4/8/12 are ready @16/20/24/28 are ready LnLn-1Ln-2Ln-3Ln-4Ln-5L5L4L3L2L1L0 B1 B2 B3 B4 B5 B6 B7B0 P1 P2 P3 P4 P5 P6 P7P0 Mb0Mb0 Mb1 Mp0 Mp1 B ackward address jump 2x128-bit loop entry cache 2x128-bit prefetch buffer L0 Loop Entry instruction Ln Loop End instruction Flash Memory 128-bit words Mb0 Branch Cache 0 Mb1 Branch Cache 1 Mp0 Prefetch Buffer 0 Mp1 Prefetch Buffer 1

135SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

21.4.2.3 Data Read Optimization

The organization of the Flash in 128 bits is associated with two 128-bit prefetch buffers and one 128-bit data read buffer, thus providing maximum system performance. This buffer is added in order to store the requested data plus all the data contained in the 128-bit aligned data. This speeds up sequential data reads if, for example, FWS is equal to 1 (see Figure 21-6). The data read optimization is enabled by default. If the bit EEFC_FMR.SCOD is set to 1, this buffer is disabled and the data read is no longer optimized. Note: No consecutive data read accesses are ma ndatory to benefit from this optimization. Figure 21-6. Data Read Optimization for FWS = 1 Flash Access Buffer (128 bits) Master Clock ARM Request (32-bit) XXX Data to ARM Bytes 0–15 Bytes 16–31 Bytes 0–15 Bytes 0–3 4–7 8–11 12–15 16–19 20–23XXX Bytes 16–31 @Byte 0 @ 4 @ 8 @ 12 @ 16 @ 20 @ 24 @ 28 @ 32 @ 36 XXX Bytes 32–47 24–27 28–31 32–35

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 136

21.4.3 Flash Commands

The EEFC offers a set of commands to manage programming the Flash memory, locking and unlocking lock regions, consecutive programming, locking and full Flash erasing, etc. The commands are listed in the following table. In order to execute one of these co mmands, select the required command us ing the FCMD field in the Flash Command register (EEFC_FCR). As soon as EEFC_FCR is written, the FRDY flag and the FVALUE field in the Flash Result register (EEFC_FRR) are automatically cleared. Once the current command has completed, the FRDY flag is automatically set. If an interrupt has been enabled by setting the bit EEFC_FMR.FRDY, the corresponding interrupt line of the interrupt controller is activated. (Note that this is true for all commands except for the STUI command. The FRDY flag is not set when the STUI command has completed.) All the commands are protected by the same keyword, which must be written in the eight highest bits of EEFC_FCR. Writing EEFC_FCR with data that does not contain the correct key and/or with an invalid command has no effect on the whole memory plane, but the FCMDE flag is set in the Flash Status register (EEFC_FSR). This flag is automatically cleared by a read access to EEFC_FSR. When the current command writes or erases a page in a locked region, the command has no effect on the whole memory plane, but the FLOCKE flag is set in EEFC_FSR. This flag is automatically cleared by a read access to EEFC_FSR. Table 21-2. Set of Commands Command Value Mnemonic Get Flash descriptor 0x00 GETD Write page 0x01 WP Write page and lock 0x02 WPL Erase page and write page 0x03 EWP Erase page and write page then lock 0x04 EWPL Erase all 0x05 EA Erase pages 0x07 EPA Set lock bit 0x08 SLB Clear lock bit 0x09 CLB Get lock bit 0x0A GLB Set GPNVM bit 0x0B SGPB Clear GPNVM bit 0x0C CGPB Get GPNVM bit 0x0D GGPB Start read unique identifier 0x0E STUI Stop read unique identifier 0x0F SPUI Get CALIB bit 0x10 GCALB Erase sector 0x11 ES Write user signature 0x12 WUS Erase user signature 0x13 EUS Start read user signature 0x14 STUS Stop read user signature 0x15 SPUS

137SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 Figure 21-7. Command State Chart Check if FRDY flag Set No Yes Read Status: EEFC_FSR Write FCMD and PAGENB in Flash Command Register Check if FLOCKE flag Set Check if FRDY flag Set No Read Status: EEFC_FSR Yes Yes Locking region violation No Check if FCMDE flag Set Yes No Bad keyword violation Command Successful

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 138

21.4.3.1 Get Flash Descriptor Command

This command provides the system with information on the Flash organization. The system can take full advantage of this information. For instance, a device co uld be replaced by one with more Flash capacity, and so the software is able to adapt itself to the new configuration. To get the embedded Flash descriptor, the application writes the GETD command in EEFC_FCR. The first word of the descriptor can be read by the software application in EEFC_FRR as soon as the FRDY flag in EEFC_FSR rises. The next reads of EEFC_FRR provide the followin g word of the descriptor. If extra read operations to EEFC_FRR are done after the last word of the descriptor has been returned, the EEFC_FRR value is 0 until the next valid command.

21.4.3.2 Write Commands

DMA write accesses must be 32-bit aligned. If a single byte is to be written in a 32-bit word, the rest of the word must be written with ones. Several commands are used to program the Flash. Only 0 values can be programmed using Flash technology; 1 is the erased value. In order to program words in a page, the page must first be erased. Commands are available to erase the full memory plane or a given number of pages. With the EWP and EWPL commands, a page erase is done automatically before a page programming. After programming, the page (the entire lock region) c an be locked to prevent miscellaneous write or erase sequences. The lock bit can be automatically set after page programming using WPL or EWPL commands. Data to be programmed in the Flash must be written in an internal latch buffer before writing the programming command in EEFC_FCR. Data can be written at their final de stination address, as the latch buffer is mapped into the Flash memory address space and wraps around within this Flash address space. Byte and half-word AHB accesses to the latch buffer are not allowed. Only 32-bit word accesses are supported. 32-bit words must be written continuously, in either as cending or descending order. Writ ing the latch buffer in a random order is not permitted. This prevents mapping a C-code structure to the latch buffer and accessing the data of the structure in any order. It is instead recommended to fill in a C-code structure in SRAM and copy it in the latch buffer in a continuous order. Write operations in the latch buffer are performed with the number of wait states programmed for reading the Flash. The latch buffer is automatically re-initialized, i.e., written with logical 1, after execution of each programming command. The programming sequence is the following: Table 21-3. Flash Descriptor Definition Symbol Word Index Description FL_ID 0 Flash interface description FL_SIZE 1 Flash size in bytes FL_PAGE_SIZE 2 Page size in bytes FL_NB_PLANE 3 Number of planes FL_PLANE[0] 4 Number of bytes in the plane FL_NB_LOCK 4 + FL_NB_PLANE Number of lock bits. A bit is associated with a lock region. A lock bit is used to prevent write or erase operations in the lock region. FL_LOCK[0] 4 + FL_NB_PLANE + 1 Number of bytes in the first lock region

139SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 1. Write the da ta to be programmed in the latch buffer. 2. Write the programming command in EEFC_FCR. Th is automatically clears the bit EEFC_FSR.FRDY. 3. When Flash programming is completed, the bit EEFC_ FSR.FRDY rises. If an interrupt has been enabled by setting the bit EEFC_FMR.FRDY , the interrupt line of the EEFC is activated. Three errors can be detected in EEFC_FSR after a programming sequence:  Command Error: A bad keyword has been written in EEFC_FCR.  Lock Error: The page to be programmed belongs to a locked region. A command must be run previously to unlock the corresponding region.  Flash Error: When programming is completed, the WriteVerify test of the Flash memory has failed. Only one page can be programmed at a time. It is po ssible to program all the bits of a page (full page programming) or only some of the bits of the page (partial page programming). Depending on the number of bits to be programmed within the page, the EEFC adapts the write operations required to program the Flash. When a ‘Write Page’ (WP) command is issued, the EEFC starts the programming sequence and all the bits written at 0 in the latch buffer are cleared in the Flash memory array. During programming, i.e., until EEFC_FSR.FDRY rises, access to the Flash is not allowed. Full Page Programming To program a full page, all the bits of the page must be erased before writing the latc h buffer and issuing the WP command. The latch buffer must be written in ascending order, starting from the first address of the page. See Figure 21-8 "Full Page Programming". Partial Page Programming To program only part of a page using the WP command, the following constraints must be respected: See Figure 21-9 "Partial Page Programming". Optimized Partial Page Programming The EEFC automatically detects the number of 128-bit wo rds to be programmed. If only one 128-bit aligned word is to be programmed in the Flash array, the process is optimized to reduce the time needed for programming. If several 128-bit words are to be programmed, a standard page programming operation is performed. See Figure 21-10 "Optimized Partial Page Programming". Programming Bytes Individual bytes can be programmed using the Partial page programming mode. Refer to Figure 21-11 "Programming Bytes in the Flash".  Data to be programmed must be contained in integer multiples of 128-bit address-aligned words.  128-bit words can be programmed only if all the corresponding bits in the Flash array are erased (at logical value 1). In this case, an area of 128 bits must be reserved for each byte.

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 140 Figure 21-8. Full Page Programming FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 0xX00 0xX04 0xX08 0xX0C 0xX10 0xX14 0xX18 0xX1C 0xX00 0xX04 0xX08 0xX0C 0xX10 0xX14 0xX18 0xX1C 0xX00 0xX04 0xX08 0xX0C 0xX10 0xX14 0xX18 0xX1C Before programming: Unerased page in Flash array CA FE CA FE CA FE CA FE CA FE CA FE CA FE CA FE CA FE CA FE CA FE CA FE CA FE CA FE CA FE CA FE Step 1: Flash array after page erase FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF address space for Page N address space for latch buffer Step 2: Writing a page in the latch buffer DE CA DE CA DE CA DE CA DE CA DE CA DE CA DE CA DE CA DE CA DE CA DE CA DE CA DE CA DE CA DE CA DE CA DE CA CA FE CA FE 0xX00 0xX04 0xX08 0xX0C 0xX10 0xX14 0xX18 0xX1C address space for Page N Step 3: Page in Flash array after issuing WP command and FRDY=1 DE CA DE CA DE CA DE CA DE CA DE CA DE CA DE CA DE CA DE CA DE CA DE CA DE CA DE CA DE CA DE CA DE CA DE CA FF FF FF FF 32 bits wide 32 bits wide

141SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 Figure 21-9. Partial Page Programming 32 bits wide 32 bits wide FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 0xX00 0xX04 0xX08 0xX0C 0xX10 0xX14 0xX18 0xX1C Step 2: Flash array after programming 128-bit at address 0xX00 (write latch buffer + WP) CA FE CA FE CA FE CA FE address space for Page N FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF Step 1: Flash array after page erase CA FE CA FE CA FE CA FE 32 bits wide 0xX00 0xX04 0xX08 0xX0C 0xX10 0xX14 0xX18 0xX1C Step 3: Flash array after programming a second 128-bit data at address 0xX10 (write latch buffer + WP) CA FE CA FE CA FE CA FE FF FF FF FF FF FF FF FF FF FF FF FF CA FE CA FE CA FE CA FE CA FE CA FE CA FE CA FE CA FE CA FE CA FE CA FE CA FE CA FE CA FE CA FE

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 142 Figure 21-10. Optimized Partial Page Programming 32 bits wide FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 32 bits wide FF FF FF FF Case 2: 2 x 32 bits modified, not crossing 128-bit boundary User programs WP, Flash Controller sends Write Word => Only 1 word programmed => programming period reduced FF FF FF FF FF FF FF FF FF FF FF FF CA FE FF FF FF FF CA FE CA FE FF FF FF FF CA FE 0xX00 0xX04 0xX08 0xX0C 0xX10 0xX14 0xX18 0xX1C 0xX00 0xX04 0xX08 0xX0C 0xX10 0xX14 0xX18 0xX1C 32 bits wide FF FF FF FF Case 3: 4 x 32 bits modified across 128-bit boundary User programs WP, Flash Controller sends WP => Whole page programmed FF FF FF FF FF FF FF FF FF FF FF FF 32 bits wide FF FF FF FF Case 4: 4 x 32 bits modified, not crossing 128-bit boundary User programs WP, Flash Controller sends Write Word => Only 1 word programmed => programming period reduced FF FF FF FF FF FF FF FF FF FF FF FF CA FE CA FE 0xX00 0xX04 0xX08 0xX0C 0xX10 0xX14 0xX18 0xX1C 0xX00 0xX04 0xX08 0xX0C 0xX10 0xX14 0xX18 0xX1C CA FE CA FE CA FE CA FE CA FE CA FE CA FE CA FE CA FE CA FE CA FE CA FE CA FE CA FE FF FF FF FF CA FE CA FE Case 1: 2 x 32 bits modified, not crossing 128-bit boundary User programs WP, Flash Controller sends Write Word => Only 1 word programmed => programming period reduced CA FE CA FE FF FF FF FF FF FF FF FF 4 x 32 bits 4 x 32 bits 4 x 32 bits 4 x 32 bits

143SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 Figure 21-11. Programming Bytes in the Flash

21.4.3.3 Erase Commands

Erase commands are allowed only on unlocked regions. Depending on the Flash memory, several commands can be used to erase the Flash:  Erase All Memory (EA): All memory is erased. The processor must not fetch code from the Flash memory.  Erase Pages (EPA): 8 or 16 pages are erased in the Flash sector selected. The first page to be erased is specified in the FARG[15:2] field of the EEFC_FCR. The first page number must be a multiple of 8, 16 or 32 depending on the number of pages to erase at the same time.  Erase Sector (ES): A full memory sector is erased. Sector size depends on the Flash memory. EEFC_FCR.FARG must be set with a page number that is in the sector to be erased. If the processor is fetching code fr om the Flash memory while the EPA or ES command is being executed, the processor accesses are stalled until the EPA command is completed. To avoid stalling the processor, the code can be run out of internal SRAM. The erase sequence is the following: 32 bits wide FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 0xX00 0xX04 0xX08 0xX0C 0xX10 0xX14 0xX18 0xX1C address space for Page N Step 1: Flash array after programming first byte (0xAA) 128-bit used at address 0xX00 (write latch buffer + WP) FF FF FF FF xx xx xx xx xx xx xx AA 32 bits wide 0xX00 0xX04 0xX08 0xX0C 0xX10 0xX14 0xX18 0xX1C FF FF FF FF xx xx xx xx xx xx xx AA Step 2: Flash array after programming second byte (0x55) 128-bit used at address 0xX10 (write latch buffer + WP) xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx 55 xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx Note: The byte location shown here is for example only, it can be any byte location within a 64-bit word 4 x 32 bits =

1 Flash word

4 x 32 bits = Note: If one subsector is locked within the first sector, the Erase Sector (ES) command cannot be processed on non-locked subsectors of the fi rst sector. All the lock bits of the first se ctor must be cleared prior to issuing an ES command on the first sector. After the ES command has been is sued, the first sector lock bits must be reverted to the state before clearing them.

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 144 1. Er ase starts as soon as one of the erase commands and the FARG field are written in EEFC_FCR. ̶ For the EPA command, the two lowest bits of the FARG field define the number of pages to be erased (FARG[1:0]): 2. When erasing is completed, the bit EEFC_FSR.FRDY rises. If an interrupt has been enabled by setting the bit EEFC_FMR.FRDY, the interrupt line of the interrupt controller is activated. Three errors can be detected in EEFC_FSR after an erasing sequence:  Command Error: A bad keyword has been written in EEFC_FCR.  Lock Error: At least one page to be erased belongs to a locked region. The erase command has been refused, no page has been erased. A command must be run previously to unlock the corresponding region.  Flash Error: At the end of the erase period, the EraseVerify test of the Flash memory has failed.

21.4.3.4 Lock Bit Protection

Lock bits are associated with several pages in the embedded Flash memory plane. This defines lock regions in the embedded Flash memory plane. They prevent writing/erasing protected pages. The lock sequence is the following: 1. Execute the ‘ Set Lock Bit’ command by writing EEFC_FCR.FCMD with the SLB command and EEFC_FCR.FARG with a page number to be protected. 2. When the locking completes, the bit EEFC_FSR.FRDY rises. If an interrupt has been enabled by setting the bit EEFC_FMR.FRDY, the interrupt line of the interrupt controller is activated. 3. The result of the SLB command can be checke d running a ‘Get Lock Bit’ (GLB) command. Note: The value of the FARG argument pa ssed together with SLB command must not exceed the higher lock bit index available in the product. Two errors can be detected in EEFC_FSR after a programming sequence:  Command Error: A bad keyword has been written in EEFC_FCR.  Flash Error: At the end of the programming, the EraseVerify or WriteVerify test of the Flash memory has failed. It is possible to clear lock bits prev iously set. After the lock bits are cleared, the locked region can be erased or programmed. The unlock sequence is the following: 1. Execute the ‘Cle ar Lock Bit’ command by writing EEFC_FCR.FCMD with the CLB command and EEFC_FCR.FARG with a page number to be unprotected. 2. When the unlock completes, the bit EEFC_FSR.FRDY rises. If an interrupt has been enabled by setting the bit EEFC_FMR.FRDY, the interrupt line of the interrupt controller is activated. Note: The value of the FARG argument pa ssed together with CLB command must not exceed the higher lock bit index available in the product. Two errors can be detected in EEFC_FSR after a programming sequence:  Command Error: A bad keyword has been written in EEFC_FCR.  Flash Error: At the end of the programming, the EraseVerify or WriteVerify test of the Flash memory has failed. Table 21-4. EEFC_FCR.FARG Field for EPA Command FARG[1:0] Number of pages to be erased with EPA command 0 4 pages (only valid for small 8 KB sectors) 1 8 pages (only valid for small 8 KB sectors) 2 16 pages 3 32 pages (not valid for small 8 KB sectors)

145SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 The status of lock bits can be returned by the EEFC. The ‘Get Lock Bit’ sequence is the following: 1. Execute the ‘Get Lock Bit’ comm and by writing EEFC_FCR.FCMD with the GLB command. Field EEFC_FCR.FARG is meaningless. 2. Lock bits can be read by the software application in EEFC_FRR. The first word read corresponds to the 32 first lock bits, next reads providing the next 32 lock bits as long as it is meaningful. Extra reads to EEFC_FRR return 0. For example, if the third bit of the first word read in EEFC_FRR is set, the third lock region is locked. Two errors can be detected in EEFC_FSR after a programming sequence:  Command Error: A bad keyword has been written in EEFC_FCR.  Flash Error: At the end of the programming, the EraseVerify or WriteVerify test of the Flash memory has failed. Note: Access to the Flash in read is permitted when a ‘Set Lock Bit’, ‘Clear Lock Bit’ or ‘Get Lock Bit’ command is executed.

21.4.3.5 GPNVM Bit

GPNVM bits do not interfere with the embedded Flash memory plane. For more details, refer to Section 10. ”Memories” of this datasheet. The ‘Set GPNVM Bit’ sequence is the following: 1. Execute the ‘ Set GPNVM Bit’ command by writing EEFC_FCR.FCMD with the SGPB command and EEFC_FCR.FARG with the number of GPNVM bits to be set. 2. When the GPNVM bit is set, the bit EEFC_FSR.FRDY ri ses. If an interrupt was enabled by setting the bit EEFC_FMR.FRDY, the interrupt line of the interrupt controller is activated. 3. The result of the SGPB command can be checked by running a ‘Get GPNVM Bit’ (GGPB) command. Note: The value of the FARG argument pa ssed together with SGPB command must not exceed the higher GPNVM index available in the product. Flash data content is not altered if FARG exceeds the limit. Command Error is detected only if FARG is greater than 8. Two errors can be detected in EEFC_FSR after a programming sequence:  Command Error: A bad keyword has been written in EEFC_FCR.  Flash Error: At the end of the programming, the EraseVerify or WriteVerify test of the Flash memory has failed. It is possible to clear GPNVM bits previously set. The ‘Clear GPNVM Bit’ sequence is the following: 1. Execute the ‘Cle ar GPNVM Bit’ command by writing EEFC_FCR.FCMD with the CGPB command and EEFC_FCR.FARG with the number of GPNVM bits to be cleared. 2. When the clear completes, the bit EEFC_FSR.FRDY rises. If an interrupt has been enabled by setting the bit EEFC_FMR.FRDY, the interrupt line of the interrupt controller is activated. Note: The value of the FARG argument passed together with CGPB command must not exceed the higher GPNVM index available in the product. Flash data content is not altered if FARG exceeds the limit. Command Error is detected only if FARG is greater than 8. Two errors can be detected in EEFC_FSR after a programming sequence:  Command Error: A bad keyword has been written in EEFC_FCR.  Flash Error: At the end of the programming, the EraseVerify or WriteVerify test of the Flash memory has failed. The status of GPNVM bits can be returned by the EEFC. The sequence is the following: 1. Execute the ‘Get GPNVM Bit’ comm and by writing EEFC_FCR.FCMD with the GGPB command. Field EEFC_FCR.FARG is meaningless. 2. GPNVM bits can be read by the software application in EEFC_FRR. The first word read corresponds to the 32 first GPNVM bits, following reads provide the next 32 GPNVM bits as long as it is meaningful. Extra reads to EEFC_FRR return 0.

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 146 For example, if the third bit of the first word read in EEFC_FRR is set, the third GPNVM bit is active. One error can be detected in EEFC_FSR after a programming sequence:  Command Error: A bad keyword has been written in EEFC_FCR. Note: Access to the Flash in read is permitted when a ‘Set GP NVM Bit’, ‘Clear GPNVM Bit’ or ‘Get GPNVM Bit’ command is executed.

21.4.3.6 Calibration Bit

Calibration bits do not interfere with the embedded Flash memory plane. The calibration bits cannot be modified. The status of calibration bits are returned by the EEFC. The sequence is the following: 1. Execute the ‘Get CALIB Bit’ comm and by writing EEFC_FCR.FCMD with the GCALB command. Field EEFC_FCR.FARG is meaningless. 2. Calibration bits can be read by the software application in EEFC_FRR. The first word read corresponds to the first 32 calibration bits. The following reads provide the next 32 calibration bits as long as it is meaningful. Extra reads to EEFC_FRR return 0. The 8/12 MHz fast RC oscillator is calibrated in production. This calibration can be read through the GCALB command. Table 21-5 shows the bit implementation. The RC calibration for the 4 MHz is set to ‘1000000’.

21.4.3.7 Security Bit Protection

When the security bit is enabled, the Embedded Trace Macrocell (ETM) is disabled and access to the Flash through the SWD interface or through the Fast Flash Programming interface is forbidden. This ensures the confidentiality of the code programmed in the Flash. The security bit is GPNVM0. Disabling the security bit can only be achieved by asse rting the ERASE pin at ‘1’, and after a full Flash erase is performed. When the security bit is deactivated, all accesses to the Flash are permitted.

21.4.3.8 Unique Identifier Area

Each device is programmed with a 128-bit unique identifier area. See Figure 21-1 "Flash Memory Areas". The sequence to read the unique identifier area is the following: 1. Execute the ‘Start Read Unique Identifier’ comman d by writing EEFC_FCR.FCMD with the STUI command. Field EEFC_FCR.FARG is meaningless. 2. Wait until the bit EEFC_FSR.FRDY falls to read the un ique identifier area. The unique identifier field is located in the first 128 bits of the Flash memory mapping. The ‘Start Read Unique Identifier’ command reuses some addresses of the memory plane for code, but the unique identifier area is physically different from the memory plane for code. 3. To stop reading the unique identifier area, execute t he ‘Stop Read Unique Identifier’ command by writing EEFC_FCR.FCMD with the SPUI command. Field EEFC_FCR.FARG is meaningless. 4. When the SPUI command has been executed, the bit EEFC_FSR.FRDY rises. If an interrupt was enabled by setting the bit EEFC_FMR.FRDY, the interrupt line of the interrupt controller is activated. Note that during the sequence, the software cannot be fetched from the Flash. Table 21-5. Calibration Bit Indexes RC Calibration Frequency EEFC_FRR Bits

8 MHz output [28–22]

12 MHz output [38–32]

147SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

21.4.3.9 User Signature Area

Each product contains a user signature area of 512 bytes. It can be used for storage. Read, write and erase of this area is allowed. See Figure 21-1 "Flash Memory Areas". The sequence to read the user signature area is the following: 1. Execute the ‘Start Read User Signature’ command by writing EEFC_FCR.FCMD with the STUS command. Field EEFC_FCR.FARG is meaningless. 2. Wait until the bit EEFC_FSR.FRDY falls to read the user signature area. The user signature area is located in the first 512 bytes of the Flash memory mapping. The ‘Start Read User Signature’ command reuses some addresses of the memory plane but the user signature area is physically different from the memory plane 3. To stop reading the user signat ure area, execute the ‘Stop Read User Signature’ command by writing EEFC_FCR.FCMD with the SPUS command. Field EEFC_FCR.FARG is meaningless. 4. When the SPUI command has been executed, the bit EEFC_FSR.FRDY rises. If an interrupt was enabled by setting the bit EEFC_FMR.FRDY, the interrupt line of the interrupt controller is activated. Note that during the sequence, the software cannot be fetched from the Flash or from the second plane in case of dual plane. One error can be detected in EEFC_FSR after this sequence:  Command Error: A bad keyword has been written in EEFC_FCR. The sequence to write the user signature area is the following: 1. Write the full p age, at any page address, within the internal memory area address space. 2. Execute the ‘Write User Signature’ command by writing EEFC_FCR.FCMD with the WUS command. Field EEFC_FCR.FARG is meaningless. 3. When programming is completed, the bit EEFC_FSR.FR DY rises. If an interrupt has been enabled by setting the bit EEFC_FMR.FRDY, the corresponding interrupt line of the interrupt controller is activated. Two errors can be detected in EEFC_FSR after this sequence:  Command Error: A bad keyword has been written in EEFC_FCR.  Flash Error: At the end of the programming, the WriteVerify test of the Flash memory has failed. The sequence to erase the user signature area is the following: 1. Execute the ‘Erase User Signature’ command by writing EEFC_FCR.FCMD with the EUS command. Field EEFC_FCR.FARG is meaningless. 2. When programming is completed, the bit EEFC_FSR.FR DY rises. If an interrupt has been enabled by setting the bit EEFC_FMR.FRDY, the corresponding interrupt line of the interrupt controller is activated. Two errors can be detected in EEFC_FSR after this sequence:  Command Error: A bad keyword has been written in EEFC_FCR.  Flash Error: At the end of the programming, the EraseVerify test of the Flash memory has failed.

21.4.3.10 ECC Errors and Corrections

The Flash embeds an ECC module able to correct one unique error and able to detect two errors. The errors are detected while a read access is performed into memory array and stored in EEFC_FSR (see Section 21.5.3 ”EEFC Flash Status Register”). The error report is kept until EEFC_FSR is read. There is one flag for a unique error on lower half part of the Flash word (64 LSB) and one flag for the upper half part (MSB). The multiple errors are reported in the same way. Due to the anticipation technique to improve bandwidth throughput on instruction fetch, a reported error can be located in the next sequential Flash word compared to the location of the instruction being executed, which is located in the previously fetched Flash word.

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 148 If a software routine processes the e rror detection independently from the main software routine, the entire Flash located software must be rewritten because there is no storage of the error location. If only a software routine is running to program and ch eck pages by reading EEFC_FSR, the situation differs from the previous case. Performing a chec k for ECC unique errors just after page programming completion involves a read of the newly programmed page. This read sequence is viewed as data accesses and is not optimized by the Flash controller. Thus, in case of unique error, only the current page must be reprogrammed.

21.4.4 Register Write Protection

To prevent any single software error from corrupting EEFC behavior, certain registers in the address space can be write-protected by setting the WPEN bit in the (EEFC_WPMR). The following register can be write-protected:  EEFC Flash Mode Register

149SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

21.5 Enhanced Embedded Flash Cont roller (EEFC) User Interface

The User Interface of the Embedded Flash Controller (EEFC) is integrated within the System Controller with base address 0x400E0C00. Table 21-6. Register Mapping Offset Register Name Access Reset State 0x00 EEFC Flash Mode Register EEFC_FMR Read/Write 0x0400_0000 0x04 EEFC Flash Command Register EEFC_FCR Write-only – 0x08 EEFC Flash Status Register EEFC_FSR Read-only 0x0000_0001 0x0C EEFC Flash Result Register EEFC_FRR Read-only 0x0 0x10–0x14 Reserved – – – 0x18–0xE0 Reserved – – – 0xE4 Write Protection Mode Register EEFC_WPMR Read/Write 0x0

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 150

21.5.1 EEFC Flash Mode Register

Name: EEFC_FMR Address: 0x400E0C00 Access: Read/Write This register can only be written if the WPEN bit is cleared in the “EEFC Write Protection Mode Register” .

• FRDY: Flash Ready Interrupt Enable 0: Flash ready does not generate an interrupt. 1: Flash ready (to accept a new command) generates an interrupt.
• FWS: Flash Wait State This field defines the number of wait states for read and write operations: FWS = Number of cycles for Read/Write operations - 1
• SCOD: Sequential Code Optimization Disable 0: The sequential code optimization is enabled. 1: The sequential code optimization is disabled. No Flash read should be done during change of this field.
• CLOE: Code Loop Optimization Enable 0: The opcode loop optimization is disabled. 1: The opcode loop optimization is enabled. No Flash read should be done during change of this field. 31 302 92 82 72 62 52 4 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 –––– FWS 76543 210

151SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

21.5.2 EEFC Flash Command Register

Name: EEFC_FCR Address: 0x400E0C04 Access: Write-only

• FCMD: Flash Command 31 302 92 82 72 62 52 4 FKEY 23 22 21 20 19 18 17 16 FARG 15 14 13 12 11 10 9 8 FARG 76543 210 FCMD Value Name Description 0x00 GETD Get Flash descriptor 0x01 WP Write page 0x02 WPL Write page and lock 0x03 EWP Erase page and write page 0x04 EWPL Erase page and write page then lock 0x05 EA Erase all 0x07 EPA Erase pages 0x08 SLB Set lock bit 0x09 CLB Clear lock bit 0x0A GLB Get lock bit 0x0B SGPB Set GPNVM bit 0x0C CGPB Clear GPNVM bit 0x0D GGPB Get GPNVM bit 0x0E STUI Start read unique identifier 0x0F SPUI Stop read unique identifier 0x10 GCALB Get CALIB bit 0x11 ES Erase sector 0x12 WUS Write user signature 0x13 EUS Erase user signature 0x14 STUS Start read user signature 0x15 SPUS Stop read user signature

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 152

• FARG: Flash Command Argument
• FKEY: Flash Writing Protection Key GETD, GLB, GGPB, STUI, SPUI, GCALB, WUS, EUS, STUS, SPUS, EA Commands requiring no argument, including Erase all command FARG is meaningless, must be written with 0 ES Erase sector command FARG must be written with any page number within the sector to be erased EPA Erase pages command FARG[1:0] defines the number of pages to be erased The start page must be written in FARG[15:2]. FARG[1:0] = 0: Four pages to be erased. FARG[15:2] = Page_Number / 4 FARG[1:0] = 1: Eight pages to be erased. FARG[15:3] = Page_Number / 8, FARG[2]=0 FARG[1:0] = 2: Sixteen pages to be erased. FARG[15:4] = Page_Number / 16, FARG[3:2]=0 FARG[1:0] = 3: Thirty-two pages to be erased. FARG[15:5] = Page_Number / 32, FARG[4:2]=0 Refer to Table 21-4 “EEFC_FCR.FARG Field for EPA Command”. WP , WPL, EWP , EWPL Programming commands FARG must be written with the page number to be programmed SLB, CLB Lock bit commands FARG defines the page number to be locked or unlocked SGPB, CGPB GPNVM commands FARG defines the GPNVM number to be programmed Value Name Description 0x5A PASSWD The 0x5A value enables the command defined by the bits of the register. If the field is written with a different value, the write is not performed and no action is started.

153SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

21.5.3 EEFC Flash Status Register

Name: EEFC_FSR Address: 0x400E0C08 Access: Read-only

• FRDY: Flash Ready Status (cleared when Flash is busy) 0: The EEFC is busy. 1: The EEFC is ready to start a new command. When set, this flag triggers an interrupt if the FRDY flag is set in EEFC_FMR. This flag is automatically cleared when the EEFC is busy.
• FCMDE: Flash Command Error Status (cleared on read or by writing EEFC_FCR) 0: No invalid commands and no bad keywords were written in EEFC_FMR. 1: An invalid command and/or a bad keyword was/were written in EEFC_FMR.
• FLOCKE: Flash Lock Error Status (cleared on read) 0: No programming/erase of at least one locked region has happened since the last read of EEFC_FSR. 1: Programming/erase of at least one locked region has happened since the last read of EEFC_FSR. This flag is automatically cleared when EEFC_FSR is read or EEFC_FCR is written.
• FLERR: Flash Error Status (cleared when a programming operation starts) 0: No Flash memory error occurred at the end of programming (EraseVerify or WriteVerify test has passed). 1: A Flash memory error occurred at the end of programming (EraseVerify or WriteVerify test has failed).
• UECCELSB: Unique ECC Error on LSB Part of the Memory Flash Data Bus (cleared on read) 0: No unique error detected on 64 LSB data bus of the Flash memory since the last read of EEFC_FSR. 1: One unique error detected but corrected on 64 LSB data bus of the Flash memory since the last read of EEFC_FSR.
• MECCELSB: Multiple ECC Error on LSB Part of the Memory Flash Data Bus (cleared on read) 0: No multiple error detected on 64 LSB part of the Flash memory data bus since the last read of EEFC_FSR. 1: Multiple errors detected and NOT corrected on 64 LSB part of the Flash memory data bus since the last read of EEFC_FSR.
• UECCEMSB: Unique ECC Error on MSB Part of the Memory Flash Data Bus (cleared on read) 0: No unique error detected on 64 MSB data bus of the Flash memory since the last read of EEFC_FSR. 1: One unique error detected but corrected on 64 MSB data bus of the Flash memory since the last read of EEFC_FSR. 31 302 92 82 72 62 52 4 23 22 21 20 19 18 17 16 –––– M ECCEMSB UECCEMSB MECCELSB U ECCELSB 15 14 13 12 11 10 9 8 76543 210 –––– F LERR F LOCKE F CMDE F RDY

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 154

• MECCEMSB: Multiple ECC Error on MSB Part of the Memory Flash Data Bus (cleared on read) 0: No multiple error detected on 64 MSB part of the Flash memory data bus since the last read of EEFC_FSR. 1: Multiple errors detected and NOT corrected on 64 MSB part of the Flash memory data bus since the last read of EEFC_FSR.

155SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

21.5.4 EEFC Flash Result Register

Name: EEFC_FRR Address: 0x400E0C0C Access: Read-only

• FVALUE: Flash Result Value The result of a Flash command is returned in this register. If the size of the result is greater than 32 bits, the next resulting value is accessible at the next register read. 31 302 92 82 72 62 52 4 FVALUE 23 22 21 20 19 18 17 16 FVALUE 15 14 13 12 11 10 9 8 FVALUE 76543 210 FVALUE

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 156

21.5.5 EEFC Write Protection Mode Register

Name: EEFC_WPMR Address: 0x400E0CE4 Access: Read/Write

• WPEN: Write Protection Enable 0: Disables the write protection if WPKEY corresponds to 0x454643 (EFC in ASCII). 1: Enables the write protection if WPKEY corresponds to 0x454643 (EFC in ASCII). See Section 21.4.4 ”Register Write Protection” for the list of registers that can be protected.
• WPKEY: Write Protection Key 31 302 92 82 72 62 52 4 WPKEY 23 22 21 20 19 18 17 16 WPKEY 15 14 13 12 11 10 9 8 WPKEY 76543 210 Value Name Description 0x454643 PASSWD Writing any other value in this field aborts the write operation. Always reads as 0.

157SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 22. Supply Controller (SUPC)

22.1 Description

The Supply Controller (SUPC) controls the supply voltages of the system and manages the Backup mode. In this mode, current consumption is reduced to a few microamps for backup power retention. Exit from this mode is possible on multiple wake-up sources. The SUPC also generates the slow clock by selecting either the low-power RC oscillator or the low-power crystal oscillator.

22.2 Embedded Characteristics

 Manages the core power supply VDDCORE and backup mode by controlling the embedded voltage regulator  A supply monitor detection on VDDIO or a brownout detection on VDDCORE triggers a core reset  Generates the slow clock SLCK by selecting either the 22-42 kHz low-power RC oscillator or the 32 kHz low- power crystal oscillator  Backup SRAM  Low-power tamper detection on two inputs  Anti-tampering by immediate clear of the general-purpose backup registers  Supports multiple wake-up sources for exit from backup mode ̶ 14 Wake-up Inputs with programmable debouncing ̶ Real-Time Clock Alarm ̶ Real-Time Timer Alarm ̶ Supply monitor detection on VDDIO, with programmable scan period and voltage threshold

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 158

22.3 Block Diagram

Figure 22-1. Supply Controller Block Diagram Backup Area VDDOUT VDDIN on/off Reset Controller vddcore_nreset supc_irqPower-On Reset VDDCORE Brown-Out Detector VDDCORE por_core_out bod_out sm_out por_io_out Real-Time Clock WKUP0-WKUP13 Voltage Regulator Controller Real-Time Timer rtc_alarm VROFF Supply Monitor Controller BODDIS SMSMPL SMTH OSCBYPASS SMRSTEN BODRSTEN XTALSEL Slow Clock Controller SMIEN Supply Controller SMEN Wake-Up Controller RTCEN rtt_alarm RTTEN RTCOUT0 RTCOUT1 sm_out LPDBCEN0 LPDBCEN1 LPDBCCLR WKUPEN0..15 WKUPT0..15 WKUPDBC LPDBC General-Purpose Backup Registers clear wake_up SLCK XIN32 XOUT32 Programmable Supply Monitor VDDIO Zero-Power Power-On Reset VDDIO XTAL OSC 32kHz RC OSC 32kHz Interrupt Controller ONREG proc_nreset periph_nreset ice_nreset Backup SRAM BKUPRETON Power SwitchVDDIO Core Voltage Regulator SLCK VDDCORE Backup Mode NRST

159SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

22.4 Functional Description

22.4.1 Overview

The device is divided into two power supply areas:  VDDIO power supply: includes the Supply Controller, part of the Reset Controller, the slow clock switch, the general-purpose backup registers, the supply monitor and the clock which includes the Real-time Timer and the Real-time Clock.  Core power supply: includes part of the Reset Controller, the Brownout Detector, the processor, the SRAM memory, the Flash memory and the peripherals. The Supply Controller (SUPC) controls the supply volt age of the core power supply. The SUPC intervenes when the VDDIO power supply rises (when the system is starting) or when Backup mode is entered. The SUPC also integrates the slow clock generator, which is based on a 32 kHz crystal oscillator, and an embedded 32 kHz RC oscillator. The slow clock defaults to the RC oscillat or, but the software can enable the crystal oscillator and select it as the slow clock source. The SUPC and the VDDIO power supply have a reset circuitry based on a zero-power power-on reset cell. The zero-power power-on reset allows the SUPC to start correctly as soon as the VDDIO voltage becomes valid. At start-up of the system, once th e backup voltage VDDIO is valid and the embedded 32 kHz RC oscillator is stabilized, the SUPC starts up the core by sequentially enabling the internal voltage regulator. The SUPC waits until the core voltage VDDCORE is valid, then releases the reset signal of the core vddcore_nreset signal. Once the system has started, the user can program a supply mo nitor and/or a brownout detector. If the supply monitor detects a voltage level on VDDI O that is too low, the SUPC as serts the reset signal of the core vddcore_nreset signal until VDDIO is valid. Likewise, if the brownout de tector detects a core voltage level VDDCORE that is too low, the SUPC asserts the reset signal vddcore_nreset until VDDCORE is valid. When Backup mode is entered, the SUPC sequentially a sserts the reset signal of the core power supply vddcore_nreset and disables the voltage regulator, in order to supply only the V DDIO power supply. Current consumption is reduced to a few micr oamps for the backup part retention. Ex it from this mode is possible on multiple wake-up sources including an event on WKUP pi ns, or a clock alarm. To exit this mode, the SUPC operates in the same way as system start-up.

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 160

22.4.2 Slow Clock Generator

The SUPC embeds a slow clock generator that is supplied with the VDDIO power supply. As soon as the VDDIO is supplied, both the crystal oscillat or and the embedded RC oscillator are powered up, but only the embedded RC oscillator is enabled. When the RC oscillator is selected as the slow clock source, the slow clock stabilizes more quickly than when the crystal oscillator is selected. The user can select the crystal oscillator to be the source of the slow clock, as it provides a more accurate frequency than the RC oscillator. The crystal oscillator is selected by setting the XTALSEL bit in the SUPC Control register (SUPC_CR). The following sequence must be used to switch from the RC oscillator to the crystal oscillator: 1. The PIO lines multiplexed with XIN 32 and XOUT32 are configured to be driven by the oscillator. 2. The crystal oscillator is enabled. 3. A number of RC oscillator clock periods is counted to cover the start-up time of the crystal oscillator. Refer to Section 56. ”Electrical Characteristics” for information on 32 kHz crystal oscillator start-up time. 4. The slow clock is switched to t he output of the crystal oscillator. 5. The RC oscillator is disabled to save power. The switching time may vary depending on the RC oscillator clock frequency range. The sw itch of the slow clock source is glitch-free. The OSCSEL bit of the SUPC Status register (SUPC_SR) indicates when the switch sequence is finished. Reverting to the RC oscillator as a slow clock source is only possible by shutting down the VDDIO power supply. If the user does not need the crystal oscillator, the XIN32 and XOUT32 pins should be left unconnected. The user can also set the crystal oscillator in Bypass m ode instead of connecting a crystal. In this case, the user has to provide the external clock signal on XIN32. The i nput characteristics of the XIN32 pin are given in the section ‘Electrical Characteristics. To enter Bypass mode, the OSCBYPASS bit in the Mode register (SUPC_MR) must be set before setting XTALSEL.

22.4.3 Core Voltage Regulator Control/Backup Low-power Mode

The SUPC can be used to control the embedded voltage regulator. The voltage regulator automatically adapts its quiescent current depending on the required load current. Refer to Section 56. ”Electrical Characteristics”. The user can switch off the voltage regulator, and thus put the device in Backup mode, by writing a 1 to the VROFF bit in SUPC_CR. Backup mode can also be entered by executing the WFE (Wait for Event) Cortex-M processor instruction with the SLEEPDEEP bit set to 1. This asserts the vddcore_nreset signal after the write resynchronization time, which lasts two slow clock cycles (worst case). Once the vddcore_nreset signal is asserted, the processor and the peripherals are stopped one slow clock cycle before the core power supply shuts off. When the internal voltage regulator is not used and VDDCORE is supplied by an external supply, the voltage regulator can be disabled by writing a 1 to the ONREG bit in SUPC_MR.

161SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

22.4.4 Using Backup Batteries/Backup Supply

When backup batteries or, more generally, a separate back up supply is used, only VDD IO voltage is present in Backup mode. No other external supply is applied on the chip. In this case, the VDDIORDY bit in SUPC_MR must be cleared at least two slow clock periods before VDDIO voltage is removed. When waking up from Backup mode, VDDIORDY must be set. Figure 22-2. Separate Backup Supply Powering Scheme Note: Restrictions With main supply < 3.0V, USB is not usable. With main supply < 2.0V, ADC, DAC and Analog comparator are not usable. With main supply and VDDIN > 3V, all peripherals are usable. Main Supply VDDCORE Supply ADC, DAC Analog Comp. USB Transceivers. VDDIN Voltage Regulator VDDOUT VDDCORE VDDIO VDDPLL VDDUTMIC VDDUTMII

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 162 When no separate backup supply for VDDIO is used, since the external voltage applied on VDDIO is kept, all the I/O configurations (i.e., WKUP pin configuration) are maintained in Backup mode. When not using backup batteries, VDDIORDY is set so the user does not need to program it. Figure 22-3. No Separate Backup Supply Powering Scheme Note: Restrictions With main supply < 2.0 V, USB and ADC/DAC and analog comparator are not usable. With main supply > 2.0V and < 3V, USB is not usable. With main supply > 3V, all peripherals are usable. Main Supply ADC, DAC Analog Comp. USB Transceivers VDDIN Voltage Regulator VDDOUT VDDCORE VDDIO VDDPLL VDDUTMIC VDDUTMII

163SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 Figure 22-4 illustrates an example of the po wering scheme when using a backup battery. Since the PIO state is preserved when in Backup mode, any free PIO line can be used to switch off the extern al regulator by driving the PIO line at low level (PIO is input, pull-up enabled after backup reset). System wake-up can be performed using a wake-up pin (WKUPx). See Section 22.4.9 ”Wake-up Sources” for further details. Figure 22-4. Battery Backup

22.4.5 Supply Monitor

The SUPC embeds a supply monitor located in the VDDIO power supply and which monitors VDDIO power supply. The supply monitor can be used to prevent the processor from falling into an unpredictable state if the main power supply drops below a certain level. The threshold of the supply monitor is programmable in the SMTH field of the Supply Monitor Mode register (SUPC_SMMR). Refer to Supply Monitor characteristics in Section 56. ”Electrical Characteristics”. The supply monitor can also be enabled during one slow clock period on every one of either 32, 256 or 2048 slow clock periods, depending on the user selection. This is configured in the SMSMPL field in SUPC_SMMR. Enabling the supply monitor for such reduced times divides the typical supply monitor power consumption by factors of 2, 16 and 128, respectively, if continuous monitoring of the VDDIO power supply is not required. A supply monitor detection generates either a reset of the core power supply or a wake-up of the core power supply. Generating a core reset when a supply monitor detection occurs is enabled by setting the SMRSTEN bit in SUPC_SMMR. Waking up the core power supply when a supply monitor detection occurs can be enabled by setting the SMEN bit in the Wake-up Mode register (SUPC_WUMR). The SUPC provides two status bits in the SUPC_SR for the supply monitor t hat determine whether the last wake- up was due to the supply monitor: ADC, DAC Analog Comp. USB Transceivers. VDDIN Voltage RegulatorLDO Regulator Backup Battery + ON/OFF IN OUT VDDOUTMain Supply VDDCORE VDDUTMII VDDIO VDDPLL PIOx (Output) WKUPx External wakeup signal Note: The two diodes provide a “switchover circuit” between the backup battery and the main supply when the system is put in backup mode. VDDUTMIC

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 164  The SMOS bit provides real-time information, updated at each measurement cycle or updated at each slow clock cycle, if the measurement is continuous.  The SMS bit provides saved information and shows a supply monitor detection has occurred since the last read of SUPC_SR. The SMS flag generates an interrupt if the SMIEN bit is set in SUPC_SMMR. Figure 22-5. Supply Monitor Status Bit and Associated Interrupt

22.4.6 Backup Power Supply Reset

22.4.6.1 Raising the Backup Power Supply

When the backup voltage VDDIO rises, the RC oscillator is powered up and the zero-power power-on reset cell maintains its output low as long as VDDIO has not reached its target voltage. During this period, the SUPC is reset. When the VDDIO voltage becomes valid and the zero-power power-on reset signal is released, a counter is started for five slow clock cycles. This is the time required for the 32 kHz RC oscillator to stabilize. After this time, the voltage regulator is enabled. The core power supply ri ses and the brownout detector provides the bodcore_in signal as soon as the core voltage VDDCORE is valid. This results in releasing the vddcore_nreset signal to the Reset Controll er after the bodcore_in signal has been confirmed as being valid for at least one slow clock cycle. Supply Monitor ON 3.3 V 0 V Threshold SMS and SUPC interrupt Read SUPC_SR Periodic Sampling Continuous Sampling (SMSMPL = 1)

165SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 Figure 22-6. Raising the VDDIO Power Supply

22.4.7 Core Reset

The Supply Controller manages the vddcore_nreset signal to the Reset Controller, as described in Section 22.4.6 ”Backup Power Supply Reset”. The vddcore_nreset signal is normally asserted before shutting down the core power supply and released as soon as the core power supply is correctly regulated. There are two additional sources which can be programmed to activate vddcore_nreset:  a supply monitor detection  a brownout detection

22.4.7.1 Supply Monitor Reset

The supply monitor is capable of generating a reset of the system. This is enabled by setting the SMRSTEN bit in SUPC_SMMR. If SMRSTEN is set and if a supply monitor detection occurs, the vddcore_nreset signal is immediately activated for a minimum of one slow clock cycle.

22.4.7.2 Brownout Detector Reset

The brownout detector provides the bodcore_in signal to the SUPC. This signal indicates that the voltage regulation is operating as programmed. If this signal is lost for longer than 1 slow clock period while the voltage regulator is enabled, the SUPC asserts vddcore_nreset if BODRSTEN is written to 1 in SUPC_MR. Zero-Power Power-On Reset Cell output 22 - 42 kHz RC Oscillator output Fast RC Oscillator output Backup Power Supply vr_on bodcore_in vddcore_nreset NRST (no ext. drive assumed) proc_nreset Note: After “proc_nreset” rising, the core starts fetching instructions from Flash at 4 MHz. periph_nreset 7 x Slow Clock Cycles 3 x Slow Clock Cycles 2 x Slow Clock Cycles 6.5 x Slow Clock Cycles TON Voltage Regulator Zero-Power POR Core Power Supply RSTC.ERSTL (5 for startup slow RC + 2 for synchro.) default = 2

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 166 If BODRSTEN is set and the voltage regulation is lost (output voltage of the regulator too low), the vddcore_nreset signal is asserted for a minimum of one slow clock cycle and then rel eased if bodcore_in has been reactivated. The BODRSTS bit in SUPC_SR indicates the source of the last reset. Until bodcore_in is deactivated, the vddcore_nreset signal remains active.

22.4.8 Controlling the SRAM Power Supply

The SUPC can be used to switch on or off the power supply of the backup SRAM by opening or closing the SRAM power switch. This power switch is controlled by the BKUPRETON bit of SUPC_MR. However, the battery backup SRAM is automatically switched on when the core power supply is enabled, as the processor requires the SRAM as data memory space.  If BKUPRETON is written to 1, there is no immediate effect, but the SRAM will be left powered when the SUPC enters Backup mode, thus retaining its content.  If BKUPRETON is written to 0, there is no immediate effect, but the SRAM will be switched off when the SUPC enters Backup mode. The SRAM is automatically switched on when Backup mode is exited.

22.4.9 Wake-up Sources

The wake-up events allow the device to exit Backup mode. When a wake-up event is detected, the SUPC performs a sequence that automatically reenables the core power supply. Figure 22-7. Wake-up Sources WKUP13 WKUPEN13WKUPT13 WKUPEN1 WKUPEN0 Debouncer SLCK WKUPDBC WKUPS RTCEN rtc_alarm SMEN sm_out Core Supply Restart WKUPIS0 WKUPIS1 WKUPIS13 WKUPT0 WKUPT1 WKUP0 WKUP1 RTTEN rtt_alarm Debouncer RTCOUT0 LPDBC Debouncer LPDBC RTCOUT0 LPDBCS0 LPDBCS1LPDBCEN1 WKUPT1 LPDBCEN0 WKUPT0 Falling/Rising Edge Detect Low-power Tamper Detection Logic GPBR Clear LPDBCCLR LPDBCS1 LPDBCS0 Falling/Rising Edge Detect Falling/Rising Edge Detect Falling/Rising Edge Detect Falling/Rising Edge Detect

167SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

22.4.9.1 Wake-up Inputs

The wake-up inputs, WKUPx, can be programmed to perform a wake-up of the core power supply. Each input can be enabled by writing a 1 to the corresponding bit, WKUPENx, in the Wake-up Inputs register (SUPC_WUIR). The wake-up level can be selected with the corresponding polarity bit, WKUPTx, also located in SUPC_WUIR. The resulting signals are wired-ORed to trigger a debounce counter, which is programmed with the WKUPDBC field in SUPC_WUMR. The WKUPDBC field selects a debouncing period of 3, 32, 512, 4,096 or 32,768 slow clock cycles. The duration of these periods corresponds, resp ectively, to about 100 µs, about 1 ms, about 16 ms, about 128 ms and about 1 second (for a typical slow clock frequency of 32 kHz). Programming WKUPDBC to 0x0 selects an immediate wake-up, i.e., an enabled WKUP pin must be active according to its polarity during a minimum of one slow clock period to wake up the core power supply. If an enabled WKUP pin is asserted for a duration longer than the debouncing period, a wake-up of the core power supply is started and the signals, WKUP0 to WKUPx as shown in Figure 22-7 "Wake-up Sources" , are latched in SUPC_SR. This allows the user to identify the source of the wake-up. However, if a new wake-up condition occurs, the primary information is lost. No new wake-up can be detected si nce the primary wake-up condition has disappeared. Before instructing the system to enter Backup mode, if the field WKUPDBC > 0, it must be checked that none of the WKUPx pins that are enabled for a wake-up (exit from Backup mode) holds an active polarity. This is checked by reading the pin status in the PIO Controller. If WKUPENx=1 and the pin WKUPx holds an active polarity, the system must not be instructed to enter Backup mode. Figure 22-8. Entering and Exiting Backup Mode with a WKUP Pin

22.4.9.2 Low-power Tamper De tection and Anti-Tampering

Low-power debouncer inputs (WKUP0, WKUP1) can be used fo r tamper detection. If the tamper sensor is biased through a resistor and constantly driven by the power supply, this leads to power consumption as long as the tamper detection switch is in its active state. To prevent power consumption when the switch is in active state, the tamper sensor circuitry must be intermittently powered , and thus a specific waveform must be applied to the sensor circuitry. The waveform is generated using RTCOUTx in all modes including Backup mode. Refer to Section 26. ”Real-time Clock (RTC)” for waveform generation. Separate debouncers are embedded, one for WKUP0 input, one for WKUP1 input. The WKUP0 and/or WKUP1 inputs perform a system wake-up upon tamper detection. This is enabled by setting the LPDBCEN0/1 bit in the SUPC_WUMR. WKUP0 and/or WKUP1 inputs can also be used when VDDCORE is powered to detect a tamper. WKUPx WKUPTx=0 Active BACKUP Active BACKUP Active BACKUPSystem Edge detect + debounce time Edge detect + debounce time active runtime active runtime VROFF=1VROFF=1 check WKUPx status check WKUPx status WKUPDBC > 0

169SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 The wake-up polarity of the inputs can be independently configured by writing WKUPT0 and/ or WKUPT1 fields in SUPC_WUMR. In order to determine which wake-up/tamper pin triggers the system wa ke-up, a status flag is associated for each low-power debouncer. These flags are read in SUPC_SR. A debounce event (tamper detection) can perform an immediate clear (0 delay) on the first half the general- purpose backup registers (GPBR). The LPDBCCLR bit must be set in SUPC_WUMR. Note that it is not mandatory to use the RTCOUTx pin when using the WKUP0/WKUP1 pins as tampering inputs in any mode. Using the RTCOUTx pin provides a “sampling mode” to further reduce the power consumption of the tamper detection circuitry. If RTCOUTx is not used, the RTC must be configured to create an internal sampling point for the debouncer logic. The period of time betw een two samples can be configured by programming the TPERIOD field in RTC_MR. Figure 22-11 illustrates the use of WKUPx without the RTCOUTx pin. Figure 22-11. Using WKUP Pins Without RTCOUTx Pins

22.4.9.3 Clock Alarms

The RTC and the RTT alarms can generate a wake-up of the core power supply. This can be enabled by setting, respectively, the bits RTCEN and RTTEN in SUPC_WUMR. The Supply Controller does not provide any status as the information is available in the user interface of either the Real-Time Timer or the Real-Time Clock.

22.4.9.4 Supply Monitor Detection

The supply monitor can generate a wake-up of the core power supply. See Section 22.4.5 ”Supply Monitor”. MCU WKUP0 WKUP1 VDDIO Pull-up Resistor Pull-up Resistor GND GND GND

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 170

22.4.10 Register Write Protection

To prevent any single software error from corrupting SYSC behavior, certain registers in the address space can be write-protected by setti ng the WPEN bit in the ”System Controller Write Protection Mode Register” (SYSC_WPMR). The following registers can be write-protected:  RSTC Mode Register  RTT Mode Register  RTT Alarm Register  RTC Control Register  RTC Mode Register  RTC Time Alarm Register  RTC Calendar Alarm Register  General Purpose Backup Registers  Supply Controller Control Register  Supply Controller Supply Monitor Mode Register  Supply Controller Mode Register  Supply Controller Wake-up Mode Register  Supply Controller Wake-up Inputs Register

22.4.11 Register Bits in Backup Domain (VDDIO)

The following configuration registers, or certain bits of the registers, are physically located in the product backup domain:  RSTC Mode Register (all bits)  RTT Mode Register (all bits)  RTT Alarm Register (all bits)  RTC Control Register (all bits)  RTC Mode Register (all bits)  RTC Time Alarm Register (all bits)  RTC Calendar Alarm Register (all bits)  General Purpose Backup Registers (all bits)  Supply Controller Control Register (see register description for details)  Supply Controller Supply Monitor Mode Register (all bits)  Supply Controller Mode Register (see register description for details)  Supply Controller Wake-up Mode Register (all bits)  Supply Controller Wake-up Inputs Register (all bits)  Supply Controller Status Register (all bits)

171SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

22.5 Supply Controller (S UPC) User Interface

The user interface of the Supply Controller is part of the System Controller user interface.

22.5.1 System Controller (SYSC) User Interface

22.5.2 Supply Controller (SUPC) User Interface

Table 22-1. System Controller Registers Offset System Controller Peripheral Name 0x00-0x0c Reset Controller RSTC 0x10-0x2C Supply Controller SUPC 0x30-0x3C Real Time Timer RTT 0x50-0x5C Watchdog Timer WDT 0x60-0x8C Real Time Clock RTC 0x90-0xDC General Purpose Backup Register GPBR 0xE0 Reserved – 0xE4 Write Protection M ode Register SYSC_WPMR 0xE8-0xF8 Reserved – Table 22-2. Register Mapping Offset Register Name Access Reset 0x00 Supply Controller Control Register SUPC_CR Write-only – 0x04 Supply Controller Supply Monitor M ode Register SUPC_SMMR Read/Write 0x0000_0000 0x08 Supply Controller Mode Regi ster SUPC_MR Read/Write 0x0000_5A00 0x0C Supply Controller Wake-up Mode Re gister SUPC_WUMR Read/Write 0x0000_0000 0x10 Supply Controller Wake-up Inputs Register SUPC_WUIR Read/Write 0x0000_0000 0x14 Supply Controller Status Register SUPC_SR Read-only 0x0000_0000 0x18 Reserved – – –

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 172

22.5.3 Supply Controller Control Register

Name: SUPC_CR Address: 0x400E1810 Access: Write-only This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode Register (SYSC_MR).

• VROFF: Voltage Regulator Off 0 (NO_EFFECT): No effect. 1 (STOP_VREG): If KEY is correct, VROFF asserts the vddcore_nreset and stops the voltage regulator. Note: This bit is located in the VDDIO domain.
• XTALSEL: Crystal Oscillator Select 0 (NO_EFFECT): No effect. 1 (CRYSTAL_SEL): If KEY is correct, XTALSEL switches the slow clock on the crystal oscillator output. Note: This bit is located in the VDDIO domain.
• KEY: Password 31 30 29 28 27 26 25 24 KEY 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 Value Name Description 0xA5 PASSWD Writing any other value in this field aborts the write operation.

173SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

22.5.4 Supply Controller Supply Monitor Mode Register

Name: SUPC_SMMR Address: 0x400E1814 Access: Read/Write This register is located in the VDDIO domain. This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode Register (SYSC_MR).

• SMTH: Supply Monitor Threshold Selects the threshold voltage of the supply monitor. Refer to Section 56. ”Electrical Characteristics” for voltage values.
• SMSMPL: Supply Monitor Sampling Period
• SMRSTEN: Supply Monitor Reset Enable 0 (NOT_ENABLE): The core reset signal vddcore_nreset is not affected when a supply monitor detection occurs. 1 (ENABLE): The core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs.
• SMIEN: Supply Monitor Interrupt Enable 0 (NOT_ENABLE): The SUPC interrupt signal is not affected when a supply monitor detection occurs. 1 (ENABLE): The SUPC interrupt signal is asserted when a supply monitor detection occurs. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 – – SMIEN SMRSTEN – SMSMPL 76543210 –––– SMTH Value Name Description 0x0 SMD Supply Monitor disabled 0x1 CSM Continuous Supply Monitor 0x2 32SLCK Supply Monitor enabled one SLCK period every 32 SLCK periods 0x3 256SLCK Supply Monitor enabled one SLCK period every 256 SLCK periods 0x4 2048SLCK Supply Monitor enabled one SLCK period every 2,048 SLCK periods

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 174

22.5.5 Supply Controller Mode Register

Name: SUPC_MR Address: 0x400E1818 Access: Read/Write This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode Register (SYSC_MR).

• BODRSTEN: Brownout Detector Reset Enable 0 (NOT_ENABLE): The core reset signal vddcore_nreset is not affected when a brownout detection occurs. 1 (ENABLE): The core reset signal, vddcore_nreset is asserted when a brownout detection occurs. Note: This bit is located in the VDDIO domain.
• BODDIS: Brownout Detector Disable 0 (ENABLE): The core brownout detector is enabled. 1 (DISABLE): The core brownout detector is disabled. Note: This bit is located in the VDDIO domain.
• ONREG: Voltage Regulator Enable 0 (ONREG_UNUSED): Internal voltage regulator is not used (external power supply is used). 1 (ONREG_USED): Internal voltage regulator is used. Note: This bit is located in the VDDIO domain.
• BKUPRETON: SRAM On In Backup Mode 0: SRAM (Backup) switched off in Backup mode. 1: SRAM (Backup) switched on in Backup mode. Note: This bit is located in the VDDIO domain.
• OSCBYPASS: Oscillator Bypass 0 (NO_EFFECT): No effect. Clock selection depends on the value of XTALSEL (SUPC_CR). 1 (BYPASS): The 32 kHz crystal oscillator is bypassed if XTALSEL (SUPC_CR) is set. OSCBYPASS must be set prior to setting XTALSEL. Note: This bit is located in the VDDIO domain. 31 30 29 28 27 26 25 24 KEY 23 22 21 20 19 18 17 16 – – – OSCBYPASS – – BKUPRETON – 15 14 13 12 11 10 9 8 – O N R E G B O D D I S B O D R S T E N –––– 76543210

175SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

• KEY: Password Key Value Name Description 0xA5 PASSWD Writing any other value in this field aborts the write operation.

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 176

22.5.6 Supply Controller Wake-up Mode Register

Name: SUPC_WUMR Address: 0x400E181C Access: Read/Write This register is located in the VDDIO domain. This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode Register (SYSC_MR).

• SMEN: Supply Monitor Wake-up Enable 0 (NOT_ENABLE): The supply monitor detection has no wake-up effect. 1 (ENABLE): The supply monitor detection forces the wake-up of the core power supply.
• RTTEN: Real-time Timer Wake-up Enable 0 (NOT_ENABLE): The RTT alarm signal has no wake-up effect. 1 (ENABLE): The RTT alarm signal forces the wake-up of the core power supply.
• RTCEN: Real-time Clock Wake-up Enable 0 (NOT_ENABLE): The RTC alarm signal has no wake-up effect. 1 (ENABLE): The RTC alarm signal forces the wake-up of the core power supply.
• LPDBCEN0: Low-power Debouncer Enable WKUP0 0 (NOT_ENABLE): The WKUP0 input pin is not connected to the low-power debouncer. 1 (ENABLE): The WKUP0 input pin is connected to the low-power debouncer and forces a system wake-up.
• LPDBCEN1: Low-power Debouncer Enable WKUP1 0 (NOT_ENABLE): The WKUP1 input pin is not connected to the low-power debouncer. 1 (ENABLE): The WKUP1 input pin is connected to the low-power debouncer and forces a system wake-up.
• LPDBCCLR: Low-power Debouncer Clear 0 (NOT_ENABLE): A low-power debounce event does not create an immediate clear on the first half of GPBR registers. 1 (ENABLE): A low-power debounce event on WKUP0 or WKUP1 generates an immediate clear on the first half of GPBR registers. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 LPDBCCLR LPDBCEN1 LPDBCEN0 – RTCEN RTTEN SMEN –

177SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

• WKUPDBC: Wake-up Inputs Debouncer Period
• LPDBC: Low-power Debouncer Period Value Name Description 0 IMMEDIATE Immediate, no deboun cing, detected active at least on one Slow Clock edge. 13 _SLCK WKUPx shall be in its active state for at least 3 SLCK periods 2 32_SLCK WKUPx shall be in its active state for at least 32 SLCK periods 3 512_SLCK WKUPx shall be in its active state for at least 512 SLCK periods 4 4096_S LCK WKUPx shall be in its active state for at least 4,096 SLCK periods 5 32768_S LCK WKUPx shall be in its active state for at least 32,768 SLCK periods Value Name Description 0 DISABLE Disable the low-power debouncers. 1 2_RTCOUT WKUP0/1 in active state for at least 2 RTCOUTx clock periods 2 3_RTCOUT WKUP0/1 in active state for at least 3 RTCOUTx clock periods 3 4_RTCOUT WKUP0/1 in active state for at least 4 RTCOUTx clock periods 4 5_RTCOUT WKUP0/1 in active state for at least 5 RTCOUTx clock periods 5 6_RTCOUT WKUP0/1 in active state for at least 6 RTCOUTx clock periods 6 7_RTCOUT WKUP0/1 in active state for at least 7 RTCOUTx clock periods 7 8_RTCOUT WKUP0/1 in active state for at least 8 RTCOUTx clock periods

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 178

22.5.7 Supply Controller Wake-up Inputs Register

Name: SUPC_WUIR Address: 0x400E1820 Access: Read/Write This register is located in the VDDIO domain. This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode Register (SYSC_MR).

• WKUPEN0 - WKUPENx: Wake- up Input Enable 0 to x 0 (DISABLE): The corresponding wake-up input has no wake-up effect. 1 (ENABLE): The corresponding wake-up input is enabled for a wake-up of the core power supply.
• WKUPT0 - WKUPTx: Wake-up Input Type 0 to x 0 (LOW): A falling edge followed by a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. 1 (HIGH): A rising edge followed by a high level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. 31 30 29 28 27 26 25 24 – – WKUPT13 WKUPT12 WKUPT11 WKUPT10 WKUPT9 WKUPT8 23 22 21 20 19 18 17 16 WKUPT7 WKUPT6 WKUPT5 WKUPT4 WKUPT3 WKUPT2 WKUPT1 WKUPT0 15 14 13 12 11 10 9 8 – – WKUPEN13 WKUPEN12 WKUPEN 11 WKUPEN10 WKUPEN9 WKUPEN8 76543210 WKUPEN7 WKUPEN6 WKUPEN5 WKUPEN4 WKUPEN3 WKUPEN2 WKUPEN1 WKUPEN0

179SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

22.5.8 Supply Controller Status Register

Name: SUPC_SR Address: 0x400E1824 Access: Read-only Note: Because of the asynchronism between the Slow Clock (SLCK) and the System Clock (MCK), the status register flag reset is taken into account only 2 slow clock cycles after the read of the SUPC_SR. This register is located in the VDDIO domain.

• WKUPS: WKUP Wake-up Stat us (cleared on read) 0 (NO): No wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. 1 (PRESENT): At least one wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR.
• SMWS: Supply Monitor Detection Wake-up Status (cleared on read) 0 (NO): No wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR. 1 (PRESENT): At least one wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR.
• BODRSTS: Brownout Detector Reset Status (cleared on read) 0 (NO): No core brownout rising edge event has been detected since the last read of the SUPC_SR. 1 (PRESENT): At least one brownout output rising edge event has been detected since the last read of the SUPC_SR. When the voltage remains below the defined threshold, there is no rising edge event at the output of the brownout detec- tion cell. The rising edge event occurs only when there is a voltage transition below the threshold.
• SMRSTS: Supply Monitor Reset Status (cleared on read) 0 (NO): No supply monitor detection has generated a core reset since the last read of the SUPC_SR. 1 (PRESENT): At least one supply monitor detection has generated a core reset since the last read of the SUPC_SR.
• SMS: Supply Monitor Status (cleared on read) 0 (NO): No supply monitor detection since the last read of SUPC_SR. 1 (PRESENT): At least one supply monitor detection since the last read of SUPC_SR.
• SMOS: Supply Monitor Output Status 0 (HIGH): The supply monitor detected VDDIO higher than its threshold at its last measurement. 1 (LOW): The supply monitor detected VDDIO lower than its threshold at its last measurement. 31 30 29 28 27 26 25 24 – – WKUPIS13 WKUPIS12 WKUPIS11 WKUPIS10 WKUPIS9 WKUPIS8 23 22 21 20 19 18 17 16 WKUPIS7 WKUPIS6 WKUPIS5 WKUPIS4 WKUPIS3 WKUPIS2 WKUPIS1 WKUPIS0 15 14 13 12 11 10 9 8 76543210 OSCSEL SMOS SMS SMRSTS BODRSTS SMWS WKUPS –

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 180

• OSCSEL: 32-kHz Oscillator Selection Status 0 (RC): The slow clock, SLCK, is generated by the embedded 32 kHz RC oscillator. 1 (CRYST): The slow clock, SLCK, is generated by the 32 kHz crystal oscillator.
• LPDBCS0: Low-power Debouncer Wake-up Status on WKUP0 (cleared on read) 0 (NO): No wake-up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR. 1 (PRESENT): At least one wake-up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR.
• LPDBCS1: Low-power Debouncer Wake-up Status on WKUP1 (cleared on read) 0 (NO): No wake-up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR. 1 (PRESENT): At least one wake-up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR.
• WKUPISx: WKUPx Input Status (cleared on read) 0 (DIS): The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. 1 (EN): The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR.

181SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

22.5.9 System Controller Write Protection Mode Register

Name: SYSC_WPMR Access: Read/Write

• WPEN: Write Protection Enable 0: Disables the write protection if WPKEY corresponds to 0x525443 (“RTC” in ASCII). 1: Enables the write protection if WPKEY corresponds to 0x525443 (“RTC” in ASCII). See Section 22.4.10 ”Register Write Protection” for the list of registers that can be write-protected.
• WPKEY: Write Protection Key. 31 30 29 28 27 26 25 24 WPKEY 23 22 21 20 19 18 17 16 WPKEY 15 14 13 12 11 10 9 8 WPKEY 76543210 Value Name Description 0x525443 PASSWD Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0.

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 182 23. Watchdog Timer (WDT)

23.1 Description

The Watchdog Timer (WDT) is used to prevent system lock-up if the software becomes trapped in a deadlock. It features a 12-bit down counter that allows a watchdog period of up to 16 seconds (slow clock around 32 kHz). It can generate a general reset or a processor reset only. In addition, it can be stop ped while the processor is in Debug mode or Sleep mode (Idle mode).

23.2 Embedded Characteristics

 12-bit Key-protected Programmable Counter  Watchdog Clock is Independent from Processor Clock  Provides Reset or Interrupt Signals to the System  Counter May Be Stopped while the Processor is in Debug State or in Idle Mode

183SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

23.3 Block Diagram

Figure 23-1. Watchdog Timer Block Diagram = 0 set resetread WDT_SR or reset wdt_fault (to Reset Controller) set reset WDFIEN wdt_int WDT_MR SLCK1/128 12-bit Down Counter Current Value WDD WDT_MR <= WDD WDV WDRSTT WDT_MR WDT_CR reload WDUNF WDERR reload write WDT_MR WDT_MR WDRSTEN

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 184

23.4 Functional Description

The Watchdog Timer is used to prevent system lock-up if the software becomes trapped in a deadlock. It is supplied with VDDCORE. It restarts with initial values on processor reset. The watchdog is built around a 12-bit down counter, which is loaded with the value defined in the field WDV of the Mode Register (WDT_MR). The Watchdog Timer uses the slow clock divided by 128 to establish the maximum watchdog period to be 16 seconds (with a typical slow clock of 32.768 kHz). After a processor reset, the value of WDV is 0xFFF, co rresponding to the maximum value of the counter with the external reset generation enabled (field WDRSTEN at 1 after a backup reset). This means that a default watchdog is running at reset, i.e., at power-up. The user ca n either disable the WDT by setting bit WDT_MR.WDDIS or reprogram the WDT to meet the maximum watchdog period the application requires. When setting the WDDIS bit, and while it is set, the fields WDV and WDD must not be modified. If the watchdog is restarted by writing into the Cont rol Register (WDT_CR), WDT_ MR must not be programmed during a period of time of three slow clock periods following the WDT_CR write access. In any case, programming a new value in WDT_MR automatically initiates a restart instruction. WDT_MR can be written only once. Only a processor reset resets it. Writing WDT_MR reloads the timer with the newly programmed mode parameters. In normal operation, the user reloads the watchdog at regular intervals before the timer underflow occurs, by setting bit WDT_CR.WDRSTT. The watchdog counter is then immediately reloaded from WDT_MR and restarted, and the slow clock 128 divider is reset and restarted. WDT_CR is write-protected. As a result, writing WDT_CR without the correct hard-coded key has no effect. If an un derflow does occur, the “wdt_f ault” signal to the Reset Controller is asserted if bit WDT_MR.WDRSTEN is set. Mo reover, the bit WDUNF is set in the Status Register (WDT_SR). To prevent a software deadlock that continuously triggers the watchdog, the reload of the watchdog must occur while the watchdog counter is within a window between 0 and WDD. WDD is defined in WDT_MR. Any attempt to restart the watchdog while the watchdog counter is between WDV and WDD results in a watchdog error, even if the watchdog is disabled. The bit WDT_ SR.WDERR is updated and the “wdt_fault” signal to the Reset Controller is asserted. Note that this feature can be disabled by programming a WDD value greater than or equal to the WDV value. In such a configuration, restarting the Watchdog Timer is permitted in the whole range [0; WDV] and does not generate an error. This is the default configuration on reset (the WDD and WDV values are equal). The status bits WDUNF (Watchdog Underflow) and WDERR (Watchdog Error) trigger an interrupt, provided the bit WDT_MR.WDFIEN is set. The signal “wdt_fault” to the Reset Controller causes a watchdog reset if the WDRSTEN bit is set as already explained in the Reset Controller documentation. In this case, the processor and the Watchdog Timer are reset, and the WDERR and WDUNF flags are reset. If a reset is generated or if WDT_SR is read, the status bits are reset, the interrupt is cleared, and the “wdt_fault” signal to the reset controller is deasserted. Writing WDT_MR reloads and restarts the down counter. While the processor is in debug state or in Sleep mo de, the counter may be stopped depending on the value programmed for the bits WDIDLEHLT and WDDBGHLT in WDT_MR.

185SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 Figure 23-2. Watchdog Behavior WDV WDD WDT_CR.WDRSTT=1 Watchdog Fault Normal behavior Watchdog Error Watchdog Underflow FFF if WDRSTEN is 1 if WDRSTEN is 0 Forbidden Window Permitted Window

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 186

23.5 Watchdog Timer (WDT) User Interface

Table 23-1. Register Mapping Offset Register Name Access Reset 0x00 Control Register WDT_CR Write-only – 0x04 Mode Register WDT_MR Read/Write Once 0x3FFF_2FFF 0x08 Status Register WDT_SR Read-only 0x0000_0000

187SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

23.5.1 Watchdog Timer Control Register

Name: WDT_CR Address: 0x400E1850 Access: Write-only Note: The WDT_CR register values must not be modified within th ree slow clock periods following a restart of the watchdog performed by a write access in WDT_CR. Any modification will cause the watchdog to trigger an end of period earlier than expected.

• WDRSTT: Watchdog Restart 0: No effect. 1: Restarts the watchdog if KEY is written to 0xA5.
• KEY: Password 31 302 92 82 72 62 52 4 KEY 23 22 21 20 19 18 17 16 15 14 1 3 12 11 10 9 8 76543 210 Value Name Description 0xA5 PASSWD Writing any other value in th is field aborts the write operation.

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 188

23.5.2 Watchdog Timer Mode Register

Name: WDT_MR Address: 0x400E1854 Access: Read/Write Once Notes: 1. The first write access prevents any further modification of the value of this register. Read accesses remain possible. 2. The WDT_MR register values must not be modified within th ree slow clock periods following a restart of the watchdog performed by a write access in WDT_CR. Any modification will cause the watchdog to trigger an end of period earlier than expected.

• WDV: Watchdog Counter Value Defines the value loaded in the 12-bit watchdog counter.
• WDFIEN: Watchdog Fault Interrupt Enable 0: A watchdog fault (underflow or error) has no effect on interrupt. 1: A watchdog fault (underflow or error) asserts interrupt.
• WDRSTEN: Watchdog Reset Enable 0: A watchdog fault (underflow or error) has no effect on the resets. 1: A watchdog fault (underflow or error) triggers a watchdog reset.
• WDDIS: Watchdog Disable 0: Enables the Watchdog Timer. 1: Disables the Watchdog Timer. Note: When setting the WDDIS bit, and while it is set, the fields WDV and WDD must not be modified.
• WDD: Watchdog Delta Value Defines the permitted range for reloading the Watchdog Timer. If the Watchdog Timer value is less than or equal to WDD, setting bit WDT_CR.WDRSTT restarts the timer. If the Watchdog Timer value is greater than WDD, setting bit WDT_CR.WDRSTT causes a watchdog error.
• WDDBGHLT: Watchdog Debug Halt 0: The watchdog runs when the processor is in debug state. 1: The watchdog stops when the processor is in debug state. 31 302 92 82 72 62 52 4 – – WDIDLEHLT WDDBGHLT WDD 23 22 21 20 19 18 17 16 WDD 15 14 13 12 11 10 9 8 WDDIS –W D R STEN WDFIEN WDV 76543 210 WDV

189SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

• WDIDLEHLT: Watchdog Idle Halt 0: The watchdog runs when the system is in idle state. 1: The watchdog stops when the system is in idle state.

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 190

23.5.3 Watchdog Timer Status Register

Name: WDT_SR Address: 0x400E1858 Access Read-only

• WDUNF: Watchdog Underflow (cleared on read) 0: No watchdog underflow occurred since the last read of WDT_SR. 1: At least one watchdog underflow occurred since the last read of WDT_SR.
• WDERR: Watchdog Error (cleared on read) 0: No watchdog error occurred since the last read of WDT_SR. 1: At least one watchdog error occurred since the last read of WDT_SR. 31 302 92 82 72 62 52 4 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543 210

191SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 24. Reinforced Safety W atchdog Timer (RSWDT)

24.1 Description

The Reinforced Safety Watchdog Timer (RSWDT) works in parallel with the Watchdog Timer (WDT) to reinforce safe watchdog operations. The RSWDT can be used to reinforce the safety level prov ided by the WDT in order to prevent system lock-up if the software becomes trapped in a deadlock. The RSWDT works in a fully operable mode, independent of the WDT. Its clock source is automatically selected from either the slow RC oscillator clock or main RC oscillator divided clock to get an equiv alent slow RC oscillator clock. If the WDT clock source (for example, the 32 kHz crystal oscillator) fails, the system lock-up is no l onger monitored by the WDT be cause the RSWDT performs the monitoring. Thus, there is no lack of safety irrespec tive of the external operating conditions. The RSWDT shares the same features as the WDT (i.e., a 12-bit down counter that allows a watchdog period of up to 16 seconds with slow clock at 32.768 kHz). It can generate a general reset or a processor reset only. In addition, it can be stopped while the processor is in debug mode or idle mode.

24.2 Embedded Characteristics

 Automatically Selected Reliable RSWDT Clock Source (independent of WDT clock source)  12-bit Key-protected Programmable Counter  Provides Reset or Interrupt Signals to the System  Counter may be Stopped While Processor is in Debug State or Idle Mode

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 192

24.3 Block Diagram

Figure 24-1. Reinforced Safety Watchdog Timer Block Diagram = 0 read RSWDT_SR or reset set reset slow RC clock 12-bit Down Counter Current Value WDV WDRSTT RSWDT_MR RSWDT_CR reload WDUNF reload write RSWDT_MR main RC clock divider main RC frequency Automatic selection [CKGR_MOR.MOSCRCEN = 0 and (WDT_MR.WDDIS or SUPC_MR.XTALSEL = 1)] rswdt_fault (to Reset Controller) (ORed with wdt_fault) WDFIEN rswdt_int (ORed with wdt_int) RSWDT_MR RSWDT_MR WDRSTEN

193SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

24.4 Functional Description

The RSWDT is supplied by VDDCORE. The RSWDT is initia lized with default values on processor reset or on a power-on sequence and is disabled (its default mode) under such conditions. The RSWDT must not be enabled if the WDT is disabled. The main RC oscillator divided cl ock is selected if the main RC oscillator is already enabled by th e application (CKGR_MOR.MOSCRCEN = 1) or if the WDT is driven by the slow RC oscillator. The RSWDT is built around a 12-bit down counter, which is loaded with a slow clock value other than that of the slow clock in the WDT, defined in the WDV (Watchdog Counter Value) field of th e Mode Register (RSWDT_MR). The RSWDT uses the slow clock divided by 128 to establish the maximum watchdog period to be 16 seconds (with a typical slow clock of 32.768 kHz). After a processor reset, the value of WDV is 0xFFF, co rresponding to the maximum value of the counter with the external reset generation enabled (RSWDT _MR.WDRSTEN = 1 after a backup re set). This means that a default watchdog is running at reset, i.e., at power-up. If the watchdog is restarted by writing into the Cont rol Register (RSWDT_CR), the RSWDT_MR must not be programmed during a period of time of three slow clock periods following the RSWDT_CR write access. Programming a new value in the RSWDT_MR automatically initiates a restart instruction. RSWDT_MR can be written only once. Only a processor reset resets it. Writing RSWDT_MR reloads the timer with the newly programmed mode parameters. In normal operation, the user reloads the watchdog at regular intervals before the timer underflow occurs, by setting bit RSWDT_CR.WDRSTT. The watchdog counter is then immediately reloaded from the RSWDT_MR and restarted, and the slow clock 128 divider is reset and re started. The RSWDT_CR is wr ite-protected. As a result, writing RSWDT_CR without the correct hard-coded key has no effect. If an un derflow does occur, the “wdt_fault” signal to the reset controller is asserted if the bit RSWDT_MR.WDRSTEN is set. Moreover, the bit WDUNF (Watchdog Underflow) is set in the Status Register (RSWDT_SR). The status bits WDUNF and WDERR trigger an interrupt, provided the WDFIEN bit is set in the RSWDT_MR. The signal “wdt_fault” to the reset controller causes a Watchdog reset if the WDRSTEN bit is set as explained in the “Reset Controller (RSTC)” section of the product datasheet. In this case, the processor and the RSWDT are reset, and the WDUNF and WDERR flags are reset. If a reset is generated, or if RSWDT_ SR is read, the status bits are reset, the interrupt is cleared, and the “wdt_fault” signal to the reset controller is deasserted. Writing RSWDT_MR reloads and restarts the down counter. The RSWDT is disabled after any power-on sequence. While the processor is in debug state or in idle mode, the counter may be stopped depending on the value programmed for the WDIDLEHLT and WDDBGHLT bits in the RSWDT_MR.

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 194 Figure 24-2. Watchdog Behavior WDV RSWDT_CR.WDRSTT = 1 Watchdog Fault Normal behavior Watchdog Underflow 0xFFF if WDRSTEN is 1 if WDRSTEN is 0

195SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

24.5 Reinforced Safety Watchdog Timer (RSWDT) User Interface

Table 24-1. Register Mapping Offset Register Name Access Reset 0x00 Control Register RSWDT_CR Write-only – 0x04 Mode Register RSWDT_MR Read-write Once 0x3FFF_AFFF 0x08 Status Register RSWDT_SR Read-only 0x0000_0000

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 196

24.5.1 Reinforced Safety Watchdog Timer Control Register

Name: RSWDT_CR Address: 0x400E1900 Access: Write-only

• WDRSTT: Watchdog Restart 0: No effect. 1: Restarts the watchdog.
• KEY: Password 31 302 92 82 72 62 52 4 KEY 23 22 21 20 19 18 17 16 15 14 1 3 12 11 10 9 8 76543 210 Value Name Description 0xC4 PASSWD Writing any other value in this field aborts the write operation.

197SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

24.5.2 Reinforced Safety Watchdog Timer Mode Register

Name: RSWDT_MR Address: 0x400E1904 Access: Read-write Once Note: The first write access prevents any further modification of the value of this register; read accesses remain possible. Note: The WDV value must not be modified within three slow clock periods following a restart of the watchdog performed by means of a write access in the RSWDT_CR, else the watchdog may trigger an end of period earlier than expected.

• WDV: Watchdog Counter Value Defines the value loaded in the 12-bit watchdog counter.
• WDFIEN: Watchdog Fault Interrupt Enable 0: A Watchdog fault (underflow or error) has no effect on interrupt. 1: A Watchdog fault (underflow or error) asserts interrupt.
• WDRSTEN: Watchdog Reset Enable 0: A Watchdog fault (underflow or error) has no effect on the resets. 1: A Watchdog fault (underflow or error) triggers a watchdog reset.
• WDDIS: Watchdog Disable 0: Enables the RSWDT. 1: Disables the RSWDT.
• ALLONES: Must Always Be Written with 0xFFF
• WDDBGHLT: Watchdog Debug Halt 0: The RSWDT runs when the processor is in debug state. 1: The RSWDT stops when the processor is in debug state.
• WDIDLEHLT: Watchdog Idle Halt 0: The RSWDT runs when the system is in idle mode. 1: The RSWDT stops when the system is in idle state. 31 302 92 82 72 62 52 4 – – WDIDLEHLT WDDBGHLT ALLONES 23 22 21 20 19 18 17 16 ALLONES 15 14 13 12 11 10 9 8 WDDIS –W D R STEN WDFIEN WDV 76543 210 WDV

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 198

24.5.3 Reinforced Safety Watchdog Timer Status Register

Name: RSWDT_SR Address: 0x400E1908 Access: Read-only

• WDUNF: Watchdog Underflow 0: No watchdog underflow occurred since the last read of RSWDT_SR. 1: At least one watchdog underflow occurred since the last read of RSWDT_SR. 31 302 92 82 72 62 52 4 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543 210

199SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 25. Reset Controller (RSTC)

25.1 Description

The Reset Controller (RSTC), based on power-on reset cell s, handles all the resets of the system without any external components. It reports which reset occurred last. The Reset Controller also drives independently or si multaneously the ex ternal reset and the peripheral and processor resets.

25.2 Embedded Characteristics

 Management of All System Resets, Including ̶ External Devices through the NRST Pin ̶ Processor Reset  Based on Embedded Power-on Cell  Reset Source Status ̶ Status of the Last Reset ̶ Either Software Reset, User Reset, Watchdog Reset  External Reset Signal Shaping

25.3 Block Diagram

Figure 25-1. Reset Controller Block Diagram NRST proc_nreset wd_fault periph_nreset SLCK Reset State Manager Reset Controller rstc_irq NRST Manager exter_nresetnrst_out core_backup_reset WDRPROC user_reset vddcore_nreset

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 200

25.4 Functional Description

25.4.1 Reset Controller Overview

The Reset Controller is made up of an NRST manager and a reset state manager. It runs at slow clock and generates the following reset signals:  proc_nreset: processor reset line (also resets the Watchdog Timer)  periph_nreset: affects the whole set of embedded peripherals  nrst_out: drives the NRST pin These reset signals are asserted by the Reset Controller, either on events generated by peripherals, events on NRST pin, or on software action. The reset state manager controls the generation of reset signals and provides a signal to the NRST manager when an assertion of the NRST pin is required. The NRST manager shapes the NRST assertion during a programmable time, thus controlling external device resets. The Reset Controller Mode Register (RSTC_MR), used to configure the Reset Controller, is powered with VDDIO, so that its configuration is saved as long as VDDIO is on.

25.4.2 NRST Manager

The NRST manager samples the NRST input pin and drives this pin low when required by the reset state manager. Figure 25-2 shows the block diagram of the NRST manager. Figure 25-2. NRST Manager

25.4.2.1 NRST Signal or Interrupt

The NRST manager samples the NRST pin at slow clock speed. When the line is detected low, a User Reset is reported to the reset state manager. However, the NRST manager can be programmed to not trigger a reset when an assertion of NRST occurs. Writing a 0 to the URSTEN bit in the RSTC_MR disables the User Reset trigger. The level of the pin NRST can be read at any time in the bit NRSTL (NRST level) in the Reset Controller Status Register (RSTC_SR). As soon as the NRST pin is asserted, bit URSTS in the RSTC_SR is set. This bit is cleared only when the RSTC_SR is read. The Reset Controller can also be programmed to generate an interrupt instead of generating a reset. To do so, set the URSTIEN bit in the RSTC_MR. External Reset Timer URSTS URSTEN ERSTL exter_nreset URSTIEN RSTC_MR RSTC_MR RSTC_MR RSTC_SR NRSTL nrst_out NRST rstc_irq Other interrupt sources user_reset

201SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

25.4.2.2 NRST External Reset Control

The reset state manager asserts the signal exter_nreset to assert the NRST pin. When this occurs, the “nrst_out” signal is driven low by the NRST manager for a time programmed by field ERSTL in the RSTC_MR. This assertion duration, named External Reset Length, lasts 2 (ERSTL+1) slow clock cycles. This gi ves the approximate duration of an assertion between 60 µs and 2 sec onds. Note that ERSTL at 0 defines a two-cycle duration for the NRST pulse. This feature allows the Reset Controller to shape the NRST pin level, and thus to guarantee that the NRST line is driven low for a time compliant with potential external devices connected on the system reset. RSTC_MR is backed up, making it possible to use the ERSTL field to shape the system power-up reset for devices requiring a longer startup time than that of the slow clock oscillator.

25.4.3 Reset States

The reset state manager handles the different reset sources and generates the internal reset signals. It reports the reset status in field RSTTYP of the Status Register (RSTC_SR). The upd ate of RSTC_SR.RSTTYP is performed when the processor reset is released.

25.4.3.1 General Reset

A general reset occurs when a VDDIO power-on-reset is detected, a brownout or a voltage regulation loss is detected by the Supply Controller. The vddcore_nreset signal is asserted by the Supply Controller when a general reset occurs. All the reset signals are released and field RSTC_SR.RSTTYP reports a general reset. As the RSTC_MR is reset, the NRST line rises two cycles after the vddcore_nreset, as ERSTL defaults at value 0x0. Figure 25-3 shows how the general reset affects the reset signals. Figure 25-3. General Reset State SLCK periph_nreset proc_nreset NRST (nrst_out) External Reset Length = 2 cycles MCK Processor Startup = 2 cycles vddio_nreset Any Freq. RSTTYP XXX 0x0 = General Reset XXX

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 202

25.4.3.2 Backup Reset

A backup reset occurs when the chip exits from Backup mode. While exiting Backup mode, the vddcore_nreset signal is asserted by the Supply Controller. Field RSTC_SR.RSTTYP is updated to report a backup reset.

25.4.3.3 Watchdog Reset

The watchdog reset is entered when a watchdog fault occurs. This reset lasts three slow clock cycles. When in watchdog reset, assertion of the reset signals depends on the WDRPROC bit in the WDT_MR:  If WDRPROC = 0, the processor reset and the peripheral reset are asserted. The NRST line is also asserted, depending on how field RSTC_MR.ERSTL is programmed. However, the resulting low level on NRST does not result in a user reset state.  If WDRPROC = 1, only the processor reset is asserted. The Watchdog Timer is reset by the proc_nreset signal. As the watchdog fault always causes a processor reset if WDRSTEN in the WDT_MR is set, the Watchdog Timer is always reset after a watchdog reset, and the Watchdog is enabled by default and with a period set to a maximum. When bit WDT_MR.WDRSTEN is reset, the watchdog fault has no impact on the Reset Controller. Figure 25-4. Watchdog Reset Only if WDRPROC = 0 SLCK periph_nreset proc_nreset wd_fault NRST (nrst_out) EXTERNAL RESET LENGTH 8 cycles (ERSTL=2) MCK Processor Startup = 2 cycles Any Freq. RSTTYP Any XXX 0x2 = Watchdog Reset

203SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

25.4.3.4 Software Reset

The Reset Controller offers commands to assert the di fferent reset signals. These commands are performed by writing the Control Register (RSTC_CR) with the following bits at 1:  RSTC_CR.PROCRST: Writing a 1 to PROCRST resets the processor and all the embedded peripherals, including the memory system and, in particular, the Remap Command.  RSTC_CR.EXTRST: Writing a 1 to EXTRST asserts low the NRST pin during a time defined by the field RSTC_MR.ERSTL. The software reset is entered if at least one of these bits is set by the software. All these commands can be performed independently or simultaneously. The software reset lasts three slow clock cycles. The internal reset signals are asserted as soon as the register write is performed. This is detected on the Master Clock (MCK). They are released when the software reset has ended, i.e., synchronously to SLCK. If EXTRST is set, the nrst_out si gnal is asserted depending on the c onfiguration of field RSTC_MR.ERSTL. However, the resulting falling edge on NRST does not lead to a user reset. If and only if the PROCRST bit is set, the Reset Controller reports the software status in field RSTC_SR.RSTTYP. Other software resets are not reported in RSTTYP. As soon as a software operation is detected, the bit S RCMP (Software Reset Command in Progress) is set in the RSTC_SR. SRCMP is cleared at the end of the software reset. No other software reset can be performed while the SRCMP bit is set, and writing any value in the RSTC_CR has no effect. Figure 25-5. Software Reset SLCK periph_nreset if PERRST=1 proc_nreset if PROCRST=1 Write RSTC_CR NRST (nrst_out) if EXTRST=1 EXTERNAL RESET LENGTH 8 cycles (ERSTL=2) MCK Processor Startup = 2 cycles Any Freq. RSTTYP Any XXX 0x3 = Software Reset Resynch. 1 cycle SRCMP in RSTC_SR

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 204

25.4.3.5 User Reset

The user reset is entered when a low level is detected on the NRST pin and bit URSTEN in the RSTC_MR is at 1. The NRST input signal is resynchronized with SLCK to insure proper behavior of the system. The user reset is entered as soon as a low level is detected on NRST. The processor reset and the peripheral reset are asserted. The user reset ends when NRST rises, after a two-cy cle resynchronization time and a three-cycle processor startup. The processor clock is re-enabled as soon as NRST is confirmed high. When the processor reset signal is released, field RSTC_SR.RSTTYP is load ed with the value 0x4, indicating a user reset. The NRST manager guarantees that the NRST line is asse rted for External Reset Length slow clock cycles, as programmed in field RSTC_MR.ERSTL. However, if NRST does not rise after External Reset Length because it is driven low externally, the internal reset lines remain asserted until NRST actually rises. Figure 25-6. User Reset State SLCK periph_nreset proc_nreset NRST NRST (nrst_out) >= EXTERNAL RESET LENGTH MCK Processor Startup = 2 cycles Any Freq. Resynch. 2 cycles RSTTYP Any XXX Resynch. 2 cycles 0x4 = User Reset

205SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

25.4.4 Reset State Priorities

The reset state manager manages the priorities among the different reset sources. The resets are listed in order of priority as follows: 1. Gener al reset 2. Backup reset 3. Watchdog reset 4. Software reset 5. User reset Particular cases are listed below:  When in user reset: ̶ A watchdog event is impossible because the Watchdog Timer is being reset by the proc_nreset signal. ̶ A software reset is impossible, since the processor reset is being activated.  When in software reset: ̶ A watchdog event has priority over the current state. ̶ The NRST has no effect.  When in watchdog reset: ̶ The processor reset is active and so a software reset cannot be programmed. ̶ A user reset cannot be entered.

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 206

25.5 Reset Controller (RSTC) User Interface

Note: 1. This value assumes that a general reset has been performe d, subject to change if other types of reset are generated. Table 25-1. Register Mapping Offset Register Name Access Reset 0x00 Control Register RSTC_CR Write-only – 0x04 Status Register RSTC_SR Read-only 0x0000_0000 (1) 0x08 Mode Register RSTC_MR Read/Write 0x0000_0001

207SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

25.5.1 Reset Controller Control Register

Name: RSTC_CR Address: 0x400E1800 Access: Write-only

• PROCRST: Processor Reset 0: No effect 1: If KEY is correct, resets the processor
• EXTRST: External Reset 0: No effect 1: If KEY is correct, asserts the NRST pin
• KEY: System Reset Key 31 30 29 28 27 26 25 24 KEY 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 Value Name Description 0xA5 PASSWD Writing any other value in this field aborts the write operation.

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 208

25.5.2 Reset Controller Status Register

Name: RSTC_SR Address: 0x400E1804 Access: Read-only

• URSTS: User Reset Status A high-to-low transition of the NRST pin sets the URSTS bit. This transition is also detected on the MCK rising edge. If the user reset is disabled (URSTEN = 0 in RSTC_MR) and if the interruption is enabled by the URSTIEN bit in the RSTC_MR, the URSTS bit triggers an interrupt. Reading the RSTC_SR resets the URSTS bit and clears the interrupt. 0: No high-to-low edge on NRST happened since the last read of RSTC_SR. 1: At least one high-to-low transition of NRST has been detected since the last read of RSTC_SR.
• RSTTYP: Reset Type This field reports the cause of the last processor reset. Reading this RSTC_SR does not reset this field.
• NRSTL: NRST Pin Level This bit registers the NRST pin level sampled on each Master Clock (MCK) rising edge.
• SRCMP: Software Reset Command in Progress When set, this bit indicates that a software reset command is in progress and that no further software reset should be per- formed until the end of the current one. This bit is automatically cleared at the end of the current software reset. 0: No software command is being performed by the Reset Controller. The Reset Controller is ready for a software command. 1: A software reset command is being performed by the Reset Controller. The Reset Controller is busy. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 Value Name Description

0 GENERAL_RST First power-up reset

1 BACKUP_RST Return from Backup Mode

2 WDT_RST Watchdog fault occurred

3 SOFT_RST Processor reset required by the software

4 USER_RST NRST pin detected low

5– Reserved 6– Reserved 7– Reserved

209SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

25.5.3 Reset Controller Mode Register

Name: RSTC_MR Address: 0x400E1808 Access: Read/Write This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode Register (SYSC_WPMR).

• URSTEN: User Reset Enable 0: The detection of a low level on the NRST pin does not generate a user reset. 1: The detection of a low level on the NRST pin triggers a user reset.
• URSTIEN: User Reset Interrupt Enable 0: USRTS bit in RSTC_SR at 1 has no effect on rstc_irq. 1: USRTS bit in RSTC_SR at 1 asserts rstc_irq if URSTEN = 0.
• ERSTL: External Reset Length This field defines the external reset length. The external reset is asserted during a time of 2(ERSTL+1) slow clock cycles. This allows assertion duration to be programmed between 60 µs and 2 seconds. Note that synchronization cycles must also be considered when calculating the actual reset length as previously described.
• KEY: Write Access Password 31 30 29 28 27 26 25 24 KEY 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 –––– ERSTL 76543210 Value Name Description 0xA5 PASSWD Writing any other value in this field aborts the write operation. Always reads as 0.

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 210 26. Real-time Clock (RTC)

26.1 Description

The Real-time Clock (RTC) peripheral is designed for very low power consumption. For optimal functionality, the RTC requires an accurate external 32.768 kHz clock, which can be provided by a crystal oscillator. It combines a complete time-of-day clock with alarm and a Gregorian or Persian calendar, complemented by a programmable periodic interrupt. The alarm and calendar registers are accessed by a 32-bit data bus. The time and calendar values are coded in binary-coded decimal (BCD) format. The time format can be 24-hour mode or 12-hour mode with an AM/PM indicator. Updating time and calendar fields and configuring the alarm fields are performed by a parallel capture on the 32-bit data bus. An entry control is performed to avoid loading registers with incompatible BCD format data or with an incompatible date according to the current month/year/century. A clock divider calibration circuitry can be used to compensate for crystal oscillator frequency variations. An RTC output can be programmed to generate several waveforms, including a prescaled clock derived from 32.768 kHz.

26.2 Embedded Characteristics

 Full Asynchronous Design for Ultra Low Power Consumption  Gregorian and Persian Modes Supported  Programmable Periodic Interrupt  Safety/security Features: ̶ Valid Time and Date Programmation Check ̶ On-The-Fly Time and Date Validity Check  Counters Calibration Circuitry to Compensate for Crystal Oscillator Variations  Waveform Generation  Register Write Protection

211SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

26.3 Block Diagram

Figure 26-1. Real-time Clock Block Diagram

26.4 Product Dependencies

26.4.1 Power Management

The Real-time Clock is continuously clocked at 32.768 kHz. The Power Management Controller has no effect on RTC behavior.

26.4.2 Interrupt

Within the System Controller, the RTC interrupt is OR-wired with all the other module interrupts. Only one System Controller interrupt line is connected on one of the internal sources of the interrupt controller. RTC interrupt requires the interrupt controller to be programmed first. When a System Controller interrupt occurs, the service routine must first determine the cause of the interrupt. This is done by reading each status register of the System Controller peripherals successively. User Interface

32768 Divider

TimeSlow Clock: SLCK System Bus Date RTC InterruptEntry Control Interrupt Control Clock Calibration RTCOUT0 RTCOUT1 Wave Generator Alarm Table 26-1. Peripheral IDs Instance ID RTC 2

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 212

26.5 Functional Description

The RTC provides a full binary-coded decimal (BCD) clock that includes century (19/20), year (with leap years), month, date, day, hours, minutes and seconds reported in RTC Time Register (RTC_TIMR) and RTC Calendar Register (RTC_CALR). The valid year range is up to 2099 in Gregorian mode (or 1300 to 1499 in Persian mode). The RTC can operate in 24-hour mode or in 12-hour mode with an AM/PM indicator. Corrections for leap years are included (all years divisible by 4 being leap years except 1900). This is correct up to the year 2099. The RTC can generate configurable waveforms on RTCOUT0/1 outputs.

26.5.1 Reference Clock

The reference clock is the Slow Clock (SLCK). It can be driven internally or by an external 32.768 kHz crystal. During low power modes of the processor, the oscillator runs and power co nsumption is critical. The crystal selection has to take into account the current consumption for power saving and the frequency drift due to temperature effect on the circuit for time accuracy.

26.5.2 Timing

The RTC is updated in real time at one-second intervals in Normal mode for the counters of seconds, at one- minute intervals for the counter of minutes and so on. Due to the asynchronous operation of the RTC with respect to the rest of the chip, to be certain that the value read in the RTC registers (century, year, month, date, day, hours, minutes, seconds) are valid and stable, it is necessary to read these registers twice. If the data is the same both times, then it is valid. Therefore, a minimum of two and a maximum of three accesses are required.

26.5.3 Alarm

The RTC has five programmable fields: month, date, hours, minutes and seconds. Each of these fields can be enabled or disabled to match the alarm condition:  If all the fields are enabled, an alarm flag is generated (the corresponding flag is asserted and an interrupt generated if enabled) at a given month, date, hour/minute/second.  If only the “seconds” field is enabled, then an alarm is generated every minute. Depending on the combination of fields enabled, a large num ber of possibilities are available to the user ranging from minutes to 365/366 days. Hour, minute and second matching alarm (SECEN, MI NEN, HOUREN) can be enabled independently of SEC, MIN, HOUR fields. Note: To change one of the SEC, MIN, HOUR, DATE, MONTH fields, it is recommended to disable the field before changing the value and then re-enable it after the change has been made. This requires up to three accesses to the RTC_TIMALR or RTC_CALALR. The first access clears the enable corresponding to the field to change (SECEN, MINEN, HOUREN, DATEEN, MTHEN). If the field is already cleared, this access is not required. The second access performs the change of the value (SEC, MIN, HOUR, DATE, MONTH). The third access is required to re-enable the field by writing 1 in SECEN, MINEN, HOUREn, DATEEN, MTHEN fields.

26.5.4 Error Checking when Programming

Verification on user interface data is performed when accessing the cent ury, year, month, date, day, hours, minutes, seconds and alarms. A check is performed on illegal BCD entries such as illegal date of the month with regard to the year and century configured.

213SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 If one of the time fields is not correct, the data is not loaded into the register/counter and a flag is set in the validity register. The user can not reset this flag. It is reset as soon as an acceptable value is programmed. This avoids any further side effects in the hardware. The same procedure is followed for the alarm. The following checks are performed: 1. Century (check if it i s in range 19–20 or 13–14 in Persian mode) 2. Year (BCD entry check) 3. Date (check range 01–31) 4. Month (check if it is in BCD rang e 01–12, check validity regarding “date”) 5. Day (check range 1–7) 6. Hour (BCD checks: in 24-hour mode, check range 00–23 and check that AM/PM flag is not set if RTC is set in 24-hour mode; in 12-hour mode check range 01–12) 7. Minute (check BCD and range 00–59) 8. Second (check BCD and range 00–59) Note: If the 12-hour mode is selected by means of the RTC Mode Register (RTC_MR), a 12-hour value can be programmed and the returned value on RTC_TIMR will be the corresponding 24-hour value. The entry control checks the value of the AM/PM indicator (bit 22 of RTC_TIMR) to determine the range to be checked.

26.5.5 RTC Internal Free Running Counter Error Checking

To improve the reliability and security of the RTC, a permanent check is performed on the internal free running counters to report non-BCD or invalid date/time values. An error is reported by TDERR bit in the status register (RTC_SR) if an incorrect value has been detected. The flag can be cleared by setting the TDERRCLR bit in the Status Clear Command Register (RTC_SCCR). Anyway the TDERR error flag will be set again if the sour ce of the error has not been cleared before clearing the TDERR flag. The clearing of the source of such error can be done by reprogramming a correct value on RTC_CALR and/or RTC_TIMR. The RTC internal free running counters may automatically clear the source of TDERR due to their roll-over (i.e., every 10 seconds for SECONDS[3:0] field in RTC_TIMR). In this case the TDERR is held high until a clear command is asserted by TDERRCLR bit in RTC_SCCR.

26.5.6 Updating Time/Calendar

To update any of the time/calendar fields, the user must first stop the RTC by setting the corresponding field in the Control Register (RTC_CR). Bit UPDTIM must be set to update time fields (hour, minute, second) and bit UPDCAL must be set to update calendar fields (century, year, month, date, day). The ACKUPD bit is automatically set within a second af ter setting the UPDTIM and/or UPDCAL bit (meaning one second is the maximum duration of the polling or wait for interrupt period). Once ACKUPD is set, it is mandatory to clear this flag by writing the corresponding bit in th e RTC_SCCR, after which the user can write to the Time Register, the Calendar Register, or both. Once the update is finished, the user must clear UPDTIM and/or UPDCAL in the RTC_CR. When entering the programming mode of the calendar fiel ds, the time fields remain enabled. When entering the programming mode of the time fields, both time and calendar fields are stopped. This is due to the location of the calendar logic circuity (downstream fo r low-power considerations). It is highly recommended to prepare all the fields to be updated before entering programming mode. In successive update operations, the user must wait at least one second after resetting the UPDTIM/UPDCAL bit in the RTC_CR before setting these bits again. This is done by waiting for the SEC flag in the RTC_ SR before setting UPDTIM/UPDCAL bit. After clearing UPDTIM/UPDCAL, the SEC flag must also be cleared.

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 214 Figure 26-2. Update Sequence Prepare Time or Calendar Fields Set UPDTIM and/or UPDCAL bit(s) in RTC_CR Read RTC_SR ACKUPD = 1 ? Clear ACKUPD bit in RTC_SCCR Update Time and/or Calendar values in RTC_TIMR/RTC_CALR Clear UPDTIM and/or UPDCAL bit in RTC_CR No Yes Begin End Polling or IRQ (if enabled)

215SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

26.5.7 RTC Accurate Clock Calibration

The crystal oscillator that drives the RTC may not be as accurate as expected mainly due to temperature variation. The RTC is equipped with circuitry able to correct slow clock crystal drift. To compensate for possible temperature variations over time, this accurate clock calibration circuitry can be programmed on-the-fly and also programmed during app lication manufacturing, in order to correct the crystal frequency accuracy at room temperature (20–25°C). The typical clock drift range at room temperature is ±20 ppm. In the device operating temperature range, the 32.768 kHz crystal oscillator clock inaccuracy can be up to -200 ppm. The RTC clock calibration circuitry allows positive or negative correction in a range of 1.5 ppm to 1950 ppm. The calibration circuitry is fully digital. Thus, the co nfigured correction is independent of temperature, voltage, process, etc., and no additional measurement is required to check that the correction is effective. If the correction value configured in the calibration circuitry results from an accurate crystal frequency measure, the remaining accuracy is bounded by the values listed below:  Below 1 ppm, for an initial crystal drift between 1.5 ppm up to 20 ppm, and from 30 ppm to 90 ppm  Below 2 ppm, for an initial crystal drift between 20 ppm up to 30 ppm, and from 90 ppm to 130 ppm  Below 5 ppm, for an initial crystal drift between 130 ppm up to 200 ppm The calibration circuitry does not modify the 32.768 kHz cr ystal oscillator clock frequency but it acts by slightly modifying the 1 Hz clock period from time to ti me. The correction event occurs every 1 + [(20 - (19 x HIGHPPM)) x CORRECTION] seconds. When the pe riod is modified, depending on the sign of the correction, the 1 Hz clock period increases or r educes by around 4 ms. Dependi ng on the CORRECTION, NEGPPM and HIGHPPM values configured in RTC_MR, the period interval between two correction events differs. Figure 26-3. Calibration Circuitry 32.768 kHz Oscillator Other Logic RTC Time/Calendar1Hz CORRECTION, HIGHPPMIntegrator Comparator Divider by 32768 Add 32.768 kHz NEGPPM Suppress

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 216 Figure 26-4. Calibration Circuitry Waveforms The inaccuracy of a crystal oscillator at typical room te mperature (±20 ppm at 20–25 °C) can be compensated if a reference clock/signal is used to measure such inaccuracy. This kind of calibration operation can be set up during the final product manufacturing by means of measurement equipment embedding such a reference clock. The correction of value must be programmed into the (RTC_MR) , and this value is kept as long as the circuitry is powered (backup area). Removing the backup power supply cancels this calibration. This room temperature calibration can be further processed by means of the networking capability of the target application. Time Monotonic 1 Hz Counter value 32.768 kHz -50 ppm 32.768 kHz +50 ppm Crystal frequency remains unadjusted Internal 1 Hz clock is adjusted Phase adjustment (~4 ms) User configurable period (integer multiple of 1s or 20s) Time -50 ppm -25 ppm -50 ppm correction period -25 ppm correction period Nominal 32.768 kHz Crystal clock Internally divided clock (256 Hz) Internally divided clock (128 Hz) Clock pulse periodically suppressed when correction period elapses 128 Hz clock edge delayed by 3.906 ms when correction period elapses Internally divided clock (256 Hz) Internally divided clock (128 Hz) Internally divided clock (64 Hz) 128 Hz clock edge delayed by 3.906 ms when correction period elapses Clock edge periodically added when correction period elapses 1.000 second 1.003906 second 1.000 second 0.996094 second NEGATIVE CORRECTIONPOSITIVE CORRECTION

217SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 To ease the comparison of the inherent crystal accuracy with the reference clock/sig nal during manufacturing, an internal prescaled 32.768 kHz clock derivative signal can be assigned to drive RTC output. To accommodate the measure, several clock frequencies can be selected among 1 Hz, 32 Hz, 64 Hz, 512 Hz. The clock calibration correction drives the internal RTC counters but can also be observed in the RTC output when one of the following three frequencies 1 Hz, 32 Hz or 64 Hz is configured. The correction is not visible in the RTC output if 512 Hz frequency is configured. In any event, this adjustment does not take into account the temperature variation. The frequency drift (up to -200 ppm) due to temperature variation can be compensated using a reference time if the application can access such a reference. If a refe rence time cannot be used, a temperature sensor can be placed close to the crystal oscillator in order to get the oper ating temperature of the crystal oscillator. Once obtained, the temperature may be converted using a lookup table (describing the accuracy/temperature curve of the crystal oscillator used) and RTC_MR configured accordingly. The calibration can be performed on-the-fly. This adjustment method is not based on a measurement of the crystal frequency/drift and therefore can be improved by means of the networking capability of the target application. If no crystal frequency adjustment has been done during manufa cturing, it is still poss ible to do it. In the case where a reference time of the day can be obtained through LAN/WAN network, it is possible to calculate the drift of the application crystal oscillator by comparing the values read on RTC Time Register (RTC_TIMR) and programming the HIGHPPM and CORRECTION fields on RTC_MR according to the difference measured between the reference time and those of RTC_TIMR.

26.5.8 Waveform Generation

Waveforms can be generated by the RTC in order to take advantage of the RTC inherent prescalers while the RTC is the only powered circuitry (Low-power mode of operation, Backup mode) or in any active mode. Going into Backup or Low-power operating modes does not affect the waveform generation outputs. The RTC outputs (RTCOUT0 and RTCOUT1) have a source driver selected among seven possibilities. The first selection choice sticks the associated output at 0 (This is the reset value and it can be used at any time to disable the waveform generation). Selection choices 1 to 4 respectively select 1 Hz, 32 Hz, 64 Hz and 512 Hz. 32 Hz or 64 Hz can drive, for example, a TN LCD bac kplane signal while 1 Hz can be used to drive a blinking character like “:” for basic time display (hour, minute) on TN LCDs. Selection choice 5 provides a toggling signal when the RTC alarm is reached. Selection choice 6 provides a copy of the alarm flag, so the associated output is set high (logical 1) when an alarm occurs and immediately cleared when software clears the alarm interrupt source. Selection choice 7 provides a 1 Hz periodic high pulse of 15 µs duration that can be used to drive external devices for power consumption reduction or any other purpose. PIO lines associated to RTC outputs are automatical ly selecting these waveforms as soon as RTC_MR corresponding fields OUT0 and OUT1 differ from 0.

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 218 Figure 26-5. Waveform Generation RTCOUT1 ‘0’ 1 Hz 32 Hz 64 Hz 512 Hz toggle_alarm flag_alarm pulse RTC_MR(OUT1) RTCOUT0 ‘0’ 1 Hz 32 Hz 64 Hz 512 Hz toggle_alarm flag_alarm pulse RTC_MR(OUT0) flag_alarm alarm match event 1 RTC_SCCR(ALRCLR) alarm match event 2 RTC_SCCR(ALRCLR) toggle_alarm pulse Tperiod Tperiod Thigh

219SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

26.6 Real-time Clock (RTC) User Interface

Note: If an offset is not listed in the table it must be considered as reserved. Table 26-2. Register Mapping Offset Register Name Access Reset 0x00 Control Register RTC_CR Read/Write 0x00000000 0x04 Mode Register RTC_MR Read/Write 0x00000000 0x08 Time Register RTC_TIMR Read/Write 0x00000000 0x0C Calendar Register RTC_CALR Read/Write 0x01E11220 0x10 Time Alarm Register RTC_TIMALR Read/Write 0x00000000 0x14 Calendar Alarm Register RTC_CALALR Read/Write 0x01010000 0x18 Status Register RTC_SR Read-only 0x00000000 0x1C Status Clear Command R egister RTC_SCCR Write-only – 0x20 Interrupt Enable Register RTC_IER Write-only – 0x24 Interrupt Disable Register RTC_IDR Write-only – 0x28 Interrupt Mask Register RTC_IMR Read-only 0x00000000 0x2C Valid Entry Register RTC_VER Read-only 0x00000000 0x30–0xC8 Reserved – – – 0xCC Reserved – – – 0xD0 Reserved – – – 0xD4–0xE0 Reserved – – – 0xE4 Write Protection Mode Register RTC_WPMR Read/Write 0x00000000 0xE8–0xF8 Reserved – – – 0xFC Reserved – – –

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 220

26.6.1 RTC Control Register

Name: RTC_CR Address: 0x400E1860 Access: Read/Write This register can only be written if the WPEN bit is cleared in the RTC Write Protection Mode Register.

• UPDTIM: Update Request Time Register 0: No effect or, if UPDTIM has been previously written to 1, stops the update procedure. 1: Stops the RTC time counting. Time counting consists of second, minute and hour counters. Time counters can be programmed once this bit is set and acknowledged by the bit ACKUPD of the RTC_SR.
• UPDCAL: Update Reque st Calendar Register 0: No effect or, if UPDCAL has been previously written to 1, stops the update procedure. 1: Stops the RTC calendar counting. Calendar counting consists of day, date, month, year and century counters. Calendar counters can be programmed once this bit is set and acknowledged by the bit ACKUPD of the RTC_SR.
• TIMEVSEL: Time Event Selection The event that generates the flag TIMEV in RTC_SR depends on the value of TIMEVSEL.
• CALEVSEL: Calendar Event Selection The event that generates the flag CALEV in RTC_SR depends on the value of CALEVSEL 31 302 92 82 72 62 52 4 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543 210 Value Name Description

0 MINUTE Minute change

1 HOUR Hour change

2 MIDNIGHT Every day at midnight

3 NOON Every day at noon

0 WEEK Week change (every Monday at time 00:00:00)

1 MONTH Month change (every 01 of each month at time 00:00:00)

2 YEAR Year change (every January 1 at time 00:00:00)

221SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

26.6.2 RTC Mode Register

Name: RTC_MR Address: 0x400E1864 Access: Read/Write This register can only be written if the WPEN bit is cleared in the RTC Write Protection Mode Register.

• HRMOD: 12-/24-hour Mode 0: 24-hour mode is selected. 1: 12-hour mode is selected.
• PERSIAN: PERSIAN Calendar 0: Gregorian calendar. 1: Persian calendar.
• NEGPPM: NEGative PPM Correction 0: Positive correction (the divider will be slightly higher than 32768). 1: Negative correction (the divider will be slightly lower than 32768). Refer to CORRECTION and HIGHPPM field descriptions. Note: NEGPPM must be cleared to corre ct a crystal slower than 32.768 kHz.
• CORRECTION: Slow Clock Correction 0: No correction 1–127: The slow clock will be corrected according to the formula given in HIGHPPM description.
• HIGHPPM: HIGH PPM Correction 0: Lower range ppm correction with accurate correction. 1: Higher range ppm correction with accurate correction. If the absolute value of the correction to be applied is lower than 30 ppm, it is recommended to clear HIGHPPM. HIGHPPM set to 1 is recommended for 30 ppm correction and above. Formula: If HIGHPPM = 0, then the clock frequenc y correction range is from 1.5 ppm up to 98 ppm. The RTC accuracy is less than 1 ppm for a range correction from 1.5 ppm up to 30 ppm. The correction field must be programmed according to the required correction in ppm; the formula is as follows: 31 302 92 82 72 62 52 4 – – TPERIOD – THIGH 23 22 21 20 19 18 17 16 –O UT1–O UT0 15 14 13 12 11 10 9 8 HIGHPPM CORRECTION 76543 210 – – – NEGPPM – – PERSIAN HRMOD CORRECTION 3906

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 222 The value obtained must be rounded to the nearest integer prior to being programmed into CORRECTION field. If HIGHPPM = 1, then the clock frequency correction range is from 30.5 ppm up to 1950 ppm. The RTC accuracy is less than 1 ppm for a range correction from 30.5 ppm up to 90 ppm. The correction field must be programmed according to the required correction in ppm; the formula is as follows: The value obtained must be rounded to the nearest integer prior to be programmed into CORRECTION field. If NEGPPM is set to 1, the ppm correction is negative (used to correct crystals that are faster than the nominal 32.768 kHz).

• OUT0: RTCOUT0 OutputSource Selection
• OUT1: RTCOUT1 Output Source Selection
• THIGH: High Duration of the Output Pulse Value Name Description

0 NO_WAVE No waveform, stuck at ‘0’

1 FREQ1HZ 1 Hz square wave

2 FREQ32HZ 32 Hz square wave

3 FREQ64HZ 64 Hz square wave

4 FREQ512HZ 512 Hz square wave

5 ALARM_TOGGLE Output toggles when alarm flag rises

6 ALARM_FLAG Output is a copy of the alarm flag

7 PROG_PULSE Duty cycle programmable pulse

0 H_31MS 31.2 ms 1 H_16MS 15.6 ms 2 H_4MS 3.91 ms

3 H_976US 976 µs

4 H_488US 488 µs

223SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

• TPERIOD: Period of the Output Pulse

5 H_122US 122 µs

6 H_30US 30.5 µs 7 H_15US 15.2 µs Value Name Description

0 P_1S 1 second

1 P_500MS 500 ms

2 P_250MS 250 ms

3 P_125MS 125 ms

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 224

26.6.3 RTC Time Register

Name: RTC_TIMR Address: 0x400E1868 Access: Read/Write

• SEC: Current Second The range that can be set is 0–59 (BCD). The lowest four bits encode the units. The higher bits encode the tens.
• MIN: Current Minute The range that can be set is 0–59 (BCD). The lowest four bits encode the units. The higher bits encode the tens.
• HOUR: Current Hour The range that can be set is 1–12 (BCD) in 12-hour mode or 0–23 (BCD) in 24-hour mode.
• AMPM: Ante Meridiem Post Meridiem Indicator This bit is the AM/PM indicator in 12-hour mode. 0: AM. 1: PM. 31 302 92 82 72 62 52 4 23 22 21 20 19 18 17 16 –A MPM HOUR 15 14 13 12 11 10 9 8 –M IN 76543 210 – SEC

225SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

26.6.4 RTC Calendar Register

Name: RTC_CALR Address: 0x400E186C Access: Read/Write

• CENT: Current Century The range that can be set is 19–20 (Gregorian) or 13–14 (Persian) (BCD). The lowest four bits encode the units. The higher bits encode the tens.
• YEAR: Current Year The range that can be set is 00–99 (BCD). The lowest four bits encode the units. The higher bits encode the tens.
• MONTH: Current Month The range that can be set is 01–12 (BCD). The lowest four bits encode the units. The higher bits encode the tens.
• DAY: Current Day in Current Week The range that can be set is 1–7 (BCD). The coding of the number (which number represents which day) is user-defined as it has no effect on the date counter.
• DATE: Current Day in Current Month The range that can be set is 01–31 (BCD). The lowest four bits encode the units. The higher bits encode the tens. 31 302 92 82 72 62 52 4 –– DATE 23 22 21 20 19 18 17 16 DAY MONTH 15 14 13 12 11 10 9 8 YEAR 76543 210 –C ENT

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 226

26.6.5 RTC Time Alarm Register

Name: RTC_TIMALR Address: 0x400E1870 Access: Read/Write This register can only be written if the WPEN bit is cleared in the RTC Write Protection Mode Register. Note: To change one of the SEC, MIN, HOUR fields, it is recommend ed to disable the field before changing the value and then re- enable it after the change has been made. This requires up to three accesses to the RTC_TIMALR. The first access clears the enable corresponding to the field to change (SECEN, MINEN, HOUREN). If the field is already cleared, this access is not required. The second access performs the change of the value (SEC, MIN, HOUR). The third access is required to re-enable the field by writing 1 in SECEN, MINEN, HOUREN fields.

• SEC: Second Alarm This field is the alarm field corresponding to the BCD-coded second counter.
• SECEN: Second Alarm Enable 0: The second-matching alarm is disabled. 1: The second-matching alarm is enabled.
• MIN: Minute Alarm This field is the alarm field corresponding to the BCD-coded minute counter.
• MINEN: Minute Alarm Enable 0: The minute-matching alarm is disabled. 1: The minute-matching alarm is enabled.
• HOUR: Hour Alarm This field is the alarm field corresponding to the BCD-coded hour counter.
• AMPM: AM/PM Indicator This field is the alarm field corresponding to the BCD-coded hour counter.
• HOUREN: Hour Alarm Enable 0: The hour-matching alarm is disabled. 1: The hour-matching alarm is enabled. 31 302 92 82 72 62 52 4 23 22 21 20 19 18 17 16 HOUREN AMPM HOUR 15 14 13 12 11 10 9 8 MINEN MIN 76543 210 SECEN SEC

227SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

26.6.6 RTC Calendar Alarm Register

Name: RTC_CALALR Address: 0x400E1874 Access: Read/Write This register can only be written if the WPEN bit is cleared in the RTC Write Protection Mode Register. Note: To change one of the DATE, MONTH fields, it is recommended to disable the field before changing the value and then re-enable it after the change has been made. This requires up to three accesses to the RTC_CALALR. The first access clears the enable corresponding to the field to change (DATEEN, MTHEN). If the field is already cleared, this access is not required. The second access performs the change of the value (DATE, MONTH). The third access is required to re-enable the field by writing 1 in DATEEN, MTHEN fields.

• MONTH: Month Alarm This field is the alarm field corresponding to the BCD-coded month counter.
• MTHEN: Month Alarm Enable 0: The month-matching alarm is disabled. 1: The month-matching alarm is enabled.
• D A T E : D a t e A l a r m This field is the alarm field corresponding to the BCD-coded date counter.
• DATEEN: Date Alarm Enable 0: The date-matching alarm is disabled. 1: The date-matching alarm is enabled. 31 302 92 82 72 62 52 4 DATEEN – DATE 23 22 21 20 19 18 17 16 MTHEN – – MONTH 15 14 13 12 11 10 9 8 76543 210

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 228

26.6.7 RTC Status Register

Name: RTC_SR Address: 0x400E1878 Access: Read-only

• ACKUPD: Acknowledge for Update
• ALARM: Alarm Flag
• SEC: Second Event
• TIMEV: Time Event Note: The time event is se lected in the TIMEVSEL field in the Control Register (RTC_CR) and can be any one of the following events: minute change, hour change, noon, midnight (day change).
• CALEV: Calendar Event Note: The calendar even t is selected in the CALEVSEL field in the Control Register (RTC_CR) and can be any one of the following events: week change, month change and year change. 31 302 92 82 72 62 52 4 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543 210 – – TDERR CALEV TIMEV SEC ALARM ACKUPD Value Name Description 0 FREERUN Time and calendar registers cannot be updated. 1 UPDATE Time and calendar registers can be updated. Value Name Description 0 NO_ALARMEVENT No alarm matching condition occurred. 1 ALARMEVENT An alarm matching condition has occurred. Value Name Description 0 NO_SECEVENT No second event has occurred since the last clear. 1 SECEVENT At least one second event ha s occurred since the last clear. Value Name Description 0 NO_TIMEVENT No time event has occurred since the last clear. 1 TIMEVENT At least one time event has occurred since the last clear. Value Name Description 0 NO_CALEVENT No calendar event has occurred since the last clear. 1 CALEVENT At least one calendar event has occurred since the last clear.

229SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

• TDERR: Time and/or Date Free Running Error Value Name Description 0 CORRECT The internal free running counters are carrying valid values since the last read of the Status Register (RTC_SR).

1 ERR_TIMEDATE The internal free running counters have been corrupted (invalid date or time, non-BCD

values) since the last read and/or they are still invalid.

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 230

26.6.8 RTC Status Clear Command Register

Name: RTC_SCCR Address: 0x400E187C Access: Write-only

• ACKCLR: Acknowledge Clear 0: No effect. 1: Clears corresponding status flag in the Status Register (RTC_SR).
• ALRCLR: Alarm Clear 0: No effect. 1: Clears corresponding status flag in the Status Register (RTC_SR).
• SECCLR: Second Clear 0: No effect. 1: Clears corresponding status flag in the Status Register (RTC_SR).
• TIMCLR: Time Clear 0: No effect. 1: Clears corresponding status flag in the Status Register (RTC_SR).
• CALCLR: Calendar Clear 0: No effect. 1: Clears corresponding status flag in the Status Register (RTC_SR).
• TDERRCLR: Time and/or Date Free Running Error Clear 0: No effect. 1: Clears corresponding status flag in the Status Register (RTC_SR). 31 302 92 82 72 62 52 4 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543 210 – – TDERRCLR CALCLR TIMCLR SECCLR ALRCLR ACKCLR

231SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

26.6.9 RTC Interrupt Enable Register

Name: RTC_IER Address: 0x400E1880 Access: Write-only

• ACKEN: Acknowledge Update Interrupt Enable 0: No effect. 1: The acknowledge for update interrupt is enabled.
• ALREN: Alarm Interrupt Enable 0: No effect. 1: The alarm interrupt is enabled.
• SECEN: Second Event Interrupt Enable 0: No effect. 1: The second periodic interrupt is enabled.
• TIMEN: Time Event Interrupt Enable 0: No effect. 1: The selected time event interrupt is enabled.
• CALEN: Calendar Ev ent Interrupt Enable 0: No effect. 1: The selected calendar event interrupt is enabled.
• TDERREN: Time and/or Date Error Interrupt Enable 0: No effect. 1: The time and date error interrupt is enabled. 31 302 92 82 72 62 52 4 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543 210 – – TDERREN CALEN TIMEN SECEN ALREN ACKEN

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 232

26.6.10 RTC Interrupt Disable Register

Name: RTC_IDR Address: 0x400E1884 Access: Write-only

• ACKDIS: Acknowledge Update Interrupt Disable 0: No effect. 1: The acknowledge for update interrupt is disabled.
• ALRDIS: Alarm Interrupt Disable 0: No effect. 1: The alarm interrupt is disabled.
• SECDIS: Second Event Interrupt Disable 0: No effect. 1: The second periodic interrupt is disabled.
• TIMDIS: Time Event Interrupt Disable 0: No effect. 1: The selected time event interrupt is disabled.
• CALDIS: Calendar Ev ent Interrupt Disable 0: No effect. 1: The selected calendar event interrupt is disabled.
• TDERRDIS: Time and/or Da te Error Interrupt Disable 0: No effect. 1: The time and date error interrupt is disabled. 31 302 92 82 72 62 52 4 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543 210 – – TDERRDI S CALDIS TIMDISS ECDIS ALRDIS ACKDIS

233SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

26.6.11 RTC Interrupt Mask Register

Name: RTC_IMR Address: 0x400E1888 Access: Read-only

• ACK: Acknowledge Update Interrupt Mask 0: The acknowledge for update interrupt is disabled. 1: The acknowledge for update interrupt is enabled.
• ALR: Alarm Interrupt Mask 0: The alarm interrupt is disabled. 1: The alarm interrupt is enabled.
• SEC: Second Event Interrupt Mask 0: The second periodic interrupt is disabled. 1: The second periodic interrupt is enabled.
• TIM: Time Event Interrupt Mask 0: The selected time event interrupt is disabled. 1: The selected time event interrupt is enabled.
• CAL: Calendar Event Interrupt Mask 0: The selected calendar event interrupt is disabled. 1: The selected calendar event interrupt is enabled.
• TDERR: Time and/or Date Error Mask 0: The time and/or date error event is disabled. 1: The time and/or date error event is enabled. 31 302 92 82 72 62 52 4 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543 210 – – TDERR CAL TIM SEC ALR ACK

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 234

26.6.12 RTC Valid Entry Register

Name: RTC_VER Address: 0x400E188C Access: Read-only

• NVTIM: Non-valid Time 0: No invalid data has been detected in RTC_TIMR (Time Register). 1: RTC_TIMR has contained invalid data since it was last programmed.
• NVCAL: Non-valid Calendar 0: No invalid data has been detected in RTC_CALR (Calendar Register). 1: RTC_CALR has contained invalid data since it was last programmed.
• NVTIMALR: Non-valid Time Alarm 0: No invalid data has been detected in RTC_TIMALR (Time Alarm Register). 1: RTC_TIMALR has contained invalid data since it was last programmed.
• NVCALALR: Non-valid Calendar Alarm 0: No invalid data has been detected in RTC_CALALR (Calendar Alarm Register). 1: RTC_CALALR has contained invalid data since it was last programmed. 31 302 92 82 72 62 52 4 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543 210 –––– N VCALALR N VTIMALR N VCAL N VTIM

235SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

26.6.13 RTC Write Protection Mode Register

Name: RTC_WPMR Address: 0x400E1944 Access: Read/Write

• WPEN: Write Protection Enable 0: Disables the write protection if WPKEY corresponds to 0x525443 (“RTC” in ASCII). 1: Enables the write protection if WPKEY corresponds to 0x525443 (“RTC” in ASCII). The following registers can be write-protected:  RTC Mode Register  RTC Time Alarm Register  RTC Calendar Alarm Register
• WPKEY: Write Protection Key 31 30 29 28 27 26 25 24 WPKEY 23 22 21 20 19 18 17 16 WPKEY 15 14 13 12 11 10 9 8 WPKEY 76543210 Value Name Description 0x525443 PASSWD Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0.

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 236 27. Real-time Timer (RTT)

27.1 Description

The Real-timeTimer (RTT) is built around a 32-bit counter used to count roll-over events of the programmable 16- bit prescaler driven from the 32-kHz slow clock source. It generates a periodic interrupt and/or triggers an alarm on a programmed value. The RTT can also be configured to be driven by the 1Hz RTC signal, thus ta king advantage of a calibrated 1Hz clock. The slow clock source can be fully disabled to reduce power consumption when only an elapsed seconds count is required.

27.2 Embedded Characteristics

 32-bit Free-running Counter on prescaled slow clock or RTC calibrated 1Hz clock  16-bit Configurable Prescaler  Interrupt on Alarm or Counter Increment

27.3 Block Diagram

Figure 27-1. Real-time Timer SLCK RTPRES RTTINC ALMS 16-bit Prescaler 32-bit Counter ALMV CRTV RTT_MR RTT_VR RTT_AR RTT_SR RTTINCIEN RTT_MR ALMIEN rtt_int RTT_MR set set RTT_SR read RTT_SR reset reset RTT_MR reload rtt_alarm RTTRST RTT_MR RTTRST RTT_MR RTTDIS RTT_MR RTC1HZ RTC 1Hz

237SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

27.4 Functional Description

The programmable 16-bit prescaler value can be configured through the RTPRES field in the “Real-timeTimer Mode Register” (RTT_MR). Configuring the RTPRES field value to 0x8000 (default value) corresponds to feeding the real-time counter with a 1Hz signal (if the slow cloc k is 32.768 kHz). The 32-bit counter can count up to 2 32 seconds, corresponding to more than 136 years, then roll over to 0. Bit RTTINC in the “Real-time Timer Status Register” (RTT_SR) is set each time there is a prescaler roll-over (see Figure 27-2) The real-time 32-bit counter can also be supplied by t he 1Hz RTC clock. This mode is interesting when the RTC 1Hz is calibrated (CORRECTION field ≠ 0 in RTC_MR) in order to guaranty the synchronism between RTC and RTT counters. Setting the RTC1HZ bit in the RTT_MR drives the 32-bit RTT counter from the 1Hz RTC clock. In this mode, the RTPRES field has no effect on the 32-bit counter. The prescaler roll-over generates an increment of the real-time timer counter if RTC1HZ = 0. Otherwise, if RTC1HZ = 1, the real-time timer coun ter is incremented every second. The RTTINC bit is set independently from the 32-bit counter increment. The real-time timer can also be used as a free-running timer with a lower time-base. The best accuracy is achieved by writing RTPRES to 3 in RTT_MR. Programming RTPRES to 1 or 2 is forbidden. If the RTT is configured to trigger an interrupt, the interrupt occurs two slow clock cycles after reading the RTT_SR. To prevent several executions of the interrupt handler, the interrupt must be disabled in the interrupt handler and re-enabled when the RTT_SR is cleared. The CRTV field can be read at any time in the “Real-time Timer Value Register” (RTT_VR). As this value can be updated asynchronously with the Master Clock, the CRTV field must be read twice at the same value to read a correct value. The current value of the counter is compared with the value written in the “Real-time Timer Alarm Register” (RTT_AR). If the counter value matches the alarm, the ALMS bit in the RTT_SR is set. The RTT_AR is set to its maximum value (0xFFFF_FFFF) after a reset. The ALMS flag is always a source of the RTT alarm signal that may be used to exit the system from low power modes (see Figure 27-1). The alarm interrupt must be disabled (ALMIEN must be cleared in RTT_MR) when writing a new ALMV value in the RTT_AR. The RTTINC bit can be used to start a periodic interrupt, the period being one second when the RTPRES field value = 0x8000 and the slow clock = 32.768 kHz. The RTTINCIEN bit must be cleared prior to writing a new RTPRES value in the RTT_MR. Reading the RTT_SR automatically clears the RTTINC and ALMS bits. Writing the RTTRST bit in the RTT_MR immediately reloads and restarts the clock divider with the new programmed value. This also resets the 32-bit counter. When not used, the Real-time Timer can be disabled in order to suppress dynamic power consumption in this module. This can be achieved by setting the RTTDIS bit in the RTT_MR.

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 238 Figure 27-2. RTT Counting Prescaler ALMVALMV-10 ALMV+1 RTPRES - 1 CRTV read RTT_SR ALMS (RTT_SR) APB Interface SLCK RTTINC (RTT_SR) ALMV+2 ALMV+3... APB cycleAPB cycle

239SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

27.5 Real-time Timer (R TT) User Interface

Table 27-1. Register Mapping Offset Register Name Access Reset 0x00 Mode Register RTT_MR Read/Write 0x0000_8000 0x04 Alarm Register RTT_AR Read/Write 0xFFFF_FFFF 0x08 Value Register RTT_VR Read-only 0x0000_0000 0x0C Status Register RTT_SR Read-only 0x0000_0000

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 240

27.5.1 Real-timeTimer Mode Register

Name: RTT_MR Address: 0x400E1830 Access: Read/Write

• RTPRES: Real-time Timer Prescaler Value Defines the number of SLCK periods required to increment the real-time timer. RTPRES is defined as follows: RTPRES = 0: The prescaler period is equal to 216 * SLCK periods. RTPRES = 1 or 2: forbidden. RTPRES ≠ 0,1 or 2: The prescaler period is equal to RTPRES * SLCK periods. Note: The RTTINCIEN bit mu st be cleared prior to writing a new RTPRES value.  ALMIEN: Alarm Interrupt Enable 0: The bit ALMS in RTT_SR has no effect on interrupt. 1: The bit ALMS in RTT_SR asserts interrupt.  RTTINCIEN: Real-time Timer Increment Interrupt Enable 0: The bit RTTINC in RTT_SR has no effect on interrupt. 1: The bit RTTINC in RTT_SR asserts interrupt.  RTTRST: Real-time Timer Restart 0: No effect. 1: Reloads and restarts the clock divider with the new programmed value. This also resets the 32-bit counter.  RTTDIS: Real-time Timer Disable 0: The real-time timer is enabled. 1: The real-time timer is disabled (no dynamic power consumption).  RTC1HZ: Real-time Clock 1Hz Clock Selection 0: The RTT 32-bit counter is driven by the 16-bit prescaler roll-over events. 1: The RTT 32-bit counter is driven by the 1Hz RTC clock. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 – – – RTTDIS – RTTRST RTTINCIEN ALMIEN 15 14 13 12 11 10 9 8 RTPRES 76543210 RTPRES

241SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

27.5.2 Real-time Timer Alarm Register

Name: RTT_AR Address: 0x400E1834 Access: Read/Write  ALMV: Alarm Value When the CRTV value in RTT_VR equals the ALMV field, the ALMS flag is set in RTT_SR. As soon as the ALMS flag rises, the CRTV value equals ALMV+1 (refer to Figure 27-2). Note: The alarm interrupt must be disabled (ALMIEN must be cleared in RTT_MR) when writing a new ALMV value. 31 30 29 28 27 26 25 24 ALMV 23 22 21 20 19 18 17 16 ALMV 15 14 13 12 11 10 9 8 ALMV 76543210 ALMV

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 242

27.5.3 Real-time Timer Value Register

Name: RTT_VR Address: 0x400E1838 Access: Read-only  CRTV: Current Real-time Value Returns the current value of the Real-time Timer. Note: A s CRTV can be updated asynchronously, it must be read twice at the same value. 31 30 29 28 27 26 25 24 CRTV 23 22 21 20 19 18 17 16 CRTV 15 14 13 12 11 10 9 8 CRTV 76543210 CRTV

243SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

27.5.4 Real-time Timer Status Register

Name: RTT_SR Address: 0x400E183C Access: Read-only  ALMS: Real-time Alarm Status (cleared on read) 0: The real-time alarm has not occurred since the last read of RTT_SR. 1: The real-time alarm occurred since the last read of RTT_SR.  RTTINC: Prescaler Roll-over Status (cleared on read) 0: No prescaler roll-over occurred since the last read of the RTT_SR. 1: Prescaler roll-over occurred since the last read of the RTT_SR. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 244 28. SDRAM Controller (SDRAMC)

28.1 Description

The SDRAM Controller (SDRAMC) extends the memory capabilities of a chip by providing the interface to external 16-bitDRAM devices. The page size supports ranges from 2048 to 8192 and the number of columns from 256 to 2048. It supports byte (8-bit), half-word (16-bit) and word (32-bit) accesses. The SDRAMC supports a read or write burst length of one location. It keeps track of the active row in each bank, thus maximizing SDRAM performance, e.g., the applic ation may be placed in one bank and data in the other banks. For optimized performance, it is advisable to avoid accessing different rows in the same bank. The SDRAMC supports a CAS latency of 1, 2 or 3 and optimizes the read access depending on the frequency. The different modes available – Self-refresh, Power-down and Deep Power-down modes – minimize power consumption on the SDRAM device.

28.2 Embedded Characteristics

 Numerous Configurations Supported ̶ 2K, 4K, 8K Row Address Memory Parts ̶ SDRAM with Two or Four Internal Banks ̶ SDRAM with 16-bit Data Path  Programming Facilities ̶ Word, Half-word, Byte Access ̶ Automatic Page Break When Memory Boundary Has Been Reached ̶ Multibank Ping-pong Access ̶ Timing Parameters Specified by Software ̶ Automatic Refresh Operation, Refresh Rate is Programmable ̶ Automatic Update of DS, TCR and PASR Parameters (Mobile SDRAM Devices)  Energy-saving Capabilities ̶ Self-refresh, Power-down and Deep Power Modes Supported ̶ Supports Mobile SDRAM Devices  Error Detection ̶ Refresh Error Interrupt  SDRAM Power-up Initialization by Software  CAS Latency of 1, 2, 3 Supported  Auto Precharge Command Not Used  Zero Wait State Scrambling/Unscrambling Function with User Key

245SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

28.3 Signal Description

Table 28-1. Signal Description Name Description Type Active Level SDCK SDRAM Clock Output – SDCKE SDRAM Clock Enable Output High SDCS SDRAMC Chip Select Output Low BA[1:0] Bank Select Signals Output – RAS Row Signal Output Low CAS Column Signal Output Low SDWE SDRAM Write Enable Output Low NBS[1:0] Data Mask Enable Signals Output Low SDRAMC_A[12:0] Address Bus Output – D[15:0] Data Bus I/O –

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 246

28.4 Software Interface/SDRAM Organization, Address Mapping

The SDRAM address space is organized into banks, rows, and columns. Th e SDRAMC allows mapping different memory types according to the values set in the SDRAMC Configuration Register (SDRAMC_CR). The SDRAMC makes the SDRAM device acce ss protocol transparent to the user. Table 28-2 to Table 28-4 illustrate the SDRAM device memory m apping seen by the user in correlat ion with the device structure. Various configurations are illustrated.

28.4.1 SDRAM Address Mapping for 16-bit Memory Data Bus Width

Notes: 1. M0 is the byte addre ss inside a 16-bit half-word. 2. Bk[1] = BA1, Bk[0] = BA0. Table 28-2. SDRAM Configuration Mapping: 2K Rows, 256/512/1024/2048 Columns CPU Address Line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bk[1:0] Row[10:0] Column[7:0] M0 Bk[1:0] Row[10:0] Column[8:0] M0 Bk[1:0] Row[10:0] Column[9:0] M0 Bk[1:0] Row[10:0] Column[10:0] M0 Table 28-3. SDRAM Configuration Mapping: 4K Rows, 256/512/1024/2048 Columns CPU Address Line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bk[1:0] Row[11:0] Column[7:0] M0 Bk[1:0] Row[11:0] Column[8:0] M0 Bk[1:0] Row[11:0] Column[9:0] M0 Bk[1:0] Row[11:0] Column[10:0] M0 Table 28-4. SDRAM Configuration Mapping: 8K Rows, 256/512/1024/2048 Columns CPU Address Line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bk[1:0] Row[12:0] Column[7:0] M0 Bk[1:0] Row[12:0] Column[8:0] M0 Bk[1:0] Row[12:0] Column[9:0] M0 Bk[1:0] Row[12:0] Column[10:0] M0

247SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

28.5 Product Dependencies

28.5.1 SDRAM Device Initialization

The initialization sequence is generated by software. The SDRAM devices are init ialized by the following sequence: 1. Set the SDRAM features in the SDRAMC_CR: asyn chronous timings (TRC, TRAS, etc.), number of columns, number of rows, CAS latency and data bus width. For mobile SDRAM, configure temperature- compensated self-refresh (TCSR), drive strength (DS) and partial array self-refresh (PASR) in the Low Power Register (SDRAMC_LPR). 2. Select the SDRAM memory device type in the Memory Device Register (SDRAMC_MDR). 3. A pause of at least 200 µs must be observed before a signal toggle. 4. (1)A NOP command is issued to the SDRAM devices. The application must write a 1 to the MODE field in the Mode Register (SDRAMC_MR). Read the SDRAMC_MR and add a memory barrier assembler instruction just after the read. Perform a write access to any SDRAM address. 5. An All Banks Precharge command is issued to the SDRAM. The application must write a 2 to the MODE field in the SDRAMC_MR. Read the SDRAMC_MR and add a memory barrier assembler instruction just after the read. Perform a write access to any SDRAM address. 6. Eight auto-refresh (CBR) cycles are provided. Th e application must set the MODE field to 4 in the SDRAMC_MR. Read the SDRAMC_MR and add a memory barrier assembler instruction just after the read. Perform a write access to any SDRAM location eight times. 7. A Mode Register set (MRS) cycle is issued to program the parameters of the SDRAM, in particular CAS latency and burst length. The application must write a 3 to the MODE field in the SDRAMC_MR. Read the SDRAMC_MR and add a memory barrier assembler instruction just after the read. Perform a write access to the SDRAM. The write address must be chosen so that BA[1:0] are set to 0. For example, with a 16-bit 128 MB SDRAM (12 rows, 9 columns, 4 banks) bank address, the SDRAM write access should be done at the address 0x70000000. 8. For mobile SDRAM initialization, an Extended Mode Register set (EMR S) cycle is issued to program the SDRAM parameters (TCSR, PASR, DS). The application must set the MODE field to 5 in the SDRAMC_MR. Read the SDRAMC_MR and add a memory barrier assembler instruction just after the read. Perform a write access to the SDRAM. The write address must be chosen so that BA[1] or BA[0] are set to 1. For example, with a 16-bit 128 MB SDRAM (12 rows, 9 columns, 4 banks) bank address, the SDRAM write access should be done at address 0x70800000 or 0x70400000. 9. The application must go into Normal mode. Configure MODE to 0 in th e SDRAMC_MR. Read the SDRAMC_MR and add a memory barrier assembler instruction just after the read. Perform a write access at any location in the SDRAM. 10. Write the refresh rate into th e COUNT field in the SDRAMC Refresh Timer Register (SDRAMC_TR). (Refresh rate = delay between refresh cycles). The SDRAM device requires a refresh every 15.625 µs or 7.81 µs. With a 100 MHz frequency, the Refresh Timer Register must be set with the value 1562 (15.625 µs x 100 MHz) or 781 (7.81 µs x 100 MHz). After initialization, the SDRAM devices are fully functional. Note: 1. The instructions stated in Step 4 of the initialization process must be respected to make sure the subsequent commands issued by the SDRAMC are taken into account.

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 248 Figure 28-1. SDRAM Device Initialization Sequence

28.5.2 I/O Lines

The pins used for interfacing the SDRAMC may be mult iplexed with the PIO lines. The programmer must first program the PIO controller to assign the SDRAMC pins to their peripheral function. If I/O lines of the SDRAMC are not used by the application, they can be used for other purposes by the PIO Controller. SDCK SDRAMC_A[9:0] A10 SDRAMC_A[12:11] SDCS RAS CAS SDWE NBS Inputs Stable for 200 μs Precharge All Banks 1st Auto-refresh 8th Auto-refresh MRS Command Valid Command SDCKE tRP tRFC tMRD Table 28-5. I/O Lines Instance Signal I/O Line Peripheral SDRAMC A0/NBS0 PC18 A SDRAMC A1 PC19 A SDRAMC A2 PC20 A SDRAMC A3 PC21 A SDRAMC A4 PC22 A SDRAMC A5 PC23 A SDRAMC A6 PC24 A SDRAMC A7 PC25 A SDRAMC A8 PC26 A SDRAMC A9 PC27 A SDRAMC A10 PC28 A SDRAMC A11 PC29 A SDRAMC A12 PC30 A

249SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 SDRAMC A13 PC31 A SDRAMC A14 PA18 C SDRAMC A15 PA19 C SDRAMC A16/BA0 PA20 C SDRAMC A17/BA1 PA0 C SDRAMC A18 PA1 C SDRAMC A19 PA23 C SDRAMC A20 PA24 C SDRAMC A21/NANDALE PC16 A SDRAMC A22/NANDCLE PC17 A SDRAMC A23 PA25 C SDRAMC CAS PD17 C SDRAMC D0 PC0 A SDRAMC D1 PC1 A SDRAMC D2 PC2 A SDRAMC D3 PC3 A SDRAMC D4 PC4 A SDRAMC D5 PC5 A SDRAMC D6 PC6 A SDRAMC D7 PC7 A SDRAMC D8 PE0 A SDRAMC D9 PE1 A SDRAMC D10 PE2 A SDRAMC D11 PE3 A SDRAMC D12 PE4 A SDRAMC D13 PE5 A SDRAMC D14 PA15 A SDRAMC D15 PA16 A SDRAMC NANDOE PC9 A SDRAMC NANDWE PC10 A SDRAMC NCS0 PC14 A SDRAMC NCS1/SDCS PC15 A SDRAMC NCS1/SDCS PD18 A SDRAMC NCS2 PA22 C SDRAMC NCS3 PC12 A SDRAMC NCS3 PD19 A SDRAMC NRD PC11 A SDRAMC NWAIT PC13 A Table 28-5. I/O Lines

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 250

28.5.3 Power Management

The SDRAMC may be clocked through the Power Management Controller (PMC), thus the programmer must first configure the PMC to enable the SDRAMC clock. The SDRAM clock on pin SDCK is out put as soon as the first access to the SDRAM is made during the initialization phase. To stop the SDRAM clock signal, the SDRAMC_LPR must be programmed with the self- refresh command.

28.5.4 Interrupt Sources

The SDRAMC interrupt (Refresh Error notification) is c onnected to the memory controller. This interrupt may be ORed with other system peripheral interrupt lines and is finally provided as the system interrupt source (Source 1) to the interrupt controller. Using the SDRAMC interrupt requires the interrupt controller to be programmed first. SDRAMC NWR0/NWE PC8 A SDRAMC NWR1/NBS1 PD15 C SDRAMC RAS PD16 C SDRAMC SDA10 PC13 C SDRAMC SDA10 PD13 C SDRAMC SDCK PD23 C SDRAMC SDCKE PD14 C SDRAMC SDWE PD29 C Table 28-5. I/O Lines Table 28-6. Peripheral IDs Instance ID SDRAMC 62

251SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

28.6 Functional Description

28.6.1 SDRAM Controller Write Cycle

The SDRAMC allows burst access or single access. In bo th cases, the SDRAMC keeps track of the active row in each bank, thus maximizing pe rformance. To initiate a burst access, the SDRAMC uses the transfer type signal provided by the master requesting the access. If the next access is a sequential write access, writing to the SDRAM device is carried out. If the next access is a write-sequential access, but the current access is to a boundary page, or if the next access is in another row, then the SDRAMC generates a precharge command, activates the new row and initiates a write command. To comply with SDRAM timing parameters, additional clock cycles are inserted between precharge and active commands (t RP), and between active and write commands (tRCD) . For definition of these timing parameters, refer to the SDRAMC Configuration Register. Refer to Figure 28-2. Figure 28-2. Write Burst SDRAM Access SDCK SDCS RAS CAS SDRAMC_A[12:0] DATA tRCD Dna SDWE Dnb Dnc Dnd Dne Dnf Dng Dnh Dni Dnj Dnk Dnl Row n col a col b col c col d col e col f col g col h col i col j col k col l

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 252

28.6.2 SDRAM Controller Read Cycle

The SDRAMC allows burst access, incr emental burst of unspecified length or single access. In all cases, the SDRAMC keeps track of the active row in each bank, thus maximizing performance of the SDRAM. If row and bank addresses do not match the previous row/bank address, then the SDRAMC automatically generates a precharge command, activates the new row and starts the read command. To comply with the SDRAM timing parameters, additional clock cycles on SDCK are inserted between pr echarge and active commands (t RP), and between active and read commands (t RCD). These two parameters are set in the SDRAMC_CR. After a read command, additional wait states are generated to comply with the CAS latency (1, 2 or 3 clock delays specified in the SDRAMC_CR). For a single access or an incremented burst of unspec ified length, the SDRAMC anticipates the next access. While the last value of the column is returned by the SDRAMC on the bus, the SDRAMC anticipates the read to the next column and thus anticipates the CAS latency. This reduces the effect of the CAS latency on the internal bus. For burst access of specified length (4, 8, 16 words), a ccess is not anticipated. This case leads to the best performance. If the burst is broken (border, Busy mode, etc.), the next access is handled as an incrementing burst of unspecified length. Figure 28-3. Read Burst SDRAM Access SDCK SDCS RAS CAS SDRAMC_A[12:0] DATA (Input) tRCD Dna SDWE Dnb Dnc Dnd Dne Dnf Row n col a col b col c col d col e col f CAS

253SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

28.6.3 Border Management

When the memory row boundary has been reached, an auto matic page break is inserted. In this case, the SDRAMC generates a precharge command, activates the new row and initiates a read or write command. To comply with SDRAM timing parameters, an additional clock cycle is inserted between the precharge and the active command (tRP) and between the active and the read command (tRCD). Refer to Figure 28-4. Figure 28-4. Read Burst with Boundary Row Access SDCK SDCS RAS CAS SDRAMC_A[12:0] DATA tRP SDWE Row mcol a col a col b col c col d col e Dna Dnb Dnc Dnd tRCD CAS col b col c col d Dma Dmb Dmc Dmd Row n Dme

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 254

28.6.4 SDRAM Controller Refresh Cycles

An auto-refresh command is used to refresh the SDRAM device. Refresh addresses are generated internally by the SDRAM device and incremented after each auto-refr esh automatically. The SDRAMC generates these auto- refresh commands periodically. An internal timer is loaded with the value in S DRAMC_TR that indicates the number of clock cycles between refresh cycles. A refresh error interrupt is generated when the previous auto-refresh command did not perform. It is acknowledged by reading the Interrupt Status Register (SDRAMC_ISR). When the SDRAMC initiates a refresh of the SDRAM device, internal memory accesses are not delayed. However, if the processor tries to access the SDRAM, the slave indicates that the device is busy and the master is held by a wait signal. Refer to Figure 28-5. Figure 28-5. Refresh Cycle Followed by a Read Access

28.6.5 Power Management

Three low-power modes are available:  Self-refresh mode: The SDRAM executes its own Auto-refresh cycle without control of the SDRAMC. Current drained by the SDRAM is very low.  Power-down mode: Auto-refresh cycles are controlled by the SDRAMC. Between auto-refresh cycles, the SDRAM is in power-down. Current drained in Power-down mode is higher than in Self-refresh Mode.  Deep Power-down mode (only available with Mobile SDRAM): The SDRAM contents are lost, but the SDRAM does not drain any current. The SDRAMC activates one low-power mode as soon as the SDRAM device is not selected. It is possible to delay the entry in Self-refresh and Power-down modes after the last access by programming a timeout value in the SDRAMC_LPR.

28.6.5.1 Self-refresh Mode

This mode is selected by configuri ng the LPCB field to 1 in SDRAMC_LP R. In Self-refresh mode, the SDRAM device retains data without external clocking and provides its own internal clocking, thus performing its own auto- refresh cycles. All the inputs to the SDRAM device bec ome “don’t care” except SDCKE, which remains low. As soon as the SDRAM device is select ed, the SDRAMC provides a sequence of commands and exits Self-refresh mode. SDCK SDCS RAS CAS SDRAMC_A[12:0] DATA (input) tRP SDWE Dnb Dnc Dnd col c col d CAS Row m col a tRFC tRCD Dma Row n

255SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 Some low-power SDRAMs (e.g., mobile SDRAM) can refresh only one-quarter or a half quarter or all banks of the SDRAM array. This feature reduces the self-refresh current. To configure this feature, Temperature Compensated Self-Refresh (TCSR), Partial Array Self-Refresh (PASR) a nd Drive Strength (DS) parame ters must be set in the SDRAMC_LPR and transmitted to the low-power SDRAM during initialization. After initialization, as soon as the PASR/DS/TCSR fields are modified and Self-refresh mode is activated, the Extended Mode Register is accessed automatically and the PASR/DS/TCSR bits are updated before entry into Self-refresh mode. This feature is not supported when SDRAMC shares an external bus with another controller. The SDRAM device must remain in Self-refresh mode for a minimum period of t RAS and may remain in Self-refresh mode for an indefinite period. Refer to Figure 28-6. Note: Some SDRAM providers impose some cycles of burs t auto-refresh immediately before self-refresh entry and immediately after self-refresh exit. For example, a SDRAM with 4096 rows will impose 4096 cycles of burst auto- refresh. This constraint is not supported. Figure 28-6. Self-refresh Mode Behavior SDCK SDCS RAS CAS SDRAMC_A[12:0] Self Refresh Mode SDWE Row tXSR SDCKE Write SDRAMC_LPR LPCB = 1 Access Request to the SDRAM Controller

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 256

28.6.5.2 Low-power Mode

This mode is selected by configuring the LPCB field to 2 in the SDRAMC_LPR. Power consumption is greater than in Self-refresh mode. All the input and output buffers of the SDRAM device are deactivated except SDCKE, which remains low. In contrast to Self-refresh mode, the SDRAM device ca nnot remain in Low-power mode longer than the refresh period (64 ms for a whole device refresh operation). As no auto-refresh operations are performed by the SDRAM itself, the SDRAMC carries out the refresh operat ion. The exit procedure is faster than in Self-refresh mode. Refer to Figure 28-7. Figure 28-7. Low-power Mode Behavior SDCK SDCS RAS CAS SDRAMC_A[12:0] DATA (input) tRCD Dna Dnb Dnc Dnd Dne Dnf Row n col a col b col c col d col e col f CAS SDCKE Low Power Mode

257SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

28.6.5.3 Deep Power-down Mode

This mode is selected by configuring the LPCB field to 3 in the SDRAMC_LPR. When this mode is activated, all internal voltage generators inside the SDRAM are stopped and all data is lost. When this mode is enabled, the application must not access to the SDRAM until a new initialization sequence is done (see Section 28.5.1 “SDRAM Device Initialization”). Refer to Figure 28-8. Figure 28-8. Deep Power-down Mode Behavior

28.6.6 Scrambling/Unscrambling Function

The external data bus can be scrambled in order to prevent intellectual property data located in off-chip memories from being easily recovered by analyzing data at the package pin level of either microcontroller or memory device. The scrambling and unscrambling are performed on-the-fly without additional wait states. The scrambling/unscrambling function can be enabled or disabled by configuring the SDR_SE bit in the SDRAMC OCMS Register (SDRAMC_OCMS). This bit cannot be re -configured as long as the external memory device is powered. The scrambling method depends on two user-configurable key re gisters, SDRAMC_OCMS_KEY1 and SDRAMC_OCMS_KEY2 plus a random value depending on device processing characteristics. These key registers are only accessible in Write mode. The scrambling user key or the seed for key generation mu st be securely stored in a reliable non-volatile memory in order to recover data from the off-chip memory. Any data scrambled with a given key cannot be recovered if the key is lost. When multiple chip selects are handled, it is possible to configure the scrambling function per chip select using the OCMS field in the SDRAMC_OCMS registers. SDCK SDCS RAS CAS SDRAMC_A[12:0] DATA (input) tRP SDWE Dnb Dnc Dnd col c col d Row n CKE

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 258

28.7 SDRAM Controller (SDRAMC) User Interface

Note: All unlisted offset values are considered as ‘reserved’. Table 28-7. Register Mapping Offset Register Name Access Reset 0x00 SDRAMC Mode Register SDRAMC_MR Read/Write 0x00000000 0x04 SDRAMC Refresh Timer Register SDRAMC_TR Read/Write 0x00000000 0x08 SDRAMC Configuration Regi ster SDRAMC_CR Read/Write 0x852372C0 0x10 SDRAMC Low Power Register SDRAMC_LPR Read/Write 0x00000000 0x14 SDRAMC Interrupt Enable Register SDRAMC_IER Write-only – 0x18 SDRAMC Interrupt Disable Register SDRAMC_IDR Write-only – 0x1C SDRAMC Interrupt Mask Register SDRAMC_IMR Read-only 0x00000000 0x20 SDRAMC Interrupt Status Regi ster SDRAMC_ISR Read-only 0x00000000 0x24 SDRAMC Memory Device Register SDRAMC_MDR Read/Write 0x00000000 0x28 SDRAMC Configuration Regist er 1 SDRAMC_CFR1 Read/Write 0x00000002 0x2C SDRAMC OCMS Register SDRAMC_OCMS Read/Write 0x00000000 0x30 SDRAMC OCMS KEY1 Register SDRAMC_OCMS_KEY1 Write-only – 0x34 SDRAMC OCMS KEY2 Register SDRAMC_OCMS_KEY2 Write-only – 0x38–0xFC Reserved – – –

259SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

28.7.1 SDRAMC Mode Register

Name: SDRAMC_MR Address: 0x40084000 Access: Read/Write

• MODE: SDRAMC Command Mode This field defines the command issued by the SDRAMC when the SDRAM device is accessed. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 Value Name Description 0N O R M A L Normal mode. Any access to the SDRAM is decoded normally. To activate this mode, the command must be followed by a write to the SDRAM. 1N O P The SDRAMC issues a NOP command when the SDRAM device is accessed regardless of the cycle. To activate this mode, the command must be followed by a write to the SDRAM.

2 ALLBANKS_PRECHARGE

The SDRAMC issues an “All Banks Precharge” command when the SDRAM device is accessed regardless of the cycle. To activate this mode, the command must be followed by a write to the SDRAM.

3 LOAD_MODEREG

The SDRAMC issues a “Load Mode Register” command when the SDRAM device is accessed regardless of the cycle. To activate this mode, the command must be followed by a write to the SDRAM.

4 AUTO_REFRESH

The SDRAMC issues an “Auto-Refresh” Command when the SDRAM device is accessed regardless of the cycle. Previously, an “All Banks Precharge” command must be issued. To activate this mode, the command must be followed by a write to the SDRAM.

5 EXT_LOAD_MODEREG

The SDRAMC issues an “Extended Load Mode Register” command when the SDRAM device is accessed regardless of the cycle. To activate this mode, the “Extended Load Mode Register” command must be followed by a write to the SDRAM. The write in the SDRAM must be done in the appropriate bank; most low-power SDRAM devices use the bank 1. 6 DEEP_POWERDOWN Deep Power-down mode. Enters Deep Power-down mode.

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 260

28.7.2 SDRAMC Refresh Timer Register

Name: SDRAMC_TR Address: 0x40084004 Access: Read/Write

• COUNT: SDRAMC Refresh Timer Count This 12-bit field is loaded into a timer that generates the refresh pulse. Each time the refresh pulse is generated, a refresh burst is initiated. The SDRAM device requires a refresh every 15.625 µs or 7.81 µs. With a 100 MHz frequency, the Refresh Timer Counter Register must be set with the value 1562 (15.625 µs x 100 MHz) or 781 (7.81 µs x 100 MHz). To refresh the SDRAM device, this 12-bit field must be written. If this condition is not satisfied, no refresh command is issued and no refresh of the SDRAM device is carried out. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 –––– COUNT 76543210 COUNT

261SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

28.7.3 SDRAMC Confi guration Register

Name: SDRAMC_CR Address: 0x40084008 Access: Read/Write Warning: Bit 7 (DBW) must always be set when programming the SDRAMC_CR.

• NC: Number of Column Bits Reset value is 8 column bits.
• NR: Number of Row Bits Reset value is 11 row bits.
• NB: Number of Banks Reset value is two banks. 31 30 29 28 27 26 25 24 TXSR TRAS 23 22 21 20 19 18 17 16 TRCD TRP 15 14 13 12 11 10 9 8 TRC_TRFC TWR 76543210 DBW CAS NB NR NC Value Name Description

0 COL8 8 column bits

1 COL9 9 column bits

2 COL10 10 column bits

3 COL11 11 column bits

0 ROW11 11 row bits

1 ROW12 12 row bits

2 ROW13 13 row bits

3– R e s e r v e d Value Name Description

0 BANK2 2 banks

1 BANK4 4 banks

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 262

• CAS: CAS Latency Reset value is two cycles. In the SDRAMC, only a CAS latency of one, two and three cycles are managed.
• DBW: Data Bus Width Reset value is 16 bits. This bit defines the Data Bus Width, which is 16 bits. It must be set to 1.
• TWR: Write Recovery Delay Reset value is two cycles. This field defines the Write Recovery Time in number of cycles. Number of cycles is between 0 and 15.
• TRC_TRFC: Row Cycle Delay and Row Refresh Cycle Reset value is seven cycles. This field defines two timings: –t h e d e lay (t RFC) between two Refresh commands and between a Refresh command and an Activate command – and the delay (tRC) between two Active commands in number of cycles. The number of cycles is between 0 and 15. The end user must program max {tRC, tRFC}.
• TRP: Row Precharge Delay Reset value is three cycles. This field defines the delay between a Precharge Command and another Command in number of cycles. Number of cycles is between 0 and 15.
• TRCD: Row to Column Delay Reset value is two cycles. This field defines the delay between an Activate Command and a Read/Write Command in number of cycles. Number of cycles is between 0 and 15.
• TRAS: Active to Precharge Delay Reset value is five cycles. This field defines the delay between an Activate Command and a Precharge Command in number of cycles. Number of cycles is between 0 and 15.
• TXSR: Exit Self-Refre sh to Active Delay Reset value is eight cycles. This field defines the delay between SCKE set high and an Activate Command in number of cycles. Number of cycles is between 0 and 15. Value Name Description 0– R e s e r v e d

1 LATENCY1 1 cycle latency

2 LATENCY2 2 cycle latency

3 LATENCY3 3 cycle latency

263SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

28.7.4 SDRAMC Low Power Register

Name: SDRAMC_LPR Address: 0x40084010 Access: Read/Write

• LPCB: Low-power Configuration Bits
• PASR: Partial Array Self-refresh (only for low-power SDRAM) PASR parameter is transmitted to the SDRAM during initialization to specify whether only one quarter, one half or all banks of the SDRAM array are enabled. Disabled banks are not refreshed in Self-refresh mode. This parameter must be set according to the SDRAM device specification. After initialization, as soon as the PASR field is modified and Self-refresh mode is activated, the Extended Mode Register is accessed automatically and PASR bits are updated before entry in Self-refresh mode. This feature is not supported when SDRAMC shares an external bus with another controller.
• TCSR: Temperature Compensated Self-Refresh (only for low-power SDRAM) TCSR parameter is transmitted to the SDRAM during initialization to set the refresh interval during Self-refresh mode depending on the temperature of the low-power SDRAM. This parameter must be set according to the SDRAM device specification. After initialization, as soon as the TCSR field is modified and Self-refresh mode is activated, the Extended Mode Register is accessed automatically and TCSR bits are updated before entry in Self-refresh mode. This feature is not supported when SDRAMC shares an external bus with another controller.
• DS: Drive Strength (only for low-power SDRAM) DS parameter is transmitted to the SDRAM during initialization to select the SDRAM strength of data output. This parame- ter must be set according to the SDRAM device specification. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 –– T IMEOUT DS TCSR 76543210 – PASR – – LPCB Value Name Description

0 DISABLED The low-power feature is inhibited: no Power-down, Self-refresh or Deep Power-down command

is issued to the SDRAM device.

1 SELF_REFRESH

The SDRAMC issues a Self-refresh command to the SDRAM device, the SDCK clock is deactivated and the SDCKE signal is set low. The SDRAM device leaves the Self-refresh mode when accessed and enters it after the access. 2P O W E R _ D O W N The SDRAMC issues a Power-down Command to the SDRAM device after each access, the SDCKE signal is set to low. The SDRAM device leaves the Power-down mode when accessed and enters it after the access. 3 DEEP_POWER_DOWN The SDRAMC issues a Deep Power-down command to the SDRAM device. This mode is unique to low-power SDRAM.

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 264 After initialization, as soon as the DS field is modified and Self-refresh mode is activated, the Extended Mode Register is accessed automatically and DS bits are updated before entry in Self-refresh mode. This feature is not supported when SDRAMC shares an external bus with another controller.

• TIMEOUT: Time to Define When Low-power Mode Is Enabled Value Name Description

0 LP_LAST_XFER The SDRAMC activates the SDRAM Low-power mode immediately after the end of the last

transfer. 1 LP_LAST_XFER_64 The SDRAMC activates the SDRAM Low-power mode 64 clock cycles after the end of the last transfer. 2 LP_LAST_XFER_128 The SDRAMC activates the SDRAM Low-power mode 128 clock cycles after the end of the last transfer. 3– R e s e r v e d

265SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

28.7.5 SDRAMC Interrupt Enable Register

Name: SDRAMC_IER Address: 0x40084014 Access: Write-only

• RES: Refresh Error Status 0: No effect. 1: Enables the refresh error interrupt. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 266

28.7.6 SDRAMC Interrupt Disable Register

Name: SDRAMC_IDR Address: 0x40084018 Access: Write-only

• RES: Refresh Error Status 0: No effect. 1: Disables the refresh error interrupt. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210

267SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

28.7.7 SDRAMC Interr upt Mask Register

Name: SDRAMC_IMR Address: 0x4008401C Access: Read-only

• RES: Refresh Error Status 0: The refresh error interrupt is disabled. 1: The refresh error interrupt is enabled. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 268

28.7.8 SDRAMC Interrupt Status Register

Name: SDRAMC_ISR Address: 0x40084020 Access: Read-only

• RES: Refresh Error Status (cleared on read) 0: No refresh error has been detected since the register was last read. 1: A refresh error has been detected since the register was last read. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210

269SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

28.7.9 SDRAMC Memory Device Register

Name: SDRAMC_MDR Address: 0x40084024 Access: Read/Write

• MD: Memory Device Type 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 Value Name Description

0 SDRAM SDRAM

1 LPSDRAM Low-power SDRAM

2– R e s e r v e d 3– R e s e r v e d

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 270

28.7.10 SDRAMC Configuration Register 1

Name: SDRAMC_CFR1 Address: 0x40084028 Access: Read/Write

• TMRD: Load Mode Register Command to Active or Refresh Command Reset value is 2 cycles. This field defines the delay between a “Load Mode Register” command and an active or refresh command in number of cycles. Number of cycles is between 0 and 15.
• UNAL: Support Unaligned Access This mode is enabled with masters which have an AXI interface. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 –––– TMRD Value Name Description 0 UNSUPPORTED Unaligned access is not supported. 1 SUPPORTED Unaligned access is supported.

271SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

28.7.11 SDRAMC OCMS Register

Name: SDRAMC_OCMS Address: 0x4008402C Access: Read/Write

• SDR_SE: SDRAM Memory Co ntroller Scrambling Enable 0: Disables off-chip scrambling for SDR-SDRAM access. 1: Enables off-chip scrambling for SDR-SDRAM access. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 272

28.7.12 SDRAMC OCMS KEY1 Register

Name: SDRAMC_OCMS_KEY1 Address: 0x40084030 Access: Write-once

• KEY1: Off-chip Memory Scrambling (OCMS) Key Part 1 When off-chip memory scrambling is enabled, the data scrambling depends on KEY1 and KEY2 values. 31 30 29 28 27 26 25 24 KEY1 23 22 21 20 19 18 17 16 KEY1 15 14 13 12 11 10 9 8 KEY1 76543210 KEY1

273SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

28.7.13 SDRAMC OCMS KEY2 Register

Name: SDRAMC_OCMS_KEY2 Address: 0x40084034 Access: Write-once

• KEY2: Off-chip Memory Scrambling (OCMS) Key Part 2 When off-chip memory scrambling is enabled, the data scrambling depends on KEY1 and KEY2 values. 31 30 29 28 27 26 25 24 KEY2 23 22 21 20 19 18 17 16 KEY2 15 14 13 12 11 10 9 8 KEY2 76543210 KEY2

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 274 29. General Purpose Backup Registers (GPBR)

29.1 Description

The System Controller embeds 256 bits of General Purpose Backup registers organized as 8 32-bit registers. It is possible to generate an immediate clear of the content of General Purpose Backup registers 0 to 3 (first half) if a Low-power Debounce event is detected on one of the wakeup pins, WKUP0 or WKUP1. The content of the other General Purpose Backup registers (second half) remains unchanged. The Supply Controller module must be programmed accord ingly. In the register SUPC_WUMR in the Supply Controller module, LPDBCCLR, LPDBCEN0 and/or LPDBCEN1 bit must be configured to 1 and LPDBC must be other than 0. If a Tamper event has been detected, it is not possible to write to the General Purpose Backup registers while the LPDBCS0 or LPDBCS1 flags are not cleared in the Supply Controller Status Register (SUPC_SR).

29.2 Embedded Characteristics

 256 bits of General Purpose Backup Registers

275SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

29.3 General Purpose Backup Regi sters (GPBR) User Interface

Table 29-1. Register Mapping Offset Register Name Access Reset 0x0 General Purpose Backup Regist er 0 SYS_GPBR0 Read/Write 0x00000000 0x1C General Purpose Ba ckup Register 7 SYS_GPBR7 Read/Write 0x00000000

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 276

29.3.1 General Purpose Backup Register x

Name: SYS_GPBRx Address: 0x400E1890 Access: Read/Write These registers are reset at first power-up and on each loss of VDDIO.

• GPBR_VALUE: Value of GPBR x If a Tamper event has been detected, it is not possible to write GPBR_VALUE as long as the LPDBCS0 or LPDBCS1 flag has not been cleared in the Supply Controller Status Register (SUPC_SR). 31 302 92 82 72 62 52 4 GPBR_VALUE 23 22 21 20 19 18 17 16 GPBR_VALUE 15 14 13 12 11 10 9 8 GPBR_VALUE 76543 210 GPBR_VALUE

277SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 30. Clock Generator

30.1 Description

The Clock Generator user interface is embedded withi n the Power Management Cont roller and is described in Section 31.20 ”Power Management Controller (PMC) User Interface”. However, the Clock Generator registers are named CKGR_.

30.2 Embedded Characteristics

The Clock Generator is made up of:  A low-power 32.768 kHz crystal oscillator with Bypass mode  A low-power embedded 32 kHz (typical) RC oscillator  A 3 to 20 MHz crystal or ceramic resonator-based oscillator with Bypass mode  An embedded RC oscillator. Three output frequencies can be selected: 4/8/12 MHz. By default 4 MHz is selected. 8 MHz and 12 MHz are factory-trimmed.  A 480 MHz UTMI PLL, providing a clock for the USB High-speed Controller  A 160 to 500 MHz programmable PLL (input from 8 to 32 MHz) It provides the following clocks:  SLCK, the slow clock, which is the only permanent clock within the system.  MAINCK is the output of the main clock oscillator selection: either the crystal or ceramic resonator-based oscillator or 4/8/12 MHz RC oscillator.  PLLACK is the output of the divider and 160 to 500 MHz programmable PLL (PLLA)  UPLLCK is the output of the 480 MHz UTMI PLL (UPLL)

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 278

30.3 Block Diagram

Figure 30-1. Clock Generator Block Diagram Power Management Controller Main Clock MAINCK PLLA Clock PLLACK ControlStatus 3-20 MHz Crystal Oscillator MOSCSEL Clock Generator PLLA and Divider Embedded 12/8/4 MHz RC Oscillator XIN XOUT XIN32 XOUT32 Slow Clock SLCK XTALSEL (Supply Controller) Embedded 32 kHz RC Oscillator 32768 Hz Crystal Oscillator UPLL Clock UPLLCK USB UTMI PLL CKGR_MOR

279SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

30.4 Slow Clock

The Supply Controller embeds a slow clock generator that is supplied with the VDD IO power supply. As soon as VDDIO is supplied, both th e crystal oscillator and the embedded RC os cillator are powered up, but only the embedded 32 kHz (typical) RC oscillator is enabled. This allows the slow clock to be valid in a short time (about 100 µs). The slow clock is generated either by the 32.768 kHz cr ystal oscillator or by the embedded 32 kHz (typical) RC oscillator. The selection is made via the XTALSEL bit in the Supply Controller Control register (SUPC_CR).

30.4.1 Embedded 32 kHz (typical) RC Oscillator

By default, the embedded 32 kHz (typical) RC oscillator is enabled and selected. The user has to take into account the possible drifts of this oscillator. Refer to section Section 56.2 ”DC Characteristics”. This oscillator is disabled by clearing the SUPC_CR.XTALSEL. 30.4.2 32.768 kHz Crystal Oscillator The Clock Generator integrates a low-power 32.768 kHz oscillator. To use this oscillator, the XIN32 and XOUT32 pins must be connected to a 32.768 kHz crystal. Two external capacitors must be wired as shown in Figure 30-2. More details are given in the section “DC Characteristics”. Note that the user is no t obliged to use the 32.768 kHz crystal osc illator and can use the 32 kHz (typical) RC oscillator instead. Figure 30-2. Typical 32.768 kHz Crystal Oscillator Connection The 32.768 kHz crystal oscillator provides a more accurate frequency than the 32 kHz (typical) RC oscillator. To select the 32.768 kHz crystal oscillator as the source of the slow clock, the bit SUPC_CR.XTALSEL must be set. This results in a sequence which first configures the PIO lines multiplexed with XIN32 and XOUT32 to be driven by the crystal oscillator, then enables the 32. 768 kHz crystal oscillator and then disables the 32 kHz (typical) RC oscillator to save power. The switch of the slow clock source is glitch-free. Reverting to the 32 kHz (typical) RC osc illator is only possible by shutting down the VDDIO power supply. If the user does not need the 32.768 kHz crysta l oscillator, the XIN32 and XOUT32 pins can be left unconnected since by default the XIN32 and XOUT32 system I/O pins are in PIO input mode with pull-up after reset. The user can also set the 32.768 kHz crystal oscillator in Bypass mode instead of c onnecting a crystal. In this case, the user must provide the exte rnal clock signal on XIN32. The input characteristics of the XIN32 pin are given in the section “Electrical Characteristics”. To enter Bypass mo de, the OSCBYPASS bit of the Supply Controller Mode register (SUPC_MR) must be set prior to setting SUPC_CR.XTALSEL.

30.5 Main Clock

Figure 30-3 shows the main clock block diagram. XIN32 XOUT32 GND 32768 Hz Crystal

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 280 Figure 30-3. Main Clock Block Diagram The main clock has two sources:  A 4/8/12 MHz RC oscillator with a fast start-up time and that is selected by default to start the system  A 3 to 20 MHz crystal or ceramic resonator-based oscillator which can be bypassed. Refer to Section 30.5.5 ”Bypassing the Main Crystal Oscillator”.

30.5.1 Embedded 4/8/12 MHz RC Oscillator

After reset, the 4/8/12 MHz RC oscillator is enabled with the 4 MHz frequency selected. This oscillator is selected as the source of MAINCK. MAINCK is the default clock selected to start the system. Only the 8/12 MHz RC oscillator frequencies are calibrated in production. Refer to Section 56.2 ”DC Characteristics”. The software can disable or enable the 4/8/12 MHz RC oscillator with the MOSCRCEN bit in the Clock Generator Main Oscillator register (CKGR_MOR). XIN XOUT MOSCXTEN MOSCXTST MOSCXTS Main Clock Frequency Counter MAINF SLCK Slow Clock Main Crystal or Ceramic Resonator Oscillator Main Oscillator Counter MOSCRCEN Fast RC Oscillator MOSCRCS MOSCRCF MOSCRCEN MOSCXTEN MOSCSEL MOSCSEL MOSCSELS MAINCK Main Clock MAINCK Main Clock Ref. RCMEAS CKGR_MCFR CKGR_MOR CKGR_MOR CKGR_MOR PMC_SR PMC_SR CKGR_MOR CKGR_MOR CKGR_MOR CKGR_MOR CKGR_MOR CKGR_MCFR PMC_SR CKGR_MCFR MAINFRDY

281SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 The output frequency of the RC oscillator can be selected among 4, 8 or 12 MHz. Selection is done by configuring the field MOSCRCF in CKGR_MOR. When changing the frequency selection, the MO SCRCS bit in the Power Management Controller Status register (PMC_SR) is automatically cleared and MAINCK is stopped until the oscillator is stabilized. Once the oscillator is stabilized, the main clock restarts and PMC_SR.MOSCRCS is set. When disabling the main clock by clearing the CKGR_MOR.MOSCRCEN bit, the PMC_SR.MOSCRCS bit is automatically cleared, indicating the main clock is off. Setting the MOSCRCS bit in the Power Management Controller Interrupt Enable register (PMC_IER) triggers an interrupt to the processor. When the main clock (MAINCK) is not used to drive the processor and the frequency monitor (SLCK is used instead), it is recommended to disable the 4/8/12 MHz RC oscillator and 3 to 20 MHz crystal oscillator. The user can adjust the value of the fast RC oscillator frequency by modifying the trimming values done in production by Atmel on 8 MHz and 12 MHz. Refer to Section 30.5.2 ”4/8/12 MHz RC Oscillator Clock Frequency Adjustment”. The values stored in the Flash cannot be erased by a Flash erase command or by the ERASE pin. Values written by the user application in PMC_OCR are reset after each power-up or peripheral reset. 30.5.2 4/8/12 MHz RC Oscillat or Clock Frequency Adjustment The user can adjust the 4/8/12 MHz RC os cillator frequency in PMC_OCR. By default, SEL4/8/12 are cleared, so the RC oscillator will be driven with Flash calibration bits which are programmed during chip production. The user can adjust the trimming of the 4/8/12 MHz fast RC oscillator through this register to obtain more accurate frequency and to compensate derating factors such as temperature and voltage. In order to calibrate the oscillator lower frequency, SEL4 must be set to ‘1’ and a valid frequency value must be configured in CAL4. Likewise, SEL8/12 must be set to ‘1’ and a trim value must be configured in CAL8/12 in order to adjust the other frequencies of the oscillator. It is possible to adjust the oscillator frequency while operating from this clock. For example, when running on lowest frequency it is possible to change the CAL4 value if SEL4 is set in PMC_OCR. At any time, it is possible to restart a measurement of the frequency of the selected clock via the RCMEAS bit in Main Clock Frequency register (CKGR_MCFR). Thus, when CKGR_MCFR.MAINFRDY flag reads 1, another read access on CKGR_MCFR provides an image of the frequen cy of the main clock on CKGR_MCFR.MAINF. The software can calculate the error with an expect ed frequency and correct the CAL4, CAL8 and CAL12 fields accordingly. This may be used to compensate frequency drift due to derating factors such as temperature and/or voltage. 30.5.3 3 to 20 MHz Crystal or Ceramic Resonator-based Oscillator After reset, the 3 to 20 MHz crystal or ceramic resonator-based oscillator is disabled and is not selected as the source of the main clock. As the source of MAINCK, the 3 to 20 MHz crystal or ce ramic resonator-based oscillator provides a very precise frequency. The software enables or di sables this oscillator in order to reduce power consumption via CKGR_MOR.MOSCXTEN. When disabling this oscillator by clearing the CK GR_MOR.MOSCXTEN, PMC_SR.MOSCXTS is automatically cleared, indicating the 3 to 20 MHz crystal oscillator is off. When enabling this oscillator, the user must initiate the start-up time counter. The start-up time depends on the characteristics of the external device connected to this oscillator. When CKGR_MOR.MOSCXTEN and CKGR_M OR.MOSCXTST are written to enable this oscillator, the XIN and XOUT pins are automatically switched into Oscillator mode. PMC_SR.MOSCXTS is cleared and the counter starts counting down on the slow clock divided by 8 from the CKGR_MOR.MOSCXTST value. Since the CKGR_MOR.MOSCXTST value is coded with 8 bits, the maximum start-up time is about 62 ms.

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 282 When the start-up time counter reaches 0, PMC_SR.MOS CXTS is set, indicating that the 3 to 20 MHz crystal oscillator is stabilized. Setting the MOSCXTS bit in the Interrupt Mask register (PMC_IMR) can trigger an interrupt to the processor.

30.5.4 Main Clock Source Selection

The user can select the source of the main clock from ei ther the 4/8/12 MHz fast RC oscillator, the 3 to 20 MHz crystal oscillator or the ceramic resonator-based oscillator. The advantage of the 4/8/12 MHz fast RC oscillator is its fast start-up time. By default, this oscillator is selected to start the system. The 4/8/12 MHz fast RC oscillator must be selected when entering Wait mode. The advantage of the 3 to 20 MHz crystal oscillator or ceramic resonator-based oscillator is the high level of accuracy provided. The selection of the oscillator is ma de by writing CKGR_MOR.MOSCSEL. The s witch of the main clock source is glitch-free, so there is no need to run out of SLCK , PLLACK or PLLBCK or UPLLCK in order to change the selection. PMC_SR.MOSCSELS indicates when the switch sequence is done. Setting PMC_IMR.MOSCSELS triggers an interrupt to the processor. Enabling the 4/8/12 MHz RC oscillator (MOSCRCEN = 1) and changing its frequency (MOSCCRF) at the same time is not allowed. This oscillator must be enabled first and its frequency changed in a second step.

30.5.5 Bypassing the Main Crystal Oscillator

Prior to bypassing the 3 to 20 MHz crystal oscillator, the external clock frequency provided on the XIN pin must be stable and within the values specified in the XIN Clock characteristics in the section “Electrical Characteristics”. The sequence is as follows: 1. Ensure that an external clock is connected on XIN. 2. Enable the bypass by setting CKGR_MOR.MOSCXTBY. 3. Disable the 3 to 20 MHz oscillator by clearing the bit CKGR_MOR.MOSCXTEN.

30.5.6 Main Clock Frequency Counter

The frequency counter is managed by CKGR_MCFR. During the measurement period, the frequency counter increments at the speed of the clock defined by the bit CKGR_MCFR.CCSS. A measurement is started in the following cases:  When the RCMEAS bit of CKGR_MCFR is written to 1.  When the 4/8/12 MHz RC oscillator is selected as the source of main clock and when this oscillator becomes stable (i.e., when the MOSCRCS bit is set)  When the 3 to 20 MHz crystal or ceramic resonator-based oscillator is selected as the source of main clock and when this oscillator becomes stable (i.e., when the MOSCXTS bit is set)  When the main clock source selection is modified The measurement period ends at the 16th falling edge of slow clock, the MAINFRDY bit in CKGR_MCFR is set and the counter stops counting. Its value can be read in the MAINF field of CKGR_MCFR and gives the number of clock cycles during 16 periods of slow clock, so that the frequency of the 4/8/12 MHz RC oscillator or 3 to 20 MHz crystal or ceramic resonator-based oscillator can be determined.

283SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

30.5.7 Switching Main Clock between the RC Oscillator and Crystal Oscillator

When switching the source of the ma in clock between the RC oscillator and t he crystal oscillator, both oscillators must be enabled. After completion of the switch, the unused oscillator can be disabled. If switching to the crystal oscillator, follow the programming sequence below to ensure that the oscillator is present and that its frequency is valid: 1. Enable the crystal oscillator by setting CKGR_M OR.MOSCXTEN. Configure the CKGR_MOR. MOSCXTST field with the crystal oscillator start-up time as defined in the section “Electrical Characteristics”. 2. Wait for PMC_SR.MOSCXTS flag to rise, indicating the end of a start-up period of the crystal oscillator. 3. Select the crystal oscillator as the source clock of th e frequency meter by setting CKGR_MCFR.CCSS. 4. Initiate a frequency measurement by setting CKGR_MCFR.RCMEAS. 5. Read CKGR_MCFR.MAINFRDY until its value equals 1. 6. Read CKGR_MCFR.MAINF and compute the value of the crystal frequency. 7. If the MAINF value is valid, the main clock can be switched to the 3 to 20 MHz crystal oscillator.

30.6 Divider and PLL Block

The device features one divider/one PLL block that permits a wide range of frequencies to be selected on either the master clock, the processor clock or the programm able clock outputs. Additiona lly, they provide a 48 MHz signal to the embedded USB device port regardless of the frequency of the main clock. Figure 30-4 shows the block diagram of the dividers and PLL blocks. Figure 30-4. Divider and PLL Block Diagram

30.6.1 Divider and Phase Lock Loop Programming

The divider can be set between 1 and 255 in steps of 1. When a divider field (DIV) is cleared, the output of the corresponding divider and the PLL output is a continuous signal at level 0. On reset, each DIV field is cleared, thus the corresponding PLL input clock is stuck at 0. The PLL (PLLA) allows multiplication of the divider’s outputs. The PLL clock signal has a frequency that depends on the respective source signal frequency and on the parameters DIV (DIVA) and MUL (MULA). The factor applied to the source signal frequency is (MUL + 1)/DIV. When MUL is written to ‘0’ or DIV=0, the PLL is disabled and its power consumption is saved. Note that there is a del ay of two SLCK clock cycle s between the disable command and the real disable of the PLL. Re-enabling the PLL can be performed by writing a value higher than 0 in the MUL field and DIV higher than 0. Whenever the PLL is re-enabled or one of its parame ters is changed, the LOCK (LOCKA) bit in PMC_SR is automatically cleared. The values written in the PLLCOUNT field (PLLACOUNT) in CKGR_PLLR (CKGR_PLLAR) are loaded in the PLL counter. The PLL counter then decrem ents at the speed of SLCK until it reaches 0. At this Divider DIVA PLLA MULA PLLACOUNT LOCKASLCK MAINCK PLLACK PLLA Counter CKGR_PLLAR CKGR_PLLAR CKGR_PLLAR PMC_SR

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 284 time, PMC_SR.LOCK is set and can trigger an interrupt to the processor. The user has to load the number of slow clock cycles required to cover the PLL transient time into the PLLCOUNT field. To avoid programming the PLL with a multiplication factor th at is too high, the user can saturate the multiplication factor value sent to the PLL by setting the PLLA_MMAX field in PMC_PMMR. It is prohibited to change the 4/8/12 MHz fast RC oscillator or the main oscillator selection in CKGR_MOR while the master clock source is the PLL and the PLL reference clock is the fast RC oscillator. The user must: 1. Switch on the main RC oscillator by writing a ‘1’ to PMC_MCKR.CSS. 2. Change the frequency (MOSCRCF) or osc illator selection (MOSCSEL) in CKGR_MOR. 3. Wait for MOSCRCS (if frequency ch anges) or MOSCSELS (if oscillator selection changes) in PMC_SR. 4. Disable and then enable the PLL. 5. Wait for the LOCK flag in PMC_SR. 6. Switch back to the PLL by writing the appropriate value to PMC_MCKR.CSS.

30.7 UTMI Phase Lock Loop Programming

The source clock of the UTMI PLL is the 3 to 20 MHz crystal oscillator. Figure 30-5. UTMI PLL Block Diagram Whenever the UTMI PLL is enabled by writing UPLLEN in UTMI Clock register (CKGR_UCKR), the LOCKU bit in PMC_SR is automatically cleared. Th e values written in the PLLCOUNT field in CKGR_UCKR are loaded in the UTMI PLL counter. The UTMI PLL counte r then decrements at the speed of the slow clock divided by 8 until it reaches 0. At this time, the LOCKU bit is set in PMC_SR and can trigger an interrupt to the processor. The user has to load the number of slow clock cycles required to cover the UTMI PLL transient time into the PLLCOUNT field. UTMI PLL UPLLEN UPLLCOUNT LOCKUSLCK MAINCK UPLLCK UTMI PLL Counter CKGR_UCKR PMC_SR CKGR_UCKR

285SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 31. Power Management Controller (PMC)

31.1 Description

The Power Management Controller (PMC) optimizes power consumption by controlling all system and user peripheral clocks. The PMC enables/disables the clock inputs to many of the peripherals and the Cortex-M7 processor. The Supply Controller sele cts either the embedded 32 kHz RC oscillator or the 32.768 kH z crystal oscillator. The unused oscillator is disabled automatically so that power consumption is optimized. By default, at startup, the chip runs out of the master clock using the 4/8/12 MHz RC oscillator running at 4 MHz. The user can trim the 4/8/12 MHz RC oscillator frequencies by software.

31.2 Embedded Characteristics

The Power Management Controller provides the following clocks:  MCK, the Master Clock, programmable from a few hundred Hz to the maximum operating frequency of the device. It is available to the modules running permanently, such as the Enhanced Embedded Flash Controller.  Processor Clock (HCLK), automatically switched off when entering the processor in Sleep Mode.  Free-running processor Clock (FCLK)  the Cortex-M7 SysTick external clock  USB Clock (USBCK), required by USB Device Port operations.  Peripheral Clocks, provided to the embedded peripherals (USART, SPI, TWI, TC, etc.) and independently controllable.  Programmable Clock Outputs (PCKx), selected from the clock generator outputs to drive the device PCK pins.  Clock sources independent of MCK and HCLK, provided by internal PCKx for USART, UART, and TC  Generic Clock (GCLK) independent of MCK and HCLK  Embedded Trace Macrocell (ETM) and CAN Clocks, provided by internal PCKx clocks The Power Management Controller also provides the following features on clocks:  A 3 to 20 MHz crystal oscillator clock failure detector.  A 32.768 kHz crystal oscillator frequency monitor.  A frequency counter on 3 to 20 MHz crystal oscillator or 4/8/12 MHz RC oscillator  An on-the-fly adjustable 4/8/12 MHz RC oscillator frequency

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 286

31.3 Block Diagram

Figure 31-1. General Clock Block Diagram

31.4 Master Clock Controller

The Master Clock Controller provides selection and division of the master clock (MCK). MCK is the source clock of the peripheral clocks. MCK is selected from one of the clocks provided by the Clock Generator. Selecting the slow clock (SLCK) provides a slow clock signal to the whole device. Selecting the main clock saves power consumption of the PLLs. The Master Clock Controller is made up of a clock selector and a prescaler. MCK is selected by configuring PMC_MCKR.CSS. The presc aler supports the division by a power of 2 of the selected clock between 1 and 64, and the division by 3. The prescaler is configured using PMC_MCKR.PRES. Each time PMC_MCKR is written to define a new master clock, the MCKRDY bit is cleared in PMC_SR. It reads ‘0’ until the master clock is established. Then, the MCKRDY bit is set and can trigger an interrupt to the processor. This feature is useful when switching from a high-speed clock to a lower one to inform the software when the change is completed. Power Management Controller Main Clock MAINCK PLLA Clock PLLACK ControlStatus 3-20 MHz Crystal or Ceramic Resonator Oscillator PLLA XIN XOUT XIN32 XOUT32 SLCK (Supply Controller) Embedded 32 kHz RC Oscillator 32768 Hz Crystal Oscillator UPLL Clock UPLLCK int SLCK MAINCK PLLACK Prescaler /1,/2,/3,/4,/8, /16,/32,/64 HCLK Processor Clock Controller Sleep Mode Master Clock Controller (PMC_MCKR) USB FS Clock Prescaler pck[..] FCLK SysTick External Clock Divider SLCK MAINCK PLLACK Processor Clock Free Running Clock MCK Master Clock USB UTMI PLL Embedded 4/8/12 MHz RC Oscillator Programmable Clock Controller (PMC_PCKx) PRES PRESCSS CSS Divider /1, /2 USB_48M UPLLDIV2 Divider /1,/2,/3,...,/16 USB Clock Controller (PMC_USB) USBDIVUSBS UPLLCKDIV USB_480M USB HS Clock PLLACK MCK Slow Clock Clock Generator XTALSEL PMC_MCKR MOSCSEL CKGR_MOR (PMC_SCER/SCDR) /1 to /256 granularity=1 /1, /2, /3, /4 Divider MDIV periph_clk[PID] Peripheral Clock Controller (PMC_PCR) EN(PID) PCKx USBCLK UPLLCKDIV UPLLCKDIV MCK PLLACK UPLLCK MAINCK SLCK GCLKCSS(PID) Prescaler /1,/2,/3,...,/256 GCLKDIV(PID) GCLK[PID] GCLKEN(PID)

287SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

31.5 Processor Clock Controller

The PMC features a Processor Clock (HCLK) Controller that implements the processor Sleep mode. HCLK can be disabled by executing the WFI (WaitForInterrupt) or the WFE (WaitForEvent) processor instruction while the LPM bit is at 0 in the PMC Fast Startup Mode register (PMC_FSMR). HCLK is enabled after a reset and is automatically re-enabled by any enabled interrupt. The processor Sleep mode is entered by disabling the processor clock, which is automatically re-enabled by any enabled fast or normal interrupt, or by the reset of the product. When processor Sleep mode is entered, the current instruction is finish ed before the clock is stopped, but this does not prevent data transfers from other masters of the system bus.

31.6 SysTick External Clock

When the processor selects the SysTick external clock, the calibration value is fixed to 37500. This allows the generation of a time base of 1 ms with the SysTick clock at the maximum frequency on MCK divided by 8. Refer to Section 14. ”ARM Cortex-M7 Processor” for details on selecting the SysTick external clock.

31.7 USB Clock Controller

The user can select the PLLA or the UPLL output as the USB source clock by writing the USBS bit in PMC_USB. If using the USB, the user must program the PLL to generate an appropriate frequency depending on the USBDIV bit in the USB Clock register (PMC_USB). When PMC_SR.LOCKA and PMC_SR.LOCKU are set to ‘1’, the PLLA and UPLL are stable. Then, the USB FS clock can be enabled by setting the USBCLK bit in the System Clock Enable register (PMC_SCER). To save power on this peripheral when not used, the user can set the USBCLK bit in the System Clock Disable register (PMC_SCDR). The USBCLK bit in the System Clock Status register (PMC_SCSR) gives the status of this clock. The USB port requires both the USB clock signal and the pe ripheral clock. The USB peripheral clock is controlled by means of the Master Clock Controller.

31.8 Peripheral Clock Controller

The PMC controls the clocks of the embedded peripher als by means of the Peripheral Control register (PMC_PCR). With this register, the user can enable and disable the clock of each peripheral. This register is also used to enable, disable and configure the GCLK of I2SC0 and I2SC1. GCLK is independent of MCK and HCLK. To configure the clocks of a peripheral, PMC_PCR.CMD must be written to ‘1’ and PMC_PCR.PID must be written with the index of the corresponding peripheral. All other configuration fields must be correctly set. To read the current clock configuration of a peripheral, PMC_PCR.CMD must be written to ‘0’ and PMC_PCR.PID must be written with the index of the corresponding peripheral regardless of the values of other fields. This write does not modify the configuration of the peripheral. The PMC_PCR register can then be read to know the configuration status of the corresponding PID. The user can also enable and disable these clocks by writing Peripheral Clock Enable (PMC_PCERx) and Peripheral Clock Dis able (PMC_PCDRx) register s. The status of the peripheral cl ock activity can be read in the Peripheral Clock Status registers (PMC_PCSRx). When the peripheral clock is disabled, it is immediately stopped. The peripheral clocks are automatically disabled after a reset. To stop a peripheral clock, it is recommended that the system software wait until the peripheral has executed its last programmed operation before disabling the clock. This is to avoid data corruption or erroneous behavior of the system.

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 288 The bit number in PMC_PCERx, PMC_PCDRx, and PMC_ PCSRx is the Peripheral Identifier defined at the product level. The bit number corresponds to the interrupt source number assigned to the peripheral.

31.9 Asynchronous Partial Wake-up

31.9.1 Description

The asynchronous partial wake-up wakes up a peripheral in a fully asynchronous way when activity is detected on the communication line. The asynchronous partial wake-up function automatically manages the peripheral clock. It reduces overall power consumption of the system by clocking peripherals only when needed. Asynchronous partial wake-up can be enabled in Wait mode (SleepWalking), or in Active mode. Only the following peripherals can be configured with asynchronous partial wake-up: UARTx and TWIHSx. The peripheral selected for asynchronous partial wake-up must first be configured so that its clock is enabled. To do so, write a ‘1’ to the appropriate PIDx bit in PMC_PCER registers.

31.9.2 Asynchronous Partial Wake-u p in Wait Mode (SleepWalking)

When the system is in Wait mode, all clocks of t he system (except SLCK) are stopped. When an asynchronous clock request from a peripheral occu rs, the PMC partially wakes up the syst em to feed the clock only to this peripheral. The rest of the system is not fed with the clock, thus optimizing power consumption. Finally, depending on user-configurable conditions, the per ipheral either wakes up the whole system if these conditions are met or stops the peripheral clock until the next clock request. If a wake-up request occurs, SleepWalking is automatically disabled until the user instructs the PMC to enable SleepWalk ing. This is done by writing a ‘1’ to PIDx in the PMC SleepWalking Enable register (PMC_SLPWK_ER). Figure 31-2. SleepWalking Waveforms

31.9.2.1 Configuration Procedure

Before configuring SleepWalking for a peripheral, check that the PIDx bit in PMC_PCSR is set. This ensures that the peripheral clock is enabled. To enable SleepWalking for a peripheral, follow the steps below: 1. Check th at the corresponding PIDx bit in the PMC SleepWalking Activity Status register (PMC_SLPWK_ASR) is set to ‘0’. This ensures that the peripheral has no activity in progress. 2. Enable SleepWalking for the peripheral by writing a ‘1’ to the corresponding PIDx bit in the PMC_SLPWK_ER. 3. Check that the corresponding PIDx bit in PMC_SLPWK_ASR is set to ‘0’. This ensures that no activity has started during the enable phase. 4. In the PMC_SLPWK_ASR, if the corres ponding PIDx bit is set, SleepWalking must be immediately disabled by writing a ‘1’ to the PIDx bit in the PMC SleepWalking Disable register (PMC_SLPWK_DR). Wait for the system_clock peripheral_clock peripheral clock request peripheral wakeup request peripheral sleepwalking status The wakeup request wakes up the system and resets the sleepwalking status of the peripheral The system is in wait mode. No clock is fed to the system.

289SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 end of peripheral activity before reinitializing the procedure. If the corresponding PIDx bit is set to ‘0’, then the peripheral clock is disabled and the system can now be placed in Wait mode. Before entering Wait mode, check that the AIP bit in the PMC SleepWalking Activity In Progress register (PMC_SLPWK_AIPR) is cleared. This ensures that none of the peripherals is currently active. Note: When SleepWalking for a peripheral is enabled and the core is running (system not in Wait mode), the peripheral must not be accessed before a wake-up of the peripheral is performed.

31.9.3 Asynchronous Partial Wake-Up in Active Mode

When the system is in Active mode, peripherals enabled for a synchronous partial wake-u p have their respective clocks stopped until the peripherals request a clock. When a peripheral requests the cl ock, the PMC provides the clock without processor intervention. The triggering of the peripheral clock request depends on conditions which can be configured for each peripheral. If these conditions are met, the peripheral asserts a request to the PMC. The PMC disables the Asynchronous Partial Wake-up mode of the peripheral and provides the clock to the peripheral until the user instructs the PMC to re-enable partial wake-up on the peripheral. This is done by setting PMC_SLPWK_ER.PIDx. If the conditions are not me t, the peripheral clears the clock request an d the PMC stops the peripheral clock until the clock request is re-asserted by the peripheral. Note: Configuring Asynchronous Partial Wake-up mode requires the same registers as SleepWalking mode. Figure 31-3. Asynchronous Partial Wake-up in Active Mode

31.9.3.1 Configuration Procedure

Before configuring the asynchronous partial wake-up function of a peri pheral, check that the PIDx bit in PMC_PCSR is set. This ensures that the peripheral clock is enabled. To enable the asynchronous partial wake-up function of a peripheral, follow the steps below: 1. Check th at the corresponding PIDx bit in the PMC SleepWalking Activity Status register (PMC_SLPWK_ASR) is set to ‘0’. This ensures that the peripheral has no activity in progress. 2. Enable the asynchronous partial wake-up function of the peripheral by writing a ‘1’ to the corresponding PIDx bit in the PMC_SLPWK_ER. 3. Check that the corresponding PIDx bit in PMC_SLPWK_ASR is set to ‘0’. This ensu res that no activity has started during the enable phase. If an activity has started during the enable phase, the asynchronous partial wake-up function must be immediately disabled by writing a ‘1’ to the PIDx bit in the PMC SleepWalking Disable register (PMC_SLPWK_DR). Wait for the end of peripheral activity before reinitializing the procedure. system_clock peripheral_clock Peripheral clock request Peripheral wakeup request Peripheral SleepWalking status The wakeup request resets the SleepWalking status of the peripheral

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 290

31.10 Free-Running Processor Clock

The free-running processor clock (FCLK) used for sampli ng interrupts and clocking debug blocks ensures that interrupts can be sampled, and sleep events can be traced, while the processor is sleeping.

31.11 Programmable Clock Output Controller

The PMC controls three signals to be output on the external pins PCKx. Each signal can be independently programmed via the Programmable Clock registers (PMC_PCKx). PCKx can be independently selected between the slow clo ck (SLCK), the main clock (MAINCK), the PLLA clock (PLLACK), UTMI PLL clock divided by 1 or 2 (UPLLCKDIV) and the master clock (MCK) by configuring PMC_PCKx.CSS. Each output signal can also be divi ded by a power of 2 between 1 and 64 by configuring PMC_PCKx.PRES. Each output signal can be enabled and disabled by wr iting 1 in the correspondi ng PMC_SCER.PCKx and PMC_SCDR.PCKx, respectively. Status of the active programmable output clocks are given in PMC_SCSR.PCKx The status flag PMC_SR.PCKRDYx indicates that the programmable clock is actually what has been programmed in registers PMC_PCKx. As the Programmable Clock Controller does not manage with glitch prevention when switching clocks, it is strongly recommended to disable the programmable clock before any configuration change and to re-enable it after the change is performed.

31.12 Core and Bus Independe nt Clocks for Peripherals

Table 31-1 lists the peripherals that can operate while the core, bus and peripheral clock frequencies are modified, thus providing communications at a rate which is independent for the core/bus/peripheral clock. This mode of operation is possible by using the internally generated independent clock sources. Internal clocks can be independently selected between the slow clock (SLCK), the main clock (MAINCK), any available PLL clock, and the master clock (MCK) by configuring PMC_PCKx.CSS. The independent clock sources can be also divided by configuring PMC_PCKx.PRES. Each internal clock signal (PCKx) can be enabled and disabled by writing a ‘1’ to the corresponding PMC_SCER.PCKx and PMC_SCDR.PCKx, respectively. Th e status of the internal clocks are given in PMC_SCSR.PCKx. The status flag PMC_SR.PCKRDYx indi cates that the programmable internal clock has been programmed in the programmable clock registers. The independent clock source must also be selected in each peripheral in Table 31-1 to operate communications, timings, etc without influencing the frequency of the core/bus/peripherals (except frequency limitations listed in each peripheral).

31.13 Fast Startup

At exit from Wait mode, the device allows the processor to restart in less than 10 microseconds only if the C-code function that manages the Wait mode entry and exit is linked to and executed from on-chip SRAM. Table 31-1. Clock Assignment Clock Name Peripheral PCK3 ETM PCK4 UART/USART PCK5 CAN PCK6 TC

291SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 The fast startup time cannot be achieved if the first instruction after an exit is located in the embedded Flash. If fast startup is not required, or if the first instruction after exit from Wait mode is located in embedded Flash, see Section 31.14 ”Startup from Embedded Flash”. Prior to instructing the device to enter Wait mode: 1. Select the 4/8/12 MHz RC oscillator as the master clock source by configuring PMC_MCKR.CSS to ‘1’. 2. Disable the PLL if enabled. 3. Wait for two SLCK clock cycles. 4. Clear the internal wake-up sources. 5. Verify that none of the enabled external wake-up inputs (WKUP) hold an active polarity. The system enters Wait mo de either by setting the WAITMODE bit in CKGR_MOR, or by executing the WaitForEvent (WFE) instruction of the processor while the LPM bit is at ‘1’ in PMC_FSMR. Immediately after setting the WAITMODE bit or using the WFE instruction, wait for the MCKRDY bit to be set in PMC_SR. A fast startup is enabled upon the detection of a program med level on one of the 14 wake-up inputs (WKUP) or upon an active alarm from the RTC, RTT and USB Controller. The polarity of the 14 wake-up inputs is programmable by writing the PMC Fast Startup Polarity register (PMC_FSPR). WARNING: The duration of the WKUPx pins active level must be greater than four main clock cycles. The fast startup circuitry, as shown in Figure 31-4, is fully asynchronous and provides a fast startup signal to the PMC. As soon as the fast startup signal is asserted, the embedded 4/8/12 MHz RC oscillator restarts automatically. When entering Wait mode, the embedded Flash can be placed in one of the low-power modes (Deep-power-down or Standby mode) with PMC_FSMR.FLPM. FLPM can be configured at any time and its value will be applied to the next Wait mode period. The power consumption reduction is optimal when PMC_ FSMR.FLPM is configured to ‘1’ (Deep-power-down mode). If the field is configured to ‘0’ (Standby mode), the power consumption is slightly higher than in Deep- power-down mode. When PMC_FSMR.FLPM is configured to ‘2’, the Wait mode Flash power consumption is equivalent to that of the Active mode when there is no read access on the Flash.

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 292 Figure 31-4. Fast Startup Circuitry Each wake-up input pin and alarm can be enabled to generate a fast startup event by setting the corresponding bit in PMC_FSMR. The user interface does not provide any status for fast st artup. The status can be read in the PIO Controller and the status registers of the RTC, RTT and USB Controller.

31.14 Startup from Embedded Flash

The inherent start-up time of the embedded Flash cannot provide a fast startup of the system. If system fast start-up time is not required, the first in struction after a Wait mode exit can be located in the embedded Flash. Under these conditions, prior to entering Wait mode, the Flash controller must be programmed to perform access in 0 wait-state (refer to Section 21. ”Enhanced Embedded Flash Controller (EEFC)”). The procedure and conditions to enter Wait mode and the circ uitry to exit Wait mode ar e strictly the same as fast startup (see Section 31.13 ”Fast Startup”).

31.15 Main Clock Failure Detection

The clock failure detector monitors t he 3 to 20 MHz crystal oscillator or ceramic resonator- based oscillator to identify a failure of this oscillator when selected as main clock. fast_restart GMAC Wake on LAN event FSTT14 FSTP14 WKUP13 FSTT13 FSTP13 WKUP0 FSTT0 FSTP0 RTTAL RTCAL USBAL RTT Alarm RTC Alarm FSTT15 FSTP15 Processor CDBGPWRUPREQ USBHS Interrupt Line

293SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 The clock failure detector can be enabled or disabled by configuring CKGR_MOR .CFDEN. After a VDDCORE reset, the detector is disabled. Howe ver, if the oscillator is disabled (M OSCXTEN = 0), the detector is also disabled. To initialize the clock failure detector, follow the sequence below: 1. The 4/8/12 MHz RC o scillator must be selected as the source of MAINCK. 2. MCK must select MAINCK. 3. Enable the clock failure detect or by writing a ‘1’ to CFDEN. 4. PMC_SR must be read two slow clock cycles after enabling the clock failure detector. The value read is meaningless. The clock failure detector is now initialized and MCK can select another clock source by configuring PMC_MCKR.CSS. A failure is detected by means of a counter incrementing on the main clock and detection logic is triggered by the 32 kHz (typical) RC oscillator which is automatically enabled when CFDEN=1. The counter is cleared when the 32 kHz (typical) RC osci llator clock signal is low and enabled when the signal is high. Thus, the failure detection time is one RC oscillator period. If, duri ng the high level period of the 32 kHz (typical) RC oscillator clock signal, less than eight 3 to 20 MHz crystal oscillator clock periods have been counted, then a failure is reported. If a failure of the main clock is de tected, PMC_SR.CFDEV indicates a failure event and generates an interrupt if the corresponding interrupt source is enabled. The interrupt remains active until a read occurs in PMC_SR. The status of the clock failure detection can be read at any time from PMC_SR.CFDS. Figure 31-5. Clock Failure Detection Example If the 3 to 20 MHz crysta l oscillator or ceramic resonator-based oscillator is selected as the source clock of MAINCK (CKGR_MOR.MOSCSEL = 1), and if MCK source is PLLACK or UPLLCKDIV (CSS = 2 or 3), a clock failure detection automatically forces the MAINCK to be the source cl ock for the master clock MCK. Then, regardless of the PMC configuration, a clock failure detection automatically forces the 4/8/12 MHz RC oscillator to be the source clock for MAINCK. If the fast RC oscillator is disabled when a clock failure detection occurs, it is automatically re-enabled by the clock failure detection mechanism. It takes two 32 kHz (typical) RC oscillator clock cycles to detect and switch from the 3 to 20 MHz crystal oscillator, to the 4/8/12 MHz RC oscillator if the source master clock (MCK) is main clock (MAINCK), or three 32 kHz (typical) RC oscillator clock cycles if the source of MCK is PLLACK or UPLLCKDIV. A clock failure detection activates a fault output that is connected to the Pulse Width Modulator (PWM) Controller. With this connection, the PWM controller is able to forc e its outputs and to protect the driven device, if a clock failure is detected. The user can know the status of the clock failure detector at any time by reading the FOS bit in PMC_SR. Main Crytal Clock SLCK Note: ratio of clock periods is for illustration purposes only CDFEV CDFS Read PMC_SR

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 294 This fault output remains active until the defect is detected and until it is cleared by the bit FOCLR in the PMC Fault Output Clear register (PMC_FOCR). 31.16 32.768 kHz Crystal Osci llator Frequency Monitor The frequency of the 32.768 kHz crystal oscillator can be monitored by means of logic driven by the 4/8/12 MHz RC oscillator known as a reliable clock source. This function is enabled by configuring the XT32KFME bit of CKGR_MOR. The SEL4/SEL8/SEL12 bits of PMC_OCR must be cleared. An error flag (XT32KERR in PMC_SR) is asserted when th e 32.768 kHz crystal oscillator frequency is out of the ±10% nominal frequency value (i.e. 32.768 kHz). The erro r flag can be cleared only if the slow clock frequency monitoring is disabled. When the 4/8/12 MHz RC oscillator frequency is 4 MHz, the accuracy of the measurement is ±40% as this frequency is not trimmed during production. Therefore, ±10% accuracy is obtained only if the RC oscillator frequency is configured for 8 or 12 MHz. The monitored clock frequency is declared invalid if at l east 4 consecutive clock period measurement results are over the nominal period ±10%. Due to the possible frequency variation of the 4/8/12 MHz RC oscillator acting as reference clock for the monitor logic, any 32.768 kHz crystal frequency deviation over ±10% of the nominal frequency is systematically reported as an error by means of XT32KERR in PMC_SR. Between -1% and -10% and +1% and +10%, the error is not systematically reported. Thus only a crystal running at 32.768 kHz frequency ensures that the error flag will not be asserted. The permitted drift of the crystal is 10000ppm (1%), which allows any standard crystal to be used. If the 4/8/12 MHz RC oscillator frequency needs to be changed while the slow clock frequency monitor is operating, the monitoring must be stopped prior to change the 4/8/12 MHz RC oscillator frequency. Then it can be re-enabled as soon as MOSCRCS is set in PMC_SR. The error flag can be defined as an interrupt source of the PMC by setting the XT32KERR bit of PMC_IER.

31.17 Programming Sequence

1. If the 3 to 20 MHz crystal oscillator is not required, the PLL and divider can be directly configured (Step 6.) else this oscillator must be started (Step 2.). 2. Enable the 3 to 20 MHz crystal oscillator by sett ing CKGR_MOR.MOSCXTEN. The user can define a start- up time. This can be achieved by writing a value in the CKGR_MOR.MOSCXTST. Once this register has been correctly configured, the user must wait for PMC_SR.MOSCXTS to be set. This can be done either by polling PMC_SR.MOSCXTS, or by waiting for the interrupt line to be raised if the associated interrupt source (MOSCXTS) has been enabled in PMC_IER. 3. Switch the main clock to the 3 to 20 MHz cr ystal oscillator by setting CKGR_MOR.MOSCSEL. 4. Wait for PMC_SR.MOSCSELS to be set to ensure the switchover is complete. 5. Check the main clock frequency: This frequency can be measured via CKGR_MCFR. Read CKGR_MCFR until the MAINFRDY field is set, after which the user can read CKGR_MCFR.MAINF by performing an additional read. This provides the number of main clock cycles that have been counted during a period of 16 slow clock cycles. If MAINF = 0, switch the main clock to the 4/8/12 RC Oscillator by clearing CKGR_MOR.MOSCSEL. If MAINF ≠ 0, proceed to Step 6. 6. Set PLLx and Divider (if not required, proceed to Step 7.): In the names PLLx, DIVx, MULx, LOCKx, PLLxCOUNT, and CKGR_PLLxR, ‘x’ represents A.

295SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 All parameters needed to configure PLLx and the divider are located in CKGR_PLLxR. CKGR_PLLxR.DIVx is used to control the divider itself. This parameter can be programmed between 0 and 127. Divider output is divider input divided by DIVx parameter. By default, DIVx field is cleared which means that the divider and PLLx are turned off. CKGR_PLLxR.MULx is the PLLx multiplier factor. This parameter can be programmed between 0 and 62. If MULx is cleared, PLLx will be turned off, otherwise the PLLx output frequency is PLLx input frequency multiplied by (MULx + 1). CKGR_PLLxR.PLLxCOUNT specifies the number of slow clock cycles before PMC_SR.LOCKx is set after CKGR_PLLxR has been written. Once CKGR_PLLxR has been written, the user must wait for PMC_SR.LOCKx to be set. This can be done either by polling PMC_SR.LOCKx or by waiting for the interrupt line to be raised if the associated interrupt source (LOCKx) has been enabled in PMC_IER. All fields in CKGR_PLLxR can be programmed in a single write operation. If MULx or DIVx is modified, the LOCKx bit goes low to indicate that PLLx is not yet ready. When PLLx is locked, LOCKx is set again. The user must wait for the LOCKx bit to be set before using the PLLx output clock. 7. Select the master clock and processor clock: The master clock and the processor clock are configurable via PMC_MCKR. PMC_MCKR.CSS is used to select the clock source of the master clock and processor clock dividers. By default, the selected clock source is the main clock. PMC_MCKR.PRES is used to define the processor clock and master clock prescaler. The user can choose between different values (1, 2, 3, 4, 8, 16, 32, 64). Prescaler output is the selected clock source frequency divided by the PRES value. PMC_MCKR.MDIV is used to define the master clock divider. It is possible to choose between different values (0, 1, 2, 3). The master clock output is the processor clock frequency divided by 1, 2, 3 or 4, depending on the value programmed in MDIV. By default, MDIV is cleared, which indicates that the processor clock is equal to the master clock. Once the PMC_MCKR has been written, the user must wait for PMC_SR.MCKRDY to be set. This can be done either by polling PMC_SR.MCKRDY or by waiting for the interrupt line to be raised if the associated interrupt source (MCKRDY) has been enabled in PMC_IER. PMC_MCKR must not be programmed in a single write operation. The programming sequence for PMC_MCKR is as follows: If a new value for PMC_MCKR.CSS corresponds to PLL clock: a. Program the PMC_MCKR.PRES. b. Wait for PMC_SR.MCKRDY to be set. c. Program the PMC_MCKR.MDIV. d. Wait for PMC_SR.MCKRDY to be set. e. Program the PMC_MCKR.CSS. f. Wait for PMC_SR.MCKRDY to be set. If a new value for PMC_MCKR.CSS corresponds to MAINCK or SLCK: a. Program PMC_MCKR.CSS. b. Wait for PMC_SR.MCKRDY to be set. c. Program PMC_MCKR.PRES. d. Wait for PMC_SR.MCKRDY to be set. If CSS, MDIV or PRES are modified at any stage, the MCKRDY bit goes low to indicate that the master clock and the processor clock are not yet ready. The user must wait for MCKRDY bit to be set again before using the master and processor clocks.

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 296 Note: IF PLLx clock was selected as the master clock and the user decides to modify it by writing in CKGR_PLLxR, the MCKRDY flag will go low while PLLx is unlocked. Once PLLx is locked again, LOCKx goes high and MCKRDY is set. While PLLx is unlocked, the master clock selection is automatically changed to slow clock for PLLA. For further information, see Section 31.18.2 ”Clock Switching Waveforms”. The master clock is the main clock divided by 2. 8. Select the programmable clocks: Programmable clocks are controlled via registers PMC_SCER, PMC_SCDR and PMC_SCSR. Programmable clocks can be enabled and/or disabled via PMC_SCER and PMC_SCDR. Three programmable clocks can be used. PMC_SCSR indicates which programmable clock is enabled. By default all programmable clocks are disabled. PMC_PCKx registers are used to configure programmable clocks. PMC_PCKx.CSS is used to select the programmable clock divider source. Several clock options are available: main clock, slow clock, master clock, PLLACK and UPLLCKDIV. The slow clock is the default clock source. PMC_PCKx.PRES is used to control the programmable clock prescaler. It is possible to choose between different values (1, 2, 4, 8, 16, 32, 64). Programmable clock output is prescaler input divided by PRES. By default, the PRES value is cleared which means that PCKx is equal to slow clock. Once PMC_PCKx has been configured, the corresponding programmable clock must be enabled and the user must wait for PMC_SR.PCKRDYx to be set. This can be done either by polling PMC_SR.PCKRDYx or by waiting for the interrupt line to be raised if the associated interrupt source (PCKRDYx) has been enabled in PMC_IER. All parameters in PMC_PCKx can be programmed in a single write operation. If the PMC_PCKx.CSS and PMC_PCKx.PRES parameters are to be modified, the corresponding programmable clock must be disabled first. The parameters can then be modified. Once this has been done, the user must re-enable the programmable clock and wait for the PCKRDYx bit to be set. 9. Enable the peripheral clocks Once all of the previous steps have been completed, the peripheral clocks can be enabled and/or disabled via registers PMC_PCERx and PMC_PCDRx.

31.18 Clock Switching Details

31.18.1 Master Clock Switching Timings

Table 31-2 and Table 31-3 give the worst case timings required for the master clock to switch from one selected clock to another one. This is in the event that the presca ler is de-activated. When the prescaler is activated, an additional time of 64 clock cycles of the newly selected clock has to be added. Table 31-2. Clock Switching Timings (Worst Case) From MAINCK SLCK PLL Clock To Main Clock – 4 x SLCK + 2.5 x MAINCK 3 x PLL Clock + 4 x SLCK + 1 x MAINCK SLCK 0.5 x MAINCK + 4.5 x SLCK – 3 x PLL Clock + 5 x SLCK PLL Clock 0.5 x MAINCK + 4 x SLCK + PLLCOUNT x SLCK + 2.5 x PLLx Clock 2.5 x PLL Clock + 5 x SLCK + PLLCOUNT x SLCK 2.5 x PLL Clock + 4 x SLCK + PLLCOUNT x SLCK

297SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 Notes: 1. PLL designates either the PLLA or the UPLL clock. 2. PLLCOUNT designates either PLLACOUNT or UPLLCOUNT.

31.18.2 Clock Switching Waveforms

Figure 31-6. Switch Master Clock from Slow Clock to PLLx Clock Table 31-3. Clock Switching Timings between Two PLLs (Worst Case) Fro m PLLA Clock UPLL Clock To PLLA Clock 2.5 x PLLA Clock + 4 x SLCK + PLLACOUNT x SLCK 3 x PLLA Clock + 4 x SLCK + 1.5 x PLLA Clock UPLL Clock 3 x UPLL Clock + 4 x SLCK + 1.5 x UPLL Clock 2.5 x UPLL Clock + 4 x SLCK Slow Clock LOCK MCKRDY Master Clock Write PMC_MCKR PLLx Clock

299SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 Figure 31-9. Programmable Clock Output Programming

31.19 Register Write Protection

To prevent any single software error from corrupting PM C behavior, certain registers in the address space can be write-protected by setting the WPEN bit in the PMC Write Protection Mode Register (PMC_WPMR). If a write access to a write-protected register is detected, the WPVS flag in the PMC Write Protection Status Register (PMC_WPSR) is set and the field WPVSRC indicates the register in which the write access has been attempted. The WPVS bit is automatically cleared after reading the PMC_WPSR. The following registers are write-protected when the WPEN bit is set in PMC_WPMR:  PMC System Clock Disable Register  PMC Peripheral Clock Enable Register 0  PMC Peripheral Clock Disable Register 0  PMC Clock Generator Main Oscillator Register  PMC Clock Generator Main Clock Frequency Register  PMC Clock Generator PLLA Register  PMC UTMI Clock Configuration Register  PMC Master Clock Register  PMC USB Clock Register  PMC Programmable Clock Register  PMC Fast Startup Mode Register  PMC Fast Startup Polarity Register  PMC Peripheral Clock Enable Register 1 PLLx Clock PCKRDY PCKx Output Write PMC_PCKx Write PMC_SCER Write PMC_SCDR PCKx is disabled PCKx is enabled PLL Clock is selected

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 300  PMC Peripheral Clock Disable Register 1  PMC Oscillator Calibration Register  PMC SleepWalking Enable Register 0  PMC SleepWalking Disable Register 0  PLL Maximum Multiplier Value Register  PMC SleepWalking Enable Register 1  PMC SleepWalking Disable Register 1

301SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

31.20 Power Management Controll er (PMC) User Interface

Table 31-4. Register Mapping Offset Register Name Access Reset 0x0000 System Clock Enable Register PMC_SCER Write-only – 0x0004 System Clock Disable Register PMC_SCDR Write-only – 0x0008 System Clock Status Register PMC_SCSR Read-only 0x0000_0001 0x000C Reserved – – – 0x0010 Peripheral Clock Enable Register 0 PMC_PCER0 Write-only – 0x0014 Peripheral Clock Disable Register 0 PMC_PCDR0 Write-only – 0x0018 Peripheral Clock Status Register 0 PMC_PCSR0 Read-only 0x0000_0000 0x001C UTMI Clock Register CKGR_UCKR Read/Write 0x1020_0800 0x0020 Main Oscillator Register CKGR_MOR Read/Write 0x0000_0008 0x0024 Main Clock Frequency Register CKGR_MCFR Read/Write 0x0000_0000 0x0028 PLLA Register CKGR_PLLAR Read/Write 0x0000_3F00 0x002C Reserved – – – 0x0030 Master Clock Register PMC_MCKR Read/Write 0x0000_0001 0x0034 Reserved – – – 0x0038 USB Clock Register PMC_USB Read/Write 0x0000_0000 0x003C Reserved – – – 0x0040+chid*0x04 Programmable Clock Register PMC_PCK Read/Write 0x0000_0000 0x005C Reserved – – – 0x0060 Interrupt Enable Register PMC_IER Write-only – 0x0064 Interrupt Disable Register PMC_IDR Write-only – 0x0068 Status Register PMC_SR Read-only 0x0003_0008 0x006C Interrupt Mask Regist er PMC_IMR Read-only 0x0000_0000 0x0070 Fast Startup Mode Register PMC_FSMR Read/Write 0x0000_0000 0x0074 Fast Startup Polarity Register PMC_FSPR Read/Write 0x0000_0000 0x0078 Fault Output Clear Register PMC_FOCR Write-only – 0x007C–0x00E0 Reserved – – – 0x00E4 Write Protection Mode Register PMC_WPMR Read/Write 0x0 0x00E8 Write Protection Status Register PMC_WPSR Read-only 0x0 0x00EC–0x00FC Reserved – – – 0x0100 Peripheral Clock Enable Register 1 PMC_PCER1 Write-only – 0x0104 Peripheral Clock Disable Register 1 PMC_PCDR1 Write-only – 0x0108 Peripheral Clock Status Register 1 PMC_PCSR1 Read-only 0x0000_0000 0x010C Peripheral Control Register PMC_PCR Read/Write 0x0000_0000 0x0110 Oscillator Calibration Register PMC_OCR Read/Write (2) 0x0114 SleepWalking Enable Register 0 PMC_SLPWK_ER0 Write-only –

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 302 Notes: 1. If an offset is not listed in Table 31-4 it must be considered as “reserved”. 2. The reset value depends on factory settings. 0x0118 SleepWalking Disable Register 0 PMC_SLPWK_DR0 Write-only – 0x011C SleepWalking Status Register 0 PMC_SLPWK_SR0 Read-only 0x00000000 0x0120 SleepWalking Activity Status Register 0 PMC_SLPWK_ASR0 Read-only 0x00000000 0x0130 PLL Maximum Multiplier Value Register PMC_PMMR Read/Write 0x0000_07FF 0x0134 SleepWalking Enable Register 1 PMC_SLPWK_ER1 Write-only – 0x0138 SleepWalking Disable Register 1 PMC_SLPWK_DR1 Write-only – 0x013C SleepWalking Status Register 1 PMC_SLPWK_SR1 Read-only 0x00000000 0x0140 SleepWalking Activity Status Register 1 PMC_SLPWK_ASR1 Read-only 0x00000000 0x0144 SleepWalking Activity In Progress Register PMC_SLPWK_AIPR Read-only – Table 31-4. Register Mapping (Continued) Offset Register Name Access Reset

303SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

31.20.1 PMC System Clock Enable Register

Name: PMC_SCER Address: 0x400E0600 Access: Write-only This register can only be written if the WPEN bit is cleared in PMC Write Protection Mode Register.

• USBCLK: Enable USB FS Clock 0: No effect. 1: Enables USB FS clock.
• PCKx: Programmable Clock x Output Enable 0: No effect. 1: Enables the corresponding Programmable Clock output. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 – PCK6 PCK5 PCK4 PCK3 PCK2 PCK1 PCK0 76543210

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 304

31.20.2 PMC System Cl ock Disable Register

Name: PMC_SCDR Address: 0x400E0604 Access: Write-only This register can only be written if the WPEN bit is cleared in PMC Write Protection Mode Register.

• USBCLK: Disable USB FS Clock 0: No effect. 1: Disables USB FS clock.
• PCKx: Programmable Clock x Output Disable 0: No effect. 1: Disables the corresponding Programmable Clock output. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 – PCK6 PCK5 PCK4 PCK3 PCK2 PCK1 PCK0 76543210

305SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

31.20.3 PMC System Clock Status Register

Name: PMC_SCSR Address: 0x400E0608 Access: Read-only

• HCLKS: Processor Clock Status 0: The processor clock is disabled. 1: The processor clock is enabled.
• USBCLK: USB FS Clock Status 0: The USB FS clock is disabled. 1: The USB FS clock is enabled.
• PCKx: Programmable Clock x Output Status 0: The corresponding Programmable Clock output is disabled. 1: The corresponding Programmable Clock output is enabled. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 – PCK6 PCK5 PCK4 PCK3 PCK2 PCK1 PCK0 76543210

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 306

31.20.4 PMC Peripheral Clock Enable Register 0

Name: PMC_PCER0 Address: 0x400E0610 Access: Write-only This register can only be written if the WPEN bit is cleared in PMC Write Protection Mode Register.

• PIDx: Peripheral Clock x Enable 0: No effect. 1: Enables the corresponding peripheral clock. Note: PIDx refers to identifiers defined in the section “Peripheral Identifiers”. Other peripherals can be enabled in PMC_PCER1 (Section 31.20.23 ”PMC Peripheral Clock Enable Register 1”). Note: Programming the control bits of the Peripheral ID that are not implemented has no effect on the behavior of the PMC. 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 76543210

307SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

31.20.5 PMC Peripheral Clock Disable Register 0

Name: PMC_PCDR0 Address: 0x400E0614 Access: Write-only This register can only be written if the WPEN bit is cleared in PMC Write Protection Mode Register.

• PIDx: Peripheral Clock x Disable 0: No effect. 1: Disables the corresponding peripheral clock. Note: PIDx refers to identifiers defined in the section “Peripheral Identifiers”. Other peripherals can be disabled in PMC_PCDR1 (Section 31.20.24 ”PMC Peripheral Clock Disable Register 1”). 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 76543210

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 308

31.20.6 PMC Peripheral Clock Status Register 0

Name: PMC_PCSR0 Address: 0x400E0618 Access: Read-only

• PIDx: Peripheral Clock x Status 0: The corresponding peripheral clock is disabled. 1: The corresponding peripheral clock is enabled. Note: PIDx refers to identifiers defined in the section “Peripheral Identifiers”. Other peripherals status can be read in PMC_PCSR1 (Section 31.20.25 ”PMC Peripheral Clock Status Register 1”). 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 76543210

309SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

31.20.7 PMC UTMI Clock Configuration Register

Name: CKGR_UCKR Address: 0x400E061C Access: Read/Write This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register.

• UPLLEN: UTMI PLL Enable 0: The UTMI PLL is disabled. 1: The UTMI PLL is enabled. When UPLLEN is set, the LOCKU flag is set once the UTMI PLL start-up time is achieved.
• UPLLCOUNT: UTMI PLL Start-up Time Specifies the number of Slow Clock cycles multiplied by 8 for the UTMI PLL start-up time. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 UPLLCOUNT – – – UPLLEN 15 14 13 12 11 10 9 8 76543210

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 310

31.20.8 PMC Clock Generator Main Oscillator Register

Name: CKGR_MOR Address: 0x400E0620 Access: Read/Write This register can only be written if the WPEN bit is cleared in PMC Write Protection Mode Register.

• MOSCXTEN: 3 to 20 MHz Crystal Oscillator Enable A crystal must be connected between XIN and XOUT. 0: The 3 to 20 MHz crystal oscillator is disabled. 1: The 3 to 20 MHz crystal oscillator is enabled. MOSCXTBY must be cleared. When MOSCXTEN is set, the MOSCXTS flag is set once the Main Crystal Oscillator start-up time is achieved.
• MOSCXTBY: 3 to 20 MHz Crystal Oscillator Bypass 0: No effect. 1: The 3 to 20 MHz crystal oscillator is bypassed. MOSCXTEN must be cleared. An external clock must be connected on XIN. When MOSCXTBY is set, the MOSCXTS flag in PMC_SR is automatically set. Clearing MOSCXTEN and MOSCXTBY bits resets the MOSCXTS flag. Note: When the cry stal oscillator bypass is disabled (MOSCXTBY=0), the MOSCXTS flag must be read at 0 in PMC_SR before enabling the crystal oscillator (MOSCXTEN=1).
• WAITMODE: Wait Mode Command (Write-only) 0: No effect. 1: Puts the device in Wait mode.
• MOSCRCEN: 4/8/12 MHz On-Chip RC Oscillator Enable 0: The 4/8/12 MHz on-chip RC oscillator is disabled. 1: The 4/8/12 MHz on-chip RC oscillator is enabled. When MOSCRCEN is set, the MOSCRCS flag is set once the on-chip RC oscillator start-up time is achieved. 31 30 29 28 27 26 25 24 ––––– X T32KFME C FDEN M OSCSEL 23 22 21 20 19 18 17 16 KEY 15 14 13 12 11 10 9 8 MOSCXTST 76543210 – MOSCRCF MOSCRCEN WAITMODE MOSCXTBY MOSCXTEN

311SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

• MOSCRCF: 4/8/12 MHz RC Oscillator Frequency Selection At startup, the RC oscillator frequency is 4 MHz. Note: MOSCRCF must be changed only if MOSCRCS is set in th e PMC_SR register. Therefore MOSCRCF and MOSCRCEN cannot be changed at the same time.
• MOSCXTST: 3 to 20 MHz Crystal Oscillator Start-up Time Specifies the number of slow clock cycles multiplied by 8 for the main crystal oscillator start-up time.
• KEY: Write Access Password
• MOSCSEL: Main Clock Oscillator Selection 0: The 4/8/12 MHz RC oscillator is selected. 1: The 3 to 20 MHz crystal oscillator is selected.
• CFDEN: Clock Failure Detector Enable 0: The clock failure detector is disabled. 1: The clock failure detector is enabled. Note: 1. The 32 kHz (typical) RC oscillator must be enabled when CFDEN is enabled.
• XT32KFME: 32.768 kHz Crystal Oscillator Frequency Monitoring Enable 0: The 32.768 kHz crystal oscillator frequency monitoring is disabled. 1: The 32.768 kHz crystal oscillator frequency monitoring is enabled. Value Name Description 0 4_MHz The RC oscillator frequency is at 4 MHz (default) 1 8_MHz The RC oscillator frequency is at 8 MHz 2 12_MHz The RC oscillator frequency is at 12 MHz Value Name Description 0x37 PASSWD Writing any other value in this field aborts the write operation. Always reads as 0.

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 312

31.20.9 PMC Clock Generator Main Clock Frequency Register

Name: CKGR_MCFR Address: 0x400E0624 Access: Read/Write This register can only be written if the WPEN bit is cleared in PMC Write Protection Mode Register.

• MAINF: Main Clock Frequency Gives the number of cycles of the clock selected by the bit CCSS within 16 slow clock periods. To calculate the frequency of the measured clock: fSELCLK = (MAINF x fSLCK)/16 where frequency is in MHz.
• MAINFRDY: Main Clock Frequency Measure Ready 0: MAINF value is not valid or the measured oscillator is disabled or a measure has just been started by means of RCMEAS. 1: The measured oscillator has been enabled previously and MAINF value is available. Note: To ensure that a correct value is read on the MAINF field, the MAINFRDY flag must be read at 1 then another read access must be performed on the register to get a stable value on the MAINF field.
• RCMEAS: RC Oscillator Frequency Measure (write-only) 0: No effect. 1: Restarts measuring of the frequency of the main clock source. MAINF carries the new frequency as soon as a low-to- high transition occurs on the MAINFRDY flag. The measurement is performed on the main frequency (i.e., not limited to RC oscillator only).If the main clock frequency source is the 3 to 20 MHz crystal oscillator, the restart of measurement is not required because of the stability of crystal oscillators.
• CCSS: Counter Clock Source Selection 0: The clock of the MAINF counter is the RC oscillator. 1: The clock of the MAINF counter is the crystal oscillator. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 MAINF 76543210 MAINF

313SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

31.20.10 PMC Clock Generator PLLA Register

Name: CKGR_PLLAR Address: 0x400E0628 Access: Read/Write Possible limitations on PLLA input frequencies and multiplier factors should be checked before using the PMC. Warning: Bit 29 must always be set to ‘1’ when programming the CKGR_PLLAR register. This register can only be written if the WPEN bit is cleared in PMC Write Protection Mode Register.

• DIVA: PLLA Front End Divider
• PLLACOUNT: PLLA Counter Specifies the number of slow clock cycles before the LOCKA bit is set in PMC_SR after CKGR_PLLAR is written.
• MULA: PLLA Multiplier 0: The PLLA is deactivated (PLLA also disabled if DIVA = 0). 1 up to 62 = The PLLA Clock frequency is the PLLA input frequency multiplied by MULA + 1. Unlisted values are forbidden.
• ONE: Must Be Set to 1 Bit 29 must always be set to ‘1’ when programming the CKGR_PLLAR register. 31 30 29 28 27 26 25 24 –– O NE –– MULA 23 22 21 20 19 18 17 16 MULA 15 14 13 12 11 10 9 8 – – PLLACOUNT 76543210 DIVA Value Name Description 0 0 Divider output is 0 and PLLA is disabled. 1 BYPASS Divider is bypassed (divide by 1) and PLLA is enabled. 2–255 – Divider output is the selected clock divided by DIVA.

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 314

31.20.11 PMC Master Clock Register

Name: PMC_MCKR Address: 0x400E0630 Access: Read/Write This register can only be written if the WPEN bit is cleared in PMC Write Protection Mode Register.

• CSS: Master Clock Source Selection
• PRES: Processor Clock Prescaler 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 –P RES– – C SS Value Name Description

0 SLOW_CLK Slow Clock is selected

1 MAIN_CLK Main Clock is selected

2 PLLA_CLK PLLA Clock is selected

3 UPLL_CLK Divided UPLL Clock is selected

0 CLK_1 Selected clock

1 CLK_2 Selected clock divided by 2

2 CLK_4 Selected clock divided by 4

3 CLK_8 Selected clock divided by 8

4 CLK_16 Selected clock divided by 16

5 CLK_32 Selected clock divided by 32

6 CLK_64 Selected clock divided by 64

7 CLK_3 Selected clock divided by 3

315SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

• MDIV: Master Clock Division
• UPLLDIV2: UPLL Divisor by 2 Value Name Description 0 EQ_PCK Master Clock is Prescaler Output Clock divided by 1. 1 PCK_DIV2 Master Clock is Prescaler Output Clock divided by 2. 2 PCK_DIV4 Master Clock is Prescaler Output Clock divided by 4. 3 PCK_DIV3 Master Clock is Prescaler Output Clock divided by 3. UPLLDIV2 UPLL Clock Division 0 UPLL clock frequency is divided by 1. 1 UPLL clock frequency is divided by 2.

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 316

31.20.12 PMC USB Clock Register

Name: PMC_USB Address: 0x400E0638 Access: Read/Write This register can only be written if the WPEN bit is cleared in PMC Write Protection Mode Register.  USBS: USB Input Clock Selection 0: USB clock input is PLLA. 1: USB clock input is UPLL.  USBDIV: Divider for USB Clock USB clock is input clock divided by USBDIV+1. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 –––– USBDIV 76543210

317SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

31.20.13 PMC Programmable Clock Register

Name: PMC_PCKx[x=0..6] Address: 0x400E0640 Access: Read/Write This register can only be written if the WPEN bit is cleared in PMC Write Protection Mode Register.

• CSS: Programmable Clock Source Selection
• PRES: Programmable Clock Prescaler 0-255: Selected clock is divided by PRES+1. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 –––– PRES 76543210 PRES – CSS Value Name Description

4M CK M aster Clock is selected

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 318

31.20.14 PMC Interrupt Enable Register

Name: PMC_IER Address: 0x400E0660 Access: Write-only The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Enables the corresponding interrupt.

• MOSCXTS: 3 to 20 MHz Crystal Oscillator Status Interrupt Enable
• LOCKA: PLLA Lock Interrupt Enable
• MCKRDY: Master Clock Ready Interrupt Enable
• LOCKU: UTMI PLL Lo ck Interrupt Enable
• PCKRDYx: Programmable Cloc k Ready x Interrupt Enable
• MOSCSELS: Main Clock Source Oscilla tor Selection Status Interrupt Enable
• MOSCRCS: 4/8/12 MHz RC Oscillator Status Interrupt Enable
• CFDEV: Clock Failure Detector Event Interrupt Enable
• XT32KERR: 32.768 kHz Crystal Oscillator Error Interrupt Enable 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 – – XT32KERR – – CFDEV MOSCRCS MOSCSELS 15 14 13 12 11 10 9 8 ––––– P CKRDY2 P CKRDY1 P CKRDY0 76543210 – LOCKU – – MCKRDY – LOCKA MOSCXTS

319SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

31.20.15 PMC Interrupt Disable Register

Name: PMC_IDR Address: 0x400E0664 Access: Write-only The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Disables the corresponding interrupt.

• MOSCXTS: 3 to 20 MHz Crystal Oscillator Status Interrupt Disable
• LOCKA: PLLA Lock Interrupt Disable
• MCKRDY: Master Clock Re ady Interrupt Disable
• LOCKU: UTMI PLL Lock Interrupt Disable
• PCKRDYx: Programmable Cloc k Ready x Interrupt Disable
• MOSCSELS: Main Clock Source Oscillato r Selection Status Interrupt Disable
• MOSCRCS: 4/8/12 MHz RC Status Interrupt Disable
• CFDEV: Clock Failure Detector Event Interrupt Disable
• XT32KERR: 32.768 kHz Crystal Os cillator Error Interrupt Disable 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 – – XT32KERR – – CFDEV MOSCRCS MOSCSELS 15 14 13 12 11 10 9 8 ––––– P CKRDY2 P CKRDY1 P CKRDY0 76543210 – LOCKU – – MCKRDY – LOCKA MOSCXTS

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 320

31.20.16 PMC Status Register

Name: PMC_SR Address: 0x400E0668 Access: Read-only

• MOSCXTS: 3 to 20 MHz Crystal Oscillator Status 0: 3 to 20 MHz crystal oscillator is not stabilized. 1: 3 to 20 MHz crystal oscillator is stabilized.
• LOCKA: PLLA Lock Status 0: PLLA is not locked 1: PLLA is locked.
• MCKRDY: Master Clock Status 0: Master Clock is not ready. 1: Master Clock is ready.
• LOCKU: UTMI PLL Lock Status 0: UTMI PLL is not locked 1: UTMI PLL is locked.
• OSCSELS: Slow Clock Sour ce Oscillator Selection 0: Embedded 32 kHz RC oscillator is selected. 1: 32.768 kHz crystal oscillator is selected.
• PCKRDYx: Programmabl e Clock Ready Status 0: Programmable Clock x is not ready. 1: Programmable Clock x is ready.
• MOSCSELS: Main Clock Source Oscillator Selection Status 0: Selection is in progress. 1: Selection is done. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 – – XT32KERR FOS CFDS CFDEV MOSCRCS MOSCSELS 15 14 13 12 11 10 9 8 ––––– P CKRDY2 P CKRDY1 P CKRDY0 76543210 OSCSELS LOCKU – – MCKRDY – LOCKA MOSCXTS

321SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

• MOSCRCS: 4/8/12 MHz RC Oscillator Status 0: 4/8/12 MHz RC oscillator is not stabilized. 1: 4/8/12 MHz RC oscillator is stabilized.
• CFDEV: Clock Failure Detector Event 0: No clock failure detection of the 3 to 20 MHz crystal oscillator clock has occurred since the last read of PMC_SR. 1: At least one clock failure detection of the 3 to 20 MHz crystal oscillator clock has occurred since the last read of PMC_SR.
• CFDS: Clock Failure Detector Status 0: A clock failure of the 3 to 20 MHz crystal oscillator clock is not detected. 1: A clock failure of the 3 to 20 MHz crystal oscillator clock is detected.
• FOS: Clock Failure Detector Fault Output Status 0: The fault output of the clock failure detector is inactive. 1: The fault output of the clock failure detector is active.
• XT32KERR: Slow Crystal Oscillator Error 0: The frequency of the 32.768 kHz crystal oscillator is correct (32.768 kHz ±1%) or the monitoring is disabled. 1: The frequency of the 32.768 kHz crystal oscillator is incorrect or has been incorrect for an elapsed period of time since the monitoring has been enabled.

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 322

31.20.17 PMC Interrupt Mask Register

Name: PMC_IMR Address: 0x400E066C Access: Read-only The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Enables the corresponding interrupt.

• MOSCXTS: 3 to 20 MHz Crystal Oscillator Status Interrupt Mask
• LOCKA: PLLA Lock Interrupt Mask
• MCKRDY: Master Clock Ready Interrupt Mask
• LOCKU: UTMI PLL Lock Interrupt Mask
• PCKRDYx: Programmable Cloc k Ready x Interrupt Mask
• MOSCSELS: Main Clock Source Oscilla tor Selection Status Interrupt Mask
• MOSCRCS: 4/8/12 MHz RC Status Interrupt Mask
• CFDEV: Clock Failure Detector Event Interrupt Mask
• XT32KERR: 32.768 kHz Crystal Oscillator Error Interrupt Mask 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 – – XT32KERR – – CFDEV MOSCRCS MOSCSELS 15 14 13 12 11 10 9 8 ––––– P CKRDY2 P CKRDY1 P CKRDY0 76543210 – LOCKU – – MCKRDY – LOCKA MOSCXTS

323SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

31.20.18 PMC Fast Startup Mode Register

Name: PMC_FSMR Address: 0x400E0670 Access: Read/Write This register can only be written if the WPEN bit is cleared in PMC Write Protection Mode Register.

• FSTT0 - FSTT15: Fast Startup Input Enable 0 to 15 0: The corresponding wake-up input has no effect on the PMC. 1: The corresponding wake-up input enables a fast restart signal to the PMC.
• RTTAL: RTT Alarm Enable 0: The RTT alarm has no effect on the PMC. 1: The RTT alarm enables a fast restart signal to the PMC.
• RTCAL: RTC Alarm Enable 0: The RTC alarm has no effect on the PMC. 1: The RTC alarm enables a fast restart signal to the PMC.
• USBAL: USB Alarm Enable 0: The USB alarm has no effect on the PMC. 1: The USB alarm enables a fast restart signal to the PMC.
• LPM: Low-power Mode 0: The WaitForInterrupt (WFI) or the WaitForEvent (WFE) instruction of the processor makes the processor enter Sleep mode. 1: The WaitForEvent (WFE) instruction of the processor makes the system enter Wait mode.
• FFLPM: Force Flash Low-power Mode 0: The Flash Low-power mode, defined in the FLPM field, is automatically applied when in Wait mode and released when going back to Active mode. 1: The Flash Low-power mode is user defined by the FLPM field and immediately applied. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FFLPM FLPM LPM – USBAL RTCAL RTTAL 15 14 13 12 11 10 9 8 FSTT15 FSTT14 FSTT13 FSTT12 FSTT11 FSTT10 FSTT9 FSTT8 76543210 FSTT7 FSTT6 FSTT5 FSTT4 FSTT3 FSTT2 FSTT1 FSTT0

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 324

• FLPM: Flash Low-power Mode Value Name Description

0 FLASH_STANDBY Flash is in Standby Mode when system enters Wait Mode

1 FLASH_DEEP_POWERDOWN Flash is in Deep-power-down mode when system enters Wait Mode

2 FLASH_IDLE Idle mode

325SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

31.20.19 PMC Fast Startup Polarity Register

Name: PMC_FSPR Address: 0x400E0674 Access: Read/Write This register can only be written if the WPEN bit is cleared in PMC Write Protection Mode Register.

• FSTPx: Fast Startup Input Polarity x Defines the active polarity of the corresponding wake-up input. If the corresponding wake-up input is enabled and at the FSTP level, it enables a fast restart signal. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 FSTP15 FSTP14 FSTP13 FSTP12 FSTP11 FSTP10 FSTP9 FSTP8 76543210 FSTP7 FSTP6 FSTP5 FSTP4 FSTP3 FSTP2 FSTP1 FSTP0

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 326

31.20.20 PMC Fault Output Clear Register

Name: PMC_FOCR Address: 0x400E0678 Access: Write-only

• FOCLR: Fault Output Clear Clears the clock failure detector fault output. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210

327SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

31.20.21 PMC Write Protection Mode Register

Name: PMC_WPMR Address: 0x400E06E4 Access: Read/Write

• WPEN: Write Protection Enable 0: Disables the write protection if WPKEY corresponds to 0x504D43 (“PMC” in ASCII). 1: Enables the write protection if WPKEY corresponds to 0x504D43 (“PMC” in ASCII). See Section 31.19 ”Register Write Protection” for the list of registers that can be write-protected.
• WPKEY: Write Protection Key 31 30 29 28 27 26 25 24 WPKEY 23 22 21 20 19 18 17 16 WPKEY 15 14 13 12 11 10 9 8 WPKEY 76543210 Value Name Description 0x504D43 PASSWD Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0.

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 328

31.20.22 PMC Write Protection Status Register

Name: PMC_WPSR Address: 0x400E06E8 Access: Read-only

• WPVS: Write Protection Violation Status 0: No write protection violation has occurred since the last read of the PMC_WPSR. 1: A write protection violation has occurred since the last read of the PMC_WPSR. If this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field WPVSRC.
• WPVSRC: Write Protection Violation Source When WPVS = 1, WPVSRC indicates the register address offset at which a write access has been attempted. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WPVSRC 15 14 13 12 11 10 9 8 WPVSRC 76543210

329SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

31.20.23 PMC Peripheral Clock Enable Register 1

Name: PMC_PCER1 Address: 0x400E0700 Access: Write-only This register can only be written if the WPEN bit is cleared in PMC Write Protection Mode Register.

• PIDx: Peripheral Clock x Enable 0: No effect. 1: Enables the corresponding peripheral clock. Notes: 1. PIDx refers to identifiers as defi ned in the section “Peripheral Identifiers”. 2. Programming the control bits of the Pe ripheral ID that are not implemented has no effect on the behavior of the PMC. 31 302 92 82 72 62 52 4 – – – PID60 PID59 PID58 PID57 PID56 23 22 21 20 19 18 17 16 –– P ID53 PID52 PID51 PID50 PID49 PID48 15 14 13 12 11 10 9 8 PID47 PID46 PID45 PID44 PID4 3 PID42 PID41 PID40 76543 210 PID39–P I D 37–P I D 35P I D 34P I D 33 PID32

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 330

31.20.24 PMC Peripheral Clock Disable Register 1

Name: PMC_PCDR1 Address: 0x400E0704 Access: Write-only This register can only be written if the WPEN bit is cleared in PMC Write Protection Mode Register.

• PIDx: Peripheral Clock x Disable 0: No effect. 1: Disables the corresponding peripheral clock. Note: PIDx refers to identifiers as defined in the section “Peripheral Identifiers”. 31 302 92 82 72 62 52 4 – – – PID60 PID59 PID58 PID57 PID56 23 22 21 20 19 18 17 16 –– P ID53 PID52 PID51 PID50 PID49 PID48 15 14 13 12 11 10 9 8 PID47 PID46 PID45 PID44 PID4 3 PID42 PID41 PID40 76543 210 PID39–P I D 37–P I D 35P I D 34P I D 33 PID32

331SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

31.20.25 PMC Peripheral Clock Status Register 1

Name: PMC_PCSR1 Address: 0x400E0708 Access: Read-only

• PIDx: Peripheral Clock x Status 0: The corresponding peripheral clock is disabled. 1: The corresponding peripheral clock is enabled. Note: PIDx refers to identifiers as defined in the section “Peripheral Identifiers”. 31 302 92 82 72 62 52 4 – – – PID60 PID59 PID58 PID57 PID56 23 22 21 20 19 18 17 16 –– P ID53 PID52 PID51 PID50 PID49 PID48 15 14 13 12 11 10 9 8 PID47 PID46 PID45 PID44 PID4 3 PID42 PID41 PID40 76543 210 PID39–P I D 37–P I D 35P I D 34P I D 33 PID32

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 332

31.20.26 PMC Peripheral Control Register

Name: PMC_PCR Address: 0x400E070C Access: Read/Write

• PID: Peripheral ID Peripheral ID selection from PID2 to PID127. PID2 to PID127 refer to identifiers as defined in Section 13.1 ”Peripheral Identifiers”.
• GCLKCSS: Generic Clock Source Selection
• C M D : C o m m a n d 0: Read mode. 1: Write mode.
• GCLKDIV: Generic Clock Division Ratio Generic clock is the selected clock period divided by GCLKDIV + 1. GCLKDIV must not be changed while the peripheral selects GCLKx (e.g., bit rate, etc.).
• EN: Enable 0: Selected Peripheral clock is disabled. 1: Selected Peripheral clock is enabled.
• GCLKEN: Generic Clock Enable 0: The selected generic clock is disabled. 1: The selected generic clock is enabled. 31 30 29 28 27 26 25 24 – – GCLKEN EN GCLKDIV 23 22 21 20 19 18 17 16 GCLKDIV –––– 15 14 13 12 11 10 9 8 – – – CMD – GCLKCSS 76543210 –P ID Value Name Description

2 PLLA_CLK PLLACK is selected

3 UPLL_CLK UPLL Clock is selected

4 MCK_CLK Master Clock is selected

333SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

31.20.27 PMC Oscillator Calibration Register

Name: PMC_OCR Address: 0x400E0710 Access: Read/Write This register can only be written if the WPEN bit is cleared in PMC Write Protection Mode Register.

• CAL4: RC Oscillator Calibration bits for 4 MHz Calibration bits applied to the RC Oscillator when SEL4 is set.
• SEL4: Selection of RC Oscillator Calibration bits for 4 MHz 0: Default value stored in Flash memory. 1: Value written by user in CAL4 field of this register.
• CAL8: RC Oscillator Calibration bits for 8 MHz Calibration bits applied to the RC Oscillator when SEL8 is set.
• SEL8: Selection of RC Oscillator Calibration bits for 8 MHz 0: Factory-determined value stored in Flash memory. 1: Value written by user in CAL8 field of this register.
• CAL12: RC Oscillato r Calibration bits for 12 MHz Calibration bits applied to the RC Oscillator when SEL12 is set.
• SEL12: Selection of RC Oscillato r Calibration bits for 12 MHz 0: Factory-determined value stored in Flash memory. 1: Value written by user in CAL12 field of this register. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SEL12 CAL12 15 14 13 12 11 10 9 8 SEL8 CAL8 76543210 SEL4 CAL4

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 334

31.20.28 PMC SleepWalking Enable Register 0

Name: PMC_SLPWK_ER0 Address: 0x400E0714 Access: Write-only This register can only be written if the WPEN bit is cleared in PMC Write Protection Mode Register.

• PIDx: Peripheral x SleepWalking Enable 0: No effect. 1: The asynchronous partial wake-up (SleepWalking) function of the corresponding peripheral is enabled. Not all PIDs can be configured with asynchronous partial wake-up. Only the following PID can be configured with asynchronous partial wake-up: UARTx and TWIHSx. The clock of the peripheral must be enabled before using its asynchronous partial wake-up (SleepWalking) function (its associated PIDx field in PMC Peripheral Clock Status Register 0 or PMC Peripheral Clock Status Register 1 is set to ‘1’). Note: PIDx refers to identifiers as defined in the section “Peripheral Identifiers”. 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 76543210

335SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

31.20.29 PMC SleepWalking Enable Register 1

Name: PMC_SLPWK_ER1 Address: 0x400E0734 Access: Write-only This register can only be written if the WPEN bit is cleared in PMC Write Protection Mode Register.

• PIDx: Peripheral x SleepWalking Enable 0: No effect. 1: The asynchronous partial wake-up (SleepWalking) function of the corresponding peripheral is enabled. Not all PIDs can be configured with asynchronous partial wake-up. Only the following PID can be configured with asynchronous partial wake-up: UARTx and TWIHSx. The clock of the peripheral must be enabled before using its asynchronous partial wake-up (SleepWalking) function (the associated PIDx field in PMC Peripheral Clock Status Register 1 or PMC Peripheral Clock Status Register 0 is set to ‘1’). Note: PIDx refers to identifiers as defined in the section “Peripheral Identifiers”. 31 30 29 28 27 26 25 24 – – – PID60 PID59 PID58 PID57 PID56 23 22 21 20 19 18 17 16 – – PID53 PID52 PID51 PID50 PID49 PID48 15 14 13 12 11 10 9 8 PID47 PID46 PID45 PID44 PID43 PID42 PID41 PID40 76543210 PID39 – PID37 – PID3 5P I D 3 4P I D 3 3P I D 3 2

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 336

31.20.30 PMC SleepWalking Disable Register 0

Name: PMC_SLPWK_DR0 Address: 0x400E0718 Access: Write-only This register can only be written if the WPEN bit is cleared in PMC Write Protection Mode Register.

• PIDx: Peripheral x SleepWalking Disable 0: No effect. 1: The asynchronous partial wake-up (SleepWalking) function of the corresponding peripheral is disabled. Not all PIDs can be configured with asynchronous partial wake-up. Only the following PIDs can be configured with asynchronous partial wake-up: UARTx and TWIHSx. Note: PIDx refers to identifiers as defined in the section “Peripheral Identifiers”. 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 76543210

337SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

31.20.31 PMC SleepWalking Disable Register 1

Name: PMC_SLPWK_DR1 Address: 0x400E0738 Access: Write-only This register can only be written if the WPEN bit is cleared in PMC Write Protection Mode Register.

• PIDx: Peripheral x SleepWalking Disable 0: No effect. 1: The asynchronous partial wake-up (SleepWalking) function of the corresponding peripheral is disabled. Not all PIDs can be configured with asynchronous partial wake-up. Only the following PIDs can be configured with asynchronous partial wake-up: UARTx and TWIHSx. Note: PIDx refers to identifiers as defined in the section “Peripheral Identifiers”. 31 30 29 28 27 26 25 24 – – – PID60 PID59 PID58 PID57 PID56 23 22 21 20 19 18 17 16 – – PID53 PID52 PID51 PID50 PID49 PID48 15 14 13 12 11 10 9 8 PID47 PID46 PID45 PID44 PID43 PID42 PID41 PID40 76543210 PID39 – PID37 – PID3 5P I D 3 4P I D 3 3P I D 3 2

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 338

31.20.32 PMC SleepWalking Status Register 0

Name: PMC_SLPWK_SR0 Address: 0x400E071C Access: Read-only

• PIDx: Peripheral x SleepWalking Status 0: The asynchronous partial wake-up (SleepWalking) function of the peripheral is currently disabled or the peripheral enabled for asynchronous partial wake-up (SleepWalking) cleared the PIDx bit upon detect ion of a wake-up condition. 1: The asynchronous partial wake-up (SleepWalking) function of the peripheral is currently enabled. Not all PIDs can be configured with asynchronous partial wake-up. Only the following PIDs can be configured with asynchronous partial wake-up: UARTx and TWIHSx. Note: PIDx refers to identifiers as defined in the section “Peripheral Identifiers”. 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 76543210

339SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

31.20.33 PMC SleepWalking Status Register 1

Name: PMC_SLPWK_SR1 Address: 0x400E073C Access: Read-only

• PIDx: Peripheral x SleepWalking Status 0: The asynchronous partial wake-up (SleepWalking) function of the peripheral is currently disabled or the peripheral enabled for asynchronous partial wake-up (SleepWalking) cleared the PIDx bit upon detect ion of a wake-up condition. 1: The asynchronous partial wake-up (SleepWalking) function of the peripheral is currently enabled. Not all PIDs can be configured with asynchronous partial wake-up. Only the following PIDs can be configured with asynchronous partial wake-up: UARTx and TWIHSx. Note: PIDx refers to identifiers as defined in the section “Peripheral Identifiers”. 31 30 29 28 27 26 25 24 – – – PID60 PID59 PID58 PID57 PID56 23 22 21 20 19 18 17 16 – – PID53 PID52 PID51 PID50 PID49 PID48 15 14 13 12 11 10 9 8 PID47 PID46 PID45 PID44 PID43 PID42 PID41 PID40 76543210 PID39 – PID37 – PID3 5P I D 3 4P I D 3 3P I D 3 2

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 340

31.20.34 PMC SleepWalking Activity Status Register 0

Name: PMC_SLPWK_ASR0 Address: 0x400E0720 Access: Read-only

• PIDx: Peripheral x Activity Status 0: The peripheral x is not currently active. The asynchronous partial wake-up (SleepWalking) function can be activated. 1: The peripheral x is currently active. The asynchronous partial wake-up (SleepWalking) function must not be activated. Only the following PIDs can be configured with asynchronous partial wake-up: UARTx and TWIHSx. All other PIDs are always read at 0. Note: PIDx refers to identifiers as defined in the section “Peripheral Identifiers”. 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 76543210

341SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

31.20.35 PLL Maximum Multiplier Value Register

Name: PMC_PMMR Address: 0x400E0730 Access: Read/Write This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register.

• PLLA_MMAX: PLLA Maximum Allowed Multiplier Value Defines the maximum value of multiplication factor that can be sent to PLLA. Any value of the MULA field (see PMC Clock Generator PLLA Register) above PLLA_MMAX is saturated to PLLA_MMAX. PLLA_MMAX write operation is cancelled in the following cases: T h e value of MULA is currently saturated by PLLA_MMAX T h e user is trying to write a value of PLLA_MMAX that is smaller than the current value of MULA 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 PLLA_MMAX

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 342

31.20.36 PMC SleepWalking Activity Status Register 1

Name: PMC_SLPWK_ASR1 Address: 0x400E0740 Access: Read-only

• PIDx: Peripheral x Activity Status 0: The peripheral x is not currently active. The asynchronous partial wake-up (SleepWalking) function can be activated. 1: The peripheral x is currently active. The asynchronous partial wake-up (SleepWalking) function must not be activated. Only the following PIDs can be configured with asynchronous partial wake-up: UARTx and TWIHSx. All other PIDs are always read at 0. Note: PIDx refers to identifiers as defined in the section “Peripheral Identifiers”. 31 30 29 28 27 26 25 24 – – – PID60 PID59 PID58 PID57 PID56 23 22 21 20 19 18 17 16 – – PID53 PID52 PID51 PID50 PID49 PID48 15 14 13 12 11 10 9 8 PID47 PID46 PID45 PID44 PID43 PID42 PID41 PID40 76543210 PID39 – PID37 – PID3 5P I D 3 4P I D 3 3P I D 3 2

343SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

31.20.37 PMC SleepWalking Activity In Progress Register

Name: PMC_SLPWK_AIPR Address: 0x400E0744 Access: Read-only

• AIP: Activity In Progress 0: There is no activity on peripherals. The asynchronous partial wake-up (SleepWalking) function can be activated on one or more peripherals. The device can enter Wait mode. Only the following PIDs can be configured with asynchronous partial wake-up: UARTx and TWIHSx. 1: One or more peripherals are currently active. The device must not enter Wait mode if the asynchronous partial wake-up is enabled for one of the following PIDs: UARTx and TWIHSx. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 344 32. Parallel Input/Output Controller (PIO)

32.1 Description

The Parallel Input/Output Controller (PIO) manages up to 32 fully programm able input/output lines. Each I/O line may be dedicated as a general-purpose I/O or be assigned to a function of an embedded peripheral. This ensures effective optimization of the pins of the product. Each I/O line is associated with a bit number in all of the 32-bit registers of the 32-bit wide user interface. Each I/O line of the PIO Controller features:  An input change interrupt enabling level change detection on any I/O line.  Additional Interrupt modes enabling rising edge, falling edge, low-level or high-level detection on any I/O line.  A glitch filter providing rejection of glitches lower than one-half of peripheral clock cycle.  A debouncing filter providing rejection of unwanted pulses from key or push button operations.  Multi-drive capability similar to an open drain I/O line.  Control of the pull-up and pull-down of the I/O line.  Input visibility and output control. The PIO Controller also features a synchronous output prov iding up to 32 bits of data output in a single write operation. An 8-bit parallel capture mode is also available whic h can be used to interface a CMOS digital image sensor, an ADC, a DSP synchronous port in synchronous mode, etc.

345SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

32.2 Embedded Characteristics

 Up to 32 Programmable I/O Lines  Fully Programmable through Set/Clear Registers  Multiplexing of Four Peripheral Functions per I/O Line  For each I/O Line (Whether Assigned to a Peripheral or Used as General Purpose I/O) ̶ Input Change Interrupt ̶ Programmable Glitch Filter ̶ Programmable Debouncing Filter ̶ Multi-drive Option Enables Driving in Open Drain ̶ Programmable Pull-Up on Each I/O Line ̶ Pin Data Status Register, Supplies Visibility of the Level on the Pin at Any Time ̶ Additional Interrupt Modes on a Programmable Event: Rising Edge, Falling Edge, Low-Level or High- Level ̶ Lock of the Configuration by the Connected Peripheral  Synchronous Output, Provides Set and Clear of Several I/O Lines in a Single Write  Register Write Protection  Programmable Schmitt Trigger Inputs  Programmable I/O Drive  Parallel Capture Mode ̶ Can Be Used to Interface a CMOS Digital Image Sensor, an ADC, etc. ̶ One Clock, 8-bit Parallel Data and Two Data Enable on I/O Lines ̶ Data Can be Sampled Every Other Time (For Chrominance Sampling Only) ̶ Supports Connection of One DMA Controller Channel Which Offers Buffer Reception Without Processor Intervention

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 346

32.3 Block Diagram

Figure 32-1. Block Diagram Embedded Peripheral Embedded Peripheral PIO Interrupt PIO Controller Parallel Capture Mode PMC Up to x peripheral IOs Up to x peripheral IOs Peripheral Clock APB Data, Enable PIN x-1 PIN 1 PIN 0 Data, Enable DMA Data Events PIODCCLK PIODC[7:0] PIODCEN1 PIODCEN2 Interrupt Controller x is an integer representing the maximum number of IOs managed by one PIO controller. Table 32-1. Signal Description Signal Name Signal Description Signal Type PIODCCLK Parallel Capture Mode Clock Input PIODC[7:0] Parallel Capture Mode Data Input PIODCEN1 Parallel Capture Mode Data Enable 1 Input PIODCEN2 Parallel Capture Mode Data Enable 2 Input

347SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

32.4 Product Dependencies

32.4.1 Pin Multiplexing

Each pin is configurable, depending on the product, as ei ther a general-purpose I/O line only, or as an I/O line multiplexed with one or two peripheral I/Os. As the multiplexing is hardware defined and thus product-dependent, the hardware designer and programmer must carefully determine the configuration of the PIO Controllers required by their application. When an I/O line is general-purpose only, i.e., not multiplexed with any peripheral I/O, programming of the PIO Controller regarding the assignment to a peripheral has no effect and only the PIO Controller can control how the pin is driven by the product.

32.4.2 External Interrupt Lines

When the WKUPx input pins must be used as external interrupt lines, the PIO Controller must be configured to disable the peripheral control on these IOs, and the corresponding IO lines must be set to Input mode.

32.4.3 Power Management

The Power Management Controller controls the peripheral clock in order to save power. Writing any of the registers of the user interface does not require the peripheral clock to be enabled. This means that the configuration of the I/O lines does not require the peripheral clock to be enabled. However, when the clock is disabled, not all of the features of the PIO Controller are available, including glitch filtering. Note that the input change interrupt, the interrupt modes on a programmable event and the read of the pin level require the clock to be validated. After a hardware reset, the peripheral clock is disabled by default. The user must configure the Power Management Controller before any access to the input line information.

32.4.4 Interrupt Sources

For interrupt handling, the PIO Controllers are considered as user peripherals. This means that the PIO Controller interrupt lines are connected among the interrupt sources. Refer to the PIO Controller peripheral identifier in Section 13.1 ”Peripheral Identifiers” to identify the interrupt sources dedica ted to the PIO Controllers. Using the PIO Controller requires the Interrupt Controller to be programmed first. The PIO Controller interrupt can be generated only if the peripheral clock is enabled. Table 32-2. Peripheral IDs Instance ID PIOA 10 PIOB 11 PIOC 12 PIOD 16 PIOE 17

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 348

32.5 Functional Description

The PIO Controller features up to 32 fully-programmable I/O lines. Most of the control logic associated to each I/O is represented in Figure 32-2. In this description each signal shown represents one of up to 32 possible indexes. Figure 32-2. I/O Line Control Logic

32.5.1 Pull-up and Pull-down Resistor Control

Each I/O line is designed with an embedded pull-up resistor and an embedded pull-down resistor. The pull-up resistor can be enabled or disabled by writing to the Pull-up Enable Register (PIO_P UER) or Pull-up Disable Register (PIO_PUDR), respectively. Writing to these registers results in setting or clearing the corresponding bit in the Pull-up Status Register (PIO_PUSR). Reading a one in PIO_PUSR means the pull-up is disabled and reading a zero means the pull-up is enabled. The pull-down resist or can be enabled or disabled by writing the Pull-down Enable Register (PIO_PPDER) or the Pull-down Disable Register (PIO_PPDDR), respectively. Writing in these DQ DQ DFF Programmable Glitch or Debouncing Filter PIO_PDSR[0] PIO_ISR[0] PIO_IDR[0] PIO_IMR[0] PIO_IER[0] PIO Interrupt (Up to 32 possible inputs) PIO_ISR[31] PIO_IDR[31] PIO_IMR[31] PIO_IER[31] Pad PIO_PUDR[0] PIO_PUSR[0] PIO_PUER[0] PIO_MDDR[0] PIO_MDSR[0] PIO_MDER[0] PIO_CODR[0] PIO_ODSR[0] PIO_SODR[0] PIO_PDR[0] PIO_PSR[0] PIO_PER[0]PIO_ABCDSR1[0] PIO_ODR[0] PIO_OSR[0] PIO_OER[0] Peripheral Clock Resynchronization Stage Peripheral A Input Peripheral D Output Enable Peripheral A Output Enable EVENT DETECTORDFF PIO_IFDR[0] PIO_IFSR[0] PIO_IFER[0] Peripheral Clock Clock Divider PIO_IFSCSR[0] PIO_IFSCER[0] PIO_IFSCDR[0] PIO_SCDR Slow Clock Peripheral B Output Enable Peripheral C Output Enable Peripheral D Output Peripheral A Output Peripheral B Output Peripheral C Output PIO_ABCDSR2[0] Peripheral B Input Peripheral C Input Peripheral D Input PIO_PPDDR[0] PIO_PPDSR[0] PIO_PPDER[0] VDD GND Integrated Pull-Down Resistor Integrated Pull-Up Resistor div_slck

349SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 registers results in setting or clearing the correspond ing bit in the Pull-down Status Register (PIO_PPDSR). Reading a one in PIO_PPDSR means the pull-up is disabled and reading a zero means the pull-down is enabled. Enabling the pull-down resistor while th e pull-up resistor is still enabled is not possible. In this case, the write of PIO_PPDER for the relevant I/O line is discarded. Likewise, enabling the pull-up resistor while the pull-down resistor is still enabled is not possible. In this case, the write of PIO_PUER for the relevant I/O line is discarded. Control of the pull-up resistor is possible regardless of the configuration of the I/O line. After reset, depending on the I/O, pull-up or pull-down can be set.

32.5.2 I/O Line or Peripheral Function Selection

When a pin is multiplexed with one or two peripheral functions, the selection is controlled with the Enable Register (PIO_PER) and the Disable Register (PIO_PDR). The Status Register (PIO_PSR) is the result of the set and clear registers and indicates whether the pin is controlled by the corresponding peripheral or by the PIO Controller. A value of zero indicates that the pin is controlled by the corresponding on-chip peripheral selected in the ABCD Select registers (PIO_ABCDSR1 and PIO_ABCDSR2). A valu e of one indicates the pin is controlled by the PIO Controller. If a pin is used as a general-purpose I/O line (not multiplexed with an on-chip peripheral), PIO_PER and PIO_PDR have no effect and PIO_PSR returns a one for the corresponding bit. After reset, the I/O lines are controlled by the PIO Controller, i.e., PIO_PSR resets at one. However, in some events, it is important that PIO lines are controlled by the peripheral (as in the case of memory chip select lines that must be driven inactive after reset, or for address lines that must be driven low for booting out of an external memory). Thus, the reset value of PIO_PSR is defined at the product level and depends on the multiplexing of the device.

32.5.3 Peripheral A or B or C or D Selection

The PIO Controller provides multiplexing of up to fo ur peripheral functions on a single pin. The selection is performed by writing PIO_ABCDSR1 and PIO_ABCDSR2. For each pin:  The corresponding bit at level zero in PIO_ABCDSR1 and the corresponding bit at level zero in PIO_ABCDSR2 means peripheral A is selected.  The corresponding bit at level one in PIO_ABCDSR1 and the corresponding bit at level zero in PIO_ABCDSR2 means peripheral B is selected.  The corresponding bit at level zero in PIO_ABCDSR1 and the corresponding bit at level one in PIO_ABCDSR2 means peripheral C is selected.  The corresponding bit at level one in PIO_ABCDSR1 and the corresponding bit at level one in PIO_ABCDSR2 means peripheral D is selected. Note that multiplexing of peripheral li nes A, B, C and D only affects the outp ut line. The peripheral input lines are always connected to the pin input (see Figure 32-2). Writing in PIO_ABCDSR1 and PIO_ABCDS R2 manages the multiplexing regardless of the configuration of the pin. However, assignment of a pin to a peripheral function requires a write in PIO_ABCDSR1 and PIO_ABCDSR2 in addition to a write in PIO_PDR. After reset, PIO_ABCDSR1 and PIO_ABCDSR2 are zero, thus indicating t hat all the PIO lines are configured on peripheral A. However, peripheral A generally does not drive the pin as the PIO Controller resets in I/O line mode. If the software selects a peripheral A, B, C or D which does not exist for a pin, no alternate functions are enabled for this pin and the selection is taken into account. The PIO Controller does not carry out checks to prevent selection of a peripheral which does not exist.

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 350

32.5.4 Output Control

When the I/O line is assigned to a peripheral function, i.e., the corresponding bit in PIO_PSR is at zero, the drive of the I/O line is controlled by the peripheral. Peripheral A or B or C or D depending on the value in PIO_ABCDSR1 and PIO_ABCDSR2 determines whether the pin is driven or not. When the I/O line is controlled by the PIO Controller, the pin can be configured to be driven. This is done by writing the Output Enable Register (PIO_O ER) and Output Disable Register (PIO_ODR). The results of these write operations are detected in the Output St atus Register (PIO_OSR). When a bit in this register is at zero, the corresponding I/O line is used as an input only. When the bit is at one, the corresponding I/O line is driven by the PIO Controller. The level driven on an I/O line can be determined by writing in the Set Output Data Register (PIO_SODR) and the Clear Output Data Register (PIO_CODR). These write operations, respectively, set and clear the Output Data Status Register (PIO_ODSR), which represents the data driven on th e I/O lines. Writing in PIO_OER and PIO_ODR manages PIO_OSR whether the pi n is configured to be controlled by the PIO Controller or assigned to a peripheral function. This enables configuration of the I/O line prior to setting it to be managed by the PIO Controller. Similarly, writing in PIO_SO DR and PIO_CODR affects PIO_ODSR. This is important as it defines the first level driven on the I/O line.

32.5.5 Synchronous Data Output

Clearing one or more PIO line(s) and setting another one or more PIO line(s) synchronously cannot be done by using PIO_SODR and PIO_CODR. It requires two successive write operations into two different registers. To overcome this, the PIO Controller offers a direct control of PIO outputs by single write access to PIO_ODSR. Only bits unmasked by the Output Write Status Register (PIO_OWSR) are written. The mask bits in PIO_OWSR are set by writing to the Output Write Enable Register (PIO_OWE R) and cleared by writing to the Output Write Disable Register (PIO_OWDR). After reset, the synchronous data output is disabled on all the I/O lines as PIO_OWSR resets at 0x0.

32.5.6 Multi-Drive Control (Open Drain)

Each I/O can be independently programmed in open drain by using the multi-drive feat ure. This feature permits several drivers to be connected on the I/O line which is driven low only by each device. An external pull-up resistor (or enabling of the internal one) is generally required to guarantee a high level on the line. The multi-drive feature is controlled by the Multi-driver Enable Register (PIO_MDER) and the Multi-driver Disable Register (PIO_MDDR). The multi-drive can be selected whether the I/O line is controlled by the PIO Controller or assigned to a peripheral function. The Multi-driver St atus Register (PIO_MDSR) indicates the pins that are configured to support external drivers. After reset, the multi-drive feature is disabled on all pins, i.e., PIO_MDSR resets at value 0x0.

32.5.7 Output Line Timings

Figure 32-3 shows how the outputs are driven either by writi ng PIO_SODR or PIO_CODR, or by directly writing PIO_ODSR. This last case is valid only if the corresponding bit in PIO_OWSR is set. Figure 32-3 also shows when the feedback in the Pin Data Status Register (PIO_PDSR) is available.

351SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 Figure 32-3. Output Line Timings

32.5.8 Inputs

The level on each I/O line can be read through PIO_PDSR. This register indicates the level of the I/O lines regardless of their configuration, whether uniquely as an input, or driven by the PIO Controller, or driven by a peripheral. Reading the I/O line levels requires the clock of the PI O Controller to be enabled, otherwise PIO_PDSR reads the levels present on the I/O line at the time the clock was disabled.

32.5.9 Input Glitch and Debouncing Filters

Optional input glitch and debouncing filters are independently programmable on each I/O line. The glitch filter can filter a glitch with a duration of less than 1/2 peripheral clock and the debouncing filter can filter a pulse of less than 1/2 period of a programmable divided slow clock. The selection between glitch filtering or debounce filterin g is done by writing in the PIO Input Filter Slow Clock Disable Register (PIO_IFSCDR) and the PIO Input Filter Slow Clock Enable Register (PIO_IFSCER). Writing PIO_IFSCDR and PIO_IFSCER, re spectively, sets and clears bits in the Input Filter Slow Clock Status Register (PIO_IFSCSR). The current selection status can be checked by reading the PIO_IFSCSR.  If PIO_IFSCSR[i] = 0: The glitch filter can filter a glitch with a duration of less than 1/2 master clock period.  If PIO_IFSCSR[i] = 1: The debouncing filter can filter a pulse with a duration of less than 1/2 programmable divided slow clock period. For the debouncing filter, the period of the divided slow clock is defined by writing in the DIV field of the Slow Clock Divider Debouncing Register (PIO_SCDR): t div_slck = ((DIV + 1) × 2) × tslck When the glitch or debouncing filter is enabled, a glitch or pulse with a duration of less than 1/2 selected clock cycle (selected clock represents peripheral clock or divided slow clock depending on PIO_IFSCDR and PIO_IFSCER programming) is automatically rejected, while a pulse with a duration of one selected clock (peripheral clock or divided slow clock) cycle or more is accepted. For pulse durations between 1/2 selected clock cycle and one selected clock cycle, the pulse may or ma y not be taken into account, depending on the precise timing of its occurrence. Thus for a pulse to be visible, it must exceed one selected clock cycle, whereas for a glitch to be reliably filtered out, its duration must not exceed 1/2 selected clock cycle. The filters also introduce some latencies, illustrated in Figure 32-4 and Figure 32-5. 2 cycles APB Access 2 cycles APB Access Peripheral clock Write PIO_SODR Write PIO_ODSR at 1 PIO_ODSR PIO_PDSR Write PIO_CODR Write PIO_ODSR at 0

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 352 The glitch filters are controlled by t he Input Filter Enable Regi ster (PIO_IFER), the Input Filter Disable Register (PIO_IFDR) and the Input Filter Status Register (PIO_IF SR). Writing PIO_IFER and PIO_IFDR respectively sets and clears bits in PIO_IFSR. This last register enables the glitch filter on the I/O lines. When the glitch and/or debouncing filter is enabled, it does not modify the beha vior of the inputs on the peripherals. It acts only on the value read in PIO_PDSR and on the input change interrupt detection. The glitch and debouncing filters require that the peripheral clock is enabled. Figure 32-4. Input Glitch Filter Timing Figure 32-5. Input Debouncing Filter Timing

32.5.10 Input Edge/Level Interrupt

The PIO Controller can be programmed to generate an interrupt when it detects an edge or a level on an I/O line. The Input Edge/Level interrupt is controlled by writing the Interrupt Enable Register (PIO_IER) and the Interrupt Disable Register (PIO_IDR), whic h enable and disable the input change inte rrupt respectively by setting and clearing the corresponding bit in the Interrupt Mask Register (PIO_IMR). As input change detection is possible only by comparing two successive samplings of the input of the I/O line, the peripheral clock must be enabled. The Input Change interrupt is available regardless of the configur ation of the I/O line, i.e., configured as an input only, controlled by the PIO Controller or assigned to a peripheral function. By default, the interrupt can be generated at any time an edge is detected on the input. Some additional interrupt modes can be enabled/disabled by writing in the Additional Interrupt Modes Enable Register (PIO_AIMER) and Additional Interrupt Modes Di sable Register (PIO_AIMDR). The current state of this selection can be read through the Additional Interrupt Modes Mask Register (PIO_AIMMR). These additional modes are: Peripheral clcok Pin Level PIO_PDSR if PIO_IFSR = 0 PIO_PDSR if PIO_IFSR = 1 1 cycle 1 cycle 1 cycle up to 1.5 cycles 2 cycles up to 2.5 cycles up to 2 cycles 1 cycle 1 cycle PIO_IFCSR = 0 Divided Slow Clock (div_slck) Pin Level PIO_PDSR if PIO_IFSR = 0 PIO_PDSR if PIO_IFSR = 1 1 cycle tdiv_slck up to 1.5 cycles tdiv_slck 1 cycle tdiv_slck up to 2 cycles tperipheral clock up to 2 cycles tperipheral clock up to 2 cycles tperipheral clockup to 2 cycles tperipheral clock up to 1.5 cycles tdiv_slck PIO_IFCSR = 1

353SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16  Rising edge detection  Falling edge detection  Low-level detection  High-level detection In order to select an additional interrupt mode:  The type of event detection (edge or level) must be selected by writing in the Edge Select Register (PIO_ESR) and Level Select Register (PIO_LSR) which select, respectively, the edge and level detection. The current status of this selection is accessible through the Edge/Level Status Register (PIO_ELSR).  The polarity of the event detection (rising/falling edge or high/low-level) must be selected by writing in the Falling Edge/Low-Level Select Register (PIO_FELLSR) and Rising Edge/High-Level Select Register (PIO_REHLSR) which allow to select falling or rising edge (if edge is selected in PIO_ELSR) edge or high- or low-level detection (if level is selected in PIO_ELSR). The current status of this selection is accessible through the Fall/Rise - Low/High Status Register (PIO_FRLHSR). When an input edge or level is detected on an I/O line, the corresponding bit in the Interrupt Status Register (PIO_ISR) is set. If the corresponding bit in PIO_IMR is set, the PIO Controller interrupt line is asserted.The interrupt signals of the 32 channels are ORed-wired together to generate a single interrupt signal to the interrupt controller. When the software reads PIO_ISR, all the interrupts are autom atically cleared. This signifies that all the interrupts that are pending when PIO_ISR is read must be handled. When an Interrupt is enabled on a “level”, the interrupt is generated as long as the interrupt source is not cleared, even if some read accesses in PIO_ISR are performed.

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 354 Figure 32-6. Event Detector on Input Lines (Figure Represents Line 0) Example of interrupt generation on following lines:  Rising edge on PIO line 0  Falling edge on PIO line 1  Rising edge on PIO line 2  Low-level on PIO line 3  High-level on PIO line 4  High-level on PIO line 5  Falling edge on PIO line 6  Rising edge on PIO line 7  Any edge on the other lines Table 32-3 provides the required configuration for this example. Event Detector Edge Detector Falling Edge Detector Rising Edge Detector PIO_FELLSR[0] PIO_FRLHSR[0] PIO_REHLSR[0] Low Level Detector High Level Detector PIO_ESR[0] PIO_ELSR[0] PIO_LSR[0] PIO_AIMDR[0] PIO_AIMMR[0] PIO_AIMER[0] Event detection on line 0 Resynchronized input on line 0 Table 32-3. Configuration for Example Interrupt Generation Configuration Description Interrupt Mode All the interrupt sources are enabled by writing 32’hFFFF_FFFF in PIO_IER. Then the additional interrupt mode is enabled for lines 0 to 7 by writing 32’h0000_00FF in PIO_AIMER. Edge or Level Detection Lines 3, 4 and 5 are configured in level detection by writing 32’h0000_0038 in PIO_LSR. The other lines are configured in edge detection by default, if they have not been previously configured. Otherwise, lines 0, 1, 2, 6 and 7 must be configured in edge detection by writing 32’h0000_00C7 in PIO_ESR. Falling/Rising Edge or Low/High-Level Detection Lines 0, 2, 4, 5 and 7 are configured in rising edge or high-level detection by writing 32’h0000_00B5 in PIO_REHLSR. The other lines are configured in falling edge or low-level detection by default if they have not been previously configured. Otherwise, lines 1, 3 and 6 must be configured in falling edge/low-level detection by writing 32’h0000_004A in PIO_FELLSR.

355SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 Figure 32-7. Input Change Interrupt Timing s When No Additional Interrupt Modes

32.5.11 I/O Lines Lock

When an I/O line is controlled by a peripheral (particularly the Pulse Width Modulati on Controller PWM), it can become locked by the action of this peripheral via an in put of the PIO Controller. When an I/O line is locked, the write of the corresponding bit in PIO_PER, PIO_PDR, PIO_MDER, PIO_MDDR, PIO_PUDR, PIO_PUER, PIO_ABCDSR1 and PIO_ABCDSR2 is discarded in order to lock its configuration. The user can know at anytime which I/O line is locked by reading the PIO Lock Status Register (PIO_LOCKSR). Once an I/O line is locked, the only way to unlock it is to apply a hardware reset to the PIO Controller.

32.5.12 Programmable I/O Drive

It is possible to configure the I/O drive for pads PA 0-PA31, PB0-PB13, PC0-PC31, PD0-PD31 and PE0-PE5.. Refer to Section 56. “Electrical Characteristics”.

32.5.13 Programmable Schmitt Trigger

It is possible to configure each input for the Schmitt trigger. By default the Schmitt tri gger is active. Disabling the Schmitt trigger is requested when using the QTouch® Library.

32.5.14 Parallel Capture Mode

32.5.14.1 Overview

The PIO Controller integrates an interface able to read data from a CMOS digital image sensor, a high-speed parallel ADC, a DSP synchronous port in synchronous mode, etc. For better understanding and to ease reading, the following description uses an example with a CMOS digital image sensor.

32.5.14.2 Functional Description

The CMOS digital image sensor provides a sensor clock, an 8-bit data synchronous with the sensor clock and two data enables which are also synchronous with the sensor clock. Peripheral clock Pin Level Read PIO_ISR APB Access PIO_ISR APB Access

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 356 As soon as the parallel capture mode is enabled by writing a one to the PCEN bit in PIO_ PCMR, the I/O lines connected to the sensor clock (PIODCCLK), the sensor data (PIODC[7:0]) and the sensor data enable signals (PIODCEN1 and PIODCEN2) are configured automatically as inputs. To know which I/O lines are associated with the sensor clock, the sensor data and the sensor data enable signals, refer to the I/O multiplexing table(s) in Section 5. “Package and Pinout”. Once enabled, the parallel capture mode samples the data at rising edge of the sensor clock and resynchronizes it with the peripheral clock domain. The size of the data which can be r ead in PIO_PCRHR can be programmed using the DSIZE field in PIO_PCMR. If this data size is larger than 8 bits, then the parallel capture mode samples several sensor data to form a concatenated data of size defined by DSIZE. Then this data is st ored in PIO_PCRHR and the flag DRDY is set to one in PIO_PCISR. The parallel capture mode can take into account the sensor data enable signals or not. If the bit ALWYS is set to zero in PIO_PCMR, the parallel capture mode samples the sensor data at the rising edge of the sensor clock only if both data enable signals are active (at one). If the bit ALWYS is set to one, the parallel capture mode samples the sensor data at the rising edge of the sensor clock whichever the data enable signals are. The parallel capture mode can sample the sensor data only one time out of two. This is particularly useful when the user wants only to sample the luminance Y of a CMOS digital image sensor which outputs a YUV422 data stream. If the HALFS bit is set to zero in PIO_PCMR, the parallel captur e mode samples the sensor data in the conditions described above. If the HALFS bit is set to one in PIO_PCMR, the parallel capture mode samples the sensor data in the conditions described above, but only one time out of two. Depending on the FRSTS bit in PIO_PCMR, the sensor can either sample the even or odd sensor data. If sensor data are numbered in the order that they are received with an index from zero to n, if FRSTS equals zero then only data with an even index are sampled. If FRSTS equals one, then only data with an odd index are sampled. If data is ready in PIO_PCRHR and it is not read before a new data is stored in PIO_PCRH R, then an overrun error occurs. The previous data is lost and the OVRE flag in PIO_PCISR is set to one. This fl ag is automatically reset when PIO_PCISR is read (reset after read). Figure 32-8. PIO Controller Connection with CMOS Digital Image Sensor PIO Controller Parallel Capture Mode CMOS Digital Image Sensor DMA Data Events PIODCCLK PIODC[7:0] PIODCEN1 PIODCEN2 PCLK DATA[7:0] VSYNC HSYNC The parallel capture mode can be associated with a re ception channel of the DMA Controller. This performs reception transfer from parallel capture mode to a memory buffer without any intervention from the CPU. The flags DRDY and OVRE can be a source of the PIO interrupt.

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 358 Figure 32-11. Parallel Capture Mode Waveforms (DSIZE = 2, ALWYS = 0, HALFS = 1, FRSTS = 0) Figure 32-12. Parallel Capture Mode Waveforms (DSIZE = 2, ALWYS = 0, HALFS = 1, FRSTS = 1)

32.5.14.3 Restrictions

 Configuration fields DSIZE, ALWYS, HALFS and FRSTS in PIO_PCMR can be changed ONLY if the parallel capture mode is disabled at this time (PCEN = 0 in PIO_PCMR).  The frequency of peripheral clock must be strictly superior to two times the frequency of the clock of the device which generates the parallel data. 0x23 0x34 0x450x12 0x56 0x67 0x78 0x89 0x6745_2301 PIODCLK PIODC[7:0] PIODCEN1 PIODCEN2 DRDY (PIO_PCISR) RDATA (PIO_PCRHR) 0x01 Read of PIO_PCISR MCK 0x23 0x34 0x450x12 0x56 0x67 0x78 0x89 0x7856_3412 0x01 PIODCLK PIODC[7:0] PIODCEN1 PIODCEN2 DRDY (PIO_PCISR) RDATA (PIO_PCRHR) Read of PIO_PCISR MCK

359SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

32.5.14.4 Programming Sequence

1. Write PIO_PCIDR and PIO_PCIER in order to configure the parallel capture mode interrupt mask. 2. Write PIO_PCMR to set the fields DSIZE, ALWYS, HALFS and FRSTS in order to configure the parallel capture mode WITHOUT enabling the parallel capture mode. 3. Write PIO_PCMR to set the PCEN bit to one in order to enable the parallel capture mode WITHOUT changing the previous configuration. 4. Wait for a data ready by polling the DRDY flag in PIO_PCISR or by waiting for the corresponding interrupt. 5. Check OVRE flag in PIO_PCISR. 6. Read the data in PIO_PCRHR. 7. If new data are expected, go to step 4. 8. Write PIO_PCMR to set the PCEN bit to zero in order to disable the parallel capture mode WITHOUT changing the previous configuration. With DMA 1. Write PIO_PCIDR and PIO_PCIER in order to configure the parallel capture mode interrupt mask. 2. Configure DMA transfer in DMA registers. 3. Write PIO_PCMR to set the fields DSIZE, ALWYS, HALFS and FRSTS in order to configure the parallel capture mode WITHOUT enabling the parallel capture mode. 4. Write PIO_PCMR to set PCEN bit to one in order to enable the parallel capture mode WITHOUT changing the previous configuration. 5. Wait for the DMA status flag to indicate that the buffer transfer is complete. 6. Check OVRE flag in PIO_PCISR. 7. If a new buffer transfer is expected, go to step 5 . 8. Write PIO_PCMR to set the PCEN bit to zero in order to disable the parallel capture mode WITHOUT changing the previous configuration.

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 360

32.5.15 I/O Lines Programming Example

The programming example shown in Table 32-4 is used to obtain the following configuration:  4-bit output port on I/O lines 0 to 3 (should be written in a single write operation), open-drain, with pull-up resistor  Four output signals on I/O lines 4 to 7 (to drive LEDs for example), driven high and low, no pull-up resistor, no pull-down resistor  Four input signals on I/O lines 8 to 11 (to read push-button states for example), with pull-up resistors, glitch filters and input change interrupts  Four input signals on I/O line 12 to 15 to read an external device status (polled, thus no input change interrupt), no pull-up resistor, no glitch filter  I/O lines 16 to 19 assigned to peripheral A functions with pull-up resistor  I/O lines 20 to 23 assigned to peripheral B functions with pull-down resistor  I/O lines 24 to 27 assigned to peripheral C with input change interrupt, no pull-up resistor and no pull-down resistor  I/O lines 28 to 31 assigned to peripheral D, no pull-up resistor and no pull-down resistor Table 32-4. Programming Example Register Value to be Written PIO_PER 0x0000_FFFF PIO_PDR 0xFFFF_0000 PIO_OER 0x0000_00FF PIO_ODR 0xFFFF_FF00 PIO_IFER 0x0000_0F00 PIO_IFDR 0xFFFF_F0FF PIO_SODR 0x0000_0000 PIO_CODR 0x0FFF_FFFF PIO_IER 0x0F00_0F00 PIO_IDR 0xF0FF_F0FF PIO_MDER 0x0000_000F PIO_MDDR 0xFFFF_FFF0 PIO_PUDR 0xFFF0_00F0 PIO_PUER 0x000F_FF0F PIO_PPDDR 0xFF0F_FFFF PIO_PPDER 0x00F0_0000 PIO_ABCDSR1 0xF0F0_0000 PIO_ABCDSR2 0xFF00_0000 PIO_OWER 0x0000_000F PIO_OWDR 0x0FFF_ FFF0

361SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

32.5.16 Register Write Protection

To prevent any single software error from corrupting PIO behavior, certain registers in the address space can be write-protected by setting the WPEN bit in the PIO Write Protection Mode Register (PIO_WPMR). If a write access to a write-protected register is detected, the WPVS flag in the PIO Write Protection Status Register (PIO_WPSR) is set and the field WPVSRC indicates the register in which the write access has been attempted. The WPVS bit is automatically cleared after reading the PIO_WPSR. The following registers can be write-protected:  PIO Enable Register  PIO Disable Register  PIO Output Enable Register  PIO Output Disable Register  PIO Input Filter Enable Register  PIO Input Filter Disable Register  PIO Multi-driver Enable Register  PIO Multi-driver Disable Register  PIO Pull-Up Disable Register  PIO Pull-Up Enable Register  PIO Peripheral ABCD Select Register 1  PIO Peripheral ABCD Select Register 2  PIO Output Write Enable Register  PIO Output Write Disable Register  PIO Pad Pull-Down Disable Register  PIO Pad Pull-Down Enable Register  PIO Parallel Capture Mode Register

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 362

32.6 Parallel Input/Output Contro ller (PIO) User Interface

Each I/O line controlled by the PIO Cont roller is associated with a bit in each of the PIO Controller User Interface registers. Each register is 32-bit wide. If a parallel I/ O line is not defined, writing to the corresponding bits has no effect. Undefined bits read zero. If the I/O line is not multiplexed with any peripheral, the I/O line is controlled by the PIO Controller and PIO_PSR returns one systematically. Table 32-5. Register Mapping Offset Register Name Access Reset 0x0000 PIO Enable Register PIO_PER Write-only – 0x0004 PIO Disable Register PIO_PDR Write-only – 0x0008 PIO Status Register PIO_PSR Read-only (1) 0x000C Reserved – – – 0x0010 Output Enable Register PIO_OER Write-only – 0x0014 Output Disable Register PIO_ODR Write-only – 0x0018 Output Status Register PIO_OSR Read-only 0x00000000 0x001C Reserved – – – 0x0020 Glitch Input Filter Enable Register PIO_IFER Write-only – 0x0024 Glitch Input Filter Disable Register PIO_IFDR Write-only – 0x0028 Glitch Input Filter Status Register PIO_IFSR Read-only 0x00000000 0x002C Reserved – – – 0x0030 Set Output Data Register PIO_SODR Write-only – 0x0034 Clear Output Data Register PIO_CODR Write-only 0x0038 Output Data Status Register PIO_ODSR Read-only or(2) Read/Write 0x003C Pin Data Status Register PIO_PDSR Read-only (3) 0x0040 Interrupt Enable Register PIO_IER Write-only – 0x0044 Interrupt Disable Register PIO_IDR Write-only – 0x0048 Interrupt Mask Register PIO_IMR Read-only 0x00000000 0x004C Interrupt Status Register(4) PIO_ISR Read-only 0x00000000 0x0050 Multi-driver Enable Register PIO_MDER Write-only – 0x0054 Multi-driver Disable Register PIO_MDDR Write-only – 0x0058 Multi-driver Status Register PIO_MDSR Read-only 0x00000000 0x005C Reserved – – – 0x0060 Pull-up Disable Register PIO_PUDR Write-only – 0x0064 Pull-up Enable Register PIO_PUER Write-only – 0x0068 Pad Pull-up Status Register PIO_PUSR Read-only (1) 0x006C Reserved – – –

363SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 0x0070 Peripheral Select Register 1 PIO_ABCDSR1 Read/Write 0x00000000 0x0074 Peripheral Select Register 2 PIO_ABCDSR2 Read/Write 0x00000000 0x0078–0x007C Reserved – – – 0x0080 Input Filter Slow Clock Disable Register PIO_IFSCDR Write-only – 0x0084 Input Filter Slow Clock Enable Register PIO_IFSCER Write-only – 0x0088 Input Filter Slow Clock Status Register PIO_IFSCSR Read-only 0x00000000 0x008C Slow Clock Divider Debouncing Register PIO_SCDR Read/Write 0x00000000 0x0090 Pad Pull-down Disable Register PIO_PPDDR Write-only – 0x0094 Pad Pull-down Enable Register PIO_PPDER Write-only – 0x0098 Pad Pull-down Status Register PIO_PPDSR Read-only (1) 0x009C Reserved – – – 0x00A0 Output Write Enable PIO_OWER Write-only – 0x00A4 Output Write Disable PIO_OWDR Write-only – 0x00A8 Output Write Status Register PIO_OWSR Read-only 0x00000000 0x00AC Reserved – – – 0x00B0 Additional Interrupt Modes Enable Register PIO_AIMER Write-only – 0x00B4 Additional Interrupt Modes Disable Register PIO_AIMDR Write-only – 0x00B8 Additional Interrupt Modes Mask Register PIO_AIMMR Read-only 0x00000000 0x00BC Reserved – – – 0x00C0 Edge Select Register PIO_ESR Write-only – 0x00C4 Level Select Register PIO_LSR Write-only – 0x00C8 Edge/Level Status Register PIO_ELSR Read-only 0x00000000 0x00CC Reserved – – – 0x00D0 Falling Edge/Low-Level Select Register PIO_FELLSR Write-only – 0x00D4 Rising Edge/High-Level Select Register PIO_REHLSR Write-only – 0x00D8 Fall/Rise - Low/High Status Register PIO_FRLHSR Read-only 0x00000000 0x00DC Reserved – – – 0x00E0 Lock Status PIO_LOCKSR Read-only 0x00000000 0x00E4 Write Protection Mode Register PIO_WPMR Read/Write 0x00000000 0x00E8 Write Protection Status Register PIO_WPSR Read-only 0x00000000 0x00EC–0x00FC Reserved – – – 0x0100 Schmitt Trigger Register PIO_SCHMITT Read/Write 0x00000000 0x0104–0x010C Reserved – – – 0x0110 Reserved – – – 0x0114 Reserved – – – 0x0118 I/O Drive Register PIO_DRIVER Read/Write 0x00000000 0x011C Reserved – – – Table 32-5. Register Mapping (Continued) Offset Register Name Access Reset

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 364 Notes: 1. Reset value depends on the product implementation. 2. PIO_ODSR is Read-only or Read/Write depending on PIO_OWSR I/O lines. 3. Reset value of PIO_PDSR depends on the level of the I/O lines . Reading the I/O line levels requires the clock of the PIO Controller to be enabled, otherwise PIO_PDSR reads the levels present on the I/O line at the time the clock was disabled. 4. PIO_ISR is reset at 0x0. However, the first read of the register may read a different value as input changes may have occurred. 5. If an offset is not listed in the tabl e it must be considered as reserved. 0x0120–0x014C Reserved – – – 0x0150 Parallel Capture Mode Register PIO_PCMR Read/Write 0x00000000 0x0154 Parallel Capture Interrupt Enable Register PIO_PCIER Write-only – 0x0158 Parallel Capture Interrupt Disable Register PIO_PCIDR Write-only – 0x015C Parallel Capture Interrupt Mask Register PIO_PCIMR Read-only 0x00000000 0x0160 Parallel Capture Interrupt Status Register PIO_PCISR Read-only 0x00000000 0x0164 Parallel Capture Reception Holding Register PIO_PCRHR Read-only 0x00000000 0x0168–0x018C Reserved – – – Table 32-5. Register Mapping (Continued) Offset Register Name Access Reset

365SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

32.6.1 PIO Enable Register

Name: PIO_PER Address: 0x400E0E00 (PIOA), 0x400E1000 (PIOB), 0x400E1200 (PIOC), 0x400E1400 (PIOD), 0x400E1600 (PIOE) Access: Write-only This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register.

• P0–P31: PIO Enable 0: No effect. 1: Enables the PIO to control the corresponding pin (disables peripheral control of the pin). 31 302 92 82 72 62 52 4 P31P 30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543 210 P7 P6 P5 P4 P3 P2 P1 P0

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 366

32.6.2 PIO Disable Register

Name: PIO_PDR Address: 0x400E0E04 (PIOA), 0x400E1004 (PIOB), 0x400E1204 (PIOC), 0x400E1404 (PIOD), 0x400E1604 (PIOE) Access: Write-only This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register.

• P0–P31: PIO Disable 0: No effect. 1: Disables the PIO from controlling the corresponding pin (enables peripheral control of the pin). 31 302 92 82 72 62 52 4 P31P 30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543 210 P7 P6 P5 P4 P3 P2 P1 P0

367SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

32.6.3 PIO Status Register

Name: PIO_PSR Address: 0x400E0E08 (PIOA), 0x400E1008 (PIOB), 0x400E1208 (PIOC), 0x400E1408 (PIOD), 0x400E1608 (PIOE) Access: Read-only

• P0–P31: PIO Status 0: PIO is inactive on the corresponding I/O line (peripheral is active). 1: PIO is active on the corresponding I/O line (peripheral is inactive). 31 302 92 82 72 62 52 4 P31P 30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543 210 P7 P6 P5 P4 P3 P2 P1 P0

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 368

32.6.4 PIO Output Enable Register

Name: PIO_OER Address: 0x400E0E10 (PIOA), 0x400E1010 (PIOB), 0x400E1210 (PIOC), 0x400E1410 (PIOD), 0x400E1610 (PIOE) Access: Write-only This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register.

• P0–P31: Output Enable 0: No effect. 1: Enables the output on the I/O line. 31 302 92 82 72 62 52 4 P31P 30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543 210 P7 P6 P5 P4 P3 P2 P1 P0

369SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

32.6.5 PIO Output Disable Register

Name: PIO_ODR Address: 0x400E0E14 (PIOA), 0x400E1014 (PIOB), 0x400E1214 (PIOC), 0x400E1414 (PIOD), 0x400E1614 (PIOE) Access: Write-only This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register.

• P0–P31: Output Disable 0: No effect. 1: Disables the output on the I/O line. 31 302 92 82 72 62 52 4 P31P 30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543 210 P7 P6 P5 P4 P3 P2 P1 P0

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 370

32.6.6 PIO Output Status Register

Name: PIO_OSR Address: 0x400E0E18 (PIOA), 0x400E1018 (PIOB), 0x400E1218 (PIOC), 0x400E1418 (PIOD), 0x400E1618 (PIOE) Access: Read-only

• P0–P31: Output Status 0: The I/O line is a pure input. 1: The I/O line is enabled in output. 31 302 92 82 72 62 52 4 P31P 30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543 210 P7 P6 P5 P4 P3 P2 P1 P0

371SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

32.6.7 PIO Input Filter Enable Register

Name: PIO_IFER Address: 0x400E0E20 (PIOA), 0x400E1020 (PIOB), 0x400E1220 (PIOC), 0x400E1420 (PIOD), 0x400E1620 (PIOE) Access: Write-only This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register.

• P0–P31: Input Filter Enable 0: No effect. 1: Enables the input glitch filter on the I/O line. 31 302 92 82 72 62 52 4 P31P 30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543 210 P7 P6 P5 P4 P3 P2 P1 P0

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 372

32.6.8 PIO Input Filter Disable Register

Name: PIO_IFDR Address: 0x400E0E24 (PIOA), 0x400E1024 (PIOB), 0x400E1224 (PIOC), 0x400E1424 (PIOD), 0x400E1624 (PIOE) Access: Write-only This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register.

• P0–P31: Input Filter Disable 0: No effect. 1: Disables the input glitch filter on the I/O line. 31 302 92 82 72 62 52 4 P31P 30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543 210 P7 P6 P5 P4 P3 P2 P1 P0

373SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

32.6.9 PIO Input Filter Status Register

Name: PIO_IFSR Address: 0x400E0E28 (PIOA), 0x400E1028 (PIOB), 0x400E1228 (PIOC), 0x400E1428 (PIOD), 0x400E1628 (PIOE) Access: Read-only

• P0–P31: Input Filter Status 0: The input glitch filter is disabled on the I/O line. 1: The input glitch filter is enabled on the I/O line. 31 302 92 82 72 62 52 4 P31P 30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543 210 P7 P6 P5 P4 P3 P2 P1 P0

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 374

32.6.10 PIO Set Output Data Register

Name: PIO_SODR Address: 0x400E0E30 (PIOA), 0x400E1030 (PIOB), 0x400E1230 (PIOC), 0x400E1430 (PIOD), 0x400E1630 (PIOE) Access: Write-only

• P0–P31: Set Output Data 0: No effect. 1: Sets the data to be driven on the I/O line. 31 302 92 82 72 62 52 4 P31P 30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543 210 P7 P6 P5 P4 P3 P2 P1 P0

375SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

32.6.11 PIO Clear Output Data Register

Name: PIO_CODR Address: 0x400E0E34 (PIOA), 0x400E1034 (PIOB), 0x400E1234 (PIOC), 0x400E1434 (PIOD), 0x400E1634 (PIOE) Access: Write-only

• P0–P31: Clear Output Data 0: No effect. 1: Clears the data to be driven on the I/O line. 31 302 92 82 72 62 52 4 P31P 30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543 210 P7 P6 P5 P4 P3 P2 P1 P0

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 376

32.6.12 PIO Output Data Status Register

Name: PIO_ODSR Address: 0x400E0E38 (PIOA), 0x400E1038 (PIOB), 0x400E1238 (PIOC), 0x400E1438 (PIOD), 0x400E1638 (PIOE) Access: Read-only or Read/Write

• P0–P31: Output Data Status 0: The data to be driven on the I/O line is 0. 1: The data to be driven on the I/O line is 1. 31 302 92 82 72 62 52 4 P31P 30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543 210 P7 P6 P5 P4 P3 P2 P1 P0

377SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

32.6.13 PIO Pin Data Status Register

Name: PIO_PDSR Address: 0x400E0E3C (PIOA), 0x400E103C (PIOB), 0x400E123C (PIOC), 0x400E143C (PIOD), 0x400E163C (PIOE) Access: Read-only

• P0–P31: Output Data Status 0: The I/O line is at level 0. 1: The I/O line is at level 1. 31 302 92 82 72 62 52 4 P31P 30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543 210 P7 P6 P5 P4 P3 P2 P1 P0

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 378

32.6.14 PIO Interrupt Enable Register

Name: PIO_IER Address: 0x400E0E40 (PIOA), 0x400E1040 (PIOB), 0x400E1240 (PIOC), 0x400E1440 (PIOD), 0x400E1640 (PIOE) Access: Write-only

• P0–P31: Input Change Interrupt Enable 0: No effect. 1: Enables the input change interrupt on the I/O line. 31 302 92 82 72 62 52 4 P31P 30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543 210 P7 P6 P5 P4 P3 P2 P1 P0

379SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

32.6.15 PIO Interrupt Disable Register

Name: PIO_IDR Address: 0x400E0E44 (PIOA), 0x400E1044 (PIOB), 0x400E1244 (PIOC), 0x400E1444 (PIOD), 0x400E1644 (PIOE) Access: Write-only

• P0–P31: Input Change Interrupt Disable 0: No effect. 1: Disables the input change interrupt on the I/O line. 31 302 92 82 72 62 52 4 P31P 30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543 210 P7 P6 P5 P4 P3 P2 P1 P0

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 380

32.6.16 PIO Interrupt Mask Register

Name: PIO_IMR Address: 0x400E0E48 (PIOA), 0x400E1048 (PIOB), 0x400E1248 (PIOC), 0x400E1448 (PIOD), 0x400E1648 (PIOE) Access: Read-only

• P0–P31: Input Change Interrupt Mask 0: Input change interrupt is disabled on the I/O line. 1: Input change interrupt is enabled on the I/O line. 31 302 92 82 72 62 52 4 P31P 30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543 210 P7 P6 P5 P4 P3 P2 P1 P0

381SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

32.6.17 PIO Interrupt Status Register

Name: PIO_ISR Address: 0x400E0E4C (PIOA), 0x400E104C (PIOB), 0x400E124C (PIOC), 0x400E144C (PIOD), 0x400E164C (PIOE) Access: Read-only

• P0–P31: Input Change Interrupt Status 0: No input change has been detected on the I/O line since PIO_ISR was last read or since reset. 1: At least one input change has been detected on the I/O line since PIO_ISR was last read or since reset. 31 302 92 82 72 62 52 4 P31P 30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543 210 P7 P6 P5 P4 P3 P2 P1 P0

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 382

32.6.18 PIO Multi-driver Enable Register

Name: PIO_MDER Address: 0x400E0E50 (PIOA), 0x400E1050 (PIOB), 0x400E1250 (PIOC), 0x400E1450 (PIOD), 0x400E1650 (PIOE) Access: Write-only This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register.

• P0-P31: Multi-drive Enable 0: No effect. 1: Enables multi-drive on the I/O line. 31 302 92 82 72 62 52 4 P31P 30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543 210 P7 P6 P5 P4 P3 P2 P1 P0

383SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

32.6.19 PIO Multi-driver Disable Register

Name: PIO_MDDR Address: 0x400E0E54 (PIOA), 0x400E1054 (PIOB), 0x400E1254 (PIOC), 0x400E1454 (PIOD), 0x400E1654 (PIOE) Access: Write-only This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register.

• P0–P31: Multi-drive Disable 0: No effect. 1: Disables multi-drive on the I/O line. 31 302 92 82 72 62 52 4 P31P 30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543 210 P7 P6 P5 P4 P3 P2 P1 P0

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 384

32.6.20 PIO Multi-driver Status Register

Name: PIO_MDSR Address: 0x400E0E58 (PIOA), 0x400E1058 (PIOB), 0x400E1258 (PIOC), 0x400E1458 (PIOD), 0x400E1658 (PIOE) Access: Read-only

• P0–P31: Multi-drive Status 0: The multi-drive is disabled on the I/O line. The pin is driven at high- and low-level. 1: The multi-drive is enabled on the I/O line. The pin is driven at low-level only. 31 302 92 82 72 62 52 4 P31P 30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543 210 P7 P6 P5 P4 P3 P2 P1 P0

385SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

32.6.21 PIO Pull-Up Disable Register

Name: PIO_PUDR Address: 0x400E0E60 (PIOA), 0x400E1060 (PIOB), 0x400E1260 (PIOC), 0x400E1460 (PIOD), 0x400E1660 (PIOE) Access: Write-only This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register.

• P0–P31: Pull-Up Disable 0: No effect. 1: Disables the pull-up resistor on the I/O line. 31 302 92 82 72 62 52 4 P31P 30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543 210 P7 P6 P5 P4 P3 P2 P1 P0

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 386

32.6.22 PIO Pull-Up Enable Register

Name: PIO_PUER Address: 0x400E0E64 (PIOA), 0x400E1064 (PIOB), 0x400E1264 (PIOC), 0x400E1464 (PIOD), 0x400E1664 (PIOE) Access: Write-only This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register.

• P0–P31: Pull-Up Enable 0: No effect. 1: Enables the pull-up resistor on the I/O line. 31 302 92 82 72 62 52 4 P31P 30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543 210 P7 P6 P5 P4 P3 P2 P1 P0

387SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

32.6.23 PIO Pull-Up Status Register

Name: PIO_PUSR Address: 0x400E0E68 (PIOA), 0x400E1068 (PIOB), 0x400E1268 (PIOC), 0x400E1468 (PIOD), 0x400E1668 (PIOE) Access: Read-only

• P0–P31: Pull-Up Status 0: Pull-up resistor is enabled on the I/O line. 1: Pull-up resistor is disabled on the I/O line. 31 302 92 82 72 62 52 4 P31P 30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543 210 P7 P6 P5 P4 P3 P2 P1 P0

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 388

32.6.24 PIO Peripheral ABCD Select Register 1

Name: PIO_ABCDSR1 Access: Read/Write This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register.

• P0–P31: Peripheral Select If the same bit is set to 0 in PIO_ABCDSR2: 0: Assigns the I/O line to the Peripheral A function. 1: Assigns the I/O line to the Peripheral B function. If the same bit is set to 1 in PIO_ABCDSR2: 0: Assigns the I/O line to the Peripheral C function. 1: Assigns the I/O line to the Peripheral D function. 31 302 92 82 72 62 52 4 P31P 30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543 210 P7 P6 P5 P4 P3 P2 P1 P0

389SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

32.6.25 PIO Peripheral ABCD Select Register 2

Name: PIO_ABCDSR2 Address: 0x400E0E70 (PIOA), 0x400E1070 (PIOB), 0x400E1270 (PIOC), 0x400E1470 (PIOD), 0x400E1670 (PIOE) Access: Read/Write This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register.

• P0–P31: Peripheral Select If the same bit is set to 0 in PIO_ABCDSR1: 0: Assigns the I/O line to the Peripheral A function. 1: Assigns the I/O line to the Peripheral C function. If the same bit is set to 1 in PIO_ABCDSR1: 0: Assigns the I/O line to the Peripheral B function. 1: Assigns the I/O line to the Peripheral D function. 31 302 92 82 72 62 52 4 P31P 30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543 210 P7 P6 P5 P4 P3 P2 P1 P0

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 390

32.6.26 PIO Input Filter Slow Clock Disable Register

Name: PIO_IFSCDR Address: 0x400E0E80 (PIOA), 0x400E1080 (PIOB), 0x400E1280 (PIOC), 0x400E1480 (PIOD), 0x400E1680 (PIOE) Access: Write-only

• P0–P31: Peripheral Clock Glitch Filtering Select 0: No effect. 1: The glitch filter is able to filter glitches with a duration < tperipheral clock/2. 31 302 92 82 72 62 52 4 P31P 30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543 210 P7 P6 P5 P4 P3 P2 P1 P0

391SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

32.6.27 PIO Input Filter Slow Clock Enable Register

Name: PIO_IFSCER Address: 0x400E0E84 (PIOA), 0x400E1084 (PIOB), 0x400E1284 (PIOC), 0x400E1484 (PIOD), 0x400E1684 (PIOE) Access: Write-only

• P0–P31: Slow Clock Debouncing Filtering Select 0: No effect. 1: The debouncing filter is able to filter pulses with a duration < tdiv_slck/2. 31 302 92 82 72 62 52 4 P31P 30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543 210 P7 P6 P5 P4 P3 P2 P1 P0

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 392

32.6.28 PIO Input Filter Slow Clock Status Register

Name: PIO_IFSCSR Address: 0x400E0E88 (PIOA), 0x400E1088 (PIOB), 0x400E1288 (PIOC), 0x400E1488 (PIOD), 0x400E1688 (PIOE) Access: Read-only

• P0–P31: Glitch or Debouncing Filter Selection Status 0: The glitch filter is able to filter glitches with a duration < tperipheral clock/2. 1: The debouncing filter is able to filter pulses with a duration < tdiv_slck/2. 31 302 92 82 72 62 52 4 P31P 30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543 210 P7 P6 P5 P4 P3 P2 P1 P0

393SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

32.6.29 PIO Slow Clock Di vider Debouncing Register

Name: PIO_SCDR Address: 0x400E0E8C (PIOA), 0x400E108C (PIOB), 0x400E128C (PIOC), 0x400E148C (PIOD), 0x400E168C (PIOE) Access: Read/Write

• DIV: Slow Clock Divider Selection for Debouncing tdiv_slck = ((DIV + 1) × 2) × tslck 31 302 92 82 72 62 52 4 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 –– DIV 76543 210 DIV

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 394

32.6.30 PIO Pad Pull-Down Disable Register

Name: PIO_PPDDR Address: 0x400E0E90 (PIOA), 0x400E1090 (PIOB), 0x400E1290 (PIOC), 0x400E1490 (PIOD), 0x400E1690 (PIOE) Access: Write-only This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register.

• P0–P31: Pull-Down Disable 0: No effect. 1: Disables the pull-down resistor on the I/O line. 31 302 92 82 72 62 52 4 P31P 30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543 210 P7 P6 P5 P4 P3 P2 P1 P0

395SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

32.6.31 PIO Pad Pull-Down Enable Register

Name: PIO_PPDER Address: 0x400E0E94 (PIOA), 0x400E1094 (PIOB), 0x400E1294 (PIOC), 0x400E1494 (PIOD), 0x400E1694 (PIOE) Access: Write-only This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register.

• P0–P31: Pull-Down Enable 0: No effect. 1: Enables the pull-down resistor on the I/O line. 31 302 92 82 72 62 52 4 P31P 30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543 210 P7 P6 P5 P4 P3 P2 P1 P0

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 396

32.6.32 PIO Pad Pull-Down Status Register

Name: PIO_PPDSR Address: 0x400E0E98 (PIOA), 0x400E1098 (PIOB), 0x400E1298 (PIOC), 0x400E1498 (PIOD), 0x400E1698 (PIOE) Access: Read-only

• P0–P31: Pull-Down Status 0: Pull-down resistor is enabled on the I/O line. 1: Pull-down resistor is disabled on the I/O line. 31 302 92 82 72 62 52 4 P31P 30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543 210 P7 P6 P5 P4 P3 P2 P1 P0

397SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

32.6.33 PIO Output Write Enable Register

Name: PIO_OWER Address: 0x400E0EA0 (PIOA), 0x400E10A0 (PIOB), 0x400E12A0 (PIOC), 0x400E14A0 (PIOD), 0x400E16A0 (PIOE) Access: Write-only This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register.

• P0–P31: Output Write Enable 0: No effect. 1: Enables writing PIO_ODSR for the I/O line. 31 302 92 82 72 62 52 4 P31P 30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543 210 P7 P6 P5 P4 P3 P2 P1 P0

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 398

32.6.34 PIO Output Write Disable Register

Name: PIO_OWDR Address: 0x400E0EA4 (PIOA), 0x400E10A4 (PIOB), 0x400E12A4 (PIOC), 0x400E14A4 (PIOD), 0x400E16A4 (PIOE) Access: Write-only This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register.

• P0–P31: Output Write Disable 0: No effect. 1: Disables writing PIO_ODSR for the I/O line. 31 302 92 82 72 62 52 4 P31P 30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543 210 P7 P6 P5 P4 P3 P2 P1 P0

399SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

32.6.35 PIO Output Write Status Register

Name: PIO_OWSR Address: 0x400E0EA8 (PIOA), 0x400E10A8 (PIOB), 0x400E12A8 (PIOC), 0x400E14A8 (PIOD), 0x400E16A8 (PIOE) Access: Read-only

• P0–P31: Output Write Status 0: Writing PIO_ODSR does not affect the I/O line. 1: Writing PIO_ODSR affects the I/O line. 31 302 92 82 72 62 52 4 P31P 30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543 210 P7 P6 P5 P4 P3 P2 P1 P0

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 400

32.6.36 PIO Additional Interrupt Modes Enable Register

Name: PIO_AIMER Address: 0x400E0EB0 (PIOA), 0x400E10B0 (PIOB), 0x400E12B0 (PIOC), 0x400E14B0 (PIOD), 0x400E16B0 (PIOE) Access: Write-only

• P0–P31: Additional Interrupt Modes Enable 0: No effect. 1: The interrupt source is the event described in PIO_ELSR and PIO_FRLHSR. 31 302 92 82 72 62 52 4 P31P 30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543 210 P7 P6 P5 P4 P3 P2 P1 P0

401SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

32.6.37 PIO Additional Inte rrupt Modes Disable Register

Name: PIO_AIMDR Address: 0x400E0EB4 (PIOA), 0x400E10B4 (PIOB), 0x400E12B4 (PIOC), 0x400E14B4 (PIOD), 0x400E16B4 (PIOE) Access: Write-only

• P0–P31: Additional Interrupt Modes Disable 0: No effect. 1: The interrupt mode is set to the default interrupt mode (both-edge detection). 31 302 92 82 72 62 52 4 P31P 30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543 210 P7 P6 P5 P4 P3 P2 P1 P0

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 402

32.6.38 PIO Additional Interrupt Modes Mask Register

Name: PIO_AIMMR Address: 0x400E0EB8 (PIOA), 0x400E10B8 (PIOB), 0x400E12B8 (PIOC), 0x400E14B8 (PIOD), 0x400E16B8 (PIOE) Access: Read-only

• P0–P31: IO Line Index Selects the IO event type triggering an interrupt. 0: The interrupt source is a both-edge detection event. 1: The interrupt source is described by the registers PIO_ELSR and PIO_FRLHSR. 31 302 92 82 72 62 52 4 P31P 30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543 210 P7 P6 P5 P4 P3 P2 P1 P0

403SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

32.6.39 PIO Edge Select Register

Name: PIO_ESR Address: 0x400E0EC0 (PIOA), 0x400E10C0 (PIOB), 0x400E12C0 (PIOC), 0x400E14C0 (PIOD), 0x400E16C0 (PIOE) Access: Write-only

• P0–P31: Edge Interrupt Selection 0: No effect. 1: The interrupt source is an edge-detection event. 31 302 92 82 72 62 52 4 P31P 30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543 210 P7 P6 P5 P4 P3 P2 P1 P0

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 404

32.6.40 PIO Level Select Register

Name: PIO_LSR Address: 0x400E0EC4 (PIOA), 0x400E10C4 (PIOB), 0x400E12C4 (PIOC), 0x400E14C4 (PIOD), 0x400E16C4 (PIOE) Access: Write-only

• P0–P31: Level Inte rrupt Selection 0: No effect. 1: The interrupt source is a level-detection event. 31 302 92 82 72 62 52 4 P31P 30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543 210 P7 P6 P5 P4 P3 P2 P1 P0

405SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

32.6.41 PIO Edge/Level Status Register

Name: PIO_ELSR Address: 0x400E0EC8 (PIOA), 0x400E10C8 (PIOB), 0x400E12C8 (PIOC), 0x400E14C8 (PIOD), 0x400E16C8 (PIOE) Access: Read-only

• P0–P31: Edge/Level Interrupt Source Selection 0: The interrupt source is an edge-detection event. 1: The interrupt source is a level-detection event. 31 302 92 82 72 62 52 4 P31P 30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543 210 P7 P6 P5 P4 P3 P2 P1 P0

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 406

32.6.42 PIO Falling Edge/Low-Level Select Register

Name: PIO_FELLSR Address: 0x400E0ED0 (PIOA), 0x400E10D0 (PIOB), 0x400E12D0 (PIOC), 0x400E14D0 (PIOD), 0x400E16D0 (PIOE) Access: Write-only

• P0–P31: Falling Edge/Low-Level Interrupt Selection 0: No effect. 1: The interrupt source is set to a falling edge detection or low-level detection event, depending on PIO_ELSR. 31 302 92 82 72 62 52 4 P31P 30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543 210 P7 P6 P5 P4 P3 P2 P1 P0

407SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

32.6.43 PIO Rising Edge/Hi gh-Level Select Register

Name: PIO_REHLSR Address: 0x400E0ED4 (PIOA), 0x400E10D4 (PIOB), 0x400E12D4 (PIOC), 0x400E14D4 (PIOD), 0x400E16D4 (PIOE) Access: Write-only

• P0–P31: Rising Edge/High-Level Interrupt Selection 0: No effect. 1: The interrupt source is set to a rising edge detection or high-level detection event, depending on PIO_ELSR. 31 302 92 82 72 62 52 4 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543 210 P7 P6 P5 P4 P3 P2 P1 P0

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 408

32.6.44 PIO Fall/Rise - Low/High Status Register

Name: PIO_FRLHSR Address: 0x400E0ED8 (PIOA), 0x400E10D8 (PIOB), 0x400E12D8 (PIOC), 0x400E14D8 (PIOD), 0x400E16D8 (PIOE) Access: Read-only

• P0–P31: Edge/Level Interrupt Source Selection 0: The interrupt source is a falling edge detection (if PIO_ELSR = 0) or low-level detection event (if PIO_ELSR = 1). 1: The interrupt source is a rising edge detection (if PIO_ELSR = 0) or high-level detection event (if PIO_ELSR = 1). 31 302 92 82 72 62 52 4 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543 210 P7 P6 P5 P4 P3 P2 P1 P0

409SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

32.6.45 PIO Lock Status Register

Name: PIO_LOCKSR Address: 0x400E0EE0 (PIOA), 0x400E10E0 (PIOB), 0x400E12E0 (PIOC), 0x400E14E0 (PIOD), 0x400E16E0 (PIOE) Access: Read-only

• P0–P31: Lock Status 0: The I/O line is not locked. 1: The I/O line is locked. 31 302 92 82 72 62 52 4 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543 210 P7 P6 P5 P4 P3 P2 P1 P0

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 410

32.6.46 PIO Write Protection Mode Register

Name: PIO_WPMR Address: 0x400E0EE4 (PIOA), 0x400E10E4 (PIOB), 0x400E12E4 (PIOC), 0x400E14E4 (PIOD), 0x400E16E4 (PIOE) Access: Read/Write

• WPEN: Write Protection Enable 0: Disables the write protection if WPKEY corresponds to 0x50494F (“PIO” in ASCII). 1: Enables the write protection if WPKEY corresponds to 0x50494F (“PIO” in ASCII). See Section 32.5.16 “Register Write Protection” for the list of registers that can be protected.
• WPKEY: Write Protection Key 31 30 29 28 27 26 25 24 WPKEY 23 22 21 20 19 18 17 16 WPKEY 15 14 13 12 11 10 9 8 WPKEY 76543210 Value Name Description 0x50494F PASSWD Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as

411SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

32.6.47 PIO Write Protection Status Register

Name: PIO_WPSR Address: 0x400E0EE8 (PIOA), 0x400E10E8 (PIOB), 0x400E12E8 (PIOC), 0x400E14E8 (PIOD), 0x400E16E8 (PIOE) Access: Read-only

• WPVS: Write Protection Violation Status 0: No write protection violation has occurred since the last read of the PIO_WPSR. 1: A write protection violation has occurred since the last read of the PIO_WPSR. If this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field WPVSRC.
• WPVSRC: Write Protection Violation Source When WPVS = 1, WPVSRC indicates the register address offset at which a write access has been attempted. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WPVSRC 15 14 13 12 11 10 9 8 WPVSRC 76543210

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 412

32.6.48 PIO Schmitt Trigger Register

Name: PIO_SCHMITT Address: 0x400E0F00 (PIOA), 0x400E1100 (PIOB), 0x400E1300 (PIOC), 0x400E1500 (PIOD), 0x400E1700 (PIOE) Access: Read/Write

• SCHMITTx [x=0..31]: Schmitt Trigger Control 0: Schmitt trigger is enabled. 1: Schmitt trigger is disabled. 31 30 29 28 27 26 25 24 SCHMITT31 SCHMITT30 SCHMITT29 SCHMITT28 SCHMITT27 SCHMITT26 SCHMITT25 SCHMITT24 23 22 21 20 19 18 17 16 SCHMITT23 SCHMITT22 SCHMIT T21 SCHMITT20 SCHMITT19 SCHMITT18 SCHMITT17 SCHMITT16 15 14 13 12 11 10 9 8 SCHMITT15 SCHMITT14 SCHMITT13 SCHMITT12 SCH MITT11 SCHMITT10 SCHMITT9 SCHMITT8 76543210 SCHMITT7 SCHMITT6 SCHMITT5 SCHMITT4 SCHMITT3 SCHMITT2 SCHMITT1 SCHMITT0

413SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

32.6.49 PIO I/O Drive Register

Name: PIO_DRIVER Address: 0x400E0F18 (PIOA), 0x400E1118 (PIOB), 0x400E1318 (PIOC), 0x400E1518 (PIOD), 0x400E1718 (PIOE) Access: Read/Write

• LINEx [x=0..31]: Dr ive of PIO Line x 31 30 29 28 27 26 25 24 LINE31L I N E 30 LINE29 LINE28 LINE27 LINE26 LINE25 LINE24 23 22 21 20 19 18 17 16 LINE23 LINE22 LINE21 LINE20 LINE 19 LINE18 LINE17 LINE16 15 14 13 12 11 10 9 8 LINE15 LINE14 LINE13 LINE12 LINE11 LINE10 LINE9 LINE8 76543210 LINE7 LINE6 LINE5 LINE4 LINE 3 LINE2 LINE1 LINE0 Value Name Description

0 LOW_DRIVE Lowest drive

1 HIGH_DRIVE Highest drive

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 414

32.6.50 PIO Parallel Capture Mode Register

Name: PIO_PCMR Address: 0x400E0F50 (PIOA), 0x400E1150 (PIOB), 0x400E1350 (PIOC), 0x400E1550 (PIOD), 0x400E1750 (PIOE) Access: Read/Write This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register.

• PCEN: Parallel Capture Mode Enable 0: The parallel capture mode is disabled. 1: The parallel capture mode is enabled.
• DSIZE: Parallel Capture Mode Data Size
• ALWYS: Parallel Capture Mode Always Sampling 0: The parallel capture mode samples the data when both data enables are active. 1: The parallel capture mode samples the data whatever the data enables are.
• HALFS: Parallel Capture Mode Half Sampling Independently from the ALWYS bit: 0: The parallel capture mode samples all the data. 1: The parallel capture mode samples the data only every other time.
• FRSTS: Parallel Capture Mode First Sample This bit is useful only if the HALFS bit is set to 1. If data are numbered in the order that they are received with an index from 0 to n: 0: Only data with an even index are sampled. 1: Only data with an odd index are sampled. 31 302 92 82 72 62 52 4 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 –––– F RSTS H ALFS A LWYS – 76543 210 Value Name Description

0 BYTE The reception data in the PIO_PCRHR is a byte (8-bit)

1 HALF-WORD The reception data in the PIO_PCRHR is a half-word (16-bit)

2 WORD The reception data in the PIO_PCRHR is a word (32-bit)

3– R eserved

415SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

32.6.51 PIO Parallel Capture Interrupt Enable Register

Name: PIO_PCIER Address: 0x400E0F54 (PIOA), 0x400E1154 (PIOB), 0x400E1354 (PIOC), 0x400E1554 (PIOD), 0x400E1754 (PIOE) Access: Write-only The following configuration values are valid for all listed bit names of this register: 0: No effect 1: Enables the corresponding interrupt

• DRDY: Parallel Capture Mode Data Ready Interrupt Enable
• OVRE: Parallel Capture Mode Overrun Error Interrupt Enable
• ENDRX: End of Reception Transfer Interrupt Enable
• RXBUFF: Reception Buffer Full Interrupt Enable 31 302 92 82 72 62 52 4 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543 210 –––– R XBUFF E NDRX OVRE DRDY

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 416

32.6.52 PIO Parallel Capture Interrupt Disable Register

Name: PIO_PCIDR Address: 0x400E0F58 (PIOA), 0x400E1158 (PIOB), 0x400E1358 (PIOC), 0x400E1558 (PIOD), 0x400E1758 (PIOE) Access: Write-only The following configuration values are valid for all listed bit names of this register: 0: No effect 1: Disables the corresponding interrupt

• DRDY: Parallel Capture Mode Data Ready Interrupt Disable
• OVRE: Parallel Capture Mode Overrun Error Interrupt Disable
• ENDRX: End of Reception Transfer Interrupt Disable
• RXBUFF: Reception Buffer Full Interrupt Disable 31 302 92 82 72 62 52 4 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543 210 –––– R XBUFF E NDRX OVRE DRDY

417SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

32.6.53 PIO Parallel Capture Interrupt Mask Register

Name: PIO_PCIMR Address: 0x400E0F5C (PIOA), 0x400E115C (PIOB), 0x400E135C (PIOC), 0x400E155C (PIOD), 0x400E175C (PIOE) Access: Read-only The following configuration values are valid for all listed bit names of this register: 0: Corresponding interrupt is not enabled. 1: Corresponding interrupt is enabled.

• DRDY: Parallel Capture Mode Data Ready Interrupt Mask
• OVRE: Parallel Capture Mode Overrun Error Interrupt Mask
• ENDRX: End of Reception Transfer Interrupt Mask
• RXBUFF: Reception Buffer Full Interrupt Mask 31 302 92 82 72 62 52 4 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543 210 –––– R XBUFF E NDRX OVRE DRDY

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 418

32.6.54 PIO Parallel Capture Interrupt Status Register

Name: PIO_PCISR Address: 0x400E0F60 (PIOA), 0x400E1160 (PIOB), 0x400E1360 (PIOC), 0x400E1560 (PIOD), 0x400E1760 (PIOE) Access: Read-only

• DRDY: Parallel Capture Mode Data Ready 0: No new data is ready to be read since the last read of PIO_PCRHR. 1: A new data is ready to be read since the last read of PIO_PCRHR. The DRDY flag is automatically reset when PIO_PCRHR is read or when the parallel capture mode is disabled.
• OVRE: Parallel Capture Mode Overrun Error 0: No overrun error occurred since the last read of this register. 1: At least one overrun error occurred since the last read of this register. The OVRE flag is automatically reset when this register is read or when the parallel capture mode is disabled. 31 302 92 82 72 62 52 4 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543 210

419SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

32.6.55 PIO Parallel Capture Reception Holding Register

Name: PIO_PCRHR Address: 0x400E0F64 (PIOA), 0x400E1164 (PIOB), 0x400E1364 (PIOC), 0x400E1564 (PIOD), 0x400E1764 (PIOE) Access: Read-only

• RDATA: Parallel Capture Mode Reception Data If DSIZE = 0 in PIO_PCMR, only the 8 LSBs of RDATA are useful. If DSIZE = 1 in PIO_PCMR, only the 16 LSBs of RDATA are useful. 31 302 92 82 72 62 52 4 RDATA 23 22 21 20 19 18 17 16 RDATA 15 14 13 12 11 10 9 8 RDATA 76543 210 RDATA

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 420 33. External Bus Interface (EBI)

33.1 Description

The External Bus Interface (EBI) is designed to ensure the successful data transf er between several external devices and the embedded Memory Controller of an ARM-based device. The Static Memory and SDRAM Controllers are all featured external Memory Controllers on the EBI. These external Memory Controllers are capable of handling se veral types of external memory and peripheral devices, such as SRAM, PROM, EPROM , EEPROM, Flash and SDR-SDRAM. The EBI operates with 1.8V or 3.3V Power Supply (VDDIO). The EBI also supports the NAND Flash protocols via integrated circuitry that greatly reduces the requirements for external components. Furthermore, the EBI handles data tran sfers with up to six exter nal devices, each assigned to six address spaces defined by the embedded Memory Controller. Data transfers are performed through a 16-bit or 32-bit data bus, an address bus of up to 24 bits, up to four chip select lines (NCS[3:0]) and several control pins that are generally multiplexed between the different external Memory Controllers.

33.2 Embedded Characteristics

 Integrates two External Memory Controllers ̶ Static Memory Controller ̶ SDR-SDRAM Controller  Integrates NAND Flash Logic  Up to 24-bit Address Bus (up to 16 Mbytes linear per chip select)  Up to four Chip Selects, Configurable Assignment ̶ Static Memory Controller on NCS0, NCS1, NCS2, NCS3 ̶ SDR-SDRAM Controller (SDCS) or Static Memory Controller on NCS1 ̶ NAND Flash support on NCS0, NCS1, NSCS2 and NCS3

421SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

33.3 EBI Block Diagram

Figure 33-1. Organization of the External Bus Interface External Bus Interface D[15:0] A[15:2], A19 PIOMUX Logic User Interface Chip Select Assignor Static Memory Controller SDR-SDRAM Controller Bus Matrix APB AHB Address Decoders A16/BA0 A0/NBS0 A17/BA1 NCS0 NRD NCS1/SDCS NWR0/NWE NWR1/NBS1 SDCK, SDCKE DQM[1:0] RAS, CAS SDWE, SDA10 A[23:20] NCS2 NWAIT NANDOE NANDWE NAND Flash Logic A21/NANDALE A22/NANDCLE NCS3/NANDCS A18

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 422

33.4 I/O Lines Description

The connection of some signals through the MUX logic is not direct and depends on the Memory Controller in use at the moment. Table 33-2 details the connections between the two Memory Controllers and the EBI pins. Table 33-1. EBI I/O Lines Description Name Function Type Active Level EBI D0–D15 Data Bus I/O A0–A23 Address Bus Output NWAIT External Wait Signal Input Low SMC NCS0–EBI_NCS3 Chip Select Lines Output Low NWR0–NWR1 Write Signals Output Low NRD Read Signal Output Low NWE Write Enable Output Low NBS0–NBS1 Byte Mask Signals Output Low EBI for NAND Flash Support NANDCS NAND Flash Chip Select Line Output Low NANDOE NAND Flash Output Enable Output Low NANDWE NAND Flash Write Enable Output Low SDRAM Controller SDCK SDR-SDRAM Clock Output SDCKE SDR-SDRAM Clock Enable Output High SDCS SDR-SDRAM Controller Chip Select Line Output Low BA0–1 Bank Select Output SDWE SDR-SDRAM Write Enable Output Low RAS - CAS Row and Column Signal Output Low SDA10 SDRAM Address 10 Line Output Table 33-2. EBI Pins and Memory Controllers I/O Lines Connections EBIx Pins SDRAM I/O Lines SMC I/O Lines NWR1/NBS1 NBS1 NWR1 A0/NBS0 Not Supported SMC_A0 A1 Not Supported SMC_A1 A[11:2] SDRAMC_A[9:0] SMC_A[11:2] SDA10 SDRAMC_A10 Not Supported A12 Not Supported SMC_A12 A[15:13] SDRAMC_A[ 13:11] SMC_A[15:13] A[25:16] Not Supported SMC_A[25:16]

423SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

33.5 Application Example

33.5.1 Hardware Interface

Table 33-3 details the connections to be applied between the EBI pins and the external devices for each Memory Controller. Notes: 1. NWR1 enables upper byte writes. NWR0 enables lower byte writes. Table 33-3. EBI Pins and Extern al Static Device Connections Signals: EBI_ Pins of the Interfaced Device 8-bit Static Device 2 x 8-bit Static Devices 16-bit Static Device Controller SMC D0–D7 D0–D7 D0–D7 D0–D7 D8–D15 – D8–D15 D8–D15 A0/NBS0 A0 – NLB A1 A1 A0 A0 N C S 0 C SC SC S NCS1/DDRSDCS CS CS CS N C S 2 C SC SC S NCS3/NANDCS CS CS CS NRD OE OE OE NWR0/NWE WE WE (1) WE NWR1/NBS1 – WE (1) NUB

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 424 Table 33-4. EBI Pins and External Device Connections Signals: EBI_ Power supply Pins of the Interfaced Device SDR/LPSDR NAND Flash Controller SDRAMC NFC D0–D15 VDDIO D0–D15 D0–D15 A0/NBS0 VDDIO DQM0 – A1 VDDIO – – A2–A10 VDDIO A[0:8] – A11 VDDIO A9 – SDA10 VDDIO A10 – A12 VDDIO – – A13–A14 VDDIO A[11:12] – A15 VDDIO A13 – A16/BA0 VDDIO BA0 – A17/BA1 VDDIO BA1 – A18 VDDIO – – A19 VDDIO – – A20 VDDIO – – A21/NANDALE VDDIO – ALE A22/NANDCLE VDDIO – CLE A23 VDDIO – – NCS0 VDDIO – – NCS1/SDCS VDDIO SDCS – NCS2 VDDIO – – NCS3/NANDCS VDDIO – CE NANDOE VDDIO – OE NANDWE VDDIO – WE NRD VDDIO – – NWR0/NWE VDDIO – – NWR1/NBS1 VDDIO DQM1 – SDCK VDDIO CK – SDCKE VDDIO CKE – RAS VDDIO RAS – CAS VDDIO CAS – SDWE VDDIO WE – Pxx VDDIO – CE Pxx VDDIO – RDY

425SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

33.5.2 Product Dependencies

33.5.2.1 I/O Lines

The pins used for interfacing the External Bus Interface may be multiplexed with the PIO lines. The programmer must first program the PIO controller to assign the External Bus Interface pins to their peripheral function. If I/O lines of the External Bus Interface are not used by the application, they can be used for other purposes by the PIO Controller.

33.5.3 Functional Description

The EBI transfers data between the internal AHB Bus (handled by the Bus Matrix) and the external memories or peripheral devices. It controls the waveforms and the pa rameters of the external address, data and control buses and is composed of the following elements:  Static Memory Controller (SMC)  SDR-SDRAM Controller (SDRC)  A chip select assignment feature that assigns an AHB address space to the external devices  A multiplex controller circuit that shares the pins between the different Memory Controllers  Programmable NAND Flash support logic

33.5.3.1 Bus Multiplexing

The EBI offers a complete set of control signals that shar e the 16-bit data lines, the address lines of up to 24 bits and the control signals through a multiplex logic operating in function of the memory area requests. Multiplexing is specifically organized in order to guarantee the maintenance of the address and output control lines at a stable state while no external access is being performed. Multiplexing is also designed to respect the data float times defined in the Memory Controllers. Furthermo re, refresh cycles of the SDR-SDRAM are executed independently by the SDR Controller without delaying the other external Memory Controller accesses.

33.5.3.2 Static Memory Controller

For information on the Static Memory Controller, refer to Section 34. “Static Memory Controller (SMC)”

33.5.3.3 SDRAM Controller

For information on the SDR Controller, refer to Section 28. “SDRAM Controller (SDRAMC)”.

33.5.3.4 NAND Flash Support

External Bus Interfaces integrate circuitry that interfaces to NAND Flash devices. To ensure that the processor preserves transaction order and thus the correct NAND Flash behavior, the NAND Flash address space is to be declared in the Memory Protection Unit (MPU) as "Device" or "Strongly-ordered" memory. Refer to the ARM Cortex-M7 Technical Reference Manual (ARM DDI 0489) available on www.arm.com. External Bus Interface The NAND Flash Chip Select (NANDCS) is driven by the Static Memory Controller on the NCS0, NCS1, NCS2 or NCS3 address space depending on value of SMC_SMCSx bits. For example, programming the SMC_NFC3 field in the CCFG_SMCNFCS Register in the Chip Configurat ion User Interface to the appropriate value enables the NAND Flash logic. For details on this register, refer to Section 18. “Bus Matrix (MATRIX)”. Access to an external NAND Flash device is then made by accessing the addre ss space reserved to NCS3 (i.e., between 0x6300 0000 and 0x6FFF FFFF). The NAND Flash logic drives the read and write command signals of the SMC on the NANDOE and NANDWE signals when the required SMC_NFCSx signal is active . NANDOE and NANDWE are invalidated as soon as the transfer address fails to lie in the selected NCSx address space. For det ails on these waveforms, refer to Section 34. “Static Memory Controller (SMC)”.

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 426 NAND Flash Signals The address latch enable and command latch enable signals on the NAND Flash device are driven by address bits A22 and A21 of the EBI address bus. The command, address or data words on the data bus of the NAND Flash device are distinguished by using their address within the NCSx address space. The chip enable (CE) signal of the device and the ready/busy (R/B) signals are connected to PIO lines. The CE signal then remains asserted even when NCSx is not selected, preventing the device from returning to standby mode.

33.5.4 Implementation Examples

The following hardware configurations are given for illustration only. The user should refer to the memory manufacturer web site to check current device availability. 33.5.4.1 16-bit SDRAM on NCS1 Hardware Configuration Software Configuration The following configuration has to be performed:  Enable the SDRAM support by setting the bit SDRAMEN field in the CCFG_SMCNFCS Register in the Bus Matrix.  Initialize the SDRAM Controller depending on the SDRAM device and system bus frequency. The Data Bus Width is to be programmed to 16 bits. The SDRAM initialization sequence is described in Section 28.5.1 “SDRAM Device Initialization”.

427SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 34. Static Memory Controller (SMC)

34.1 Description

The External Bus Interface (EBI) is designed to ensure the successful data transf er between several external devices and the ARM-based microcontroller. The Static Memory Controller (SMC) is part of the EBI. The SMC handles several types of external memory and peripheral devices, such as SRAM, PSRAM, PROM, EPROM, EEPROM, LCD Module, NOR Flash and NAND Flash. The SMC generates the signals that cont rol the access to the external memory devices or peripheral devices. It has 4 chip selects, a 24-bit address bus, and a configurab le 8 or 16-bit data bus. Separate read and write control signals allow for direct memory and peripheral interfacing. Read and write signal waveforms are fully adjustable. The SMC can manage wait requests from external devices to extend the current access. The SMC is provided with an automatic Slow clock mode. In Slow clock mode, it switches from user-programmed waveforms to slow-rate specific waveforms on read and write signals. The SMC supports asynchronous burst read in Page mode access for page sizes up to 32 bytes. The external data bus can be scrambled/unscrambled by means of user keys.

34.2 Embedded Characteristics

 Four Chip Selects Available  16-Mbyte Address Space per Chip Select  8-bit or 16-bit Data Bus  Zero Wait State Scrambling/Unscrambling Function with User Key  Word, Halfword, Byte Transfers  Byte Write or Byte Select Lines  Programmable Setup, Pulse And Hold Time for Read Signals per Chip Select  Programmable Setup, Pulse And Hold Time for Write Signals per Chip Select  Programmable Data Float Time per Chip Select  External Wait Request  Automatic Switch to Slow Clock Mode  Asynchronous Read in Page Mode Supported: Page Size Ranges from 4 to 32 Bytes  Register Write Protection

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 428

34.3 I/O Lines Description

34.4 Multiplexed Signals

Table 34-1. I/O Line Description Name Description Type Active Level NCS[3:0] Static Memory Controller Chip Select Lines Output Low NRD Read Signal Output Low NWR0/NWE Write 0/Write Enable Signal Output Low NWR1/NBS1 Write 1/Byte 1 Select Signal Output Low A0/NBS0 Address Bit 0/Byte 0 Select Signal Output Low A[23:1] Address Bus Output – D[15:0] Data Bus I/O – NWAIT External Wait Signal Input Low NANDCS NAND Flash Chip Select Line Output Low NANDOE NAND Flash Output Enable Output Low NANDWE NAND Flash Write Enable Output Low NANDALE NAND Flash Address Latch Enable Output – NANDCLE NAND Flash Command Latch Enable Output – Table 34-2. Static Memory Contro ller (SMC) Multiplexed Signals Multiplexed Signals Related Function NWR0 NWE Byte-write or Byte-select access. A0 NBS0 8-bit or 16-bit data bus. See Section 34.7.1 ”D ata Bus Width” Select Access” A22 NANDCLE NAND Flash Command Latch Enable A21 NANDALE NAND Flash Address Latch Enable

429SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

34.5 Product Dependencies

34.5.1 I/O Lines

The pins used for interfacing the SMC are multiplexed wit h the PIO lines. The programmer must first program the PIO controller to assign the SMC pins to their peripheral function. If I/O lines of the SMC are not used by the application, they can be used for other purposes by the PIO Controller. Table 34-3. I/O Lines Instance Signal I/O Line Peripheral SMC A0/NBS0 PC18 A SMC A1 PC19 A SMC A2 PC20 A SMC A3 PC21 A SMC A4 PC22 A SMC A5 PC23 A SMC A6 PC24 A SMC A7 PC25 A SMC A8 PC26 A SMC A9 PC27 A SMC A10 PC28 A SMC A11 PC29 A SMC A12 PC30 A SMC A13 PC31 A SMC A14 PA18 C SMC A15 PA19 C SMC A16/BA0 PA20 C SMC A17/BA1 PA0 C SMC A18 PA1 C SMC A19 PA23 C SMC A20 PA24 C SMC A21/NANDALE PC16 A SMC A22/NANDCLE PC17 A SMC A23 PA25 C SMC CAS PD17 C SMC D0 PC0 A SMC D1 PC1 A SMC D2 PC2 A SMC D3 PC3 A SMC D4 PC4 A SMC D5 PC5 A

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 430

34.5.2 Power Management

The SMC is clocked through the Power Management Contro ller (PMC), thus the progra mmer must first configure the PMC to enable the SMC clock. SMC D6 PC6 A SMC D7 PC7 A SMC D8 PE0 A SMC D9 PE1 A SMC D10 PE2 A SMC D11 PE3 A SMC D12 PE4 A SMC D13 PE5 A SMC D14 PA15 A SMC D15 PA16 A SMC NANDOE PC9 A SMC NANDWE PC10 A SMC NCS0 PC14 A SMC NCS1/SDCS PC15 A SMC NCS1/SDCS PD18 A SMC NCS2 PA22 C SMC NCS3 PC12 A SMC NCS3 PD19 A SMC NRD PC11 A SMC NWAIT PC13 A SMC NWR0/NWE PC8 A SMC NWR1/NBS1 PD15 C SMC RAS PD16 C SMC SDA10 PC13 C SMC SDA10 PD13 C SMC SDCK PD23 C SMC SDCKE PD14 C SMC SDWE PD29 C Table 34-3. I/O Lines

431SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

34.6 External Memory Mapping

The SMC provides up to 24 address lines, A[23:0]. This allows each chip select line to address up to 16 Mbytes of memory. If the physical memory device connecte d on one chip select is smaller than 16 Mbytes, it wraps around and appears to be repeated within this space. The SMC correctly handles any valid access to the memory device within the page (see Figure 34-1). Figure 34-1. Memory Connections for Four External Devices

34.7 Connection to External Devices

34.7.1 Data Bus Width

A data bus width of 8 or 16 bits can be selected for each chip select. This option is controlled by the bit DBW in the Mode register (SMC_MODE) for the corresponding chip select. Figure 34-2 shows how to connect a 512-Kbyte × 8-bit memory on NCS2. Figure 34-3 shows how to connect a 512-Kbyte × 16-bit memory on NCS2. Figure 34-2. Memory Connection for an 8-bit Data Bus NRD NWE A[23:0] D[15:0] 16 or 8 Memory Enable Memory Enable Memory Enable Memory Enable Output Enable Write Enable A[23:0] D[15:0] or D[7:0] NCS3 NCS0 NCS1 NCS2 NCS[0] - NCS[3] SMC SMC NWE NRD NCS[2] Write Enable Output Enable Memory Enable D[7:0] D[7:0] A[18:2]A[18:2] A0 A0

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 432 Figure 34-3. Memory Connection for a 16-bit Data Bus

34.7.2 Byte Write or Byte Select Access

Each chip select with a 16-bit data bus can operate with one of two different types of write access: byte write or byte select. This is controlled by the BAT field of the SMC_MODE register for the corresponding chip select.

34.7.2.1 Byte Write Access

Byte write access is used to connect 2 × 8-bit devices as a 16-bit memory, and supports one write signal per byte of the data bus and a single read signal. Note that the SMC does not allow boot in Byte write access mode. For 16-bit devices, the SMC provides NWR0 and NWR1 write signals for respectively Byte0 (lower byte) and Byte1 (upper byte) of a 16-bit bus. One single read signal (NRD) is provided.

34.7.2.2 Byte Select Access

Byte select access is used to connect one 16-bit device. In this mode, read/write operations can be enabled/disabled at byte level. One byte-select line per byte of the data bus is provided. One NRD and one NWE signal control read and write. For 16-bit devices, the SMC provides NBS0 and NBS1 se lection signals for respectively Byte0 (lower byte) and Byte1 (upper byte) of a 16-bit bus. SMC NBS0 NWE NRD NCS[2] Low Byte Enable Write Enable Output Enable Memory Enable NBS1 High Byte Enable D[15:0] D[15:0] A[19:2] A[18:1] A[0]A1

433SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 Figure 34-4. Connection of 2 × 8-bit Devices on a 16-bit Bus: Byte Write Option

34.7.2.3 Signal Multiplexing

Depending on the byte access type (BAT), only the byte wr ite signals or the byte select signals are used. To save IOs at the external bus interface, control signals at the SMC interface are multiplexed. Table 34-4 shows signal multiplexing depending on the data bus width and the byte access type. For 16-bit devices, bit A0 of address is unused. When the Byte Select option is selected, NWR1 is unused. When the Byte Write option is selected, NBS0 is unused. SMC A1 NWR0 NRD NCS[3] Write Enable Read Enable Memory Enable NWR1 Write Enable Read Enable Memory Enable D[7:0] D[7:0] D[15:8] D[15:8] A[24:2] A[23:1] A[23:1] A[0] A[0] Table 34-4. SMC Multiplexed Signal Translation Device Type Signal Name 16-bit Bus 8-bit Bus 1 x 16-bit 2 x 8-bit 1 x 8-bit Byte Access Type (BAT) Byte Select Byte Write – NBS0_A0 NBS0 – A0 NWE_NWR0 NWE NWR0 NWE NBS1_NWR1 NBS1 NWR1 – A1 A1 A1 A1

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 434

34.7.3 NAND Flash Support

The SMC integrates circuitry that interfaces to NAND Flash devices. The NAND Flash logic is driven by the SMC. Config uration is done via the SMC_NFCSx field in the CCFG_SMCNFCS register in the Bus Matrix. For details on this register, refer to Section 18. ”Bus Matrix (MATRIX)” of this datasheet. The external NAND Flash device is accessed via the address space reserved for the chip select programmed. The user can connect up to four NAND Flash devices with separate chip selects. The NAND Flash logic drives the read and write command signals of the SMC on the NANDOE and NANDWE signals when the NCSx programmed is active. NANDOE and NANDWE are disabled as soon as the transfer address fails to lie in the NCSx programmed address space. Figure 34-5. NAND Flash Signal Multiplexing on SMC Pins Notes: 1. NCSx is active when CCFG_SMCNFCS.SMC_NFCSx=1. 2. When the NAND Flash logic is activated, (SMC_NFCSx =1), the NWE pin can be used only in Peripheral mode (NWE function). If the NWE function is not used for other external memories (SRAM, LCD), it must be configured in one of the following modes: – PIO Input with pull-up enabled (default state after reset) – PIO Output set at level 1 The address latch enable and command latch enable signals on the NAND Flash device are driven by address bits A22 and A21of the address bus. Any bit of the addres s bus can also be used for this purpose. The command, address or data words on the data bus of the NAND Flash device use their own addresses within the NCSx address space (configured in the register CCFG_SMCNFCS in the Bus Matrixe). The chip enable (CE) signal of the device and the ready/busy (R/B) signals are connect ed to PIO lines. The CE si gnal then remains asserted even when NAND Flash chip select is not selected, preventi ng the device from returning to Standby mode. The NANDCS output signal should be used in accordance with the external NAND Flash device type. Two types of CE behavior exist depending on the NAND Flash device:  Standard NAND Flash devices require that the CE pin remains asserted low continuously during the read busy period to prevent the device from returning to Standby mode. Since the SMC asserts the NCSx signal high, it is necessary to connect the CE pin of the NAND Flash device to a GPIO line, in order to hold it low during the busy period preceding data read out.  This restriction has been removed for “CE don’t care” NAND Flash devices. The NCSx signal can be directly connected to the CE pin of the NAND Flash device. Figure 34-6 illustrates both topologies: Standard and “CE don’t care” NAND Flash. SMC NRD NWE NANDOE NANDWE NAND Flash Logic NCSx NANDWE NANDOE

435SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 Figure 34-6. Standard and “CE don’t care” NAND Flash Application Examples

34.8 Application Example

34.8.1 Implementation Examples

Hardware configurations are given for illustration only. The user should refer to the manufacturer web site to check for memory device availability. For hardware implementation examples, refer to the eval uation kit schematics for this microcontroller, which show examples of a connection to an LCD module and NAND Flash. D[7:0] ALE NANDWE NOE NWE A[22:21] CLE AD[7:0] PIO R/B SMC CE NAND Flash PIO NCSx Not Connected NANDOE D[7:0] ALE NANDWE NOE NWE A[22:21] CLE AD[7:0] PIO R/B SMC CE “CE don’t care” NAND Flash NCSx NANDOE

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 436 34.8.1.1 8-bit NAND Flash Hardware Configuration Software Configuration Perform the following configuration: 1. Select the chip select used to drive the NAND Flash by setting the bit CCFG_SMCNFCS.SMC_NFCSx. 2. Reserve A21 / A22 for ALE / CLE functions. Address and Command Latches are controlled by setting the address bits A21 and A22, respectively, during accesses. 3. NANDOE and NANDWE signals are multiplexed with PIO lines. Thus, the dedicated PIOs must be programmed in Peripheral mode in the PIO controller. 4. Configure a PIO line as an input to manage the Ready/Busy signal. 5. Configure SMC CS3 Setup, Pulse, Cycle and Mode ac cording to NAND Flash timings, the data bus width and the system bus frequency. In this example, the NAND Flash is not addressed as a “CE don’t care”. To address it as a “CE don’t care”, connect NCS3 (if SMC_NFCS3 is set) to the NAND Flash CE. NANDOE NANDWE (ANY PIO) (ANY PIO) ALE CLE D[0..7] 3V3 3V3 2 Gb TSOP48 PACKAGE U1 K9F2G08U0MU1 K9F2G08U0M WE18 N.C6 VCC 37 CE9 RE8 N.C20 WP19 N.C5 N.C1 N.C2 N.C3 N.C4 N.C21 N.C22 N.C23 N.C24 R/B7 N.C26 N.C 27N.C 28 I/O0 29 N.C 34N.C 35 VSS 36 PRE 38N.C 39 VCC 12 VSS 13 ALE17 N.C11 N.C10 N.C14 N.C15 CLE16 N.C25 N.C 33 I/O1 30 I/O3 32I/O2 31 N.C 47 N.C 46 N.C 45 I/O7 44I/O6 43I/O5 42I/O4 41 N.C 40 N.C 48R2 10KR2 10K 100NF 100NF R1 10KR1 10K 100NF 100NF

437SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

34.8.1.2 NOR Flash

Configure the SMC CS0 Setup, Pulse, Cycle and Mode depending on Flash timings and system bus frequency.

34.9 Standard Read and Write Protocols

In the following sections, the byte acce ss type is not considered. Byte select lines (NBS0 to NBS1) always have the same timing as the A address bus. NWE represents either the NWE signal in byte select access type or one of the byte write lines (NWR0 to NWR1) in byte write access type. NWR0 to NWR1 have the same timings and protocol as NWE. If D[15:8] are used, they have the same timing as D[7:0]. In the same way, NCS represents one of the NCS[0..3] chip select lines. A21 A15 A12 A13 A11 A10 A14 A16 A17 A20 A18 A19 D[0..7] A[0..21] NRST NWE NCS0 NRD 3V3 3V3 100NF 100NF 100NF 100NF U1U1 A10 A11 A12 A13 A14 A15 A16 A17 A18 A21 A20 A19 WE RESET WP OE CE VPP DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 VCCQ VSS VSS VCC

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 438

34.9.1 Read Waveforms

The read cycle is shown in Figure 34-7. The read cycle starts with the address setting on the memory address bus. Figure 34-7. Standard Read Cycle

34.9.1.1 NRD Waveform

The NRD signal is characterized by a setup timing, a pulse width and a hold timing.  NRD_SETUP— NRD setup time is defined as the setup of address before the NRD falling edge;  NRD_PULSE—NRD pulse length is the time between NRD falling edge and NRD rising edge;  NRD_HOLD—NRD hold time is defined as the ho ld time of address after the NRD rising edge.

34.9.1.2 NCS Waveform

The NCS signal can be divided into a setup time, pulse length and hold time:  NCS_RD_SETUP—NCS setup time is defined as the se tup time of address before the NCS falling edge.  NCS_RD_PULSE—NCS pulse length is the time bet ween NCS falling edge and NCS rising edge;  NCS_RD_HOLD—NCS hold time is defined as the hold time of address after the NCS rising edge.

34.9.1.3 Read Cycle

The NRD_CYCLE time is defined as the total duration of the read cycle, i.e., from the time where address is set on the address bus to the point where address may change. The total read cycle time is defined as: NRD_CYCLE = NRD_SETUP + NRD_PULSE + NRD_HOLD, as well as NRD_CYCLE = NCS_RD_SETUP + NCS_RD_PULSE + NCS_RD_HOLD All NRD and NCS timings are defined separately for each chip select as an integer number of Master Clock cycles. The NRD_CYCLE field is common to both the NRD and NCS signals, thus the timing period is of the same duration. A[23:0] NCS NRD_SETUP NRD_PULSE NRD_HOLD MCK NRD D[7:0] NCS_RD_SETUP NCS_RD_PULSE NCS_RD_HOLD NRD_CYCLE

439SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 NRD_CYCLE, NRD_SETUP, and NRD_PULSE implicitly define the NRD_HOLD value as: NRD_HOLD = NRD_CYCLE - NRD SETUP - NRD PULSE NRD_CYCLE, NCS_RD_SETUP, and NCS_RD_PULSE implicitly define the NCS_RD_HOLD value as: NCS_RD_HOLD = NRD_CYCLE - NCS_RD_SETUP - NCS_RD_PULSE

34.9.1.4 Null Delay Setup and Hold

If null setup and hold parameters are programmed for NRD and/or NCS, NRD and NCS remain active continuously in case of consecutive read cycles in the same memory (see Figure 34-8). Figure 34-8. No Setup, No Hold on NRD and NCS Read Signals

34.9.1.5 Null Pulse

Programming a null pulse is not permitted. The pulse must be at least set to 1. A null value leads to unpredictable behavior.

34.9.2 Read Mode

As NCS and NRD waveforms are defined independently of one other, the SMC needs to know when the read data is available on the data bus. The SMC does not compar e NCS and NRD timings to know which signal rises first. The READ_MODE bit in the SMC_MODE register of the corr esponding chip select indicates which signal of NRD and NCS controls the read operation. MCK NRD_PULSE NCS_RD_PULSE NRD_CYCLE NRD_PULSE NRD_PULSE NCS_RD_PULSE NCS_RD_PULSE NRD_CYCLE NRD_CYCLE A[23:0] NCS NRD D[7:0]

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 442

34.9.3 Write Waveforms

The write protocol is similar to the read protocol. It is depicted in Figure 34-11 . The write cycle starts with the address setting on the memory address bus.

34.9.3.1 NWE Waveforms

The NWE signal is characterized by a setup timing, a pulse width and a hold timing.  NWE_SETUP—the NWE setup time is defined as the setup of address and data before the NWE falling edge;  NWE_PULSE—the NWE pulse length is the time between NWE falling edge and NWE rising edge;  NWE_HOLD—the NWE hold time is de fined as the hold time of address and data after the NWE rising edge.

34.9.3.2 NCS Waveforms

The NCS signal waveforms in write operation are not the same that those applied in read operations, but are separately defined:  NCS_WR_SETUP—the NCS setup time is defined as the setup time of address before the NCS falling edge.  NCS_WR_PULSE—the NCS pulse lengt h is the time between NCS falling edge and NCS rising edge;  NCS_WR_HOLD—the NCS hold time is defined as th e hold time of address after the NCS rising edge. Figure 34-11. Write Cycle

34.9.3.3 Write Cycle

The write_cycle time is defined as the total duration of the write cycle; that is , from the time where address is set on the address bus to the point where address may change. The total write cycle time is defined as: NWE_CYCLE = NWE_SETUP + NWE_PULSE + NWE_HOLD, as well as NWE_CYCLE = NCS_WR_SETUP + NCS_WR_PULSE + NCS_WR_HOLD A[23:0] NCS NWE_SETUP NWE_PULSE NWE_HOLD MCK NWE NCS_WR_SETUP NCS_WR_PULSE NCS_WR_HOLD NWE_CYCLE

443SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 All NWE and NCS (write) timings are defined separately for each chip select as an integer number of Master Clock cycles. The NWE_CYCLE field is common to both the NWE and NCS signals, thus the timing period is of the same duration. NWE_CYCLE, NWE_SETUP, and NWE_PULSE implicitly define the NWE_HOLD value as: NWE_HOLD = NWE_CYCLE - NWE_SETUP - NWE_PULSE NWE_CYCLE, NCS_WR_SETUP, and NCS_WR_PULSE implicitly define the NCS_WR_HOLD value as: NCS_WR_HOLD = NWE_CYCLE - NCS_WR_SETUP - NCS_WR_PULSE

34.9.3.4 Null Delay Setup and Hold

If null setup parameters are programmed for NWE and/or NCS, NWE and/or NCS remain active continuously in case of consecutive write cycles in the same memory (see Figure 34-12 ). However, for devices that perform write operations on the rising edge of NWE or NCS, such as SRAM, either a setup or a hold must be programmed. Figure 34-12. Null Setup and Hold Values of NCS and NWE in Write Cycle

34.9.3.5 Null Pulse

Programming null pulse is not permitted. Pulse must be at least set to 1. A null value leads to unpredictable behavior. NCS MCK NWE D[7:0] NWE_PULSE NCS_WR_PULSE NWE_CYCLE NWE_PULSE NCS_WR_PULSE NWE_CYCLE NWE_PULSE NCS_WR_PULSE NWE_CYCLE A[23:0]

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 444

34.9.4 Write Mode

The bit WRITE_MODE in the SMC_MODE register of the corresponding chip select indicates which signal controls the write operation. Figure 34-13 shows the waveforms of a write operation with SMC_MODE.WRITE_MODE set . The data is put on the bus during the pulse and hold steps of the NWE signal. The internal data buffers are switched to Output mode after the NWE_SETUP time, and until the end of the write cycle, regardless of the programmed waveform on NCS. Figure 34-13. SMC_MODE.WRITE_MODE = 1. Write Operation is Controlled by NWE Figure 34-14 shows the waveforms of a write operation with SMC_MODE.WRITE_MODE cleared. The data is put on the bus during the pulse and hold steps of the NCS signal. The internal data buffers are switched to Output mode after the NCS_WR_SETUP time, and until the end of the write cycle, regardless of the programmed waveform on NWE. Figure 34-14. WRITE_MODE = 0. Write Operation is Controlled by NCS MCK D[7:0] NCS A[23:0] NWE MCK D[7:0] NCS NWE A[23:0]

445SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

34.9.5 Register Write Protection

To prevent any single software error that may corrupt SMC behavior, the registers listed below can be write- protected by setting the WPEN bit in the SMC Write Protection Mode register (SMC_WPMR). If a write access in a write-protected register is de tected, the WPVS flag in the SMC Write Protection Status register (SMC_WPSR) is set and the field WPVSRC in dicates in which register the write access has been attempted. The WPVS flag is automatically cleared after reading the SSMC_WPSR. The following registers can be write-protected:  “SMC Setup Register”  “SMC Pulse Register”  “SMC Cycle Register”  “SMC Mode Register”

34.9.6 Coding Timing Parameters

All timing parameters are defined for one chip select and are grouped together in one register according to their type. The SMC_SETUP register groups the definition of all setup parameters: ̶ NRD_SETUP ̶ NCS_RD_SETUP ̶ NWE_SETUP ̶ NCS_WR_SETUP The SMC_PULSE register groups the definition of all pulse parameters: ̶ NRD_PULSE ̶ NCS_RD_PULSE ̶ NWE_PULSE ̶ NCS_WR_PULSE The SMC_CYCLE register groups the definition of all cycle parameters: ̶ NRD_CYCLE ̶ NWE_CYCLE Table 34-5 shows how the timing parameters are coded and their permitted range. Table 34-5. Coding and Range of Timing Parameters Coded Value Number of Bits Effective Value Permitted Range Coded Value Effective Value setup [5:0] 6 128 × setup[5] + setup[4:0] 0 ≤ 31 0 ≤ 128+31 pulse [6:0] 7 256 × pulse[6] + pulse[5:0] 0 ≤ 63 0 ≤ 256+63 cycle [8:0] 9 256 × cycle[8:7] + cycle[6:0] 0 ≤ 127 0 ≤ 256+127 0 ≤ 512+127 0 ≤ 768+127

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 446

34.9.7 Reset Values of Timing Parameters

Table 34-6 gives the default value of timing parameters at reset.

34.9.8 Usage Restriction

The SMC does not check the validity of the user-programmed parameters. If the sum of SETUP and PULSE parameters is larger than the corresponding CYCLE parameter, this leads to unpredictable behavior of the SMC.  For read operations: Null but positive setup and hold of address and NRD and/or NCS can not be guaranteed at the memory interface because of the propagation delay of theses signals through external logic and pads. If positive setup and hold values must be verified, then it is strictly recommended to program non-null values so as to cover possible skews between address, NCS and NRD signals.  For write operations: If a null hold value is programmed on NWE, the SMC can guarantee a positive hold of address and NCS signal after the rising edge of NWE. This is true for SMC_MODE.WRITE_MODE = 1 only. See Section 34.11.2 ”Early Read Wait State”.  For read and write operations: A null value for pulse parameters is forbidden and may lead to unpredictable behavior. In read and write cycles, the setup and hold time parameters are defined in reference to the address bus. For external devices that require setup and hold time between NCS and NRD signals (read), or between NCS and NWE signals (write), these setup and hold times must be converted into setup and hold times in reference to the address bus. Table 34-6. Reset Values of Timing Parameters Parameter Reset Value Definition SMC_SETUP 0x01010101 All setup timings are set to 1. SMC_PULSE 0x01010101 All pulse timings are set to 1. SMC_CYCLE 0x00030003 The read and write operations continue for 3 Master Clock cycles and provide one hold cycle. WRITE_MODE 1 Write is controlled with NWE. READ_MODE 1 Read is controlled with NRD.

447SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

34.10 Scrambling/Un scrambling Function

The external data bus can be scrambled to prevent recovery of intellectual property data located in off-chip memories by means of data analysis at the package pin level of either the microcontroller or the memory device. The scrambling and unscrambling are performed on-the-fly without additional wait states. The scrambling/unscrambling function can be enabled or disabled by configur ing the CSxSE bits in the SMC Off- Chip Memory Scrambling Register (SMC_OCMS). When multiple chip selects are handled, the scrambling func tion per chip select is configurable using the CSxSE bits in the SMC_OCMS register. The scrambling method depends on two user-configurable key registers, SMC_KEY1 and SMC_KEY2 plus a random value depending on device processing characteristi cs. These key registers cannot be read. They can be written once after a system reset. The scrambling user key or the seed for key generation mu st be securely stored in a reliable non-volatile memory in order to recover data from the off-chip memory. Any data scrambled with a given key cannot be recovered if the key is lost.

34.11 Automatic Wait States

Under certain circumstances, the SMC automatically inserts idle cycles between accesses to avoid bus contention or operation conflict.

34.11.1 Chip Select Wait States

The SMC always inserts an idle cycle between two transfers on separate chip selects. This idle cycle ensures that there is no bus contention between the de-activation of one device and the activation of the next one. During chip select wait state, all control lines are turned inactive: NWR, NCS[0..3], NRD lines are all set to 1. Figure 34-15 illustrates a chip select wait state between access on chip select 0 and chip select 2.

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 448 Figure 34-15. Chip Select Wait State between a Read Access on NCS0 and a Write Access on NCS2

34.11.2 Early Read Wait State

In some cases, the SMC inserts a wait state cycle between a write access and a read access to allow time for the write cycle to end before the subsequent read cycle begins. This wait state is not generated in addition to a chip select wait state. The early read cycle thus only oc curs between a write and read access to the same memory device (same chip select). An early read wait state is automatically inserted if at least one of the following conditions is valid:  if the write controlling signal has no hold time and the read controlling signal has no setup time (Figure 34- 16).  in NCS Write controlled mode (SMC_MODE.WRITE_MODE = 0), if there is no hold timing on the NCS signal and the NCS_RD_SETUP parameter is set to 0, regardless of the Read mode (Figure 34-17). The write operation must end with a NCS rising edge. Without an Early Read Wait State, the write operation could not complete properly.  in NWE controlled mode (SMC_MODE.WRITE_MODE = 1) and if there is no hold timing (NWE_HOLD = 0), the feedback of the write control signal is used to control address, data, and chip select lines. If the external write control signal is not inactivated as expected due to load capacitances, an Early Read Wait State is inserted and address, data and control signals are maintained one more cycle. See Figure 34-18. A[23:0] NCS0 NRD_CYCLE Chip Select Wait State NWE_CYCLE MCK NCS2 NRD NWE D[7:0] Read to Write Wait State

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 450 Figure 34-18. Early Read Wait State: NWE-controlled writ e with no hold followed by a read with one set-up cycle

34.11.3 Reload User Configuration Wait State

The user may change any of the configuration parameters by writing the SMC user interface. When detecting that a new user configuration has been written in the user interface, the SMC inserts a wait state before starting the next access. This “reload user configuration wait state” is used by the SMC to load the new set of parameters to apply to next accesses. The reload configuration wait state is not applied in addition to the chip select wait state. If accesses before and after re-programming the user interface are made to different devices (chip selects), then one single chip select wait state is applied. On the other hand, if accesses before and after writing th e user interface are made to the same device, a reload configuration wait state is inserted, even if the change does not concern the current chip select.

34.11.3.1 User Procedure

To insert a reload configuration wait state, the SMC detects a write access to any SMC_MODE register of the user interface. If the user only modifies timing registers (SMC_SETUP, SMC_PU LSE, SMC_CYCLE registers) in the user interface, he must validate the modification by writing the SMC_MODE, even if no change was made on the mode parameters. The user must not change the configuration parameters of an SMC chip select (Setup, Pulse, Cycle, Mode) if accesses are performed on this CS during the modifica tion. Any change of the chip select parameters, while fetching the code from a memory connected on this CS, may lead to unpredictable behavior. The instructions used to modify the parameters of an SMC chip select can be executed from the internal RAM or from a memory connected to another CS. A[25:2] write cycle (WRITE_MODE = 1) Early Read wait state MCK NRD internal write controlling signal external write controlling signal (NWE) D[7:0] read cycle no hold read setup = 1 (READ_MODE = 0 or READ_MODE = 1)

451SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

34.11.3.2 Slow Clock Mode Transition

A reload configuration wait state is al so inserted when the Slow Clock mode is entered or exited, after the end of the current transfer (see Section 34.14 ”Slow Clock Mode”).

34.11.4 Read to Write Wait State

Due to an internal mechanism, a wait cycle is always inserted between consecutive read and write SMC accesses. This wait cycle is referred to as a read to write wait state in this document. This wait cycle is applied in addition to chip select and reload user configur ation wait states when they are to be inserted. See Figure 34-15.

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 452

34.12 Data Float Wait States

Some memory devices are slow to release the external bus. For such devices, it is necessary to add wait states (data float wait states) after a read access:  before starting a read access to a different external memory  before starting a write access to the same device or to a different external one. The data float output time (t DF ) for each external memory device is programmed in the SMC_MODE.TDF_CYCLES field for the corresponding ch ip select. The value of SMC_MODE.TDF_CYCLES indicates the number of data float wait cycles (between 0 and 15) before the external device releases the bus, and represents the time allowed for the data output to go to high impedance after the memory is disabled. Data float wait states do not delay internal memory acce sses. Hence, a single access to an external memory with long tDF will not slow down the execution of a program from internal memory. The data float wait states management depends on SMC_MODE.READ_MODE and the SMC_MODE.TDF_MODE fields for the corresponding chip select. 34.12.1 SMC_MODE.READ_MODE Setting SMC_MODE.READ_MODE to 1 indicates to the SMC that the NRD signal is responsible for turning off the tri-state buffers of the external memory device. The Data Float Period then begins after the rising edge of the NRD signal and lasts SMC_MODE.TDF_CYCLES MCK cycles. When the read operation is controlled by the NCS signal (SMC_MODE.READ_MODE = 0), the TDF field gives the number of MCK cycles during which the data bus remains busy after the rising edge of NCS. Figure 34-19 illustrates the Data Float Period in NRD-controlled mode (SMC_MODE.READ_MODE =1), assuming a data float period of 2 cyc les (SMC_MODE.TDF_CYCLES = 2). Figure 34-20 shows the read operation when controlled by NCS (SMC_MODE.READ_MODE = 0) and SMC_MODE.TDF_CYCLES = 3. Figure 34-19. TDF Period in NRD Controlled Read Access (TDF = 2) NCS NRD controlled read operation tpacc MCK NRD D[7:0] TDF = 2 clock cycles A[23:0]

453SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 Figure 34-20. TDF Period in NCS Controlled Read Operation (TDF = 3) NCS TDF = 3 clock cycles tpacc MCK D[7:0] NCS controlled read operation A[23:0] NRD

455SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 34.12.3 TDF Optimization Disa bled (SMC_MODE.TDF_MODE = 0) When optimization is disabled, TDF wait states are insert ed at the end of the read transfer, so that the data float period is ended when the second access begins. If the hold period of the read1 controlling signal overlaps the data float period, no additional tdf wait states will be inserted. Figure 34-22, Figure 34-23 and Figure 34-24 illustrate the cases:  read access followed by a read access on another chip select,  read access followed by a write access on another chip select,  read access followed by a write access on the same chip select, with no TDF optimization. Figure 34-22. TDF Optimization Disabled (TDF Mode = 0): TDF wait states between 2 read accesses on different chip selects TDF_CYCLES = 6 TDF_CYCLES = 6 TDF_MODE = 0 A[23:0] read1 cycle Chip Select Wait State MCK read1 controlling signal (NRD) read2 controlling signal (NRD) D[7:0] read1 hold = 1 read 2 cycle read2 setup = 1

5 TDF WAIT STATES

(optimization disabled)

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 456 Figure 34-23. TDF Mode = 0: TDF wait states between a read and a write access on different chip selects Figure 34-24. TDF Mode = 0: TDF wait states between read and write accesses on the same chip select TDF_CYCLES = 4 TDF_CYCLES = 4 TDF_MODE = 0 (optimization disabled) A[23:0] read1 cycle Chip Select Wait State Read to Write Wait State MCK read1 controlling signal (NRD) write2 controlling signal (NWE) D[7:0] read1 hold = 1 write2 cycle write2 setup = 1

2 TDF WAIT STATES

TDF_CYCLES = 5 TDF_CYCLES = 5 TDF_MODE = 0 (optimization disabled) A[23:0] read1 cycle Read to Write Wait State MCK read1 controlling signal (NRD) write2 controlling signal (NWE) D[7:0] read1 hold = 1 write2 cycle write2 setup = 1

4 TDF WAIT STATES

457SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

34.13 External Wait

Any access can be extended by an external device using the NWAIT input signal of the SMC. The SMC_MODE.EXNW_MODE field on the corresponding chip select must be set either to “10” (Frozen mode) or “11” (Ready mode). When SMC_MODE.EXNW_MODE is se t to “00” (disabled), the NWAIT signal is simply ignored on the corresponding chip select. The NWAIT signal delays the read or write operation in regards to the read or write controlling signal, depending on the Read and Write modes of the corresponding chip select.

34.13.1 Restriction

When SMC_MODE.EXNW_MODE is enabled, it is mandatory to program at least one hold cycle for the read/write controlling signal. For that reason, the NWAIT signal cannot be used in Page mode ( Section 34.15 ”Asynchronous Page Mode”), or in Slow clock mode (Section 34.14 ”Slow Clock Mode”). The NWAIT signal is assumed to be a response of the external device to the read/write request of the SMC. Then NWAIT is examined by the SMC only in the pulse state of the read or write controlling signal. The assertion of the NWAIT signal outside the expected period has no impact on SMC behavior.

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 458

34.13.2 Frozen Mode

When the external device asserts the NWAIT signal (active low), and after internal synchronization of this signal, the SMC state is frozen, i.e., SMC internal counters are frozen, and all control signals remain unchanged. When the resynchronized NWAIT signal is d easserted, the SMC completes the access, resuming the access from the point where it was stopped. See Figure 34-25 . This mode must be selected when the external device uses the NWAIT signal to delay the access and to freeze the SMC. The assertion of the NWAIT signal outside the expected period is ignored as illustrated in Figure 34-26. Figure 34-25. Write Access with NWAIT Assertion in Frozen Mode (SMC_MODE.EXNW_MODE = 10) EXNW_MODE = 10 (Frozen) WRITE_MODE = 1 (NWE_controlled) NWE_PULSE = 5 NCS_WR_PULSE = 7 A[23:0] MCK NWE NCS 43 2 1 1 10 1 4563 2 2 2 2 1 0 Write cycle D[7:0] NWAIT FROZEN STATE internally synchronized NWAIT signal

459SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 Figure 34-26. Read Access with NWAIT Assertion in Frozen Mode (SMC_MODE.EXNW_MODE = 10) EXNW_MODE = 10 (Frozen) READ_MODE = 0 (NCS_controlled) NRD_PULSE = 2, NRD_HOLD = 6 NCS_RD_PULSE =5, NCS_RD_HOLD =3 A[23:0] MCK NCS NRD 10 55 5 22 0 21 0 21 0 Read cycle Assertion is ignored NWAIT internally synchronized NWAIT signal FROZEN STATE

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 460

34.13.3 Ready Mode

In Ready mode (SMC_MODE.EXNW_MODE = 11), the SMC behaves differently. Normally, the SMC begins the access by down counting the setup and pulse counters of the read/write controlling signal. In the last cycle of the pulse phase, the resynchronized NWAIT signal is examined. If asserted, the SMC suspends the access as shown in Figure 34-27 and Figure 34-28 . After deassertion, the access is completed: the hold step of the access is performed. This mode must be selected when the external device uses deassertion of the NWAIT signal to indicate its ability to complete the read or write operation. If the NWAIT signal is deasserted before the end of the pulse, or asserted after the end of the pulse of the controlling read/write signal, it has no impact on the access length as shown in Figure 34-28. Figure 34-27. NWAIT Assertion in Write Access: Ready Mode (SMC_MODE.EXNW_MODE = 11) EXNW_MODE = 11 (Ready mode) WRITE_MODE = 1 (NWE_controlled) NWE_PULSE = 5 NCS_WR_PULSE = 7 A[23:0] MCK NWE NCS 43 2 1 0 0 0 4563 2 1 1 1 0 Write cycle D[7:0] NWAIT internally synchronized NWAIT signal Wait STATE

461SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 Figure 34-28. NWAIT Assertion in Read Access: Ready Mode (SMC_MODE.EXNW_MODE = 11) EXNW_MODE = 11(Ready mode) READ_MODE = 0 (NCS_controlled) NRD_PULSE = 7 NCS_RD_PULSE =7 A[23:0] MCK NCS NRD 4563 2 0 0 4563 2 1 1 Read cycle Assertion is ignored NWAIT internally synchronized NWAIT signal Wait STATE Assertion is ignored

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 462

34.13.4 NWAIT Latency and Read/Write Timings

There may be a latency between the asse rtion of the read/write controlling si gnal and the assertion of the NWAIT signal by the device. The programmed pulse length of the read/write controlling signal must be at least equal to this latency plus the 2 cycles of resynchronization + one cycle. Otherwise, the SMC may enter the hold state of the access without detecting the NWAIT signal assertion. This is true in Frozen mode as well as in Ready mode. This is illustrated on Figure 34-29. When SMC_MODE.EXNW_MODE is enabled (ready or frozen), the user must program a pulse length of the read and write controlling signal of at least: Minimal pulse length = NWAIT latency + 2 resynchronization cycles + 1 cycle Figure 34-29. NWAIT Latency EXNW_MODE = 10 or 11 READ_MODE = 1 (NRD_controlled) NRD_PULSE = 5 A[23:0] MCK NRD 43 21 0 0 0 Read cycle minimal pulse length NWAIT latency NWAIT intenally synchronized NWAIT signal WAIT STATE 2 cycle resynchronization

463SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

34.14 Slow Clock Mode

The SMC is able to automatically apply a set of “Slow clock mode” read/write waveforms when an internal signal driven by the Power Management Controller is asserted because MCK has been turned to a very slow clock rate (typically 32kHz clock rate). In this mode, the user-p rogrammed waveforms are ignored and the Slow clock mode waveforms are applied. This mode is provided so as to avoid reprogramming the User Interface with appropriate waveforms at a very slow clock rate. When activated, the Slow clock mode is active on all chip selects.

34.14.1 Slow Clock Mode Waveforms

Figure 34-30 illustrates the read and write operations in Slow clock mode. They are valid on all chip selects. Table 34-7 indicates the value of read and write parameters in Slow clock mode. Figure 34-30. Read/Write Cycles in Slow Clock Mode A[23:0] NCS MCK NWE 1 NWE_CYCLE = 3 A[23:0] MCK NRD NRD_CYCLE = 2 NCS SLOW CLOCK MODE WRITE SLOW CLOCK MODE READ Table 34-7. Read and Write Timing Parameters in Slow Clock Mode Read Parameters Duration (cycles) Write Parameters Duration (cycles) NRD_SETUP 1 NWE_SETUP 1 NRD_PULSE 1 NWE_PULSE 1 NCS_RD_SETUP 0 NCS_WR_SETUP 0 NCS_RD_PULSE 2 NCS_WR_PULSE 3 NRD_CYCLE 2 NWE_CYCLE 3

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 464

34.14.2 Switching from (to) Slow Cl ock Mode to (from) Normal Mode

When switching from Slow clock mode to Normal mode, the current Slow cloc k mode transfer is completed at a high clock rate, with the set of Slow clock mode parameters.See Figure 34-31. The external device may not be fast enough to support such timings. Figure 34-32 illustrates the recommended procedure to switch from one mode to the other. Figure 34-31. Clock Rate Transition Occurs wh ile the SMC is Performing a Write Operation Figure 34-32. Recommended Procedure to Switch from Slow Clock Mode to Normal Mode or from Normal Mode to Slow Clock Mode A[23:0] NCS MCK NWE NWE_CYCLE = 3 SLOW CLOCK MODE WRITE Slow Clock Mode internal signal from PMC 11 1 2 3 2 NWE_CYCLE = 7 NORMAL MODE WRITE Slow clock mode transition is detected: Reload Configuration Wait State This write cycle finishes with the slow clock mode set of parameters after the clock rate transition SLOW CLOCK MODE WRITE A[23:0] NCS MCK NWE SLOW CLOCK MODE WRITE Slow Clock Mode internal signal from PMC 2 3 2 NORMAL MODE WRITEIDLE STATE Reload Configuration Wait State

465SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

34.15 Asynchronous Page Mode

The SMC supports asynchronous burst reads in Page mode, provided that the Page mode is enabled (SMC_MODE.PMEN =1). The page size must be configured in the SMC_MODE register (PS field) to 4, 8, 16 or 32 bytes. The page defines a set of consecutive bytes into memory. A 4-byte page (resp. 8-, 16-, 32-byte page) is always aligned to 4-byte boundaries (resp. 8-, 16-, 32-byte bou ndaries) of memory. The MSB of data address defines the address of the page in memory, the LSB of address define the address of the data in the page as detailed in Table 34-8. With Page mode memory devices, the first access to one page (tpa) takes longer than the subsequent accesses to the page (tsa) as shown in Figure 34-33. When in Page mode, the SMC enables the user to define different read timings for the first access within one page, and next accesses within the page. Note: 1. “A” denotes the addre ss bus of the memory device.

34.15.1 Protocol and Timings in Page Mode

Figure 34-33 shows the NRD and NCS timings in Page mode access. Figure 34-33. Page Mode Read Protocol (Address MSB and LSB are defined in Table 34-8) The NRD and NCS signals are held low dur ing all read transfers, whatever the programmed values of the setup and hold timings in the User Interface may be. Moreover, the NRD and NCS timings are identical. The pulse length of the first access to the page is defined with the NCS_RD_PULSE field of the SMC_PULSE register. The pulse length of subsequent accesses within the page are defined using the NRD_PULSE parameter. Table 34-8. Page Address and Data Address within a Page Page Size Page Address (1) Data Address in the Page 4 bytes A[23:2] A[1:0] 8 bytes A[23:3] A[2:0] 16 bytes A[23:4] A[3:0] 32 bytes A[23:5] A[4:0]A[MSB] NCS MCK NRD D[7:0] NCS_RD_PULSE NRD_PULSENRD_PULSE tsatpa tsa A[LSB]

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 466 In Page mode, the programming of the read timings is described in Table 34-9: The SMC does not check the coherency of timings. It will always apply the NCS_RD_PULSE timings as page access timing (t pa) and the NRD_PULSE for accesses to the page (t sa), even if the programmed value for t pa is shorter than the programmed value for tsa.

34.15.2 Page Mode Restriction

The Page mode is not compatible with the use of the NWAIT signal. Using the Page mode and the NWAIT signal may lead to unpredictable behavior.

34.15.3 Sequential and Non-sequential Accesses

If the chip select and the MSB of addresses as defined in Table 34-8 are identical, then the current access lies in the same page as the previous one, and no page break occurs. Using this information, all data within the same page, sequential or not sequential, are accessed with a minimum access time (t sa). Figure 34-34 illustrates access to an 8-bit memory device in Page mode, with 8-byte pages. Access to D1 causes a page ac cess with a long access time (t pa). Accesses to D3 and D7, though they are not sequential accesses, only require a short access time (tsa). If the MSB of addresses are different, the SMC performs the access of a new page. In the same way, if the chip select is different from the previous access, a page break occurs. If two sequential accesses are made to the Page mode memory, but separated by an other internal or ex ternal peripheral access, a page break occurs on the second access because the chip select of the device was deasserted between both accesses. Figure 34-34. Access to Non-Sequential Data within the Same Page Table 34-9. Programming of Read Timings in Page Mode Parameter Value Definition READ_MODE ‘x’ No impact NCS_RD_SETUP ‘x’ No impact NCS_RD_PULSE t pa Access time of first access to the page NRD_SETUP ‘x’ No impact NRD_PULSE t sa Access time of subsequent accesses in the page NRD_CYCLE ‘x’ No impact A[23:3] A[2], A1, A0 NCS MCK NRD Page address A1 A3 A7 D[7:0] NCS_RD_PULSE NRD_PULSENRD_PULSE D1 D3 D7

467SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

34.16 Static Memory Controll er (SMC) User Interface

The SMC is programmed using the registers listed in Table 34-10. For each chip select, a set of four registers is used to program the parameters of the external device connected on it. In Table 34-10, “CS_number” denotes the chip select num- ber. 16 bytes (0x10) are required per chip select. Note: The user must confirm the SMC configuration by writing any one of the SMC_MODE registers. Notes: 1. All unlisted offset values are considered as ‘reserved’. Table 34-10. Register Mapping Offset Register Name Access Reset 0x10 x CS_number + 0x00 SMC Setup Register SMC_SETUP Read/Write 0x01010101 0x10 x CS_number + 0x04 SMC Pulse Register SMC_PULSE Read/write 0x01010101 0x10 x CS_number + 0x08 SMC Cycle Register SMC_CYCLE Read/Write 0x00030003 0x10 x CS_number + 0x0C SMC Mode Register SMC_MODE Read/Write 0x10001003 0x80 SMC Off-Chip Memory Scrambling Register SMC_OCMS Read/Write 0x00000000 0x84 SMC Off-Chip Memory Scrambling KEY1 Register SMC_KEY1 Write-once 0x00000000 0x88 SMC Off-Chip Memory Scrambling KEY2 Register SMC_KEY2 Write-once 0x00000000 0xE4 SMC Write Protection Mode Register SMC_WPMR Read/Write 0x00000000 0xE8 SMC Write Protection Status Register SMC_WPSR Read-only 0x00000000 0xEC-0xFC Reserved – – –

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 468

34.16.1 SMC Setup Register

Name: SMC_SETUP[0..3] Address: 0x40080000 [0], 0x40080010 [1], 0x40080020 [2], 0x40080030 [3] Access: Read/Write This register can only be written if the WPEN bit is cleared in the “SMC Write Protection Mode Register” .

• NWE_SETUP: NWE Setup Length The NWE signal setup length is defined as: NWE setup length = (128* NWE_SETUP[5] + NWE_SETUP[4:0]) clock cycles
• NCS_WR_SETUP: NCS Setup Length in WRITE Access In write access, the NCS signal setup length is defined as: NCS setup length = (128* NCS_WR_SETUP[5] + NCS_WR_SETUP[4:0]) clock cycles
• NRD_SETUP: NRD Setup Length The NRD signal setup length is defined in clock cycles as: NRD setup length = (128* NRD_SETUP[5] + NRD_SETUP[4:0]) clock cycles
• NCS_RD_SETUP: NCS Setup Length in READ Access In read access, the NCS signal setup length is defined as: NCS setup length = (128* NCS_RD_SETUP[5] + NCS_RD_SETUP[4:0]) clock cycles 31 30 29 28 27 26 25 24 – – NCS_RD_SETUP 23 22 21 20 19 18 17 16 – – NRD_SETUP 15 14 13 12 11 10 9 8 – – NCS_WR_SETUP 76543210 – – NWE_SETUP

469SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

34.16.2 SMC Pulse Register

Name: SMC_PULSE[0..3] Address: 0x40080004 [0], 0x40080014 [1], 0x40080024 [2], 0x40080034 [3] Access: Read/Write This register can only be written if the WPEN bit is cleared in the “SMC Write Protection Mode Register” .

• NWE_PULSE: NWE Pulse Length The NWE signal pulse length is defined as: NWE pulse length = (256* NWE_PULSE[6] + NWE_PULSE[5:0]) clock cycles The NWE pulse length must be at least 1 clock cycle.
• NCS_WR_PULSE: NCS Pulse Length in WRITE Access In write access, the NCS signal pulse length is defined as: NCS pulse length = (256* NCS_WR_PULSE[6] + NCS_WR_PULSE[5:0]) clock cycles The NCS pulse length must be at least 1 clock cycle.
• NRD_PULSE: NRD Pulse Length In standard read access, the NRD signal pulse length is defined in clock cycles as: NRD pulse length = (256* NRD_PULSE[6] + NRD_PULSE[5:0]) clock cycles The NRD pulse length must be at least 1 clock cycle. In Page mode read access, the NRD_PULSE parameter defines the duration of the subseque nt accesses in the page.
• NCS_RD_PULSE: NCS Puls e Length in READ Access In standard read access, the NCS signal pulse length is defined as: NCS pulse length = (256* NCS_RD_PULSE[6] + NCS_RD_PULSE[5:0]) clock cycles The NCS pulse length must be at least 1 clock cycle. In Page mode read access, the NCS_RD_PULSE parameter defines the duration of the first access to one page. 31 30 29 28 27 26 25 24 – NCS_RD_PULSE 23 22 21 20 19 18 17 16 – NRD_PULSE 15 14 13 12 11 10 9 8 – NCS_WR_PULSE 76543210 –N WE_PULSE

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 470

34.16.3 SMC Cycle Register

Name: SMC_CYCLE[0..3] Address: 0x40080008 [0], 0x40080018 [1], 0x40080028 [2], 0x40080038 [3] Access: Read/Write This register can only be written if the WPEN bit is cleared in the “SMC Write Protection Mode Register” .

• NWE_CYCLE: Total Write Cycle Length The total write cycle length is the total duration in clock cycles of the write cycle. It is equal to the sum of the setup, pulse and hold steps of the NWE and NCS signals. It is defined as: Write cycle length = (NWE_CYCLE[8:7]*256 + NWE_CYCLE[6:0]) clock cycles
• NRD_CYCLE: Total Read Cycle Length The total read cycle length is the total duration in clock cycles of the read cycle. It is equal to the sum of the setup, pulse and hold steps of the NRD and NCS signals. It is defined as: Read cycle length = (NRD_CYCLE[8:7]*256 + NRD_CYCLE[6:0]) clock cycles 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 NRD_CYCLE 15 14 13 12 11 10 9 8 76543210 NWE_CYCLE

471SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

34.16.4 SMC Mode Register

Name: SMC_MODE[0..3] Address: 0x4008000C [0], 0x4008001C [1], 0x4008002C [2], 0x4008003C [3] Access: Read/Write This register can only be written if the WPEN bit is cleared in the “SMC Write Protection Mode Register” . The user must confirm the SMC configuration by writing any one of the SMC_MODE registers.

• READ_MODE: Read Mode 0: The read operation is controlled by the NCS signal. – If TDF cycle s are programmed, the external bus is marked busy after the rising edge of NCS. – If TDF optimiza tion is enabled (TDF_MODE =1), TDF wait states are inserted after the setup of NCS. 1: The read operation is controlled by the NRD signal. – If TDF cycle s are programmed, the external bus is marked busy after the rising edge of NRD. – If TDF optimiza tion is enabled (TDF_MODE =1), TDF wait states are inserted after the set up of NRD.
• WRITE_MODE: Write Mode 0: The write operation is controlled by the NCS signal. – If TDF optimiza tion is enabled (TDF_MODE =1), TDF wait states will be inserted after the setup of NCS. 1: The write operation is controlled by the NWE signal. – If TDF optimiza tion is enabled (TDF_MODE =1), TDF wait states will be inserted after the setup of NWE.
• EXNW_MODE: NWAIT Mode The NWAIT signal is used to extend the current read or write signal. It is only taken into account during the pulse phase of the read and write controlling signal. When the use of NWAIT is enabled, at least one cycle hold duration must be pro- grammed for the read and write controlling signal. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 – – – TDF_MODE TDF_CYCLES 15 14 13 12 11 10 9 8 765432 1 0 – – EXNW_MODE – – WRITE_MODE READ_MODE Value Name Description 0 DISABLED Disabled–The NWAIT input signal is ignored on the corresponding chip select. 1– R e s e r v e d 2F R O Z E N Frozen Mode–If asserted, the NWAIT signal freezes the current read or write cycle. After deassertion, the read/write cycle is resumed from the point where it was stopped. 3R E A D Y Ready Mode–The NWAIT signal indicates the availability of the external device at the end of the pulse of the controlling read or write signal, to complete the access. If high, the access normally completes. If low, the access is extended until NWAIT returns high.

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 472

• BAT: Byte Access Type This field is used only if DBW defines a 16-bit data bus.
• DBW: Data Bus Width
• TDF_CYCLES: Data Float Time This field gives the integer number of clock cycles required by the external device to release the data after the rising edge of the read controlling signal. The SMC always provide one full cycle of bus turnaround after the TDF_CYCLES period. The external bus cannot be used by another chip select during TDF_CYCLES + 1 cycles. From 0 up to 15 TDF_CYCLES can be set.
• TDF_MODE: TDF Optimization 0: TDF optimization disabled–the number of TDF wait states is inserted before the next access begins. 1: TDF optimization enabled–the number of TDF wait states is optimized using the setup period of the next read/write access.
• PMEN: Page Mode Enabled 0: Standard read is applied. 1: Asynchronous burst read in page mode is applied on the corresponding chip select.
• PS: Page Size If page mode is enabled, this field indicates the size of the page in bytes. Value Name Description

0 BYTE_SELECT

Byte select access type: - Write operation is controlled using NCS, NWE, NBS0, NBS1. - Read operation is controlled using NCS, NRD, NBS0, NBS1.

1 BYTE_WRITE

Byte write access type: - Write operation is controlled using NCS, NWR0, NWR1. - Read operation is controlled using NCS and NRD. Value Name Description 0 8_BIT 8-bit Data Bus 1 16_BIT 16-bit Data Bus Value Name Description 0 4_BYTE 4-byte page 1 8_BYTE 8-byte page 2 16_BYTE 16-byte page 3 32_BYTE 32-byte page

473SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

34.16.5 SMC Off-Chip Memo ry Scrambling Register

Name: SMC_OCMS Address: 0x40080080 Access: Read/Write

• CSxSE: Chip Select (x = 0 to 3) Scrambling Enable 0: Disable scrambling for CSx. 1: Enable scrambling for CSx.
• SMSE: Static Memory Controller Scrambling Enable 0: Disable scrambling for SMC access. 1: Enable scrambling for SMC access. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 –––– C S3SE C S2SE C S1SE C S0SE 76543210

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 474

34.16.6 SMC Off-Chip Memory Scrambling Key1 Register

Name: SMC_KEY1 Address: 0x40080084 Access: Write-once (1) Note: 1. ‘Write-once’ access indicates that the first write access after a system reset prevents any further modification of the value of this register.

• KEY1: Off-Chip Memory Sc rambling (OCMS) Key Part 1 When off-chip memory scrambling is enabled, KEY1 and KEY2 values determine data scrambling. 31 30 29 28 27 26 25 24 KEY1 23 22 21 20 19 18 17 16 KEY1 15 14 13 12 11 10 9 8 KEY1 76543210 KEY1

475SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

34.16.7 SMC Off-Chip Memory Scrambling Key2 Register

Name: SMC_KEY2 Address: 0x40080088 Access: Write-once (1) Notes: 1. ‘Write-once’ access indicates that the first write access after a system reset prevents any further modification of the value of this register.

• KEY2: Off-Chip Memory Sc rambling (OCMS) Key Part 2 When off-chip memory scrambling is enabled, KEY1 and KEY2 values determine data scrambling. 31 30 29 28 27 26 25 24 KEY2 23 22 21 20 19 18 17 16 KEY2 15 14 13 12 11 10 9 8 KEY2 76543210 KEY2

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 476

34.16.8 SMC Write Protection Mode Register

Name: SMC_WPMR Address: 0x400800E4 Access: Read/Write

• WPEN: Write Protect Enable 0: Disables the write protection if WPKEY corresponds to 0x534D43 (“SMC” in ASCII). 1: Enables the write protection if WPKEY corresponds to 0x534D43 (“SMC” in ASCII). See Section 34.9.5 ”Register Write Protection” for the list of registers that can be write-protected.
• WPKEY: Write Protection Key 31 30 29 28 27 26 25 24 WPKEY 23 22 21 20 19 18 17 16 WPKEY 15 14 13 12 11 10 9 8 WPKEY 76543210 Value Name Description 0x534D43 PASSWD Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0.

477SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

34.16.9 SMC Write Protection Status Register

Name: SMC_WPSR Address: 0x400800E8 Type: Read-only

• WPVS: Write Protection Violation Status 0: No write protection violation has occurred since the last read of the SMC_WPSR register. 1: A write protection violation has occurred since the last read of the SMC_WPSR register. If this violation is an unauthor- ized attempt to write a protected register, the associated violation is reported into field WPVSRC.
• WPVSRC: Write Protection Violation Source When WPVS = 1, WPVSRC indicates the register address offset at which a write access has been attempted. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WPVSRC 15 14 13 12 11 10 9 8 WPVSRC 76543210

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 478 35. DMA Controller (XDMAC)

35.1 Description

The DMA Controller (XDMAC) is a AHB-protocol central dire ct memory access controller. It performs peripheral data transfer and memory move operations over one or two bus ports through the unidirectional communication channel. Each channel is fully programmable and provides both peripheral or memory-to-memory transfer. The channel features are configurable at implementation.

35.2 Embedded Characteristics

 2 AHB Master Interface  24 DMA Channels  44 Hardware Requests  3.1 Kbytes Embedded FIFO  Supports Peripheral to Memory, Memory to Peripheral, or Memory to Memory Transfer Operations  Peripheral DMA Operation Runs on Bytes (8-bit), Half-Word (16-bit) and Word (32-bit)  Memory DMA Operation Runs on Bytes (8 bit), Half-Word (16-bit) and Word (32 -bit)  Supports Hardware and Software Initiated Transfers  Supports Linked List Operations  Supports Incrementing or Fixed Addressing Mode  Supports Programmable Independent Data Striding for Source and Destination  Supports Programmable Independent Microblock Striding for Source and Destination  Configurable Priority Group and Arbitration Policy  Programmable AHB Burst Length  Configuration Interface Accessible through APB Interface  XDMAC Architecture Includes Multiport FIFO  Multiple View Channel Descriptor Supported  Automatic Flush of Channel Trailing Bytes  Automatic Coarse-Grain and Fine-Grain Clock Gating  Hardware Acceleration of Memset Pattern

479SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

35.3 Block Diagram

Figure 35-1. DMA Controlle r (XDMAC) Block Diagram Status Registers Configuration Registers APB Interface DMA Interrupt Dual Master AHB Interface Request Arbiter Hardware Request InterfaceControl and Data Steering Request Pool DMA Read/Write Datapath AMBA AHB Layer APB Interface DMA Interrupt Peripheral Hardware Requests DMA ChannelData FIFO Destination FSM Source FSM DMA System Controller AMBA AHB Layer

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 480

35.4 DMA Controller Peripheral Connections

The DMA Controller handles the transfer between peripherals and memory and receives requests from the peripherals listed in Table 35-1. For each listed DMA channel number, the SIF and/or DIF bits in XDMAC_CCx must be programmed with a value compatible with the MATRIX “Master to Slave Access” definition provided in Section 18. “Bus Matrix (MATRIX)”. Depending on transfer descriptor location, the NDAIF bit in XDMAC_CNDAx must be programmed with a value compatible with the MATRIX “Master to Slave Access” definition provided in Section 18. “Bus Matrix (MATRIX)”. Table 35-1. Peripheral Hardware Requests Peripheral Name Transfer Type HW Interface Number (XDMAC_CC.PERID) HSMCI Transmit/Receive 0 SPI0 Transmit 1 SPI0 Receive 2 SPI1 Transmit 3 SPI1 Receive 4 QSPI Transmit 5 QSPI Receive 6 USART0 Transmit 7 USART0 Receive 8 USART1 Transmit 9 USART1 Receive 10 USART2 Transmit 11 USART2 Receive 12 PWM0 Transmit 13 TWIHS0 Transmit 14 TWIHS0 Receive 15 TWIHS1 Transmit 16 TWIHS1 Receive 17 TWIHS2 Transmit 18 TWIHS2 Receive 19 UART0 Transmit 20 UART0 Receive 21 UART1 Transmit 22 UART1 Receive 23 UART2 Transmit 24 UART2 Receive 25 UART3 Transmit 26 UART3 Receive 27 UART4 Transmit 28 UART4 Receive 29 DACC Transmit 30

481SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 SSC Transmit 32 SSC Receive 33 PIOA Receive 34 AFEC0 Receive 35 AFEC1 Receive 36 AES Transmit 37 AES Receive 38 PWM1 Transmit 39 TC0 Receive 40 TC3 Receive 41 TC6 Receive 42 TC9 Receive 43 I2SC0 Transmit Left 44 I2SC0 Receive Left 45 I2SC1 Transmit Left 46 I2SC1 Receive Left 47 I2SC0 Transmit Right 48 I2SC0 Receive Right 49 I2SC1 Transmit Right 50 I2SC1 Receive Right 51 Table 35-1. Peripheral Hardware Requests (Continued) Peripheral Name Transfer Type HW Interface Number (XDMAC_CC.PERID)

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 482

35.5 Functional Description

35.5.1 Basic Definitions

Source Peripheral: Slave device, memory mapped on the interconnection network, from where the XDMAC reads data. The source peripheral teams up with a destination peripheral to form a channel. A data read operation is scheduled when the peripheral transfer request is asserted. Destination Peripheral: Slave device, memory mapped on the inte rconnection network, to which the XDMAC writes. A write data operation is scheduled when the peripheral transfer request is asserted. Channel: The data movement between source and destination creates a logical channel. Transfer Type: The transfer is hardware synchronized wh en it is paced by the peripheral hardware request, otherwise the transfer is self-triggered (memory to memory transfer).

35.5.2 Transfer Hierarchy Diagram

XDMAC Master Transfer : The Master Transfer is composed of a linked list of blocks. The channel address, control and configuration registers can be modified at the inter block boundary. The descriptor structure modifies the channel registers conditionally. Interrupts can be generat ed on a per block basis or when the end of linked list event occurs. XDMAC Block : An XDMAC block is composed of a pr ogrammable number of microblocks. The channel configuration registers remain unchanged at the inter microblock boundary. The source and destination addresses are conditionally updated with a programmable signed number. XDMAC Microblock: The microblock is composed of a programmable number of data. The channel configuration registers remain unchanged at the data boundary. The data address may be fixed (a FIFO location, a peripheral transmit or receive register), incrementing (a memory mapped area) by a programmable signed number. XDMAC Burst and Incomplete Burst : In order to improve the overall performance when accessing dynamic external memory, burst access is mandatory. Each data of the microblock is considered as a part of a memory burst. The programmable burst value indicates the largest memory burst allowed on a per channel basis. When the microblock length is not an integral multiple of the burst size, an incomplete burst is performed to read or write the last trailing bytes. XDMAC Chunk and In complete Chunk : When a peripheral synchronized transfer is activated, the microblock splits into a number of data chunks. The chunk size is programmable. The larger the chunk is, the better the performance is. When the transfer size is not a multiple of the chunk size, the last chunk may be incomplete.

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 484

35.5.3 Peripheral Synchronized Transfer

A peripheral hardware request interface is used to control the pace of the chunk transfer. When a peripheral is ready to transmit or receive a chunk of data, it asserts its request line and the DMA Controller transfers a data to or from the memory to the peripheral.

35.5.3.1 Software Triggered Synchronized Transfer

The Peripheral hardware request can be software co ntrolled using the SWREQ fi eld of the XDMAC Global Channel Software Request Register (XDMAC_GSWR). The peripheral synchronized transfer is paced using a processor write access in the XDMAC_GSWR. Each bit of th at register triggers a transfer request. The XDMAC Global Channel Software Request Status Register (XDMAC_GSWS) indicates the status of the request; when set, the request is still pending.

35.5.4 XDMAC Transfer Software Operation

35.5.4.1 Single Block With Single Microblock Transfer

1. Read the XDMAC Global Channel Status Register (XDMAC_GS) to choose a free channel. 2. Clear the pending Interrupt Status bit(s) by reading the chosen XDMAC Channel x Interrupt Status Register (XDMAC_CISx). 3. Write the XDMAC Channel x Source Address Register (XDMAC_CSAx) for channel x. 4. Write the XDMAC Channel x Destination Address Register (XDMAC_CDAx) for channel x. 5. Program field UBLEN in the XDMAC Channel x Micr oblock Control Register (XDMAC_CUBCx) with the number of data. 6. Program the XDMAC Channel x Conf iguration Register (XDMAC_CCx): a. Clear XDMAC_CCx.TYPE for a memory to me mory transfer, otherwise set this bit. b. Program XDMAC_CCx.MBSIZE to the memory burst size used. c. Program XDMAC_CCx.SAM/DAM to the memory addressing scheme. d. Program XDMAC_CCx.SYNC to select the peripheral transfer direction. e. Program XDMAC_CCx.CSIZE to configure the channel chunk size (only relevant for peripheral syn- chronized transfer). f. Program XDMAC_CCx.DWIDTH to co nfigure the transfer data width. g. Program XDMAC_CCx.SIF, XDMAC_CCx.DIF to conf igure the master interface used to read data and write data respectively. h. Program XDMAC_CCx.PERID to select the active hardware request line (only relevant for a periph- eral synchronized transfer). i. Set XDMAC_CCx.SWREQ to use software reques t (only relevant for a peripheral synchronized transfer). 7. Clear the following five registers: XDMAC Channel x Next Descriptor Control Register (XDMAC_CNDCx) XDMAC Channel x Block Control Register (XDMAC_CBCx) XDMAC Channel x Data Stride Memory Set Pattern Register (XDMAC_CDS_MSPx) XDMAC Channel x Source Microblock Stride Register (XDMAC_CSUSx) XDMAC Channel x Destination Microblock Stride Register (XDMAC_CDUSx) This respectively indicates that the linked list is disabled, there is only one block and striding is disabled. 8. Enable the Microblock interrupt by writing a 1 to bit BIE in the XDMAC Channel x Interrupt Enable Register (XDMAC_CIEx), enable the Channel x Interrupt Enable bit by writing a 1 to bit IEx in the XDMAC Global Interrupt Enable Register (XDMAC_GIE). 9. Enable channel x by writing a 1 to bit ENx in the XDMAC Global Channel Enable Register (XDMAC_GE). XDMAC_GS.STx (XDMAC Channel x Status bit) is set by hardware.

485SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 10. Once completed, the DMA channel sets XDMAC_CISx.BIS (End of Block Interrupt Status bit) and generates an interrupt. XDMAC_GS.STx is cleared by hardware. The software can either wait for an interrupt or poll the channel status bit.

35.5.4.2 Single Block Transfer With Multiple Microblock

1. Read the XDMAC_GS register to choose a free channel. 2. Clear the pending Interrupt Status bit by reading the chosen XDMAC_CISx register. 3. Write the XDMAC_CSAx register for channel x. 4. Write the XDMAC_CDAx register for channel x. 5. Program XDMAC_CUBCx.UBLEN with the number of data. 6. Program XDMAC_CCx register (see single block transfer configuration). 7. Program XDMAC_CBCx.BLEN with the number of microblocks of data. 8. Clear the following four registers: XDMAC_CNDCx XDMAC_CDS_MSPx XDMAC_CSUSx XDMAC_CDUSx This respectively indicates that the linked list is disabled and striding is disabled. 9. Enable the Block interrupt by writing a 1 to XDMAC_ CIEx.BIE, enable the Channel x Interrupt Enable bit by writing a 1 to XDMAC_GIEx.IEx. 11. Once completed, the DMA channel sets XDMAC_CISx.BIS (End of Block Interrupt Status bit) and generates an interrupt. XDMAC_GS.STx is cleared by hardware. The software can either wait for an interrupt or poll the channel status bit.

35.5.4.3 Master Transfer

1. Read the XDMAC_GS register to choose a free channel. 2. Clear the pending Interrupt Status bit by reading the chosen XDMAC_CISx register. 3. Build a linked list of transf er descriptors in memory. The descriptor view is programmable on a per descriptor basis. The linked list items structure must be word aligned. MBR_UBC.NDE must be configured to 0 in the last descriptor to terminate the list. 4. Program field NDA in the XDMAC Channel x Next De scriptor Address Register (XDMAC_CNDAx) with the first descriptor address and bit XDMAC_CNDAx.NDAIF with the master interface identifier. 5. Program the XDMAC_CNDCx register: a. Set XDMAC_CNDCx.NDE to enable the descriptor fetch. b. Set XDMAC_CNDCx.NDSUP to updat e the source address at the descriptor fetch time, otherwise clear this bit. c. Set XDMAC_CNDCx.NDDUP to update the destinatio n address at the descriptor fetch time, other- wise clear this bit. d. Program XDMAC_CNDCx.NDVIEW to define the length of the first descriptor. 6. Enable the End of Linked List interr upt by writing a 1 to XDMAC_CIEx.LIE. 8. Once completed, the DMA channel sets XDMAC_CISx.BIS (End of Block Interrupt Status bit) and generates an interrupt. XDMAC_GS.STx is cleared by hardware. The software can either wait for an interrupt or poll the channel status bit.

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 486

35.5.4.4 Disabling A Channel Before Transfer Completion

Under normal operation, the software enables a channel by writing a 1 to XDMA C_GE.ENx (Global Channel x Enable Register bit), then the hardware disables a channel on transfer completion by clearing bit XDMAC_GS.STx. To disable a channel, write a 1 to bit XDMAC_GD.DIx and poll the XDMAC_GS register.

487SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

35.6 Linked List Descriptor Operation

35.6.1 Linked List Descriptor View

35.6.1.1 Channel Next Descriptor View 0–3 Structures

Table 35-2. Channel Next Descriptor View 0–3 Structures Channel Next Descriptor Offset Structure member Name View 0 Structure DSCR_ADDR+0x00 Next Descriptor Address Member MBR_NDA DSCR_ADDR+0x04 Microblock Control Member MBR_UBC DSCR_ADDR+0x08 Transfer Address Member MBR_TA View 1 Structure DSCR_ADDR+0x00 Next Descriptor Address Member MBR_NDA DSCR_ADDR+0x04 Microblock Control Member MBR_UBC DSCR_ADDR+0x08 Source Address Member MBR_SA DSCR_ADDR+0x0C Destination Address Member MBR_DA View 2 Structure DSCR_ADDR+0x00 Next Descriptor Address Member MBR_NDA DSCR_ADDR+0x04 Microblock Control Member MBR_UBC DSCR_ADDR+0x08 Source Address Member MBR_SA DSCR_ADDR+0x0C Destination Address Member MBR_DA DSCR_ADDR+0x10 Configuration Register MBR_CFG View 3 Structure DSCR_ADDR+0x00 Next Descriptor Address Member MBR_NDA DSCR_ADDR+0x04 Microblock Control Member MBR_UBC DSCR_ADDR+0x08 Source Address Member MBR_SA DSCR_ADDR+0x0C Destination Address Member MBR_DA DSCR_ADDR+0x10 Configuration Member MBR_CFG DSCR_ADDR+0x14 Block Control Member MBR_BC DSCR_ADDR+0x18 Data Stride Member MBR_DS DSCR_ADDR+0x1C Source Microblock Stride Member MBR_SUS DSCR_ADDR+0x20 Destination Microblock Stride Member MBR_DUS

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 488

35.6.2 Descriptor Structure Members Description

35.6.2.1 Descriptor Structure Microblock Control Member

Name: MBR_UBC Access: Read-only

• UBLEN: Microblock Length This field indicates the number of data in the microblock. The microblock contains UBLEN data.
• NDE: Next Descriptor Enable 0: Descriptor fetch is disabled. 1: Descriptor fetch is enabled.
• NSEN: Next Descriptor Source Update 0: Source parameters remain unchanged. 1: Source parameters are updated when the descriptor is retrieved.
• NDEN: Next Descript or Destination Update 0: Destination parameters remain unchanged. 1: Destination parameters are updated when the descriptor is retrieved.
• NVIEW: Next Descriptor View 31 30 29 28 27 26 25 24 – – – NVIEW NDEN NSEN NDE 23 22 21 20 19 18 17 16 UBLEN 15 14 13 12 11 10 9 8 UBLEN 76543210 UBLEN Value Name Description

0 NDV0 Next Descriptor View 0

1 NDV1 Next Descriptor View 1

2 NDV2 Next Descriptor View 2

3 NDV3 Next Descriptor View 3

489SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

35.7 XDMAC Maintenance Software Operations

35.7.1 Disabling a Channel

A disable channel request occurs when a write operation is performed in the XDMAC_GD register. If the channel is source peripheral synchronized (bit XDMAC_CCx.TYPE is set and bit XDMAC_CCx.DSYNC is cleared), then pending bytes (bytes located in the FIFO) are written to memory and bit XDMAC_CISx.DIS is set. If the channel is not source peripheral synchronized, the current channel transaction (read or write) is terminated and XDMAC_CISx.DIS is set. XDMAC_GS.STx is cleared by hardware when the current transfer is completed. The channel is no longer active and can be reused.

35.7.2 Suspending a Channel

A read request suspend command is issued by writing to the XDMAC_GRS register. A write request suspend command is issued by writing to the XDMAC_GWS register . A read write suspend channel is issued by writing to the XDMAC_GRWS register. These commands have an immediate effect on the scheduling of both read and write transactions. If a transaction is already in progress, it is terminated normally. The channel is not disabled. The FIFO content is preserved. The scheduling mechanism can resume normally, clearing the bit in the same registers. Pending bytes located in the FIFO are not written out to memory. The write suspend command does not affect read request operations, i.e., read operations can still occur until the FIFO is full.

35.7.3 Flushing a Channel

A FIFO flush command is issued writi ng to the XDMAC_SWF register. The co ntent of the FIFO is written to memory. XDMAC_CISx.FIS (End of Flush Interrupt Status bit) is set when the last byte is successfully transferred to memory. The channel is not disabled. The flush operat ion is not blocking, meaning that read operation can be scheduled during the flush write operation. The flush opera tion is only relevant for peripheral to memory transfer where pending peripheral bytes are buffered into the channel FIFO.

35.7.4 Maintenance Operation Priority

35.7.4.1 Disable Operation Priority

 When a disable request occurs on a suspended channel, the XDMAC_GWS.WSx (Channel x Write Suspend bit) is cleared. If the transfer is source peripheral synchronized, the pending bytes are drained to memory. The bit XDMAC_CISx.DIS is set.  When a disable request follows a flush request, if the flush last transaction is not yet scheduled, the flush request is discarded and the disable procedure is applied. The bit XDMAC_CISx.FIS is not set. Bit XDMAC_CISx.DIS will be set when the disable request is completed. If the flush request transaction is already scheduled, the XDMAC_CISx.FIS will be set. XDMAC_CISx.DIS will also be set when the disable request is completed.

35.7.4.2 Flush Operation Priority

 When a flush request occurs on a suspended channel, if there are pending bytes in the FIFO, they are written out to memory, XDMAC_CISx.FIS is set. If the FIFO is empty, XDMAC_CISx.FIS is also set.  If the flush operation is performed after a disable request, the flush command is ignored. XDMAC_CISx.FIS is not set.

35.7.4.3 Suspend Operation Priority

If the suspend operation is performed after a disable request, the write suspend operation is ignored.

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 490

35.8 XDMAC Software Requirements

 Write operations to channel registers are not be performed in an active channel after the channel is enabled. If any channel parameters must be reprogrammed, this can only be done after disabling the XDMAC channel.  XDMAC_CSAx and XDMAC_CDAx channel registers are to be programmed with a byte, half-word or word aligned address depending on the Channel x Data Width field (DWIDTH) of the XDMAC Channel x Configuration Register.

491SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

35.9 Extensible DMA Controller (XDMAC) User Interface

Table 35-3. Register Mapping Offset Register Name Access Reset 0x00 Global Type Register XDMAC_GTYPE Read-only 0x00000000 0x04 Global Configuration Register XDMAC_GCFG Read-only 0x00000000 0x08 Global Weighted Arbiter Configuration Register XDMAC_GWAC Read-only 0x00000000 0x0C Global Interrupt Enable Register XDMAC_GIE Write-only – 0x10 Global Interrupt Disable Register XDMAC_GID Write-only – 0x14 Global Interrupt Mask Register XDMAC_GIM Read-only 0x00000000 0x18 Global Interrupt Status Register XDMAC_GIS Read-only 0x00000000 0x1C Global Channel Enable Register XDMAC_GE Write-only – 0x20 Global Channel Disable Register XDMAC_GD Write-only – 0x24 Global Channel Status Register XDMAC_GS Read-only 0x00000000 0x28 Global Channel Read Suspend Register XDMAC_GRS Read/Write 0x00000000 0x2C Global Channel Write Suspend Register XDMAC_GWS Read/Write 0x00000000 0x30 Global Channel Read Write Suspend Register XDMAC_GRWS Write-only – 0x34 Global Channel Read Write Resume Register XDMAC_GRWR Write-only – 0x38 Global Channel Software Request Register XDMAC_GSWR Write-only – 0x3C Global Channel Software Request Status Register XDMAC_GSWS Read-only 0x00000000 0x40 Global Channel Software Flush Request Register XDMAC_GSWF Write-only – 0x44–0x4C Reserved – – – 0x50+chid*0x40 Channel Interrupt Enable Register XDMAC_CIE Write-only – 0x54+chid*0x40 Channel Interrupt Disable Register XDMAC_CID Write-only – 0x58+chid*0x40 Channel Interrupt Mask Register XDMAC_CIM Read-only – 0x5C+chid*0x40 Channel Interrupt Status Register XDMAC_CIS Read-only 0x00000000 0x60+chid*0x40 Channel Source Address Register XDMAC_CSA Read/Write 0x00000000 0x64+chid*0x40 Channel Destination Address Register XDMAC_CDA Read/Write 0x00000000 0x68+chid*0x40 Channel Next Descriptor Address Register XDMAC_CNDA Read/Write 0x00000000 0x6C+chid*0x40 Channel Next Descriptor Control Register XDMAC_CNDC Read/Write 0x00000000 0x70+chid*0x40 Channel Microblock Control Register XDMAC_CUBC Read/Write 0x00000000 0x74+chid*0x40 Channel Block Control Register XDMAC_CBC Read/Write 0x00000000 0x78+chid*0x40 Channel Configuration Register XDMAC_CC Read/Write 0x00000000 0x7C+chid*0x40 Channel Data Stride Memory Set Pattern XDMAC_CDS_MSP Read/Write 0x00000000 0x80+chid*0x40 Channel Source Microblock Stride XDMAC_CSUS Read/Write 0x00000000 0x84+chid*0x40 Channel Destination Microblock Stride XDMAC_CDUS Read/Write 0x00000000 0x88+chid*0x40 Reserved – – – 0x8C+chid*0x40 Reserved – – – 0xFEC–0xFFC Reserved – – –

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 492

35.9.1 XDMAC Global Type Register

Name: XDMAC_GTYPE Address: 0x40078000 Access: Read-only

• NB_CH: Number of Channels Minus One
• FIFO_SZ: Number of Bytes
• NB_REQ: Number of Peripheral Requests Minus One 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 –N B_REQ 15 14 13 12 11 10 9 8 FIFO_SZ 76543210 FIFO_SZ NB_CH

493SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

35.9.2 XDMAC Global Configuration Register

Name: XDMAC_GCFG Address: 0x40078004 Access: Read-only

• CGDISREG: Configuration Registers Clock Gating Disable 0: The automatic clock gating is enabled for the configuration registers. 1: The automatic clock gating is disabled for the configuration registers.
• CGDISPIPE: Pipeline Clock Gating Disable 0: The automatic clock gating is enabled for the main pipeline. 1: The automatic clock gating is disabled for the main pipeline.
• CGDISFIFO: FIFO Clock Gating Disable 0: The automatic clock gating is enabled for the main FIFO. 1: The automatic clock gating is disabled for the main FIFO.
• CGDISIF: Bus Interface Clock Gating Disable 0: The automatic clock gating is enabled for the system bus interface. 1: The automatic clock gating is disabled for the system bus interface.
• BXKBEN: Boundary X Kilobyte Enable 0: The 1 Kbyte boundary is used. 1: The controller does not meet the AHB specification. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 –––– CGDISIF CGDI SFIFO CGDISPIPE CGDISREG

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 494

35.9.3 XDMAC Global Weighted Arbiter Configuration Register

Name: XDMAC_GWAC Address: 0x40078008 Access: Read-only

• PW0: Pool Weight 0 This field indicates the weight of the pool 0, in the arbitration scheme of the XDMA scheduler.
• PW1: Pool Weight 1 This field indicates the weight of the pool 1, in the arbitration scheme of the XDMA scheduler.
• PW2: Pool Weight 2 This field indicates the weight of the pool 2, in the arbitration scheme of the XDMA scheduler.
• PW3: Pool Weight 3 This field indicates the weight of the pool 3, in the arbitration scheme of the XDMA scheduler. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 PW3 PW2 76543210 PW1 PW0

495SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

35.9.4 XDMAC Global Interrupt Enable Register

Name: XDMAC_GIE Address: 0x4007800C Access: Write-only

• IEx: XDMAC Channel x Interrupt Enable Bit 0: This bit has no effect. The channel x Interrupt Mask bit is not modified. 1: The corresponding mask bit is set. The XDMAC Channel x Interrupt Status Register can generate an interrupt. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 IE23 IE22 IE21 IE20 IE19 IE18 IE17 IE16 15 14 13 12 11 10 9 8 IE15 IE14 IE13 IE12 IE11 IE10 IE9 IE8 76543210 IE7 IE6 IE5 IE4 IE3 IE2 IE1 IE0

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 496

35.9.5 XDMAC Global Interrupt Disable Register

Name: XDMAC_GID Address: 0x40078010 Access: Write-only

• IDx: XDMAC Channel x Interrupt Disable Bit 0: This bit has no effect. The channel x Interrupt Mask bit is not modified. 1: The corresponding mask bit is reset. The Channel x interrupt status register interrupt is masked. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ID23 ID22 ID21 ID20 ID19 ID18 ID17 ID16 15 14 13 12 11 10 9 8 ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8 76543210 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0

497SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

35.9.6 XDMAC Global Interrupt Mask Register

Name: XDMAC_GIM Address: 0x40078014 Access: Read-only

• IMx: XDMAC Channel x Interrupt Mask Bit 0: This bit indicates that the channel x interrupt source is masked. The interrupt line is not raised. 1: This bit indicates that the channel x interrupt source is unmasked. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 IM23 IM22 IM21 IM20 IM19 IM18 IM17 IM16 15 14 13 12 11 10 9 8 IM15 IM14 IM13 IM12 IM11 IM10 IM9 IM8 76543210 IM7 IM6 IM5 IM4 IM3 IM2 IM1 IM0

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 498

35.9.7 XDMAC Global Interrupt Status Register

Name: XDMAC_GIS Address: 0x40078018 Access: Read-only

• ISx: XDMAC Channel x Interrupt Status Bit 0: This bit indicates that either the interrupt source is masked at the channel level or no interrupt is pending for channel x. 1: This bit indicates that an interrupt is pending for the channel x. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 IS23 IS22 IS21 IS20 IS19 IS18 IS17 IS16 15 14 13 12 11 10 9 8 IS15 IS14 IS13 IS12 IS11 IS10 IS9 IS8 76543210 IS7 IS6 IS5 IS4 IS3 IS2 IS1 IS0

499SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

35.9.8 XDMAC Global Channel Enable Register

Name: XDMAC_GE Address: 0x4007801C Access: Write-only

• ENx: XDMAC Channel x Enable Bit 0: This bit has no effect. 1: Enables channel x. This operation is permitted if the channel x status bit was read as 0. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 EN23 EN22 EN21 EN20 EN19 EN18 EN17 EN16 15 14 13 12 11 10 9 8 EN15 EN14 EN13 EN12 EN11 EN10 EN9 EN8 76543210 EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 500

35.9.9 XDMAC Global Channel Disable Register

Name: XDMAC_GD Address: 0x40078020 Access: Write-only

• DIx: XDMAC Channel x Disable Bit 0: This bit has no effect. 1: Disables channel x. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DI23 DI22 DI21 DI20 DI19 DI18 DI17 DI16 15 14 13 12 11 10 9 8 DI15 DI14 DI13 DI12 DI11 DI10 DI9 DI8 76543210 DI7D I6D I5D I4D I3D I2D I1D I0

501SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

35.9.10 XDMAC Global Channel Status Register

Name: XDMAC_GS Address: 0x40078024 Access: Read-only

• STx: XDMAC Channel x Status Bit 0: This bit indicates that the channel x is disabled. 1: This bit indicates that the channel x is enabled. If a channel disable request is issued, this bit remains asserted until pending transaction is completed. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ST23 ST22 ST21 ST20 ST19 ST18 ST17 ST16 15 14 13 12 11 10 9 8 ST15 ST14 ST13 ST12 ST11 ST10 ST9 ST8 76543210 ST7 ST6 ST5 ST4 ST3 ST2 ST1 ST0

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 502

35.9.11 XDMAC Global Channel Read Suspend Register

Name: XDMAC_GRS Address: 0x40078028 Access: Read/Write

• RSx: XDMAC Channel x Read Suspend Bit 0: The read channel is not suspended. 1: The source requests for channel x are no longer serviced by the system scheduler. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RS23 RS22 RS21 RS20 RS19 RS18 RS17 RS16 15 14 13 12 11 10 9 8 RS15 RS14 RS13 RS12 RS11 RS10 RS9 RS8 76543210 RS7 RS6 RS5 RS4 RS3 RS2 RS1 RS0

503SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

35.9.12 XDMAC Global Channel Write Suspend Register

Name: XDMAC_GWS Address: 0x4007802C Access: Read/Write

• WSx: XDMAC Channel x Write Suspend Bit 0: The write channel is not suspended. 1: Destination requests are no longer routed to the scheduler. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WS23 WS22 WS21 WS20 WS19 WS18 WS17 WS16 15 14 13 12 11 10 9 8 WS15 WS14 WS13 WS12 WS11 WS10 WS9 WS8 76543210 WS7 WS6 WS5 WS4 WS3 WS2 WS1 WS0

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 504

35.9.13 XDMAC Global Channel Read Write Suspend Register

Name: XDMAC_GRWS Address: 0x40078030 Access: Write-only

• RWSx: XDMAC Channel x Read Write Suspend Bit 0: No effect. 1: Read and Write requests are suspended. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RWS23 RWS22 RWS21 RWS20 RWS19 RWS18 RWS17 RWS16 15 14 13 12 11 10 9 8 RWS15 RWS14 RWS13 RWS12 RWS11 RWS10 RWS9 RWS8 76543210 RWS7 RWS6 RWS5 RWS4 RWS3 RWS2 RWS1 RWS0

505SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

35.9.14 XDMAC Global Channel Read Write Resume Register

Name: XDMAC_GRWR Address: 0x40078034 Access: Write-only

• RWRx: XDMAC Channel x Read Write Resume Bit 0: No effect. 1: Read and Write requests are serviced. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RWR23 RWR22 RWR21 RWR20 RWR19 RWR18 RWR17 RWR16 15 14 13 12 11 10 9 8 RWR15 RWR14 RWR13 RWR12 RWR11 RWR10 RWR9 RWR8 76543210 RWR7 RWR6 RWR5 RWR4 RWR3 RWR2 RWR1 RWR0

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 506

35.9.15 XDMAC Global Channel Software Request Register

Name: XDMAC_GSWR Address: 0x40078038 Access: Write-only

• SWREQx: XDMAC Channel x Software Request Bit 0: No effect. 1: Requests a DMA transfer for channel x. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SWREQ23 SWREQ22 SWREQ21 SWREQ20 SWREQ19 SWREQ18 SWREQ17 SWREQ16 15 14 13 12 11 10 9 8 SWREQ15 SWREQ14 SWREQ13 SWREQ12 SWREQ11 SWREQ10 SWREQ9 SWREQ8 76543210 SWREQ7 SWREQ6 SWREQ5 SWREQ4 SWREQ3 SWREQ2 SWREQ1 SWREQ0

507SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

35.9.16 XDMAC Global Channel Software Request Status Register

Name: XDMAC_GSWS Address: 0x4007803C Access: Read-only

• SWRSx: XDMAC Channel x Soft ware Request Status Bit 0: Channel x Source request is serviced. 1: Channel x Source request is pending. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SWRS23 SWRS22 SWRS21 SWRS20 SWRS19 SWRS18 SWRS17 SWRS16 15 14 13 12 11 10 9 8 SWRS15 SWRS14 SWRS13 SWRS12 SWRS11 SWRS10 SWRS9 SWRS8 76543210 SWRS7 SWRS6 SWRS5 SWRS4 SWRS3 SWRS2 SWRS1 SWRS0

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 508

35.9.17 XDMAC Global Channel Software Flush Request Register

Name: XDMAC_GSWF Address: 0x40078040 Access: Write-only

• SWFx: XDMAC Channel x Software Flush Request Bit 0: No effect. 1: Requests a DMA transfer flush for channel x. This bit is only relevant when the transfer is source peripheral synchronized. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SWF23 SWF22 SWF21 SWF20 SWF19 SWF18 SWF17 SWF16 15 14 13 12 11 10 9 8 SWF15 SWF14 SWF13 SWF12 SWF11 SWF10 SWF9 SWF8 76543210 SWF7 SWF6 SWF5 SWF4 SWF3 SWF2 SWF1 SWF0

509SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 35.9.18 XDMAC Channel x [x = 0..2 3] Interrupt Enable Register Name: XDMAC_CIEx [x = 0..23] Address: 0x40078050 [0], 0x40078090 [1], 0x400780D0 [2], 0x40078110 [3], 0x40078150 [4], 0x40078190 [5], 0x400781D0 [6], 0x40078210 [7], 0x40078250 [8], 0x40078290 [9], 0x400782D0 [10], 0x40078310 [11], 0x40078350 [12], 0x40078390 [13], 0x400783D0 [14], 0x40078410 [15], 0x40078450 [16], 0x40078490 [17], 0x400784D0 [18], 0x40078510 [19], 0x40078550 [20], 0x40078590 [21], 0x400785D0 [22], 0x40078610 [23] Access: Write-only

• BIE: End of Block Interrupt Enable Bit 0: No effect. 1: Enables end of block interrupt.
• LIE: End of Linked List Interrupt Enable Bit 0: No effect. 1: Enables end of linked list interrupt.
• DIE: End of Disable Interrupt Enable Bit 0: No effect. 1: Enables end of disable interrupt.
• FIE: End of Flush Interrupt Enable Bit 0: No effect. 1: Enables end of flush interrupt.
• RBIE: Read Bus Error Interrupt Enable Bit 0: No effect. 1: Enables read bus error interrupt.
• WBIE: Write Bus Error Interrupt Enable Bit 0: No effect. 1: Enables write bus error interrupt.
• ROIE: Request Overflow Error Interrupt Enable Bit 0: No effect. 1: Enables Request Overflow Error Interrupt. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 – ROIE WBIE RBIE FIE DIE LIE BIE

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 510 35.9.19 XDMAC Channel x [x = 0..2 3] Interrupt Disable Register Name: XDMAC_CIDx [x = 0..23] Address: 0x40078054 [0], 0x40078094 [1], 0x400780D4 [2], 0x40078114 [3], 0x40078154 [4], 0x40078194 [5], 0x400781D4 [6], 0x40078214 [7], 0x40078254 [8], 0x40078294 [9], 0x400782D4 [10], 0x40078314 [11], 0x40078354 [12], 0x40078394 [13], 0x400783D4 [14], 0x40078414 [15], 0x40078454 [16], 0x40078494 [17], 0x400784D4 [18], 0x40078514 [19], 0x40078554 [20], 0x40078594 [21], 0x400785D4 [22], 0x40078614 [23] Access: Write-only

• BID: End of Block In terrupt Disable Bit 0: No effect. 1: Disables end of block interrupt.
• LID: End of Linked List Interrupt Disable Bit 0: No effect. 1: Disables end of linked list interrupt.
• DID: End of Disable Interrupt Disable Bit 0: No effect. 1: Disables end of disable interrupt.
• FID: End of Flush Interrupt Disable Bit 0: No effect. 1: Disables end of flush interrupt.
• RBEID: Read Bus Error Interrupt Disable Bit 0: No effect. 1: Disables bus error interrupt.
• WBEID: Write Bus Error Interrupt Disable Bit 0: No effect. 1: Disables bus error interrupt.
• ROID: Request Overflow Error Interrupt Disable Bit 0: No effect. 1: Disables Request Overflow Error Interrupt. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 – ROID WBEID RBEID FID DID LID BID

511SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 35.9.20 XDMAC Channel x [x = 0..23] Interrupt Mask Register Name: XDMAC_CIMx [x = 0..23] Address: 0x40078058 [0], 0x40078098 [1], 0x400780D8 [2], 0x40078118 [3], 0x40078158 [4], 0x40078198 [5], 0x400781D8 [6], 0x40078218 [7], 0x40078258 [8], 0x40078298 [9], 0x400782D8 [10], 0x40078318 [11], 0x40078358 [12], 0x40078398 [13], 0x400783D8 [14], 0x40078418 [15], 0x40078458 [16], 0x40078498 [17], 0x400784D8 [18], 0x40078518 [19], 0x40078558 [20], 0x40078598 [21], 0x400785D8 [22], 0x40078618 [23] Access: Read-only

• BIM: End of Block Interrupt Mask Bit 0: Block interrupt is masked. 1: Block interrupt is activated.
• LIM: End of Linked List Interrupt Mask Bit 0: End of linked list interrupt is masked. 1: End of linked list interrupt is activated.
• DIM: End of Disable Interrupt Mask Bit 0: End of disable interrupt is masked. 1: End of disable interrupt is activated.
• FIM: End of Flush Interrupt Mask Bit 0: End of flush interrupt is masked. 1: End of flush interrupt is activated.
• RBEIM: Read Bus Error Interrupt Mask Bit 0: Bus error interrupt is masked. 1: Bus error interrupt is activated.
• WBEIM: Write Bus Erro r Interrupt Mask Bit 0: Bus error interrupt is masked. 1: Bus error interrupt is activated.
• ROIM: Request Overflow Error Interrupt Mask Bit 0: Request Overflow interrupt is masked. 1: Request Overflow interrupt is activated. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 – ROIM WBEIM RBEIM FIM DIM LIM BIM

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 512 35.9.21 XDMAC Channel x [x = 0..2 3] Interrupt Status Register Name: XDMAC_CISx [x = 0..23] Address: 0x4007805C [0], 0x4007809C [1], 0x400780DC [2], 0x4007811C [3], 0x4007815C [4], 0x4007819C [5], 0x400781DC [6], 0x4007821C [7], 0x4007825C [8], 0x4007829C [9], 0x400782DC [10], 0x4007831C [11], 0x4007835C [12], 0x4007839C [13], 0x400783DC [14], 0x4007841C [15], 0x4007845C [16], 0x4007849C [17], 0x400784DC [18], 0x4007851C [19], 0x4007855C [20], 0x4007859C [21], 0x400785DC [22], 0x4007861C [23] Access: Read-only

• BIS: End of Block Interrupt Status Bit 0: End of block interrupt has not occurred. 1: End of block interrupt has occurred since the last read of the status register.
• LIS: End of Linked List Interrupt Status Bit 0: End of linked list condition has not occurred. 1: End of linked list condition has occurred since the last read of the status register.
• DIS: End of Disable Interrupt Status Bit 0: End of disable condition has not occurred. 1: End of disable condition has occurred since the last read of the status register.
• FIS: End of Flush Interrupt Status Bit 0: End of flush condition has not occurred. 1: End of flush condition has occurred since the last read of the status register.
• RBEIS: Read Bus Error Interrupt Status Bit 0: Read bus error condition has not occurred. 1: At least one bus error has been detected in a read access since the last read of the status register.
• WBEIS: Write Bus Error Interrupt Status Bit 0: Write bus error condition has not occurred. 1: At least one bus error has been detected in a write access since the last read of the status register.
• ROIS: Request Overflow Error Interrupt Status Bit 0: Overflow condition has not occurred. 1: Overflow condition has occurred at least once. (This information is only relevant for peripheral synchronized transfers.) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 – ROIS WBEIS RBEIS FIS DIS LIS BIS

513SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 35.9.22 XDMAC Channel x [x = 0..23] Source Address Register Name: XDMAC_CSAx [x = 0..23] Address: 0x40078060 [0], 0x400780A0 [1], 0x400780E0 [2], 0x40078120 [3], 0x40078160 [4], 0x400781A0 [5], 0x400781E0 [6], 0x40078220 [7], 0x40078260 [8], 0x400782A0 [9], 0x400782E0 [10], 0x40078320 [11], 0x40078360 [12], 0x400783A0 [13], 0x400783E0 [14], 0x40078420 [15], 0x40078460 [16], 0x400784A0 [17], 0x400784E0 [18], 0x40078520 [19], 0x40078560 [20], 0x400785A0 [21], 0x400785E0 [22], 0x40078620 [23] Access: Read/Write

• SA: Channel x Source Address Program this register with the source address of the DMA transfer. A configuration error is generated when this address is not aligned with the transfer data size. 31 30 29 28 27 26 25 24 SA 23 22 21 20 19 18 17 16 SA 15 14 13 12 11 10 9 8 SA 76543210 SA

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 514 35.9.23 XDMAC Channel x [x = 0..23] Destination Address Register Name: XDMAC_CDAx [x = 0..23] Address: 0x40078064 [0], 0x400780A4 [1], 0x400780E4 [2], 0x40078124 [3], 0x40078164 [4], 0x400781A4 [5], 0x400781E4 [6], 0x40078224 [7], 0x40078264 [8], 0x400782A4 [9], 0x400782E4 [10], 0x40078324 [11], 0x40078364 [12], 0x400783A4 [13], 0x400783E4 [14], 0x40078424 [15], 0x40078464 [16], 0x400784A4 [17], 0x400784E4 [18], 0x40078524 [19], 0x40078564 [20], 0x400785A4 [21], 0x400785E4 [22], 0x40078624 [23] Access: Read/Write

• DA: Channel x Destination Address Program this register with the destination address of the DMA transfer. A configuration error is generated when this address is not aligned with the transfer data size. 31 30 29 28 27 26 25 24 DA 23 22 21 20 19 18 17 16 DA 15 14 13 12 11 10 9 8 DA 76543210 DA

515SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 35.9.24 XDMAC Channel x [x = 0..23] Next Descriptor Address Register Name: XDMAC_CNDAx [x = 0..23] Address: 0x40078068 [0], 0x400780A8 [1], 0x400780E8 [2], 0x40078128 [3], 0x40078168 [4], 0x400781A8 [5], 0x400781E8 [6], 0x40078228 [7], 0x40078268 [8], 0x400782A8 [9], 0x400782E8 [10], 0x40078328 [11], 0x40078368 [12], 0x400783A8 [13], 0x400783E8 [14], 0x40078428 [15], 0x40078468 [16], 0x400784A8 [17], 0x400784E8 [18], 0x40078528 [19], 0x40078568 [20], 0x400785A8 [21], 0x400785E8 [22], 0x40078628 [23] Access: Read/Write

• NDAIF: Channel x Next Descriptor Interface 0: The channel descriptor is retrieved through the system interface 0. 1: The channel descriptor is retrieved through the system interface 1.
• NDA: Channel x Next Descriptor Address The 30-bit width of the NDA field represents the next descriptor address range 31:2. The descriptor is word-aligned and the two least significant register bits 1:0 are ignored. 31 30 29 28 27 26 25 24 NDA 23 22 21 20 19 18 17 16 NDA 15 14 13 12 11 10 9 8 NDA 76543210 NDA – NDAIF

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 516 35.9.25 XDMAC Channel x [x = 0..23] Next Descriptor Control Register Name: XDMAC_CNDCx [x = 0..23] Address: 0x4007806C [0], 0x400780AC [1], 0x400780EC [2], 0x4007812C [3], 0x4007816C [4], 0x400781AC [5], 0x400781EC [6], 0x4007822C [7], 0x4007826C [8], 0x400782AC [9], 0x400782EC [10], 0x4007832C [11], 0x4007836C [12], 0x400783AC [13], 0x400783EC [14], 0x4007842C [15], 0x4007846C [16], 0x400784AC [17], 0x400784EC [18], 0x4007852C [19], 0x4007856C [20], 0x400785AC [21], 0x400785EC [22], 0x4007862C [23] Access: Read/Write

• NDE: Channel x Next Descriptor Enable 0 (DSCR_FETCH_DIS): Descriptor fetch is disabled. 1 (DSCR_FETCH_EN): Descriptor fetch is enabled.
• NDSUP: Channel x Next Descriptor Source Update 0 (SRC_PARAMS_UNCHANGED): Source parameters remain unchanged. 1 (SRC_PARAMS_UPDATED): Source parameters are updated when the descriptor is retrieved.
• NDDUP: Channel x Next Desc riptor Destination Update 0 (DST_PARAMS_UNCHANGED): Destination parameters remain unchanged. 1 (DST_PARAMS_UPDATED): Destination parameters are updated when the descriptor is retrieved.
• NDVIEW: Channel x Next Descriptor View 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 – – – NDVIEW NDDUP NDSUP NDE Value Name Description

517SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 35.9.26 XDMAC Channel x [x = 0..23] Microblock Control Register Name: XDMAC_CUBCx [x = 0..23] Address: 0x40078070 [0], 0x400780B0 [1], 0x400780F0 [2], 0x40078130 [3], 0x40078170 [4], 0x400781B0 [5], 0x400781F0 [6], 0x40078230 [7], 0x40078270 [8], 0x400782B0 [9], 0x400782F0 [10], 0x40078330 [11], 0x40078370 [12], 0x400783B0 [13], 0x400783F0 [14], 0x40078430 [15], 0x40078470 [16], 0x400784B0 [17], 0x400784F0 [18], 0x40078530 [19], 0x40078570 [20], 0x400785B0 [21], 0x400785F0 [22], 0x40078630 [23] Access: Read/Write

• UBLEN: Channel x Microblock Length This field indicates the number of data in the microblock. The microblock contains UBLEN data. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 UBLEN 15 14 13 12 11 10 9 8 UBLEN 76543210 UBLEN

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 518 35.9.27 XDMAC Channel x [x = 0..23] Block Control Register Name: XDMAC_CBCx [x = 0..23] Address: 0x40078074 [0], 0x400780B4 [1], 0x400780F4 [2], 0x40078134 [3], 0x40078174 [4], 0x400781B4 [5], 0x400781F4 [6], 0x40078234 [7], 0x40078274 [8], 0x400782B4 [9], 0x400782F4 [10], 0x40078334 [11], 0x40078374 [12], 0x400783B4 [13], 0x400783F4 [14], 0x40078434 [15], 0x40078474 [16], 0x400784B4 [17], 0x400784F4 [18], 0x40078534 [19], 0x40078574 [20], 0x400785B4 [21], 0x400785F4 [22], 0x40078634 [23] Access: Read/Write

• BLEN: Channel x Block Length The length of the block is (BLEN+1) microblocks. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 –––– BLEN 76543210 BLEN

519SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 35.9.28 XDMAC Channel x [x = 0..23] Configuration Register Name: XDMAC_CCx[x = 0..23] Address: 0x40078078 [0], 0x400780B8 [1], 0x400780F8 [2], 0x40078138 [3], 0x40078178 [4], 0x400781B8 [5], 0x400781F8 [6], 0x40078238 [7], 0x40078278 [8], 0x400782B8 [9], 0x400782F8 [10], 0x40078338 [11], 0x40078378 [12], 0x400783B8 [13], 0x400783F8 [14], 0x40078438 [15], 0x40078478 [16], 0x400784B8 [17], 0x400784F8 [18], 0x40078538 [19], 0x40078578 [20], 0x400785B8 [21], 0x400785F8 [22], 0x40078638 [23] Access: Read/Write

• TYPE: Channel x Transfer Type 0 (MEM_TRAN): Self triggered mode (Memory to Memory Transfer). 1 (PER_TRAN): Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer).
• MBSIZE: Channel x Memory Burst Size
• DSYNC: Channel x Synchronization 0 (PER2MEM): Peripheral to Memory transfer. 1 (MEM2PER): Memory to Peripheral transfer.
• SWREQ: Channel x Software Request Trigger 0 (HWR_CONNECTED): Hardware request line is connected to the peripheral request line. 1 (SWR_CONNECTED): Software request is connected to the peripheral request line.
• MEMSET: Channel x Fi ll Block of memory 0 (NORMAL_MODE): Memset is not activated. 1 (HW_MODE): Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8, 16 or 32 bits basis. 31 30 29 28 27 26 25 24 – PERID 23 22 21 20 19 18 17 16 WRIP RDIP INITD – DAM SAM 15 14 13 12 11 10 9 8 –D IF S IF D WIDTH CSIZE 76543210 MEMSET SWREQ – DSYNC – MBSIZE TYPE Value Name Description 0 SINGLE The memory burst size is set to one. 1 FOUR The memory burst size is set to four. 2 EIGHT The memory burst size is set to eight. 3 SIXTEEN The memory burst size is set to sixteen.

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 520

• CSIZE: Channel x Chunk Size
• DWIDTH: Channel x Data Width
• SIF: Channel x Source Interface Identifier 0 (AHB_IF0): The data is read through the system bus interface 0. 1 (AHB_IF1): The data is read through the system bus interface 1.
• DIF: Channel x Destination Interface Identifier 0 (AHB_IF0): The data is written through the system bus interface 0. 1 (AHB_IF1): The data is written though the system bus interface 1.
• SAM: Channel x Source Addressing Mode
• DAM: Channel x Destination Addressing Mode
• INITD: Channel Initialization Done (this bit is read-only) 0 (IN_PROGRESS): Channel initialization is in progress. 1 (TERMINATED): Channel initialization is completed. Value Name Description

0 CHK_1 1 data transferred

1 CHK_2 2 data transferred

2 CHK_4 4 data transferred

3 CHK_8 8 data transferred

4 CHK_16 16 data transferred

0 BYTE The data size is set to 8 bits

1 HALFWORD The data size is set to 16 bits

2 WORD The data size is set to 32 bits

0 FIXED_AM The address remains unchanged. 1 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 2 UBS_AM The microblock stride is added at the microblock boundary. 3 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. Value Name Description 0 FIXED_AM The address remains unchanged. 1 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 2 UBS_AM The microblock stride is added at the microblock boundary. 3 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

521SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

• RDIP: Read in Progress (this bit is read-only) 0 (DONE): No Active read transaction on the bus. 1 (IN_PROGRESS): A read transaction is in progress.
• WRIP: Write in Progress (this bit is read-only) 0 (DONE): No Active write transaction on the bus. 1 (IN_PROGRESS): A Write transaction is in progress.
• PERID: Channel x Peripheral Hard ware Request Line Identifier This field contains the peripheral hardware request line identifier. PERID refers to identifiers defined in Section 35.4 ”DMA Controller Peripheral Connections”.

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 522 35.9.29 XDMAC Channel x [x = 0..23] Data Stride Memory Set Pattern Register Name: XDMAC_CDS_MSPx [x = 0..23] Address: 0x4007807C [0], 0x400780BC [1], 0x400780FC [2], 0x4007813C [3], 0x4007817C [4], 0x400781BC [5], 0x400781FC [6], 0x4007823C [7], 0x4007827C [8], 0x400782BC [9], 0x400782FC [10], 0x4007833C [11], 0x4007837C [12], 0x400783BC [13], 0x400783FC [14], 0x4007843C [15], 0x4007847C [16], 0x400784BC [17], 0x400784FC [18], 0x4007853C [19], 0x4007857C [20], 0x400785BC [21], 0x400785FC [22], 0x4007863C [23] Access: Read/Write

• SDS_MSP: Channel x Source Data stride or Memory Set Pattern When XDMAC_CCx.MEMSET = 0, this field indicates the source data stride. When XDMAC_CCx.MEMSET = 1, this field indicates the memory set pattern.
• DDS_MSP: Channel x Destination Data Stride or Memory Set Pattern When XDMAC_CCx.MEMSET = 0, this field indicates the destination data stride. When XDMAC_CCx.MEMSET = 1, this field indicates the memory set pattern. 31 30 29 28 27 26 25 24 DDS_MSP 23 22 21 20 19 18 17 16 DDS_MSP 15 14 13 12 11 10 9 8 SDS_MSP 76543210 SDS_MSP

523SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 35.9.30 XDMAC Channel x [x = 0..23] Source Microblock Stride Register Name: XDMAC_CSUSx [x = 0..23] Address: 0x40078080 [0], 0x400780C0 [1], 0x40078100 [2], 0x40078140 [3], 0x40078180 [4], 0x400781C0 [5], 0x40078200 [6], 0x40078240 [7], 0x40078280 [8], 0x400782C0 [9], 0x40078300 [10], 0x40078340 [11], 0x40078380 [12], 0x400783C0 [13], 0x40078400 [14], 0x40078440 [15], 0x40078480 [16], 0x400784C0 [17], 0x40078500 [18], 0x40078540 [19], 0x40078580 [20], 0x400785C0 [21], 0x40078600 [22], 0x40078640 [23] Access: Read/Write

• SUBS: Channel x Source Microblock Stride Two’s complement microblock stride for channel x. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SUBS 15 14 13 12 11 10 9 8 SUBS 76543210 SUBS

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 524 35.9.31 XDMAC Channel x [x = 0..23] Destination Microblock Stride Register Name: XDMAC_CDUSx [x = 0..23] Address: 0x40078084 [0], 0x400780C4 [1], 0x40078104 [2], 0x40078144 [3], 0x40078184 [4], 0x400781C4 [5], 0x40078204 [6], 0x40078244 [7], 0x40078284 [8], 0x400782C4 [9], 0x40078304 [10], 0x40078344 [11], 0x40078384 [12], 0x400783C4 [13], 0x40078404 [14], 0x40078444 [15], 0x40078484 [16], 0x400784C4 [17], 0x40078504 [18], 0x40078544 [19], 0x40078584 [20], 0x400785C4 [21], 0x40078604 [22], 0x40078644 [23] Access: Read/Write

• DUBS: Channel x Destination Microblock Stride Two’s complement microblock stride for channel x. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DUBS 15 14 13 12 11 10 9 8 DUBS 76543210 DUBS

525SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 36. Image Sensor Interface (ISI)

36.1 Description

The Image Sensor Interface (ISI) connects a CMOS-type image sensor to the processor and provides image capture in various formats.The ISI performs data conversion , if necessary, before the storage in memory through DMA. The ISI supports color CMOS image sensor and grayscale image sensors with a reduced set of functionalities. In grayscale mode, the data stream is stored in memory without any processing and so is not compatible with the LCD controller. Internal FIFOs on the preview and codec paths are us ed to store the incoming data. The RGB output on the preview path is compatible with the LCD controller. This module outputs the data in RGB format (LCD compatible) and has scaling capabilities to make it compliant to the LCD display resolution (see Table 36-5 on page 530). Several input formats such as preprocessed RGB or YCbCr are supported through the data bus interface. The ISI supports two modes of synchronization:  Hardware with ISI_VSYNC and ISI_HSYNC signals  International Telecommunication Union Recommendation ITU-R BT.656-4 Start-of-Active-Video (SAV) and End-of-Active-Video (EAV) synchronization sequence Using EAV/SAV for synchronization reduces the pin count (ISI_VSYNC, ISI_HSYNC not used). The polarity of the synchronization pulse is programmable to comply with the sensor signals. Figure 36-1. ISI Connection Example Table 36-1. I/O Description Signal Direction Description ISI_VSYNC In Vertical Synchronization ISI_HSYNC In Horizontal Synchronization ISI_DATA[11..0] In Sensor Pixel Data ISI_MCK Out Master Clock Provided to the Image Sensor ISI_PCK In Pixel Clock Provided by the Image Sensor Image Sensor Image Sensor Interface data[11..0] ISI_DATA[11..0] CLK ISI_MCK PCLK ISI_PCK VSYNC HSYNC ISI_VSYNC ISI_HSYNC

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 526

36.2 Embedded Characteristics

 ITU-R BT. 601/656 8-bit Mode External Interface Support  Supports up to 12-bit Grayscale CMOS Sensors  Support for ITU-R BT.656-4 SAV and EAV Synchronization  Vertical and Horizontal Resolutions up to 2048 × 2048  Preview Path up to 640 × 480 in RGB Mode  Codec Path up to 2048 × 2048  16-byte FIFO on Codec Path  16-byte FIFO on Preview Path  Support for Packed Data Formatting for YCbCr 4:2:2 Formats  Preview Scaler to Generate Smaller Size image  Programmable Frame Capture Rate  VGA, QVGA, CIF, QCIF Formats Supported for LCD Preview  Custom Formats with Horizontal and Vertical Preview Size as Multiples of 16 Also Supported for LCD Preview

36.3 Block Diagram

Figure 36-2. ISI Block Diagram Timing Signals Interface CCIR-656 Embedded Timing Decoder(SAV/EAV) Pixel Sampling Module Clipping + Color Conversion YCC to RGB 2-D Image Scaler Pixel Formatter Rx Direct Display FIFO Core Video Arbiter Camera AHB Master Interface APB InterfaceCamera Interrupt Controller Configuration Registers Clipping + Color Conversion RGB to YCC Rx Direct Capture FIFO Scatter Mode Support Packed Formatter Frame Rate YCbCr 4:2:2 8:8:8 5:6:5RGB CMOS Sensor Pixel input up to 12 bits Hsync/Line enable Vsync/Frame enable CMOS Sensor Pixel Clock input Pixel Clock Domain AHB Clock Domain APB Clock Domain From Rx buffers Camera Interrupt Request Line codec_on AHB bus APB bus Preview path Codec path

527SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

36.4 Product Dependencies

36.4.1 I/O Lines

The pins used for interfacing the compliant external devices can be multiplexed with PIO lines. The programmer must first program the PIO controllers to assign the ISI pins to their peripheral functions.

36.4.2 Power Management

The ISI can be clocked through the Power Management Cont roller (PMC), thus the programmer must first configure the PMC to enable the ISI clock.

36.4.3 Interrupt Sources

The ISI interface has an interrupt line connected to the interrupt controller. Handling the ISI interrupt requires programming the interrupt controller before configuring the ISI. Table 36-2. I/O Lines Instance Signal I/O Line Peripheral ISI ISI_D0 PD22 D ISI ISI_D1 PD21 D ISI ISI_D2 PB3 D ISI ISI_D3 PA9 B ISI ISI_D4 PA5 B ISI ISI_D5 PD11 D ISI ISI_D6 PD12 D ISI ISI_D7 PA27 D ISI ISI_D8 PD27 D ISI ISI_D9 PD28 D ISI ISI_D10 PD30 D ISI ISI_D11 PD31 D ISI ISI_HSYNC PD24 D ISI ISI_PCK PA24 D ISI ISI_VSYNC PD25 D Table 36-3. Peripheral IDs Instance ID ISI 59

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 528

36.5 Functional Description

The Image Sensor Interface (ISI) supports direct connection to the ITU-R BT. 601/656 8-bit mode compliant sensors and up to 12-bit grayscale sensors. It receives the image data stream from the image sensor on the 12-bit data bus. This module receives up to 12 bits for data, the horizontal and vertical synchronizations and the pixel clock. The reduced pin count alternative for sync hronization is supported for sensors t hat embed SAV (start of active video) and EAV (end of active video) delimiters in the data stream. The Image Sensor Interface interrupt line is connected to the Advanced Interrupt Controller and can trigger an interrupt at the beginning of each frame and at the end of a DMA frame transfer. If the SAV/EAV synchronization is used, an interrupt can be triggered on each delimiter event. For 8-bit color sensors, the data stream received can be in several possible format s: YCbCr 4:2:2, RGB 8:8:8, RGB 5:6:5 and may be processed before the storage in memory. When the preview DMA channel is configured and enabled, the preview path is activated and an ‘RGB frame’ is moved to memory. The preview path frame rate is configured with the FRATE field of the ISI_CFG1 register. When the codec DMA channel is configured and enabled, the codec path is activated and a ‘YCbCr 4:2:2 frame’ is captured as soon as the ISI_CDC bit of the ISI Control Register (ISI_CR) is set. When the FULL bit of the ISI_CFG1 register is set, both preview DMA channel and codec DMA channel can operate simultaneously. When a zero is written to the FULL bit of the ISI_CFG1 register, a hardware scheduler checks the FRATE field. If its value is zero, a preview frame is skipped and a codec frame is moved to memory instead. If its value is other than zero, at least one free frame slot is available. The scheduler postpones the codec frame to that free available frame slot. The data stream may be sent on both preview path and codec path if the value of bit ISI_CDC in the ISI_CR is one. To optimize the bandwidth, the codec path should be enabled only when a capture is required. In grayscale mode, the input data stream is stored in memory without any processing. The 12-bit data, which represent the grayscale level for the pi xel, is stored in memory one or two pixels per word, depending on the GS_MODE bit in the ISI_CFG2 register. The codec datapath is not available when grayscale image is selected. A frame rate counter allows users to capture all frames or 1 out of every 2 to 8 frames.

529SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

36.5.1 Data Timing

36.5.1.1 VSYNC/HSYNC Data Timing

In the VSYNC/HSYNC synchronization, the valid data is captured with the active edge of the pixel clock (ISI_PCK), after SFD lines of vertical blanking and SLD pixel clock periods delay programmed in the ISI_CR. The data timing using horizontal and vertical synchronization are shown in Figure 36-4. Figure 36-3. HSYNC and VSYNC Synchronization

36.5.1.2 SAV/EAV Data Timing

The ITU-RBT.656-4 standard defines the functional timing for an 8-bit wide interface. There are two timing reference signals, one at the beginning of each video data block SAV (0xFF000080) and one at the end of each video data blo ck EAV (0xFF00009D). Only data sent between EAV and SAV is captured. Horizontal blanking and vert ical blanking are ignored. Use of the SAV and EAV synchronization eliminates the ISI_VSYNC and ISI_HSYNC signals from the interface, thereb y reducing the pin count. In order to retrieve both frame and line synchronization properly, at least one line of vertical blanking is mandatory. The data timing using EAV/SAV sequence synchronization are shown in Figure 36-4. Figure 36-4. SAV and EAV Se quence Synchronization ISI_VSYNC ISI_HSYNC ISI_PCK Frame 1 line Y Cb Y Cr Y Cb Y Cr Y Cb Y CrISI_DATA[7..0] ISII_PCK Cr Y Cb Y Cr Y Y Cr Y Cb FF 00ISI_DATA[7..0] FF 00 00 80 Y Cb Y 00 9D SAV EAVActive Video

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 530

36.5.2 Data Ordering

The RGB color space format is required for viewing im ages on a display screen preview, and the YCbCr color space format is required for encoding. All the sensors do not output the YCbCr or RGB components in the same order. The ISI allows the user to program the same component order as the sensor, reducing software treatments to restore the right format. Table 36-4. Data Ordering in YCbCr Mode Mode Byte 0 Byte 1 Byte 2 Byte 3 Default Cb(i) Y(i) Cr(i) Y(i+1) Mode 1 Cr(i) Y(i) Cb(i) Y(i+1) Mode 2 Y(i) Cb(i) Y(i+1) Cr(i) Mode 3 Y(i) Cr(i) Y(i+1) Cb(i) Table 36-5. RGB Format in Default Mode, RGB_CFG = 00, No Swap Mode Byte D7 D6 D5 D4 D3 D2 D1 D0 RGB 8:8:8 Byte 0 R7(i) R6(i) R5(i) R4(i) R3(i) R2(i) R1(i) R0(i) Byte 1 G7(i) G6(i) G5(i) G4 (i) G3(i) G2(i) G1(i) G0(i) Byte 2 B7(i) B6(i) B5(i) B4(i) B3(i) B2(i) B1(i) B0(i) Byte 3 R7(i+1) R6(i+1) R5(i+1) R4(i+1) R3(i+1) R2(i+1) R1(i+1) R0(i+1) RGB 5:6:5 Byte 0 R4(i) R3(i) R2(i) R1(i) R0(i) G5(i) G4(i) G3(i) Byte 1 G2(i) G1(i) G0(i) B4(i) B3(i) B2(i) B1(i) B0(i) Byte 2 R4(i+1) R3(i+1) R2(i+1) R1(i+1) R0(i+1) G5(i+1) G4(i+1) G3(i+1) Byte 3 G2(i+1) G1(i+1) G0(i+1) B4(i+1) B3(i+1) B2(i+1) B1(i+1) B0(i+1) Table 36-6. RGB Format, RGB_CFG = 10 (Mode 2), No Swap Mode Byte D7 D6 D5 D4 D3 D2 D1 D0 RGB 5:6:5 Byte 0 G2(i) G1(i) G0(i) R4(i) R3(i) R2(i) R1(i) R0(i) Byte 1 B4(i) B3(i) B2(i) B1(i) B0(i) G5(i) G4(i) G3(i) Byte 2 G2(i+1) G1(i+1) G0(i+1) R4(i+1) R3(i+1) R2(i+1) R1(i+1) R0(i+1) Byte 3 B4(i+1) B3(i+1) B2(i+1) B1(i+1) B0(i+1) G5(i+1) G4(i+1) G3(i+1) Table 36-7. RGB Format in Default Mo de, RGB_CFG = 00, Swap Activated Mode Byte D7 D6 D5 D4 D3 D2 D1 D0 RGB 8:8:8 Byte 0 R0(i) R1(i) R2(i) R3(i) R4(i) R5(i) R6(i) R7(i) Byte 1 G0(i) G1(i) G2(i) G3 (i) G4(i) G5(i) G6(i) G7(i) Byte 2 B0(i) B1(i) B2(i) B3(i) B4(i) B5(i) B6(i) B7(i) Byte 3 R0(i+1) R1(i+1) R2(i+1) R3(i+1) R4(i+1) R5(i+1) R6(i+1) R7(i+1) RGB 5:6:5 Byte 0 G3(i) G4(i) G5(i) R0(i) R1(i) R2(i) R3(i) R4(i) Byte 1 B0(i) B1(i) B2(i) B3(i) B4(i) G0(i) G1(i) G2(i) Byte 2 G3(i+1) G4(i+1) G5(i+1) R0(i+1) R1(i+1) R2(i+1) R3(i+1) R4(i+1) Byte 3 B0(i+1) B1(i+1) B2(i+1) B3(i+1) B4(i+1) G0(i+1) G1(i+1) G2(i+1)

531SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 The RGB 5:6:5 input format is processe d to be displayed as RGB 5:6:5 forma t, compliant with the 16-bit mode of the LCD controller.

36.5.3 Clocks

The sensor master clock (ISI_MCK) can be generated either by the Advanced Power Management Controller (APMC) through a Programmable Clock output or by an external oscillator connected to the sensor. None of the sensors embed a power management controller, so providing the clock by the APMC is a simple and efficient way to control power consumption of the system. Care must be taken when programming the system clock. The ISI has two clock domains, the sensor master clock and the pixel clock provided by sensor. The two clock domains are not synchronized, but the sensor master clock must be faster than the pixel clock.

36.5.4 Preview Path

36.5.4.1 Scaling, Decimation (Subsampling)

This module resizes captured 8-bit color sensor images to fit the LCD display format. The resize module performs only downscaling. The same ratio is applied for both horiz ontal and vertical resize, then a fractional decimation algorithm is applied. The decimation factor is a multiple of 1/16; values 0 to 15 are forbidden. Example: Input 1280 × 1024 Output = 640 × 480 Hratio = 1280/640 = 2 Vratio = 1024/480 = 2.1333 The decimation factor is 2 so 32/16. Table 36-8. Decimation Factor Decimation Value 0–15 16 17 18 19 ... 124 125 126 127 Table 36-9. Decimation and Scaler Offset Values OUTPUT INPUT 352 × 288 640 × 480 800 × 600 1280 × 1024 1600 × 1200 2048 × 1536 VGA 640 × 480 F — 16 20 32 40 51 QVGA 320 × 240 F 1 63 24 06 48 0 1 0 2 CIF 352 × 288 F 1 62 63 35 66 68 5 QCIF 176 × 144 F 32 53 66 113 133 170

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 532 Figure 36-5. Resize Examples

36.5.4.2 Color Space Conversion

This module converts YCrCb or YUV pixels to RGB color space. Clipping is performed to ensure that the samples value do not exceed the allowable range. The conversion matrix is defined below and is fully programmable: Example of programmable value to convert YCrCb to RGB: An example of programmable value to convert from YUV to RGB: 1280 1024 480 640 32/16 decimation 1280 1024 288 352 56/16 decimation R G B C0 0 C1 C0 C2– C3– C0 C4 0 YY off– Cb Cboff– Cr Croff– RY 1.596 V⋅+ = BY 2.032 U⋅+ =

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36.5.4.3 Memory Interface

The preview datapath contains a data formatter that converts 8:8:8 pixel to RGB 5:6:5 format compliant with the 16-bit format of the LCD controller. In general, when converting from a color channel with more bits to one with fewer bits, the formatter module discards the lower-order bits. For example, converting from RGB 8:8:8 to RGB 5:6:5, the formatter module discards the three LSBs from the red and blue channels, and two LSBs from the green channel. 12-bit Grayscale Mode ISI_DATA[11:0] is the physical interface to the ISI. These bits are sampled and written to memory. When 12-bit grayscale mode is enabled, two memory formats are supported: ISI_CFG2.GS_MODE = 0: two pixels per word ISI_CFG2.GS_MODE = 1: one pixel per word The following tables illustrate the memory mapping for the two formats. Table 36-10. Grayscale Memory Mapping Configuration for 12 -bit Data (ISI_CFG2.GS_MODE = 0: two pixels per word) 31 30 29 28 27 26 25 24 Pixel 0 [11:4] 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 Pixel 1 [11:4] 76543210 Pixel 1 [3:0] –––– Table 36-11. Grayscale Memory Mapping Configuration for 12 -bit Data (ISI_CFG2.GS_MODE = 1: one pixel per word) 31 30 29 28 27 26 25 24 Pixel 0 [11:4] 23 22 21 20 19 18 17 16 Pixel 0 [3:0] –––– 15 14 13 12 11 10 9 8 76543210

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 534 8-bit Grayscale Mode For 8-bit grayscale mode, ISI_DATA[7:0] on the 12-bit data bus is the physical interface to the ISI. These bits are sampled and written to memory. To enable 8-bit grayscale mode, configure ISI_CFG2 as follows: ̶ Clear ISI_CFG2.GRAYSCALE. ̶ Clear ISI_CFG2.RGB_SWAP. ̶ Clear ISI_CFG2.COL_SPACE. ̶ Configure the field ISI_CFG2.YCC_SWAP to value 0. ̶ Configure the field ISI_CFG2.IM_VSIZE with the vertical resoloution of the image minus 1. ̶ Configure the field ISI_CFG2.IM_HSIZE with the horizontal resolution of the image divided by 2. The horizontal resolution must be a multiple of 2. The codec datapath is used to capture the 8-bit grayscale image. Use the following configuration: ̶ Set ISI_DMA_C_CTRL.C_FETCH. ̶ Configure ISI_DMA_C_DSCR.C_DSCR with the descriptor address. ̶ Write a one to the bit ISI_DMA_CHER.C_CH_EN. Table 36-12. Memory Mapping for 8-bit Grayscale Mode 31 30 29 28 27 26 25 24 Pixel 3 23 22 21 20 19 18 17 16 Pixel 2 15 14 13 12 11 10 9 8 Pixel 1 76543210 Pixel 0

535SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

36.5.4.4 FIFO and DMA Features

Both preview and codec datapaths contain FIFOs. These asynchronous buffers are used to safely transfer formatted pixels from the pixel clock domain to the AHB clock domain. A video arbiter is used to manage FIFO thresholds and triggers a relevant DMA request through the AHB master interface. Thus, depending on the FIFO state, a specified length burst is asserted. Regarding AHB master interface, it supports Scatter DMA mode through linked list operation. This mode of operation improves flexibility of image buffer location and allows the user to allocate two or more frame buffers. The destination fr ame buffers are defined by a series of Frame Buffer Descriptors (FBD). Each FBD controls the transfer of one entire frame and then opti onally loads a further FBD to switch the DMA operation at another frame buffer address. The FBD is defined by a series of three words. The first one defines the current frame buffer address (named DMA_X_ADDR register), the second defines control information (named DMA_X_CTRL register) and the third defines the next descriptor address (named DMA_X_DSCR). DMA transfer mode with linked list support is available for both codec and preview datapath. The data to be transferred described by an FBD requires seve ral burst accesses. In the following example, the use of two ping-pong frame buffers is described. Example: The first FBD, stored at address 0x00030000, defines the location of the first frame buffer. This address is programmed in the ISI user interface DMA_P_DSCR. To enable the descriptor fetch operation, the value 0x00000001 must be written to the DMA_P_CTRL register. LLI_0 and LLI_1 are the two descriptors of the linked list. Destination address: frame buffer ID0 0x02A000 (LLI_0.DMA_P_ADDR) Transfer 0 Control Information, fetch and writeback: 0x00000003 (LLI_0.DMA_P_CTRL) Next FBD address: 0x00030010 (LLI_0.DMA_P_DSCR) Second FBD, stored at address 0x00030010, defines the location of the second frame buffer. Destination address: frame buffer ID1 0x0003A000 (LLI_1.DMA_P_ADDR) Transfer 1 Control information fetch and writeback: 0x00000003 (LLI_1.DMA_P_CTRL) Next FBD address: 0x00030000, wrapping to first FBD (LLI_1.DMA_P_DSCR) Using this technique, several frame buffers can be configured through the linked list. Figure 36-6 illustrates a typical three frame buffer application. Frame n is mapped to frame buffer 0, frame n+1 is mapped to frame buffer 1, frame n+2 is mapped to frame buffer 2, further frames wrap. A codec request occurs, and the full-size 4:2:2 encoded frame is stored in a dedicated memory space.

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 536 Figure 36-6. Three Frame Buffers Application and Memory Mapping frame n frame n+1 frame n+2frame n-1 frame n+3 frame n+4 Frame Buffer 0 Frame Buffer 1 Frame Buffer 3 4:2:2 Image Full ROI ISI config Space Codec Request Codec Done LCD Memory Space

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36.5.5 Codec Path

36.5.5.1 Color Space Conversion

Depending on user selection, this module can be bypassed so that input YCrCb stream is directly connected to the format converter module. If the RGB input stream is selected, this module converts RGB to YCrCb color space with the formulas given below: An example of coefficients is given below:

36.5.5.2 Memory Interface

Dedicated FIFOs are used to support packed memory mapp ing. YCrCb pixel components are sent in a single 32- bit word in a contiguous space (packed). Data is stored in the order of natural scan lines. Planar mode is not supported.

36.5.5.3 DMA Features

Like preview datapath, codec datapath DMA mode uses linked list operation. Y Cr Cb C0 C1 C2 C3 C– 4 C– 5 C– 6 C– 7 C8 R G B Yoff Croff Cboff

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36.6 Image Sensor Interface (ISI) User Interface

Note: Several parts of the ISI controller use the pixel clock provided by the image sensor (ISI_PCK). Thus the user must first p rogram the image sensor to provide this clock (ISI_PCK) before programming the Image Sensor Controller. Table 36-13. Register Mapping Offset Register Name Access Reset Value 0x00 ISI Configuration 1 Register ISI_CFG1 Read/Write 0x00000000 0x04 ISI Configuration 2 Register ISI_CFG2 Read/Write 0x00000000 0x08 ISI Preview Size Register ISI_PSIZE Read/Write 0x00000000 0x0C ISI Preview Decimation Factor Register ISI_PDECF Read/Write 0x00000010 0x10 ISI Color Space Conversion YCrCb To RGB Set 0 Register ISI_Y2R_SET0 Read/Write 0x6832CC95 0x14 ISI Color Space Conversion YCrCb To RGB Set 1 Register ISI_Y2R_SET1 Read/Write 0x00007102 0x18 ISI Color Space Conversion RGB To YCrCb Set 0 Register ISI_R2Y_SET0 Read/Write 0x01324145 0x1C ISI Color Space Conversion RGB To YCrCb Set 1 Register ISI_R2Y_SET1 Read/Write 0x01245E38 0x20 ISI Color Space Conversion RGB To YCrCb Set 2 Register ISI_R2Y_SET2 Read/Write 0x01384A4B 0x24 ISI Control Register ISI_CR Write-only – 0x28 ISI Status Register ISI_SR Read-only 0x00000000 0x2C ISI Interrupt Enable Register ISI_IER Write-only – 0x30 ISI Interrupt Disable Register ISI_IDR Write-only – 0x34 ISI Interrupt Mask Register ISI_IMR Read-only 0x00000000 0x38 DMA Channel Enable Register ISI_DMA_CHER Write-only – 0x3C DMA Channel Disable Register ISI_DMA_CHDR Write-only – 0x40 DMA Channel Status Regist er ISI_DMA_CHSR Read-only 0x00000000 0x44 DMA Preview Base Address Register ISI_DMA_P_ADDR Read/Write 0x00000000 0x48 DMA Preview Control Register ISI_DMA_P_CTRL Read/Write 0x00000000 0x4C DMA Preview Descriptor Address R egister ISI_DMA_P_DSCR Read/Write 0x00000000 0x50 DMA Codec Base Address Register ISI_DMA_C_ADDR Read/Write 0x00000000 0x54 DMA Codec Control Register ISI_DMA_C_CTRL Read/Write 0x00000000 0x58 DMA Codec Descriptor Address Register ISI_DMA_C_DSCR Read/Write 0x00000000 0x5C–0xE0 Reserved – – – 0xE4 Write Protection Mode Regist er ISI_WPMR Read/Write 0x00000000 0xE8 Write Protection Status Register ISI_WPSR Read-only 0x00000000 0xEC–0xF8 Reserved – – – 0xFC Reserved – – –

539SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

36.6.1 ISI Configuration 1 Register

Name: ISI_CFG1 Address: 0x4004C000 Access: Read/Write

• HSYNC_POL: Horizontal Synchronization Polarity 0: HSYNC active high. 1: HSYNC active low.
• VSYNC_POL: Vertical Synchronization Polarity 0: VSYNC active high. 1: VSYNC active low.
• PIXCLK_POL: Pixel Clock Polarity 0: Data is sampled on rising edge of pixel clock. 1: Data is sampled on falling edge of pixel clock.
• EMB_SYNC: Embedded Synchronization 0: Synchronization by HSYNC, VSYNC. 1: Synchronization by embedded synchronization sequence SAV/EAV.
• CRC_SYNC: Embedded Synchronization Correction 0: No CRC correction is performed on embedded synchronization. 1: CRC correction is performed. If the correction is not possible, the current frame is discarded and the CRC_ERR bit is set in the ISI_SR.
• FRATE: Frame Rate [0..7] 0: All the frames are captured, else one frame every FRATE + 1 is captured.
• DISCR: Disable Codec Request 0: Codec datapath DMA interface requires a request to restart. 1: Codec datapath DMA automatically restarts. 31 30 29 28 27 26 25 24 SFD 23 22 21 20 19 18 17 16 SLD 15 14 13 12 11 10 9 8 – THMASK FULL DISCR FRATE 76543210 CRC_SYNC EMB_SYNC – PIXCLK_POL VSYNC_POL HSYNC_POL – –

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 540

• FULL: Full Mode is Allowed 0: The codec frame is transferred to memory when an available frame slot is detected. 1: Both preview and codec DMA channels are operating simultaneously.
• THMASK: Threshold Mask
• SLD: Start of Line Delay SLD pixel clock periods to wait before the beginning of a line.
• SFD: Start of Frame Delay SFD lines are skipped at the beginning of the frame. Value Name Description

0 BEATS_4 Only 4 beats AHB burst allowed

1 BEATS_8 Only 4 and 8 beats AHB burst allowed

2 BEATS_16 4, 8 and 16 beats AHB burst allowed

541SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

36.6.2 ISI Configuration 2 Register

Name: ISI_CFG2 Address: 0x4004C004 Access: Read/Write

• IM_VSIZE: Vertical Size of the Image Sensor [0..2047] IM_VSIZE = Vertical size - 1
• GS_MODE: Grayscale Pixel Format Mode 0: 2 pixels per word. 1: 1 pixel per word.
• RGB_MODE: RGB Input Mode 0: RGB 8:8:8 24 bits. 1: RGB 5:6:5 16 bits.
• GRAYSCALE: Grayscale Mode Format Enable 0: Grayscale mode is disabled. 1: Input image is assumed to be grayscale-coded.
• RGB_SWAP: RGB Format Swap Mode 0: D7 → R7. 1: D0 → R7. The RGB_SWAP has no effect when grayscale mode is enabled.
• COL_SPACE: Color Space for the Image Data 0: YCbCr. 1: RGB.
• IM_HSIZE: Horizontal Size of the Image Sensor [0..2047] If 8-bit grayscale mode is enabled, IM_HSIZE = (Horizontal size/2) - 1. Else IM_HSIZE = Horizontal size - 1. 31 30 29 28 27 26 25 24 RGB_CFG YCC_SWAP – IM_HSIZE 23 22 21 20 19 18 17 16 IM_HSIZE 15 14 13 12 11 10 9 8 COL_SPACE RGB_SWAP GRAYSCALE RGB_MODE GS_MODE IM_VSIZE 76543210 IM_VSIZE

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 542

• YCC_SWAP: YCrCb Format Swap Mode Defines the YCC image data.
• RGB_CFG: RGB Pixel Mapping Configuration Defines RGB pattern when RGB_MODE is set to 1. If RGB_MODE is set to RGB 8:8:8, then RGB_CFG = 0 implies RGB color sequence, else it implies BGR color sequence. Value Name Description

0 DEFAULT

Byte 0 Cb(i) Byte 1 Y(i) Byte 2 Cr(i) Byte 3 Y(i+1) 1M ODE1 Byte 0 Cr(i) Byte 1 Y(i) Byte 2 Cb(i) Byte 3 Y(i+1) 2M ODE2 Byte 0 Y(i) Byte 1 Cb(i) Byte 2 Y(i+1) Byte 3 Cr(i) 3M ODE3 Byte 0 Y(i) Byte 1 Cr(i) Byte 2 Y(i+1) Byte 3 Cb(i) Value Name Description Byte 0 R/G(MSB) Byte 1 G(LSB)/B Byte 2 R/G(MSB) Byte 3 G(LSB)/B 1M ODE1 Byte 0 B/G(MSB) Byte 1 G(LSB)/R Byte 2 B/G(MSB) Byte 3 G(LSB)/R 2M ODE2 Byte 0 G(LSB)/R Byte 1 B/G(MSB) Byte 2 G(LSB)/R Byte 3 B/G(MSB) 3M ODE3 Byte 0 G(LSB)/B Byte 1 R/G(MSB) Byte 2 G(LSB)/B Byte 3 R/G(MSB)

543SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

36.6.3 ISI Preview Size Register

Name: ISI_PSIZE Address: 0x4004C008 Access: Read/Write

• PREV_VSIZE: Vertical Size for the Preview Path PREV_VSIZE = Vertical Preview size - 1 (480 max only in RGB mode).
• PREV_HSIZE: Horizontal Size for the Preview Path PREV_HSIZE = Horizontal Preview size - 1 (640 max only in RGB mode). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PREV_HSIZE 15 14 13 12 11 10 9 8 76543210 PREV_VSIZE

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 544

36.6.4 ISI Preview Decimation Factor Register

Name: ISI_PDECF Address: 0x4004C00C Access: Read/Write

• DEC_FACTOR: Decimation Factor DEC_FACTOR is 8-bit width, range is from 16 to 255. Values from 0 to 16 do not perform any decimation. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 DEC_FACTOR

545SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

36.6.5 ISI Color Space Conversion YCrCb to RGB Set 0 Register

Name: ISI_Y2R_SET0 Address: 0x4004C010 Access: Read/Write

• C0: Color Space Conversion Matrix Coefficient C0 C0 element default step is 1/128, ranges from 0 to 1.9921875.
• C1: Color Space Conversion Matrix Coefficient C1 C1 element default step is 1/128, ranges from 0 to 1.9921875.
• C2: Color Space Conversion Matrix Coefficient C2 C2 element default step is 1/128, ranges from 0 to 1.9921875.
• C3: Color Space Conversion Matrix Coefficient C3 C3 element default step is 1/128, ranges from 0 to 1.9921875. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 546

36.6.6 ISI Color Space Conversion YCrCb to RGB Set 1 Register

Name: ISI_Y2R_SET1 Address: 0x4004C014 Access: Read/Write

• C4: Color Space Conversion Matrix Coefficient C4 C4 element default step is 1/128, ranges from 0 to 3.9921875.
• Yoff: Color Space Conversion Luminance Default Offset 0: No offset. 1: Offset = 128.
• Croff: Color Space Conversion Red Chrominance Default Offset 0: No offset. 1: Offset = 16.
• Cboff: Color Space Conversion Blue Chrominance Default Offset 0: No offset. 1: Offset = 16. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 – Cboff Croff Yoff – – – C4 76543210

547SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

36.6.7 ISI Color Space Conversion RGB to YCrCb Set 0 Register

Name: ISI_R2Y_SET0 Address: 0x4004C018 Access: Read/Write

• C0: Color Space Conversion Matrix Coefficient C0 C0 element default step is 1/256, from 0 to 0.49609375.
• C1: Color Space Conversion Matrix Coefficient C1 C1 element default step is 1/128, from 0 to 0.9921875.
• C2: Color Space Conversion Matrix Coefficient C2 C2 element default step is 1/512, from 0 to 0.2480468875.
• Roff: Color Space Conversion Red Component Offset 0: No offset 1: Offset = 16 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 –C 2 15 14 13 12 11 10 9 8 –C 1 76543210 –C 0

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 548

36.6.8 ISI Color Space Conversion RGB to YCrCb Set 1 Register

Name: ISI_R2Y_SET1 Address: 0x4004C01C Access: Read/Write

• C3: Color Space Conversion Matrix Coefficient C3 C0 element default step is 1/128, ranges from 0 to 0.9921875.
• C4: Color Space Conversion Matrix Coefficient C4 C1 element default step is 1/256, ranges from 0 to 0.49609375.
• C5: Color Space Conversion Matrix Coefficient C5 C1 element default step is 1/512, ranges from 0 to 0.2480468875.
• Goff: Color Space Conversion Green Component Offset 0: No offset. 1: Offset = 128. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 –C 5 15 14 13 12 11 10 9 8 –C 4 76543210 –C 3

549SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

36.6.9 ISI Color Space Conversion RGB to YCrCb Set 2 Register

Name: ISI_R2Y_SET2 Address: 0x4004C020 Access: Read/Write

• C6: Color Space Conversion Matrix Coefficient C6 C6 element default step is 1/512, ranges from 0 to 0.2480468875.
• C7: Color Space Conversion Matrix Coefficient C7 C7 element default step is 1/256, ranges from 0 to 0.49609375.
• C8: Color Space Conversion Matrix Coefficient C8 C8 element default step is 1/128, ranges from 0 to 0.9921875.
• Boff: Color Space Conversion Blue Component Offset 0: No offset. 1: Offset = 128. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 –C 8 15 14 13 12 11 10 9 8 –C 7 76543210 –C 6

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 550

36.6.10 ISI Control Register

Name: ISI_CR Address: 0x4004C024 Access: Write-only

• ISI_EN: ISI Module Enable Request Write a one to this bit to enable the module. Software must poll the ENABLE bit in the ISI_SR to verify that the command has successfully completed.
• ISI_DIS: ISI Module Disable Request Write a one to this bit to disable the module. If both ISI_EN and ISI_DIS are asserted at the same time, the disable request is not taken into account. Software must poll the DIS_DONE bit in the ISI_SR to verify that the command has successfully completed.
• ISI_SRST: ISI Software Reset Request Write a one to this bit to request a software reset of the module. Software must poll the SRST bit in the ISI_SR to verify that the software request command has terminated.
• ISI_CDC: ISI Codec Request Write a one to this bit to enable the codec datapath and capture a full resolution frame. A new request cannot be taken into account while CDC_PND bit is active in the ISI_SR. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210

551SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

36.6.11 ISI Status Register

Name: ISI_SR Address: 0x4004C028 Access: Read-only

• ENABLE: Module Enable 0: Module is disabled. 1: Module is enabled.
• DIS_DONE: Module Disable Request has Terminated (cleared on read) 0: Indicates that the request is not completed (if a request was issued). 1: Disable request has completed. This flag is reset after a read operation.
• SRST: Module Software Reset Request has Terminated (cleared on read) 0: Indicates that the request is not completed (if a request was issued). 1: Software reset request has completed. This flag is reset after a read operation.
• CDC_PND: Pending Codec Request 0: Indicates that no codec request is pending 1: Indicates that the request has been taken into account but cannot be serviced within the current frame. The operation is postponed to the next frame.
• VSYNC: Vertical Synchron ization (cleared on read) 0: Indicates that the vertical synchronization has not been detected since the last read of the ISI_SR. 1: Indicates that a vertical synchronization has been detected since the last read of the ISI_SR.
• PXFR_DONE: Preview DMA Transfer has Terminated (cleared on read) 0: Preview transfer done not detected. 1: Preview transfer done detected. When set, this bit indicates that the data transfer on the preview channel has completed since the last read of ISI_SR.
• CXFR_DONE: Codec DMA Transfer has Terminated (cleared on read) 0: Codec transfer done not detected. 1: Codec transfer done detected. When set, this bit indicates that the data transfer on the codec channel has completed since the last read of ISI_SR. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 552

• SIP: Synchronization in Progress When the status of the preview or codec DMA channel is modified, a minimum amount of time is required to perform the clock domain synchronization. 0: The clock domain synchronization process is terminated. 1: This bit is set when the clock domain synchronization operation occurs. No modification of the channel status is allowed when this bit is set, to guarantee data integrity.
• P_OVR: Preview Datapath Ov erflow (cleared on read) 0: No overflow 1: An overrun condition has occurred in input FIFO on the preview path. The overrun happens when the FIFO is full and an attempt is made to write a new sample to the FIFO since the last read of ISI_SR.
• C_OVR: Codec Datapath Overflow (cleared on read) 0: No overflow 1: An overrun condition has occurred in input FIFO on the codec path. The overrun happens when the FIFO is full and an attempt is made to write a new sample to the FIFO since the last read of ISI_SR.
• CRC_ERR: CRC Synchronization Error (cleared on read) 0: No CRC error in the embedded synchronization frame (SAV/EAV) 1: Embedded Synchronization Correction is enabled (CRC_SYNC bit is set) in the ISI_CR and an error has been detected and not corrected since the last read of ISI_SR. The frame is discarded and the ISI waits for a new one.
• FR_OVR: Frame Rate Overrun (cleared on read) 0: No frame overrun 1: Frame overrun. The current frame is being skipped because a vsync signal has been detected while flushing FIFOs since the last read of ISI_SR.

553SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

36.6.12 ISI Interrupt Enable Register

Name: ISI_IER Address: 0x4004C02C Access: Read/Write

• DIS_DONE: Disable Done Interrupt Enable 0: No effect. 1: Enables the corresponding interrupt.
• SRST: Software Reset Interrupt Enable 0: No effect. 1: Enables the corresponding interrupt.
• VSYNC: Vertical Synchron ization Interrupt Enable 0: No effect. 1: Enables the corresponding interrupt.
• PXFR_DONE: Preview DMA Tran sfer Done Interrupt Enable 0: No effect. 1: Enables the corresponding interrupt.
• CXFR_DONE: Codec DMA Transfer Done Interrupt Enable 0: No effect. 1: Enables the corresponding interrupt.
• P_OVR: Preview Datapath Overflow Interrupt Enable 0: No effect. 1: Enables the corresponding interrupt.
• C_OVR: Codec Datapath Overflow Interrupt Enable 0: No effect. 1: Enables the corresponding interrupt. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 554

• CRC_ERR: Embedded Synchronization CRC Error Interrupt Enable 0: No effect. 1: Enables the corresponding interrupt.
• FR_OVR: Frame Rate Overflow Interrupt Enable 0: No effect. 1: Enables the corresponding interrupt.

555SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

36.6.13 ISI Interrupt Disable Register

Name: ISI_IDR Address: 0x4004C030 Access: Read/Write

• DIS_DONE: Disable Done Interrupt Disable 0: No effect. 1: Disables the corresponding interrupt.
• SRST: Software Reset Interrupt Disable 0: No effect. 1: Disables the corresponding interrupt.
• VSYNC: Vertical Synchronization Interrupt Disable 0: No effect. 1: Disables the corresponding interrupt.
• PXFR_DONE: Preview DMA Transf er Done Interrupt Disable 0: No effect. 1: Disables the corresponding interrupt.
• CXFR_DONE: Codec DMA Transfer Done Interrupt Disable 0: No effect. 1: Disables the corresponding interrupt.
• P_OVR: Preview Datapath Overflow Interrupt Disable 0: No effect. 1: Disables the corresponding interrupt.
• C_OVR: Codec Datapath Overflow Interrupt Disable 0: No effect. 1: Disables the corresponding interrupt. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 556

• CRC_ERR: Embedded Synchronization CRC Error Interrupt Disable 0: No effect. 1: Disables the corresponding interrupt.
• FR_OVR: Frame Rate Overflow Interrupt Disable 0: No effect. 1: Disables the corresponding interrupt.

557SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

36.6.14 ISI Interrupt Mask Register

Name: ISI_IMR Address: 0x4004C034 Access: Read/Write

• DIS_DONE: Module Disable Operation Completed 0: The Module Disable Operation Completed interrupt is disabled. 1: The Module Disable Operation Completed interrupt is enabled.
• SRST: Software Reset Completed 0: The Software Reset Completed interrupt is disabled. 1: The Software Reset Completed interrupt is enabled.
• VSYNC: Vertical Synchronization 0: The Vertical Synchronization interrupt is disabled. 1: The Vertical Synchronization interrupt is enabled.
• PXFR_DONE: Preview DMA Transfer Completed 0: The Preview DMA Transfer Completed interrupt is disabled. 1: The Preview DMA Transfer Completed interrupt is enabled.
• CXFR_DONE: Codec DMA Transfer Completed 0: The Codec DMA Transfer Completed interrupt is disabled. 1: The Codec DMA Transfer Completed interrupt is enabled.
• P_OVR: Preview FIFO Overflow 0: The Preview FIFO Overflow interrupt is disabled. 1: The Preview FIFO Overflow interrupt is enabled.
• C_OVR: Codec FIFO Overflow 0: The Codec FIFO Overflow interrupt is disabled. 1: The Codec FIFO Overflow interrupt is enabled. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 558

• CRC_ERR: CRC Synchronization Error 0: The CRC Synchronization Error interrupt is disabled. 1: The CRC Synchronization Error interrupt is enabled.
• FR_OVR: Frame Rate Overrun 0: The Frame Rate Overrun interrupt is disabled. 1: The Frame Rate Overrun is enabled.

559SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

36.6.15 DMA Channel Enable Register

Name: ISI_DMA_CHER Address: 0x4004C038 Access: Write-only

• P_CH_EN: Preview Channel Enable Write a one to this bit to enable the preview DMA channel.
• C_CH_EN: Codec Channel Enable Write a one to this bit to enable the codec DMA channel. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 560

36.6.16 DMA Channel Disable Register

Name: ISI_DMA_CHDR Address: 0x4004C03C Access: Read/Write

• P_CH_DIS: Preview Ch annel Disable Request 0: No effect. 1: Disables the channel. Poll P_CH_S in DMA_CHSR to verify that the preview channel status has been successfully modified.
• C_CH_DIS: Codec Channel Disable Request 0: No effect. 1: Disables the channel. Poll C_CH_S in DMA_CHSR to verify that the codec channel status has been successfully modified. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210

561SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

36.6.17 DMA Channel Status Register

Name: ISI_DMA_CHSR Address: 0x4004C040 Access: Read-only

• P_CH_S: Preview DMA Channel Status 0: Indicates that the Preview DMA channel is disabled. 1: Indicates that the Preview DMA channel is enabled.
• C_CH_S: Code DMA Channel Status 0: Indicates that the Codec DMA channel is disabled. 1: Indicates that the Codec DMA channel is enabled. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 562

36.6.18 DMA Preview Base Address Register

Name: ISI_DMA_P_ADDR Address: 0x4004C044 Access: Read/Write

• P_ADDR: Preview Image Base Address This address is word-aligned. 31 30 29 28 27 26 25 24 P_ADDR 23 22 21 20 19 18 17 16 P_ADDR 15 14 13 12 11 10 9 8 P_ADDR 76543210 P_ADDR – –

563SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

36.6.19 DMA Preview Control Register

Name: ISI_DMA_P_CTRL Address: 0x4004C048 Access: Read/Write

• P_FETCH: Descriptor Fetch Control Bit 0: Preview channel fetch operation is disabled. 1: Preview channel fetch operation is enabled.
• P_WB: Descriptor Writeback Control Bit 0: Preview channel writeback operation is disabled. 1: Preview channel writeback operation is enabled.
• P_IEN: Transfer Done Flag Control 0: Preview transfer done flag generation is enabled. 1: Preview transfer done flag generation is disabled.
• P_DONE: Preview Transfer Done This bit is only updated in the memory. 0: The transfer related to this descriptor has not been performed. 1: The transfer related to this descriptor has completed. This bit is updated in memory at the end of the transfer, when writeback operation is enabled. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 564

36.6.20 DMA Preview Descriptor Address Register

Name: ISI_DMA_P_DSCR Address: 0x4004C04C Access: Read/Write

• P_DSCR: Preview Descriptor Base Address This address is word-aligned. 31 30 29 28 27 26 25 24 P_DSCR 23 22 21 20 19 18 17 16 P_DSCR 15 14 13 12 11 10 9 8 P_DSCR 76543210 P_DSCR – –

565SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

36.6.21 DMA Codec Base Address Register

Name: ISI_DMA_C_ADDR Address: 0x4004C050 Access: Read/Write

• C_ADDR: Codec Image Base Address This address is word-aligned. 31 30 29 28 27 26 25 24 C_ADDR 23 22 21 20 19 18 17 16 C_ADDR 15 14 13 12 11 10 9 8 C_ADDR 76543210 C_ADDR – –

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 566

36.6.22 DMA Codec Control Register

Name: ISI_DMA_C_CTRL Address: 0x4004C054 Access: Read/Write

• C_FETCH: Descriptor Fetch Control Bit 0: Codec channel fetch operation is disabled. 1: Codec channel fetch operation is enabled.
• C_WB: Descriptor Writeback Control Bit 0: Codec channel writeback operation is disabled. 1: Codec channel writeback operation is enabled.
• C_IEN: Transfer Done Flag Control 0: Codec transfer done flag generation is enabled. 1: Codec transfer done flag generation is disabled.
• C_DONE: Codec Transfer Done This bit is only updated in the memory. 0: The transfer related to this descriptor has not been performed. 1: The transfer related to this descriptor has completed. This bit is updated in memory at the end of the transfer when write- back operation is enabled. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210

567SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

36.6.23 DMA Codec Descriptor Address Register

Name: ISI_DMA_C_DSCR Address: 0x4004C058 Access: Read/Write

• C_DSCR: Codec Descriptor Base Address This address is word-aligned. 31 30 29 28 27 26 25 24 C_DSCR 23 22 21 20 19 18 17 16 C_DSCR 15 14 13 12 11 10 9 8 C_DSCR 76543210 C_DSCR – –

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 568

36.6.24 ISI Write Protection Mode Register

Name: ISI_WPMR Address: 0x4004C0E4 Access: Read/Write

• WPEN: Write Protection Enable 0: Disables the write protection if WPKEY corresponds to 0x495349 (“ISI” in ASCII). 1: Enables the write protection if WPKEY corresponds to 0x495349 (“ISI” in ASCII).
• WPKEY: Write Protection Key Password 31 30 29 28 27 26 25 24 WPKEY 23 22 21 20 19 18 17 16 WPKEY 15 14 13 12 11 10 9 8 WPKEY 76543210 Value Name Description 0x495349 PASSWD Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0.

569SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

36.6.25 ISI Write Protection Status Register

Name: ISI_WPSR Address: 0x4004C0E8 Access: Read/Write

• WPVS: Write Protection Violation Status
• WPVSRC: Write Protection Violation Source 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WPVSRC 15 14 13 12 11 10 9 8 WPVSRC 76543210 Value Description 0 No write protection violation occurred since the last read of ISI_WPSR. 1 A write protection violation has occurred since the last read of the ISI_WPSR. If this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field WPVSRC. Value Description 0 No Write Protection Violation occurred since the last read of this register (ISI_WPSR). 1 Write access in ISI_CFG1 while Write Protection was enabled (since the last read). 2 Write access in ISI_CFG2 while Write Protection was enabled (since the last read). 3 Write access in ISI_PSIZE while Write Protection was enabled (since the last read). 4 Write access in ISI_PDECF while Write Protection was enabled (since the last read). 5 Write access in ISI_Y2R_SET0 while Write Protection was enabled (since the last read). 6 Write access in ISI_Y2R_SET1 while Write Protection was enabled (since the last read). 7 Write access in ISI_R2Y_SET0 while Write Protection was enabled (since the last read). 8 Write access in ISI_R2Y_SET1 while Write Protection was enabled (since the last read). 9 Write access in ISI_R2Y_SET2 while Write Protection was enabled (since the last read).

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 570 37. USB High-Speed Interface (USBHS)

37.1 Description

The USB High-Speed Interface (USBHS) complies with the Universal Serial Bus (USB) 2.0 specification in all speeds. Each pipe/endpoint can be configured in one of several USB transfer types. It can be associated with one, two or three banks of a DPRAM used to store the current data payload. If two or three banks are used, then one DPRAM bank is read or written by the CPU or the DMA, while the other is read or written by the USBHS core. This feature is mandatory for isochronous pipes/endpoints. Table 37-1 describes the hardware configuration of the USB MCU device.

37.2 Embedded Characteristics

 Compatible with the USB 2.0 Specification  Supports High-Speed (480Mbps), Full-Speed (12Mbps) and Low-Speed (1.5Mbps) Communication  10 Pipes/Endpoints  4096 bytes of Embedded Dual-Port RAM (DPRAM) for Pipes/Endpoints  Up to 3 Memory Banks per Pipe/Endpoint (not for Control Pipe/Endpoint)  Flexible Pipe/Endpoint Configuration and Management with Dedicated DMA Channels  On-Chip UTMI Transceiver including Pull-ups/Pull-downs Table 37-1. Description of USB Pipes/Endpoints Pipe/Endpoint Mnemonic Max. Nb. Banks DMA High Band Width Max. Pipe/ Endpoint Size Type

0 PEP_0 1 N N 64 Control

1 PEP_1 3 Y Y 1024 Isochronous/Bulk/Interrupt/Control

2 PEP_2 3 Y Y 1024 Isochronous/Bulk/Interrupt/Control

3 PEP_3 2 Y Y 1024 Isochronous/Bulk/Interrupt/Control

4 PEP_4 2 Y Y 1024 Isochronous/Bulk/Interrupt/Control

5 PEP_5 2 Y Y 1024 Isochronous/Bulk/Interrupt/Control

6 PEP_6 2 Y Y 1024 Isochronous/Bulk/Interrupt/Control

7 PEP_7 2 Y Y 1024 Isochronous/Bulk/Interrupt/Control

8 PEP_8 2 N Y 1024 Isochronous/Bulk/Interrupt/Control

9 PEP_9 2 N Y 1024 Isochronous/Bulk/Interrupt/Control

571SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

37.3 Block Diagram

The USBHS provides a hardware device to interface a USB link to a data flow stored in a dual-port RAM (DPRAM). In normal operation (SPDCONF = 0), the UTMI transceiver requires the UTMI PLL (480 MHz). In case of full- speed or low-speed only, for a lower consumption (SPDCONF = 1), the UTMI transceiver only requires 48 MHz. Figure 37-1. USBHS Block Diagram

37.3.1 Signal Description

Table 37-2. Signal Description Name Description Type HSDM/DM HS/FS Differential Data Line - Input/Output HSDP/DP HS/FS Differential Data Line + Input/Output 32 bits System Clock Domain USB Clock Domain Rd/Wr/Ready APB Interface USB2.0 CORE PEP Alloc AHB1 DMA AHB0 Local AHB Slave interface Master AHB Multiplexer Slave DPRAM UTMI 16/8 bits APB Bus AHB Bus AHB Bus PMC HSDP/DP HSDM/DM ctrl status USB_48M Clock (needed only when SPDCONF=1) USB_480M Clock (needed only when SPDCONF=0) MCK

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 572

37.4 Product Dependencies

37.4.1 I/O Lines

A regular PIO line must be used to control VBUS. This is configured in the I/O Controller.

37.4.2 Clocks

The clock for the USBHS bus interface is generated by the Power Management Controller. This clock can be enabled or disabled in the Power Management Contro ller. It is recommended to disable the USBHS before disabling the clock, to avoid freezing the USBHS in an undefined state. Before enabling the USB clock in the Power Management Controller, the USBHS must be enabled (by writing a one to the USBHS_CTRL.USBE bit and a zero to the USBHS_CTRL.FRZCLK bit). The USBHS can work in two modes:  Normal mode (SPDCONF = 0) where High speed, Full speed and Low speed are available.  Low-power mode (SPDCONF = 1) where Full speed and Low speed are available. To ensure successful start-up, follow the sequences below: - In Normal mode: 1. Enable the USBHS peripheral clock. Th is is done via the register PMC_PCER. 2. Enable the USBHS (UIMOD , USBE = 1, FRZCLK = 0). 3. Enable the UPLL 480 MHz. 4. Wait for the UPLL 480 MHz to be considered as locked by the PMC. - In Low-power mode: 1. As USB_48M must be set to 48 MHz (refer to Section 31. ”Power Management Controller (PMC)”), select either the PLLA or the UPLL (previously set to ON), and program the PMC_USB register (source selec- tion and divider). 2. Enable the USBHS peripheral clock (PMC_PCER). 3. Put the USBHS in Low-po wer mode (SPDCONF = 1). 4. Enable the USBHS (UIMOD, USBE = 1, FRZCLK = 0). 5. Enable the USBCK bit (PMC_SCER).

37.4.3 Interrupt Sources

The USBHS interrupt request line is conn ected to the interrupt controller. Us ing the USBHS interrupt requires the interrupt controller to be programmed first.

37.4.4 USB Pipe/Endpoint x FIFO Data Register (USBFIFOxDATA)

The application has access to each pipe/endpoint FIFO through its reserved 32 KB address space. The application can access a 64-KB buffer linearly or fixedly as the DPRAM address increment is fully handled by hardware. Byte, half-word and word accesses are supported. Data should be accessed in a big-endian way. Disabling the USBHS (by writing a zero to the USBHS_CTRL.USBE bit) does not reset the DPRAM. Table 37-3. Peripheral IDs Instance ID USBHS 34

573SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

37.5 Functional Description

37.5.1 USB General Operation

37.5.1.1 Power-On and Reset

Figure 37-2 describes the USBHS general states. Figure 37-2. General States After a hardware reset, the USBHS is in Reset state. In this state:  The USBHS is disabled. The USBHS Enable bit in the General Control register (USBHS_CTRL.USBE) is zero.  The USBHS clock is stopped in order to minimize power consumption. The Freeze USB Clock bit (USBHS_CTRL.FRZCLK) is set.  The UTMI is in Suspend mode.  The internal states and registers of the Device and Host modes are reset.  The DPRAM is not cleared and is accessible. After writing a one to USBHS_CTRL.USBE, the USBHS enters the Device or the Host mode in idle state. The USBHS can be disabled at any time by writing a zero to USBHS_CTRL.USBE. This acts as a hardware reset, except that the USBHS_CTRL.FRZCLK, USBHS_CTRL.UIMOD and USBHS_DEVCTRL.LS bits are not reset. Device USBHS_CTRL.USBE = 0 USBHS_CTRL.USBE = 1 USBHS_CTRL.UIMOD = 1 Macro off: USBHS_CTRL.USBE = 0 Clock stopped: USBHS_CTRL.FRZCLK = 1 USBHS_CTRL_USBE = 0 HW RESET USBHS_CTRL.UIMOD= 0 Reset Host USBHS_CTRL.USBE = 1 <any other state> USBHS_CTRL.USBE = 0

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 574

37.5.1.2 Interrupts

One interrupt vector is assigned to the USB interface. Figure 37-3 shows the structure of the USB interrupt system. Figure 37-3. Interrupt System There are two kinds of general interrupts: processing, i.e., their generation is part of the normal processing, and exception, i.e., errors (not related to CPU exceptions).

37.5.1.3 MCU Power Modes

In Peripheral mode, the Suspend Interrupt bit in the Device Global Interrupt Status register (USBHS_DEVISR.SUSP) indicate s that the USB line is in Suspend m ode. In this case, the transceiver is automatically set in Suspend mode to reduce consumption. USBHS_SR.RDERRI USBHS_CTRL.RDERRE USB General Interrupt USB Device Interrupt USB Host Interrupt USB Interrupt Asynchronous interrupt source USBHS_DEVIMR.SUSPE USBHS_DEVIMR.SUSP USBHS_DEVIMR.SOF USBHS_DEVIMR.SOFE USBHS_DEVIMR.EORST USBHS_DEVIMR.EORSTE USBHS_DEVIMR.WAKEUP USBHS_DEVIMR.WAKEUPE USBHS_DEVIMR.EORSM USBHS_DEVIMR.EORSME USBHS_DEVIMR.UPRSM USBHS_DEVIMR.UPRSME USBHS_DEVIMR.EPXINT USBHS_DEVIMR.EPXINTE USBHS_DEVIMR.DMAXINT USBHS_DEVIMR.DMAXINTE USBHS_HSTIMR.DCONNIE USBHS_HSTISR.DCONNI USBHS_HSTISR.DDISCI USBHS_HSTIMR.DDISCIE USBHS_HSTISR.RSTI USBHS_HSTIMR.RSTIE USBHS_HSTISR.RSMEDI USBHS_HSTIMR.RSMEDIE USBHS_HSTISR.RXRSMI USBHS_HSTIMR.RXRSMIE USBHS_HSTISR.HSOFI USBHS_HSTIMR.HSOFIE USBHS_HSTISR.HWUPI USBHS_HSTIMR.HWUPIE USBHS_HSTISR.PXINT USBHS_HSTIMR.PXINTE USBHS_HSTISR.DMAXINT USBHS_HSTIMR.DMAXINTE USBHS_DEVEPTIMRx.TXINE USBHS_DEVEPTISRx.TXINI USBHS_DEVEPTISRx.RXOUTI USBHS_DEVEPTIMRx.RXOUTE USBHS_DEVEPTISRx.RXSTPI USBHS_DEVEPTIMRx.RXSTPE USBHS_DEVEPTISRx.UNDERFI USBHS_DEVEPTIMRx.UNDERFE USBHS_DEVEPTISRx.NAKOUTI USBHS_DEVEPTIMRx.NAKOUTE USBHS_DEVEPTISRx.NAKINI USBHS_DEVEPTIMRx.NAKINE USBHS_DEVEPTISRx.OVERFI USBHS_DEVEPTIMRx.OVERFE USBHS_DEVEPTISRx.STALLEDI USBHS_DEVEPTIMRx.STALLEDE USBHS_DEVEPTISRx.CRCERRI USBHS_DEVEPTIMRx.CRCERRE USBHS_DEVEPTISRx.SHORTPACKET USBHS_DEVEPTIMRx.SHORTPACKETE USBHS_DEVEPTISRx.DTSEQ=MDATA & UESTAX.RXOUTI USBHS_DEVEPTIMRx.MDATAE USBHS_HSTPIPIMRx.RXINE USBHS_HSTPIPISRx.RXINI USBHS_HSTPIPISRx.TXOUTI USBHS_HSTPIPIMRx.TXOUTE USBHS_HSTPIPISRx.TXSTPI USBHS_HSTPIPIMRx.TXSTPE USBHS_HSTPIPISRx.UNDERFI USBHS_HSTPIPIMRx.UNDERFIE USBHS_HSTPIPISRx.PERRI USBHS_HSTPIPIMRx.PERRE USBHS_HSTPIPISRx.NAKEDI USBHS_HSTPIPIMRx.NAKEDE USBHS_HSTPIPISRx.OVERFI USBHS_HSTPIPIMRx.OVERFIE USBHS_HSTPIPISRx.RXSTALLDI USBHS_HSTPIPIMRx.RXSTALLDE USBHS_HSTPIPISRx.CRCERRI USBHS_HSTPIPIMRx.CRCERRE USBHS_HSTPIPISRx.SHORTPACKETI USBHS_HSTPIPIMRx.SHORTPACKETIE USBHS_HSTPIPISRx.NBUSYBK USBHS_HSTPIPIMRx.NBUSYBKE UDDMAX_CONTROL.EOT_IRQ_EN USBHS_DEVDMASTATUSx.EOT_STA USBHS_DEVDMASTATUSx.EOCH_BUFF_STA UDDMAX_CONTROL.EOBUFF_IRQ_EN USBHS_DEVDMASTATUSx.DESC_LD_STA UDDMAX_CONTROL.DESC_LD_IRQ_EN USBHS_HSTDMACONTROLx.EOT_IRQ_EN USBHS_HSTDMASTATUSx.EOT_STA USBHS_HSTDMASTATUSx.EOCH_BUFF_STA USBHS_HSTDMACONTROLx.EOBUFF_IRQ_EN USBHS_HSTDMASTATUSx.DESC_LD_STA USBHS_HSTDMACONTROLx.DESC_LD_IRQ_EN USB Device Endpoint X Interrupt USB Host Pipe X Interrupt USB Device DMA Channel X Interrupt USB Host DMA Channel X Interrupt USBHS_DEVIMR.MSOFE USBHS_DEVIMR.MSOF USBHS_DEVEPTISRx.HBISOINERRI USBHS_DEVEPTIMRx.HBISOINERRE USBHS_DEVEPTISRx.HBISOFLUSHI USBHS_DEVEPTIMRx.HBISOFLUSHE USBHS_DEVEPTISRx.DTSEQ=DATAX & UESTAX.RXOUTI USBHS_DEVEPTIMRx.DATAXE USBHS_DEVEPTISRx.TRANSERR USBHS_DEVEPTIMRx.TRANSERRE USBHS_DEVEPTISRx.NBUSYBK USBHS_DEVEPTIMRx.NBUSYBKE

575SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 Clock Frozen The USBHS can be frozen when the USB line is in the Suspend mode, by writing a one to the USBHS_CTRL.FRZCLK bit, which reduces power consumption. In this case, it is still possible to access the following:  USBHS_CTRL.FRZCLK, USBHS_CTRL.USBE and USBHS_DEVCTRL.LS bits Moreover, when USBHS_CTRL.FRZCLK = 1, only the asynchronous interrupt sources can trigger the USB interrupt:  Wake-up Interrupt (USBHS_DEVISR.WAKEUP)  Host Wake-up Interrupt (USBHS_HSTISR.HWUPI)

37.5.1.4 Speed Control

When the USB interface is in Device mode, the speed selection (Full-speed or High-speed) is performed automatically by the USBHS during the USB reset accordin g to the host speed capability. At the end of the USB reset, the USBHS enables or disables high-speed terminations and pull-up. It is possible to set the USBHS to Full-speed or Low-speed mode via USBHS_DEVCTRL.LS and USBHS_DEVCTRL.SPDCONF. Host Mode When the USB interface is in Host mode, internal pull- down resistors are connected on both D+ and D- and the interface detects the speed of the connected device, which is reflected by the Speed Status (USBHS_SR.SPEED) field.

37.5.1.5 DPRAM Management

Pipes and endpoints can only be allocated in ascending order, from pipe/endpoint 0 to the last pipe/endpoint to be allocated. The user should therefore configure them in the same order. The allocation of a pipe/endpoint x starts when the Endpoint Memory Allocate bit in the Endpoint x Configuration register (USBHS_DEVEPTCFGx.ALLOC) is written to one. Then, the hardware allocate s a memory area in the DPRAM and inserts it between the x-1 and x+1 pipes/end points. The x+1 pipe/endpoint memory window slides up and its data is lost. Note that the following pipe/endpoint memory windows (from x+2) do not slide. Disabling a pipe, by writing a zero to the Pipe x Enabl e bit in the Host Pipe regi ster (USBHS_HSTPIP.PENx), or disabling an endpoint, by writing a zero to the End point x Enable bit in the Device Endpoint register (USBHS_DEVEPT.EPENx), do es not reset the USBHS_DEVEPTCFGx .ALLOC bit or the Pipe/Endpoint configuration:  Pipe Configuration ̶ Pipe Banks (USBHS_HSTPIPCFGx.PBK) ̶ Pipe Size (USBHS_HSTPIPCFGx.PSIZE) ̶ Pipe Token (USBHS_HSTPIPCFGx.PTOKEN) ̶ Pipe Type (USBHS_HSTPIPCFGx.PTYPE) ̶ Pipe Endpoint Number (USBHS_HSTPIPCFGx.PEPNUM) ̶ Pipe Interrupt Request Frequency (USBHS_HSTPIPCFGx.INTFRQ)  Endpoint Configuration ̶ Endpoint Banks (USBHS_DEVEPTCFGx.EPBK) ̶ Endpoint Size (USBHS_DEVEPTCFGx. EPSIZE) ̶ Endpoint Direction (USBHS_DEVEPTCFGx.EPDIR) ̶ Endpoint Type (USBHS_DEVEPTCFGx.EPTYPE)

577SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

37.5.1.6 Pad Suspend

Figure 37-5 shows the pad behavior. Figure 37-5. Pad Behavior  In Idle state, the pad is put in Low-power mode, i.e., the differential receiver of the USB pad is off, and internal pull-downs with a strong value (15 K) are set in HSDP/D and HSDM/DM to avoid floating lines.  In Active state, the pad is working. Figure 37-6 illustrates the pad events leading to a PAD state change. Figure 37-6. Pad Events The USBHS_DEVISR.SUSP bit is set and the Wake-Up Interrupt (USBHS_DEVISR.WAKEUP) bit is cleared when a USB “Suspend” state has been detected on the USB bus. This event automa tically puts the USB pad in Idle state. The detection of a non-id le event sets USBHS_DEVISR.WAKEU P, clears USBHS_DEVISR.SUSP and wakes up the USB pad. The pad goes to the Idle state if the USBHS is disabled or if the USBHS_DEVCTRL.DETACH bit = 1. It returns to the Active state when USBHS_CTRL.USBE = 1 and USBHS_DEVCTRL.DETACH = 0. Idle Active USBHS_CTRL.USBE = 1 & USBHS_DEVCTRL.DETACH = 0 & Suspend USBHS_CTRL.USBE = 0 | USBHS_DEVCTRL.DETACH = 1 | Suspend USBHS_DEVISR.SUSP pu- e k a w n o d e r a e l Cd e t c e t e d d n e p suS Wake-up detected Cleared b y software to acknowledge the interruptUSBHS_DEVISR.WAKEUP PAD State ActiveIdleActive

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 578

37.5.2 USB Device Operation

37.5.2.1 Introduction

In Device mode, the USBHS supports high-, full- and low-speed data transfers. In addition to the default control endpoint, 10 endpoints are provided, which can be configured with an isochronous, bulk or interrupt type, as described in Table 37-1 on page 570. As the Device mode starts in Idle state, the pad consumption is reduced to the minimum.

37.5.2.2 Power-On and Reset

Figure 37-7 describes the USBHS Device mode main states. Figure 37-7. Device Mode Main States After a hardware reset, the USBHS Device mode is in Reset state. In this state:  the USBHS clock is stopped to minimize power consumption (USBHS_CTRL.FRZCLK = 1),  the internal registers of the Device mode are reset,  the endpoint banks are de-allocated,  neither D+ nor D- is pulled up (USBHS_DEVCTRL.DETACH = 1). D+ or D- is pulled up according to the selected speed as soon as the USBHS_DEVCTRL.DETACH bit is written to zero. See “Device Mode” for further details. When the USBHS is enabled (USBHS_CTRL.USBE = 1) in Device mode (U SBHS_CTRL.UIMOD = 1), its Device mode state enters Idle state with minimal power consumption. This does not require the USB clock to be activated. The USBHS Device mode can be disabl ed and reset at any time by disab ling the USBHS (by writing a zero to USBHS_CTRL.USBE) or when the Host mode is enabled (USBHS_CTRL.UIMOD = 0).

37.5.2.3 USB Reset

The USB bus reset is managed by hardware. It is initiated by a connected host. When a USB reset is detected on the USB line, the following operations are performed by the controller:  All endpoints are disabled, except the default control endpoint.  The default control endpoint is reset (see Section 37.5.2.4 for more details).  The data toggle sequence of the default control endpoint is cleared.  At the end of the reset process, the End of Reset (USBHS_DEVISR.EORST) bit is set. Reset Idle HW USBHS_CTRL.USBE = 0 | USBHS_CTRL.UIMOD = 0 <any other state> USBHS_CTRL.USBE = 0 | USBHS_CTRL.UIMOD = 0 & USBHS_CTRL.UIMOD = 1 USBHS_CTRL.USBE = 1 USBHS_HSTCTRL.RESET

579SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16  During a reset, the USBHS automatically switches to High-speed mode if the host is High-speed-capable (the reset is called High-speed reset). The user should observe the USBHS_SR.SPEED field to know the speed running at the end of the reset (USBHS_DEVISR.EORST = 1).

37.5.2.4 Endpoint Reset

An endpoint can be reset at any time by writing a one to the Endpoint x Reset bit USBHS_DEVEPT.EPRSTx. This is recommended before using an endpoint upon hardware reset or when a USB bus reset has been received. This resets:  the internal state machine of the endpoint,  the receive and transmit bank FIFO counters,  all registers of this endpoint (USBHS_DEVEPTCFGx, USBHS_DEVEPTISRx, the Endpoint x Control (USBHS_DEVEPTIMRx) register), except its configuration (USBHS_DEVEPTCFGx.ALLOC, USBHS_DEVEPTCFGx.EPBK, USBHS_DEVEPTCFGx.EPSIZE, USBHS_DEVEPTCFGx.EPDIR, USBHS_DEVEPTCFGx.EPTYPE) and the Data Toggle Sequence (USBHS_DEVEPTISRx.DTSEQ) field. Note: The interrupt sour ces located in USBHS_DEVEPTISRx are not cleared when a USB bus reset has been received. The endpoint configuration remains active and the endpoint is still enabled. The endpoint reset may be associated with a clear of the data toggle sequence as an answer to the CLEAR_FEATURE USB request. This can be achieved by writing a one to the Reset Data Toggle Set bit (RSTDTS) in the Device Endpoint x Control Set register (this sets the Reset Data Toggle bit USBHS_DEVEPTIMRx.RSTDT). In the end, the user has to write a zero to the USBHS_DEVEPT.EPRSTx bit to complete the reset operation and to start using the FIFO.

37.5.2.5 Endpoint Activation

The endpoint is maintained inactive and reset (see Section 37.5.2.4 for more details) as long as it is disabled (USBHS_DEVEPT.EPENx = 0). USBHS_DEVEPTISRx.DTSEQ is also reset. The algorithm represented on Figure 37-8 must be followed in order to activate an endpoint. Figure 37-8. Endpoint Activation Algorithm As long as the endpoint is not correctly configured (USBHS_HSTPIPISRx.CFGOK = 0), the controller does not acknowledge the packets sent by the host to this endpoint. Endpoint Activation USBHS_HSTPIPISRx.CFCFGOK== 1? ERROR Ye s Endpoint Activated Enable the endpoint.USBHS_DEVEPT.EPENx = 1 Test if the endpoint configuration is correct. USBHS_DEVEPTCFGx .EPTYPE .EPDIR .EPSIZE .EPBK .ALLOC Configure the endpoint: - type - direction size number of banks Allocate the configured DPRAM banks. No

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 580 The USBHS_HSTPIPISRx.CFGOK bit is set provided that the configured size and number of banks are correct as compared to the endpoint maximal allowed values (see Table 37-1 on page 570 ) and to the maximal FIFO size (i.e., the DPRAM size). See Section 37.5.1.5 for more details about DPRAM management.

37.5.2.6 Address Setup

The USB device address is set up according to the USB protocol.  After all kinds of resets, the USB device address is 0.  The host starts a SETUP transaction with a SET_ADDRESS (addr) request.  The user writes this address to the USB Address (USBHS_DEVCTRL.UADD) field, and writes a zero to the Address Enable (USBHS_DEVCTRL.ADDEN) bit, so the actual address is still 0.  The user sends a zero-length IN packet from the control endpoint.  The user enables the recorded USB device address by writing a one to USBHS_DEVCTRL.ADDEN. Once the USB device address is configured, the controller filters the packets to accept only those targeting the address stored in USBHS_DEVCTRL.UADD. USBHS_DEVCTRL.UADD and USBHS_DEVCTRL.ADDEN must not be written all at once. USBHS_DEVCTRL.UADD and USBHS_DEVCTRL.ADDEN are cleared:  on a hardware reset,  when the USBHS is disabled (USBHS_CTRL.USBE = 0),  when a USB reset is detected. When USBHS_DEVCTRL.UADD or USBHS_DEVCTRL.ADDEN is cleared, the default device address 0 is used.

37.5.2.7 Suspend and Wake-up

When an idle USB bus state has been detected for 3 ms, the controller sets the Suspend (USBHS_DEVISR.SUSP) interrupt bit. The user may then write a one to the USBHS_CTRL.FRZCLK bit to reduce power consumption. To recover from the Suspend mode, the user should wait for the Wa ke-Up (USBHS_DEVISR.WAKEUP) interrupt bit, which is set when a non-idle event is detected, then write a zero to USBHS_CTRL.FRZCLK. As the USBHS_DEVISR.WAKEUP in terrupt bit is set when a non-idle event is detected, it can occur whether the controller is in the Suspend mode or not. The U SBHS_DEVISR.SUSP and USBHS_DEVISR.WAKEUP interrupts are thus independent, except that one bit is cleared when the other is set.

37.5.2.8 Detach

The reset value of the USBHS_DEVCTRL.DETACH bit is one. It is possible to initiate a device re-enumera tion by simply writing a one, and then a zero, to USBHS_DEVCTRL.DETACH. USBHS_DEVCTRL.DETA CH acts on the pull-up connecti ons of the D+ and D- pads. See “Device Mode” for further details.

37.5.2.9 Remote Wake-up

The Remote Wake-Up request (also known as Upstream Re sume) is the only one the device may send without a host invitation, assuming a host command allowing the device to send such a request was previously issued. The sequence is the following:

581SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 1. The U SBHS must have detected a “Suspend” state on the bus, i.e., the Remote Wake-Up request can only be sent after a USBHS_DEVISR.SUSP interrupt has been set. 2. The user writes a one to the Remote Wake-Up (USBHS_DEVCTRL.RMWKUP) bit to send an upstream resume to the host for a remote wake-up. This will automatically be done by the controller after 5ms of inactivity on the USB bus. 3. When the controller sends the upstream resu me, the Upstream Resume (USBHS_DEVISR.UPRSM) interrupt is set and USBHS_DEVISR.SUSP is cleared. 4. USBHS_DEVCTRL.RMWKUP is cleared at the end of the upstream resume. 5. When the controller detects a valid “End of Resume” signal from the host, the End of Resume (USBHS_DEVISR.EORSM) interrupt is set.

37.5.2.10 STALL Request

For each endpoint, the STALL management is performed using:  the STALL Request (USBHS_DEVEPTIMRx.STALLRQ) bit to initiate a STALL request,  the STALLed Interrupt (USBHS_DEVEPTISRx.STALLEDI) bit, which is set when a STALL handshake has been sent. To answer the next request with a STALL handshake, USBHS_DEVEPTIMRx.STALLRQ has to be set by writing a one to the STALL Request Set (USBHS_DEVEPTIERx.STALLRQS) bit. All following requests are discarded (USBHS_DEVEPTISRx.RX OUTI, etc. is not be set) and handshaked with a STALL until the USBHS_DEVEPTIMRx.STALLRQ bit is cleared, which is done when a new SETUP packet is received (for control endpoints) or when the STALL Request Clear (USBHS_DEVEPTIMRx.STALLRQC) bit is written to one. Each time a STALL handshake is sent, the USBHS_DEVEPTISRx.STALLEDI bit is set by the USBHS and the PEP_x interrupt is set. Special Considerations for Control Endpoints If a SETUP packet is received into a control endpoint for which a STALL is requested, the Received SETUP Interrupt (USBHS_DEVEPTISR x.RXSTPI) bit is set and US BHS_DEVEPTIMRx.STALLRQ and USBHS_DEVEPTISRx.STALLEDI are cleared. The SETUP has to be ACKed. This simplifies the enumeration process management. If a command is not supported or contains an error, the user requests a STALL and can return to the main task, waiting for the next SETUP request. STALL Handshake and Retry Mechanism The retry mechanism has priority over the STALL handshake. A STALL handshake is sent if the USBHS_DEVEPTIMRx.STALLRQ bit is set and if no retry is required.

37.5.2.11 Management of Control Endpoints

A SETUP request is always ACKed. When a new SETUP packet is received, the USBHS_DEVEPTISRx.RXSTPI is set; the Received OUT Data Interrupt (USBHS_DEVEPTISRx.RXOUTI) bit is not. The FIFO Control (USBHS_DEVEPTIMRx.FIF OCON) bit and the Re ad/Write Allowed (USBHS_DEVEPTISRx.RWALL) bit are irrele vant for control endpoints. The user neve r uses them on these endpoints. When read, their values are always zero. Control endpoints are managed using:  the USBHS_DEVEPTISRx.RXSTPI bit, which is set when a new SETUP packet is received and which is cleared by firmware to acknowledge the packet and to free the bank;  the USBHS_DEVEPTISRx.RXOUTI bit, which is set when a new OUT packet is received and which is cleared by firmware to acknowledge the packet and to free the bank;

583SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 wait for RXOUTI OR TXINI if RXOUTI, then clear bit and return if TXINI, then continue Once the OUT status stage has been received, the US BHS waits for a SETUP request. The SETUP request has priority over any other request and has to be ACKed. This means that any other bit should be cleared and the FIFO reset when a SETUP is received. The user has to consider that the byte counter is reset when a zero-length OUT packet is received.

37.5.2.12 Management of IN Endpoints

IN packets are sent by the USB device controller upon IN requests from the host. All data which acknowledges or not the bank can be written when it is full. The endpoint must be configured first. The USBHS_DEVEPTISRx.TXINI bit is set at the same time as U SBHS_DEVEPTIMRx.FI FOCON when the current bank is free. This triggers a PEP_x interrupt if the Trans mitted IN Data Interrupt Enable (USBHS_DEVEPTIMRx.TXINE) bit is one. USBHS_DEVEPTISRx.TXINI is cleared by software (by writing a one to the Transmitted IN Data Interrupt Clear bit (USBHS_DEVEPTIDRx.TXINIC) to acknowledge the interrupt, which has no effect on the endpoint FIFO. The user then writes into the FIFO and writes a one to the FIFO Control Clear (USBHS_DEVEPTIDRx.FIFOCONC) bit to clear the USBHS_DEVEPTIMRx.F IFOCON bit. This allows the USBHS to send the data. If the IN endpoint is composed of multiple banks, this also switches to the next bank. The USBHS_DEVEPTISRx.TXINI and USBHS_DEVEPTIMRx.FIFOC ON bits are updated in accordance with the status of the next bank. USBHS_DEVEPTISRx.TXINI is always cleared before clearing USBHS_DEVEPTIMRx.FIFOCON. The USBHS_DEVEPTISRx.RWALL bi t is set when the current bank is not fu ll, i.e., when the software can write further data into the FIFO. Figure 37-11. Example of an IN Endpoint with one Data Bank IN DATA (bank 0) ACK USBHS_DEVEPTISRx.TXINI USBHS_DEVEPTIMRx.FIFOCON HW write data to CPU BANK 0 SW SW SW SW INNAK write data to CPU BANK 0

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 584 Figure 37-12. Example of an IN Endpoint with two Data Banks IN DATA (bank 0) ACK USBHS_DEVEPTISRx.TXINI USBHS_DEVEPTIMRx.FIFOCON write data to CPU BANK 0 SW SW SW SW IN DATA (bank 1) ACK write data to CPU BANK 1 SW HW write data to CPU BANK0

585SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 Detailed Description The data is written as follows:  When the bank is empty, USBHS_DEVEPTISRx.TXINI and USBHS_DEVEPTIMRx.FIFOCON are set, which triggers a PEP_x interrupt if USBHS_DEVEPTIMRx.TXINE = 1.  The user acknowledges the interrupt by clearing USBHS_DEVEPTISRx.TXINI.  The user writes the data into the current bank by using the USB Pipe/Endpoint nFIFO Data (USBFIFOnDATA) register, until all the data frame is written or the bank is full (in which case USBHS_DEVEPTISRx.RWALL is cleared and the Byte Count (USBHS_DEVEPTISRx.BYCT) field reaches the endpoint size).  The user allows the controller to send the bank and switches to the next bank (if any) by clearing USBHS_DEVEPTIMRx.FIFOCON. If the endpoint uses several banks, the current one can be written while the previous one is being read by the host. Then, when the user clears USBH S_DEVEPTIMRx.FIFOCON, the following bank may already be free and USBHS_DEVEPTISRx.TXINI is set immediately. An “Abort” stage can be produced when a zero-length OUT packet is received during an IN stage of a control or isochronous IN tran saction. The Kill IN Bank (USBHS_DEVEPTIMRx.KI LLBK) bit is used to kill the last written bank. The best way to manage this abort is to apply the algorithm represented in Figure 37-13. Figure 37-13. Abort Algorithm

37.5.2.13 Management of OUT Endpoints

OUT packets are sent by the host. All data which acknowledges or not the bank can be read when it is empty. The endpoint must be configured first. The USBHS_DEVEPTISRx.RXOUTI bit is set at the same time as USBHS_DEVEPTIMRx.FIFOCON when the current bank is full. This trigge rs a PEP_x interrupt if the Received OUT Data Interrupt Enable (USBHS_DEVEPTIMRx.RXOUTE) bit is one. USBHS_DEVEPTISRx.RXOUTI is cleared by software (by writing a one to the Received OUT Data Interrupt Clear (USBHS_DEVEPTICRx.RXOUTIC) bit to acknowledge the interrupt, which has no effect on the endpoint FIFO. Endpoint Abort Abort Done Abort is based on the fact that no bank is busy, i.e., that nothing has to be sent Disable the USBHS_DEVEPTISRx.TXINI interrupt. USBHS_DEVEPT. EPRSTx = 1 USBHS_DEVEPTISRx.NBUSYBK == 0? Yes USBHS_DEVEPTIDRx.TXINEC = 1 No USBHS_DEVEPTIERx.KILLBKS = 1 USBHS_DEVEPTIMRx.KILLBK == 1?Yes Kill the last written bank. Wait for the end of the procedure No

587SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 Detailed Description The data is read as follows:  When the bank is full, USBHS_DEVEPTISRx.RXOUTI and USBHS_DEVEPTIMRx.FIFOCON are set, which triggers a PEP_x interrupt if USBHS_DEVEPTIMRx.RXOUTE = 1.  The user acknowledges the interrupt by writing a one to USBHS_DEVEPTICRx.RXOUTIC in order to clear USBHS_DEVEPTISRx.RXOUTI.  The user can read the byte count of the current bank from USBHS_DEVEPTISRx.BYCT to know how many bytes to read, rather than polling USBHS_DEVEPTISRx.RWALL.  The user reads the data from the current bank by using the USBFIFOnDATA register, until all the expected data frame is read or the bank is empty (in which case USBHS_DEVEPTISRx.RWALL is cleared and USBHS_DEVEPTISRx.BYCT reaches zero).  The user frees the bank and switches to the next bank (if any) by clearing USBHS_DEVEPTIMRx.FIFOCON. If the endpoint uses several banks, the current one can be read while the following one is being written by the host. Then, when the user clears USBH S_DEVEPTIMRx.FIFOCON, the following bank can already be read and USBHS_DEVEPTISRx.RXOUTI is set immediately. In High-speed mode, the PING and NYET protocols are handled by the USBHS.  For a single bank, a NYET handshake is always sent to the host (on Bulk-out transaction) to indicate that the current packet is acknowledged but there is no room for the next one.  For a double bank, the USBHS responds to the OUT/DATA transaction with an ACK handshake when the endpoint accepted the data successfully and has room for another data payload (the second bank is free).

37.5.2.14 Underflow

This error only exists for isochronous IN/OUT endpoints. It sets the Underflow Interrupt (USBHS_DEVEPTISRx. UNDERFI) bit, which triggers a PEP_x interrupt if the Underflow Interrupt Enable (USBHS_DEVEPTIMRx.UNDERFE) bit is one.  An underflow can occur during the IN stage if the host attempts to read from an empty bank. A zero-length packet is then automatically sent by the USBHS.  An underflow cannot occur during the OUT stage on a CPU action, since the user may only read if the bank is not empty (USBHS_DEVEPTISRx.RXOUTI = 1 or USBHS_DEVEPTISRx.RWALL = 1).  An underflow can also occur during the OUT stage if the host sends a packet while the bank is already full. Typically, the CPU is not fast enough. The packet is lost.  An underflow cannot occur during the IN stage on a CPU action, since the user may only write if the bank is not full (USBHS_DEVEPTISRx.TXINI = 1or USBHS_DEVEPTISRx.RWALL = 1).

37.5.2.15 Overflow

This error exists for all endpoint types. It sets the Overflow in terrupt (USBHS_DEVEPTISRx .OVERFI) bit, which triggers a PEP_x interrupt if the Overflow Interrupt Enable (USBHS_DEVEPTIMRx.OVERFE) bit is one.  An overflow can occur during the OUT stage if the host attempts to write into a bank which is too small for the packet. The packet is acknowledged and the USBHS_DEVEPTISRx.RXOUTI bit is set as if no overflow had occurred. The bank is filled with all the first bytes of the packet that fit in.  An overflow cannot occur during the IN stage on a CPU action, since the user may only write if the bank is not full (USBHS_DEVEPTISRx.TXINI = 1 or USBHS_DEVEPTISRx.RWALL = 1).

37.5.2.16 HB IsoIn Error

This error only exists for high-bandwidth isochronous IN endpoints. At the end of the microframe, if at least one packet has been sent to the host and fewer banks than expected have been validated (by clearing the USBHS_DEVEPTIMRx.U SBHS_DEVEPTIMRx.FIFOCON) for this microframe, it

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 588 sets the USBHS_DEVEPTISRx.HBISOINERRORI bit, which trigge rs a PEP_x interrupt if the High Bandwidth Isochronous IN Error Interrupt Enable (HBISOINERRORE) bit is one. For example, if the Number of Tr ansactions per MicroFrame for Isoc hronous Endpoint (NBTRANS) field in USBHS_DEVEPTCFGx is three (three transactions per mi croframe), only two banks are filled by the CPU (three expected) for the current microframe. Then, the HBISOINERRI interrupt is generated at the end of the microframe. Note that an UNDERFI interrupt is also generated (with an automatic zero-length-packet), except in the case of a missing IN token.

37.5.2.17 HB IsoFlush

This error only exists for high-bandwidth isochronous IN endpoints. At the end of the microframe, if at least one packet has been sent to the host and there is a missing IN token during this microframe, the bank(s) destined to this microframe is/are flushed out to ensure a good data synchronization between the host and the device. For example, if NBTRANS is three (three transactions pe r microframe) and if only the first IN token (among three) is well received by the USBHS, the last two banks are discarded.

37.5.2.18 CRC Error

This error only exists for isochronous OUT endpoints. It sets the CRC Error Interrupt (USBHS_DEVEPTISRx.CRCERRI) bit, which triggers a PEP_x interrupt if the CRC Error Interrupt Enable (USBHS_DEVEPTIMRx.CRCERRE) bit is one. A CRC error can occur during the OUT stage if the USBHS detects a corrupted received packet. The OUT packet is stored in the bank as if no CRC error had occurred (USBHS_DEVEPTISRx.RXOUTI is set).

37.5.2.19 Interrupts

See the structure of the USB device interrupt system on Figure 37-3 on page 574. There are two kinds of device interrupts: processing, i.e., their generation is part of the normal processing, and exception, i.e., errors (not related to CPU exceptions). Global Interrupts The processing device global interrupts are:  Suspend (USBHS_DEVISR.SUSP)  Start of Frame (USBHS_DEVISR.SOF) interrupt with no frame number CRC error - the Frame Number CRC Error (USBHS_DEVFNUM.FNCERR) bit is zero.  Micro Start of Frame (USBHS_DEVISR.MSOF) with no CRC error  End of Reset (USBHS_DEVISR.EORST)  Wake-Up (USBHS_DEVISR.WAKEUP)  End of Resume (USBHS_DEVISR.EORSM)  Upstream Resume (USBHS_DEVISR.UPRSM)  Endpoint x (USBHS_DEVISR.PEP_x)  DMA Channel x (USBHS_DEVISR.DMA_x) The exception device global interrupts are:  Start of Frame (USBHS_DEVISR.SOF) with a frame number CRC error (USBHS_DEVFNUM.FNCERR = 1)  Micro Start of Frame (USBHS_DEVFNUM.FNCERR.MSOF) with a CRC error Endpoint Interrupts The processing device endpoint interrupts are:  Transmitted IN Data (USBHS_DEVEPTISRx.TXINI)  Received OUT Data (USBHS_DEVEPTISRx.RXOUTI)

589SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16  Received SETUP (USBHS_DEVEPTISRx.RXSTPI)  Short Packet (USBHS_DEVEPTISRx.SHORTPACKET)  Number of Busy Banks (USBHS_DEVEPTISRx.NBUSYBK)  Received OUT Isochronous Multiple Data (DTSEQ=MDATA & USBHS_DEVEPTISRx.RXOUTI)  Received OUT Isochronous DataX (DTSEQ=DATAX & USBHS_DEVEPTISRx.RXOUTI) The exception device endpoint interrupts are:  Underflow (USBHS_DEVEPTISRx.UNDERFI)  NAKed OUT (USBHS_DEVEPTISRx.NAKOUTI)  High-Bandwidth Isochronous IN Error (USBHS_DEVEPTISRx.HBISOINERRI)  NAKed IN (USBHS_DEVEPTISRx.NAKINI)  High-Bandwidth Isochronous IN Flush error (USBHS_DEVEPTISRx.HBISOFLUSHI)  Overflow (USBHS_DEVEPTISRx.OVERFI)  STALLed (USBHS_DEVEPTISRx.STALLEDI)  CRC Error (USBHS_DEVEPTISRx.CRCERRI)  Transaction Error (USBHS_DEVEPTISRx.ERRORTRANS) DMA Interrupts The processing device DMA interrupts are:  End of USB Transfer Status (USBHS_DEVDMASTATUSx.END_TR_ST)  End of Channel Buffer Status (USBHS_DEVDMASTATUSx.END_BF_ST)  Descriptor Loaded Status (USBHS_DEVDMASTATUSx.DESC_LDST) There is no exception device DMA interrupt.

37.5.2.20 Test Modes

When written to one, the USBHS_DEVC TRL.TSTPCKT bit switches the USB device controller to a “Test-packet” mode: The transceiver repeatedly transmits the packet stored in the current bank. USBHS_DEVCTRL.TSTPCKT must be written to zero to exit the Test-packet mode. The endpoint is reset by software after a Test-packet mode. This enables the testing of rise and falling times, eye patterns, jitter, and any other dynamic waveform specifications. The flow control used to send the packets is as follows:  USBHS_DEVCTRL.TSTPCKT=1;  Store data in an endpoint bank  Write a zero to the USBHS_DEVEPTIDRx.FIFOCON bit To stop the Test-packet mode, write a zero to the USBHS_DEVCTRL.TSTPCKT bit.

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 590

37.5.3 USB Host Operation

37.5.3.1 Description of Pipes

For the USBHS in Host mode, the term “pipe” is used instead of “endpoint” (used in Device mode). A host pipe corresponds to a device endpoint, as described in Figure 37-16 (from the USB Specification). Figure 37-16. USB Communication Flow In Host mode, the USBHS associates a pipe to a de vice endpoint, considering the device configuration descriptors.

37.5.3.2 Power-On and Reset

Figure 37-17 describes the USBHS Host mode main states. Figure 37-17. Host Mode Main States After a hardware reset, the USBHS Host mode is in the Reset state. When the USBHS is enabled (USBHS_CTRL.USBE = 1) in Host mode (USBHS_CTRL.UIMOD = 0), it goes to the Idle state. In this state, the controller waits for a device connection with a minimal power consumption. The USB pad should be in the Idle state. Once a device is connec ted, the USBHS enters the Ready state, which does not require the USB clock to be activated. Ready Idle Device Disconnection <anyother state> Device Connection Macro off Clock stopped Device Disconnection SuspendSOFE = 1 SOFE = 0

591SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 The controller enters the Suspend state when the USB bus is in a “Suspend” state, i.e., when the Host mode does not generate the “Start of Frame (SOF)”. In this state, the USB consumption is minimal. The Host mode exits the Suspend state when starting to generate the SOF over the USB line.

37.5.3.3 Device Detection

A device is detected by the USBHS Host mode when D+ or D- is no longer tied low, i.e., when the device D+ or D- pull-up resistor is connected. The bit USBHS_SFR.VBUSRQS must be set to ‘1’ to enable this detection. Note: The VBUS supply is not managed by the USBHS interface. It must be generated on-board. The device disconnection is detected by the host controller when both D+ and D- are pulled down.

37.5.3.4 USB Reset

The USBHS sends a USB bus reset when the user writes a one to the Send USB Reset bit in the Host General Control register (USBHS_HSTCTRL.RESET). The USB Reset Sent Interrupt bit in the Host Global Interrupt Status register (USBHS_HSTISR.RSTI) is set when the USB reset has been sent. In this case, all pipes are disabled and de-allocated. If the bus was previously in a “Suspend” state (the Start of Frame Generation Enable (USBHS_HSTCTRL.SOFE) bit is zero), the USBHS automatically switches to the “Resume” state, the Host Wake-Up Interrupt (USBHS_HSTISR.HWUPI) bit is set and the USBHS_HSTCTR L.SOFE bit is set in order to generate SOFs or micro SOFs immediately after the USB reset. At the end of the reset, th e user should check the U SBHS_SR.SPEED field to know the speed running according to the peripheral capability (LS.FS/HS).

37.5.3.5 Pipe Reset

A pipe can be reset at any time by writing a one to the Pipe x Reset (USBHS_HSTPIP.PRSTx) bit. This is recommended before using a pipe upon hardware reset or when a USB bus reset has been sent. This resets:  the internal state machine of the pipe,  the receive and transmit bank FIFO counters,  all the registers of the pipe (USBHS_HSTPIPCFGx, USBHS_HSTPIPISRx, USBHS_HSTPIPIMRx), except its configuration (USBHS_HSTPIPCFGx.ALLOC, USBHS_HSTPIPCFGx.PBK, USBHS_HSTPIPCFGx.PSIZE, USBHS_HSTPIPCFGx.PTOKEN, USBHS_HSTPIPCFGx.PTYPE, USBHS_HSTPIPCFGx.PEPNUM, USBHS_HSTPIPCFGx.INTFRQ) and its Data Toggle Sequence field (USBHS_HSTPIPISRx.DTSEQ). The pipe configuration remains active and the pipe is still enabled. The pipe reset may be associated with a clear of the data toggle sequence. This can be achieved by setting the Reset Data Toggle bit in the Pipe x Control register (USBHS_HSTPIPIMRx.RSTDT) (by writing a one to the Reset Data Toggle Set bit in the Pipe x Control Set register (USBHS_HSTPIPIERx.RSTDTS)). In the end, the user has to write a zero to the USBH S_HSTPIP.PRSTx bit to complete the reset operation and to start using the FIFO.

37.5.3.6 Pipe Activation

The pipe is maintained inactive and reset (see Section 37.5.3.5 for more details) as long as it is disabled (USBHS_HSTPIP.PENx = 0). The Data Toggle Sequence field (USBHS_HSTPIPISRx.DTSEQ) is also reset. The algorithm represented on Figure 37-18 must be followed in order to activate a pipe.

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 592 Figure 37-18. Pipe Activation Algorithm As long as the pipe is not correctly configured (USBHS_HSTPIPISRx.CFGOK = 0), the controller cannot send packets to the device through this pipe. The USBHS_HSTPIPISRx.CFGOK bit is only set if the configured size and number of banks are correct as compared to their maximal allowed values for the pipe (see Table 37-1 on page 570) and to the maximal FIFO size (i.e., the DPRAM size). See Section 37.5.1.5 for more details about DPRAM management. Once the pipe is correctly configured (USBHS_HSTPIPISRx.CFGOK = 1), only the USBHS_HSTPIPCFGx.PTOKEN and USBH S_HSTPIPCFGx.INTFRQ fields can be written by software. USBHS_HSTPIPCFGx.INTFRQ is meaningless for non-interrupt pipes. When starting an enumeration, the user gets the devi ce descriptor by sending a GET_DESCRIPTOR USB request. This descriptor contains the maximal packet size of the device default control endpoint (bMaxPacketSize0) and the user reconfigures the size of the default control pipe with this size parameter.

37.5.3.7 Address Setup

Once the device has answered the first host requests wi th the default device address 0, the host assigns a new address to the device. The host controller has to send a USB reset to the device and to send a SET_ADDRESS (addr) SETUP request with the new address to be used by the device. Once this SETUP transaction is over, the user writes the new address into the USB Host Address fo r Pipe x field in the USB Host Device Address register (HSTADDR.HSTADDRPx). All the following requests on all pipes are then performed using this new address. When the host controller sends a USB reset, the HSTADD RPx field is reset by hardware and the following host requests are performed using the default device address 0.

37.5.3.8 Remote Wake-up

The controller Host mode enters the Suspend state when the USBHS_HSTCTRL.SOFE bit is written to zero. No more “Start of Frame” is sent on the USB bus and the USB device enters the Suspend state 3 ms later. The device awakes the host by sending an Upstream Resume (Remote Wake-Up feature). When the host controller detects a non-idle state on the USB bus, it sets the Host Wa ke-Up interrupt (USBHS_HSTISR.HWUPI) bit. If the non-idle bus state corresponds to an Upstre am Resume (K state), the Upstream Resume Received Interrupt (USBHS_HSTISR.RXRSMI) bit is set. The user has to generate a Downstream Resume within 1 ms and Pipe Activation USBHS_HSTPIPISRx.CFGOK == 1? ERROR Ye s Pipe Activated Enable the pipe.USBHS_HSTPIP .PENx = 1 Test if the pipe configuration is correct. USBHS_HSTPIPPCFGx .INTFRQ .PEPNUM .PTYPE .PTOKEN .PSIZE .PBK .ALLOC Configure the pipe: - interrupt request frequency - endpoint number - type - size - number of banks Allocate the configured DPRAM banks No

593SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 for at least 20 ms by writing a one to the Send USB Resume (USBHS_HSTCTRL.RESUME) bit. It is mandatory to write a one to USBHS_HSTCTRL.SOFE before writing a one to USBHS_HS TCTRL.RESUME to enter the Ready state, otherwise USBHS_HSTCTRL.RESUME has no effect.

37.5.3.9 Management of Control Pipes

A control transaction is composed of three stages:  SETUP  Data (IN or OUT)  Status (OUT or IN) The user has to change the pipe token according to each stage. For the control pipe only, each token is assigned a specific initial data toggle sequence:  SETUP: Data0  IN: Data1  OUT: Data1

37.5.3.10 Management of IN Pipes

IN packets are sent by the USB device controller upon IN requests from the host. All data which acknowledges or not the bank can be read when it is empty. The pipe must be configured first. When the host requires data from the device, the user has to first select the IN Request mode with the IN Request Mode bit in the Pipe x IN Request register (USBHS_HSTPIPINRQx.INMODE):  When USBHS_HSTPIPINRQx.INMODE = 0, the USBHS performs (INRQ + 1) IN requests before freezing the pipe.  When USBHS_HSTPIPINRQx.INMODE = 1, the USBHS performs IN requests endlessly when the pipe is not frozen by the user. The generation of IN requests starts when the pipe is unfrozen (the Pipe Freeze (USBHS_HSTPIPIMRx.PFREEZE) field in USBHS_HSTPIPIMRx is zero). The Received IN Data Interrupt (USBH S_HSTPIPISRx.RXINI) bit is set at th e same time as the FIFO Control (USBHS_HSTPIPIMRx.FIFOCON) bit when the current bank is full. This triggers a PEP_x interrupt if the Received IN Data Interrupt Enable (USBHS_HSTPIPIMRx.RXINE) bit is one. USBHS_HSTPIPISRx.RXINI is cleared by software (by writing a one to the Received IN Data Interrupt Clear bit in the Host Pipe x Clear register (USBH S_HSTPIPIDRx.RXINIC)) to acknowled ge the interrupt, which has no effect on the pipe FIFO. The user then reads from the FIFO and clears the USBHS_HSTPIPIMRx.FIFOCON bit (by writing a one to the FIFO Control Clear (USBHS_HSTPIPIDRx.FIFOCONC) bit) to free the bank. If the IN pipe is composed of multiple banks, this also switches to the next bank. The USBHS_HSTPIPISRx.RXINI and USBHS_HSTPIPIMRx.FIFOCON bits are updated in accordance with the status of the next bank. USBHS_HSTPIPISRx.RXINI is always cleared before clearing USBHS_HSTPIPIMRx.FIFOCON. The Read/Write Allowed (USBHS_HSTPIPIS Rx.RWALL) bit is set when the current bank is not empty, i.e., when the software can read further data from the FIFO.

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 594 Figure 37-19. Example of an IN Pipe with one Data Bank Figure 37-20. Example of an IN Pipe with two Data Banks

37.5.3.11 Management of OUT Pipes

OUT packets are sent by the host. All data which acknowledges or not the bank can be written when it is full. The pipe must be configured and unfrozen first. The Transmitted OUT Data Interrupt (USBHS_HSTPIPI SRx.TXOUTI) bit is set at the same time as USBHS_HSTPIPIMRx.FIFOCON when the current bank is free. This triggers a PEP_x interrupt if the Transmitted OUT Data Interrupt Enable (USBHS_HSTPIPIMRx.TXOUTE) bit is one. USBHS_HSTPIPISRx.TXOUTI is cleared by software (by writing a one to the Transmitted OUT Data Interrupt Clear (USBHS_HSTPIPIDRx.TXOUTIC) bit to acknowledge the interrupt, which has no effect on the pipe FIFO. The user then writes into the FIFO and clears the USBHS_HSTPIPIDRx.FIFOCON bit to allow the USBHS to send the data. If the OUT pipe is composed of multiple banks, this also switches to the next bank. The USBHS_HSTPIPISRx.TXOUTI and USBHS_HSTPIPIMRx.F IFOCON bits are updated in accordance with the status of the next bank. USBHS_HSTPIPISRx.TXOUTI is always cleared before clearing USBHS_HSTPIPIMRx.FIFOCON. The USBHS_HSTPIPISRx.RWALL bit is set when the current bank is not full, i.e., when the software can write further data into the FIFO. Notes: 1. If the user decides to switch to the Suspend state (by writing a zero to the USBHS_HSTCTRL.SOFE bit) while a bank is ready to be sent, the USBHS automatically exits this state and the bank is sent. 2. In High-speed operating mode, the host controller automa tically manages the PING protocol to maximize the USB bandwidth. The user can tune the PING protocol by handling the Ping Enable (PINGEN) bit and the bInterval IN DATA (bank 0) ACK USBHS_HSTPIPISRx.RXINI USBHS_HSTPIPIMRx.FIFOCON HW IN DATA (bank 0) ACK HW SW SW SW read data from CPU BANK 0 read data from CPU BANK 0 IN DATA (bank 0) ACK HW IN DATA (bank 1) ACK SW SWread data from CPU BANK 0 HW SW read data from CPU BANK 1 USBHS_HSTPIPISRx.RXINI USBHS_HSTPIPIMRx.FIFOCON

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 596

37.5.3.12 CRC Error

This error exists only for isochronous IN pipes. It sets the CRC Error Interrupt (USBHS_HSTPIPISRx.CRCERRI) bit, which triggers a PEP_x interrupt if then the CRC Error Interrupt Enable (USBHS_HSTPIPIMRx.CRCERRE) bit is one. A CRC error can occur during IN stage if the USBHS detects a corrupted received packet. The IN packet is stored in the bank as if no CRC error had occurred (USBHS_HSTPIPISRx.RXINI is set).

37.5.3.13 Interrupts

See the structure of the USB host interrupt system on Figure 37-3 on page 574. There are two kinds of host interrupts: processing, i.e., their generation is part of the normal processing, and exception, i.e., errors (not related to CPU exceptions). Global Interrupts The processing host global interrupts are:  Device Connection (USBHS_HSTISR.DCONNI)  Device Disconnection (USBHS_HSTISR.DDISCI)  USB Reset Sent (USBHS_HSTISR.RSTI)  Downstream Resume Sent (USBHS_HSTISR.RSMEDI)  Upstream Resume Received (USBHS_HSTISR.RXRSMI)  Host Start of Frame (USBHS_HSTISR.HSOFI)  Host Wake-Up (USBHS_HSTISR.HWUPI)  Pipe x (USBHS_HSTISR.PEP_x)  DMA Channel x (USBHS_HSTISR.DMAxINT) There is no exception host global interrupt. Pipe Interrupts The processing host pipe interrupts are:  Received IN Data (USBHS_HSTPIPISRx.RXINI)  Transmitted OUT Data (USBHS_HSTPIPISRx.TXOUTI)  Transmitted SETUP (USBHS_HSTPIPISRx.TXSTPI)  Short Packet (USBHS_HSTPIPISRx.SHORTPACKETI)  Number of Busy Banks (USBHS_HSTPIPISRx.NBUSYBK) The exception host pipe interrupts are:  Underflow (USBHS_HSTPIPISRx.UNDERFI)  Pipe Error (USBHS_HSTPIPISRx.PERRI)  NAKed (USBHS_HSTPIPISRx.NAKEDI)  Overflow (USBHS_HSTPIPISRx.OVERFI)  Received STALLed (USBHS_HSTPIPISRx.RXSTALLDI)  CRC Error (USBHS_HSTPIPISRx.CRCERRI) DMA Interrupts The processing host DMA interrupts are:  The End of USB Transfer Status (USBHS_HSTDMASTATUSx.END_TR_ST)  The End of Channel Buffer Status (USBHS_HSTDMASTATUSx.END_BF_ST)  The Descriptor Loaded Status (USBHS_HSTDMASTATUSx.DESC_LDST) There is no exception host DMA interrupt.

597SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

37.5.4 USB DMA Operation

USB packets of any length may be transferred when requ ired by the USBHS. These transfers always feature sequential addressing. Such characteristics mean that in case of high USBHS throughput, both AHB ports benefit from “incrementing burst of unspecified length” since the average access latency of AHB slaves can then be reduced. The DMA uses word “incrementing burst of unspecified length” of up to 256 beats for both data transfers and channel descriptor loading. A burst may last on the AHB busses for the duration of a whole USB packet transfer, unless otherwise broken by the AHB arbitration or the AHB 1-Kbyte boundary crossing. Packet data AHB bursts may be locked on a DMA buffer basis for drastic overall AHB bus bandwidth performance boost with paged memories. This prevents large AHB bursts from being broken in case of conflict with other AHB bus masters, thus avoiding access latencies due to memory row changes. This means up to 128 words single cycle unbroken AHB bursts for bulk pipes/endpoints and 256 words single cycle unbroken bursts for isochronous pipes/endpoints. This maximal burst length is then co ntrolled by the lowest programmed USB Pipe/Endpoint Size (USBHS_HSTPIPCFGx.PSIZE / USBHS_DEVEPTC FGx.EPSIZE) and the Buffer Byte Length (USBHS_HSTDMACONTROLx.BUFF_LENGTH / USBHS_DEVDMACONTROLx.BUFF_LENGTH) fields. The USBHS average throughput can reach nearly 480 Mbps. Its average access latency decreases as burst length increases due to the zero wait-state side effect of unchanged pipe/endpoint. Word access allows reducing the AHB bandwidth required for the USB by four, as compared to native byte access. If at least 0 wait-state word burst capability is also provided by the other DMA AHB bus slaves, each DMA AHB bus needs less than 60% bandwidth allocation for full USB bandwidth usage at 33 MHz, and less than 30% at 66 MHz. Figure 37-24. Example of a DMA Chained List Data Buffer 1 Data Buffer 2 Data Buffer 3 Memory Area Transfer Descriptor Next Descriptor Address AHB Address Control Transfer Descriptor Transfer Descriptor USB DMA Channel X Registers (Current Transfer Descriptor) Next Descriptor Address AHB Address Control NULL Status Next Descriptor Address AHB Address Control Next Descriptor Address AHB Address Control

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 598

37.5.5 USB DMA Channel Transfer Descriptor

The DMA channel transfer descriptor is loaded from the memory. The following structures apply: Offset 0:  The address must be aligned: 0xXXXX0  Next Descriptor Address Register: USBHS_xxxDMANXTDSCx Offset 4:  The address must be aligned: 0xXXXX4  DMA Channelx Address Register: USBHS_xxxDMAADDRESSx Offset 8:  The address must be aligned: 0xXXXX8  DMA Channelx Control Register: USBHS_xxxDMACONTROLx To use the DMA channel transfer descriptor, fill the structures with the correct values (as described in the following pages), then write directly in USBHS_xxxDMANXTDSCx the address of the descriptor to be used first. Then write 1 in the USBHS_xxxDMACONTROLx.LDNXT_DSC bit (load next channel transfer descriptor). The descriptor is automatically loaded upon pipe x / endpoint x request for packet transfer.

599SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

37.6 USB High-Speed (USBHS) User Interface

Table 37-4. Register Mapping Offset Register Name Access Reset 0x0000 Device General Control Register USBHS_DEVCTRL Read/Write 0x00000100 0x0004 Device Global Interrupt Status Register USBHS_DEVISR Read-only 0x00000000 0x0008 Device Global Interrupt Clear Register USBHS_DEVICR Write-only 0x000C Device Global Interrupt Set Register USBHS_DEVIFR Write-only 0x0010 Device Global Interrupt Mask Register USBHS_DEVIMR Read-only 0x00000000 0x0014 Device Global Interrupt Disable Register USBHS_DEVIDR Write-only 0x0018 Device Global Interrupt Enable Register USBHS_DEVIER Write-only 0x001C Device Endpoint Register USBHS_DEVEPT Read/Write 0x00000000 0x0020 Device Frame Number Register USBHS_DEVFNUM Read-only 0x00000000 0x0100 + (n * 0x04) + 0x00 Device Endpoint Confi guration Register USBHS_DEVEPTCFG Read/Write 0x00002000 0x0100 + (n * 0x04) + 0x30 Device Endpoint St atus Register USBHS_DEVEPTISR Read-only 0x00000100 0x0100 + (n * 0x04) + 0x60 Device Endpoint Clear Register USBHS_DEVEPTICR Write-only 0x0100 + (n * 0x04) + 0x90 Device Endpoint Set Register USBHS_DEVEPTIFR Write-only 0x0100 + (n * 0x04) + 0x0C0 Device Endpoint Mask Register USBHS_DEVEPTIMR Read-only 0x00000000 0x0100 + (n * 0x04) + 0x0F0 Device Endpoint Enable Register USBHS_DEVEPTIER Write-only 0x0100 + (n * 0x04) + 0x0120 Device Endpoint Disable Register USBHS_DEVEPTIDR Write-only 0x0300 + (n * 0x10)+0x00 Device DMA Channel Next Descriptor Address Register USBHS_DEVDMANXTDSC Read/Write 0x00000000 0x0300 + (n * 0x10)+0x04 Device DMA Channel Address Register USBHS_DEVDMAADDRESS Read/Write 0x00000000 0x0300 + (n * 0x10)+0x08 Device DMA Channel Control Register USBHS_DEVDMACONTROL Read/Write 0x00000000 0x0300 + (n * 0x10)+0x0C Device DMA Channel Status Register USBHS_DEVDMASTATUS Read/Write 0x00000000 0x0400 Host General Control Register USBHS_HSTCTRL Read/Write 0x00000000 0x0404 Host Global Interrupt Status Register USBHS_HSTISR Read-only 0x00000000 0x0408 Host Global Interrupt Clear Register USBHS_HSTICR Write-only 0x040C Host Global Interrupt Set Register USBHS_HSTIFR Write-only 0x0410 Host Global Interrupt Mask Register USBHS_HSTIMR Read-only 0x00000000 0x0414 Host Global Interrupt Disable Register USBHS_HSTIDR Write-only 0x0418 Host Global Interrupt Enable Register USBHS_HSTIER Write-only 0x0041C Host Pipe Register USBHS_HSTPIP Read/Write 0x00000000 0x0420 Host Frame Number Register USBHS_HSTFNUM Read/Write 0x00000000 0x0424 Host Address 1 Register USBHS_HSTADDR1 Read/Write 0x00000000 0x0428 Host Address 2 Register USBHS_HSTADDR2 Read/Write 0x00000000 0x042C Host Address 3 Register USBHS_HSTADDR3 Read/Write 0x00000000 0x0500 + (n * 0x04) + 0x00 Host Pipe Configuration Register USBHS_HSTPIPCFG Read/Write 0x00000000 0x0500 + (n * 0x04) + 0x30 Host Pipe Status Register USBHS_HSTPIPISR Read-only 0x00000000 0x0500 + (n * 0x04) + 0x60 Host Pipe Clear Register USBHS_HSTPIPICR Write-only 0x0500 + (n * 0x04) + 0x90 Host Pipe Set Register USBHS_HSTPIPIFR Write-only

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 600 0x0500 + (n * 0x04) + 0xC0 Host Pipe Mask Register USBHS_HSTPIPIMR Read-only 0x00000000 0x0500 + (n * 0x04) + 0xF0 Host Pipe Enabl e Register USBHS_HSTPIPIER Write-only 0x0500+ (n * 0x04) + 0x120 Host Pipe Disabl e Register USBHS_HSTPIPIDR Write-only 0x0500+ (n * 0x04) + 0x150 Host Pipe IN Request Register USBHS_HSTPIPINRQ Read/Write 0x00000000 0x0500 + (n * 0x04) + 0x180 Host Pipe Error Register USBHS_HSTPIPERR Read/Write 0x00000000 0x0700 + (n * 0x10) + 0x00 Host DMA Channel Next Descriptor Address Register USBHS_HSTDMANXTDSC Read/Write 0x00000000 0x0700 + (n * 0x10) + 0x04 Host DMA Channel Addres s Register USBHS_HSTDMAADDRESS Read/Write 0x00000000 0x0700 + (n * 0x10) + 0x08 Host DMA Channel Control Register USBHS_HSTDMACONTROL Read/Write 0x00000000 0x0700 + (n * 0x10) + 0x0C Host DMA Channel Status Register USBHS_HSTDMASTATUS Read/Write 0x00000000 0x0800 General Control Register USBHS_CTRL Read/Write 0x03004000 0x0804 General Status Register USBHS_SR Read-only 0x00000400 0x0808 General Status Clear Register USBHS_SCR Write-only 0x080C General Status Set Register USBHS_SFR Write-only 0x0810 - 0x082C Reserved – – – Table 37-4. Register Mapping (Continued) Offset Register Name Access Reset

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37.6.1 General Control Register

Name: USBHS_CTRL Address: 0x40038800 Access: Read/Write

• RDERRE: Remote Device Connect ion Error Interrupt Enable 0: The Remote Device Connection Error Interrupt (USBHS_SR.RDERRI) is disabled. 1: The Remote Device Connection Error Interrupt (USBHS_SR.RDERRI) is enabled.
• VBUSHWC: VBUS Hardware Control Must be set to ‘1’.
• FRZCLK: Freeze USB Clock 0: The clock inputs are enabled. 1: The clock inputs are disabled (the resume detection is still active). This reduces the power consumption. Unless explic- itly stated, all registers then become read-only. This bit can be written even if USBE = 0. Disabling the USBHS (by writing a zero to the USBE bit) does not reset this bit, but it freezes the clock inputs whatever its value.
• USBE: USBHS Enable Writing a zero to this bit resets the USBHS, disables the USB transceiver, and disables the USBHS clock inputs. Unless explicitly stated, all registers then become read-only and are reset. 0: The USBHS is disabled. 1: The USBHS is enabled. This bit can be written even if FRZCLK = 1
• UIMOD: USBHS Mode 0 (HOST): The module is in USB Host mode. 1 (DEVICE): The module is in USB Device mode. This bit can be written even if USBE = 0 or FRZCLK = 1. Disabling the USBHS (by writing a zero to the USBE bit) does not reset this bit. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 USBE F RZCLK ––––– V BUSHWC 76543210

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 602

37.6.2 General Status Register

Name: USBHS_SR Address: 0x40038804 Access: Read-only

• RDERRI: Remote Device Connection Error Interrupt (Host mode only) 0: Cleared when USBHS_SCR.RDERRIC = 1. 1: Set when an error occurs during the remote device connection. This triggers a USB interrupt if USBHS_CTRL.RDERRE = 1.
• SPEED: Speed Status (Device mode only) This field is set according to the controller speed mode.
• CLKUSABLE: UTMI Clock Usable 0: Cleared when the UTMI 30 MHz is not usable. 1: Set when the UTMI 30 MHz is usable. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 Value Name Description

0 FULL_SPEED Full- Speed mode

1 HIGH_SPEED High-Speed mode

2 LOW_SPEED Low-Speed mode

3– R eserved

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37.6.3 General Status Clear Register

Name: USBHS_SCR Address: 0x40038808 Access: Write-only This register always reads as zero.

• RDERRIC: Remote Device Conne ction Error Interrupt Clear 0: No effect. 1: Clears the RDERRI bit in USBHS_SR. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 604

37.6.4 General Status Set Register

Name: USBHS_SFR Address: 0x4003880C Access: Write-only This register always reads as zero.

• RDERRIS: Remote Device Connection Error Interrupt Set 0: No effect. 1: Sets the RDERRI bit in USBHS_SR, which may be useful for test or debug purposes.
• VBUSRQS: VBUS Request Set Must be set to ‘1’. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210

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37.6.5 Device General Control Register

Name: USBHS_DEVCTRL Address: 0x40038000 Access: Read/Write

• UADD: USB Address This field contains the device address. This field is cleared when a USB reset is received.
• ADDEN: Address Enable 0: No effect. 1: Activates the UADD field (USB address). This bit is cleared when a USB reset is received.
• DETACH: Detach 0: Reconnects the device. 1: Physically detaches the device (disconnects the internal pull-up resistor from D+ and D-).
• RMWKUP: Remote Wake-Up 0: No effect. 1: Sends an upstream resume to the host for a remote wake-up. This bit is cleared when the USBHS receives a USB reset or once the upstream resume has been sent.
• SPDCONF: Mode Configuration This field contains the peripheral speed: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 TSTPCKT TSTK TSTJ LS SPDCONF RMWKUP DETACH 76543210 ADDEN UADD Value Name Description 0N ORMAL The peripheral starts in Full-speed mode and performs a high-speed reset to switch to High- speed mode if the host is high-speed-capable. 1 LOW_POWER For a better consumption, if high speed is not needed.

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 606

• LS: Low-Speed Mode Force 0: The Full-speed mode is active. 1: The Low-speed mode is active. This bit can be written even if USBHS_CTRL.USBE = 0 or USBHS_CTRL.FRZCLK = 1. Disabling the USBHS (by writing a zero to the USBHS_CTRL.USBE bit) does not reset this bit.
• TSTJ: Test mode J 0: The UTMI transceiver is in Normal operating mode. 1: The UTMI transceiver generates high-speed J state for test purposes.
• TSTK: Test mode K 0: The UTMI transceiver is in Normal operating mode. 1: The UTMI transceiver generates high-speed K state for test purposes.
• TSTPCKT: Test packet mode 0: The UTMI transceiver is in Normal operating mode. 1: The UTMI transceiver generates test packets for test purposes.
• OPMODE2: Specific Operational mode 0: The UTMI transceiver is in Normal operating mode. 1: The UTMI transceiver is in the “Disable bit stuffing and NRZI encoding” operational mode for test purposes.

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37.6.6 Device Global Interrupt Status Register

Name: USBHS_DEVISR Address: 0x40038004 Access: Read-only

• SUSP: Suspend Interrupt 0: Cleared when the USBHS_DEVICR.SUSPC bit is written to one to acknowledge the interrupt, or when the Wake-Up (WAKEUP) interrupt bit is set. 1: Set when a USB “Suspend” idle bus state has been detected for 3 frame periods (J state for 3 ms). This triggers a USB interrupt if USBHS_DEVIMR.SUSPE = 1.
• MSOF: Micro Start of Frame Interrupt 0: Cleared when the USBHS_DEVICR.MSOFC bit is written to one to acknowledge the interrupt. 1: Set in High-speed mode when a USB “Micro Start of Frame” PID (SOF) has been detected (every 125 µs). This triggers a USB interrupt if MSOFE = 1. The MFNUM field is updated. The FNUM field is unchanged.
• SOF: Start of Frame Interrupt 0: Cleared when the USBHS_DEVICR.SOFC bit is written to one to acknowledge the interrupt. 1: Set when a USB “Start of Frame” PID (SOF) has been detected (every 1 ms). This triggers a USB interrupt if SOFE = 1. The FNUM field is updated. In High-speed mode, the MFNUM field is cleared.
• EORST: End of Reset Interrupt 0: Cleared when the USBHS_DEVICR.EORSTC bit is written to one to acknowledge the interrupt. 1: Set when a USB “End of Reset” has been detected. This triggers a USB interrupt if USBHS_DEVIMR.EORSTE = 1.
• WAKEUP: Wake-Up Interrupt 0: Cleared when the USBHS_DEVICR.WAKEUPC bit is written to one to acknowledge the interrupt (USB clock inputs must be enabled before), or when the Suspend (SUSP) interrupt bit is set. 1: Set when the USBHS is reactivated by a filtered non-idle signal from the lines (not by an upstream resume). This triggers an interrupt if USBHS_DEVIMR.WAKEUPE = 1. This interrupt is generated even if the clock is frozen by the USBHS_CTRL.FRZCLK bit.
• EORSM: End of Resume Interrupt 0: Cleared when the USBHS_DEVICR.EORSMC bit is written to one to acknowledge the interrupt. 1: Set when the USBHS detects a valid “End of Resume” signal initiated by the host. This triggers a USB interrupt if USBHS_DEVIMR.EORSME = 1. 31 30 29 28 27 26 25 24 DMA_7 DMA_6 DMA_5 DMA_4 DMA_3 DMA_2 DMA_1 – 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 – UPRSM EORSM WAKEUP EORST SOF MSOF SUSP

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 608

• UPRSM: Upstream Resume Interrupt 0: Cleared when the USBHS_DEVICR.UPRSMC bit is written to one to acknowledge the interrupt (USB clock inputs must be enabled before). 1: Set when the USBHS sends a resume signal called “Upstream Resume”. This triggers a USB interrupt if USBHS_DEVIMR.UPRSME = 1.
• PEP_x: Endpoint x Interrupt 0: Cleared when the interrupt source is serviced. 1: Set when an interrupt is triggered by endpoint x (USBHS_DEVEPTISRx, USBHS_DEVEPTIMRx). This triggers a USB interrupt if USBHS_DEVIMR.PEP_x = 1.
• DMA_x: DMA Channel x Interrupt 0: Cleared when the USBHS_DEVDMASTATUSx interrupt source is cleared. 1: Set when an interrupt is triggered by the DMA channel x. This triggers a USB interrupt if DMA_x = 1.

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37.6.7 Device Global Interrupt Clear Register

Name: USBHS_DEVICR Address: 0x40038008 Access: Write-only This register always reads as zero. The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Clears the corresponding bit in USBHS_DEVISR.

• SUSPC: Suspend Interrupt Clear
• MSOFC: Micro Start of Frame Interrupt Clear
• SOFC: Start of Frame Interrupt Clear
• EORSTC: End of Reset Interrupt Clear
• WAKEUPC: Wake-Up Interrupt Clear
• EORSMC: End of Resume Interrupt Clear
• UPRSMC: Upstream Resume Interrupt Clear 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 – UPRSMC EORSMC WAKEUPC EORSTC SOFC MSOFC SUSPC

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 610

37.6.8 Device Global Interrupt Set Register

Name: USBHS_DEVIFR Address: 0x4003800C Access: Write-only This register always reads as zero. The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Sets the corresponding bit in USBHS_DEVISR.

• SUSPS: Suspend Interrupt Set
• MSOFS: Micro Start of Frame Interrupt Set
• SOFS: Start of Frame Interrupt Set
• EORSTS: End of Reset Interrupt Set
• WAKEUPS: Wake-Up Interrupt Set
• EORSMS: End of Resume Interrupt Set
• UPRSMS: Upstream Resume Interrupt Set
• DMA_x: DMA Channel x Interrupt Set 31 30 29 28 27 26 25 24 DMA_7 DMA_6 DMA_5 DMA_4 DMA_3 DMA_2 DMA_1 – 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 – UPRSMS EORSMS WAKEUPS EORSTS SOFS MSOFS SUSPS

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37.6.9 Device Global Interrupt Mask Register

Name: USBHS_DEVIMR Address: 0x40038010 Access: Read-only The following configuration values are valid for all listed bit names of this register: 0: The corresponding interrupt is not enabled. 1: The corresponding interrupt is enabled.

• SUSPE: Suspend Interrupt Mask
• MSOFE: Micro Start of Frame Interrupt Mask
• SOFE: Start of Frame Interrupt Mask
• EORSTE: End of Reset Interrupt Mask
• WAKEUPE: Wake-Up Interrupt Mask
• EORSME: End of Resume Interrupt Mask
• UPRSME: Upstream Resume Interrupt Mask
• PEP_x: Endpoint x Interrupt Mask
• DMA_x: DMA Channel x Interrupt Mask 31 30 29 28 27 26 25 24 DMA_7 DMA_6 DMA_5 DMA_4 DMA_3 DMA_2 DMA_1 – 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 – UPRSME EORSME WAKEUPE EORSTE SOFE MSOFE SUSPE

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 612

37.6.10 Device Global Interrupt Disable Register

Name: USBHS_DEVIDR Address: 0x40038014 Access: Write-only This register always reads as zero. The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Clears the corresponding bit in USBHS_DEVIMR.

• SUSPEC: Suspend Interrupt Disable
• MSOFEC: Micro Start of Frame Interrupt Disable
• SOFEC: Start of Frame Interrupt Disable
• EORSTEC: End of Reset Interrupt Disable
• WAKEUPEC: Wake-Up Interrupt Disable
• EORSMEC: End of Resume Interrupt Disable
• UPRSMEC: Upstream Resu me Interrupt Disable
• PEP_x: Endpoint x Interrupt Disable
• DMA_x: DMA Channel x Interrupt Disable 31 30 29 28 27 26 25 24 DMA_7 DMA_6 DMA_5 DMA_4 DMA_3 DMA_2 DMA_1 – 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 – UPRSMEC EORSMEC WAKEUPEC EORSTEC SOFEC MSOFEC SUSPEC

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37.6.11 Device Global Interrupt Enable Register

Name: USBHS_DEVIER Address: 0x40038018 Access: Write-only This register always reads as zero. The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Sets the corresponding bit in USBHS_DEVIMR.

• SUSPES: Suspend Interrupt Enable
• MSOFES: Micro Start of Frame Interrupt Enable
• SOFES: Start of Frame Interrupt Enable
• EORSTES: End of Reset Interrupt Enable
• WAKEUPES: Wake-Up Interrupt Enable
• EORSMES: End of Resume Interrupt Enable
• UPRSMES: Upstream Resume Interrupt Enable
• PEP_x: Endpoint x Interrupt Enable
• DMA_x: DMA Channel x Interrupt Enable 31 30 29 28 27 26 25 24 DMA_7 DMA_6 DMA_5 DMA_4 DMA_3 DMA_2 DMA_1 – 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 – UPRSMES EORSMES WAKEUPES EORSTES SOFES MSOFES SUSPES

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 614

37.6.12 Device Endpoint Register

Name: USBHS_DEVEPT Address: 0x4003801C Access: Read/Write

• EPENx: Endpoint x Enable 0: Endpoint x is disabled, forcing the endpoint x state to inactive (no answer to USB requests) and resetting the endpoint x registers (USBHS_DEVEPTCFGx, USBHS_DEVEPTISRx, USBHS_DEVEPTIMRx) but not the endpoint configuration (USBHS_DEVEPTCFGx.ALLOC, USBHS_DEVEPTCFGx.EPBK, USBHS_DEVEPTCFGx.EPSIZE, USBHS_DEVEPTCFGx.EPDIR, USBHS_DEVEPTCFGx.EPTYPE). 1: Endpoint x is enabled.
• EPRSTx: Endpoint x Reset 0: Completes the reset operation and starts using the FIFO. 1: Resets the endpoint x FIFO prior to any other operation, upon hardware reset or when a USB bus reset has been received. This resets the endpoint x registers (USBHS_DEVEPTCFGx, USBHS_DEVEPTISRx, USBHS_DEVEPTIMRx) but not the endpoint configuration (USBHS_DEVEPTCFGx.ALLOC, USBHS_DEVEPTCFGx.EPBK, USBHS_DEVEPTCFGx.EPSIZE, USBHS_DEVEPTCFGx.EPDIR, USBHS_DEVEPTCFGx.EPTYPE). The whole endpoint mechanism (FIFO counter, reception, transmission, etc.) is reset apart from the Data Toggle Sequence field (USBHS_DEVEPTISRx.DTSEQ), which can be cleared by setting the USBHS_DEVEPTIMRx.RSTDT bit (by writing a one to the USBHS_DEVEPTIERx.RSTDTS bit). The endpoint configuration remains active and the endpoint is still enabled. This bit is cleared upon receiving a USB reset. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 EPRST7 EPRST6 EPRST5 EPRST4 EPRST3 EPRST2 EPRST1 EPRST0 15 14 13 12 11 10 9 8 76543210 EPEN7 EPEN6 EPEN5 EPEN4 EPEN3 EPEN2 EPEN1 EPEN0

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37.6.13 Device Frame Number Register

Name: USBHS_DEVFNUM Address: 0x40038020 Access: Read-only

• MFNUM: Micro Frame Number This field contains the 3-bit micro frame number information. It is provided in the last received MSOF packet. This field is cleared at the beginning of each start of frame (SOF interrupt) or upon receiving a USB reset. MFNUM is updated even if a corrupted MSOF is received.
• FNUM: Frame Number This field contains the 11-bit frame number information. It is provided in the last received SOF packet. This field is cleared upon receiving a USB reset. FNUM is updated even if a corrupted SOF is received.
• FNCERR: Frame Number CRC Error 0: Cleared upon receiving a USB reset. 1: Set when a corrupted frame number (or microframe number) is received. This bit and the SOF (or MSOF) interrupt bit are updated at the same time. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 FNCERR – FNUM 76543210 FNUM MFNUM

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 616

37.6.14 Device Endpoint x Configuration Register

Name: USBHS_DEVEPTCFGx [x=0..9] Address: 0x40038100 Access: Read/Write

• ALLOC: Endpoint Memory Allocate 0: Frees the endpoint memory. 1: Allocates the endpoint memory. The user should check the USBHS_DEVEPTISRx.CFGOK bit to know whether the allo- cation of this endpoint is correct. This bit is cleared upon receiving a USB reset (except for endpoint 0).
• EPBK: Endpoint Banks This field should be written to select the number of banks for the endpoint: For control endpoints, a single-bank endpoint (0b00) should be selected. This field is cleared upon receiving a USB reset (except for endpoint 0).
• EPSIZE: Endpoint Size This field should be written to select the size of each endpoint bank: This field is cleared upon receiving a USB reset (except for endpoint 0). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 – NBTRANS EPTYPE – AUTOSW EPDIR 76543210 – EPSIZE EPBK ALLOC – Value Name Description 0 1_BANK Single-bank endpoint 1 2_BANK Double-bank endpoint 2 3_BANK Triple-bank endpoint 3– R eserved Value Name Description 0 8_BYTE 8 bytes 1 16_BYTE 16 bytes 2 32_BYTE 32 bytes 3 64_BYTE 64 bytes 4 128_BYTE 128 bytes 5 256_BYTE 256 bytes 6 512_BYTE 512 bytes 7 1024_BYTE 1024 bytes

617SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

• EPDIR: Endpoint Direction This bit is cleared upon receiving a USB reset. 0 (OUT): The endpoint direction is OUT. 1 (IN): The endpoint direction is IN (nor for control endpoints).
• AUTOSW: Automatic Switch This bit is cleared upon receiving a USB reset. 0: The automatic bank switching is disabled. 1: The automatic bank switching is enabled.
• EPTYPE: Endpoint Type This field should be written to select the endpoint type: This field is cleared upon receiving a USB reset.
• NBTRANS: Number of transactions per microframe for isochronous endpoint This field should be written with the number of transactions per microframe to perform high-bandwidth isochronous transfer. It can be written only for endpoints that have this capability (see USBHS_FEATURES.ENHBISOx bit). Otherwise, this field is 0. This field is irrelevant for non-isochronous endpoints. Value Name Description

0 CTRL Control

1 ISO Isochronous

3 INTRPT Interrupt

0 0_TRANS Reserved to endpoint that does not have the high-bandwidth isochronous capability. 1 1_TRANS Default value: one transaction per microframe. 2 2_TRANS Two transactions per microframe. This endpoint should be configured as double-bank. 3 3_TRANS Three transactions per microframe. This endpoint should be configured as triple-bank.

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37.6.15 Device Endpoint x Status Register (Control, Bulk, Interrupt Endpoints)

Name: USBHS_DEVEPTISRx [x=0..9] Address: 0x40038130 Access: Read-only 0x0100 This register view is relevant only if EPTYPE = 0x0, 0x2or 0x3 in “Device Endpoint x Configuration Register” on page 616.

• TXINI: Transmitted IN Data Interrupt For control endpoints: 0: Cleared when TXINIC = 1. This acknowledges the interrupt and sends the packet. 1: Set when the current bank is ready to accept a new IN packet. This triggers a PEP_x interrupt if TXINE = 1. For bulk and interrupt IN endpoints: 0: Cle ared when TXINIC = 1. Thi s acknowledge s the interrupt, which h as no effect on the endpoint FIFO. USBHS_DEVEPTISRx.TXINI shall always be cleared before clearing USBHS_DEVEPTIMRx.FIFOCON. 1: Set at the same time as USBHS_DEVEPTIMRx.FIFOCON w hen the current b ank is free . This triggers a PEP_x interrupt if TXINE = 1. The user writes into the FIFO and clears the USBHS_DEVEPTIMRx.FIFOCON bit to allow the U SBHS to send the data. If the IN endpoint is compos ed of multiple b ank s, thi s also switche s to the next b ank. The USBHS_DEVEPTISRx.TXINI and USBHS_DEVEPTIMRx.FIFOCON bits are set/cleared in accordance with the status of the next bank. This bit is inactive (cleared) for bulk and interrupt OUT endpoints.
• RXOUTI: Received OUT Data Interrupt For control endpoints: 0: Cleared by writing a one to the RXOUTIC bit. This ackno wledges the interrupt and frees the bank. 1: Set when the current b ank contains a bulk OUT p acket (data or status stage). Thi s triggers a PEP_x interrupt if USBHS_DEVEPTIMRx.RXOUTE = 1. For bulk and interrupt OUT endpoints: 0: Cleared by writing a one to the RXOUTIC bit. Thi s acknowledges the interrupt, which has no effect on the endpoint FIFO. USBHS_DEVEPTISRx.RXOUTI shall always be cleared before clearing USBHS_DEVEPTIMRx.FIFOCON. 1: Set at the same time as USBHS_DEVEPTIMRx.FIFOCON when the current bank is full. This triggers a PEP_x inter- rupt if USBHS_DEVEPTIMRx.RXOUTE = 1. The user reads from the FIFO and clears the USBHS_DEVEPTIMRx.FIFOCON bit to free the b ank. If the OUT end- point is composed of multiple b anks, this also switches to the next b ank. The U SBHS_DEVEPTISRx.RXOUTI and USBHS_DEVEPTIMRx.FIFOCON bits are set/cleared in accordance with the status of the next bank. This bit is inactive (cleared) for bulk and interrupt IN endpoints. 31 30 29 28 27 26 25 24 – BYCT 23 22 21 20 19 18 17 16 BYCT – CFGOK CTRLDIR RWALL 15 14 13 12 11 10 9 8 CURRBK NBUSYBK – – DTSEQ 76543210 SHORTPACKET STALLEDI OVERFI NAKI NI NAKOUTI RXSTPI RXOUTI TXINI

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• RXSTPI: Received SETUP Interrupt This bit is set, for control endpoints, to signal that the current bank contains a new valid SETUP packet. This triggers a PEP_x interrupt if RXSTPE = 1. It is cleared by writing a one to the RXSTPIC bit. This acknowledges the interrupt and frees the bank. This bit is inactive (cleared) for bulk and interrupt IN/OUT endpoints.
• NAKOUTI: NAKed OUT Interrupt 0: Cleared when NAKOUTIC = 1. This acknowledges the interrupt. 1: Set when a NAK handshake has been sent in response to an OUT request from the host. This triggers a PEP_x interrupt if NAKOUTE = 1.
• NAKINI: NAKed IN Interrupt 0: Cleared when NAKINIC = 1. This acknowledges the interrupt. 1: Set when a NAK handshake has been sent in response to an IN request from the host. This triggers a PEP_x interrupt if NAKINE = 1.
• OVERFI: Overflow Interrupt 0: Cleared when the OVERFIC bit is written to one. This acknowledges the interrupt. 1: Set when an overflow error occurs. This triggers a PEP_x interrupt if OVERFE = 1. For all endpoint types, an overflow can occur during the OUT stage if the host attempts to write into a bank that is too small for the packet. The packet is acknowledged and the USBHS_DEVEPTISRx.RXOUTI bit is set as if no overflow had occurred. The bank is filled with all the first bytes of the packet that fit in.
• STALLEDI: STALLed Interrupt 0: Cleared when STALLEDIC = 1. This acknowledges the interrupt. 1: Set to signal that a STALL handshake has been sent. To do that, the software has to set the STALLRQ bit (by writing a one to the STALLRQS bit). This triggers a PEP_x interrupt if STALLEDE = 1.
• SHORTPACKET: Short Packet Interrupt 0: Cleared when SHORTPACKETC = 1. This acknowledges the interrupt. 1: Set for non-control OUT endpoints, when a short packet has been received. This triggers a PEP_x interrupt if USBHS_DEVEPTIMRx.SHORTPACKETE = 1.
• DTSEQ: Data Toggle Sequence This field is set to indicate the PID of the current bank: For IN transfers, it indicates the data toggle sequence that should be used for the next packet to be sent. This is not rela- tive to the current bank. For OUT transfers, this value indicates the last data toggle sequence received on the current bank. Value Name Description

0 DATA0 Data0 toggle sequence

1 DATA1 Data1 toggle sequence

2 DATA2 Reserved for high-bandwidth isochronous endpoint

3 MDATA Reserved for high-bandwidth isochronous endpoint

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 620 By default, DTSEQ is 0b01, as if the last data toggle sequence was Data1, so the next sent or expected data toggle sequence should be Data0.

• NBUSYBK: Number of Busy Banks This field is set to indicate the number of busy banks: For IN endpoints, it indicates the number of banks filled by the user and ready for IN transfer. When all banks are free, this triggers a PEP_x interrupt if NBUSYBKE = 1. For OUT endpoints, it indicates the number of banks filled by OUT transactions from the host. When all banks are busy, this triggers a PEP_x interrupt if NBUSYBKE = 1. When the USBHS_DEVEPTIMRx.FIFOCON bit is cleared (by writing a one to the USBHS_DEVEPTIMRx.FIFOCONC bit) to validate a new bank, this field is updated two or three clock cycles later to calculate the address of the next bank. A PEP_x interrupt is triggered if:  for IN endpoint, USBHS_DEVEPTIMRx.NBUSYBKE = 1 and all the banks are free;  for OUT endpoint, USBHS_DEVEPTIMRx.NBUSYBKE = 1 and all the banks are busy.
• CURRBK: Current Bank This bit is set for non-control endpoints, to indicate the current bank: This field may be updated one clock cycle after the RWALL bit changes, so the user should not poll this field as an interrupt bit.
• RWALL: Read/Write Allowed This bit is set for IN endpoints when the current bank is not full, i.e., the user can write further data into the FIFO. This bit is set for OUT endpoints when the current bank is not empty, i.e., the user can read further data from the FIFO. This bit is never set if USBHS_DEVEPTIMRx.STALLRQ = 1 or in case of error. This bit is cleared otherwise. This bit should not be used for control endpoints.
• CTRLDIR: Control Direction 0: Cleared after a SETUP packet to indicate that the following packet is an OUT packet. 1: Set after a SETUP packet to indicate that the following packet is an IN packet. Value Name Description 0 0_BUSY 0 busy bank (all banks free) 1 1_BUSY 1 busy bank 2 2_BUSY 2 busy banks 3 3_BUSY 3 busy banks Value Name Description

0 BANK0 Current bank is bank0

1 BANK1 Current bank is bank1

2 BANK2 Current bank is bank2

3– R eserved

621SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

• CFGOK: Configuration OK Status This bit is updated when USBHS_DEVEPTCFGx.ALLOC = 1. This bit is set if the endpoint x number of banks (USBHS_DEVEPTCFGx.EPBK) and size (USBHS_DEVEPTCFGx.EPSIZE) are correct compared to the maximal allowed number of banks and size for this end- point and to the maximal FIFO size (i.e., the DPRAM size). If this bit is cleared, the user should rewrite correct values to the USBHS_DEVEPTCFGx.EPBK and USBHS_DEVEPTCFGx.EPSIZE fields.
• BYCT: Byte Count This field is set with the byte count of the FIFO. For IN endpoints, the field is incremented after each byte written by the software into the endpoint and decremented after each byte sent to the host. For OUT endpoints, the field is incremented after each byte received from the host and decremented after each byte read by the software from the endpoint. This field may be updated one clock cycle after the RWALL bit changes, so the user should not poll this field as an interrupt bit.

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 622

37.6.16 Device Endpoint x Status Register (Isochronous Endpoints)

Name: USBHS_DEVEPTISRx [x=0..9] (ISOENPT) Address: 0x40038130 Access: Read-only 0x0100 This register view is relevant only if EPTYPE = 0x1 in “Device Endpoint x Configuration Register” on page 616.

• TXINI: Transmitted IN Data Interrupt For control endpoints: 0: Cleared when TXINIC = 1. This acknowledges the interrupt and sends the packet. 1: Set when the current bank is ready to accept a new IN packet. This triggers a PEP_x interrupt if TXINE = 1. For IN endpoints: 0: Cle ared when TXINIC = 1. Thi s acknowledge s the interrupt, which h as no effect on the endpoint FIFO. USBHS_DEVEPTISRx.TXINI shall always be cleared before clearing USBHS_DEVEPTIMRx.FIFOCON. 1: Set at the same time as USBHS_DEVEPTIMRx.FIFOCON w hen the current b ank is fr ee. This triggers a PEP_x interrupt if TXINE = 1. The user writes into the FIFO and clears the USBHS_DEVEPTIMRx.FIFOCON bit to allow the U SBHS to send the data. If the IN endpoint is compos ed of multiple b ank s, thi s also switche s to the next b ank. The USBHS_DEVEPTISRx.TXINI and USBHS_DEVEPTIMRx.FIFOCON bits are set/cleared in accordance with the status of the next bank. This bit is inactive (cleared) for OUT endpoints.
• RXOUTI: Received OUT Data Interrupt For control endpoints: 0: Cleared by writing a one to the RXOUTIC bit. This acknowledges the interrupt and frees the bank. 1: Set when the current b ank contains a bulk OUT p acket (data or status stage). Thi s triggers a PEP_x interrupt if USBHS_DEVEPTIMRx.RXOUTE = 1. For OUT endpoints: 0: Cleared by writing a one to the RXOUTIC bit. Thi s acknowledges the interrupt, which has no effect on the endpoint FIFO. USBHS_DEVEPTISRx.RXOUTI shall always be cleared before clearing USBHS_DEVEPTIMRx.FIFOCON. 1: Set at the same time as USBHS_DEVEPTIMRx.FIFOCON when the current bank is full. This triggers a PEP_x inter- rupt if USBHS_DEVEPTIMRx.RXOUTE = 1. The user reads from the FIFO and clears the USBHS_DEVEPTIMRx.FIFOCON bit to free the b ank. If the OUT end- point is composed of multiple b anks, this also switches to the next b ank. The U SBHS_DEVEPTISRx.RXOUTI and USBHS_DEVEPTIMRx.FIFOCON bits are set/cleared in accordance with the status of the next bank. This bit is inactive (cleared) for IN endpoints. 31 30 29 28 27 26 25 24 – BYCT 23 22 21 20 19 18 17 16 BYCT – CFGOK – RWALL 15 14 13 12 11 10 9 8 CURRBK NBUSYBK – ERRORTRANS DTSEQ 76543210 SHORTPACKET CRCERRI OVERFI HBISOFLUSHI HBISOINERRI UNDERFI RXOUTI TXINI

623SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

• UNDERFI: Underflow Interrupt This bit is set, for isochronous IN/OUT endpoints, when an underflow error occurs. This triggers a PEP_x interrupt if UNDERFE = 1. An underflow can occur during IN stage if the host attempts to read from an empty bank. A zero-length packet is then auto- matically sent by the USBHS. An underflow can also occur during OUT stage if the host sends a packet while the bank is already full. Typically, the CPU is not fast enough. The packet is lost. It is cleared by writing a one to the UNDERFIC bit. This acknowledges the interrupt.
• HBISOINERRI: High Bandwidth Isochronous IN Underflow Error Interrupt 0: Cleared when the HBISOINERRIC bit is written to one. This acknowledges the interrupt. 1: Set for High-bandwidth isochronous IN endpoint (with NBTRANS = 2 or 3) at the end of the microframe, if less than N banks were written by the CPU within this microframe. This triggers a PEP_x interrupt if HBISOINERRE = 1.
• HBISOFLUSHI: High Bandwidth Isochronous IN Flush Interrupt 0: Cleared when the HBISOFLUSHIC bit is written to one. This acknowledges the interrupt. 1: Set for High-bandwidth isochronous IN endpoint (with NBTRANS = 2 or 3) at the end of the microframe, if less than N transactions have been completed by the USBHS without underflow error. This may occur in case of a missing IN token. In this case, the banks are flushed out to ensure the data synchronization between the host and the device. This triggers a PEP_x interrupt if HBISOFLUSHE = 1.
• OVERFI: Overflow Interrupt 0: Cleared when OVERFIC = 1. This acknowledges the interrupt. 1: Set when an overflow error occurs. This triggers a PEP_x interrupt if OVERFE = 1. For all endpoint types, an overflow can occur during OUT stage if the host attempts to write into a bank that is too small for the packet. The packet is acknowl- edged and the USBHS_DEVEPTISRx.RXOUTI bit is set as if no overflow had occurred. The bank is filled with all the first bytes of the packet that fit in.
• CRCERRI: CRC Error Interrupt 0: Cleared when CRCERRIC = 1. This acknowledges the interrupt. 1: Set to signal that a CRC error has been detected in an isochronous OUT endpoint. The OUT packet is stored in the bank as if no CRC error had occurred. This triggers a PEP_x interrupt if CRCERRE = 1.
• SHORTPACKET: Short Packet Interrupt 0: Cleared when SHORTPACKETC = 1. This acknowledges the interrupt. 1: Set for non-control OUT endpoints, when a short packet has been received. This triggers a PEP_x interrupt if USBHS_DEVEPTIMRx.SHORTPACKETE = 1.

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 624

• DTSEQ: Data Toggle Sequence This field is set to indicate the PID of the current bank: For IN transfers, it indicates the data toggle sequence that should be used for the next packet to be sent. This is not rela- tive to the current bank. For OUT transfers, this value indicates the last data toggle sequence received on the current bank. By default, DTSEQ is 0b01, as if the last data toggle sequence was Data1, so the next sent or expected data toggle sequence should be Data0. For high-bandwidth isochronous endpoint, a PEP_x interrupt is triggered if: U SBHS_DEVEPTIMRx.MDATAE = 1 and a MData packet has been received (DTSEQ = MData and USBHS_DEVEPTISRx.RXOUTI = 1). U SBHS_DEVEPTISRx.DATAXE = 1 and a Data0/1/2 packet has been received (DTSEQ = Data0/1/2 and USBHS_DEVEPTISRx.RXOUTI = 1).
• ERRORTRANS: High-bandwidth Isochronous OUT Endpoint Transaction Error Interrupt This bit is set when a transaction error occurs during the current microframe (the data toggle sequencing is not compliant with the USB 2.0 standard). This triggers a PEP_x interrupt if USBHS_DEVEPTIMRx.ERRORTRANSE = 1. This bit is set as long as the current bank (CURRBK) belongs to the bad n-transactions (n = 1, 2 or 3) transferred during the microframe. It is cleared by software by clearing (at least once) the USBHS_DEVEPTIMRx.FIFOCON bit to switch to the bank that belongs to the next n-transactions (next microframe).
• NBUSYBK: Number of Busy Banks This field is set to indicate the number of busy banks: For IN endpoints, it indicates the number of banks filled by the user and ready for IN transfer. When all banks are free, this triggers a PEP_x interrupt if NBUSYBKE = 1. For OUT endpoints, it indicates the number of banks filled by OUT transactions from the host. When all banks are busy, this triggers a PEP_x interrupt if NBUSYBKE = 1. When the USBHS_DEVEPTIMRx.FIFOCON bit is cleared (by writing a one to the USBHS_DEVEPTIMRx.FIFOCONC bit) to validate a new bank, this field is updated two or three clock cycles later to calculate the address of the next bank. A PEP_x interrupt is triggered if:  For IN endpoint, USBHS_DEVEPTIMRx.NBUSYBKE = 1 and all the banks are free.  For OUT endpoint, USBHS_DEVEPTIMRx.NBUSYBKE = 1 and all the banks are busy. Value Name Description

2 DATA2 Data2 toggle sequence (for high-bandwidth isochronous endpoint)

3 MDATA MData toggle sequence (for high-bandwidth isochronous endpoint)

0 0_BUSY 0 busy bank (all banks free) 1 1_BUSY 1 busy bank 2 2_BUSY 2 busy banks 3 3_BUSY 3 busy banks

625SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

• CURRBK: Current Bank This field is used to indicate the current bank. It may be updated one clock cycle after the RWALL bit changes, so the user should not poll this field as an interrupt bit.
• RWALL: Read/Write Allowed This bit is set for IN endpoints when the current bank is not full, i.e., the user can write further data into the FIFO. This bit is set for OUT endpoints when the current bank is not empty, i.e., the user can read further data from the FIFO. This bit is never set in case of error. This bit is cleared otherwise.
• CFGOK: Configuration OK Status This bit is updated when USBHS_DEVEPTCFGx.ALLOC = 1. This bit is set if the endpoint x number of banks (USBHS_DEVEPTCFGx.EPBK) and size (USBHS_DEVEPTCFGx.EPSIZE) are correct compared to the maximal allowed number of banks and size for this end- point and to the maximal FIFO size (i.e., the DPRAM size). If this bit is cleared, the user should rewrite correct values to the USBHS_DEVEPTCFGx.EPBK and USBHS_DEVEPTCFGx.EPSIZE fields.
• BYCT: Byte Count This field is set with the byte count of the FIFO. For IN endpoints, the field is incremented after each byte written by the software into the endpoint and decremented after each byte sent to the host. For OUT endpoints, the field is incremented after each byte received from the host and decremented after each byte read by the software from the endpoint. This field may be updated one clock cycle after the RWALL bit changes, so the user should not poll this field as an interrupt bit. Value Name Description

3– R eserved

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 626

37.6.17 Device Endpoint x Clear Register (Control, Bulk, Interrupt Endpoints)

Name: USBHS_DEVEPTICRx [x=0..9] Address: 0x40038160 Access: Write-only This register view is relevant only if EPTYPE = 0x0, 0x2 or 0x3 in “Device Endpoint x Configuration Register” on page 616. For additional information, see “Device Endpoint x Status Register (Control, Bulk, Interrupt Endpoints)” on page 618. This register always reads as zero. The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Clears the corresponding bit in USBHS_DEVEPTISRx.

• TXINIC: Transmitted IN Data Interrupt Clear
• RXOUTIC: Received OUT Data Interrupt Clear
• RXSTPIC: Received SETUP Interrupt Clear
• NAKOUTIC: NAKed OUT Interrupt Clear
• NAKINIC: NAKed IN Interrupt Clear
• OVERFIC: Overflow Interrupt Clear
• STALLEDIC: STALLed Interrupt Clear
• SHORTPACKETC: Short Packet Interrupt Clear 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 SHORTPACKETC STALLEDIC OVERFIC NAKINIC NAKOUTIC RXSTPIC RXOUTIC TXINIC

627SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

37.6.18 Device Endpoint x Clear Register (Isochronous Endpoints)

Name: USBHS_DEVEPTICRx [x=0..9] (ISOENPT) Address: 0x40038160 Access: Write-only This register view is relevant only if EPTYPE = 0x1 in “Device Endpoint x Configuration Register” on page 616. For additional information, see “Device Endpoint x Status Register (Isochronous Endpoints)” on page 622. This register always reads as zero. The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Clears the corresponding bit in USBHS_DEVEPTISRx.

• TXINIC: Transmitted IN Data Interrupt Clear
• RXOUTIC: Received OUT Data Interrupt Clear
• UNDERFIC: Underflow Interrupt Clear
• HBISOINERRIC: High Bandwidth Isochronous IN Underflow Error Interrupt Clear
• HBISOFLUSHIC: High Bandwidth Isoc hronous IN Flush Interrupt Clear
• OVERFIC: Overflow Interrupt Clear
• CRCERRIC: CRC Error Interrupt Clear
• SHORTPACKETC: Short Packet Interrupt Clear 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 SHORTPACKETC CRCERRIC OVERFIC HBISOFLUSHIC HBISOINERRIC UNDERFIC RXOUTIC TXINIC

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 628

37.6.19 Device Endpoint x Set Register (Control, Bulk, Interrupt Endpoints)

Name: USBHS_DEVEPTIFRx [x=0..9] Address: 0x40038190 Access: Write-only This register view is relevant only if EPTYPE = 0x0, 0x2 or 0x3 in “Device Endpoint x Configuration Register” on page 616. For additional information, see “Device Endpoint x Status Register (Control, Bulk, Interrupt Endpoints)” on page 618.This register always reads as zero. The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Sets the corresponding bit in USBHS_DEVEPTISRx, which may be useful for test or debug purposes.

• TXINIS: Transmitted IN Data Interrupt Set
• RXOUTIS: Received OUT Data Interrupt Set
• RXSTPIS: Received SETUP Interrupt Set
• NAKOUTIS: NAKed OUT Interrupt Set
• NAKINIS: NAKed IN Interrupt Set
• OVERFIS: Overflow Interrupt Set
• STALLEDIS: STALLed Interrupt Set
• SHORTPACKETS: Short Packet Interrupt Set
• NBUSYBKS: Number of Bu sy Banks Interrupt Set 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 SHORTPACKETS STALLEDIS OVERFIS NAKINI S NAKOUTIS RXSTPIS RXOUTIS TXINIS

629SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

37.6.20 Device Endpoint x Set Register (Isochronous Endpoints)

Name: USBHS_DEVEPTIFRx [x=0..9] (ISOENPT) Address: 0x40038190 Access: Write-only This register view is relevant only if EPTYPE = 0x1 in “Device Endpoint x Configuration Register” on page 616. For additional information, see “Device Endpoint x Status Register (Isochronous Endpoints)” on page 622. The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Sets the corresponding bit in USBHS_DEVEPTISRx, which may be useful for test or debug purposes.

• TXINIS: Transmitted IN Data Interrupt Set
• RXOUTIS: Received OUT Data Interrupt Set
• UNDERFIS: Underflow Interrupt Set
• HBISOINERRIS: High Bandwidth Isochronous IN Underflow Error Interrupt Set
• HBISOFLUSHIS: High Bandwidth Isochronous IN Flush Interrupt Set
• OVERFIS: Overflow Interrupt Set
• CRCERRIS: CRC Error Interrupt Set
• SHORTPACKETS: Short Packet Interrupt Set
• NBUSYBKS: Number of Bu sy Banks Interrupt Set 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 SHORTPACKETS CRCERRIS OVERFIS HBISOFLUSHIS HBISOINERRIS UNDERFIS RXOUTIS TXINIS

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 630

37.6.21 Device Endpoint x Mask Register (Control, Bulk, Interrupt Endpoints)

Name: USBHS_DEVEPTIMRx [x=0..9] Address: 0x400381C0 Access: Read-only This register view is relevant only if EPTYPE = 0x0, 0x2 or 0x3 in “Device Endpoint x Configuration Register” on page 616.

• TXINE: Transmitted IN Data Interrupt 0: Cleared when USBHS_DEVEPTIDRx.TXINEC = 1. This disables the Transmitted IN Data interrupt (USBHS_DEVEPTISRx.TXINI). 1: Set when USBHS_DEVEPTIERx.TXINES = 1. This enables the Transmitted IN Data interrupt (USBHS_DEVEPTISRx.TXINI).
• RXOUTE: Received OUT Data Interrupt 0: Cleared when USBHS_DEVEPTIDRx.RXOUTEC = 1. This disables the Received OUT Data interrupt (USBHS_DEVEPTISRx.RXOUTI). 1: Set when USBHS_DEVEPTIERx.RXOUTES = 1. This enables the Received OUT Data interrupt (USBHS_DEVEPTISRx.RXOUTI).
• RXSTPE: Received SETUP Interrupt 0: Cleared when USBHS_DEVEPTIERx.RXSTPEC = 1. This disables the Received SETUP interrupt (USBHS_DEVEPTISRx.RXSTPI). 1: Set when USBHS_DEVEPTIERx.RXSTPES = 1. This enables the Received SETUP interrupt (USBHS_DEVEPTISRx.RXSTPI).
• NAKOUTE: NAKed OUT Interrupt 0: Cleared when USBHS_DEVEPTIDRx.NAKOUTEC = 1. This disables the NAKed OUT interrupt (USBHS_DEVEPTISRx.NAKOUTI). 1: Set when USBHS_DEVEPTIERx.NAKOUTES = 1. This enables the NAKed OUT interrupt (USBHS_DEVEPTISRx.NAKOUTI).
• NAKINE: NAKed IN Interrupt 0: Cleared when USBHS_DEVEPTIDRx.NAKINEC = 1. This disables the NAKed IN interrupt (USBHS_DEVEPTISRx.NAKINI). 1: Set when USBHS_DEVEPTIERx.NAKINES = 1. This enables the NAKed IN interrupt (USBHS_DEVEPTISRx.NAKINI). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 –––– S TALLRQ R STDT N YETDIS E PDISHDMA 15 14 13 12 11 10 9 8 – FIFOCON KILLBK NBUSYBKE –––– 76543210 SHORTPACKETE STALLEDE OVERFE NAKINE NAKOUTE RXSTPE RXOUTE TXINE

631SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

• OVERFE: Overflow Interrupt 0: Cleared when USBHS_DEVEPTIDRx.OVERFEC = 1. This disables the Overflow interrupt (USBHS_DEVEPTISRx.OVERFI). 1: Set when USBHS_DEVEPTIERx.OVERFES = 1. This enables the Overflow interrupt (USBHS_DEVEPTISRx.OVERFI).
• STALLEDE: STALLed Interrupt 0: Cleared when USBHS_DEVEPTIDRx.STALLEDEC = 1. This disables the STALLed interrupt (USBHS_DEVEPTISRx.STALLEDI). 1: Set when USBHS_DEVEPTIERx.STALLEDES = 1. This enables the STALLed interrupt (USBHS_DEVEPTISRx.STALLEDI).
• SHORTPACKETE: Short Packet Interrupt 0: Cleared when USBHS_DEVEPTIDRx.SHORTPACKETEC = 1. This disables the Short Packet interrupt (USBHS_DEVEPTISRx.SHORTPACKET). 1: Set when USBHS_DEVEPTIERx.SHORTPACKETES = 1. This enables the Short Packet interrupt (USBHS_DEVEPTISRx.SHORTPACKET). If this bit is set for non-control IN endpoints, a short packet transmission is guaranteed upon ending a DMA transfer, thus signaling an end of isochronous frame or a bulk or interrupt end of transfer, provided that the End of DMA Buffer Output Enable (END_B_EN) bit and the Automatic Switch (AUTOSW) = 1.
• NBUSYBKE: Number of Busy Banks Interrupt 0: Cleared when USBHS_DEVEPTIDRx.NBUSYBKEC = 0. This disables the Number of Busy Banks interrupt (USBHS_DEVEPTISRx.NBUSYBK). 1: Set when the USBHS_DEVEPTIERx.NBUSYBKES = 1. This enables the Number of Busy Banks interrupt (USBHS_DEVEPTISRx.NBUSYBK).
• KILLBK: Kill IN Bank This bit is set when the USBHS_DEVEPTIERx.KILLBKS bit is written to one. This kills the last written bank. This bit is cleared when the bank is killed. CAUTION: The bank is really cleared when the “kill packet” procedure is accepted by the USBHS core. This bit is automat- ically cleared after the end of the procedure: The bank is really killed: USBHS_DEVEPTISRx.NBUSYBK is decremented. The bank is not cleared but sent (IN transfer): USBHS_DEVEPTISRx.NBUSYBK is decremented. The bank is not cleared because it was empty. The user should wait for this bit to be cleared before trying to kill another packet. This kill request is refused if at the same time an IN token is coming and the last bank is the current one being sent on the USB line. If at least two banks are ready to be sent, there is no problem to kill a packet even if an IN token is coming. Indeed, in this case, the current bank is sent (IN transfer) while the last bank is killed.

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 632

• FIFOCON: FIFO Control For control endpoints: The FIFOCON and RWALL bits are irrelevant. Therefore, the software never uses them on these endpoints. When read, their value is always 0. For IN endpoints: 0: Cleared (by writing a one to the USBHS_DEVEPTIDRx.FIFOCONC bit) to send the FIFO data and to switch to the next bank. 1: Set when the current bank is free, at the same time as USBHS_DEVEPTISRx.TXINI. For OUT endpoints: 0: Cleared (by writing a one to the USBHS_DEVEPTIDRx.FIFOCONC bit) to free the current bank and to switch to the next bank. 1: Set when the current bank is full, at the same time as USBHS_DEVEPTISRx.RXOUTI.
• EPDISHDMA: Endpoint Inte rrupts Disable HDMA Request This bit is set when USBHS_DEVEPTIERx.EPDISHDMAS = 1. This pauses the on-going DMA channel x transfer on any Endpoint x interrupt (PEP_x), whatever the state of the Endpoint x Interrupt Enable bit (PEP_x). The user then has to acknowledge or to disable the interrupt source (e.g. USBHS_DEVEPTISRx.RXOUTI) or to clear the EPDISHDMA bit (by writing a one to the USBHS_DEVEPTIDRx.EPDISHDMAC bit) in order to complete the DMA transfer. In Ping-pong mode, if the interrupt is associated to a new system-bank packet (e.g. Bank1) and the current DMA transfer is running on the previous packet (Bank0), then the previous-packet DMA transfer completes normally, but the new-packet DMA transfer does not start (not requested). If the interrupt is not associated to a new system-bank packet (USBHS_DEVEPTISRx.NAKINI, NAKOUTI, etc.), then the request cancellation may occur at any time and may immediately pause the current DMA transfer. This may be used for example to identify erroneous packets, to prevent them from being transferred into a buffer, to com- plete a DMA transfer by software after reception of a short packet, etc.
• NYETDIS: NYET Token Disable 0: Cleared when USBHS_DEVEPTIDRx.NYETDISC = 1. This enables the USBHS to handle the high-speed handshake following the USB 2.0 standard. 1: Set when USBHS_DEVEPTIERx.NYETDISS = 1. This sends a ACK handshake instead of a NYET handshake in High- speed mode.
• RSTDT: Reset Data Toggle This bit is set when USBHS_DEVEPTIERx.RSTDTS = 1. This clears the data toggle sequence, i.e., sets to Data0 the data toggle sequence of the next sent (IN endpoints) or received (OUT endpoints) packet. This bit is cleared instantaneously. The user does not have to wait for this bit to be cleared.
• STALLRQ: STALL Request 0: Cleared when a new SETUP packet is received or when USBHS_DEVEPTIDRx.STALLRQC = 0. 1: Set when USBHS_DEVEPTIERx.STALLRQS = 1. This requests to send a STALL handshake to the host.

633SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

37.6.22 Device Endpoint x Mask Register (Isochronous Endpoints)

Name: USBHS_DEVEPTIMRx [x=0..9] (ISOENPT) Address: 0x400381C0 Access: Read-only This register view is relevant only if EPTYPE = 0x1 in “Device Endpoint x Configuration Register” on page 616.

• TXINE: Transmitted IN Data Interrupt 0: Cleared when USBHS_DEVEPTIDRx.TXINEC = 1. This disables the Transmitted IN Data interrupt (USBHS_DEVEPTISRx.TXINI). 1: Set when USBHS_DEVEPTIERx.TXINES = 1. This enables the Transmitted IN Data interrupt (USBHS_DEVEPTISRx.TXINI).
• RXOUTE: Received OUT Data Interrupt 0: Cleared when USBHS_DEVEPTIDRx.RXOUTEC = 1. This disables the Received OUT Data interrupt (USBHS_DEVEPTISRx.RXOUTI). 1: Set when USBHS_DEVEPTIERx.RXOUTES = 1. This enables the Received OUT Data interrupt (USBHS_DEVEPTISRx.RXOUTI).
• UNDERFE: Underflow Interrupt 0: Cleared when USBHS_DEVEPTIDRx.UNDERFEC = 1. This disables the Underflow interrupt (USBHS_DEVEPTISRx.UNDERFI). 1: Set when USBHS_DEVEPTIERx.UNDERFES = 1. This enables the Underflow interrupt (USBHS_DEVEPTISRx.UNDERFI).
• HBISOINERRE: High Bandwidth Isochronous IN Error Interrupt 0: Cleared when the USBHS_DEVEPTIDRx.HBISOINERREC bit disables the HBISOINERRI interrupt. 1: Set when USBHS_DEVEPTIERx.HBISOINERRES = 1. This enables the HBISOINERRI interrupt.
• HBISOFLUSHE: High Bandwidth Isochronous IN Flush Interrupt 0: Cleared when the USBHS_DEVEPTIDRx.HBISOFLUSHEC bit disables the HBISOFLUSHI interrupt. 1: Set when USBHS_DEVEPTIERx.HBISOFLUSHES = 1. This enables the HBISOFLUSHI interrupt.
• OVERFE: Overflow Interrupt 0: Cleared when USBHS_DEVEPTIDRx.OVERFEC = 1. This disables the Overflow interrupt (USBHS_DEVEPTISRx.OVERFI). 1: Set when USBHS_DEVEPTIERx.OVERFES = 1. This enables the Overflow interrupt (USBHS_DEVEPTISRx.OVERFI). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 – FIFOCON KILLBK NBUSYBKE – ERRORTRANSE DATAXE MDATAE 76543210 SHORTPACKETE CRCERRE OVERFE HBISOFLUSHE HBISOINERRE UNDERFE RXOUTE TXINE

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 634

• CRCERRE: CRC Error Interrupt 0: Cleared when USBHS_DEVEPTIDRx.CRCERREC = 1. This disables the CRC Error interrupt (USBHS_DEVEPTISRx.CRCERRI). 1: Set when USBHS_DEVEPTIERx.CRCERRES = 1. This enables the CRC Error interrupt (USBHS_DEVEPTISRx.CRCERRI).
• SHORTPACKETE: Short Packet Interrupt 0: Cleared when USBHS_DEVEPTIDRx.SHORTPACKETEC = 1. This disables the Short Packet interrupt (USBHS_DEVEPTISRx.SHORTPACKET). 1: Set when USBHS_DEVEPTIERx.SHORTPACKETES = 1. This enables the Short Packet interrupt (USBHS_DEVEPTISRx.SHORTPACKET). If this bit is set for non-control IN endpoints, a short packet transmission is guaranteed upon ending a DMA transfer, thus signaling an end of isochronous frame or a bulk or interrupt end of transfer, provided that the End of DMA Buffer Output Enable (END_B_EN) bit and the Automatic Switch (AUTOSW) bit = 1.
• MDATAE: MData Interrupt 0: Cleared when USBHS_DEVEPTIDRx.MDATAEC = 1. This disables the Multiple DATA interrupt. 1: Set when the USBHS_DEVEPTIERx.MDATAES = 1. This enables the Multiple DATA interrupt (see DTSEQ bits).
• DATAXE: DataX Interrupt 0: Cleared when USBHS_DEVEPTIDRx.DATAXEC = 1. This disables the DATAX interrupt. 1: Set when the USBHS_DEVEPTIERx.DATAXES = 1. This enables the DATAX interrupt (see DTSEQ bits).
• ERRORTRANSE: Transaction Error Interrupt 0: Cleared when USBHS_DEVEPTIDRx.ERRORTRANSEC = 1. This disables the transaction error interrupt (USBHS_DEVEPTISRx.ERRORTRANS). 1: Set when USBHS_DEVEPTIERx.ERRORTRANSES = 1. This enables the transaction error interrupt (USBHS_DEVEPTISRx.ERRORTRANS).
• NBUSYBKE: Number of Busy Banks Interrupt 0: Cleared when USBHS_DEVEPTIDRx.NBUSYBKEC = 0. This disables the Number of Busy Banks interrupt (USBHS_DEVEPTISRx.NBUSYBK). 1: Set when USBHS_DEVEPTIERx.NBUSYBKES = 1. This enables the Number of Busy Banks interrupt (USBHS_DEVEPTISRx.NBUSYBK).

635SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

• KILLBK: Kill IN Bank 0: Cleared when the bank is killed. 1: Set when USBHS_DEVEPTIERx.KILLBKS = 1. This kills the last written bank. Caution: The bank is really cleared when the “kill packet” procedure is accepted by the USBHS core. This bit is automati- cally cleared after the end of the procedure: The bank is really killed: USBHS_DEVEPTISRx.NBUSYBK is decremented. The bank is not cleared but sent (IN transfer): USBHS_DEVEPTISRx.NBUSYBK is decremented. The bank is not cleared because it was empty. The user should wait for this bit to be cleared before trying to kill another packet. This kill request is refused if at the same time an IN token is coming and the last bank is the current one being sent on the USB line. If at least two banks are ready to be sent, there is no problem to kill a packet even if an IN token is coming. Indeed, in this case, the current bank is sent (IN transfer) while the last bank is killed.
• FIFOCON: FIFO Control For control endpoints: The FIFOCON a nd RWALL bit s are irrelev ant. Therefore, the software never u ses them on the se endpoints . When read, their value is always 0. For IN endpoints: 0: Cleared (by writing a one to the USBHS_DEVEPTIDRx.FIFOCONC bit) to send the FIFO data and to switch to the next bank. 1: Set when the current bank is free, at the same time as USBHS_DEVEPTISRx.TX INI. For OUT endpoints: 0: Cleared (by writing a one to the USBHS_DEVEPTIDRx.FIFOCONC bit) to free the current bank and to switch to the next bank. 1: Set when the current bank is full, at the same time as USBHS_DEVEPTISRx.RXOUTI.
• EPDISHDMA: Endpoint Inte rrupts Disable HDMA Request This bit is set when USBHS_DEVEPTIERx.EPDISHDMAS = 1. This pauses the on-going DMA channel x transfer on any Endpoint x interrupt (PEP_x), whatever the state of the Endpoint x Interrupt Enable bit (PEP_x). The user then has to acknowledge or to disable the interrupt source (e.g. USBHS_DEVEPTISRx.RXOUTI) or to clear the EPDISHDMA bit (by writing a one to the USBHS_DEVEPTIDRx.EPDISHDMAC bit) in order to complete the DMA transfer. In Ping-pong mode, if the interrupt is associated to a new system-bank packet (e.g. Bank1) and the current DMA transfer is running on the previous packet (Bank0), then the previous-packet DMA transfer completes normally, but the new-packet DMA transfer does not start (not requested). If the interrupt is not associated to a new system-bank packet (USBHS_DEVEPTISRx.NAKINI, NAKOUTI, etc.), then the request cancellation may occur at any time and may immediately pause the current DMA transfer. This may be used for example to identify erroneous packets, to prevent them from being transferred into a buffer, to com- plete a DMA transfer by software after reception of a short packet, etc.
• RSTDT: Reset Data Toggle This bit is set when USBHS_DEVEPTIERx.RSTDTS = 1. This clears the data toggle sequence, i.e., sets to Data0 the data toggle sequence of the next sent (IN endpoints) or received (OUT endpoints) packet. This bit is cleared instantaneously. The user does not have to wait for this bit to be cleared.

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 636

37.6.23 Device Endpoint x Disable Register (Control, Bulk, Interrupt Endpoints)

Name: USBHS_DEVEPTIDRx [x=0..9] Address: 0x40038220 Access: Write-only This register view is relevant only if EPTYPE = 0x0, 0x2 or 0x3 in “Device Endpoint x Configuration Register” on page 616. For additional information, see “Device Endpoint x Mask Register (Control, Bulk, Interrupt Endpoints)” on page 630. This register always reads as zero. The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Clears the corresponding bit in USBHS_DEVEPTIMRx.

• TXINEC: Transmitted IN Interrupt Clear
• RXOUTEC: Received OUT Data Interrupt Clear
• RXSTPEC: Received SETUP Interrupt Clear
• NAKOUTEC: NAKed OUT Interrupt Clear
• NAKINEC: NAKed IN Interrupt Clear
• OVERFEC: Overflow Interrupt Clear
• STALLEDEC: STALLed Interrupt Clear
• SHORTPACKETEC: Shortpacket Interrupt Clear
• NBUSYBKEC: Number of Bu sy Banks Interrupt Clear
• FIFOCONC: FIFO Control Clear
• EPDISHDMAC: Endpoint Interrupts Disable HDMA Request Clear
• NYETDISC: NYET Token Disable Clear
• STALLRQC: STALL Request Clear 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 –––– S TALLRQC – N YETDISC EPDISHDMAC 15 14 13 12 11 10 9 8 76543210 SHORT PACKETEC STALLEDEC OVERFEC NAKINEC NAKOUTEC RXSTPEC RXOUTEC TXINEC

637SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

37.6.24 Device Endpoint x Disable Register (Isochronous Endpoints)

Name: USBHS_DEVEPTIDRx [x=0..9] (ISOENPT) Address: 0x40038220 Access: Write-only This register view is relevant only if EPTYPE = 0x1 in “Device Endpoint x Configuration Register” on page 616. For additional information, see “Device Endpoint x Mask Register (Isochronous Endpoints)” on page 633. This register always reads as zero. The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Clears the corresponding bit in USBHS_DEVEPTIMRx.

• TXINEC: Transmitted IN Interrupt Clear
• RXOUTEC: Received OUT Data Interrupt Clear
• UNDERFEC: Underflow Interrupt Clear
• HBISOINERREC: High Bandwidth Isochronous IN Error Interrupt Clear
• HBISOFLUSHEC: High Bandwidth Isochronous IN Flush Interrupt Clear
• OVERFEC: Overflow Interrupt Clear
• CRCERREC: CRC Error Interrupt Clear
• SHORTPACKETEC: Shortpacket Interrupt Clear
• MDATEC: MData Interrupt Clear
• DATAXEC: DataX Interrupt Clear
• ERRORTRANSEC: Transacti on Error Interrupt Clear
• NBUSYBKEC: Number of Bu sy Banks Interrupt Clear
• FIFOCONC: FIFO Control Clear
• EPDISHDMAC: Endpoint Interrupts Disable HDMA Request Clear 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 – FIFOCONC – NBUSYBKEC – ERRORTRANSEC DATAXEC MDATEC 76543210 SHORT PACKETEC CRCERREC OVERFEC HBISOFLUSHEC HBISOINERREC UNDERFEC RXOUTEC TXINEC

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 638

37.6.25 Device Endpoint x Enable Register (Control, Bulk, Interrupt Endpoints)

Name: USBHS_DEVEPTIERx [x=0..9] Address: 0x400381F0 Access: Write-only This register view is relevant only if EPTYPE = 0x0, 0x2or 0x3 in “Device Endpoint x Configuration Register” on page 616. For additional information, see “Device Endpoint x Mask Register (Control, Bulk, Interrupt Endpoints)” on page 630. This register always reads as zero. The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Sets the corresponding bit in USBHS_DEVEPTIMRx.

• TXINES: Transmitted IN Data Interrupt Enable
• RXOUTES: Received OUT Data Interrupt Enable
• RXSTPES: Received SE TUP Interrupt Enable
• NAKOUTES: NAKed OUT Interrupt Enable
• NAKINES: NAKed IN Interrupt Enable
• OVERFES: Overflow Interrupt Enable
• STALLEDES: STALLed Interrupt Enable
• SHORTPACKETES: Short Pa cket Interrupt Enable
• NBUSYBKES: Number of Bu sy Banks Interrupt Enable
• KILLBKS: Kill IN Bank
• FIFOCONS: FIFO Control
• EPDISHDMAS: Endpoint Interrupts Disable HDMA Request Enable
• NYETDISS: NYET Token Disable Enable
• RSTDTS: Reset Data Toggle Enable
• STALLRQS: STALL Request Enable 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 –––– S TALLRQS R STDTS N YETDISS EPDISHDMAS 15 14 13 12 11 10 9 8 – FIFOCONS KILLBKS NBUSYBKES –––– 76543210 SHORT PACKETES STALLEDES OVERFES NAKINES NAKOUTES RXSTPES RXOUTES TXINES

639SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

37.6.26 Device Endpoint x Enable Register (Isochronous Endpoints)

Name: USBHS_DEVEPTIERx [x=0..9] (ISOENPT) Address: 0x400381F0 Access: Write-only This register view is relevant only if EPTYPE = 0x1 in “Device Endpoint x Configuration Register” on page 616. For additional information, see “Device Endpoint x Mask Register (Isochronous Endpoints)” on page 633. This register always reads as zero. The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Clears the corresponding bit in USBHS_DEVEPTIMRx.

• TXINES: Transmitted IN Data Interrupt Enable
• RXOUTES: Received OUT Data Interrupt Enable
• UNDERFES: Underflow Interrupt Enable
• HBISOINERRES: High Bandwidth Isochronous IN Error Interrupt Enable
• HBISOFLUSHES: High Bandwidth Isochronous IN Flush Interrupt Enable
• OVERFES: Overflow Interrupt Enable
• CRCERRES: CRC Error Interrupt Enable
• SHORTPACKETES: Short Pa cket Interrupt Enable
• MDATAES: MData Interrupt Enable
• DATAXES: DataX Interrupt Enable
• ERRORTRANSES: Transaction Error Interrupt Enable
• NBUSYBKES: Number of Bu sy Banks Interrupt Enable
• KILLBKS: Kill IN Bank
• FIFOCONS: FIFO Control
• EPDISHDMAS: Endpoint Interrupts Disable HDMA Request Enable 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 –––– S TALLRQS R STDTS – E PDISHDMAS 15 14 13 12 11 10 9 8 – FIFOCONS KILLBKS NBUSYBKES – ERRORTRANSES DATAXES MDATAES 76543210 SHORT PACKETES CRCERRES OVERFES HBISOFLUSHES HBISO INERRES UNDERFES RXOUTES TXINES

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 640

• RSTDTS: Reset Data Toggle Enable
• STALLRQS: STALL Request Enable

641SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

37.6.27 Device DMA Channel x Next Descriptor Address Register

Name: USBHS_DEVDMANXTDSCx [x=1..7] Address: 0x40038310 [1], 0x40038320 [2], 0x40038330 [3], 0x40038340 [4], 0x40038350 [5], 0x40038360 [6], 0x40038370 [7] Access: Read/Write

• NXT_DSC_ADD: Next Descriptor Address This field points to the next channel descriptor to be processed. This channel descriptor must be aligned, so bits 0 to 3 of the address must be equal to zero. 31 30 29 28 27 26 25 24 NXT_DSC_ADD 23 22 21 20 19 18 17 16 NXT_DSC_ADD 15 14 13 12 11 10 9 8 NXT_DSC_ADD 76543210 NXT_DSC_ADD

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 642

37.6.28 Device DMA Channel x Address Register

Name: USBHS_DEVDMAADDRESSx [x=1..7] Address: 0x40038314 [1], 0x40038324 [2], 0x40038334 [3], 0x40038344 [4], 0x40038354 [5], 0x40038364 [6], 0x40038374 [7] Access: Read/Write

• BUFF_ADD: Buffer Address This field determines the AHB bus starting address of a DMA channel transfer. Channel start and end addresses may be aligned on any byte boundary. The firmware can write this field only when the USBHS_DEVDMASTATUS.CHANN_ENB bit is clear. This field is updated at the end of the address phase of the current access to the AHB bus. It is incremented by the access byte width. The access width is 4 bytes (or less) at packet start or end, if the start or end address is not aligned on a word boundary. The packet start address is either the channel start address or the next channel address to be accessed in the channel buf- fer. The packet end address is either the channel end address or the latest channel address accessed in the channel buffer. The channel start address is written by software or loaded from the descriptor. The channel end address is either deter- mined by the end of buffer or the USB device, or by the USB end of transfer if the USBHS_DEVDMACONTROLx.END_TR_EN bit is set. 31 30 29 28 27 26 25 24 BUFF_ADD 23 22 21 20 19 18 17 16 BUFF_ADD 15 14 13 12 11 10 9 8 BUFF_ADD 76543210 BUFF_ADD

643SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

37.6.29 Device DMA Chan nel x Control Register

Name: USBHS_DEVDMACONTROLx [x=1..7] Address: 0x40038318 [1], 0x40038328 [2], 0x40038338 [3], 0x40038348 [4], 0x40038358 [5], 0x40038368 [6], 0x40038378 [7] Access: Read/Write

• CHANN_ENB: Channel Enable Command 0: The DMA channel is disabled at end of transfer and no transfer occurs upon request. This bit is also cleared by hard- ware when the channel source bus is disabled at end of buffer. If the LDNXT_DSC bit has been cleared by descriptor loading, the firmware must set the corresponding CHANN_ENB bit to start the described transfer, if needed. If the LDNXT_DSC bit is cleared, the channel is frozen and the channel registers may then be read and/or written reli- ably as soon as both USBHS_DEVDMASTATUS.CHANN_ENB and CHANN_ACT flags read as 0. If a channel request is currently s erviced when this bit is cleared, the DMA FIFO buffer is drained until it is empty, then the USBHS_DEVDMASTATUS.CHANN_ENB bit is cleared. If the LDNXT_DSC bit is set at or after this bit clearing, then the currently loaded descriptor is skipped (no data transfer occurs) and the next descriptor is immediately loaded. 1: The USBHS_DEVDMASTATUS.CHANN_ENB bit is set, thus enabling the DMA channel data transfer. Then, any pend- ing request starts the transfer. This may be used to start or resume any requested transfer.
• LDNXT_DSC: Load Next Channel Transfer Descriptor Enable Command 0: No channel register is loaded after the end of the channel transfer. 1: The channel controller loads the next descriptor after the end of the current transfer, i.e., when the USBHS_DEVDMASTATUS.CHANN_ENB bit is reset. If the CHANN_ENB bit is cleared, the next descriptor is immediately loaded upon transfer request. DMA Channel Control Command Summary: 31 30 29 28 27 26 25 24 BUFF_LENGTH 23 22 21 20 19 18 17 16 BUFF_LENGTH 15 14 13 12 11 10 9 8 76543210 BURST_LCK DESC_LD_IT END_BUFFIT END_TR_IT END_B_EN END_TR_EN LDNXT_DSC CHANN_ENB Value LDNXT_DSC Value CHANN_ENB Name Description 0 0 STOP_NOW Stop now 0 1 RUN_AND_STOP Run and stop at end of buffer 1 0 LOAD_NEXT_DESC Load next descriptor now 1 1 RUN_AND_LINK Run and link at end of buffer

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 644

• END_TR_EN: End of Transfer Enable Control (OUT transfers only) 0: The USB end of transfer is ignored. 1: The USBHS device can put an end to the current buffer transfer. When set, a BULK or INTERRUPT short packet or the last packet of an ISOCHRONOUS (micro) frame (DATAX) closes the current buffer and the USBHS_DEVDMASTATUSx.END_TR_ST flag is raised. This is intended for a USBHS non-prenegotiated end of transfer (BULK or INTERRUPT) or ISOCHRONOUS microframe data buffer closure.
• END_B_EN: End of Buffer Enable Control 0: DMA Buffer End has no impact on USB packet transfer. 1: The endpoint can validate the packet (according to the values programmed in the USBHS_DEVEPTCFGx.AUTOSW and USBHS_DEVEPTIERx.SHORTPACKETES fields) at DMA Buffer End, i.e., when USBHS_DEVDMASTATUS.BUFF_COUNT reaches 0. This is mainly for short packet IN validations initiated by the DMA reaching end of buffer, but can be used for OUT packet truncation (discarding of unwanted packet data) at the end of DMA buffer.
• END_TR_IT: End of Transfer Interrupt Enable 0: USBHS device-initiated buffer transfer completion does not trigger any interrupt at USBHS_DEVDMASTATUSx.END_TR_ST rising. 1: An interrupt is sent after the buffer transfer is complete, if the USBHS device has ended the buffer transfer. Use when the receive size is unknown.
• END_BUFFIT: End of Buffer Interrupt Enable 0: USBHS_DEVDMA_STATUSx.END_BF_ST rising does not trigger any interrupt. 1: An interrupt is generated when USBHS_HSTDMASTATUSx.BUFF_COUNT reaches zero.
• DESC_LD_IT: Descriptor Loaded Interrupt Enable 0: USBHS_DEVDMASTATUSx.DESC_LDST rising does not trigger any interrupt. 1: An interrupt is generated when a descriptor has been loaded from the bus.
• BURST_LCK: Burst Lock Enable 0: The DMA never locks bus access. 1: USB packets AHB data bursts are locked for maximum optimization of the bus bandwidth usage and maximization of fly- by AHB burst duration.
• BUFF_LENGTH: Buffer Byte Length (Write-only) This field determines the number of bytes to be transferred until end of buffer. The maximum channel transfer size (32 KBytes) is reached when this field is 0 (default value). If the transfer size is unknown, this field should be set to 0, but the transfer end may occur earlier under USB device control. When this field is written, the USBHS_DEVDMASTATUSx.BUFF_COUNT field is updated with the write value. Notes: 1. Bits [31:2] are only writable when issui ng a channel Control Command other than “Stop Now”. 2. For reliability, it is highly recommended to wait for both the USBHS _DEVDMASTATUSx.CHAN_ACT and the USBHS_DEVDMASTATUSx.CHAN_ENB flags to be at 0, thus ensuring the channel has been stopped before issuing a command other than “Stop Now”.

645SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

37.6.30 Device DMA Channel x Status Register

Name: USBHS_DEVDMASTATUSx [x=1..7] Address: 0x4003831C [1], 0x4003832C [2], 0x4003833C [3], 0x4003834C [4], 0x4003835C [5], 0x4003836C [6], 0x4003837C [7] Access: Read/Write

• CHANN_ENB: Channel Enable Status 0: If cleared, the DMA channel no longer transfers data, and may load the next descriptor if the USBHS_DEVDMACONTROLx.LDNXT_DSC bit is set. When any transfer is ended either due to an elapsed byte count or to completion of a USBHS device-initiated transfer, this bit is automatically reset. 1: If set, the DMA channel is currently enabled and transfers data upon request. This bit is normally set or cleared by writing into the USBHS_DEVDMACONTROLx.CHANN_ENB bit field either by soft- ware or descriptor loading. If a channel request is currently serviced when the USBHS_DEVDMACONTROLx.CHANN_ENB bit is cleared, the DMA FIFO buffer is drained until it is empty, then this status bit is cleared.
• CHANN_ACT: Channel Active Status 0: The DMA channel is no longer trying to source the packet data. When a packet transfer is ended, this bit is automatically reset. 1: The DMA channel is currently trying to source packet data, i.e., selected as the highest-priority requesting channel. When a packet transfer cannot be completed due to an END_BF_ST, this flag stays set during the next channel descriptor load (if any) and potentially until completion of a USBHS packet transfer, if allowed by the new descriptor.
• END_TR_ST: End of Channel Transfer Status 0: Cleared automatically when read by software. 1: Set by hardware when the last packet transfer is complete, if the USBHS device has ended the transfer. Valid until the CHANN_ENB flag is cleared at the end of the next buffer transfer.
• END_BF_ST: End of Channel Buffer Status 0: Cleared automatically when read by software. 1: Set by hardware when the BUFF_COUNT count-down reaches zero. Valid until the CHANN_ENB flag is cleared at the end of the next buffer transfer. 31 30 29 28 27 26 25 24 BUFF_COUNT 23 22 21 20 19 18 17 16 BUFF_COUNT 15 14 13 12 11 10 9 8 76543210 – DESC_LDST END_BF_ST END_TR_ST – – CHANN_ACT CHANN_ENB

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 646

• DESC_LDST: Descriptor Loaded Status 0: Cleared automatically when read by software. 1: Set by hardware when a descriptor has been loaded from the system bus. Valid until the CHANN_ENB flag is cleared at the end of the next buffer transfer.
• BUFF_COUNT: Buffer Byte Count This field determines the current number of bytes still to be transferred for this buffer. This field is decremented from the AHB source bus access byte width at the end of this bus address phase. The access byte width is 4 by default, or less, at DMA start or end, if the start or end address is not aligned on a word boundary. At the end of buffer, the DMA accesses the USBHS device only for the number of bytes needed to complete it. Note: For OUT endpoints, if the receive buffer byte length (B UFF_LENGTH) has been defaulted to zero because the USB transfer length is unknown, the actual buffer byte length received is 0x10000-BUFF_COUNT.

647SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

37.6.31 Host General Control Register

Name: USBHS_HSTCTRL Address: 0x40038400 Access: Read/Write

• SOFE: Start of Frame Generation Enable 0: Disables the SOF generation and leaves the USB bus in idle state. 1: Generates SOF on the USB bus in Full- or High-speed mode and sends “keep alive” signals in Low-speed mode. This bit is set when a USB reset is requested or an upstream resume interrupt is detected (USBHS_HSTISR.TXRSMI).
• RESET: Send USB Reset 0: No effect. 1: Generates a USB Reset on the USB bus. This bit is cleared when the USB Reset has been sent. It may be useful to write a zero to this bit when a device disconnection is detected (USBHS_HSTISR.DDISCI = 1) whereas a USB Reset is being sent.
• RESUME: Send USB Resume 0: No effect. 1: Generates a USB Resume on the USB bus. This bit is cleared when the USB Resume has been sent or when a USB reset is requested. This bit should be written to one only when the start of frame generation is enabled (SOFE = 1).
• SPDCONF: Mode Configuration This field contains the host speed capability:. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 – – SPDCONF – RESUME RESET SOFE 76543210 Value Name Description 0N ORMAL The host starts in Full-speed mode and performs a high-speed reset to switch to High-speed mode if the downstream peripheral is high-speed capable. 1 LOW_POWER For a better consumption, if high speed is not needed.

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37.6.32 Host Global Interrupt Status Register

Name: USBHS_HSTISR Address: 0x40038404 Access: Read-only

• DCONNI: Device Connection Interrupt 0: Cleared when USBHS_HSTICR.DCONNIC = 1. 1: Set when a new device has been connected to the USB bus.
• DDISCI: Device Disconnection Interrupt 0: Cleared when USBHS_HSTICR.DDISCIC = 1. 1: Set when the device has been removed from the USB bus.
• RSTI: USB Reset Sent Interrupt 0: Cleared when USBHS_HSTICR.RSTIC = 1. 1: Set when a USB Reset has been sent to the device.
• RSMEDI: Downstream Re sume Sent Interrupt 0: Cleared when USBHS_HSTICR.RSMEDIC = 1. 1: Set when a Downstream Resume has been sent to the device.
• RXRSMI: Upstream Resume Received Interrupt 0: Cleared when USBHS_HSTICR.RXRSMIC = 1. 1: Set when an Upstream Resume has been received from the device.
• HSOFI: Host Start of Frame Interrupt 0: Cleared when USBHS_HSTICR.HSOFIC = 1. 1: Set when a SOF is issued by the host controller. This triggers a USB interrupt when HSOFE = 1. When using the host controller in Low-speed mode, this bit is also set when a keep-alive is sent.
• HWUPI: Host Wake-Up Interrupt This bit is set when the host controller is in Suspend mode (SOFE = 0) and an upstream resume from the peripheral is detected. This bit is set when the host controller is in Suspend mode (SOFE = 0) and a peripheral disconnection is detected. This interrupt is generated even if the clock is frozen by the USBHS_CTRL.FRZCLK bit. 31 30 29 28 27 26 25 24 DMA_7 DMA_6 DMA_5 DMA_4 DMA_3 DMA_2 DMA_1 – 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 PEP_7 PEP_6 PEP_5 PEP_4 PEP_3 PEP_2 PEP_1 PEP_0 76543210 – HWUPI HSOFI RXRSMI RSMEDI RSTI DDISCI DCONNI

649SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

• PEP_x: Pipe x Interrupt 0: Cleared when the interrupt source is served. 1: Set when an interrupt is triggered by pipe x (USBHS_HSTPIPISRx). This triggers a USB interrupt if the corresponding bit in USBHS_HSTIMR = 1.
• DMA_x: DMA Channel x Interrupt 0: Cleared when the USBHS_HSTDMASTATUSx interrupt source is cleared. 1: Set when an interrupt is triggered by the DMA channel x. This triggers a USB interrupt if the corresponding bit in USBHS_HSTIMR = 1.

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 650

37.6.33 Host Global Interrupt Clear Register

Name: USBHS_HSTICR Address: 0x40038408 Access: Write-only This register always reads as zero. The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Clears the corresponding bit in USBHS_HSTISR.

• DCONNIC: Device Connection Interrupt Clear
• DDISCIC: Device Disconnection Interrupt Clear
• RSTIC: USB Reset Se nt Interrupt Clear
• RSMEDIC: Downstream Resume Sent Interrupt Clear
• RXRSMIC: Upstream Resume Received Interrupt Clear
• HSOFIC: Host Start of Frame Interrupt Clear
• HWUPIC: Host Wake-Up Interrupt Clear 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 – HWUPIC HSOFIC RXRSMIC RSMEDIC RSTIC DDISCIC DCONNIC

651SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

37.6.34 Host Global Interrupt Set Register

Name: USBHS_HSTIFR Address: 0x4003840C Access: Write-only This register always reads as zero. The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Sets the corresponding bit in USBHS_HSTISR, which may be useful for test or debug purposes.

• DCONNIS: Device Connection Interrupt Set
• DDISCIS: Device Disconnection Interrupt Set
• RSTIS: USB Reset Sent Interrupt Set
• RSMEDIS: Downstream Resume Sent Interrupt Set
• RXRSMIS: Upstream Resume Received Interrupt Set
• HSOFIS: Host Start of Frame Interrupt Set
• HWUPIS: Host Wake-Up Interrupt Set
• DMA_x: DMA Channel x Interrupt Set 31 30 29 28 27 26 25 24 DMA_7 DMA_6 DMA_5 DMA_4 DMA_3 DMA_2 DMA_1 – 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 – HWUPIS HSOFIS RXRSMIS RSME DIS RSTIS DDISCIS DCONNIS

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 652

37.6.35 Host Global Interrupt Mask Register

Name: USBHS_HSTIMR Address: 0x40038410 Access: Read-only

• DCONNIE: Device Connection Interrupt Enable 0: Cleared when USBHS_HSTIDR.DCONNIEC = 1. This disables the Device Connection interrupt (USBHS_HSTISR.DCONNI). 1: Set when USBHS_HSTIER.DCONNIES = 1. This enables the Device Connection interrupt (USBHS_HSTISR.DCONNI).
• DDISCIE: Device Disconnection Interrupt Enable 0: Cleared when USBHS_HSTIDR.DDISCIEC = 1. This disables the Device Disconnection interrupt (USBHS_HSTISR.DDISCI). 1: Set when USBHS_HSTIER.DDISCIES = 1. This enables the Device Disconnection interrupt (USBHS_HSTISR.DDISCI).
• RSTIE: USB Reset Sent Interrupt Enable 0: Cleared when USBHS_HSTIDR.RSTIEC = 1. This disables the USB Reset Sent interrupt (USBHS_HSTISR.RSTI). 1: Set when USBHS_HSTIER.RSTIES = 1. This enables the USB Reset Sent interrupt (USBHS_HSTISR.RSTI).
• RSMEDIE: Downstream Resu me Sent Interrupt Enable 0: Cleared when USBHS_HSTIDR.RSMEDIEC = 1. This disables the Downstream Resume interrupt (USBHS_HSTISR.RSMEDI). 1: Set when USBHS_HSTIER.RSMEDIES = 1. This enables the Downstream Resume interrupt (USBHS_HSTISR.RSMEDI).
• RXRSMIE: Upstream Resume Received Interrupt Enable 0: Cleared when USBHS_HSTIDR.RXRSMIEC= 1. This disables the Downstream Resume interrupt (USBHS_HSTISR.RXRSMI). 1: Set when USBHS_HSTIER.RXRSMIES = 1. This enables the Upstream Resume Received interrupt (USBHS_HSTISR.RXRSMI).
• HSOFIE: Host Start of Frame Interrupt Enable 0: Cleared when USBHS_HSTIDR.HSOFIEC = 1. This disables the Host Start of Frame interrupt (USBHS_HSTISR.HSOFI). 1: Set when USBHS_HSTIER.HSOFIES= 1. This enables the Host Start of Frame interrupt (USBHS_HSTISR.HSOFI). 31 30 29 28 27 26 25 24 DMA_7 DMA_6 DMA_5 DMA_4 DMA_3 DMA_2 DMA_1 – 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 PEP_7 PEP_6 PEP_5 PEP_4 PEP_3 PEP_2 PEP_1 PEP_0 76543210 – HWUPIE HSOFIE RXRSMIE RSME DIE RSTIE DDISCIE DCONNIE

653SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

• HWUPIE: Host Wake-Up Interrupt Enable 0: Cleared when USBHS_HSTIDR.HWUPIEC = 1. This disables the Host Wake-up Interrupt (USBHS_HSTISR.HWUPI). 1: Set when USBHS_HSTIER.HWUPIES = 1. This enables the Host Wake-up Interrupt (USBHS_HSTISR.HWUPI).
• PEP_x: Pipe x Interrupt Enable 0: Cleared when PEP_x = 1. This disables the Pipe x Interrupt (PEP_x). 1: Set when the corresponding bit in USBHS_HSTIER = 1. This enables the Pipe x Interrupt (USBHS_HSTISR.PEP_x).
• DMA_x: DMA Channel x Interrupt Enable 0: Cleared when the corresponding bit in USBHS_HSTIDR = 1. This disables the DMA Channel x Interrupt (USBHS_HSTISR.DMA_x). 1: Set when the corresponding bit in USBHS_HSTIER = 1. This enables the DMA Channel x Interrupt (USBHS_HSTISR.DMA_x).

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 654

37.6.36 Host Global Interrupt Disable Register

Name: USBHS_HSTIDR Address: 0x40038414 Access: Write-only This register always reads as zero. The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Clears the corresponding bit in USBHS_HSTIMR.

• DCONNIEC: Device Conn ection Interrupt Disable
• DDISCIEC: Device Disconnection Interrupt Disable
• RSTIEC: USB Reset Se nt Interrupt Disable
• RSMEDIEC: Downstream Resume Sent Interrupt Disable
• RXRSMIEC: Upstream Resume Received Interrupt Disable
• HSOFIEC: Host Start of Frame Interrupt Disable
• HWUPIEC: Host Wake-Up Interrupt Disable
• PEP_x: Pipe x Interrupt Disable
• DMA_x: DMA Channel x Interrupt Disable 31 30 29 28 27 26 25 24 DMA_7 DMA_6 DMA_5 DMA_4 DMA_3 DMA_2 DMA_1 – 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 PEP_7 PEP_6 PEP_5 PEP_4 PEP_3 PEP_2 PEP_1 PEP_0 76543210 – HWUPIEC HSOFIEC RXRSMIEC RSMEDIEC RSTIEC DDISCIEC DCONNIEC

655SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

37.6.37 Host Global Interrupt Enable Register

Name: USBHS_HSTIER Address: 0x40038418 Access: Write-only This register always reads as zero. The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Sets the corresponding bit in USBHS_HSTISR.

• DCONNIES: Device Connection Interrupt Enable
• DDISCIES: Device Disconnection Interrupt Enable
• RSTIES: USB Reset Se nt Interrupt Enable
• RSMEDIES: Downstream Resu me Sent Interrupt Enable
• RXRSMIES: Upstream Resume Received Interrupt Enable
• HSOFIES: Host Start of Frame Interrupt Enable
• HWUPIES: Host Wake-Up Interrupt Enable
• PEP_x: Pipe x Interrupt Enable
• DMA_x: DMA Channel x Interrupt Enable 31 30 29 28 27 26 25 24 DMA_7 DMA_6 DMA_5 DMA_4 DMA_3 DMA_2 DMA_1 – 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 PEP_7 PEP_6 PEP_5 PEP_4 PEP_3 PEP_2 PEP_1 PEP_0 76543210 – HWUPIES HSOFIES RXRSMIES RSMEDIES RSTIES DDISCIES DCONNIES

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 656

37.6.38 Host Frame Number Register

Name: USBHS_HSTFNUM Address: 0x40038420 Access: Read/Write

• MFNUM: Micro Frame Number This field contains the current microframe number (can vary from 0 to 7), updated every 125 µs. When operating in Full-speed mode, this field is tied to zero.
• FNUM: Frame Number This field contains the current SOF number. This field can be written. In this case, the MFNUM field is reset to zero.
• FLENHIGH: Frame Length In High-speed mode, this field contains the 8 high-order bits of the 16-bit internal frame counter (at 30 MHz, the counter length is 3750 to ensure a SOF generation every 125 µs). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FLENHIGH 15 14 13 12 11 10 9 8 – – FNUM 76543210 FNUM MFNUM

657SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

37.6.39 Host Address 1 Register

Name: USBHS_HSTADDR1 Address: 0x40038424 Access: Read/Write

• HSTADDRP0: USB Host Address This field contains the address of the Pipe0 of the USB device. This field is cleared when a USB reset is requested.
• HSTADDRP1: USB Host Address This field contains the address of the Pipe1 of the USB device. This field is cleared when a USB reset is requested.
• HSTADDRP2: USB Host Address This field contains the address of the Pipe2 of the USB device. This field is cleared when a USB reset is requested.
• HSTADDRP3: USB Host Address This field contains the address of the Pipe3 of the USB device. This field is cleared when a USB reset is requested. 31 30 29 28 27 26 25 24 – HSTADDRP3 23 22 21 20 19 18 17 16 – HSTADDRP2 15 14 13 12 11 10 9 8 – HSTADDRP1 76543210 – HSTADDRP0

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 658

37.6.40 Host Address 2 Register

Name: USBHS_HSTADDR2 Address: 0x40038428 Access: Read/Write

• HSTADDRP4: USB Host Address This field contains the address of the Pipe4 of the USB device. This field is cleared when a USB reset is requested.
• HSTADDRP5: USB Host Address This field contains the address of the Pipe5 of the USB device. This field is cleared when a USB reset is requested.
• HSTADDRP6: USB Host Address This field contains the address of the Pipe6 of the USB device. This field is cleared when a USB reset is requested.
• HSTADDRP7: USB Host Address This field contains the address of the Pipe7 of the USB device. This field is cleared when a USB reset is requested. 31 30 29 28 27 26 25 24 – HSTADDRP7 23 22 21 20 19 18 17 16 – HSTADDRP6 15 14 13 12 11 10 9 8 – HSTADDRP5 76543210 – HSTADDRP4

659SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

37.6.41 Host Address 3 Register

Name: USBHS_HSTADDR3 Address: 0x4003842C Access: Read/Write

• HSTADDRP8: USB Host Address This field contains the address of the Pipe8 of the USB device. This field is cleared when a USB reset is requested.
• HSTADDRP9: USB Host Address This field contains the address of the Pipe9 of the USB device. This field is cleared when a USB reset is requested. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 – HSTADDRP9 76543210 – HSTADDRP8

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 660

37.6.42 Host Pipe Register

Name: USBHS_HSTPIP Address: 0x4003841C Access: Read/Write

• PENx: Pipe x Enable 0: Disables Pipe x, which forces the Pipe x state to inactive and resets the pipe x registers (USBHS_HSTPIPCFGx, USBHS_HSTPIPISRx, USBHS_HSTPIPIMRx), but not the pipe configuration (USBHS_HSTPIPCFGx.ALLOC, USBHS_HSTPIPCFGx.PBK, USBHS_HSTPIPCFGx.PSIZE). 1: Enables Pipe x.
• P R S T x : P i p e x R e s e t 0: Completes the reset operation and allows to start using the FIFO. 1: Resets the Pipe x FIFO. This resets the pipe x registers (USBHS_HSTPIPCFGx, USBHS_HSTPIPISRx, USBHS_HSTPIPIMRx), but not the pipe configuration (ALLOC, PBK, PSIZE, PTOKEN, PTYPE, PEPNUM, INTFRQ). The whole pipe mechanism (FIFO counter, reception, transmission, etc.) is reset, apart from the Data Toggle management. The pipe configuration remains active and the pipe is still enabled. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PRST7 PRST6 PRST5 PRST4 PRST3 PRST2 PRST1 PRST0 15 14 13 12 11 10 9 8 76543210 PEN7 PEN6 PEN5 PEN4 PEN3 PEN2 PEN1 PEN0

661SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

37.6.43 Host Pipe x Configuration Register

Name: USBHS_HSTPIPCFGx [x=0..9] Address: 0x40038500 Access: Read/Write For High-speed Bulk-out Pipe, see “Host Pipe x Configuration Register (High-speed Bulk-out or High-speed Control Pipe)” on page 664.

• ALLOC: Pipe Memory Allocate 0: Frees the pipe memory. 1: Allocates the pipe memory. This bit is cleared when a USB Reset is requested. Refer to Section 37.5.1.5 ”DPRAM Management” for more details.
• P B K : P i p e B a n k s This field contains the number of banks for the pipe. For control pipes, a single-bank pipe (0b00) should be selected. This field is cleared upon sending a USB reset. 31 30 29 28 27 26 25 24 INTFRQ 23 22 21 20 19 18 17 16 –––– PEPNUM 15 14 13 12 11 10 9 8 – – PTYPE – AUTOSW PTOKEN 76543210 – PSIZE PBK ALLOC – Value Name Description 0 1_BANK Single-bank pipe 1 2_BANK Double-bank pipe 2 3_BANK Triple-bank pipe 3– R eserved

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 662

• PSIZE: Pipe Size This field contains the size of each pipe bank. This field is cleared upon sending a USB reset.
• PTOKEN: Pipe Token This field contains the pipe token.
• AUTOSW: Automatic Switch This bit is cleared upon sending a USB reset. 0: The automatic bank switching is disabled. 1: The automatic bank switching is enabled.
• PTYPE: Pipe Type This field contains the pipe type. This field is cleared upon sending a USB reset.
• PEPNUM: Pipe Endpoint Number This field contains the number of the endpoint targeted by the pipe. This value is from 0 to 10. This field is cleared upon sending a USB reset. Value Name Description 0 8_BYTE 8 bytes 1 16_BYTE 16 bytes 2 32_BYTE 32 bytes 3 64_BYTE 64 bytes 4 128_BYTE 128 bytes 5 256_BYTE 256 bytes 6 512_BYTE 512 bytes 7 1024_BYTE 1024 bytes Value Name Description

0 SETUP SETUP

3– R e s e r v e d Value Name Description 0C T R L C o n t r o l

663SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

• INTFRQ: Pipe Interrupt Request Frequency This field contains the maximum value in milliseconds of the polling period for an Interrupt Pipe. This value has no effect for a non-Interrupt Pipe. This field is cleared upon sending a USB reset.

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 664

37.6.44 Host Pipe x Configuration Register (High-speed Bulk-out or High-speed Control Pipe)

Name: USBHS_HSTPIPCFGx [x=0..9] (HSBOHSCP) Address: 0x40038500 Access: Read/Write This configuration is relevant only if PTYPE = 0x0 or 0x2 in “Host Pipe x Configuration Register” on page 661.

• ALLOC: Pipe Memory Allocate 0: Frees the pipe memory. 1: Allocates the pipe memory. This bit is cleared when a USB Reset is requested. Refer to Section 37.5.1.5 ”DPRAM Management” for more details.
• P B K : P i p e B a n k s This field contains the number of banks for the pipe. For control pipes, a single-bank pipe (0b00) should be selected. This field is cleared upon sending a USB reset. 31 30 29 28 27 26 25 24 BINTERVAL 23 22 21 20 19 18 17 16 – – – PINGEN PEPNUM 15 14 13 12 11 10 9 8 – – PTYPE – AUTOSW PTOKEN 76543210 – PSIZE PBK ALLOC – Value Name Description 0 1_BANK Single-bank pipe 1 2_BANK Double-bank pipe 2 3_BANK Triple-bank pipe 3– R eserved

665SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

• PSIZE: Pipe Size This field contains the size of each pipe bank. This field is cleared upon sending a USB reset.
• PTOKEN: Pipe Token This field contains the pipe token.
• AUTOSW: Automatic Switch This bit is cleared upon sending a USB reset. 0: The automatic bank switching is disabled. 1: The automatic bank switching is enabled.
• PTYPE: Pipe Type This field contains the pipe type. This field is cleared upon sending a USB reset.
• PEPNUM: Pipe Endpoint Number This field contains the number of the endpoint targeted by the pipe. This value is from 0 to 10. This field is cleared upon sending a USB reset. Value Name Description 0 8_BYTE 8 bytes 1 16_BYTE 16 bytes 2 32_BYTE 32 bytes 3 64_BYTE 64 bytes 4 128_BYTE 128 bytes 5 256_BYTE 256 bytes 6 512_BYTE 512 bytes 7 1024_BYTE 1024 bytes Value Name Description

3– R e s e r v e d Value Name Description 0C T R L C o n t r o l 1– R e s e r v e d 2B L K B u l k 3– R e s e r v e d

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 666

• PINGEN: Ping Enable This bit is relevant for High-speed Bulk-out transaction only (including the control data stage and the control status stage). 0: Disables the ping protocol. 1: Enables the ping mechanism according to the USB 2.0 Standard. This bit is cleared upon sending a USB reset.
• BINTERVAL: Binterval Parameter for the Bulk-Out/Ping Transaction This field contains the Ping/Bulk-out period.  If BINTERVAL > 0 and PINGEN = 1, one PING token is sent every BINTERVAL microframe until it is ACKed by the peripheral.  If BINTERVAL = 0 and PINGEN = 1, multiple consecutive PING tokens are sent in the same microframe until they are ACKed.  If BINTERVAL > 0 and PINGEN = 0, one OUT token is sent every BINTERVAL microframe until it is ACKed by the peripheral.  If BINTERVAL = 0 and PINGEN = 0, multiple consecutive OUT tokens are sent in the same microframe until they are ACKed. This value must be in the range from 0 to 255.

667SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

37.6.45 Host Pipe x Status Register (Control, Bulk Pipes)

Name: USBHS_HSTPIPISRx [x=0..9] Address: 0x40038530 Access: Read-only This register view is relevant only if PTYPE = 0x0 or 0x2 in “Host Pipe x Configuration Register” on page 661.

• RXINI: Received IN Data Interrupt 0: Cleared when USBHS_HSTPIPICR.RXINIC = 1. 1: Set when a new USB message is stored in the current bank of the pipe. This triggers an interrupt if USBHS_HSTPIPIMR.RXINE = 1.
• TXOUTI: Transmitted OUT Data Interrupt 0: Cleared when USBHS_HSTPIPICR.TXOUTIC = 1. 1: Set when the current OUT bank is free and can be filled. This triggers an interrupt if USBHS_HSTPIPIMR.TXOUTE = 1.
• TXSTPI: Transmitted SETUP Interrupt 0: Cleared when USBHS_HSTPIPICR.TXSTPIC = 1. 1: Set, for control pipes, when the current SETUP bank is free and can be filled. This triggers an interrupt if USBHS_HSTPIPIMR.TXSTPE = 1.
• PERRI: Pipe Error Interrupt 0: Cleared when the error source bit is cleared. 1: Set when an error occurs on the current bank of the pipe. This triggers an interrupt if the USBHS_HSTPIPIMR.PERRE bit is set. Refer to the USBHS_HSTPIPERRx register to determine the source of the error.
• NAKEDI: NAKed Interrupt 0: Cleared when USBHS_HSTPIPICR.NAKEDIC = 1. 1: Set when a NAK has been received on the current bank of the pipe. This triggers an interrupt if USBHS_HSTPIPIMR.NAKEDE = 1.
• OVERFI: Overflow Interrupt 0: Cleared when USBHS_HSTPIPICR.OVERFIC = 1. 1: Set when the current pipe has received more data than the maximum length of the current pipe. An interrupt is triggered if USBHS_HSTPIPIMR.OVERFIE = 1. 31 30 29 28 27 26 25 24 – PBYCT 23 22 21 20 19 18 17 16 PBYCT – CFGOK – RWALL 15 14 13 12 11 10 9 8 CURRBK NBUSYBK – – DTSEQ 76543210 SHORTPACKETI RXSTALLDI OVERFI N AKEDI PERRI TXSTPI TXOUTI RXINI

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 668

• RXSTALLDI: Received STALLed Interrupt This bit is set when a STALL handshake has been received on the current bank of the pipe. The pipe is automatically fro- zen. This triggers an interrupt if USBHS_HSTPIPIMR.RXSTALLE = 1. 0: Cleared when USBHS_HSTPIPICR.RXSTALLDIC = 1.
• SHORTPACKETI: Short Packet Interrupt 0: Cleared when USBHS_HSTPIPICR.SHORTPACKETIC = 1. 1: Set when a short packet is received by the host controller (packet length inferior to the PSIZE programmed field).
• DTSEQ: Data Toggle Sequence This field indicates the data PID of the current bank. For an OUT pipe, this field indicates the data toggle of the next packet that is to be sent. For an IN pipe, this field indicates the data toggle of the received packet stored in the current bank.
• NBUSYBK: Number of Busy Banks This field indicates the number of busy banks. For an OUT pipe, this field indicates the number of busy banks, filled by the user, ready for OUT transfer. When all banks are busy, this triggers a PEP_x interrupt if USBHS_HSTPIPIMRx.NBUSYBKE = 1. For an IN pipe, this field indicates the number of busy banks filled by IN transaction from the Device. When all banks are free, this triggers a PEP_x interrupt if USBHS_HSTPIPIMRx.NBUSYBKE = 1.
• CURRBK: Current Bank For non-control pipe, this field indicates the number of the current bank. This field may be updated 1 clock cycle after the RWALL bit changes, so the user should not poll it as an interrupt bit. Value Name Description

2– R eserved 3– R eserved Value Name Description 0 0_BUSY 0 busy bank (all banks free) 1 1_BUSY 1 busy bank 2 2_BUSY 2 busy banks 3 3_BUSY 3 busy banks Value Name Description 3– R eserved

669SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

• RWALL: Read/Write Allowed For an OUT pipe, this bit is set when the current bank is not full, i.e., the software can write further data into the FIFO. For an IN pipe, this bit is set when the current bank is not empty, i.e., the software can read further data from the FIFO. This bit is cleared otherwise. This bit is also cleared when the RXSTALLDI or the PERRI bit = 1.
• CFGOK: Configuration OK Status This bit is set/cleared when the USBHS_HSTPIPCFGx.ALLOC bit is set. This bit is set if the pipe x number of banks (USBHS_HSTPIPCFGx.PBK) and size (USBHS_HSTPIPCFGx.PSIZE) are correct compared to the maximal allowed number of banks and size for this pipe and to the maximal FIFO size (i.e., the DPRAM size). If this bit is cleared, the user should rewrite correct values for the PBK and PSIZE fields in the USBHS_HSTPIPCFGx register.
• PBYCT: Pipe Byte Count This field contains the byte count of the FIFO. For an OUT pipe, the field is incremented after each byte written by the user into the pipe and decremented after each byte sent to the peripheral. For an IN pipe, the field is incremented after each byte received from the peripheral and decremented after each byte read by the user from the pipe. This field may be updated 1 clock cycle after the RWALL bit changes, so the user should not poll this field as an interrupt bit.

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 670

37.6.46 Host Pipe x Status Register (Interrupt Pipes)

Name: USBHS_HSTPIPISRx [x=0..9] (INTPIPES) Address: 0x40038530 Access: Read-only This register view is relevant only if PTYPE = 0x3 in “Host Pipe x Configuration Register” on page 661.

• RXINI: Received IN Data Interrupt 0: Cleared when USBHS_HSTPIPICR.RXINIC = 1. 1: Set when a new USB message is stored in the current bank of the pipe. This triggers an interrupt if the USBHS_HSTPIPIMR.RXINE bit = 1.
• TXOUTI: Transmitted OUT Data Interrupt 0: Cleared when USBHS_HSTPIPICR.TXOUTIC = 1. 1: Set when the current OUT bank is free and can be filled. This triggers an interrupt if USBHS_HSTPIPIMR.TXOUTE = 1.
• UNDERFI: Underflow Interrupt This bit is set, for an isochronous and interrupt IN/OUT pipe, when an error flow occurs. This triggers an interrupt if UNDERFIE = 1. This bit is set, for an isochronous or interrupt OUT pipe, when a transaction underflow occurs in the current pipe (the pipe cannot send the OUT data packet in time because the current bank is not ready). A zero-length-packet (ZLP) is sent instead. This bit is set, for an isochronous or interrupt IN pipe, when a transaction flow error occurs in the current pipe, i.e, the cur- rent bank of the pipe is not free while a new IN USB packet is received. This packet is not stored in the bank. For an interrupt pipe, the overflowed packet is ACKed to comply with the USB standard. This bit is cleared when USBHS_HSTPIPICR.UNDERFIEC = 1.
• PERRI: Pipe Error Interrupt 0: Cleared when the error source bit is cleared. 1: Set when an error occurs on the current bank of the pipe. This triggers an interrupt if the USBHS_HSTPIPIMR.PERRE bit is set. Refer to the USBHS_HSTPIPERRx register to determine the source of the error.
• NAKEDI: NAKed Interrupt 0: Cleared when USBHS_HSTPIPICR.NAKEDIC = 1. 1: Set when a NAK has been received on the current bank of the pipe. This triggers an interrupt if the USBHS_HSTPIPIMR.NAKEDE bit = 1. 31 30 29 28 27 26 25 24 – PBYCT 23 22 21 20 19 18 17 16 PBYCT – CFGOK – RWALL 15 14 13 12 11 10 9 8 CURRBK NBUSYBK – – DTSEQ 76543210 SHORTPACKETI RXSTALLDI OVERFI NAKEDI PERRI UNDERFI TXOUTI RXINI

671SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

• OVERFI: Overflow Interrupt 0: Cleared when USBHS_HSTPIPICR.OVERFIC = 1. 1: Set when the current pipe has received more data than the maximum length of the current pipe. An interrupt is triggered if the USBHS_HSTPIPIMR.OVERFIE bit = 1.
• RXSTALLDI: Received STALLed Interrupt 0: Cleared when USBHS_HSTPIPICR.RXSTALLDIC = 1. 1: Set when a STALL handshake has been received on the current bank of the pipe. The pipe is automatically frozen. This triggers an interrupt if USBHS_HSTPIPIMR.RXSTALLE = 1.
• SHORTPACKETI: Short Packet Interrupt 0: Cleared when USBHS_HSTPIPICR.SHORTPACKETIC = 1. 1: Set when a short packet is received by the host controller (packet length inferior to the PSIZE programmed field).
• DTSEQ: Data Toggle Sequence This field indicates the data PID of the current bank. For an OUT pipe, this field indicates the data toggle of the next packet that is to be sent. For an IN pipe, this field indicates the data toggle of the received packet stored in the current bank.
• NBUSYBK: Number of Busy Banks This field indicates the number of busy banks. For an OUT pipe, this field indicates the number of busy banks, filled by the user, ready for an OUT transfer. When all banks are busy, this triggers a PEP_x interrupt if USBHS_HSTPIPIMRx.NBUSYBKE = 1. For an IN pipe, this field indicates the number of busy banks filled by IN transaction from the device. When all banks are free, this triggers a PEP_x interrupt if USBHS_HSTPIPIMRx.NBUSYBKE = 1. Value Name Description

2– R eserved 3– R eserved Value Name Description 0 0_BUSY 0 busy bank (all banks free) 1 1_BUSY 1 busy bank 2 2_BUSY 2 busy banks 3 3_BUSY 3 busy banks

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 672

• CURRBK: Current Bank For a non-control pipe, this field indicates the number of the current bank. This field may be updated 1 clock cycle after the RWALL bit changes, so the user should not poll it as an interrupt bit.
• RWALL: Read/Write Allowed For an OUT pipe, this bit is set when the current bank is not full, i.e., the software can write further data into the FIFO. For an IN pipe, this bit is set when the current bank is not empty, i.e., the software can read further data from the FIFO. This bit is cleared otherwise. This bit is also cleared when RXSTALLDI or PERRI = 1.
• CFGOK: Configuration OK Status This bit is set/cleared when the USBHS_HSTPIPCFGx.ALLOC bit is set. This bit is set if the pipe x number of banks (USBHS_HSTPIPCFGx.PBK) and size (USBHS_HSTPIPCFGx.PSIZE) are correct compared to the maximal allowed number of banks and size for this pipe, and to the maximal FIFO size (i.e., the DPRAM size). If this bit is cleared, the user should rewrite correct values for the PBK and PSIZE fields in the USBHS_HSTPIPCFGx register.
• PBYCT: Pipe Byte Count This field contains the byte count of the FIFO. For an OUT pipe, the field is incremented after each byte written by the user into the pipe and decremented after each byte sent to the peripheral. For an IN pipe, the field is incremented after each byte received from the peripheral and decremented after each byte read by the user from the pipe. This field may be updated 1 clock cycle after the RWALL bit changes, so the user should not poll this field as an interrupt bit. Value Name Description

3– R eserved

673SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

37.6.47 Host Pipe x Status Register (Isochronous Pipes)

Name: USBHS_HSTPIPISRx [x=0..9] (ISOPIPES) Address: 0x40038530 Access: Read-only This register view is relevant only if PTYPE = 0x1 in “Host Pipe x Configuration Register” on page 661.

• RXINI: Received IN Data Interrupt 0: Cleared when USBHS_HSTPIPICR.RXINIC = 1. 1: Set when a new USB message is stored in the current bank of the pipe. This triggers an interrupt if USBHS_HSTPIPIMR.RXINE = 1.
• TXOUTI: Transmitted OUT Data Interrupt 0: Cleared when USBHS_HSTPIPICR.TXOUTIC = 1. 1: Set when the current OUT bank is free and can be filled. This triggers an interrupt if USBHS_HSTPIPIMR.TXOUTE = 1.
• UNDERFI: Underflow Interrupt This bit is set, for an isochronous and interrupt IN/OUT pipe, when an error flow occurs. This triggers an interrupt if the UNDERFIE bit = 1. This bit is set, for an isochronous or interrupt OUT pipe, when a transaction underflow occurs in the current pipe (the pipe cannot send the OUT data packet in time because the current bank is not ready). A zero-length-packet (ZLP) is sent instead. This bit is set, for an isochronous or interrupt IN pipe, when a transaction flow error occurs in the current pipe, i.e, the cur- rent bank of the pipe is not free while a new IN USB packet is received. This packet is not stored in the bank. For an interrupt pipe, the overflowed packet is ACKed to comply with the USB standard. This bit is cleared when USBHS_HSTPIPICR.UNDERFIEC = 1.
• PERRI: Pipe Error Interrupt 0: Cleared when the error source bit is cleared. 1: Set when an error occurs on the current bank of the pipe. This triggers an interrupt if the USBHS_HSTPIPIMR.PERRE bit is set. Refer to the USBHS_HSTPIPERRx register to determine the source of the error.
• NAKEDI: NAKed Interrupt 0: Cleared when USBHS_HSTPIPICR.NAKEDIC = 1. 1: Set when a NAK has been received on the current bank of the pipe. This triggers an interrupt if the USBHS_HSTPIPIMR.NAKEDE bit = 1. 31 30 29 28 27 26 25 24 – PBYCT 23 22 21 20 19 18 17 16 PBYCT – CFGOK – RWALL 15 14 13 12 11 10 9 8 CURRBK NBUSYBK – – DTSEQ 76543210 SHORTPACKETI CRCERRI OVERFI NAKEDI PERRI UNDERFI TXOUTI RXINI

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 674

• OVERFI: Overflow Interrupt 0: Cleared when USBHS_HSTPIPICR.OVERFIC = 1. 1: Set when the current pipe has received more data than the maximum length of the current pipe. An interrupt is triggered if the USBHS_HSTPIPIMR.OVERFIE bit = 1.
• CRCERRI: CRC Error Interrupt 0: Cleared when USBHS_HSTPIPICR.CRCERRIC = 1. 1: Set when a CRC error occurs on the current bank of the pipe. This triggers an interrupt if the USBHS_HSTPIPIMR.TXSTPE bit = 1.
• SHORTPACKETI: Short Packet Interrupt 0: Cleared when USBHS_HSTPIPICR.SHORTPACKETIC = 1. 1: Set when a short packet is received by the host controller (packet length inferior to the PSIZE programmed field).
• DTSEQ: Data Toggle Sequence This field indicates the data PID of the current bank. For an OUT pipe, this field indicates the data toggle of the next packet that is to be sent. For an IN pipe, this field indicates the data toggle of the received packet stored in the current bank.
• NBUSYBK: Number of Busy Banks This field indicates the number of busy banks. For an OUT pipe, this field indicates the number of busy banks, filled by the user, ready for an OUT transfer. When all banks are busy, this triggers a PEP_x interrupt if USBHS_HSTPIPIMRx.NBUSYBKE = 1. For an IN pipe, this field indicates the number of busy banks filled by IN transaction from the device. When all banks are free, this triggers a PEP_x interrupt if USBHS_HSTPIPIMRx.NBUSYBKE = 1. Value Name Description

2– R eserved 3– R eserved Value Name Description 0 0_BUSY 0 busy bank (all banks free) 1 1_BUSY 1 busy bank 2 2_BUSY 2 busy banks 3 3_BUSY 3 busy banks

675SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

• CURRBK: Current Bank For a non-control pipe, this field indicates the number of the current bank. This field may be updated 1 clock cycle after the RWALL bit changes, so the user should not poll it as an interrupt bit.
• RWALL: Read/Write Allowed For an OUT pipe, this bit is set when the current bank is not full, i.e., the software can write further data into the FIFO. For an IN pipe, this bit is set when the current bank is not empty, i.e., the software can read further data from the FIFO. This bit is cleared otherwise. This bit is also cleared when the RXSTALLDI or the PERRI bit = 1.
• CFGOK: Configuration OK Status This bit is set/cleared when the USBHS_HSTPIPCFGx.ALLOC bit is set. This bit is set if the pipe x number of banks (USBHS_HSTPIPCFGx.PBK) and size (USBHS_HSTPIPCFGx.PSIZE) are correct compared to the maximal allowed number of banks and size for this pipe and to the maximal FIFO size (i.e., the DPRAM size). If this bit is cleared, the user should rewrite correct values for the PBK and PSIZE fields in the USBHS_HSTPIPCFGx register.
• PBYCT: Pipe Byte Count This field contains the byte count of the FIFO. For an OUT pipe, the field is incremented after each byte written by the user into the pipe and decremented after each byte sent to the peripheral. For an IN pipe, the field is incremented after each byte received from the peripheral and decremented after each byte read by the user from the pipe. This field may be updated 1 clock cycle after the RWALL bit changes, so the user should not poll this field as an interrupt bit. Value Name Description

3– R eserved

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 676

37.6.48 Host Pipe x Clear Re gister (Control, Bulk Pipes)

Name: USBHS_HSTPIPICRx [x=0..9] Address: 0x40038560 Access: Write-only This register view is relevant only if PTYPE = 0x0 or 0x2 in “Host Pipe x Configuration Register” on page 661. For additional information, see “Host Pipe x Status Register (Control, Bulk Pipes)” on page 667. This register always reads as zero. The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Clears the corresponding bit in USBHS_HSTPIPISRx.

• RXINIC: Received IN Data Interrupt Clear
• TXOUTIC: Transmitted OUT Data Interrupt Clear
• TXSTPIC: Transmitted SETUP Interrupt Clear
• NAKEDIC: NAKed Interrupt Clear
• OVERFIC: Overflow Interrupt Clear
• RXSTALLDIC: Received STALLed Interrupt Clear
• SHORTPACKETIC: Short Packet Interrupt Clear 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 SHORT PACKETIC RXSTALLDIC OVERFIC NAKEDIC – TXSTPIC TXOUTIC RXINIC

677SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

37.6.49 Host Pipe x Clear Register (Interrupt Pipes)

Name: USBHS_HSTPIPICRx [x=0..9] (INTPIPES) Address: 0x40038560 Access: Write-only This register view is relevant only if PTYPE = 0x3 in “Host Pipe x Configuration Register” on page 661. For additional information, see “Host Pipe x Status Register (Interrupt Pipes)” on page 670. This register always reads as zero. The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Clears the corresponding bit in USBHS_HSTPIPISRx.

• RXINIC: Received IN Data Interrupt Clear
• TXOUTIC: Transmitted OUT Data Interrupt Clear
• UNDERFIC: Underflow Interrupt Clear
• NAKEDIC: NAKed Interrupt Clear
• OVERFIC: Overflow Interrupt Clear
• RXSTALLDIC: Received STALLed Interrupt Clear
• SHORTPACKETIC: Short Packet Interrupt Clear 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 SHORT PACKETIC RXSTALLDIC OVERFIC NAKEDIC – UNDERFIC TXOUTIC RXINIC

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 678

37.6.50 Host Pipe x Clear Register (Isochronous Pipes)

Name: USBHS_HSTPIPICRx [x=0..9] (ISOPIPES) Address: 0x40038560 Access: Write-only This register view is relevant only if PTYPE = 0x1 in “Host Pipe x Configuration Register” on page 661. For additional information, see “Host Pipe x Status Register (Isochronous Pipes)” on page 673. This register always reads as zero. The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Clears the corresponding bit in USBHS_HSTPIPISRx.

• RXINIC: Received IN Data Interrupt Clear
• TXOUTIC: Transmitted OUT Data Interrupt Clear
• UNDERFIC: Underflow Interrupt Clear
• NAKEDIC: NAKed Interrupt Clear
• OVERFIC: Overflow Interrupt Clear
• CRCERRIC: CRC Error Interrupt Clear
• SHORTPACKETIC: Short Packet Interrupt Clear 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 SHORT PACKETIC CRCERRIC OVERFIC NAKEDIC – UNDERFIC TXOUTIC RXINIC

679SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

37.6.51 Host Pipe x Set Register (Control, Bulk Pipes)

Name: USBHS_HSTPIPIFRx [x=0..9] Address: 0x40038590 Access: Write-only This register view is relevant only if PTYPE = 0x0 or 0x2 in “Host Pipe x Configuration Register” on page 661. For additional information, see “Host Pipe x Status Register (Control, Bulk Pipes)” on page 667. This register always reads as zero. The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Sets the corresponding bit in USBHS_HSTPIPISRx, which may be useful for test or debug purposes.

• RXINIS: Received IN Data Interrupt Set
• TXOUTIS: Transmitted OUT Data Interrupt Set
• TXSTPIS: Transmitted SETUP Interrupt Set
• PERRIS: Pipe E rror Interrupt Set
• NAKEDIS: NAKed Interrupt Set
• OVERFIS: Overflow Interrupt Set
• RXSTALLDIS: Received STALLed Interrupt Set
• SHORTPACKETIS: Short Packet Interrupt Set
• NBUSYBKS: Number of Busy Banks Set 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 SHORT PACKETIS RXSTALLDIS OVERFIS NAKEDIS PERRIS TXSTPIS TXOUTIS RXINIS

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 680

37.6.52 Host Pipe x Set Register (Interrupt Pipes)

Name: USBHS_HSTPIPIFRx [x=0..9] (INTPIPES) Address: 0x40038590 Access: Write-only This register view is relevant only if PTYPE = 0x3 in “Host Pipe x Configuration Register” on page 661. For additional information, see “Host Pipe x Status Register (Interrupt Pipes)” on page 670. This register always reads as zero. The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Sets the corresponding bit in USBHS_HSTPIPISRx, which may be useful for test or debug purposes.

• RXINIS: Received IN Data Interrupt Set
• TXOUTIS: Transmitted OUT Data Interrupt Set
• UNDERFIS: Underflow Interrupt Set
• PERRIS: Pipe E rror Interrupt Set
• NAKEDIS: NAKed Interrupt Set
• OVERFIS: Overflow Interrupt Set
• RXSTALLDIS: Received STALLed Interrupt Set
• SHORTPACKETIS: Short Packet Interrupt Set
• NBUSYBKS: Number of Busy Banks Set 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 SHORT PACKETIS RXSTALLDIS OVERFIS NAKEDIS PE RRIS UNDERFIS TXOUTIS RXINIS

681SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

37.6.53 Host Pipe x Set Register (Isochronous Pipes)

Name: USBHS_HSTPIPIFRx [x=0..9] (ISOPIPES) Address: 0x40038590 Access: Write-only This register view is relevant only if PTYPE = 0x1 in “Host Pipe x Configuration Register” on page 661. For additional information, see “Host Pipe x Status Register (Isochronous Pipes)” on page 673. This register always reads as zero. The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Sets the corresponding bit in USBHS_HSTPIPISRx, which may be useful for test or debug purposes.

• RXINIS: Received IN Data Interrupt Set
• TXOUTIS: Transmitted OUT Data Interrupt Set
• UNDERFIS: Underflow Interrupt Set
• PERRIS: Pipe E rror Interrupt Set
• NAKEDIS: NAKed Interrupt Set
• OVERFIS: Overflow Interrupt Set
• CRCERRIS: CRC Error Interrupt Set
• SHORTPACKETIS: Short Packet Interrupt Set
• NBUSYBKS: Number of Busy Banks Set 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 SHORT PACKETIS CRCERRIS OVERFIS NAKEDIS PERRIS UNDERFIS TXOUTIS RXINIS

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 682

37.6.54 Host Pipe x Mask Register (Control, Bulk Pipes)

Name: USBHS_HSTPIPIMRx [x=0..9] Address: 0x400385C0 Access: Read-only This register view is relevant only if PTYPE = 0x0 or 0x2 in “Host Pipe x Configuration Register” on page 661.

• RXINE: Received IN Data Interrupt Enable 0: Cleared when USBHS_HSTPIPIDR.RXINEC = 1. This disables the Transmitted IN Data interrupt (USBHS_HSTPIPIMR.RXINE). 1: Set when USBHS_HSTPIPIER.RXINES = 1. This enables the Transmitted IN Data interrupt (USBHS_HSTPIPIMR.RXINE).
• TXOUTE: Transmitted OU T Data Interrupt Enable 0: Cleared when USBHS_HSTPIPIDR.TXOUTEC = 1. This disables the Transmitted IN Data interrupt (USBHS_HSTPIPIMR.TXOUTE). 1: Set when USBHS_HSTPIPIER.TXOUTES = 1. This enables the Transmitted IN Data interrupt (USBHS_HSTPIPIMR.TXOUTE).
• TXSTPE: Transmitted SETUP Interrupt Enable 0: Cleared when USBHS_HSTPIPIDR.TXSTPEC = 1. This disables the Transmitted IN Data interrupt (USBHS_HSTPIPIMR.TXSTPE). 1: Set when USBHS_HSTPIPIER.TXSTPES = 1. This enables the Transmitted IN Data interrupt (USBHS_HSTPIPIMR.TXSTPE).
• PERRE: Pipe Error Interrupt Enable 0: Cleared when USBHS_HSTPIPIDR.PERREC = 1. This disables the Transmitted IN Data interrupt (USBHS_HSTPIPIMR.PERRE). 1: Set when USBHS_HSTPIPIER.PERRES = 1. This enables the Transmitted IN Data interrupt (USBHS_HSTPIPIMR.PERRE).
• NAKEDE: NAKed Interrupt Enable 0: Cleared when USBHS_HSTPIPIDR.NAKEDEC = 1. This disables the Transmitted IN Data interrupt (USBHS_HSTPIPIMR.NAKEDE). 1: Set when USBHS_HSTPIPIER.NAKEDES = 1. This enables the Transmitted IN Data interrupt (USBHS_HSTPIPIMR.NAKEDE). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ––––– R STDT P FREEZE P DISHDMA 15 14 13 12 11 10 9 8 76543210 SHORT PACKETIE RXSTALLDE OVERFIE NAKEDE PERRE TXSTPE TXOUTE RXINE

683SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

• OVERFIE: Overflow Interrupt Enable 0: Cleared when USBHS_HSTPIPIDR.OVERFIEC = 1. This disables the Transmitted IN Data interrupt (USBHS_HSTPIPIMR.OVERFIE). 1: Set when USBHS_HSTPIPIER.OVERFIES = 1. This enables the Transmitted IN Data interrupt (USBHS_HSTPIPIMR.OVERFIE).
• RXSTALLDE: Received STALLed Interrupt Enable 0: Cleared when USBHS_HSTPIPIDR.RXSTALLDEC = 1. This disables the Transmitted IN Data interrupt (USBHS_HSTPIPIMR.RXSTALLDE). 1: Set when USBHS_HSTPIPIER.RXSTALLDES = 1. This enables the Transmitted IN Data interrupt (USBHS_HSTPIPIMR.RXSTALLDE).
• SHORTPACKETIE: Short Packet Interrupt Enable 0: Cleared when USBHS_HSTPIPIDR.SHORTPACKETEC = 1. This disables the Transmitted IN Data IT (USBHS_HSTPIPIMR.SHORTPACKETE). 1: Set when USBHS_HSTPIPIER.SHORTPACKETIES = 1. This enables the Transmitted IN Data IT (USBHS_HSTPIPIMR.SHORTPACKETIE). If this bit is set for non-control OUT pipes, a short packet transmission is guaranteed upon ending a DMA transfer, thus sig- naling an end of transfer, provided that End of DMA Buffer Output Enable (USBHS_HSTDMACONTROL.END_B_EN) and Automatic Switch (USBHS_HSTPIPCFG.AUTOSW) = 1.
• NBUSYBKE: Number of Busy Banks Interrupt Enable 0: Cleared when USBHS_HSTPIPIDR.NBUSYBKEC = 1. This disables the Transmitted IN Data interrupt (USBHS_HSTPIPIMR.NBUSYBKE). 1: Set when USBHS_HSTPIPIER.NBUSYBKES = 1. This enables the Transmitted IN Data interrupt (USBHS_HSTPIPIMR.NBUSYBKE).
• FIFOCON: FIFO Control For OUT and SETUP pipes: 0: Cleared when USBHS_HSTPIPIDR.FIFOCONC = 1. This sends the FIFO data and switches the bank. 1: Set when the current bank is free, at the same time as USBHS_HSTPIPISR.TXOUTI or TXSTPI. For an IN pipe: 0: Cleared when USBHS_HSTPIPIDR.FIFOCONC = 1 . This frees the current bank and switches to the next bank. 1: Set when a new IN message is stored in the current bank, at the same time as USBHS_HSTPIPISR.RXINI.
• PDISHDMA: Pipe Interrupts Disable HDMA Request Enable See the USBHS_DEVEPTIMR.EPDISHDMA bit description.

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 684

• PFREEZE: Pipe Freeze 0: Cleared when USBHS_HSTPIPIDR.PFREEZEC = 1. This enables the pipe request generation. 1: Set when one of the following conditions is met: U SBHS_HSTPIPIER.PFREEZES=  The pipe is not configured. A STALL handshake has been received on the pipe.  An error has occurred on the pipe (USBHS_HSTPIPISR.PERRI = 1).  (INRQ+1) In requests have been processed. A P i p e R eset (USBHS_HSTPIP .PRSTx rising) has occurred.  A Pipe Enable (USBHS_HSTPIP .PEN rising) has occurred. This freezes the pipe request generation.
• RSTDT: Reset Data Toggle 0: No reset of the Data Toggle is ongoing. 0: Set when USBHS_HSTPIPIER.RSTDTS = 1. This resets the Data Toggle to its initial value for the current pipe.

685SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

37.6.55 Host Pipe x Mask Register (Interrupt Pipes)

Name: USBHS_HSTPIPIMRx [x=0..9] (INTPIPES) Address: 0x400385C0 Access: Read-only This register view is relevant only if PTYPE = 0x3 in “Host Pipe x Configuration Register” on page 661.

• RXINE: Received IN Data Interrupt Enable 0: Cleared when USBHS_HSTPIPIDR.RXINEC = 1. This disables the Transmitted IN Data interrupt (USBHS_HSTPIPIMR.RXINE). 1: Set when USBHS_HSTPIPIER.RXINES= 1. This enables the Transmitted IN Data interrupt (USBHS_HSTPIPIMR.RXINE).
• TXOUTE: Transmitted OU T Data Interrupt Enable 0: Cleared when USBHS_HSTPIPIDR.TXOUTEC = 1. This disables the Transmitted IN Data interrupt (USBHS_HSTPIPIMR.TXOUTE). 1: Set when USBHS_HSTPIPIER.TXOUTES = 1. This enables the Transmitted IN Data interrupt (USBHS_HSTPIPIMR.TXOUTE).
• UNDERFIE: Underflow Interrupt Enable 0: Cleared when USBHS_HSTPIPIDR.UNDERFIEC= 1. This disables the Transmitted IN Data interrupt (USBHS_HSTPIPIMR.UNDERFIE). 1: Set when USBHS_HSTPIPIER.UNDERFIES = 1. This enables the Transmitted IN Data interrupt (USBHS_HSTPIPIMR.UNDERFIE).
• PERRE: Pipe Error Interrupt Enable 0: Cleared when USBHS_HSTPIPIDR.PERREC = 1. This disables the Transmitted IN Data interrupt (USBHS_HSTPIPIMR.PERRE). 1: Set when USBHS_HSTPIPIER.PERRES = 1. This enables the Transmitted IN Data interrupt (USBHS_HSTPIPIMR.PERRE).
• NAKEDE: NAKed Interrupt Enable 0: Cleared when USBHS_HSTPIPIDR.NAKEDEC = 1. This disables the Transmitted IN Data interrupt (USBHS_HSTPIPIMR.NAKEDE). 1: Set when USBHS_HSTPIPIER.NAKEDES = 1. This enables the Transmitted IN Data interrupt (USBHS_HSTPIPIMR.NAKEDE). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ––––– R STDT P FREEZE P DISHDMA 15 14 13 12 11 10 9 8 76543210 SHORT PACKETIE RXSTALLDE OVERFIE NAKEDE PERRE UNDERFIE TXOUTE RXINE

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 686

• OVERFIE: Overflow Interrupt Enable 0: Cleared when USBHS_HSTPIPIDR.OVERFIEC = 1. This disables the Transmitted IN Data interrupt (USBHS_HSTPIPIMR.OVERFIE). 1: Set when USBHS_HSTPIPIER.OVERFIES = 1. This enables the Transmitted IN Data interrupt (USBHS_HSTPIPIMR.OVERFIE).
• RXSTALLDE: Received STALLed Interrupt Enable 0: Cleared when USBHS_HSTPIPIDR.RXSTALLDEC = 1. This disables the Transmitted IN Data interrupt (USBHS_HSTPIPIMR.RXSTALLDE). 1: Set when USBHS_HSTPIPIER.RXSTALLDES= 1. This enables the Transmitted IN Data interrupt (USBHS_HSTPIPIMR.RXSTALLDE).
• SHORTPACKETIE: Short Packet Interrupt Enable 0: Cleared when USBHS_HSTPIPIDR.SHORTPACKETEC = 1. This disables the Transmitted IN Data interrupt (USBHS_HSTPIPIMR.SHORTPACKETE). 1: Set when USBHS_HSTPIPIER.SHORTPACKETIES = 1. This enables the Transmitted IN Data interrupt (USBHS_HSTPIPIMR.SHORTPACKETIE). If this bit is set for non-control OUT pipes, a short packet transmission is guaranteed upon ending a DMA transfer, thus sig- naling an end of transfer, provided that the End of DMA Buffer Output Enable (USBHS_HSTDMACONTROL.END_B_EN) bit and the Automatic Switch (USBHS_HSTPIPCFG.AUTOSW) bit = 1.
• NBUSYBKE: Number of Busy Banks Interrupt Enable 0: Cleared when USBHS_HSTPIPIDR.NBUSYBKEC = 1. This disables the Transmitted IN Data interrupt (USBHS_HSTPIPIMR.NBUSYBKE). 1: Set when USBHS_HSTPIPIER.NBUSYBKES = 1. This enables the Transmitted IN Data interrupt (USBHS_HSTPIPIMR.NBUSYBKE).
• FIFOCON: FIFO Control For OUT and SETUP pipes: 0: Cleared when USBHS_HSTPIPIDR.FIFOCONC = 1. This sends the FIFO data and switches the bank. 1: Set when the current bank is free, at the same time as USBHS_HSTPIPISR.TXOUTI or TXSTPI. For IN pipes: 0: Cleared when USBHS_HSTPIPIDR.FIFOCONC = 1 . This frees the current bank and switches to the next bank. 1: Set when a new IN message is stored in the current bank, at the same time as USBHS_HSTPIPISR.RXINI.
• PDISHDMA: Pipe Interrupts Disable HDMA Request Enable See the USBHS_DEVEPTIMR.EPDISHDMA bit description.

687SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

• PFREEZE: Pipe Freeze 0: Cleared when USBHS_HSTPIPIDR.PFREEZEC = 1. This enables the pipe request generation. 1: Set when one of the following conditions is met: U SBHS_HSTPIPIER.PFREEZES = 1  The pipe is not configured. A STALL handshake has been received on the pipe.  An error has occurred on the pipe (USBHS_HSTPIPISR.PERRI = 1). ( I N R Q + 1 ) i n r e q u ests have been processed. A P i p e R eset (USBHS_HSTPIP .PRSTx rising) has occurred.  A Pipe Enable (USBHS_HSTPIP .PEN rising) has occurred. This freezes the pipe request generation.
• RSTDT: Reset Data Toggle 0: 0: No reset of the Data Toggle is ongoing. 1: Set when USBHS_HSTPIPIER.RSTDTS = 1. This resets the Data Toggle to its initial value for the current pipe.

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 688

37.6.56 Host Pipe x Mask Register (Isochronous Pipes)

Name: USBHS_HSTPIPIMRx [x=0..9] (ISOPIPES) Address: 0x400385C0 Access: Read-only This register view is relevant only if PTYPE = 0x1 in “Host Pipe x Configuration Register” on page 661.

• RXINE: Received IN Data Interrupt Enable 0: Cleared when USBHS_HSTPIPIDR.RXINEC = 1. This disables the Transmitted IN Data interrupt (USBHS_HSTPIPIMR.RXINE). 1: Set when USBHS_HSTPIPIER.RXINES = 1. This enables the Transmitted IN Data interrupt (USBHS_HSTPIPIMR.RXINE).
• TXOUTE: Transmitted OU T Data Interrupt Enable 0: Cleared when USBHS_HSTPIPIDR.TXOUTEC = 1. This disables the Transmitted IN Data interrupt (USBHS_HSTPIPIMR.TXOUTE). 1: Set when USBHS_HSTPIPIER.TXOUTES = 1. This enables the Transmitted IN Data interrupt (USBHS_HSTPIPIMR.TXOUTE).
• UNDERFIE: Underflow Interrupt Enable 0: Cleared when USBHS_HSTPIPIDR.UNDERFIEC = 1. This disables the Transmitted IN Data interrupt (USBHS_HSTPIPIMR.UNDERFIE). 1: Set when USBHS_HSTPIPIER.UNDERFIES = 1. This enables the Transmitted IN Data interrupt (USBHS_HSTPIPIMR.UNDERFIE).
• PERRE: Pipe Error Interrupt Enable 0: Cleared when USBHS_HSTPIPIDR.PERREC = 1. This disables the Transmitted IN Data interrupt (USBHS_HSTPIPIMR.PERRE). 1: Set when USBHS_HSTPIPIER.PERRES = 1. This enables the Transmitted IN Data interrupt (USBHS_HSTPIPIMR.PERRE).
• NAKEDE: NAKed Interrupt Enable 0: Cleared when USBHS_HSTPIPIDR.NAKEDEC = 1. This disables the Transmitted IN Data interrupt (USBHS_HSTPIPIMR.NAKEDE). 1: Set when USBHS_HSTPIPIER.NAKEDES = 1. This enables the Transmitted IN Data interrupt (USBHS_HSTPIPIMR.NAKEDE). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ––––– R STDT P FREEZE P DISHDMA 15 14 13 12 11 10 9 8 76543210 SHORT PACKETIE CRCERRE OVERFIE NAKEDE PERRE UNDERFIE TXOUTE RXINE

689SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

• OVERFIE: Overflow Interrupt Enable 0: Cleared when USBHS_HSTPIPIDR.OVERFIEC = 1. This disables the Transmitted IN Data interrupt (USBHS_HSTPIPIMR.OVERFIE). 1: Set when USBHS_HSTPIPIER.OVERFIES = 1. This enables the Transmitted IN Data interrupt (USBHS_HSTPIPIMR.OVERFIE).
• CRCERRE: CRC Error Interrupt Enable 0: Cleared when USBHS_HSTPIPIDR.CRCERREC = 1. This disables the Transmitted IN Data interrupt (USBHS_HSTPIPIMR.CRCERRE). 1: Set when USBHS_HSTPIPIER.CRCERRES = 1. This enables the Transmitted IN Data interrupt (USBHS_HSTPIPIMR.CRCERRE).
• SHORTPACKETIE: Short Packet Interrupt Enable 0: Cleared when USBHS_HSTPIPIDR.SHORTPACKETEC = 1. This disables the Transmitted interrupt Data IT (USBHS_HSTPIPIMR.SHORTPACKETE). 1: Set when USBHS_HSTPIPIER.SHORTPACKETIES = 1. This enables the Transmitted IN Data interrupt (USBHS_HSTPIPIMR.SHORTPACKETIE). If this bit is set for non-control OUT pipes, a short packet transmission is guaranteed upon ending a DMA transfer, thus sig- naling an end of transfer, provided that the End of DMA Buffer Output Enable (USBHS_HSTDMACONTROL.END_B_EN) bit and the Automatic Switch (USBHS_HSTPIPCFG.AUTOSW) bit = 1.
• NBUSYBKE: Number of Busy Banks Interrupt Enable 0: Cleared when USBHS_HSTPIPIDR.NBUSYBKEC = 1. This disables the Transmitted IN Data interrupt (USBHS_HSTPIPIMR.NBUSYBKE). 1: Set when USBHS_HSTPIPIER.NBUSYBKES = 1. This enables the Transmitted IN Data interrupt (USBHS_HSTPIPIMR.NBUSYBKE).
• FIFOCON: FIFO Control For OUT and SETUP pipes: 0: Cleared when USBHS_HSTPIPIDR.FIFOCONC = 1. This sends the FIFO data and switches the bank. 1: Set when the current bank is free, at the same time as USBHS_HSTPIPISR.TXOUTI or TXSTPI. For IN pipes: 0: Cleared when USBHS_HSTPIPIDR.FIFOCONC = 1 . This frees the current bank and switches to the next bank. 1: Set when a new IN message is stored in the current bank, at the same time as USBHS_HSTPIPISR.RXINI.
• PDISHDMA: Pipe Interrupts Disable HDMA Request Enable See the USBHS_DEVEPTIMR.EPDISHDMA bit description.

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 690

• PFREEZE: Pipe Freeze 0: Cleared when USBHS_HSTPIPIDR.PFREEZEC = 1. This enables the pipe request generation. 1: Set when one of the following conditions is met: U SBHS_HSTPIPIER.PFREEZES = 1.  The pipe is not configured. A STALL handshake has been received on the pipe.  An error has occurred on the pipe (USBHS_HSTPIPISR.PERRI = 1).  (INRQ+1) In requests have been processed. A P i p e R eset (USBHS_HSTPIP .PRSTx rising) has occurred.  A Pipe Enable (USBHS_HSTPIP .PEN rising) has occurred. This freezes the pipe request generation.
• RSTDT: Reset Data Toggle 0: No reset of the Data Toggle is ongoing. 1: Set when USBHS_HSTPIPIER.RSTDTS = 1. This resets the Data Toggle to its initial value for the current pipe.

691SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

37.6.57 Host Pipe x Disable Register (Control, Bulk Pipes)

Name: USBHS_HSTPIPIDRx [x=0..9] Address: 0x40038620 Access: Write-only This register view is relevant only if PTYPE = 0x0 or 0x2 in “Host Pipe x Configuration Register” on page 661. For additional information, see “Host Pipe x Mask Register (Control, Bulk Pipes)” on page 682. This register always reads as zero. The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Clears the corresponding bit in USBHS_HSTPIPIMRx.

• RXINEC: Received IN Data Interrupt Disable
• TXOUTEC: Transmitted OUT Data Interrupt Disable
• TXSTPEC: Transmitted SETUP Interrupt Disable
• PERREC: Pipe Erro r Interrupt Disable
• NAKEDEC: NAKed Interrupt Disable
• OVERFIEC: Overflow Interrupt Disable
• RXSTALLDEC: Received STALLed Interrupt Disable
• SHORTPACKETIEC: Short Pa cket Interrupt Disable
• NBUSYBKEC: Number of Busy Banks Disable
• FIFOCONC: FIFO Control Disable
• PDISHDMAC: Pipe Interrupts Disable HDMA Request Disable
• PFREEZEC: Pipe Freeze Disable 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 SHORT PACKETIEC RXSTALLDEC OVERFIEC NAKEDEC PERREC TXSTPEC TXOUTEC RXINEC

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 692

37.6.58 Host Pipe x Disable Register (Interrupt Pipes)

Name: USBHS_HSTPIPIDRx [x=0..9] (INTPIPES) Address: 0x40038620 Access: Write-only This register view is relevant only if PTYPE = 0x3 in “Host Pipe x Configuration Register” on page 661. For additional information, see “Host Pipe x Mask Register (Interrupt Pipes)” on page 685. This register always reads as zero. The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Clears the corresponding bit in USBHS_HSTPIPIMRx.

• RXINEC: Received IN Data Interrupt Disable
• TXOUTEC: Transmitted OUT Data Interrupt Disable
• UNDERFIEC: Underflow Interrupt Disable
• PERREC: Pipe Erro r Interrupt Disable
• NAKEDEC: NAKed Interrupt Disable
• OVERFIEC: Overflow Interrupt Disable
• RXSTALLDEC: Received STALLed Interrupt Disable
• SHORTPACKETIEC: Short Pa cket Interrupt Disable
• NBUSYBKEC: Number of Busy Banks Disable
• FIFOCONC: FIFO Control Disable
• PDISHDMAC: Pipe Interrupts Disable HDMA Request Disable
• PFREEZEC: Pipe Freeze Disable 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 SHORT PACKETIEC RXSTALLDEC OVERFIEC NAKEDEC PERREC UNDERFIEC TXOUTEC RXINEC

693SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

37.6.59 Host Pipe x Disable Register (Isochronous Pipes)

Name: USBHS_HSTPIPIDRx [x=0..9] (ISOPIPES) Address: 0x40038620 Access: Write-only This register view is relevant only if PTYPE = 0x1 in “Host Pipe x Configuration Register” on page 661. For additional information, see “Host Pipe x Mask Register (Isochronous Pipes)” on page 688. This register always reads as zero. The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Clears the corresponding bit in USBHS_HSTPIPIMRx.

• RXINEC: Received IN Data Interrupt Disable
• TXOUTEC: Transmitted OUT Data Interrupt Disable
• UNDERFIEC: Underflow Interrupt Disable
• PERREC: Pipe Erro r Interrupt Disable
• NAKEDEC: NAKed Interrupt Disable
• OVERFIEC: Overflow Interrupt Disable
• CRCERREC: CRC Error Interrupt Disable
• SHORTPACKETIEC: Short Pa cket Interrupt Disable
• NBUSYBKEC: Number of Busy Banks Disable
• FIFOCONC: FIFO Control Disable
• PDISHDMAC: Pipe Interrupts Disable HDMA Request Disable
• PFREEZEC: Pipe Freeze Disable 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 SHORT PACKETIEC CRCERREC OVERFIEC NAKEDEC PERREC UNDERFIEC TXOUTEC RXINEC

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 694

37.6.60 Host Pipe x Enable Register (Control, Bulk Pipes)

Name: USBHS_HSTPIPIERx [x=0..9] Address: 0x400385F0 Access: Write-only This register view is relevant only if PTYPE = 0x0 or 0x2 in “Host Pipe x Configuration Register” on page 661. For additional information, see “Host Pipe x Mask Register (Control, Bulk Pipes)” on page 682. This register always reads as zero. The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Sets the corresponding bit in USBHS_HSTPIPIMRx.

• RXINES: Received IN Data Interrupt Enable
• TXOUTES: Transmitted OUT Data Interrupt Enable
• TXSTPES: Transmitted SETUP Interrupt Enable
• PERRES: Pipe Erro r Interrupt Enable
• NAKEDES: NAKed Interrupt Enable
• OVERFIES: Overflow Interrupt Enable
• RXSTALLDES: Received STALLed Interrupt Enable
• SHORTPACKETIES: Short Packet Interrupt Enable
• NBUSYBKES: Number of Busy Banks Enable
• PDISHDMAS: Pipe Interrupts Disable HDMA Request Enable
• PFREEZES: Pipe Freeze Enable
• RSTDTS: Reset Data Toggle Enable 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ––––– R STDTS P FREEZES PDISHDMAS 15 14 13 12 11 10 9 8 76543210 SHORT PACKETIES RXSTALLDES OVERFIES NAKEDES PERRES TXSTPES TXOUTES RXINES

695SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

37.6.61 Host Pipe x Enable Register (Interrupt Pipes)

Name: USBHS_HSTPIPIERx [x=0..9] (INTPIPES) Address: 0x400385F0 Access: Write-only This register view is relevant only if PTYPE = 0x3 in “Host Pipe x Configuration Register” on page 661. For additional information, see “Host Pipe x Mask Register (Interrupt Pipes)” on page 685. This register always reads as zero. The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Sets the corresponding bit in USBHS_HSTPIPIMRx.

• RXINES: Received IN Data Interrupt Enable
• TXOUTES: Transmitted OUT Data Interrupt Enable
• UNDERFIES: Underflow Interrupt Enable
• PERRES: Pipe Erro r Interrupt Enable
• NAKEDES: NAKed Interrupt Enable
• OVERFIES: Overflow Interrupt Enable
• RXSTALLDES: Received STALLed Interrupt Enable
• SHORTPACKETIES: Short Packet Interrupt Enable
• NBUSYBKES: Number of Busy Banks Enable
• PDISHDMAS: Pipe Interrupts Disable HDMA Request Enable
• PFREEZES: Pipe Freeze Enable
• RSTDTS: Reset Data Toggle Enable 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ––––– R STDTS P FREEZES PDISHDMAS 15 14 13 12 11 10 9 8 76543210 SHORT PACKETIES RXSTALLDES OVERFIES NAKEDES PERRES UNDERFIES TXOUTES RXINES

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 696

37.6.62 Host Pipe x Enable Register (Isochronous Pipes)

Name: USBHS_HSTPIPIERx [x=0..9] (ISOPIPES) Address: 0x400385F0 Access: Write-only This register view is relevant only if PTYPE = 0x1 in “Host Pipe x Configuration Register” on page 661. For additional information, see “Host Pipe x Mask Register (Isochronous Pipes)” on page 688. This register always reads as zero. The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Sets the corresponding bit in USBHS_HSTPIPIMRx.

• RXINES: Received IN Data Interrupt Enable
• TXOUTES: Transmitted OUT Data Interrupt Enable
• UNDERFIES: Underflow Interrupt Enable
• PERRES: Pipe Erro r Interrupt Enable
• NAKEDES: NAKed Interrupt Enable
• OVERFIES: Overflow Interrupt Enable
• CRCERRES: CRC Error Interrupt Enable
• SHORTPACKETIES: Short Packet Interrupt Enable
• NBUSYBKES: Number of Busy Banks Enable
• PDISHDMAS: Pipe Interrupts Disable HDMA Request Enable
• PFREEZES: Pipe Freeze Enable
• RSTDTS: Reset Data Toggle Enable 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ––––– R STDTS P FREEZES PDISHDMAS 15 14 13 12 11 10 9 8 76543210 SHORT PACKETIES CRCERRES OVERFIES NAKEDES PERRE S UNDERFIES TXOUTES RXINES

697SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

37.6.63 Host Pipe x IN Request Register

Name: USBHS_HSTPIPINRQx [x=0..9] Address: 0x40038650 Access: Read/Write

• INRQ: IN Request Number before Freeze This field contains the number of IN transactions before the USBHS freezes the pipe. The USBHS performs (INRQ+1) IN requests before freezing the pipe. This counter is automatically decreased by 1 each time an IN request has been success- fully performed. This register has no effect when INMODE = 1.
• INMODE: IN Request Mode 0: Performs a pre-defined number of IN requests. This number is the INRQ field. 1: Enables the USBHS to perform infinite IN requests when the pipe is not frozen. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 INRQ

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 698

37.6.64 Host Pipe x Error Register

Name: USBHS_HSTPIPERRx [x=0..9] Address: 0x40038680 Access: Read/Write Writing a zero in a bit/field in this register clears the bit/field. Writing a one has no effect.

• DATATGL: Data Toggle Error 0: No Data Toggle error occurred since last clear of this bit. 1: This bit is automatically set when a Data Toggle error has been detected.
• DATAPID: Data PID Error 0: No Data PID error occurred since last clear of this bit. 1: This bit is automatically set when a Data PID error has been detected.
• PID: PID Error 0: No PID error occurred since last clear of this bit. 1: This bit is automatically set when a PID error has been detected.
• TIMEOUT: Time-Out Error 0: No Time-Out error occurred since last clear of this bit. 1: This bit is automatically set when a Time-Out error has been detected.
• CRC16: CRC16 Error 0: No CRC16 error occurred since last clear of this bit. 1: This bit is automatically set when a CRC16 error has been detected.
• COUNTER: Error Counter This field is incremented each time an error occurs (CRC16, TIMEOUT, PID, DATAPID or DATATGL). This field is cleared when receiving a USB packet free of error. When this field reaches 3 (i.e., 3 consecutive errors), this pipe is automatically frozen (USBHS_HSTPIPIMRx.PFREEZE is set). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 – COUNTER CRC16 TIMEOUT PID DATAPID DATATGL

699SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

37.6.65 Host DMA Channel x Next Descriptor Address Register

Name: USBHS_HSTDMANXTDSCx [x=1..7] Address: 0x40038710 [1], 0x40038720 [2], 0x40038730 [3], 0x40038740 [4], 0x40038750 [5], 0x40038760 [6], 0x40038770 [7] Access: Read/Write

• NXT_DSC_ADD: Next Descriptor Address This field points to the next channel descriptor to be processed. This channel descriptor must be aligned, so bits 0 to 3 of the address must be equal to zero. 31 30 29 28 27 26 25 24 NXT_DSC_ADD 23 22 21 20 19 18 17 16 NXT_DSC_ADD 15 14 13 12 11 10 9 8 NXT_DSC_ADD 76543210 NXT_DSC_ADD

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 700

37.6.66 Host DMA Channel x Address Register

Name: USBHS_HSTDMAADDRESSx [x=1..7] Address: 0x40038714 [1], 0x40038724 [2], 0x40038734 [3], 0x40038744 [4], 0x40038754 [5], 0x40038764 [6], 0x40038774 [7] Access: Read/Write

• BUFF_ADD: Buffer Address This field determines the AHB bus starting address of a DMA channel transfer. Channel start and end addresses may be aligned on any byte boundary. The firmware can write this field only when the USBHS_HSTDMASTATUS.CHANN_ENB bit is cleared. This field is updated at the end of the address phase of the current access to the AHB bus. It is incremented by the access byte width. The access width is 4 bytes (or less) at packet start or end, if the start or end address is not aligned on a word boundary. The packet start address is either the channel start address or the next channel address to be accessed in the channel buffer. The packet end address is either the channel end address or the latest channel address accessed in the channel buffer. The channel start address is written by software or loaded from the descriptor. The channel end address is either deter- mined by the end of buffer or the USB device, or by the USB end of transfer if the USBHS_HSTDMACONTROLx.END_TR_EN bit is set. 31 30 29 28 27 26 25 24 BUFF_ADD 23 22 21 20 19 18 17 16 BUFF_ADD 15 14 13 12 11 10 9 8 BUFF_ADD 76543210 BUFF_ADD

701SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

37.6.67 Host DMA Channel x Control Register

Name: USBHS_HSTDMACONTROLx [x=1..7] Address: 0x40038718 [1], 0x40038728 [2], 0x40038738 [3], 0x40038748 [4], 0x40038758 [5], 0x40038768 [6], 0x40038778 [7] Access: Read/Write

• CHANN_ENB: Channel Enable Command 0: The DMA channel is disabled and no transfer occurs upon request. This bit is also cleared by hardware when the chan- nel source bus is disabled at the end of the buffer. If the LDNXT_DSC bit has been cleared by descriptor loading, the firmware has to set the corresponding CHANN_ENB bit to start the described transfer, if needed. If the LDNXT_DSC bit is cleared, the channel is frozen and the channel registers may then be read and/or written reliably as soon as both the USBHS_HSTDMASTATUS.CHANN_ENB and the CHANN_ACT flags read as 0. If a channel request is currently serviced when this bit is cleared, the DMA FIFO buffer is drained until it is empty, then the USBHS_HSTDMASTATUS.CHANN_ENB bit is cleared. If the LDNXT_DSC bit is set or after it has been cleared, the currently loaded descriptor is skipped (no data transfer occurs) and the next descriptor is immediately loaded. 1: The USBHS_HSTDMASTATUS.CHANN_ENB bit is set, enabling DMA channel data transfer. Then, any pending request starts the transfer. This may be used to start or resume any requested transfer.
• LDNXT_DSC: Load Next Channel Transfer Descriptor Enable Command 0: No channel register is loaded after the end of the channel transfer. 1: The channel controller loads the next descriptor after the end of the current transfer, i.e., when the USBHS_HSTDMASTATUS.CHANN_ENB bit is reset. If the CHANN_ENB bit is cleared, the next descriptor is loaded immediately upon transfer request. DMA Channel Control Command Summary: 31 30 29 28 27 26 25 24 BUFF_LENGTH 23 22 21 20 19 18 17 16 BUFF_LENGTH 15 14 13 12 11 10 9 8 76543210 BURST_LCK DESC_LD_IT END_BUFFIT END_TR_IT END_B_EN END_TR_EN LDNXT_DSC CHANN_ENB Value LDNXT_DSC Value CHANN_ENB Name Description 0 0 STOP_NOW Stop now 0 1 RUN_AND_STOP Run and stop at end of buffer 1 0 LOAD_NEXT_DESC Load next descriptor now 1 1 RUN_AND_LINK Run and link at end of buffer

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 702

• END_TR_EN: End of Transfer Enable Control (OUT transfers only) 0: USB end of transfer is ignored. 1: The USBHS device can put an end to the current buffer transfer. When set, a BULK or INTERRUPT short packet closes the current buffer and the USBHS_HSTDMASTATUSx.END_TR_ST flag is raised. This is intended for a USBHS non-prenegotiated USB transfer size.
• END_B_EN: End of Buffer Enable Control 0: DMA Buffer End has no impact on USB packet transfer. 1: The pipe can validate the packet (according to the values programmed in the USBHS_HSTPIPCFGx.AUTOSW and USBHS_HSTPIPIMRx.SHORTPACKETIE fields) at DMA Buffer End, i.e., when USBHS_HSTDMASTATUS.BUFF_COUNT reaches 0. This is mainly for short packet OUT validations initiated by the DMA reaching the end of buffer, but could be used for IN packet truncation (discarding of unwanted packet data) at the end of DMA buffer.
• END_TR_IT: End of Transfer Interrupt Enable 0: Completion of a USBHS device-initiated buffer transfer does not trigger any interrupt at USBHS_HSTDMASTATUSx.END_TR_ST rising. 1: An interrupt is sent after the buffer transfer is complete, if the USBHS device has ended the buffer transfer. Use when the receive size is unknown.
• END_BUFFIT: End of Buffer Interrupt Enable 0: USBHS_HSTDMASTATUSx.END_BF_ST rising does not trigger any interrupt. 1: An interrupt is generated when USBHS_HSTDMASTATUSx.BUFF_COUNT reaches zero.
• DESC_LD_IT: Descriptor Loaded Interrupt Enable 0: USBHS_HSTDMASTATUSx.DESC_LDST rising does not trigger any interrupt. 1: An interrupt is generated when a descriptor has been loaded from the bus.
• BURST_LCK: Burst Lock Enable 0: The DMA never locks the bus access. 1: USB packets AHB data bursts are locked for maximum optimization of the bus bandwidth usage and maximization of fly- by AHB burst duration.
• BUFF_LENGTH: Buffer Byte Length (Write-only) This field determines the number of bytes to be transferred until end of buffer. The maximum channel transfer size (32 KBytes) is reached when this field is 0 (default value). If the transfer size is unknown, this field should be set to 0, but the transfer end may occur earlier under USB device control. When this field is written, the USBHS_HSTDMASTATUSx.BUFF_COUNT field is updated with the write value. Notes: 1. Bits [31:2] are only writable when issui ng a channel Control Command other than “Stop Now”. 2. For reliability, it is highly recommended to wait for both the USBHS_HSTDMASTATUSx.CHAN_ACT and the CHAN_ENB flags to be at 0, thus ensuring the channel has been stopped before issuing a command other than “Stop Now”.

703SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

37.6.68 Host DMA Channel x Status Register

Name: USBHS_HSTDMASTATUSx [x=1..7] Address: 0x4003871C [1], 0x4003872C [2], 0x4003873C [3], 0x4003874C [4], 0x4003875C [5], 0x4003876C [6], 0x4003877C [7] Access: Read/Write

• CHANN_ENB: Channel Enable Status 0: If cleared, the DMA channel no longer transfers data, and may load the next descriptor if the USBHS_HSTDMACONTROLx.LDNXT_DSC bit is set. When any transfer is ended either due to an elapsed byte count or to completion of a USBHS device-initiated transfer, this bit is automatically reset. 1: If set, the DMA channel is currently enabled and transfers data upon request. This bit is normally set or cleared by writing into the USBHS_HSTDMACONTROLx.CHANN_ENB bit field either by soft- ware or descriptor loading. If a channel request is currently serviced when the USBHS_HSTDMACONTROLx.CHANN_ENB bit is cleared, the DMA FIFO buffer is drained until it is empty, then this status bit is cleared.
• CHANN_ACT: Channel Active Status 0: The DMA channel is no longer trying to source the packet data. When a packet transfer is ended, this bit is automatically reset. 1: The DMA channel is currently trying to source packet data, i.e., selected as the highest-priority requesting channel. When a packet transfer cannot be completed due to an END_BF_ST, this flag stays set during the next channel descriptor load (if any) and potentially until completion of a USBHS packet transfer, if allowed by the new descriptor.
• END_TR_ST: End of Channel Transfer Status 0: Cleared automatically when read by software. 1: Set by hardware when the last packet transfer is complete, if the USBHS device has ended the transfer. Valid until the CHANN_ENB flag is cleared at the end of the next buffer transfer.
• END_BF_ST: End of Channel Buffer Status 0: Cleared automatically when read by software. 1: Set by hardware when the BUFF_COUNT count-down reaches zero. Valid until the CHANN_ENB flag is cleared at the end of the next buffer transfer. 31 30 29 28 27 26 25 24 BUFF_COUNT 23 22 21 20 19 18 17 16 BUFF_COUNT 15 14 13 12 11 10 9 8 76543210 – DESC_LDST END_BF_ST END_TR_ST – – CHANN_ACT CHANN_ENB

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 704

• DESC_LDST: Descriptor Loaded Status 0: Cleared automatically when read by software. 1: Set by hardware when a descriptor has been loaded from the system bus. Valid until the CHANN_ENB flag is cleared at the end of the next buffer transfer.
• BUFF_COUNT: Buffer Byte Count This field determines the current number of bytes still to be transferred for this buffer. This field is decremented from the AHB source bus access byte width at the end of this bus address phase. The access byte width is 4 by default, or less, at DMA start or end, if the start or end address is not aligned on a word boundary. At the end of buffer, the DMA accesses the USBHS device only for the number of bytes needed to complete it. Note: For IN pipes, if the receive buffer byte length (USBHS _HSTDMACONTROL.BUFF_LENGTH) has been defaulted to zero because the USB transfer length is unknown, the actual buffer byte length received is 0x10000-BUFF_COUNT.

705SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 38. Ethernet MAC (GMAC)

38.1 Description

The Ethernet MAC (GMAC) module implements a 10/100 Mbps Ethernet MAC comp atible with the IEEE 802.3 standard. The GMAC can operate in either half or full duplex mode at all supported speeds. The GMAC Network Configuration Register is used to select the speed, duplex mode and interface type (MII, RMII).

38.2 Embedded Characteristics

 Compatible with IEEE Standard 802.3  10, 100 Mbps Operation  Full and Half Duplex Operation at all Supported Speeds of Operation  Statistics Counter Registers for RMON/MIB  MII/RMII Interface to the Physical Layer  Integrated Physical Coding  Direct Memory Access (DMA) Interface to External Memory  Support for 3 Priority Queues in DMA  8 Kbytes Transmit RAM (2 KB for Queue 0, 2 KB for Queue 1, 4 KB for Queue 2) and 4 Kbytes Receive RAM  Programmable Burst Length and Endianism for DMA  Interrupt Generation to Signal Receive and Transmit Completion, Errors or Other Events  Automatic Pad and Cyclic Redundancy Check (CRC) Generation on Transmitted Frames  Automatic Discard of Frames Received with Errors  Receive and Transmit IP , TCP and UDP Checksum Offload. Both IPv4 and IPv6 Packet Types Supported  Address Checking Logic for Four Specific 48-bit Addresses, Four Type IDs, Promiscuous Mode, Hash Matching of Unicast and Multicast Destination Addresses and Wake-on-LAN  Management Data Input/Output (MDIO) Interface for Physical Layer Management  Support for Jumbo Frames up to 10240 Bytes  Full Duplex Flow Control with Recognition of Incoming Pause Frames and Hardware Generation of Transmitted Pause Frames  Half Duplex Flow Control by Forcing Collisions on Incoming Frames  Support for 802.1Q VLAN Tagging with Recognition of Incoming VLAN and Priority Tagged Frames  Support for 802.1Qbb Priority-based Flow Control  Programmable Inter Packet Gap (IPG) Stretch  Recognition of IEEE 1588 PTP Frames  IEEE 1588 Time Stamp Unit (TSU)  Support for 802.1AS Timing and Synchronization  Supports 802.1Qav Traffic Shaping on Two Highest Priority Queues

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 706

38.3 Block Diagram

Figure 38-1. Block Diagram

38.4 Signal Interface

The GMAC includes the following signal interfaces:  MII, RMII to an external PHY  MDIO interface for external PHY management  Slave APB interface for accessing GMAC registers  Master AHB interface for memory access  GTSUCOMP signal for TSU timer count value comparison Register Interface Status & Statistic Registers Control Registers FIFO Interface AHB DMA Interface MAC Transmitter MAC Receiver Frame Filtering MDIO Media Interface APB AHB Packet Buffer Memories Table 38-1. GMAC Connecti ons in Different Modes Signal Name Function MII RMII GTXCK Transmit Clock or Reference Clock TXCK REFCK GTXEN Transmit Enable TXEN TXEN GTX[3..0] Transmit Data TXD[3:0] TXD[1:0] GTXER Transmit Coding Error TXER Not Used GRXCK Receive Clock RXCK Not Used GRXDV Receive Data Valid RXDV CRSDV GRX[3..0] Receive Data RXD[3:0] RXD[1:0] GRXER Receive Error RXER RXER GCRS Carrier Sense and Data Valid CRS Not Used

707SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

38.5 Product Dependencies

38.5.1 I/O Lines

The pins used for interfacing the GMAC may be multiplexed with PIO lines. The programmer must first program the PIO Controller to assign th e pins to their peripheral function. If I/O lines of the GMAC are not used by the application, they can be used for other purposes by the PIO Controller.

38.5.2 Power Management

The GMAC is not continuously clocked. The user must first enable the GMAC clock in the Power Management Controller before using it. GCOL Collision Detect COL Not Used GMDC Management Data Clock MDC MDC GMDIO Management Data Input/Output MDIO MDIO Table 38-1. GMAC Connections in Different Modes (Continued) Signal Name Function MII RMII Table 38-2. I/O Lines Instance Signal I/O Line Peripheral GMAC GCOL PD13 A GMAC GCRS PD10 A GMAC GMDC PD8 A GMAC GMDIO PD9 A GMAC GRXCK PD14 A GMAC GRXDV PD4 A GMAC GRXER PD7 A GMAC GRX0 PD5 A GMAC GRX1 PD6 A GMAC GRX2 PD11 A GMAC GRX3 PD12 A GMAC GTSUCOMP PB1 B GMAC GTSUCOMP PB12 B GMAC GTSUCOMP PD11 C GMAC GTSUCOMP PD20 C GMAC GTXCK PD0 A GMAC GTXEN PD1 A GMAC GTXER PD17 A GMAC GTX0 PD2 A GMAC GTX1 PD3 A GMAC GTX2 PD15 A GMAC GTX3 PD16 A

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 708

38.5.3 Interrupt Sources

The GMAC interrupt line is connected to one of the inte rnal sources of the interrupt controller. Using the GMAC interrupt requires prior programming of the interrupt controller. The GMAC features three interrupt sources. Interrupt source 39 is the interrupt number for the GMAC priority queue 0 and all general interrupts. The interrupt sources 66 and 67 are the interrupt numbers for GMAC priority queue Q1 and Q2, respectively.

38.6 Functional Description

38.6.1 Media Access Controller

The Media Access Controller (MAC) transmit block takes data from FIFO, adds preamble and, if necessary, pad and frame check sequence (FCS). Both half duplex and full duplex Ethernet modes of operation are supported. When operating in half duplex mode, the MAC transmit block generates data according to the carrier sense multiple access with collision detect (CSMA/CD) protocol. The start of trans mission is deferred if carrier sense (CRS) is active. If collisi on (COL) becomes active during transmission, a jam s equence is asserted and the transmission is retried after a random back off. The CRS and COL signals have no effect in full duplex mode. The MAC receive block checks for valid preamble, FCS, alignment and lengt h, and presents received frames to the MAC address checking block and FIFO. Software can co nfigure the GMAC to receive jumbo frames up to 10240 bytes. It can optionally strip CRC from the received frame prior to transfer to FIFO. The address checker recognizes four specific 48-bit addr esses, can recognize four different type ID values, and contains a 64-bit Hash register for matching multicast and unicast addresses as requi red. It can recognize the broadcast address of all ones and copy all frames. The MAC can also reject all frames that are not VLAN tagged and recognize Wake on LAN events. The MAC receive block supports offloading of IP, TC P and UDP checksum calculations (both IPv4 and IPv6 packet types supported), and can automatically discard bad checksum frames. 38.6.2 1588 Time Stamp Unit The 1588 time stamp unit (TSU) is implemented as a 94-bit timer. The 48 upper bits [93:46] of the timer count seconds and are accessible in the “GMAC 1588 Timer Seconds High Register” (GMAC_TSH) and “GMAC 1588 Timer Seconds Low Register” (GMAC_TSL). The 30 lower bits [45:16] of the timer count nanoseconds and are accessible in the “GMAC 1588 Timer Nanoseconds Register” (GMAC_TN). The lowest 16 bits [15:0] of the timer count sub-nanoseconds. The 46 lower bits roll over when they have counted to one second. The timer increments by a programmable period (to approximately 15.2 femtoseconds resolution) with each MCK period and can also be adjusted in 1ns resolution (incremented or decremented) through APB register accesses.

38.6.3 AHB Direct Memory Access Interface

The GMAC DMA controller is connected to the MAC FIFO interface and provides a scatter-gather type capability for packet data storage. The DMA implements packet buffering where dual-port memories are used to buffer multiple frames. Table 38-3. Peripheral IDs Instance ID GMAC 39

709SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16

38.6.3.1 Packet Buffer DMA

 Easier to guarantee maximum line rate due to the ability to store multiple frames in the packet buffer, where the number of frames is limited by the amount of packet buffer memory and Ethernet frame size  Full store and forward, or partial store and forward programmable options (partial store will cater for shorter latency requirements)  Support for Transmit TCP/IP checksum offload  Support for priority queueing  When a collision on the line occurs during transmission, the packet will be automatically replayed directly from the packet buffer memory rather than having to re-fetch through the AHB (full store and forward ONLY)  Received errored packets are automatically dropped before any of the packet is presented to the AHB (full store and forward ONLY), thus reducing AHB activity  Supports manual RX packet flush capabilities  Optional RX packet flush when there is lack of AHB resource

38.6.3.2 Partial Store and Forward Using Packet Buffer DMA

The DMA uses SRAM-based packet buffers, and can be programmed into a low latency mode, known as Partial Store and Forward. This allows for a reduced latency as the full packet is not buffered before forwarding. Note that this option is only available when the device is configur ed for full duplex operation. This feature is enabled via the programmable TX and RX Partial Store and Forward registers (GMAC_TPSF and GMAC_RPSF). When the transmit Partial Store a nd Forward mode is activated, the transmitter will only begin to forward the packet to the MAC when there is enough packet data stored in the packet buffer. Likewise, when the receive Partial Store and Forward mode is activated, the receiver will only begin to forward the packet to the AHB when enough packet data is stored in the packet buffer. The amount of packe t data required to activate the forwarding process is programmable via watermark registers which are located at the same address as the partial store and forward enable bits. Note that the minimum operational value for the TX partial store and forward watermark is 20. There is no operational limit for the RX partial store and forward wa termark. Enabling partial store and forward is a useful means to reduce latency, but there are performance implications. The GMAC DMA uses separate transmit and receive lists of buffer descriptors, with each descriptor describing a buffer area in memory. This allows Ethernet packets to be broken up and scattered around the AHB memory space.

38.6.3.3 Receive AHB Buffers

Received frames, optionally including FCS, are written to receive AHB buffers stored in memory. The receive buffer depth is programmable in the range of 64 bytes to 16 Kbytes through the DMA Configuration register (GMAC_DCFGR), with the default being 128 bytes. The start location for each receive AHB buffer is stored in memory in a list of receive buffer descriptors at an address location pointed to by the receive buffer queue pointer. The base address for the receive buffer queue pointer is configured in software using the Receive Buffer Queue Base Address register (GMAC_RBQB). Each list entry consists of two words. The first is the address of the receive AHB buffer and the second the receive status. If the length of a receive frame exceeds the AHB buffer length, the status word for the used buffer is written with zeroes except for the “start of frame” bit, which is always set for the first buffer in a frame. Bit zero of the address field is written to 1 to show the buffer has bee n used. The receive buffer manager then reads the location of the next receive AHB buffer and fills that with the next part of the received frame data. AHB buffers are filled until the frame is complete and the final buffer descriptor status word contains the complete frame status. Refer to Table 38-4 for details of the receive buffer descriptor list. Each receive AHB buffer start location is a word address. The start of the first AHB buffer in a frame can be offset by up to three bytes, depending on the value written to bits 14 and 15 of the Network Configuration register (GMAC_NCFGR). If the start location of the AHB buffer is offset, the available lengt h of the first AHB buffer is reduced by the corresponding number of bytes.

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 710 Table 38-4. Receive Buffer Descriptor Entry Bit Function Word 0 31:2 Address of beginning of buffer 1 Wrap—marks last descriptor in receive buffer descriptor list. Ownership—needs to be zero for the GMAC to write data to the receive buffer. The GMAC sets this to one once it has successfully written a frame to memory. Software has to clear this bit before the buffer can be used again. Word 1

31 Global all ones broadcast address detected

30 Multicast hash match

29 Unicast hash match

28 – 27 Specific Address Register match found, bit 25 and bit 26 indicate which Specific Address Register causes the match. 26:25 Specific Address Register match. Encoded as follows: 00: Specific Address Register 1 match 01: Specific Address Register 2 match 10: Specific Address Register 3 match 11: Specific Address Register 4 match If more than one specific address is matched only one is indicated with priority 4 down to 1. This bit has a different meaning depending on whether RX checksum offloading is enabled. With RX checksum offloading disabled: (bit 24 clear in Network Configuration Register) Type ID register match found, bit 22 and bit 23 indicate which type ID register causes the match. With RX checksum offloading enabled: (bit 24 set in Network Configuration Register) 0: The frame was not SNAP encoded and/or had a VLAN tag with the Canonical Format Indicator (CFI) bit set. 1: The frame was SNAP encoded and had either no VLAN tag or a VLAN tag with the CFI bit not set. 23:22 This bit has a different meaning depending on whether RX checksum offloading is enabled. With RX checksum offloading disabled: (bit 24 clear in Network Configuration) Type ID register match. Encoded as follows: 00: Type ID register 1 match 01: Type ID register 2 match 10: Type ID register 3 match 11: Type ID register 4 match If more than one Type ID is matched only one is indicated with priority 4 down to 1. With RX checksum offloading enabled: (bit 24 set in Network Configuration Register) 00: Neither the IP header checksum nor the TCP/UDP checksum was checked. 01: The IP header checksum was checked and was correct. Neither the TCP nor UDP checksum was checked. 10: Both the IP header and TCP checksum were checked and were correct. 11: Both the IP header and UDP checksum were checked and were correct. 21 VLAN tag detected—type ID of 0x8100. For packets incorporating the stacked VLAN processing feature, this bit will be set if the second VLAN tag has a type ID of 0x8100

711SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 To receive frames, the AHB buffer descriptors must be init ialized by writing an appropriate address to bits 31:2 in the first word of each list entry. Bit 0 mu st be written with zero. Bit 1 is the wrap bit and indicates the last entry in the buffer descriptor list. The start location of the receive buffer descriptor list must be written with the receive buffer queue base address before reception is enabled (receive enable in the Networ k Control (GMAC_NCR) register). Once reception is enabled, any writes to the Re ceive Buffer Queue Base Addr ess register are ignored. Wh en read, it will return the current pointer position in the descriptor list, though this is only valid and stable when receive is disabled. If the filter block indicates that a frame should be copied to memory, the receive data DMA operation starts writing data into the receive buffer. If an error occurs, the buffer is recovered. An internal counter within the GMAC represents the receive buffer queue pointer and it is not visible through the CPU interface. The receive buffer queue pointer increment s by two words after each buffer has been used. It re- initializes to the receive buffer queue base address if any descriptor has its wrap bit set. As receive AHB buffers are used, the receive AHB buffer manager sets bit zero of the first word of the descriptor to logic one indicating the AHB buffer has been used. Software should search through the “used” bits in the AHB buffer descriptors to find out how many frames have been received, checking the start of frame and end of frame bits. When the DMA is configured in the packet buffer Partial Store And Forward mode, received frames are written out to the AHB buffers as soon as enough frame data exists in the packet buffer. For both cases, this may mean 20 Priority tag detected—type ID of 0x8100 and null VLAN identifier. For packets incorporating the stacked VLAN processing feature, this bit will be set if the second VLAN tag has a type ID of 0x8100 and a null VLAN identifier. 19:17 VLAN priority—only valid if bit 21 is set. 16 Canonical format indicator (CFI) bit (only valid if bit 21 is set). 15 End of frame—when set the buffer contains the end of a frame. If end of frame is not set, then the only valid status bit is start of frame (bit 14). 14 Start of frame—when set the buffer contains the start of a frame. If both bits 15 and 14 are set, the buffer contains a whole frame. This bit has a different meaning depending on whether jumbo frames and ignore FCS modes are enabled. If neither mode is enabled this bit will be zero. With jumbo frame mode enabled: (bit 3 set in Network Configuration Register) Additional bit for length of frame (bit[13]), that is concatenated with bits[12:0] With ignore FCS mode enabled and jumbo frames disabled: (bit 26 set in Network Configuration Register and bit 3 clear in Network Configuration Register) This indicates per frame FCS status as follows: 0: Frame had good FCS 1: Frame had bad FCS, but was copied to memory as ignore FCS enabled. 12:0 These bits represent the length of the received frame which may or may not include FCS depending on whether FCS discard mode is enabled. With FCS discard mode disabled: (bit 17 clear in Network Configuration Register) Least significant 12 bits for length of frame including FCS. If jumbo frames are enabled, these 12 bits are concatenated with bit[13] of the descriptor above. With FCS discard mode enabled: (bit 17 set in Network Configuration Register) Least significant 12 bits for length of frame excluding FCS. If jumbo frames are enabled, these 12 bits are concatenated with bit[13] of the descriptor above. Table 38-4. Receive Buffer Descriptor Entry (Continued) Bit Function

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 712 several full AHB buffers are used before some error conditi ons can be detected. If a receive error is detected the receive buffer currently being written will be recovered. Previo us buffers will not be re covered. As an example, when receiving frames with cyclic redundancy check (CRC) erro rs or excessive length, it is possible that a frame fragment might be stored in a sequence of AHB receive buffe rs. Software can detect this by looking for start of frame bit set in a buffer following a buffer with no end of frame bit set. To function properly, a 10/100 Ethernet system should have no excessive length frames or frames greater than 128 bytes with CRC errors. Collision fragments will be less than 128 bytes long, therefore it will be a rare occurrence to find a frame fragment in a receive AHB buffer, when using the default value of 128 bytes for the receive buffers size. When in packet buffer full store and forward mode, only good received frames are written out of the DMA, so no fragments will exist in the AHB buffers due to MAC receiver errors. There is still the possibility of fragments due to DMA errors, for example used bit read on the second buffer of a multi-buffer frame. If bit zero of the receive buffer descri ptor is already set when the receive buffer manager reads the location of the receive AHB buffer, then the buffer has been already used and cannot be used again until software has processed the frame and cleared bit zero. In this case, the “buffer not available” bit in the receive status register is set and an interrupt triggered. The receive resource error statistics register is also incremented. When the DMA is configured in the packet buffer full store and forward mode, the user can optionally select whether received frames should be automatically discarded when no AHB buffer res ource is available. This feature is selected via bit 24 of the DMA Configurat ion register (by default, the received frames are not automatically discarded). If this feature is off, then re ceived packets will remain to be stored in the SRAM-based packet buffer until AHB buffer resource next becomes available. This may lead to an eventual packet buffer overflow if packets continue to be rece ived when bit zero (used bit) of the receive buffer descriptor remains set. Note that after a used bit has been read, the receive bu ffer manager will re-read the location of the receive buffer descriptor every time a new packet is received. When the DMA is not configured in the packet buffer full store and forward mode and a used bit is read, the frame currently being received will be automatically discarded. When the DMA is configured in the pack et buffer full store and forward mode, a receive overrun condition occurs when the receive SRAM-based packet buffer is full, or because HRESP was not OK. In all other modes, a receive overrun condition occurs when either the AHB bus was not granted quickly enough, or because HRESP was not OK, or because a new frame has been detected by the receive block, but the status update or write back for the previous frame has not yet finished. For a receive overrun condition, the receive overrun interrupt is asserted and the buffer currently being written is recovered. The next frame that is received whose address is recognized reuses the buffer. In any packet buffer mode, a write to bit 18 of GMAC_N CR will force a packet from the external SRAM-based receive packet buffer to be flushed. This feature is only acted upon when the RX DMA is not currently writing packet data out to AHB, i.e., it is in an IDLE state. If the RX DMA is active, a write to this bit is ignored.

38.6.3.4 Transmit AHB Buffers

Frames to transmit are stored in one or more transmit AHB buffers. Transmit frames can be between 1 and 16384 bytes long, so it is possible to transmit frames longer than the maximu m length specified in the IEEE 802.3 standard. It should be noted that zero length AHB buffers are allowed and that the maximum number of buffers permitted for each transmit frame is 128. The start location for each transmit AHB buffer is stored in memory in a list of transmit buffer descriptors at a location pointed to by the transmit buffer queue pointer. The base address for this queue pointer is set in software using the Transmit Buffer Queue Base Address register. Each list entry consists of two words. The first is the byte address of the transmit buffer and th e second containing the transmit control and status. For the packet buffer DMA, the start location for each AHB buffer is a byte addre ss, the bottom bits of the address being used to offset the start of the data from the data-word boundary (i.e., bits 2,1 and 0 are used to offset the address for 64-bit datapaths).

713SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 Frames can be transmitted with or without automatic CRC generation. If CRC is automatically generated, pad will also be automatically generated to take frames to a mini mum length of 64 bytes. When CRC is not automatically generated (as defined in word 1 of the transmit buffer descriptor), the frame is assumed to be at least 64 bytes long and pad is not generated. An entry in the transmit buffer descriptor list is described in Table 38-5. To transmit frames, the buffer descriptors must be initialized by writing an appropriate byte address to bits [31:0] in the first word of each descriptor list entry. The second word of the transmit buffer descriptor is initialized with control in formation that indicates the length of the frame, whether or not the MAC is to append CRC and whether the buffer is the last buffer in the frame. After transmission the status bits are wr itten back to the second word of the first buffer along with the used bit. Bit 31 is the used bit which must be zero when the control word is read if transmission is to take place. It is written to one once the frame has been transmitted. Bits[29:20] indica te various transmit error conditions. Bit 30 is the wrap bit which can be set for any buffer within a frame. If no wrap bit is encountered the queue pointer continues to increment. The Transmit Buffer Queue Base Address register can only be updated while transmission is disabled or halted; otherwise any attempted write will be ignored. When transmission is halted the transmit buffer queue pointer will maintain its value. Therefore when transmission is rest arted the next descriptor read from the queue will be from immediately after the last successfully transmitted frame. while transmit is disabled (bit 3 of the Network Control register set low), the transmit buffer queue pointer resets to point to the address indicated by the Transmit Buffer Queue Base Address register. Note that disabling receive does not have the same effect on the receive buffer queue pointer. Once the transmit queue is initialized, transmit is activated by writing to the transmit star t bit (bit 9) of the Network Control register. Transmit is halted when a buffer descriptor with its used bit set is read, a transmit error occurs, or by writing to the transmit halt bit of the Network Contro l register. Transmission is suspended if a pause frame is received while the pause enable bit is set in the Netw ork Configuration register. Re writing the start bit while transmission is active is allowed. This is implemented with TXGO variable which is readable in the Transmit Status register at bit location 3. The TXGO variable is reset when:  Transmit is disabled.  A buffer descriptor with its ownership bit set is read.  Bit 10, THALT, of the Network Control register is written.  There is a transmit error such as too many retries or a transmit underrun. To set TXGO, write TSTART to the bit 9 of the Network Control register. Transmit halt does not take effect until any ongoing transmit finishes. If the DMA is configured for packet buffer Partial Store and Fo rward mode and a collision occurs during transmission of a multi-buffer frame, transmission will automatically restart from the first buffer of the frame. For packet buffer mode, the entire contents of the frame are read into th e transmit packet buffer memory, so the retry attempt will be replayed directly from the packet buffer memory rather than having to re-fetch through the AHB. If a used bit is read midway through tr ansmission of a multi-buffer frame, this is treated as a transmit error. Transmission stops, GTXER is asserted and the FCS will be bad. If transmission stops due to a transmit error or a used bit being read, transmission restarts from the first buffer descriptor of the frame being transmitted when the transmit start bit is rewritten.

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 714

38.6.3.5 DMA Bursting on the AHB

The DMA will always use SINGLE, or INCR type AHB accesses for buffer management operations. When performing data transfers, the AHB burst length used can be programmed using bits 4:0 of the DMA Configuration register so that either SINGLE, INCR or fixed length increm enting bursts (INCR4, INCR8 or INCR16) are used where possible. When there is enough space and enough data to be transferred, the programmed fixed length bursts will be used. If there is not enough data or space available, for example when at the beginning or the end of a buffer, SINGLE Table 38-5. Transmit Buffer Descriptor Entry Bit Function Word 0 31:0 Byte address of buffer Word 1 31 Used—must be zero for the GMAC to read data to the transmit buffer. The GMAC sets this to one for the first buffer of a frame once it has been successfully transmitted. Software must clear this bit before the buffer can be used again. 30 Wrap—marks last descriptor in transmit buffer descriptor list. This can be set for any buffer within the frame.

29 Retry limit exceeded, transmit error detected

28 Reserved. Transmit frame corruption due to AHB error—set if an error o ccurs while midway through reading transmit frame from the AHB, including HRESP errors and buffers exhausted mid frame (if the buffers run out during transmission of a frame then transmission stops, FCS shall be bad and GTXER asserted). Also set if single frame is too large for configured packet buffer memory size. 26 Late collision, transmit error detected. 25:23 Reserved 22:20 Transmit IP/TCP/UDP checksum generation offload errors: 000: No Error. 001: The Packet was identified as a VLAN type, but the header was not fully complete, or had an error in it. 010: The Packet was identified as a SNAP type, but the header was not fully complete, or had an error in it. 011: The Packet was not of an IP type, or the IP packet was invalidly short, or the IP was not of type IPv4/IPv6. 100: The Packet was not identified as VLAN, SNAP or IP. 101: Non supported packet fragmentation occurred. For IPv4 packets, the IP checksum was generated and inserted. 110: Packet type detected was not TCP or UDP. TCP/UDP checksum was therefore not generated. For IPv4 packets, the IP checksum was generated and inserted. 111: A premature end of packet was detected and the TCP/UDP checksum could not be generated. 19:17 Reserved No CRC to be appended by MAC. When set, this implies that the data in the buffers already contains a valid CRC, hence no CRC or padding is to be appended to the current frame by the MAC. This control bit must be set for the first buffer in a frame and will be ignored for the subsequent buffers of a frame. Note that this bit must be clear when using the transmit IP/TCP/UDP checksum generation offload, otherwise checksum generation and substitution will not occur. 15 Last buffer, when set this bit will indicate the last buffer in the current frame has been reached.

14 Reserved

13:0 Length of buffer

715SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 type accesses are used. Also SINGLE type accesses are used at 1024 byte boundaries, so that the 1 Kbyte boundaries are not burst over as per AHB requirements. The DMA will not terminate a fixed length burst early, unless an error condition occurs on the AHB or if receive or transmit are disabled in the Network Control register.

38.6.3.6 DMA Packet Buffer

The DMA uses packet buffers for both transmit and rece ive paths. This mode allows multiple packets to be buffered in both transmit and receive directions. This allows the DMA to withstand fa r greater access latencies on the AHB and make more efficient use of the AHB bandwidth. There are two modes of operation—Full Store and Forward and Partial Store and Forward. As described above ( Section 38.6.3.2 ”Partial Store and Forward Using Packet Buffer DMA” ), the DMA can be programmed into a low latency mode, known as Partial Stor e and Forward. For further details of this mode, see Section 38.6.3.2. When the DMA is in full store and forward mode, full packets are buffered which provides the possibility to:  Discard packets with error on the receive path before they are partially written out of the DMA, thus saving AHB bus bandwidth and driver processing overhead,  Retry collided transmit frames from the buffer, thus saving AHB bus bandwidth,  Implement transmit IP/TCP/UDP checksum generation offload. With the packet buffers included, the structure of the GMAC data paths is shown in Figure 38-2.

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 716 Figure 38-2. Data Paths with Packet Buffers Included

38.6.3.7 Transmit Packet Buffer

The transmitter packet buffer will continue attempting to fetch frame data from the AHB system memory until the packet buffer itself is full, at which point it will attempt to maintain its full level. To accommodate the status and statistics associated with each frame, three words per packet (or two if the GMAC is configured in 64-bit datapath mode) are reserved at the end of the packet data. If the packet is bad and requires to be dropped, the status and statisti cs are the only information held on that packet. Storing the status in the DPRAM is required in order to decouple the DMA interface of the buffer from the MAC interface, to update the MAC status/statistics and to generate interrupts in the order in which the packets that they represent were fetched from the AHB memory. If any errors occur on the AHB while reading the transmit frame, the fetching of packet data from AHB memory is halted. The MAC transmitter will continue to fetch packe t data, thereby emptying the packet buffer and allowing any good non-errored frames to be transmitted succes sfully. Once these have been fully transmitted, the status/statistics for the er rored frame will be updated and software wi ll be informed via an interrupt that an AHB error occurred. This way, the error is reported in the correct packet order. MAC Transmitter TX Packet Buffer RX Packet Buffer MAC Receive RX DMA TX DMA RX Packet Buffer DPSRAM TX Packet Buffer DPSRAM Frame Filtering AHBAHB DMA Status and Statistic Registers Register Interface Control Interface Ethernet MAC RX GMII TX GMII MDIO APB

717SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 The transmit packet buffer will only attempt to read more frame da ta from the AHB when s pace is available in the packet buffer memory. If space is not available it must wait until the a packet fetched by the MAC completes transmission and is subsequently removed from the packet buffer memory. Note that if full store and forward mode is active and if a single frame is fetched that is too large for the packet buffer memory, the frame is flushed and the DMA halted with an error status. This is because a complete frame must be written into the packet buffer before transmission can begin, and therefore the minimum packet buffer memory size should be chosen to satisfy the maximum frame to be transmitted in the application. In full store and forward mode, once the complete transmit frame is written into the packet buffer memory, a trigger is sent across to the MAC transmitter, which will then begin reading the frame from the packet buffer memory. Since the whole frame is present and stable in the packet buffer memory an underflow of the transmitter is not possible. The frame is kept in the packet buffer until not ification is received from the MAC that the frame data has either been successfully transmitted or can no longer be retransmitted (too many retries in half duplex mode). When this notification is received the frame is flushed from memory to make room for a new frame to be fetched from AHB system memory. In Partial Store and Forward mode, a trigger is sent ac ross to the MAC transmitter as soon as sufficient packet data is available, whic h will then begin fetching the frame from the pack et buffer memory. If, af ter this point, the MAC transmitter is able to fetch data from the packet buffer faster than the AHB DMA can fill it, an underflow of the transmitter is possible. In this ca se, the transmission is terminated early, and the packet buffer is completely flushed. Transmission can only be restarted by writing to the transmit START bit. In half duplex mode, the frame is kept in the packet buffer until notification is received from the MAC that the frame data has either been successfully transmitted or can no longer be retransmitted (too many retries in half duplex mode). When this notification is received the frame is flushed from memory to make room for a new frame to be fetched from AHB system memory. In full duplex mode, the frame is removed from the packet buffer on the fly. Other than underflow , the only MAC related errors that ca n occur are due to collisions during half duplex transmissions. When a collision occurs the frame still exists in the packet buffer memory so can be retried directly from there. Only once the MAC transmitter has failed to tr ansmit after sixteen attempts is the frame finally flushed from the packet buffer.

38.6.3.8 Receive Packet Buffer

The receive packet buffer stores frames from the MAC re ceiver along with their status and statistics. Frames with errors are flushed from the packet buffer memory, while good frames are pushed onto the DMA AHB interface. The receiver packet buffer monitors the FIFO write interface from the MAC receiver and translates the FIFO pushes into packet buffer writes. At the end of the received frame the status and statistics are buffered so that the information can be used when the frame is read out. When programmed in full store and forward mode, if the frame has an error the frame data is immediately flushed from the packet buffer memory allowing subsequent frames to utilise the freed up space. The status and statistics for bad frames ar e still used to update the GMAC registers. To accommodate the status and statistics associated with each frame, three words per packet (or two if configured in 64-bit datapath mode) are reserved at the end of the packet data. If the packet is bad and requires to be dropped, the status and statistics are the only information held on that packet. The receiver packet buffer will also detect a full condition so that an overfl ow condition can be detected. If this occurs, subsequent packets are dropped and an RX overflow interrupt is raised. For full store and forward, the DMA only begins packet fetches once the stat us and statistics for a frame are available. If the frame has a bad status due to a frame error, the status and statistics are passed on to the GMAC registers. If the frame has a good status, the information is used to read the frame from the packet buffer memory and burst onto the AHB using the DMA buffer management protocol. Once the last frame data has been transferred to the packet buffer, the status and statistics are updated to the GMAC registers.

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 718 If Partial Store and Forward mode is active, the DMA will begin fetching the packet data before the status is available. As soon as the status becomes available, the DMA will fetch this information as soon as possible before continuing to fetch the remainder of the frame. Once the last frame data has been transferred to the packet buffer, the status and statistics are updated to the GMAC registers.

38.6.3.9 Priority Queueing in the DMA

The DMA by default uses a single transmit and receive queue. This means the list of transmit/receive buffer descriptors point to data buffers associated with a single transmit/receive data stream. The GMAC can select up to 3 priority queues. Each queue has an independent list of buffer descriptors pointing to separate data streams. In the transmit direction, higher priority queues are always serviced before lower priority queues, with Q0 as lowest priority and Q2 as highest priority. This strict priority scheme requires the user to ensure that high priority traffic is constrained so that lower priority traffic will have required bandwidth. The GMAC DMA will determine the next queue to service by initiating a sequence of buffer descript or reads interrogating the ownership bits of each. The buffer descriptor corresponding to the highest priority queue is read first. As an example, if the ownership bit of this descriptor is set, then the DMA will progress to reading the 2nd highest priority queue’s descriptor. If that ownership bit read of this lower priority queue is set, then the DMA will read the 3rd highest priority queue’s descriptor. If all the descriptors return an ownership bit set, then a resource error has occurred, an interrupt is generated and transmission is automatically halted. Transmission can only be re started by setting the START bit in the Network Control register. The GMAC DMA will need to identify the highest available queue to transmit from when the START bit in the Network Control register is written to and the TX is in a halted state, or when the last word of any packet has been fetched from external AHB memory. The GMAC transmit DMA maximizes the effectiveness of priority queuing by ensuring that high priority traffic be transmitted as early as possible after being fetched from AHB. High priority traffic fetched from AHB will be pushed to the MAC layer, depending on traffic shaping being enabl ed and the associated credit value for that queue, before any lower priority traffic that may pre-exist in the transmit SRAM-based packet buffer. This is achieved by separating the transmit SRAM-based packet buffer into regions, one region per queue. The size of each region determines the amount of SRAM space allocated per queue. For each queue, there is an associated Transmit Buffer Queue Base Ad dress register. For the lowest priority queue (or the only queue when only one queue is selected), the Transmit Buffer Queue Base Address is located at address 0x1C. For all other queues, the Transmit Buffer Queue Base Address registers are located at sequential addresses starting at address 0x440. In the receive direction each packet is written to AHB data buffers in the order that it is received. For each queue, there is an independent set of receive AHB buffers for each queue. There is therefore a separate Receive Buffer Queue Base Address register for each queue. For t he lowest priority queue (or the only queue when only one queue is selected), the Receive Buffer Queue Base Addres s is located at address 0x18. For all other queues, the Receive Buffer Queue Base Address registers are located at sequential addresses starting at address 0x480. Every received packet will pass through a programmable screening algorithm which will allocate a particular queue to that frame. The user interface to the screeners is through two types of programmable registers:  Screening Type 1 registers—The module features 4 Scre ening Type 1 registers. Screening Type 1 registers hold values to match against specific IP and UDP fields of the received frames. The fields matched against are DS (Differentiated Services field of IPv4 frames), TC (Traffic class field of IPv6 frames) and/or the UDP destination port.  Screening Type 2 registers—The module features 8 Screening Type 2 registers GMAC_ST2RPQ. Screening Type 2 registers operate independently of Screening Type 1 registers and offer additional match capabilities. Screening Type 2 allows a screen to be configured that is the combination of all or any of the following comparisons:

719SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 1. An ena ble bit VLAN priority, VLANE. A VLAN priority match will be performed if the VLAN priority enable is set. The extracted priority field in the VLAN header is compared against VLANP in the GMAC_ST2RPQ register itself. 2. An enable bit EtherType, ETHE. The EtherType fiel d I2ETH inside GMAC_ST2RPQ maps to one of 4 EtherType match registers, GMAC_ST2ER. The extracted EtherType is compared against GMAC_ST2ER designated by this EtherType field. 3. An enable bit Compare A, COMPAE. This bit is associated with a Screening Type 2 Compare Word 0/1 register x, GMAC_ST2CW0/1. 4. An enable bit Compare B, COMPBE. This bit is a ssociated with a Screening Type 2 Compare Word 0/1 register x, GMAC_ST2CW0/1. 5. An enable bit Compare C, COMPCE. This bit is associated with a Screening Type 2 Compare Word 0/1 register x, GMAC_ST2CW0/1. Each screener type has an enable bit, a match pattern and a queue number. If a received frame matches on an enabled screening register, then the frame will be t agged with the queue value in the associated screening register, and forwarded onto the DMA and subsequently into the external memory associated with that queue. If two screeners are matched then the one which resides at the lowest register address will take priority so care must be taken on the selection of the screener location. When the priority queuing feature is en abled, the number of interrupt outputs from the GMAC core is increased to match the number of supported queues. The number of Interrupt Status registers is increased by the same number. Only DMA related events are reported using the individual interrupt outputs, as the GMAC can relate these events to specific queues. All other events generated within the GMAC are reported in the interrupt associated with the lowest priority queue. For the lowest priority queue (or the only queue when only 1 queue is selected), the Interrupt Status register is located at address 0x24. For all other queues, the Interrupt Status register is located at sequential addresses starting at address 0x400. Note: The address matching is the first level of filtering. If th ere is a match, the screeners are the next level of filtering for routing the data to the appropriate queue. See Section 38.6.7 ”MAC Filtering Block” for more details. The additional screening done by the functions Compare A, B, and C each have an enable bit and compare register field. COMPA, COMPB and COMPC in GMAC_ST2RPQ are pointers to a configured offset (OFFSVAL), value (COMPVAL), and mask (MASKVAL). If enabled, the compar e is true if the data at the offset into the frame, ANDed with MASKVAL, is equal to the value of COMPVA L ANDed with MASKVAL. A 16-bit word comparison is done. The byte at the offset number of bytes from the index start is comp ared to bits 7:0 of the configured COMPVAL and MASKVAL. The byte at the offset number of bytes + 1 from the index start is compared to bits 15:8 of the configured COMPVAL and MASKVAL. The offset value in bytes, OFFSVAL, ranges from 0 to 127 bytes from either the start of the frame, the byte after the EtherType field, the byte after the IP header (IPv4 or IPv6) or the byte after the TCP/UDP header. Note the logic to decode the IP header or the TCP/UDP header is reused from the TCP/UDP/IP checksum offload logic and therefore has the same restrictions on use (the main limitat ion is that IP fragmentatio n is not supported). Refer to the Checksum Offload for IP, TCP and UDP section of this documentation for further details. Compare A, B, and C use a common set of 24 GMAC_ST2CW0/1 registers, thus all COMPA, COMPB and COMPC fields in the registers GMAC_ST2RPQ point to a single pool of 24 GMAC_ST2CW0/1 registers. Note that Compare A, B and C together allow matching ag ainst an arbitrary 48 bits of data and so can be used to match against a MAC address. All enabled comparisons are ANDed together to form the overall type 2 screening match.

38.6.4 MAC Transmit Block

The MAC transmitter can operate in either half duplex or full duplex mode and transmits frames in accordance with the Ethernet IEEE 802.3 sta ndard. In half duplex mode, the CSMA/CD protocol of the IEEE 802.3 specification is followed.

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 720 A small input buffer receives data through the FIFO interface which will extract data in 32 -bit form. All subsequent processing prior to the final output is performed in bytes. Transmit data can be output using the MII interface. Frame assembly starts by adding preamble and the start frame delimiter. Data is taken from the transmit FIFO interface a word at a time. If necessary, padding is added to take the frame length to 60 bytes. CRC is calculated using an order 32-bit polynomial. This is inverted and appended to the end of th e frame taking the frame length to a minimum of 64 bytes. If the no CRC bit is set in the second word of the last buffer descriptor of a transmit frame, neither pad nor CRC are appended. The no CRC bit can also be set through the FIFO interface. In full duplex mode (at all data rates), frames are transmitted immediately. Back to back frames are transmitted at least 96 bit times apart to guarantee the interframe gap. In half duplex mode, the transmitter ch ecks carrier sense. If asserted, t he transmitter waits for the signal to become inactive, and then starts transmission after the interframe gap of 96 bit times. If the collision signal is asserted during transmission, the transmitter will transmit a jam sequence of 32 bits taken from the data register and then retry transmission after the back off time has elapsed. If the collision occurs during either the preamble or Start Frame Delimiter (SFD), then these fields will be completed prior to generation of the jam sequence. The back off time is based on an XOR of the 10 least significant bi ts of the data coming from the transmit FIFO interface and a 10-bit pseudo random number generator. The number of bits used depends on the number of collisions seen. After the first collision 1 bit is used, then the second 2 bits and so on up to the maximum of 10 bits. All 10 bits are used above ten collis ions. An error will be i ndicated and no further at tempts will be made if 16 IEEE 802.3 standard which refers to the truncated binary exponential back off algorithm. In 10/100 mode, both collisions and late collisions are treated identically, and back off and retry will be performed up to 16 times. This condition is repo rted in the transmit buffer descriptor word 1 (late collision, bit 26) and also in the Transmit Status register (late collision, bit 7). An interrupt can also be generated (if enabled) when this exception occurs, and bit 5 in the Interrupt Status register will be set. In all modes of operation, if the transmit DMA underr uns, a bad CRC is automatically appended using the same mechanism as jam insertion and the GTXER signal is asserted. For a properly configured system this should never happen and also it is impossible if configured to use the DMA with packet buffers, as the complete frame is buffered in local packet buffer memory. By setting when bit 28 is set in the Network Configurat ion register, the Inter Packet Gap (IPG) may be stretched beyond 96 bits depending on the length of the previously transmitted frame and the value written to the IPG Stretch register (GMAC_IPGS). The least significant 8 bits of the IPG Stretch register multiply the previous frame length (including preamble). The next significant 8 bits (+1 so as not to get a divide by zero) divide the frame length to generate the IPG. IPG stretch only works in full duplex mode and when bit 28 is set in the Network Configuration register. The IPG Stretch register cannot be used to shrink the IPG below 96 bits. If the back pressure bit is set in the Network Control regi ster, or if the HDFC configuration bit is set in the GMAC_UR register (10M or 100M half duplex mode), the transmit block transmits 64 bits of data, which can consist of 16 nibbles of 1011 or in bit rate mode 64 1s, whenever it sees an incoming frame to force a collision. This provides a way of implementing flow control in half duplex mode.

38.6.5 MAC Receive Block

All processing within the MAC receive block is implemen ted using a 16-bit data path. The MAC receive block checks for valid preamble, FCS, alignment and length, pr esents received frames to the FIFO interface and stores the frame destination address for use by the address checking block. If, during the frame reception, the frame is found to be too long, a bad frame indication is sent to the FIFO interface. The receiver logic ceases to send data to memory as soon as this condition occurs.

721SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 At end of frame reception the receive block indicates to the DMA block whether the frame is good or bad. The DMA block will recover the current receive buffer if the frame was bad. Ethernet frames are normally stored in DMA memory comple te with the FCS. Setting the FCS remove bit in the network configuration (bit 17) causes frames to be stored without their corresponding FCS. The reported frame length field is reduced by four bytes to reflect this operation. The receive block signals to the register block to incr ement the alignment, CRC (FCS), short frame, long frame, jabber or receive symbol errors when any of these exception conditions occur. If bit 26 is set in the network co nfiguration, CRC errors will be ignor ed and CRC errored frames will not be discarded, though the Frame Check Sequence Errors statistic register will still be in cremented. Additionally, if not enabled for jumbo frames mode, then bit[13] of the receiver descriptor word 1 will be updated to indicate the FCS validity for the particular frame. This is useful for applications such as EtherCAT whereby individual frames with FCS errors must be identified. Received frames can be checked for length field error by setting the length field error frame discard bit of the Network Configuration register (bit-16). When this bit is set, the receiver compares a frame's measured length with the length field (bytes 13 and 14) extracted from the frame. The fram e is discarded if the measured length is shorter. This checking procedure is for received frames between 64 bytes and 1518 bytes in length. Each discarded frame is counted in the 10-bit length field error statistics register. Frames where the length field is greater than or equal to 0x0600 hex will not be checked.

38.6.6 Checksum Offload for IP, TCP and UDP

The GMAC can be programmed to perform IP, TCP and UDP checksum offloading in both receive and transmit directions, which is enabled by setting bit 24 in the Network Configuration register for receive and bit 11 in the DMA Configuration register for transmit. IPv4 packets contain a 16-bit checksum field, which is the 16-bit 1’s complement of the 1’s complement sum of all 16-bit words in the header. TCP and UDP packets contain a 16-bit checksum field, which is the 16-bit 1’s complement of the 1’s complement sum of all 16-bit words in the header, the data and a conceptual IP pseudo header. To calculate these checksums in software requires each byte of the packet to be processed. For TCP and UDP this can use a large amount of processing power. Offloading the checksum calculation to hardware can result in significant performance improvements. For IP, TCP or UDP checksum offload to be useful, the operating system c ontaining the protocol stack must be aware that this offload is available so that it can make use of the fact that the hardware can either generate or verify the checksum.

38.6.6.1 Receiver Checksum Offload

When receive checksum offloading is enabled in the GMAC , the IPv4 header checksum is checked as per RFC 791, where the packet meets the following criteria:  If present, the VLAN header must be four octets long and the CFI bit must not be set.  Encapsulation must be RFC 894 Ethernet Type Encoding or RFC 1042 SNAP Encoding.  IPv4 packet  IP header is of a valid length The GMAC also checks the TCP checksum as per RFC 793, or the UDP checksum as per RFC 768, if the following criteria are met:  IPv4 or IPv6 packet  Good IP header checksum (if IPv4)  No IP fragmentation  TCP or UDP packet

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 722 When an IP, TCP or UDP frame is received, the receive buffer descriptor gives an indication if the GMAC was able to verify the checksums. There is also an indication if the frame had SNAP encapsulation. These indication bits will replace the type ID match indication bits when the receive checksum offload is enabled. For details of these indication bits refer to Table 38-4 “Receive Buffer Descriptor Entry”. If any of the checksums are verified as incorrect by the GMAC, the packet is discarded and the appropriate statistics counter incremented.

38.6.6.2 Transmitter Checksum Offload

The transmitter checksum offloa d is only available if the full store and forward mode is enabled. This is because the complete frame to be transmitted must be read into the packet buffer memory before the checksum can be calculated and written back into the headers at the beginning of the frame. Transmitter checksum offload is enabled by setting bit [11] in the DMA Configuration register. When enabled, it will monitor the frame as it is written into the transmitter packet buffer memory to automatically detect the protocol of the frame. Protocol support is identical to the receiver checksum offload. For transmit checksum generation and substitution to occur, the protocol of the frame must be recognized and the frame must be provided without the FCS field, by making sure that bit [16] of the transmit descriptor word 1 is clear. If the frame data already had the FCS field, this would be corrupted by the substitution of the new checksum fields. If these conditions are met, the transmit checksum offload engine will calculate the IP, TCP and UDP checksums as appropriate. Once the full packet is completely wr itten into packet buffer memory, the checksums will be valid and the relevant DPRAM locations will be updated for the new chec ksum fields as per standard IP/TCP and UDP packet structures. If the transmitter checksum engine is prevented from g enerating the relevant checksums, bits [22:20] of the transmitter DMA writeback status will be updated to identify the reason for the error. Note that the frame will still be transmitted but without the checksum substitution, as typica lly the reason that the su bstitution did not occur was that the protocol was not recognized.

38.6.7 MAC Filtering Block

The filter block determines which frames should be written to the FIFO interface and on to the DMA. Whether a frame is passed depends on what is enabled in the Network Confi guration register, the state of the external matching pins, the contents of the specific address, type and Hash registers and the frame's destination address and type field. If bit 25 of the Network Configuration register is not se t, a frame will not be copied to memory if the GMAC is transmitting in half duplex mode at the time a destination address is received. Ethernet frames are transmitted a byte at a time, least significant bit first. The first six bytes (48 bits) of an Ethernet frame make up the destination address. The first bit of the destination address, which is the LSB of the first byte of the frame, is the group or individual bit. This is o ne for multicast addresses and zero for unicast. The all ones address is the broadcast address and a special case of multicast. The GMAC supports recognition of four specific addresse s. Each specific address requires two registers, Specific Address register Bottom and Specific Address register Top. Specific Address register Bottom stores the first four bytes of the destination address and Specific Address re gister Top contains the last two bytes. The addresses stored can be specific, group, local or universal. The destination address of received frames is compared against the data stored in the Specific Address registers once they have been activated. The addresses are deacti vated at reset or when their corresponding Specific Address register Bottom is written. They are activated w hen Specific Address register Top is written. If a receive frame address matches an active address, the frame is written to the FIFO interface and on to DMA memory.

723SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 Frames may be filtered using the type ID field for matching. Four type ID registers exist in the register address space and each can be enabled for matching by writing a one to the MSB (bit 31) of the respective register. When a frame is received, the matching is implemented as an OR function of the various types of match. The contents of each type ID register (when enabled) are compared against the length/type ID of the frame being received (e.g., bytes 13 and 14 in non-VLAN and non-SNAP encapsulated frames) and copied to memory if a match is found. The encoded type ID match bits (Word 0, Bit 22 and Bit 23) in the receive buffer descriptor status are set indicating which type ID register generated the match, if the receive checksum offload is disabled. The reset state of the type ID registers is zero, hence each is initially disabled. The following example illustrates the use of the address and type ID match registers for a MAC address of 21:43:65:87:A9:CB: Note: 1. Contains the address of the transmitting device The sequence above shows t he beginning of an Ethernet fr ame. Byte order of transmiss ion is from top to bottom as shown. For a successful match to specific address 1, the following address matching registers must be set up: Specific Address 1 Bottom register (GMAC_SAB1) (Address 0x088) 0x87654321 Specific Address 1 Top register (GMAC_SAT1) (Address 0x08C) 0x0000CBA9 For a successful match to the type ID, the following Type ID Match 1 register must be set up: Type ID Match 1 register (GMAC_TIDM1) (Address 0x0A8) 0x80004321

38.6.8 Broadcast Address

Frames with the broadcast address of 0xFFFFFFFFFFFF are stored to memory only if the 'no broadcast' bit in the Network Configuration register is set to zero.

38.6.9 Hash Addressing

The hash address register is 64 bits long and takes up two locations in the memory map. The least significant bits are stored in Hash Register Bottom and the most significant bits in Hash Register Top. Preamble 55 SFD D5 DA (Octet 0 - LSB) 21 DA (Octet 1) 43 DA (Octet 2) 65 DA (Octet 3) 87 DA (Octet 4) A9 DA (Octet 5 - MSB) CB SA (LSB) 00(1) SA 00(1) SA 00(1) SA 00(1) SA 00(1) SA (MSB) 00(1) Type ID (MSB) 43 Type ID (LSB) 21

SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 724 The unicast hash enable and the multicas t hash enable bits in the Network Configuration register enable the reception of hash matched frames. The destination address is reduced to a 6-bit index into the 64-bit Hash register using the following hash function: The hash function is an XOR of every sixth bit of the destination address. hash_index[05] = da[05] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47] hash_index[04] = da[04] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46] hash_index[03] = da[03] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45] hash_index[02] = da[02] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44] hash_index[01] = da[01] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43] hash_index[00] = da[00] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42] da[0] represents the least significant bit of the first byte received, that is, the multicast/unicast indicator, and da[47] represents the most significant bit of the last byte received. If the hash index points to a bit that is set in the Hash register then the frame will be matched according to whether the frame is multicast or unicast. A multicast match will be signalled if the multicast hash enable bit is set, da[0] is logic 1 and the hash index points to a bit set in the Hash register. A unicast match will be signalled if the unicast hash enable bit is set, da[0] is logic 0 and the hash index points to a bit set in the Hash register. To receive all multicast frames, the Hash register should be set with all ones and the multicast hash enable bit should be set in the Network Configuration register.

38.6.10 Copy all Frames (Promiscuous Mode)

If the Copy All Frames bit is set in the Network Configuration register then all frames (except those that are too long, too short, have FCS errors or have GRXER asserted during reception) will be copied to memory. Frames with FCS errors will be copied if bit 26 is set in the Network Configuration register.

38.6.11 Disable Copy of Pause Frames

Pause frames can be prevented from being written to memory by setting the disable copying of pause frames control bit 23 in the Network Configuration register. When set, pause frames are not copied to memory regardless of the Copy All Frames bit, whether a hash match is found, a type ID match is identified or if a destination address match is found.

38.6.12 VLAN Support

The following table describes an Ethernet encoded 802.1Q VLAN tag. The VLAN tag is inserted at the 13th byte of the frame adding an extra four bytes to the frame. To support these extra four bytes, the GMAC can accept frame lengths up to 1536 bytes by setting bit 8 in the Network Configuration register. Table 38-6. 802.1Q VLAN Tag TPID (Tag Protocol Identifier) 16 bits TCI (Tag Control Information) 16 bits 0x8100 First 3 bits priority, then CFI bit, last 12 bits VID

725SAM E70 [DATASHEET] Atmel-11296D-ATARM-SAM E70-Datasheet_19-Jan-16 If the VID (VLAN identifier) is null (0x000) this indicates a priority-tagged frame. The following bits in the receive buffer descriptor status word give information about VLAN tagged frames:-  Bit 21 set if receive frame is VLAN tagged (i.e., type ID of 0x8100).  Bit 20 set if receive frame is priority tagged (i.e., type ID of 0x8100 and null VID). (If bit 20 is set, bit 21 will be set also.)  Bit 19, 18 and 17 set to priority if bit 21 is set.  Bit 16 set to CFI if bit 21 is set. The GMAC can be configured to reject all frames except VLAN tagged frames by setting the discard non-VLAN frames bit in the Network Configuration register.

38.6.13 Wake on LAN Support

The receive block supports Wake on LAN by detecting the following events on incoming receive frames:  Magic packet  Address Resolution Protocol (ARP) request to the device IP address  Specific address 1 filter match  Multicast hash filter match These events can be individually enabled through bits [19:16] of the Wake on LAN register. Also, for Wake on LAN detection to occur, receive enable must be set in the Network Control register, however a receive buffer does not have to be available. In case of an ARP requ est, specific address 1 or multicast filter events will occur even if the frame is errored. For magic packet events, the frame must be correctly formed and error free. A magic packet event is detected if all of the following are true:  Magic packet events are enabled through bit 16 of the Wake on LAN register  The frame's destination address matches specific address 1  The frame is correctly formed with no errors  The frame contains at least 6 bytes of 0xFF for synchronization  There are 16 repetitions of the contents of Specific Address 1 register immediately following the synchronization An ARP request event is detected if all of the following are true:  ARP request events are enabled through bit 17 of the Wake on LAN register  Broadcasts are allowed by bit 5 in the Network Configuration register  The frame has a broadcast destination address (bytes 1 to 6)  The frame has a type ID field of 0x0806 (bytes 13 and 14)  The frame has an ARP operation field of 0x0001 (bytes 21 and 22)  The least significant 16 bits of the frame's ARP target protocol address (bytes 41 and 42) match the value programmed in bits[15:0] of the Wake on LAN register The decoding of the ARP fields adjusts automatically if a VLAN tag is det ected within the frame. The reserved value of 0x0000 for the Wake on LA N target address value will not cause an ARP request event, even if matched by the frame. A specific address 1 filter match event will occur if all of the following are true:  Specific address 1 events are enabled through bit 18 of the Wake on LAN register  The frame's destination address matches the value programmed in the Specific Address 1 registers A multicast filter match event will occur if all of the following are true:  Multicast hash events are enabled through bit 19 of the Wake on LAN register

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