SAM9N12 ATMEL | Alldatasheet

Document overview

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Technical content

Features

  • Core – ARM926EJ-S™ ARM ® Thumb® Processor running up to 400 MHz @ 1.0V +/- 10% – 16 Kbytes Data Cache, 16 Kbytes Instruction Cache, Memory Management Unit
  • Memories – One 128-Kbyte internal ROM embedding secure bootstrap routine – One 32-Kbyte internal SRAM, single-cycle access at system speed – 32-bit External Bus Interface supporting 8-bank DDR2/LPDDR, SDR/LPSDR, Static Memories – MLC/SLC NAND Controller, with up to 24-bit Programmable Multi-bit Error Correcting Code (PMECC) – System running up to 133 MHz – Power-on Reset, Reset Controller, Shut Down Controller, Periodic Interval Timer, Watchdog Timer and Real Time Clock – Boot Mode Select Option, Remap Command – Internal Low Power 32 kHz RC and Fast 12 MHz RC Oscillators – Selectable 32768 Hz Low-power Oscillator, 16 MHz Oscillator, one PLL for the system and one PLL optimized for USB –S i x 32-bit-layer AHB Bus Matrix – Dual Peripheral Bridge with dedicated programmable clock – One dual port 8-channel DMA Controller – Advanced Interrupt Controller and Debug Unit – Two Programmable External Clock Signals
  • Low Power Mode – Shut Down Controller with four 32-bit battery backup registers – Clock Generator and Power Management Controller – Very Slow Clock Operating Mode, Software Pr ogrammable Power Optimization Capabilities
  • Peripherals – LCD Controller – USB Device Full Speed with dedicated On-Chip Transceiver – USB Host Full Speed with dedicated On-C hip Transceiver – One High speed SD card and SDIO Host Controller – Two Master/Slave Serial Peripheral Interfaces – Two Three-channel 32-bit Timer/Counters – One Synchronous Serial Controller – One Four-channel 16-bit PWM Controller – Two Two-wire Interfaces – Four USARTs plus two UARTs – One 12-channel 10-bit Analog-to-Digital Converter with up to 5-wire resistive Touch screen support – Write Protected Registers
  • Cryptography – TRNG True Random Number Generator compliant with NIST Special Publication 800-22 – AES 256-, 192-, 128-bit Key Algorithm compliant with FIPS Publication 197 – SHA (SHA1 and SHA256) Complian t with FIPS Publication 180-2 – 256 Fuse bits for crypto key and 64 Fuse bits for device configuration, including JTAG disable and forced boot from the on-chip ROM
  • I/O – Four 32-bit Parallel Input/Output Controllers – 105 Programmable I/O Lines Multiplexed with up to Three Peripheral I/Os – Input Change Interrupt Capability on Each I/O Line, optional Schmitt Trigger input – Individually Programmable Open-drain, Pull-up and Pull-down Resistor, Synchronous Output – Packages: 217-ball BGA, pitch 0.8 mm, and 247-ball BGA, pitch 0.5 mm AT91SAM ARM-based Embedded MPU SAM9N12 SAM9CN11 SAM9CN12 11063G–ATARM–09-Oct-12

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 1. Description The ARM926EJ-S based SAM9CN12 features the frequently requested combination of user interface functionality and high data rate connectivity, including LCD Controller, resistive touch-screen, multiple UARTs, SPI, I2C, full speed USB Host and Device and SDIO. The SAM9CN12 supports the latest generation of LPDDR/DDR2 and NAND Flash memory interfaces for program and data storage. An internal 133 MHz multi-layer bus architecture associated with 8 DMA channels, a distributed memory including a 32-Kbyte SRAM, sustains the high bandwidth required by the processor and the high speed peripherals. Embedded on SAM9CN12, on-chip hardware accelerators with DMA support, enable high- speed data encryption and authentication of the transferred data or application. Supported standards are up to 256-bit AES, and FIPS Publication 180-2 compliant SHA1 and SHA256. A True Random Number Generator is embedded for key generation and exchange protocols. There are fuse bits for crypto key (SAM9CN12), user configuration (SAM9N12 and SAM9CN11) and device configuration (All). SAM9CN12 includes a Secured Boot ROM. SAM9N12 and SAM9CN11 include a Standard Boot ROM. The I/Os support 1.8V or 3.3V operation, which are independently configurable for the mem- ory interface and peripheral I/Os. This feature completely eliminates the need for any external level shifters. In addition it supports 0.8 ball pitch package for low cost PCB manufacturing. The SAM9CN12 power management controller features efficient clock gating and a battery backup section minimizing power consumption in active and standby modes. There are several devices. The following table shows the embedded features. Table 1-1. Devices Device SAM9N12 SAM9CN11 SAM9CN12 Standard Boot with BSC X X - Secured Boot - - X TRNG X X X AES - X X SHA - X X

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 2. Block Diagram Figure 2-1. SAM9N12/CN11/CN12 Block Diagram AIC APB PLLA System Controller PMC PIT WDT OSC 32K SHDC RSTC POR DBGU GPBR USART0 USART1 USART2 USART3 SPI0 OSC16M PIOB POR PIOC RTC RC PIOD SSC PIO PIO ARM926EJ-S JTAG / Boundary Scan In-Circuit Emulator MMU Bus Interface ID ICache

16 Kbytes

FIFOMCI0_CK MCI0_DA0-MCI0_DA3 MCI0_CDA LCD DMA 12-CH 10-bit ADC TouchScreen PIO PWM Peripheral Bridge Peripheral Bridge TK TF TD RD RF RK 8-CH DMA PWM0-PWM3 EBI Static Memory Controller D0-D15 A0/NBS0 NCS0 NCS1/SDCS NRD NWR0/NWE NWR1/NBS1 SDCK, #SDCK, SDCKE RAS, CAS SDWE, SDA10 A1/NBS2/NWR2/DQM2 NANDOE, NANDWE NWAIT NCS2, NCS3, NCS4, NCS5 NANDCS DQM[0..1] DQS[0..1] NANDALE, NANDCLE PIO D16-D31 NWR3/NBS3/DQM3 A20-A25 TWI0 TWI1 TWCK0-TWCK1 TWD0-TWD1 Multi-Layer AHB Matrix DDR2/LPDDR SDR/LPSDR Controller SRAM

32 Kbytes

A2-A15, A19 A16/BA0 A18/BA2 A17/BA1 NAND Flash Controller PMECC PMERRLOC TCLK0-TCLK5 TIOA0-TIOA5 TIOB0-TIOB5 LCDDAT0-LCDDAT23 LCDVSYNC,LCDHSYNC LCDPCK LDDEN,LCDPWM LCDDISP AES *TRNG SHA * USB FS OHCI DMA HDP HDM USB FS DeviceDDM DDP Transceiver DPRAM Transceiver Fuse Box PLLB ROM

128 Kbytes

  • except SAM9N12

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 3. Signal Description Table 3-1 gives details on the signal names classified by peripheral. Table 3-1. Signal Description List Signal Name Function Type Active Level Clocks, Oscillators and PLLs XIN Main Oscillator Input Input XOUT Main Oscillator Output Output XIN32 Slow Clock Oscillator Input Input XOUT32 Slow Clock Oscillator Output Output VBG Bias Voltage Reference for USB Analog PCK0 - PCK1 Programmable Clock Output Output Shutdown, Wakeup Logic SHDN Shut-Down Control Output WKUP Wake-Up Input Input ICE and JTAG TCK Test Clock Input TDI Test Data In Input TDO Test Data Out Output TMS Test Mode Select Input JTAGSEL JTAG Selection Input RTCK Return Test Clock Output Reset/Test NRST Microcontroller Reset I/O Low NTRST Test Reset Signal Input BMS Boot Mode Select Input Debug Unit - DBGU DRXD Debug Receive Data Input DTXD Debug Transmit Data Output Advanced Interrupt Controller - AIC IRQ External Interrupt Input Input FIQ Fast Interrupt Input Input PIO Controller - PIOA - PIOB - PIOC - PIOD PA0 - PA31 Parallel IO Controller A I/O PB0 - PB18 Parallel IO Controller B I/O PC0 - PC31 Parallel IO Controller C I/O PD0 - PD21 Parallel IO Controller D I/O

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 External Bus Interface - EBI D0 -D15 Data Bus I/O D16 -D31 Data Bus I/O A0 - A25 Address Bus Output NWAIT External Wait Signal Input Low Static Memory Controller - SMC NCS0 - NCS5 Chip Select Lines Output Low NWR0 - NWR3 Write Signal Output Low NRD Read Signal Output Low NWE Write Enable Output Low NBS0 - NBS3 Byte Mask Signal Output Low NAND Flash Support NFD0-NFD15 NAND Flash I/O I/O NANDCS NAND Flash Chip Select Output Low NANDOE NAND Flash Output Enable Output Low NANDWE NAND Flash Write Enable Output Low DDR2/SDRAM/LPDDR Controller SDCK,#SDCK DDR2/SDRAM differential clock Output SDCKE DDR2/SDRAM Clock Enable Output High SDCS DDR2/SDRAM Controller Chip Select Output Low BA[0..2] Bank Select Output Low SDWE DDR2/SDRAM Write Enable Output Low RAS - CAS Row and Column Signal Output Low SDA10 SDRAM Address 10 Line Output DQS[0..1] Data Strobe I/O DQM[0..3] Write Data Mask Output High Speed Multimedia Card Interface - HSMCI MCI_CK Multimedia Card Clock I/O MCI_CDA Multimedia Ca rd Slot Command I/O MCI_DA0 - MCI_DA7 Multimedia Card Slot Data I/O Universal Synchronous Asynchronous Receiver Transmitter- USARTx SCKx USARTx Serial Clock I/O TXDx USARTx Transmit Data Output RXDx USARTx Receive Data Input RTSx USARTx Request To Send Output CTSx USARTx Clear To Send Input Table 3-1. Signal Description List (Continued) Signal Name Function Type Active Level

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Universal Asynchronous Receiver Transmitter - UARTx UTXDx UARTx Transmit Data Output URXDx UARTx Receive Data Input Synchronous Serial Controller - SSC TD SSC Transmit Data Output RD SSC Receive Data Input TK SSC Transmit Clock I/O RK SSC Receive Clock I/O TF SSC Transmit Frame Sync I/O RF SSC Receive Frame Sync I/O Timer Counter - TCx x=0..5 TCLKx TC Channel x External Clock Input Input TIOAx TC Channel x I/O Line A I/O TIOBx TC Channel x I/O Line B I/O Serial Peripheral Interface - SPIx SPIx_MISO Master In Slave Out I/O SPIx_MOSI Master Out Slave In I/O SPIx_SPCK SPI Serial Clock I/O SPIx_NPCS0 SPI Peripheral Chip Select 0 I/O Low SPIx_NPCS1- SPIx_NPCS3 SPI Peripheral Chip Select Output Low Two-wire Interface -TWIx TWDx Two-wire Serial Data I/O TWCKx Two-wire Serial Clock I/O Pulse Width Modulation Controller- PWM PWM0 - PWM3 Pulse Width Modulation Output Output USB Device Full Speed Port - UDP DDP USB Device Data + Analog DDM USB Device Data - Analog USB Host Full Speed Port - UHP HDP USB Host Data + Analog HDM USB Host Data - Analog LCD Controller - LCDC LCDDAT 0-23 LCD Data Bus Output LCDVSYNC LCD Vertical Synchronization Output LCDHSYNC LCD Horizontal Synchronization Output LCDPCK LCD Pixel Clock Output Table 3-1. Signal Description List (Continued) Signal Name Function Type Active Level

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 When “Reset State” is stated, the configuration is defined by the “Reset State” column of the Pin Description table. LCDDEN LCD Data Enable Output LCDPWM LCD Contrast Control Output LCDDISP LCD Display Enable Output Analog-to-Digital Converter - ADC AD0XP_UL Top/Upper Left Channel Analog AD1XM_UR Bottom/Upper Right Channel Analog AD2YP_LL Right/Lower Left Channel Analog AD3YM_SENSE Left/Sense Channel Analog AD4LR Lower Right Channel Analog AD5-AD11 7 Analog Inputs Analog ADTRG ADC Trigger Input ADVREF ADC Reference Analog Table 3-1. Signal Description List (Continued) Signal Name Function Type Active Level Table 3-2. SAM9N12/CN11/CN12 I/O Type Description I/O Type Signal Name Voltage Range Analog Pull-up Pull-up Value (Ohm) Pull-down Pull-down Value (Ohm) Schmitt Trigger GPIO all PIO lines except following 1.65-3.6V switchable 50-100K switchable 50-100K switchable GPIO_CLK MCICK, SPI0SPCK, SPI1SPCK 1.65-3.6V switchable 50-100K switchable 50-100K switchable GPIO_CLK2 LCDDOTCK 1.65-3.6V switchable 50-100K switchable 50-100K switchable GPIO_ANA ADx, GPADx 3.0-3.6V I switchable 50-100K switchable EBI all Data lines (Input/output) except the following 1.65-1.95V, 3.0-3.6V switchable 50-100K switchable 50-100K EBI_O all Address and control lines (output only) except the following 1.65-1.95V, 3.0-3.6V Reset State 50-100K Reset State 50-100K EBI_CLK SDCK, #SDCK 1.65-1.95V, 3.0-3.6V RSTJTAG NRST, NTRST, BMS, TCK, TDI, TMS, TDO, RTCK 3.0-3.6V Reset State 100K Reset State 100K Reset State SYSC WKUP , SHDN, JTAGSEL, SHDN 1.65-3.6V Reset State 100k Reset State 15K Reset State VBG VBG 0.9-1.1V I USBFS HDP , HDM, DDP , DDM 3.0-3.6V I/O CLOCK XIN, XOUT, XIN32, XOUT32 1.65-3.6V I/O

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 4. Package and Pinout The SAM9CN12 is available in 217-ball and 247-ball BGA packages.

4.1 Mechanical Overview of the 217-ball BGA Package

Figure 4-1 shows the orientation of the 217-ball BGA Package Figure 4-1. Orientation of the 217-ball BGA Package

4.2 Mechanical Overview of the 247-ball BGA Package

Figure 4-2 shows the orientation of the 247-ball BGA Package Figure 4-2. Orientation of the 247-ball BGA Package TOP VIEW BALL A1 ABCDEFGHJ KLM NPRTU BOTTOM VIEW BALL A1

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 4.3 217-ball BGA Package Pinout Table 4-1. BGA217 Pin Description Ball Power Rail I/O Type Primary Alternate PIO Peripheral A PIO Peripheral B PIO Peripheral C Reset State Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir Signal, Dir, PU, PD, ST T3 VDDIOP0 GPIO PA0 I/O TXD0 O SPI1_NPCS1 O PIO, I, PU, ST U2 VDDIOP0 GPIO PA1 I/O RXD0 I SPI0_NPCS2 O PIO, I, PU, ST U3 VDDIOP0 GPIO PA2 I/O RTS0 O PIO, I, PU, ST P4 VDDIOP0 GPIO PA3 I/O CTS0 I PIO, I, PU, ST T4 VDDIOP0 GPIO PA4 I/O SCK0 I/O PIO, I, PU, ST U4 VDDIOP0 GPIO PA5 I/O TXD1 O PIO, I, PU, ST P5 VDDIOP0 GPIO PA6 I/O RXD1 I PIO, I, PU, ST R4 VDDIOP0 GPIO PA7 I/O TXD2 O SPI0_NPCS1 O PIO, I, PU, ST U6 VDDIOP0 GPIO PA8 I/O RXD2 I SPI1_NPCS0 I/O PIO, I, PU, ST R5 VDDIOP0 GPIO PA9 I/O DRXD I PIO, I, PU, ST R6 VDDIOP0 GPIO PA10 I/O DTXD O PIO, I, PU, ST T5 VDDIOP0 GPIO PA11 I/O SPI0_MISO I/O MCDA4 I/O PIO, I, PU, ST T6 VDDIOP0 GPIO PA12 I/O SPI0_MOSI I/O MCDA5 I/O PIO, I, PU, ST U5 VDDIOP0 GPIO_CLK PA13 I/O SPI0_SPCK I/O MCDA6 I/O PIO, I, PU, ST U7 VDDIOP0 GPIO PA14 I/O SPI0_NPCS0 I/O MCDA7 I/O PIO, I, PU, ST T7 VDDIOP0 GPIO PA15 I/O MCDA0 I/O PIO, I, PU, ST R7 VDDIOP0 GPIO PA16 I/O MCCDA I/O PIO, I, PU, ST U8 VDDIOP0 GPIO_CLK PA17 I/O MCCK I/O PIO, I, PU, ST P8 VDDIOP0 GPIO PA18 I/O MCDA1 I/O PIO, I, PU, ST T8 VDDIOP0 GPIO PA19 I/O MCDA2 I/O PIO, I, PU, ST R8 VDDIOP0 GPIO PA20 I/O MCDA3 I/O PIO, I, PU, ST U9 VDDIOP0 GPIO PA21 I/O TIOA0 I/O SPI1_MISO I/O PIO, I, PU, ST U10 VDDIOP0 GPIO PA22 I/O TIOA1 I/O SPI1_MOSI I/O PIO, I, PU, ST T9 VDDIOP0 GPIO_CLK PA23 I/O TIOA2 I/O SPI1_SPCK I/O PIO, I, PU, ST U11 VDDIOP0 GPIO PA24 I/O TCLK0 I TK I/O PIO, I, PU, ST T10 VDDIOP0 GPIO PA25 I/O TCLK1 I TF I/O PIO, I, PU, ST R9 VDDIOP0 GPIO PA26 I/O TCLK2 I TD O PIO, I, PU, ST U12 VDDIOP0 GPIO PA27 I/O TIOB0 I/O RD I PIO, I, PU, ST T11 VDDIOP0 GPIO PA28 I/O TIOB1 I/O RK I/O PIO, I, PU, ST U13 VDDIOP0 GPIO PA29 I/O TIOB2 I/O RF I/O PIO, I, PU, ST R10 VDDIOP0 GPIO PA30 I/O TWD0 I/O SPI1_NPCS3 O PIO, I, PU, ST T12 VDDIOP0 GPIO PA31 I/O TWCK0 O SPI1_NPCS2 O PIO, I, PU, ST E4 VDDANA GPIO PB0 I/O RTS2 O PIO, I, PU, ST F3 VDDANA GPIO PB1 I/O CTS2 I PIO, I, PU, ST F4 VDDANA GPIO PB2 I/O SCK2 I/O PIO, I, PU, ST F2 VDDANA GPIO PB3 I/O SPI0_NPCS3 O PIO, I, PU, ST

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 G4 VDDANA GPIO_CLK PB4 I/O PIO, I, PU, ST G3 VDDANA GPIO PB5 I/O PIO, I, PU, ST D2 VDDANA GPIO_ANA PB6 I/O AD7 I PIO, I, PU, ST E2 VDDANA GPIO_ANA PB7 I/O AD8 I PIO, I, PU, ST D1 VDDANA GPIO_ANA PB8 I/O AD9 I PIO, I, PU, ST F1 VDDANA GPIO_ANA PB9 I/O AD10 I PCK1 O PIO, I, PU, ST E1 VDDANA GPIO_ANA PB10 I/O AD11 I PCK0 O PIO, I, PU, ST A1 VDDANA GPIO_ANA PB11 I/O AD0 I PWM0 O PIO, I, PU, ST C3 VDDANA GPIO_ANA PB12 I/O AD1 I PWM1 O PIO, I, PU, ST B1 VDDANA GPIO_ANA PB13 I/O AD2 I PWM2 O PIO, I, PU, ST C2 VDDANA GPIO_ANA PB14 I/O AD3 I PWM3 O PIO, I, PU, ST D3 VDDANA GPIO_ANA PB15 I/O AD4 I PIO, I, PU, ST C1 VDDANA GPIO_ANA PB16 I/O AD5 I I PIO, I, PU, ST E3 VDDANA GPIO_ANA PB17 I/O AD6 I I PIO, I, PU, ST D4 VDDANA GPIO PB18 I/O IRQ I ADTRG I PIO, I, PU, ST G2 VDDIOP1 GPIO PC0 I/O LCDDAT0 O TWD1 I/O PIO, I, PU, ST G1 VDDIOP1 GPIO PC1 I/O LCDDAT1 O TWCK1 O PIO, I, PU, ST H4 VDDIOP1 GPIO PC2 I/O LCDDAT2 O TIOA3 I/O PIO, I, PU, ST J1 VDDIOP1 GPIO PC3 I/O LCDDAT3 O TIOB3 I/O PIO, I, PU, ST H3 VDDIOP1 GPIO PC4 I/O LCDDAT4 O TCLK3 I PIO, I, PU, ST J3 VDDIOP1 GPIO PC5 I/O LCDDAT5 O TIOA4 I/O PIO, I, PU, ST H2 VDDIOP1 GPIO PC6 I/O LCDDAT6 O TIOB4 I/O PIO, I, PU, ST H1 VDDIOP1 GPIO PC7 I/O LCDDAT7 O TCLK4 I PIO, I, PU, ST K2 VDDIOP1 GPIO PC8 I/O LCDDAT8 O UTXD0 O PIO, I, PU, ST J2 VDDIOP1 GPIO PC9 I/O LCDDAT9 O URXD0 I PIO, I, PU, ST L1 VDDIOP1 GPIO PC10 I/O LCDDAT10 O PWM0 O PIO, I, PU, ST K1 VDDIOP1 GPIO PC11 I/O LCDDAT11 O PWM1 O PIO, I, PU, ST L2 VDDIOP1 GPIO PC12 I/O LCDDAT12 O TIOA5 I/O PIO, I, PU, ST K3 VDDIOP1 GPIO PC13 I/O LCDDAT13 O TIOB5 I/O PIO, I, PU, ST M1 VDDIOP1 GPIO PC14 I/O LCDDAT14 O TCLK5 I PIO, I, PU, ST M2 VDDIOP1 GPIO_CLK PC15 I/O LCDDAT15 O PCK0 O PIO, I, PU, ST K4 VDDIOP1 GPIO PC16 I/O LCDDAT16 O UTXD1 O PIO, I, PU, ST M3 VDDIOP1 GPIO PC17 I/O LCDDAT17 O URXD1 I PIO, I, PU, ST N1 VDDIOP1 GPIO PC18 I/O LCDDAT18 O PWM0 O PIO, I, PU, ST N2 VDDIOP1 GPIO PC19 I/O LCDDAT19 O PWM1 O PIO, I, PU, ST N3 VDDIOP1 GPIO PC20 I/O LCDDAT20 O PWM2 O PIO, I, PU, ST P1 VDDIOP1 GPIO PC21 I/O LCDDAT21 O PWM3 O PIO, I, PU, ST P2 VDDIOP1 GPIO PC22 I/O LCDDAT22 O TXD3 O PIO, I, PU, ST Table 4-1. BGA217 Pin Description (Continued) Ball Power Rail I/O Type Primary Alternate PIO Peripheral A PIO Peripheral B PIO Peripheral C Reset State Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir Signal, Dir, PU, PD, ST

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 P3 VDDIOP1 GPIO PC23 I/O LCDDAT23 O RXD3 I PIO, I, PU, ST R1 VDDIOP1 GPIO PC24 I/O LCDDISP O RTS3 O PIO, I, PU, ST R3 VDDIOP1 GPIO PC25 I/O CTS3 I PIO, I, PU, ST R2 VDDIOP1 GPIO PC26 I/O LCDPWM O SCK3 I/O PIO, I, PU, ST T1 VDDIOP1 GPIO PC27 I/O LCDVSYNC O RTS1 O PIO, I, PU, ST M4 VDDIOP1 GPIO PC28 I/O LCDHSYNC O CTS1 I PIO, I, PU, ST N4 VDDIOP1 GPIO_CLK PC29 I/O LCDDEN O SCK1 I/O PIO, I, PU, ST T2 VDDIOP1 GPIO_CLK2 PC30 I/O LCDPCK O PIO, I, PU, ST U1 VDDIOP1 GPIO PC31 I/O FIQ I PCK1 O PIO, I, PU, ST P15 VDDNF EBI PD0 I/O NANDOE O PIO, I, PU N14 VDDNF EBI PD1 I/O NANDWE O PIO, I, PU M15 VDDNF EBI PD2 I/O A21/NANDALE O A21,O, PD M14 VDDNF EBI PD3 I/O A22/NANDCLE O A22,O, PD P16 VDDNF EBI PD4 I/O NCS3 O PIO, I, PU M17 VDDNF EBI PD5 I/O NWAIT I PIO, I, PU L15 VDDNF EBI PD6 I/O D16 O PIO, I, PU L16 VDDNF EBI PD7 I/O D17 O PIO, I, PU L17 VDDNF EBI PD8 I/O D18 O PIO, I, PU K17 VDDNF EBI PD9 I/O D19 O PIO, I, PU K16 VDDNF EBI PD10 I/O D20 O PIO, I, PU K15 VDDNF EBI PD11 I/O D21 O PIO, I, PU J17 VDDNF EBI PD12 I/O D22 O PIO, I, PU J16 VDDNF EBI PD13 I/O D23 O PIO, I, PU H17 VDDNF EBI PD14 I/O D24 O PIO, I, PU J15 VDDNF EBI PD15 I/O D25 O A20 O A20, O, PD G17 VDDNF EBI PD16 I/O D26 O A23 O A23, O, PD H16 VDDNF EBI PD17 I/O D27 O A24 O A24, O, PD H15 VDDNF EBI PD18 I/O D28 O A25 O A25, O, PD F17 VDDNF EBI PD19 I/O D29 O NCS2 O PIO, I, PU G16 VDDNF EBI PD20 I/O D30 O NCS4 O PIO, I, PU E17 VDDNF EBI PD21 I/O D31 O NCS5 O PIO, I, PU H10 VDDIOM POWER VDDIOM I I J14 K14 L14 VDDNF POWER VDDNF I I Table 4-1. BGA217 Pin Description (Continued) Ball Power Rail I/O Type Primary Alternate PIO Peripheral A PIO Peripheral B PIO Peripheral C Reset State Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir Signal, Dir, PU, PD, ST

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 J10 K10 GNDIOM GND GNDIOM I I P12 VDDIOP0 POWER VDDIOP0 I I VDDIOP1 POWER VDDIOP1 I I P13 GNDIOP GND GNDIOP I I D6 VDDBU POWER VDDBU I I GNDBU GND GNDBU I I C4 VDDANA POWER VDDANA I I B2 GNDANA GND GNDANA I I T16 VDDPLL POWER VDDPLL I I P14 GNDPLL GND GNDPLL I I R14 VDDOSC POWER VDDOSC I I R15 VDDUSB POWER VDDUSB I I N16 VDDFUSE POWER VDDFUSE I I M16 GNDFUSE GND GNDFUSE I T17 GNDUSB GND GNDUSB I I G15 P10 VDDCORE POWER VDDCORE I I H14 P11 GNDCORE GND GNDCORE I I B14 VDDIOM EBI D0 I/O O, PD A14 VDDIOM EBI D1 I/O O, PD C14 VDDIOM EBI D2 I/O O, PD D13 VDDIOM EBI D3 I/O O, PD C13 VDDIOM EBI D4 I/O O, PD B13 VDDIOM EBI D5 I/O O, PD A13 VDDIOM EBI D6 I/O O, PD C12 VDDIOM EBI D7 I/O O, PD D12 VDDIOM EBI D8 I/O O, PD B12 VDDIOM EBI D9 I/O O, PD C11 VDDIOM EBI D10 I/O O, PD D11 VDDIOM EBI D11 I/O O, PD Table 4-1. BGA217 Pin Description (Continued) Ball Power Rail I/O Type Primary Alternate PIO Peripheral A PIO Peripheral B PIO Peripheral C Reset State Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir Signal, Dir, PU, PD, ST

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 A12 VDDIOM EBI D12 I/O O, PD B11 VDDIOM EBI D13 I/O O, PD A11 VDDIOM EBI D14 I/O O, PD C10 VDDIOM EBI D15 I/O O, PD D17 VDDIOM EBI_O A0 O NBS0 O O, PD C17 VDDIOM EBI_O A1 O NBS2/ DQM2/ NWR2 O O, PD F16 VDDIOM EBI_O A2 O O, PD B17 VDDIOM EBI_O A3 O O, PD A17 VDDIOM EBI_O A4 O O, PD F15 VDDIOM EBI_O A5 O O, PD E16 VDDIOM EBI_O A6 O O, PD D16 VDDIOM EBI_O A7 O O, PD E15 VDDIOM EBI_O A8 O O, PD G14 VDDIOM EBI_O A9 O O, PD C16 VDDIOM EBI_O A10 O O, PD F14 VDDIOM EBI_O A11 O O, PD B16 VDDIOM EBI_O A12 O O, PD A16 VDDIOM EBI_O A13 O O, PD C15 VDDIOM EBI_O A14 O O, PD D15 VDDIOM EBI_O A15 O O, PD B15 VDDIOM EBI_O A16 O BA0 O O, PD E14 VDDIOM EBI_O A17 O BA1 O O, PD A15 VDDIOM EBI_O A18 O BA2 O O, PD D14 VDDIOM EBI_O A19 O O, PD B7 VDDIOM EBI_O NCS0 O O, PU C5 VDDIOM EBI_O NCS1 O SDCS O O, PU C7 VDDIOM EBI_O NRD O O, PU A6 VDDIOM EBI_O NWR0 O NWRE O O, PU C6 VDDIOM EBI_O NWR1 O NBS1 O O, PU D7 VDDIOM EBI_O NWR3 O NBS3/ DQM3 O O, PU A10 VDDIOM EBI_CLK SDCK O O A9 VDDIOM EBI_CLK #SDCK O O D10 VDDIOM EBI_O SDCKE O O, PU B9 VDDIOM EBI_O RAS O O, PU D9 VDDIOM EBI_O CAS O O, PU B10 VDDIOM EBI_O SDWE O O, PU B6 VDDIOM EBI_O SDA10 O O, PU C9 VDDIOM EBI_O DQM0 O O, PU Table 4-1. BGA217 Pin Description (Continued) Ball Power Rail I/O Type Primary Alternate PIO Peripheral A PIO Peripheral B PIO Peripheral C Reset State Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir Signal, Dir, PU, PD, ST

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 A8 VDDIOM EBI_O DQM1 O O, PU B8 VDDIOM EBI DQS0 I/O O, PD A7 VDDIOM EBI DQS1 I/O O, PD A2 VDDANA POWER ADVREF I I P17 VDDUSB USBFS HDP I/O O, PD N17 VDDUSB USBFS HDM I/O O, PD R17 VDDUSB USBFS DDP I/O O, PD R16 VDDUSB USBFS DDM I/O O, PD A5 VDDBU SYSC WKUP I I, ST B5 VDDBU SYSC SHDN O O, PU U15 VDDCORE RSTJTAG BMS I I, PD, ST B4 VDDBU SYSC JTAGSEL I I, PD R12 VDDIOP0 RSTJTAG TCK I I, ST R11 VDDIOP0 RSTJTAG TDI I I, ST U14 VDDIOP0 RSTJTAG TDO O O T13 VDDIOP0 RSTJTAG TMS I I, ST T14 VDDIOP0 RSTJTAG RTCK O O R13 VDDIOP0 RSTJTAG NRST I/O I, PU, ST T15 VDDIOP0 RSTJTAG NTRST I I, PU, ST A4 VDDBU CLOCK XIN32 I I A3 VDDBU CLOCK XOUT32 O O U17 VDDIOP0 CLOCK XIN I I U16 VDDIOP0 CLOCK XOUT O O N15 NC Table 4-1. BGA217 Pin Description (Continued) Ball Power Rail I/O Type Primary Alternate PIO Peripheral A PIO Peripheral B PIO Peripheral C Reset State Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir Signal, Dir, PU, PD, ST

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 4.4 247-ball BGA Package Pinout Table 4-2. BGA247 Pin Description Ball Power Rail I/O Type Primary Alternate PIO Peripheral A PIO Peripheral B PIO Peripheral C Reset State Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir Signal, Dir, PU, PD, ST P3 VDDIOP0 GPIO PA0 I/O TXD0 O SPI1_NPCS1 O PIO, I, PU, ST R2 VDDIOP0 GPIO PA1 I/O RXD0 I SPI0_NPCS2 O PIO, I, PU, ST R9 VDDIOP0 GPIO PA2 I/O RTS0 O PIO, I, PU, ST N5 VDDIOP0 GPIO PA3 I/O CTS0 I PIO, I, PU, ST P10 VDDIOP0 GPIO PA4 I/O SCK0 I/O PIO, I, PU, ST R3 VDDIOP0 GPIO PA5 I/O TXD1 O PIO, I, PU, ST R10 VDDIOP0 GPIO PA6 I/O RXD1 I PIO, I, PU, ST T2 VDDIOP0 GPIO PA7 I/O TXD2 O SPI0_NPCS1 O PIO, I, PU, ST P6 VDDIOP0 GPIO PA8 I/O RXD2 I SPI1_NPCS0 I/O PIO, I, PU, ST T3 VDDIOP0 GPIO PA9 I/O DRXD I PIO, I, PU, ST U2 VDDIOP0 GPIO PA10 I/O DTXD O PIO, I, PU, ST P5 VDDIOP0 GPIO PA11 I/O SPI0_MISO I/O MCDA4 I/O PIO, I, PU, ST V2 VDDIOP0 GPIO PA12 I/O SPI0_MOSI I/O MCDA5 I/O PIO, I, PU, ST V1 VDDIOP0 GPIO_CLK PA13 I/O SPI0_SPCK I/O MCDA6 I/O PIO, I, PU, ST W2 VDDIOP0 GPIO PA14 I/O SPI0_NPCS0 I/O MCDA7 I/O PIO, I, PU, ST W1 VDDIOP0 GPIO PA15 I/O MCDA0 I/O PIO, I, PU, ST V3 VDDIOP0 GPIO PA16 I/O MCCDA I/O PIO, I, PU, ST R5 VDDIOP0 GPIO_CLK PA17 I/O MCCK I/O PIO, I, PU, ST U3 VDDIOP0 GPIO PA18 I/O MCDA1 I/O PIO, I, PU, ST V4 VDDIOP0 GPIO PA19 I/O MCDA2 I/O PIO, I, PU, ST U4 VDDIOP0 GPIO PA20 I/O MCDA3 I/O PIO, I, PU, ST V5 VDDIOP0 GPIO PA21 I/O TIOA0 I/O SPI1_MISO I/O PIO, I, PU, ST U5 VDDIOP0 GPIO PA22 I/O TIOA1 I/O SPI1_MOSI I/O PIO, I, PU, ST R6 VDDIOP0 GPIO_CLK PA23 I/O TIOA2 I/O SPI1_SPCK I/O PIO, I, PU, ST R7 VDDIOP0 GPIO PA24 I/O TCLK0 I TK I/O PIO, I, PU, ST U6 VDDIOP0 GPIO PA25 I/O TCLK1 I TF I/O PIO, I, PU, ST V6 VDDIOP0 GPIO PA26 I/O TCLK2 I TD O PIO, I, PU, ST R8 VDDIOP0 GPIO PA27 I/O TIOB0 I/O RD I PIO, I, PU, ST U7 VDDIOP0 GPIO PA28 I/O TIOB1 I/O RK I/O PIO, I, PU, ST P11 VDDIOP0 GPIO PA29 I/O TIOB2 I/O RF I/O PIO, I, PU, ST V7 VDDIOP0 GPIO PA30 I/O TWD0 I/O SPI1_NPCS3 O PIO, I, PU, ST N12 VDDIOP0 GPIO PA31 I/O TWCK0 O SPI1_NPCS2 O PIO, I, PU, ST G6 VDDANA GPIO PB0 I/O RTS2 O PIO, I, PU, ST E3 VDDANA GPIO PB1 I/O CTS2 I PIO, I, PU, ST G5 VDDANA GPIO PB2 I/O SCK2 I/O PIO, I, PU, ST F2 VDDANA GPIO PB3 I/O SPI0_NPCS3 O PIO, I, PU, ST E2 VDDANA GPIO_CLK PB4 I/O PIO, I, PU, ST

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 E5 VDDANA GPIO PB5 I/O PIO, I, PU, ST C2 VDDANA GPIO_ANA PB6 I/O AD7 I PIO, I, PU, ST B2 VDDANA GPIO_ANA PB7 I/O AD8 I PIO, I, PU, ST A2 VDDANA GPIO_ANA PB8 I/O AD9 I PIO, I, PU, ST B1 VDDANA GPIO_ANA PB9 I/O AD10 I PCK1 O PIO, I, PU, ST A1 VDDANA GPIO_ANA PB10 I/O AD11 I PCK0 O PIO, I, PU, ST C7 VDDANA GPIO_ANA PB11 I/O AD0 I PWM0 O PIO, I, PU, ST C8 VDDANA GPIO_ANA PB12 I/O AD1 I PWM1 O PIO, I, PU, ST D3 VDDANA GPIO_ANA PB13 I/O AD2 I PWM2 O PIO, I, PU, ST F5 VDDANA GPIO_ANA PB14 I/O AD3 I PWM3 O PIO, I, PU, ST E6 VDDANA GPIO_ANA PB15 I/O AD4 I PIO, I, PU, ST C9 VDDANA GPIO_ANA PB16 I/O AD5 I I PIO, I, PU, ST D2 VDDANA GPIO_ANA PB17 I/O AD6 I I PIO, I, PU, ST E7 VDDANA GPIO PB18 I/O IRQ I ADTRG I PIO, I, PU, ST F3 VDDIOP1 GPIO PC0 I/O LCDDAT0 O TWD1 I/O PIO, I, PU, ST G2 VDDIOP1 GPIO PC1 I/O LCDDAT1 O TWCK1 O PIO, I, PU, ST L7 VDDIOP1 GPIO PC2 I/O LCDDAT2 O TIOA3 I/O PIO, I, PU, ST G3 VDDIOP1 GPIO PC3 I/O LCDDAT3 O TIOB3 I/O PIO, I, PU, ST H5 VDDIOP1 GPIO PC4 I/O LCDDAT4 O TCLK3 I PIO, I, PU, ST M7 VDDIOP1 GPIO PC5 I/O LCDDAT5 O TIOA4 I/O PIO, I, PU, ST H3 VDDIOP1 GPIO PC6 I/O LCDDAT6 O TIOB4 I/O PIO, I, PU, ST H2 VDDIOP1 GPIO PC7 I/O LCDDAT7 O TCLK4 I PIO, I, PU, ST J3 VDDIOP1 GPIO PC8 I/O LCDDAT8 O UTXD0 O PIO, I, PU, ST M8 VDDIOP1 GPIO PC9 I/O LCDDAT9 O URXD0 I PIO, I, PU, ST J5 VDDIOP1 GPIO PC10 I/O LCDDAT10 O PWM0 O PIO, I, PU, ST K6 VDDIOP1 GPIO PC11 I/O LCDDAT11 O PWM1 O PIO, I, PU, ST P9 VDDIOP1 GPIO PC12 I/O LCDDAT12 O TIOA5 I/O PIO, I, PU, ST L6 VDDIOP1 GPIO PC13 I/O LCDDAT13 O TIOB5 I/O PIO, I, PU, ST J2 VDDIOP1 GPIO PC14 I/O LCDDAT14 O TCLK5 I PIO, I, PU, ST K3 VDDIOP1 GPIO_CLK PC15 I/O LCDDAT15 O PCK0 O PIO, I, PU, ST K2 VDDIOP1 GPIO PC16 I/O LCDDAT16 O UTXD1 O PIO, I, PU, ST K5 VDDIOP1 GPIO PC17 I/O LCDDAT17 O URXD1 I PIO, I, PU, ST L3 VDDIOP1 GPIO PC18 I/O LCDDAT18 O PWM0 O PIO, I, PU, ST N8 VDDIOP1 GPIO PC19 I/O LCDDAT19 O PWM1 O PIO, I, PU, ST L2 VDDIOP1 GPIO PC20 I/O LCDDAT20 O PWM2 O PIO, I, PU, ST P8 VDDIOP1 GPIO PC21 I/O LCDDAT21 O PWM3 O PIO, I, PU, ST M3 VDDIOP1 GPIO PC22 I/O LCDDAT22 O TXD3 O PIO, I, PU, ST L5 VDDIOP1 GPIO PC23 I/O LCDDAT23 O RXD3 I PIO, I, PU, ST N6 VDDIOP1 GPIO PC24 I/O LCDDISP O RTS3 O PIO, I, PU, ST Table 4-2. BGA247 Pin Description (Continued) Ball Power Rail I/O Type Primary Alternate PIO Peripheral A PIO Peripheral B PIO Peripheral C Reset State Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir Signal, Dir, PU, PD, ST

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 N2 VDDIOP1 GPIO PC25 I/O CTS3 I PIO, I, PU, ST P7 VDDIOP1 GPIO PC26 I/O LCDPWM O SCK3 I/O PIO, I, PU, ST M2 VDDIOP1 GPIO PC27 I/O LCDVSYNC O RTS1 O PIO, I, PU, ST M5 VDDIOP1 GPIO PC28 I/O LCDHSYNC O CTS1 I PIO, I, PU, ST N3 VDDIOP1 GPIO_CLK PC29 I/O LCDDEN O SCK1 I/O PIO, I, PU, ST M6 VDDIOP1 GPIO_CLK2 PC30 I/O LCDPCK O PIO, I, PU, ST P2 VDDIOP1 GPIO PC31 I/O FIQ I PCK1 O PIO, I, PU, ST R14 VDDNF EBI PD0 I/O NANDOE O PIO, I, PU R15 VDDNF EBI PD1 I/O NANDWE O PIO, I, PU T17 VDDNF EBI PD2 I/O A21/NANDALE O A21,O, PD P15 VDDNF EBI PD3 I/O A22/NANDCLE O A22,O, PD R17 VDDNF EBI PD4 I/O NCS3 O PIO, I, PU M15 VDDNF EBI PD5 I/O NWAIT I PIO, I, PU N15 VDDNF EBI PD6 I/O D16 O PIO, I, PU V13 VDDNF EBI PD7 I/O D17 O PIO, I, PU L14 VDDNF EBI PD8 I/O D18 O PIO, I, PU W18 VDDNF EBI PD9 I/O D19 O PIO, I, PU V18 VDDNF EBI PD10 I/O D20 O PIO, I, PU W19 VDDNF EBI PD11 I/O D21 O PIO, I, PU V19 VDDNF EBI PD12 I/O D22 O PIO, I, PU N18 VDDNF EBI PD13 I/O D23 O PIO, I, PU L15 VDDNF EBI PD14 I/O D24 O PIO, I, PU N17 VDDNF EBI PD15 I/O D25 O A20 O A20, O, PD M18 VDDNF EBI PD16 I/O D26 O A23 O A23, O, PD M17 VDDNF EBI PD17 I/O D27 O A24 O A24, O, PD P17 VDDNF EBI PD18 I/O D28 O A25 O A25, O, PD L18 VDDNF EBI PD19 I/O D29 O NCS2 O PIO, I, PU K15 VDDNF EBI PD20 I/O D30 O NCS4 O PIO, I, PU L17 VDDNF EBI PD21 I/O D31 O NCS5 O PIO, I, PU E8, E9, E13, F7, F8, F9, G14 VDDIOM POWER VDDIOM I I M14,P 13,U1 0,V9, V10, V11 VDDNF POWER VDDNF I I Table 4-2. BGA247 Pin Description (Continued) Ball Power Rail I/O Type Primary Alternate PIO Peripheral A PIO Peripheral B PIO Peripheral C Reset State Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir Signal, Dir, PU, PD, ST

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 H6, H7, J6, J7, J8, F10, F11, F12, F13, F14, F15, F16 GNDIOM GND GNDIOM I I N11, M12, M13 VDDIOP0 POWER VDDIOP0 I I M9, M10, M11 VDDIOP1 POWER VDDIOP1 I I L10, L11, L12, L13, V14 GNDIOP GND GNDIOP I I B6 VDDBU POWER VDDBU I I B7 GNDBU GND GNDBU I I F6 VDDANA POWER VDDANA I I C3 GNDANA GND GNDANA I I V17 VDDPLL POWER VDDPLL I I U16 GNDPLL GND GNDPLL I I P14 VDDFUSE POWER VDDFUSE I I N14 GNDFUSE GND GNDFUSE I I R12 VDDOSC POWER VDDOSC I I U13 VDDUSB POWER VDDUSB I I U17 GNDUSB GND GNDUSB I I J12, J13, J14, K10, K11, K12, K13, K14, U15 VDDCORE POWER VDDCORE I I H9, J9, J10, J11, K7, K9, L8, GNDCORE GND GNDCORE I I A19 VDDIOM EBI D0 I/O I, PD Table 4-2. BGA247 Pin Description (Continued) Ball Power Rail I/O Type Primary Alternate PIO Peripheral A PIO Peripheral B PIO Peripheral C Reset State Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir Signal, Dir, PU, PD, ST

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 E15 VDDIOM EBI D1 I/O I, PD C18 VDDIOM EBI D2 I/O I, PD D15 VDDIOM EBI D3 I/O I, PD B17 VDDIOM EBI D4 I/O I, PD E14 VDDIOM EBI D5 I/O I, PD C16 VDDIOM EBI D6 I/O I, PD A18 VDDIOM EBI D7 I/O I, PD B15 VDDIOM EBI D8 I/O I, PD G12 VDDIOM EBI D9 I/O I, PD C14 VDDIOM EBI D10 I/O I, PD D13 VDDIOM EBI D11 I/O I, PD A16 VDDIOM EBI D12 I/O I, PD A14 VDDIOM EBI D13 I/O I, PD B13 VDDIOM EBI D14 I/O I, PD H13 VDDIOM EBI D15 I/O I, PD J15 VDDIOM EBI_O A0 O NBS0 O O K18 VDDIOM EBI_O A1 O NBS2/ DQM2/ NWR2 O O K17 VDDIOM EBI_O A2 O O H15 VDDIOM EBI_O A3 O O J18 VDDIOM EBI_O A4 O O J17 VDDIOM EBI_O A5 O O G17 VDDIOM EBI_O A6 O O H17 VDDIOM EBI_O A7 O O H18 VDDIOM EBI_O A8 O O H14 VDDIOM EBI_O A9 O O G18 VDDIOM EBI_O A10 O O F18 VDDIOM EBI_O A11 O O F17 VDDIOM EBI_O A12 O O E19 VDDIOM EBI_O A13 O O D19 VDDIOM EBI_O A14 O O E18 VDDIOM EBI_O A15 O O G15 VDDIOM EBI_O A16 O BA0 O O E16 VDDIOM EBI_O A17 O BA1 O O B19 VDDIOM EBI_O A18 O BA2 O O D17 VDDIOM EBI_O A19 O O B9 VDDIOM EBI_O NCS0 O O, PU B8 VDDIOM EBI_O NCS1 O SDCS O O, PU E10 VDDIOM EBI_O NRD O O, PU Table 4-2. BGA247 Pin Description (Continued) Ball Power Rail I/O Type Primary Alternate PIO Peripheral A PIO Peripheral B PIO Peripheral C Reset State Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir Signal, Dir, PU, PD, ST

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 G10 VDDIOM EBI_O NWR0 O NWRE O O, PU C10 VDDIOM EBI_O NWR1 O NBS1 O O, PU G9 VDDIOM EBI_O NWR3 O NBS3/ DQM3 O O, PU B10 VDDIOM EBI_CLK SDCK O O B11 VDDIOM EBI_CLK #SDCK O O C12 VDDIOM EBI_O SDCKE O O, PU G11 VDDIOM EBI_O RAS O O, PU E12 VDDIOM EBI_O CAS O O, PU H12 VDDIOM EBI_O SDWE O O, PU H10 VDDIOM EBI_O SDA10 O O, PU A12 VDDIOM EBI_O DQM0 O O, PU C11 VDDIOM EBI_O DQM1 O O, PU H11 VDDIOM EBI DQS0 I/O I, PD E11 VDDIOM EBI DQS1 I/O I, PD B3 VDDANA POWER ADVREF I I T18 VDDUSB USBFS HDP I/O O, PD U18 VDDUSB USBFS HDM I/O O, PD P18 VDDUSB USBFS DDP I/O O, PD R18 VDDUSB USBFS DDM I/O O, PD C6 VDDBU SYSC WKUP I I, ST G8 VDDBU SYSC SHDN O O, PU U14 VDDCORE RSTJTAG BMS I I, PU, ST C4 VDDBU SYSC JTAGSEL I I, PD, ST C5 VDDBU SYSC TST I I, PD, ST V8 VDDIOP0 RSTJTAG TCK I I, ST U8 VDDIOP0 RSTJTAG TDI I I, ST P12 VDDIOP0 RSTJTAG TDO O O, ST R11 VDDIOP0 RSTJTAG TMS I I, ST V12 VDDIOP0 RSTJTAG RTCK O O, ST U11 VDDIOP0 RSTJTAG NRST I/O O, PU, ST U9 VDDIOP0 RSTJTAG NTRST I I, PU, ST B4 VDDBU CLOCK XIN32 I I B5 VDDBU CLOCK XOUT32 O O V16 VDDIOP0 CLOCK XIN I I V15 VDDIOP0 CLOCK XOUT O O H8 NC U12 NC R13 NC Table 4-2. BGA247 Pin Description (Continued) Ball Power Rail I/O Type Primary Alternate PIO Peripheral A PIO Peripheral B PIO Peripheral C Reset State Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir Signal, Dir, PU, PD, ST

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 5. Power Considerations

5.1 Power Supplies

The SAM9N12/CN11/CN12 has several types of power supply pins: Table 5-1. SAM9N12/CN11/CN12 Power Supplies Name Voltage Range, nominal Associated Ground Powers VDDCORE 0.9-1.1V, 1.0V GNDCORE the core, including the processor, the embedded memories and the peripherals, the internal 12 MHz RC VDDIOM 1.65-1.95V, 1.8V 3.0-3.6V, 3.3V GNDIOM the External Memory Interface I/O lines VDDNF 1.65-1.95V, 1.8V 3.0-3.6V, 3.3V GNDIOM the NAND Flash I/O and control, D16-D32 and multiplexed SMC lines VDDIOP0 1.65-3.6V GNDIOP a part of Peripherals I/O lines VDDIOP1 1.65-3.6V GNDIOP a part of Peripherals I/O lines VDDBU 1.65-3.6V GNDBU the Slow Clock oscillator, the internal 32-kbyte RC and a part of the System Controller VDDUSB 3.0-3.6V, 3.3V GNDUSB the USB interface VDDPLL 0.9-1.1V, 1.0V GNDPLL the PLL cells VDDOSC 1.65-3.6V GNDPLL the Main Oscillator cells VDDANA 3.0-3.6V, 3.3V GNDANA the Analog to Digital Converter VDDFUSE 3.0-3.6V, 3.3V GNDFUSE Fuse box for programming

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 6. Memories Figure 6-1. SAM9N12/CN11/CN12 Memory Mapping 0x1000 0000 0x0000 0000 0x0FFF FFFF 0xF000 0000 0xEFFF FFFF Address Memory Space Internal Peripherals Internal Memories EBI Chip Select 0 Undefined (Abort) 1,792 MBytes 0x2000 0000 0x1FFF FFFF 0x3000 0000 0x2FFF FFFF 0x4000 0000 0x3FFF FFFF 0x5000 0000 0x4FFF FFFF

256 MBytes

Notes: (1) Can be ROM, EBI1_NCS0 or SRAM depending on BMS and REMAP 0xFFFF FFFF EBI Chip Select 3/ NANDFlash EBI Chip Select 4 EBI Chip Select 1/ DDR2/LPDDR SDR/LPSDR EBI Chip Select 2 0xF800 8000 0xF801 0000 SPI0 0xF800 C000 TC0, TC1, TC2 MCI 0xF000 8000 0xF001 0000 USART0 USART1 TWI1 TWI0 0xF001 4000 0xFFFF FE00 0xFFFF FC00

16 Bytes

512 Bytes

16 BytesSHDC

16 BytesPITC

16 BytesWDTC

4 Bytes

1 MBytes

Boot Memory (1) 0x0000 0000 Undefined (Abort) TC3, TC4, TC5 UART0 UART1 Reserved 0xF804 0000 0xF804 8000 0xF804 4000 0xF804 C000 (Abort) 0xF000 4000 LCDC 0xF805 0000 0xFFFF FEC0 Reserved Reserved 0xFFFF F000 0xFFFF F200 0xFFFF F400 0xFFFF F600 0xFFFF F800 0xFFFF FA00 0xFFFF EC00 0xFFFF EA00 0xFFFF E800 0xFFFF E600 0xFFFF E000 (Abort) Reserved Reserved Reserved AES * TRNG SHA 0xF001 8000 Reserved FUSE 512 Bytes 0xFFFF DC00 EBI Chip Select 5 0x6FFF FFFF 0x6000 0000 0x5FFF FFFF 0x7000 0000

  • Reserved for SAM9N12

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

6.1 Memory Mapping

A first level of address decoding is performed by the AHB Bus Matrix, i.e., the implementation of the Advanced High performance Bus (AHB) fo r its Master and Slave interfaces with addi- tional features. Decoding breaks up the 4 Gbytes of address space into 16 banks of 256 Mbytes. The banks 1 to 6 are directed to the EBI that associates these banks to the external chip selects EBI_NCS0 to EBI_NCS5. The bank 0 is reserved for the addressing of the internal memories, and a sec- ond level of decoding provides 1Mbyte of internal memory area. Bank 15 is reserved for the peripherals and provides access to the Advanced Peripheral Bus (APB). Other areas are unused and performing an access within them provides an abort to the master requesting such an access.

6.2 Embedded Memories

6.2.1 Internal SRAM

The SAM9N12/CN11/CN12 embeds a total of 32 Kbytes high-speed SRAM. After reset and until the Remap Command is performed, the SRAM is only accessible at address 0x0030 0000. After Remap, the SRAM also becomes available at address 0x0.

6.2.2 Internal ROM

The SAM9CN12 contains the secure bootloader (standard bootloader for SAM9N12 and SAM9CN11) and specific tables used to compute SLC and MLC NAND Flash ECC. The ROM is mapped at address 0x0010 0000. It is also accessible at address 0x0 (BMS = 1) after the reset and before the Remap Command.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

6.3 External Memories Overview

The SAM9N12/CN11/CN12 features an External Bus Interface to provide interface to a wide range of external memories and to any parallel peripheral.

6.3.1 External Bus Interface

  • Integrates three External Memory Controllers: – Static Memory Controller – DDR2/SDRAM Controller – MLC NAND Flash ECC Controller
  • Up to 26-bit Address Bus (up to 64 MBytes linear per chip select)
  • Up to 6 chips selects, Configurable Assignment: – Static Memory Controller on NCS 0, NCS1, NCS2, NCS3, NCS4, NCS5 – DDR2/SDRAM Controller (SDCS) or Static Memory Controller on NCS1 – NAND Flash support on NCS3

6.3.2 Static Memory Controller

  • 8- or 16-bit Data Bus
  • Multiple Access Modes supported – Byte Write or Byte Select Lines – Asynchronous read in Page Mode supported (4- up to 16-byte page size)
  • Multiple device adaptability – Control signals programmable setup, pulse and hold time for each Memory Bank
  • Multiple Wait State Management – Programmable Wait State Generation – External Wait Request – Programmable Data Float Time
  • Slow Clock mode supported

6.3.3 DDR-SDRAM Controller

  • Supports DDR2-SDRAM, Low-power DDR1-SDRAM or DDR2-SDRAM, SDR-SDRAM and Low-power SDR-SDRAM
  • Numerous Configurations Supported – 2K, 4K, 8K, 16K Row Address Memory Parts – SDRAM with 4 Internal Banks – SDR-SDRAM with 16-bit or 32-bit Data Path – DDR-SDRAM with 16-bit Data Path – One Chip Select for SDRAM Device (256 Mbytes Address Space)
  • Programming Facilities – Multibank Ping-pong Access (Up to 4 Banks or 8 Banks Opened at Same Time = Reduced Average Latency of Transactions) – Timing Parameters Specified by Software – Automatic Refresh Operation, Refresh Rate is Programmable

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 – Automatic Update of DS, TCR and PASR Parameters (Low-power SDRAM Devices)

  • Energy-saving Capabilities – Self-refresh, Power-down, Active Power-down and Deep Power-down Modes Supported
  • SDRAM Power-up Initialization by Software
  • CAS Latency of 2, 3 Supported
  • Reset Function Supported (DDR2-SDRAM)
  • ODT (On-die Termination) Not Supported
  • Auto Precharge Command Not Used
  • SDR-SDRAM with 16-bit Datapath and Eight Columns Not Supported
  • DDR2-SDRAM with Eight Internal Banks Supported
  • Linear and interleaved decoding supported
  • Clock Frequency Change in Precharge Power-down Mode Not Supported
  • OCD (Off-chip Driver) Mode Not Supported

6.3.4 Programmable Multi-bit Error Correcting Code (PMECC)

  • Multibit Error Correcting Code.
  • Algorithm based on binary shortened Bose, Chaudhuri and Hocquenghem (BCH) codes.
  • Programmable Error Correcting Capability: 2, 4, 8, 16 and 24 bit of errors per block.
  • Programmable block size: 512 bytes or 1024 bytes.
  • Programmable number of block per page: 1, 2, 4 or 8 blocks of data per page.
  • Programmable spare area size.
  • Supports spare area ecc protection.
  • Supports 8 kbytes page size using 1024 bytes/block and 4 kbytes page size using 512 bytes/block.
  • Multibit Error detection is interrupt driven.

6.3.5 Programmable Multi-bit ECC Error Location (PMERRLOC)

  • Provides hardware acceleration for determining roots of polynomials defined over a finite field
  • Programmable finite Field GF(2^13) or GF(2^14)
  • Finds roots of error-locator polynomial.
  • Programmable number of roots.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 7. System Controller The System Controller is a set of peripherals that allows handling of key elements of the sys- tem, such as power, resets, clocks, time, interrupts, watchdog, etc. The System Controller User Interface also embed s the registers that configure the Matrix and a set of registers for the chip configuration. The chip configuration registers configure the EBI chip select assignment and voltage range for external memories.

7.1 System Controller Mapping

The System Controller’s peripherals are all mapped within the highest 16 Kbytes of address space, between addresses 0xFFFF E400 and 0xFFFF FFFF. However, all the registers of the System Controller are mapped on the top of the address space. All the registers of the System Controller can be addressed from a single pointer by using the standard ARM instruction set, as the Load/Store instruction have an indexing mode of ±4 Kbytes. Figure 7-1 on page 27 shows the System Controller block diagram. Figure 6-1 on page 22 shows the mapping of the User Interfaces of the System Controller peripherals.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

7.2 System Controller Block DIagram

Figure 7-1. SAM9N12/CN11/CN12 System Controller Block Diagram NRST SLCK Advanced Interrupt Controller Periodic Interval Timer Reset Controller PA0-PA31 periph_nreset System Controller Watchdog Timer wdt_fault WDRPROC PIO Controllers Power Management Controller XIN XOUT MAINCK PLLACK pit_irq MCK proc_nreset wdt_irq periph_irq[2..3]periph_nreset periph_clk[2..30] PCK MCK pmc_irq nirq nfiq Embedded Peripheralsperiph_clk[2..3] pck[0-1] in out enable ARM926EJ-S SLCK irq fiq irq fiq periph_irq[5..30] periph_irq[2..30] int int periph_nreset periph_clk[5..30] jtag_nreset por_ntrst proc_nreset periph_nreset dbgu_txd dbgu_rxd pit_irq dbgu_irq pmc_irq rstc_irq wdt_irq rstc_irq SLCK Boundary Scan TAP Controller jtag_nreset debug PCK debug idle debug Bus Matrix MCK periph_nresetproc_nreset periph_nreset idle Debug Unit dbgu_irqMCK dbgu_rxd periph_nreset dbgu_txd Shut-Down Controller SLCK backup_nreset SHDN WKUP

4 General-purpose

backup_nreset XIN32 XOUT32 PB0-PB18 PC0-PC31 VDDBU Powered VDDCORE Powered ntrst VDDCORE POR

16 MHz

por_ntrst VDDBU USB Host Full Speed Port UHPCK periph_nreset periph_irq[22] 32-Kbyte RC OSC PD0-PD21 SCKCR SCKCR Real-Time Clock rtc_irqSLCK backup_nreset rtc_alarm DDR sysclk

12 MHz RC

rtc_alarm LCD Pixel clock BSCR USB Device Full Speed Port UDPCK periph_nreset periph_irq[23] UDPCK UHPCK PLLBCKPLLB

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

7.3 Chip Identification

  • Chip ID: 0x819A_07A1
  • SAM9CN12 Chip ID Extension: 5
  • SAM9CN11 Chip ID Extension: 9
  • SAM9N12 Chip ID Extension: 6
  • JTAG ID: 0x05B3_003F
  • ARM926 TAP ID: 0x0792_603F

7.4 Backup Section

The SAM9N12/CN11/CN12 features a Backup Section that embeds:

  • RC Oscillator
  • Slow Clock Oscillator
  • Real Time Counter (RTC)
  • Shutdown Controller
  • 4 backup registers
  • Slow Clock Control Register (SCKCR)
  • A part of the reset Controller (RSTC)
  • This section is powered by the VDDBU rail.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 8. Peripherals

8.1 Peripheral Mapping

As shown in Figure 6-1, the Peripherals are mapped in the upper 256 Mbytes of the address space between the addresses 0xFFF7 8000 and 0xFFFC FFFF. Each User Peripheral is allocated 16 Kbytes of address space.

8.2 Peripheral Identifiers

Figure 8-1 defines the Peripheral Identifiers of the SAM9N12/CN11/CN12. A peripheral identi- fier is required for the control of the peripheral interrupt with the Advanced Interrupt Controller and for the control of the peripheral clock with the Power Management Controller. Table 8-1. SAM9N12/CN11/CN12 Peripheral Identifiers Instance ID Instance name Instance descri ption External interrupt Wired-or interrupt

0 AIC Advanced Interrupt Controller FIQ

1 SYS System Controller Interrupt DBGU, PMC, SYSC,

PMECC, PMERRLOC

2 PIOA,PIOB Parallel I/O Controller A and B

3 PIOC,PIOD Parallel I/O Controller C and D

4 FUSE FUSE Controller

5 USART0 USART 0

6 USART1 USART 1

7 USART2 USART 2

8 USART3 USART 3

9 TWI0 Two-Wire Interface 0

10 TWI1 Two-Wire Interface 1

11 Reserved

12 HSMCI High Speed Multimedia Card Interface

13 SPI0 Serial Peripheral Interface 0

14 SPI1 Serial Peripheral Interface 1

15 UART0 UART 0

16 UART1 UART 1

17 TC0,TC1 Timer Counter 0,1,2,3,4,5

18 PWM Pulse Width Modulation Controller

19 ADC ADC Controller

20 DMAC DMA Controller

21 Reserved

22 UHP USB Host

23 UDP USB Device

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

8.3 Peripheral Interr upts and Clock Control

8.3.1 System Interrupt

The System Interrupt in Source 1 is the wired-OR of the interrupt signals coming from:

  • the DDR2/LPDDR Controller
  • the Debug Unit
  • the Periodic Interval Timer
  • the Real-Time Clock
  • the Watchdog Timer
  • the Reset Controller
  • the Power Management Controller The clock of these peripherals cannot be deactivated and Peripheral ID 1 can only be used within the Advanced Interrupt Controller.

8.3.2 External Interrupts

All external interrupt signals, i.e., the Fast Interrupt signal FIQ or the Interrupt signal IRQ, use a dedicated Peripheral ID. However, there is no clock control associated with these peripheral IDs.

8.4 Peripheral Signal Multiplexing on I/O Lines

The SAM9N12/CN11/CN12 features 4 PIO contro llers, PIOA, PIOB, PIOC and PIOD, which multiplex the I/O lines of the peripheral set. Each PIO Controller controls 32 lines, 19 lines, 32 lines and 22 lines respectively for PIOA, PIOB, PIOC and PIOD. Each line can be assigned to one of three peripheral functions, A, B or Refer to Section 4. “Package and Pinout” and the package pinout tables, Table 4-1, Table 4-2, depending on the package.

8.4.1 Reset State

The column “Reset State” ( Table 4-1 , Table 4-2 ) indicates the reset state of the line with mnemonics.

24 Reserved

25 LCDC LCD Controller

26 Reserved

27 SHA Secure Hash Algorithm

28 SSC Synchronous Serial Controller

29 AES Advanced Encryption Standard

30 TRNG True Random Number Generator

31 AIC Advanced Interrupt Controller IRQ

Table 8-1. SAM9N12/CN11/CN12 Peripheral Identifiers (Continued) Instance ID Instance name Instance descri ption External interrupt Wired-or interrupt

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Indicates whether the PIO Line resets in I/O mode or in peripheral mode. If “PIO” is mentioned, the PIO Line is maintained in a static state as soon as the reset is released. As a result, the bit corresponding to the PIO Line in the register PIO_PSR (Peripheral Status Register) resets low. If a signal name is mentioned in the “Reset State” column, the PIO Line is assigned to this function and the corresponding bit in PIO_PSR resets high. This is the case on pins controlling memories, in particular the address lines, which require the pin to be driven as soon as the reset is released.

  • ‘I’/’O’ Indicates whether the signal is input or output state. Indicates whether Pull-up or Pull-down, or nothing is enabled.
  • “ S T ” Indicates if Schmitt Trigger is enabled. Note: Example: The PB18 “Reset State” column shows “PIO, I, PU, ST”. That means the line PIO18 is configured as an Input with Pull-Up and Schmitt Trigger enabled. PD14 reset state is “PIO, I, PU”. That means PIO Input with Pull-Up. PD15 reset state is “A20, O, PD” which means output address line 20 with Pull-Down.

8.4.2 PIO Line Selection

Peripheral A, B or C is selected thanks to the PIO_ABCDSR1 and PIO_ABCDSR2 registers in the PIO Controller Interface. Table 8-2. PIO Line Selection Px value in PIO_ABCDSR2 Px value in PIO_ABCDSR1 A, B or C 00A 01B 10C

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

8.5 Fuse Box Features

SAM9CN12 embeds 320 One Time Programming (OTP) bits. When the OTP bit is set, it is seen as ‘1’. The user interface allows the user to perform the following operations:

8.5.1 Read

  • 10 registers SR0-SR9 that reflect OTP bit state
  • MSK field (write-once) allow user to mask registers SR1 to SR9
  • All OTP bits are read as ‘1’ when VDDFUSE is floating, all security features are set.

8.5.2 Write

  • Done in one 32-bit DATA register
  • SEL field to select the 32-bit word 0 to 9

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 9. ARM926EJ-S Processor Overview

9.1 Description

The ARM926EJ-S processor is a member of the ARM9™ family of general-purpose microproces- sors. The ARM926EJ-S implements ARM architectu re version 5TEJ and is targeted at multi- tasking applications where full memory management, high performance, low die size and low power are all important features. The ARM926EJ-S processor supports the 32- bit ARM and 16-bit THUMB instruction sets, enabling the user to trade off between high performance and high code density. It also supports 8-bit Java instruction set and includes features fo r efficient execution of Java bytecode, provid- ing a Java performance similar to a JIT (Just-In-Time compilers), for the next generation of Java- powered wireless and embedded devices. It includes an enhanced multiplier design for improved DSP performance. The ARM926EJ-S processor supports the ARM debug architecture and includes logic to assist in both hardware and software debug. The ARM926EJ-S provides a complete high performance processor subsystem, including:

  • an ARM9EJ-S™ integer core
  • a Memory Management Unit (MMU)
  • separate instruction and data AMBA AHB bus interfaces
  • separate instruction and data TCM interfaces

9.2 Embedded Characteristics

  • ARM9EJ-S™ Based on ARM® Architecture v5TEJ with Jazelle Technology – Three Instruction Sets –A R M ® High-performance 32-bit Instruction Set –T h u m b® High Code Density 16-bit Instruction Set – Jazelle® 8-bit Instruction Set
  • 5-Stage Pipeline Architecture when Jazelle is not Used – Fetch (F) – Decode (D) – Execute (E) –M e m o r y ( M ) –W r i t e b a c k ( W )
  • 6-Stage Pipeline when Jazelle is Used –F e t c h – Jazelle/Decode (Two Cycles) –E x e c u t e –M e m o r y –W r i t e b a c k
  • ICache and DCache – Virtually-addressed 4-way Set Associative Caches – 8 Words per Line

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 – Critical-word First Cache Refilling – Write-though and Write-back Operation for DCache Only – Pseudo-random or Round-robin Replacement – Cache Lockdown Registers – Cache Maintenance

  • Write Buffer – 16-word Data Buffer – 4-address Address Buffer – Software Control Drain
  • DCache Write-back Buffer – 8 Data Word Entries – One Address Entry – Software Control Drain
  • Tightly-coupled Memory (TCM) – Separate Instruction and Data TCM Interfaces – Provides a Mechanism for DMA Support
  • Memory Management Unit (MMU) – Access Permission for Sections – Access Permission for Large Pages and Small Pages – 16 Embedded Domains – 64 Entry Instruction TLB and 64 Entry Data TLB
  • Memory Access – 8-, 16-, and 32-bit Data Types – Separate AMBA AHB Buses for Both the 32-bit Data Interface and the 32-bit Instructions Interface
  • Bus Interface Unit – Arbitrates and Schedules AHB Requests – Enables Multi-layer AHB to be Implemented – Increases Overall Bus Bandwidth – Makes System Architecture Mode Flexible

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

9.3 Block Diagram

Figure 9-1. ARM926EJ-S Internal Functional Block Diagram CP15 System Configuration Coprocessor External Coprocessor Interface Trace Port Interface ARM9EJ-S Processor Core DTCM Interface Data TLB Instruction TLB ITCM Interface Data Cache AHB Interface and Write Buffer Instruction Cache Write Data Read Data Instruction Fetches Data Address Instruction Address Data Address Instruction Address Instruction TCMData TCM MMU AMBA AHB External Coprocessors ETM9

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

9.4 ARM9EJ-S Processor

9.4.1 ARM9EJ-S Operating States

The ARM9EJ-S processor can operate in three different states, each with a specific instruction set:

  • ARM state: 32-bit, word-aligned ARM instructions.
  • THUMB state: 16-bit, halfword-aligned Thumb instructions.
  • Jazelle state: variable length, byte-aligned Jazelle instructions. In Jazelle state, all instruction Fetches are in words.

9.4.2 Switching State

The operating state of the ARM9EJ-S core can be switched between:

  • ARM state and THUMB state using the BX and BLX instructions, and loads to the PC
  • ARM state and Jazelle state using the BXJ instruction All exceptions are entered, handled and exited in ARM state. If an exception occurs in Thumb or Jazelle states, the processor reverts to ARM state. The transition back to Thumb or Jazelle states occurs automatically on return from the exception handler.

9.4.3 Instruction Pipelines

The ARM9EJ-S core uses two kinds of pipelines to increase the speed of the flow of instructions to the processor. A five-stage (five clock cycles) pipeline is used for ARM and Thumb states. It consists of Fetch, Decode, Execute, Memory and Writeback stages. A six-stage (six clock cycles) pipeline is us ed for Jazelle state It consists of Fetch, Jazelle/Decode (two clock cycles), Execute, Memory and Writeback stages.

9.4.4 Memory Access

The ARM9EJ-S core supports byte (8-bit), half-word (16-bit) and word (32-bit) access. Words must be aligned to four-byte boundaries, half-words must be aligned to two-byte boundaries and bytes can be placed on any byte boundary. Because of the nature of the pipelines, it is possible for a value to be required for use before it has been placed in the register bank by the actions of an earlier instruction. The ARM9EJ-S con- trol logic automatically detects these cases and stalls the core or forward data.

9.4.5 Jazelle Technology

The Jazelle technology enables direct and efficient execution of Java byte codes on ARM pro- cessors, providing high performance for the next generation of Java-powered wireless and embedded devices. The new Java feature of ARM9EJ-S can be described as a hardware emulation of a JVM (Java Virtual Machine). Java mode will appear as another state: instead of executing ARM or Thumb instructions, it executes Java byte codes. The Java byte code decoder logic implemented in ARM9EJ-S decodes 95% of executed byte codes and turns them into AR M instructions without any overhead, while less frequently used byte codes are broken down into optimized sequences of ARM instructions. The hardware/software split is invisible to the programmer, invisible to the application and invisible to the operating system. All existing ARM registers are re-used in Jazelle state and all registers then have particular functions in this mode.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Minimum interrupt latency is maintained across both ARM state and Java state. Since byte codes execution can be restarted, an interrupt automatically triggers the core to switch from Java state to ARM state for the execution of the interrupt handler. This means that no special provision has to be made for handling interrupts while executing byte codes, whether in hard- ware or in software.

9.4.6 ARM9EJ-S Operating Modes

In all states, there are seven operation modes:

  • User mode is the usual ARM program execution state. It is used for executing most application programs
  • Fast Interrupt (FIQ) mode is used for handling fast interrupts. It is suitable for high-speed data transfer or channel process
  • Interrupt (IRQ) mode is used for general-purpose interrupt handling
  • Supervisor mode is a protected mode for the operating system
  • Abort mode is entered after a data or instruction prefetch abort
  • System mode is a privileged user mode for the operating system
  • Undefined mode is entered when an undefined instruction exception occurs Mode changes may be made under software control, or may be brought about by external inter- rupts or exception processing. Most application programs execute in User Mode. The non-user modes, known as privileged modes, are entered in order to service interrupts or exceptions or to access protected resources.

9.4.7 ARM9EJ-S Registers

The ARM9EJ-S core has a total of 37 registers.

  • 31 general-purpose 32-bit registers
  • 6 32-bit status registers Table 9-1 shows all the registers in all modes. Table 9-1. ARM9TDMI Modes and Registers Layout User and System Mode Supervisor Mode Abort Mode Undefined Mode Interrupt Mode Fast Interrupt Mode R0 R0 R0 R0 R0 R0 R1 R1 R1 R1 R1 R1 R2 R2 R2 R2 R2 R2 R3 R3 R3 R3 R3 R3 R4 R4 R4 R4 R4 R4 R5 R5 R5 R5 R5 R5 R6 R6 R6 R6 R6 R6 R7 R7 R7 R7 R7 R7 R8 R8 R8 R8 R8 R8_FIQ R9 R9 R9 R9 R9 R9_FIQ R10 R10 R10 R10 R10 R10_FIQ R11 R11 R11 R11 R11 R11_FIQ

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 The ARM state register set contains 16 directly-accessible registers, r0 to r15, and an additional register, the Current Program Status Register (CPSR). Registers r0 to r13 are general-purpose registers used to hold either data or address va lues. Register r14 is used as a Link register that holds a value (return address) of r15 when BL or BLX is executed. Register r15 is used as a pro- gram counter (PC), whereas the Current Program Status Register (CPSR) contains condition code flags and the current mode bits. In privileged modes (FIQ, Supervisor, Abort, IRQ, Undefined), mode-specific banked registers (r8 to r14 in FIQ mode or r13 to r14 in the other modes) become available. The corresponding banked registers r14_fiq, r14_svc, r14_abt, r14_irq, r14_und are similarly used to hold the val- ues (return address for each mode) of r15 (PC) when interrupts and exceptions arise, or when BL or BLX instructions are executed within interrupt or exception routines. There is another reg- ister called Saved Program Status Register (SPSR) that becomes available in privileged modes instead of CPSR. This register contains condition code flags and the current mode bits saved as a result of the exception that caused entry to the current (privileged) mode. In all modes and due to a software agreement, register r13 is used as stack pointer. The use and the function of all the registers described above should obey ARM Procedure Call Standard (APCS) which defines:

  • constraints on the use of registers
  • stack conventions
  • argument passing and result return For more details, refer to ARM Software Development Kit. The Thumb state register set is a subset of the ARM state set. The programmer has direct access to:
  • Eight general-purpose registers r0-r7
  • Stack pointer, SP
  • Link register, LR (ARM r14)
  • P C
  • CPSR R12 R12 R12 R12 R12 R12_FIQ R13 R13_SVC R13_ABORT R13_UNDEF R13_IRQ R13_FIQ R14 R14_SVC R14_ABORT R14_UNDEF R14_IRQ R14_FIQ PC PC PC PC PC PC CPSR CPSR CPSR CPSR CPSR CPSR SPSR_SVC SPSR_ABORT SPSR_UNDEF SPSR_IRQ SPSR_FIQ Mode-specific banked registers Table 9-1. ARM9TDMI Modes and Registers Layout (Continued) User and System Mode Supervisor Mode Abort Mode Undefined Mode Interrupt Mode Fast Interrupt Mode

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 There are banked registers SPs, LRs and SPSRs for each privileged mode (for more details see the ARM9EJ-S Technical Reference Manual, revision r1p2 page 2-12).

9.4.7.1 Status Registers

The ARM9EJ-S core contains one CPSR, and fi ve SPSRs for exception handlers to use. The program status registers:

  • hold information about the most recently performed ALU operation
  • control the enabling and disabling of interrupts
  • set the processor operation mode Figure 9-2. Status Register Format Figure 9-2 shows the status register format, where:
  • N: Negative, Z: Zero, C: Carry, and V: Overflow are the four ALU flags
  • The Sticky Overflow (Q) flag can be set by certain multiply and fractional arithmetic instructions like QADD, QDADD, QSUB, QDSUB, SMLAxy, and SMLAWy needed to achieve DSP operations. The Q flag is sticky in that, when set by an instruction, it remains set until explicitly cleared by an MSR instruction writing to the CPSR. Instructions cannot execute conditionally on the status of the Q flag.
  • The J bit in the CPSR indicates when the AR M9EJ-S core is in Jazelle state, where: – J = 0: The processor is in ARM or Thumb state, depending on the T bit – J = 1: The processor is in Jazelle state.
  • Mode: five bits to encode the current processor mode

9.4.8 Exceptions

9.4.8.1 Exception Types and Priorities

The ARM9EJ-S supports five types of exceptions. Each type drives the ARM9EJ-S in a privi- leged mode. The types of exceptions are:

  • Fast interrupt (FIQ)
  • Normal interrupt (IRQ)
  • Data and Prefetched aborts (Abort)
  • Undefined instruction (Undefined)
  • Software interrupt and Reset (Supervisor) NZ CVQ JI F T ModeReserved Mode bits Thumb state bit FIQ disable IRQ disable Jazelle state bit Reserved Sticky Overflow Overflow Carry/Borrow/Extend Zero Negative/Less than 31 30 29 28 27 24 7 6 5 0

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 When an exception occurs, the banked version of R14 and the SPSR for the exception mode are used to save the state. More than one exception can happen at a time, therefore the ARM9EJ-S takes the arisen excep- tions according to the following priority order:

  • Reset (highest priority)
  • Data Abort
  • F I Q
  • I R Q
  • P r e f e t c h A b o r t
  • BKPT, Undefined instruction, and Software Interrupt (SWI) (Lowest priority) The BKPT, or Undefined instruction, and SWI exceptions are mutually exclusive. Note that there is one exception in the priority scheme: when FIQs are enabled and a Data Abort occurs at the same time as an FIQ, the ARM9EJ-S core enters the Data Abort handler, and pro- ceeds immediately to FIQ vector. A normal return from the FIQ causes the Data Abort handler to resume execution. Data Aborts must have higher priority than FIQs to ensure that the transfer error does not escape detection.

9.4.8.2 Exception Modes and Handling

Exceptions arise whenever the normal flow of a program must be halted temporarily, for exam- ple, to service an interrupt from a peripheral. When handling an ARM exception, the ARM9EJ-S core performs the following operations: 1. Preserves the address of the next instruction in the appropriate Link Register that cor- responds to the new mode that has been entered. When the exception entry is from: – ARM and Jazelle states, the ARM9EJ-S copies the address of the next instruction into LR (current PC(r15) + 4 or PC + 8 depending on the exception). – THUMB state, the ARM9EJ-S writes the value of the PC into LR, offset by a value (current PC + 2, PC + 4 or PC + 8 depending on the exception) that causes the program to resume from the correct place on return. 2. Copies the CPSR into the appropriate SPSR. 3. Forces the CPSR mode bits to a value that depends on the exception. 4. Forces the PC to fetch the next instruction from the relevant exception vector. The register r13 is also banked across exception modes to provide each exception handler with private stack pointer. The ARM9EJ-S can also set the interrupt disable flags to prevent otherwise unmanageable nesting of exceptions. When an exception has completed, the exception handler must move both the return value in the banked LR minus an offset to the PC and the SPSR to the CPSR. The offset value varies according to the type of exception. This action restores both PC and the CPSR. The fast interrupt mode has seven private registers r8 to r14 (banked registers) to reduce or remove the requirement for register saving which minimizes the overhead of context switching. The Prefetch Abort is one of the aborts that indicates that the current memory access cannot be completed. When a Prefetch Abort occurs, the ARM9EJ-S marks the prefetched instruction as invalid, but does not take the exception until th e instruction reaches the Execute stage in the

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 pipeline. If the instruction is not executed, for example because a branch occurs while it is in the pipeline, the abort does not take place. The breakpoint (BKPT) instruction is a new feat ure of ARM9EJ-S that is destined to solve the problem of the Prefetch Abort. A breakpoint instruction operates as though the instruction caused a Prefetch Abort. A breakpoint instruction does not cause the ARM9EJ-S to take the Prefetch Abort exception until the instruction reaches the Execute stage of the pipeline. If the instruction is not executed, for example because a branch occurs while it is in the pipeline, the breakpoint does not take place.

9.4.9 ARM Instruction Set Overview

The ARM instruction set is divided into:

  • Branch instructions
  • Data processing instructions
  • Status register transfer instructions
  • Load and Store instructions
  • Coprocessor instructions
  • Exception-generating instructions ARM instructions can be executed conditionally. Every instruction contains a 4-bit condition code field (bits[31:28]). Table 9-2 gives the ARM instruction mnemonic list. Table 9-2. ARM Instruction Mnemonic List Mnemonic Operation Mnemonic Operation MOV Move MVN Move Not ADD Add ADC Add with Carry SUB Subtract SBC Subtract with Carry RSB Reverse Subtract RSC Reverse Subtract with Carry CMP Compare CMN Compare Negated TST Test TEQ Test Equivalence AND Logical AND BIC Bit Clear EOR Logical Exclusive OR ORR Logical (inclusive) OR MUL Multiply MLA Multiply Accumulate SMULL Sign Long Multiply UMULL Unsigned Long Multiply SMLAL Signed Long Multiply Accumulate UMLAL Unsigned Long Multiply Accumulate MSR Move to Status Register MRS Move From Status Register B Branch BL Branch and Link BX Branch and Exchange SWI Software Interrupt LDR Load Word STR Store Word LDRSH Load Signed Halfword LDRSB Load Signed Byte LDRH Load Half Word STRH Store Half Word LDRB Load Byte STRB Store Byte

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9.4.10 New ARM Instruction Set

Notes: 1. A Thumb BLX contains two consecutiv e Thumb instructions, and takes four cycles.

9.4.11 Thumb Instruction Set Overview

The Thumb instruction set is a re-encoded subset of the ARM instruction set. The Thumb instruction set is divided into:

  • Branch instructions
  • Data processing instructions
  • Load and Store instructions LDRBT Load Register Byte with Translation STRBT Store Register Byte with Translation LDRT Load Register with Translation STRT Store Register with Translation LDM Load Multiple STM Store Multiple SWP Swap Word SWPB Swap Byte MCR Move To Coprocessor MRC Move From Coprocessor LDC Load To Coprocessor STC Store From Coprocessor CDP Coprocessor Data Processing Table 9-2. ARM Instruction Mnemonic List (Continued) Mnemonic Operation Mnemonic Operation Table 9-3. New ARM Instruction Mnemonic List Mnemonic Operation Mnemonic Operation BXJ Branch and exchange to Java MRRC Move double from coprocessor BLX (1) Branch, Link and exchange MCR2 Alternative move of ARM reg to coprocessor SMLAxy Signed Multiply Accumulate 16 * 16 bit MCRR Move double to coprocessor SMLAL Signed Multiply Accumulate Long CDP2 Alternative Coprocessor Data Processing SMLAWy Signed Multiply Accumulate 32 * 16 bit BKPT Breakpoint SMULxy Signed Multiply 16 * 16 bit PLD Soft Preload, Memory prepare to load from address SMULWy Signed Multiply 32 * 16 bit STRD Store Double QADD Saturated Add STC2 Alternative Store from Coprocessor QDADD Saturated Add with Double LDRD Load Double QSUB Saturated subtract LDC2 Alternative Load to Coprocessor QDSUB Saturated Subtract with double CLZ Count Leading Zeroes

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

  • Load and Store multiple instructions
  • Exception-generating instruction Table 9-4 gives the Thumb instruction mnemonic list. Table 9-4. Thumb Instruction Mnemonic List Mnemonic Operation Mnemonic Operation MOV Move MVN Move Not ADD Add ADC Add with Carry SUB Subtract SBC Subtract with Carry CMP Compare CMN Compare Negated TST Test NEG Negate AND Logical AND BIC Bit Clear EOR Logical Exclusive OR ORR Logical (inclusive) OR LSL Logical Shift Left LSR Logical Shift Right ASR Arithmetic Shift Right ROR Rotate Right MUL Multiply BLX Branch, Link, and Exchange B Branch BL Branch and Link BX Branch and Exchange SWI Software Interrupt LDR Load Word STR Store Word LDRH Load Half Word STRH Store Half Word LDRB Load Byte STRB Store Byte LDRSH Load Signed Halfword LDRSB Load Signed Byte LDMIA Load Multiple STMIA Store Multiple PUSH Push Register to stack POP Pop Register from stack BCC Conditional Branch BKPT Breakpoint

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

9.5 CP15 Coprocessor

Coprocessor 15, or System Control Coprocessor CP15, is used to configure and control all the items in the list below:

  • ARM9EJ-S
  • Caches (ICache, DCache and write buffer)
  • T C M
  • M M U
  • Other system options To control these features, CP15 provides 16 additional registers. See Table 9-5. Notes: 1. Register locations 0,5, and 13 each provide access to more than one register. The register accessed depends on the value of the opcode_2 field. 2. Register location 9 provides access to more than one register. The register accessed depends on the value of the CRm field. Table 9-5. CP15 Registers Register Name Read/Write

0 ID Code(1) Read/Unpredictable

0 Cache type(1) Read/Unpredictable

0 TCM status(1) Read/Unpredictable

1 Control Read/write

2 Translation Table Base Read/write

3 Domain Access Control Read/write

4 Reserved None

5 Data fault Status(1) Read/write

5 Instruction fault status(1) Read/write

6 Fault Address Read/write

7 Cache Operations Read/Write

8 TLB operations Unpredictable/Write

9 cache lockdown(2) Read/write

9 TCM region Read/write

10 TLB lockdown Read/write

11 Reserved None

12 Reserved None

13 FCSE PID (1) Read/write

13 Context ID (1) Read/Write

14 Reserved None

15 Test configuration Read/Write

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

9.5.1 CP15 Registers Access

CP15 registers can only be accessed in privileged mode by:

  • MCR (Move to Coprocessor from ARM Register) instruction is used to write an ARM register to CP15.
  • MRC (Move to ARM Register from Coprocessor) instruction is used to read the value of CP15 to an ARM register. Other instructions like CDP, LDC, STC can cause an undefined instruction exception. The assembler code for these instructions is: MCR/MRC{cond} p15, opcode_1, Rd, CRn, CRm, opcode_2. The MCR, MRC instructions bit pattern is shown below:  CRm[3:0]: Specified Coprocessor Action Determines specific coprocessor action. Its value is dependen t on the CP15 register used. For details, refer to CP15 spe- cific register behavior.  opcode_2[7:5] Determines specific coprocessor operation code. By default, set to 0.  Rd[15:12]: ARM Register Defines the ARM register whose value is transferred to the coprocessor. If R15 is chosen, the result is unpredictable.  CRn[19:16]: Coprocessor Register Determines the destination coprocessor register.  L: Instruction Bit 0 = MCR instruction 1 = MRC instruction  opcode_1[23:20]: Coprocessor Code Defines the coprocessor specific code. Value is c15 for CP15.  cond [31:28]: Condition For more details, see Chapter 2 in ARM926EJ-S TRM. 31 30 29 28 27 26 25 24 cond 1110 23 22 21 20 19 18 17 16 opcode_1 L CRn 15 14 13 12 11 10 9 8 Rd 1111 76543210 opcode_2 1 CRm

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9.6 Memory Management Unit (MMU)

The ARM926EJ-S processor implements an enhanced ARM architecture v5 MMU to provide vir- tual memory features required by operati ng systems like Symbian OS , WindowsCE, and Linux. These virtual memory features are memory access permission controls and virtual to physical address translations. The Virtual Address generated by the CPU core is converted to a Modified Virtual Address (MVA) by the FCSE (Fast Context Switch Extens ion) using the value in CP15 register13. The MMU translates modified virtual addresses to physical addresses by using a single, two-level page table set stored in physical memory. Each entry in the set contains the access permissions and the physical address that correspond to the virtual address. The first level translation tables contain 4096 entries indexed by bits [31:20] of the MVA. These entries contain a pointer to either a 1 MB secti on of physical memory along with attribute infor- mation (access permissions, domain, etc.) or an entry in the second level translation tables; coarse table and fine table. The second level translation tables contain tw o subtables, coarse table and fine table. An entry in the coarse table contains a pointer to both large pages and small pages along with access permissions. An entry in the fine table contains a pointer to large, small and tiny pages. Table 7 shows the different attributes of each page in the physical memory. The MMU consists of:

  • Access control logic
  • Translation Look-aside Buffer (TLB)
  • Translation table walk hardware

9.6.1 Access Control Logic

The access control logic controls access information for every entry in the translation table. The access control logic checks two pieces of access information: domain and access permissions. The domain is the primary access control mechanism for a memory region; there are 16 of them. It defines the conditions necessary for an access to proceed. The domain determines whether the access permissions are used to qualify the access or whether they should be ignored. The second access control mechanism is access permissions that are defined for sections and for large, small and tiny pages. Sections and tiny pages have a single set of access permissions whereas large and small pages can be associated with 4 sets of access permissions, one for each subpage (quarter of a page). Table 9-6. Mapping Details Mapping Name Mapping Size Access Permission By Subpage Size Section 1M byte Section - Large Page 64K bytes 4 separated subpages 16K bytes Small Page 4K bytes 4 separated subpages 1K byte Tiny Page 1K byte Tiny Page -

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9.6.2 Translation Look-aside Buffer (TLB)

The Translation Look-aside Buffer (TLB) caches translated entries and thus avoids going through the translation process every time. When the TLB contains an entry for the MVA (Modi- fied Virtual Address), the access control logic dete rmines if the access is permitted and outputs the appropriate physical address corresponding to the MVA. If access is not permitted, the MMU signals the CPU core to abort. If the TLB does not contain an entry for the MVA, the translation table walk hardware is invoked to retrieve the translation information from the translation table in physical memory.

9.6.3 Translation Table Walk Hardware

The translation table walk hardware is a logic that traverses the translation tables located in physical memory, gets the physical address and access permissions and updates the TLB. The number of stages in the hardware table walking is one or two depending whether the address is marked as a section-mapped access or a page-mapped access. There are three sizes of page-mapped accesses and one size of section-mapped access. Page- mapped accesses are for large pages, small pages and tiny pages. The translation process always begins with a level one fetch. A section-mapped access requires only a level one fetch, but a page-mapped access requires an additional level two fetch. For further details on the MMU, please refer to chapter 3 in ARM926EJ-S Technical Reference Manual.

9.6.4 MMU Faults

The MMU generates an abort on the following types of faults:

  • Alignment faults (for data accesses only)
  • Translation faults
  • Domain faults
  • Permission faults The access control mechanism of the MMU detects the conditions that produce these faults. If the fault is a result of memory access, the MMU aborts the access and signals the fault to the CPU core.The MMU retains status and address information about faults generated by the data accesses in the data fault status register and fault address register. It also retains the status of faults generated by instruction fetches in the instruction fault status register. The fault status register (register 5 in CP15) indicates the cause of a data or prefetch abort, and the domain number of the aborted access when it happens. The fault address register (register 6 in CP15) holds the MVA associated with the access that caused the Data Abort. For further details on MMU faults, please refer to chapter 3 in ARM926EJ-S Technical Reference Manual.

9.7 Caches and Write Buffer

The ARM926EJ-S contains a 16KB Instruction Cache (ICache), a 16KB Data Cache (DCache), and a write buffer. Al though the ICache and DCache share common features, each still has some specific mechanisms. The caches (ICache and DCache) are four-way set associative, addressed, indexed and tagged using the Modified Virtual Address (MVA), with a ca che line length of eight words with two dirty bits for the DCache. The ICache and DCache provide mechanisms for cache lockdown, cache pollution control, and line replacement.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 A new feature is now supported by ARM926EJ-S caches called allocate on read-miss commonly known as wrapping. This feature enables the caches to perform critical word first cache refilling. This means that when a request for a word caus es a read-miss, the cache performs an AHB access. Instead of loading the whole line (eight words), the cache loads the critical word first, so the processor can reach it quickly, and then the remaining words, no matter where the word is located in the line. The caches and the write buffer are controlled by the CP15 register 1 (Control), CP15 register 7 (cache operations) and CP15 register 9 (cache lockdown).

9.7.1 Instruction Cache (ICache)

The ICache caches fetched instructions to be executed by the processor. The ICache can be enabled by writing 1 to I bit of the CP15 Register 1 and disabled by writing 0 to this same bit. When the MMU is enabled, all instruction fetches are subject to translation and permission checks. If the MMU is disabled, all instructions fetches are cachable, no protection checks are made and the physical address is flat-mapped to the modified virtual address. With the MVA use disabled, context switching incurs ICache cleaning and/or invalidating. When the ICache is disabled, all instruction fetches appear on external memory (AHB) (see Tables 4-1 and 4-2 in page 4-4 in ARM926EJ-S TRM). On reset, the ICache entries are invalidated and the ICache is disabled. For best performance, ICache should be enabled as soon as possible after reset.

9.7.2 Data Cache (DCache) and Write Buffer

ARM926EJ-S includes a DCache and a write buffer to reduce the effect of main memory band- width and latency on data access performance. The operations of DCache and write buffer are closely connected.

9.7.2.1 DCache

The DCache needs the MMU to be enabled. All data accesses are subject to MMU permission and translation checks. Data accesses that are aborted by the MMU do not cause linefills or data accesses to appear on the AMBA ASB interface. If the MMU is disabled, all data accesses are noncachable, nonbufferable, with no protecti on checks, and appear on the AHB bus. All addresses are flat-mapped, VA = MVA = PA, whic h incurs DCache cleaning and/or invalidating every time a context switch occurs. The DCache stores the Physical Address Tag (PA Tag) from which every line was loaded and uses it when writing modified lines back to external memory. This means that the MMU is not involved in write-back operations. Each line (8 words) in the DCache has two dirty bits, one for the first four words and the other one for the second four words. These bits, if set, mark the associated half- lines as dirty. If the cache line is replaced due to a linefill or a cache clean operation, the dirty bits are used to decide whether all, half or none is written back to memory. DCache can be enabled or disabled by writing either 1 or 0 to bit C in register 1 of CP15 (see Tables 4-3 and 4-4 on page 4-5 in ARM926EJ-S TRM). The DCache supports write-through and write-back cache operations, selected by memory region using the C and B bits in the MMU translation tables.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 The DCache contains an eight data word entr y, single address entry write-back buffer used to hold write-back data for cache line eviction or cleaning of dirty cache lines. The Write Buffer can hold up to 16 words of data and four separate addresses. DCache and Write Buffer operations are closely connected as their configuration is set in each section by the page descriptor in the MMU translation table.

9.7.2.2 Write Buffer

The ARM926EJ-S contains a write buffer that has a 16-word data buffer and a four- address buf- fer. The write buffer is used for all writes to a bufferable region, write-through region and write- back region. It also allows to avoid stalling the processor when writes to external memory are performed. When a store occurs, data is written to the write buffer at core speed (high speed). The write buffer then completes the store to external memory at bus speed (typically slower than the core speed). During this time, the ARM9EJ-S processor can preform other tasks. DCache and Write Buffer support write-back and write-through memory regions, controlled by C and B bits in each section and page descriptor within the MMU translation tables.

9.7.2.3 Write-though Operation

When a cache write hit occurs, the DCache line is updated. The updated data is then written to the write buffer which transfers it to external memory. When a cache write miss occurs, a line, chosen by round robin or another algorithm, is stored in the write buffer which transfers it to external memory.

9.7.2.4 Write-back Operation

When a cache write hit occurs, the cache line or half line is marked as dirty, meaning that its contents are not up-to-date with those in the external memory. When a cache write miss occurs, a line, chosen by round robin or another algorithm, is stored in the write buffer which transfers it to external memory.

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9.8 Bus Interface Unit

The ARM926EJ-S features a Bus Interface Unit (BIU) that arbitrates and schedules AHB requests. The BIU implements a multi-layer AHB, based on the AHB-Lite protocol, that enables parallel access paths between multiple AHB masters and slaves in a system. This is achieved by using a more complex interconnection matrix and gives the benefit of increased overall bus bandwidth, and a more flexible system architecture. The multi-master bus architecture has a number of benefits:

  • It allows the development of multi-master systems with an increased bus bandwidth and a flexible architecture.
  • Each AHB layer becomes simple because it only has one master, so no arbitration or master- to-slave muxing is required. AHB layers, implementing AHB-Lite protocol, do not have to support request and grant, nor do they have to support retry and split transactions.
  • The arbitration becomes effective when more than one master wants to access the same slave simultaneously.

9.8.1 Supported Transfers

The ARM926EJ-S processor performs all AHB accesses as single word, bursts of four words, or bursts of eight words. Any ARM9EJ-S core request that is not 1, 4, 8 word s in size is split into packets of these sizes. Note that the Atmel ® bus is AHB-Lite protocol compliant, hence it does not support split and retry requests. Table 8 gives an overview of the supported transfers and different kinds of transactions they are used for.

9.8.2 Thumb Instruction Fetches

All instructions fetches, regardless of the state of ARM9EJ-S core, are made as 32-bit accesses on the AHB. If the ARM9EJ-S is in Thumb state, then two instructions can be fetched at a time.

9.8.3 Address Alignment

The ARM926EJ-S BIU performs address alignment checking and aligns AHB addresses to the necessary boundary. 16-bit accesses are aligned to halfword boundaries, and 32-bit accesses are aligned to word boundaries. Table 9-7. Supported Transfers HBurst[2:0] Description SINGLE Single transfer Single transfer of word, half word, or byte:

  • data write (NCNB, NCB, WT, or WB that has missed in DCache)
  • data read (NCNB or NCB)
  • NC instruction fetch (prefetched and non-prefetched)
  • page table walk read INCR4 Four-word incrementing burst Half-line cache write-back, Instruction prefetch, if enabled. Four-word burst NCNB, NCB, WT, or WB write. INCR8 Eight-word incrementing burst Full-line cache writ e-back, eight-word burst NCNB, NCB, WT, or WB write. WRAP8 Eight-word wrapping burst Cache linefill

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 10. Debug and Test

10.1 Description

The SAM9CN12 features a number of complementary debug and test capabilities. A common JTAG/ICE (In-Circuit Emulator) port is used for standard debugging functions, such as down- loading code and single-stepping through programs. The Debug Unit provides a two-pin UART that can be used to upload an application into internal SRAM. It manages the interrupt handling of the internal COMMTX and COMMRX signals that trace the activity of the Debug Communica- tion Channel. A set of dedicated debug and test input/output pins gives direct access to these capabilities from a PC-based test environment.

10.2 Embedded Characteristics

Debug capabilities can be forbidden with a fuse bit.

  • ARM926 Real-time In-circuit Emulator – Two real-time Watchpoint Units – Two Independent Registers: Debug Control Register and Debug Status Register – Test Access Port Accessible through JTAG Protocol – Debug Communications Channel
  • Debug Unit –T w o - p i n U A R T – Debug Communication Channel Interrupt Handling – Chip ID Register
  • IEEE1149.1 JTAG Boundary-scan on All Digital Pins.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

10.3 Block Diagram

Figure 10-1. Debug and Test Block Diagram ICE-RTARM9EJ-S DBGU PIO DRXD DTXD TMS TCK TDI JTAGSEL TDO Reset TAP: Test Access Port Boundary Port ICE/JTAG TAP ARM926EJ-S POR RTCK NTRST DMA

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

10.4 Application Examples

10.4.1 Debug Environment

Figure 10-2 on page 53 shows a complete debug environment example. The ICE/JTAG inter- face is used for standard debugging functions, such as downloading code and single-stepping through the program. A software debugger running on a personal computer provides the user interface for configuring a Trace Port interface utilizing the ICE/JTAG interface. Figure 10-2. Application Debug and Trace Environment Example AT91SAM9-based Application Board ICE /JT AG Interface Host Debugger ICE /JT AG C onnector AT91SAM9 Ter m i n alR S232 C onnector

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

10.4.2 Test Environment

Figure 10-3 on page 54 shows a test environment example. Test vectors are sent and inter- preted by the tester. In this example, the “board in test” is designed using a number of JTAG- compliant devices. These devices can be connected to form a single scan chain. Figure 10-3. Application Test Environment Example

10.5 Debug and Test Pin Description

AT91SAM9-based Application Board In T est AT91SAM9 Test Ad ap t o r Ch i p 2Ch i p n Ch i p 1 Test er Table 10-1. Debug and Test Pin List Pin Name Function Type Active Level Reset/Test NRST Microcontroller Reset Input/Output Low ICE and JTAG NTRST Test Reset Signal Input Low TCK Test Clock Input TDI Test Data In Input TDO Test Data Out Output TMS Test Mode Select Input RTCK Returned Test Clock Output JTAGSEL JTAG Selection Input Debug Unit DRXD Debug Receive Data Input DTXD Debug Transmit Data Output

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

10.6 Functional Description

10.6.1 EmbeddedICE

The ARM9EJ-S EmbeddedICE-RT ™ is supported via the ICE/JTAG port. It is connected to a host computer via an ICE interface. Debug support is implemented using an ARM9EJ-S core embedded within the ARM926EJ-S. The internal state of the ARM926EJ-S is examined through an ICE/JTAG port which allows instructions to be serially inserted into the pipeline of the core without using the external data bus. Therefore, when in debug state, a store-multiple (STM) can be inserted into the instruction pipeline. This exports the contents of the ARM9EJ-S registers. This data can be serially shifted out without affecting the rest of the system. There are two scan chains inside the ARM9EJ -S processor which support testing, debugging, and programming of the EmbeddedICE-RT. The scan chains are controlled by the ICE/JTAG port. EmbeddedICE mode is selected when JTAGSEL is low. It is not possible to switch directly between ICE and JTAG operations. A chip reset must be performed after JTAGSEL is changed. For further details on the EmbeddedICE-RT, see the ARM document: ARM9EJ-S Technical Reference Manual (DDI 0222A).

10.6.2 JTAG Signal Description

TMS is the Test Mode Select input which controls the transitions of the test interface state machine. TDI is the Test Data Input line which supplies the data to the JTAG registers (Boundary Scan Register, Instruction Register, or other data registers). TDO is the Test Data Output line which is used to serially output the data from the JTAG regis- ters to the equipment controlling the test. It carries the sampled values from the boundary scan chain (or other JTAG registers) and propagates them to the next chip in the serial test circuit. NTRST (optional in IEEE Standard 1149.1) is a Test-ReSeT input which is mandatory in ARM cores and used to reset the debug logic. On Atmel ARM926EJ-S-based cores, NTRST is a Power On Reset output. It is asserted on power on. If necessary, the user can also reset the debug logic with the NTRST pin assertion during 2.5 MCK periods. TCK is the Test ClocK input which enables the te st interface. TCK is pulsed by the equipment controlling the test and not by the tested device. It can be pulsed at any frequency. Note the maximum JTAG clock rate on ARM926EJ-S cores is 1/6th the clock of the CPU. This gives 5.45 kHz maximum initial JTAG clock rate for an ARM9E running from the 32.768 kHz slow clock. RTCK is the Return Test Clock. Not an IEEE Standard 1149.1 signal added for a better clock handling by emulators. From some ICE Interface probes, this return signal can be used to syn- chronize the TCK clock and take not care about the given ratio between the ICE Interface clock and system clock equal to 1/6th. This signal is only available in JTAG ICE Mode and not in boundary scan mode.

10.6.3 Debug Unit

The Debug Unit provides a two-pin (DXRD a nd TXRD) USART that can be used for several debug and trace purposes and offers an ideal means for in-situ programming solutions and debug monitor communication. Moreover, the association with two peripheral data controller channels permits packet handling of these tasks with processor time reduced to a minimum.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 The Debug Unit also manages the interrupt handling of the COMMTX and COMMRX signals that come from the ICE and that trace the activity of the Debug Communication Channel.The Debug Unit allows blockage of access to the system through the ICE interface. A specific register, the Debug Unit Chip ID Register, gives information about the product version and its internal configuration. For further details on the Debug Unit, see the Debug Unit section. 10.6.4 IEEE 1149.1 JTAG Boundary Scan IEEE 1149.1 JTAG Boundary Scan allows pin-level access independent of the device packaging technology. IEEE 1149.1 JTAG Boundary Scan is enabled when JTAGSEL is high. The SAMPLE, EXTEST and BYPASS functions are implemented. In ICE debug mode, the AR M processor responds with a non-JTAG chip ID that identifies the processor to the ICE system. This is not IEEE 1149.1 JTAG-compliant. It is not possible to switch directly between JTAG and ICE operations. A chip reset must be per- formed after JTAGSEL is changed. A Boundary-scan Descriptor Language (BSDL) file is provided to set up test.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

10.6.5 JTAG ID Code Register

Access: Read-only  VERSION[31:28]: Product Version Number Set to 0x0.  PART NUMBER[27:12]: Product Part Number Product part Number is 0x05B3  MANUFACTURER IDENTITY[11:1] Set to 0x01F. Bit[0] required by IEEE Std. 1149.1. Set to 0x1. JTAG ID Code value is 0x05B3_003F. 31 30 29 28 27 26 25 24 VERSION PART NUMBER 23 22 21 20 19 18 17 16 PART NUMBER 15 14 13 12 11 10 9 8 PART NUMBER MANUFACTURER IDENTITY 76543210 MANUFACTURER IDENTITY 1

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 11. Advanced Interrupt Controller (AIC)

11.1 Description

The Advanced Interrupt Controller (AIC) is an 8-level priority, individually maskable, vectored interrupt controller, providing handling of up to thirty-two interrupt sources. It is designed to sub- stantially reduce the software and real-time overhead in handling internal and external interrupts. The AIC drives the nFIQ (fast interrupt request) and the nIRQ (standard interrupt request) inputs of an ARM processor. Inputs of the AIC are either internal peripheral interrupts or external inter- rupts coming from the product's pins. The 8-level Priority Controller allows the user to define the priority for each interrupt source, thus permitting higher priority interrupts to be serviced even if a lower priority interrupt is being treated. Internal interrupt sources can be programmed to be level sensitive or edge triggered. External interrupt sources can be programmed to be positive-edge or negative-edge triggered or high- level or low-level sensitive. The fast forcing feature redirects any internal or external interrupt source to provide a fast inter- rupt rather than a normal interrupt.

11.2 Embedded Characteristics

  • Controls the Interrupt Lines (nIRQ and nFIQ) of an ARM ® Processor
  • Thirty-two Individually Maskable and Vectored Interrupt Sources – Source 0 is Reserved for the Fast Interrupt Input (FIQ) – Source 1 is Reserved for System Peripherals – Source 2 to Source 31 Control up to Thirty Embedded Peripheral Interrupts or External Interrupts – Programmable Edge-triggered or Level-sensitive Internal Sources – Programmable Positive/Negative Edge-triggered or High/Low Level-sensitive External Sources
  • 8-level Priority Controller – Drives the Normal Interrupt of the Processor – Handles Priority of the Interrupt Sources 1 to 31 – Higher Priority Interrupts Can Be Served During Service of Lower Priority Interrupt
  • Vectoring – Optimizes Interrupt Service Routine Branch and Execution – One 32-bit Vector Register per Interrupt Source – Interrupt Vector Register Reads the Corresponding Current Interrupt Vector
  • P r o t e c t M o d e – Easy Debugging by Preventing Automatic Operations when Protect Models Are Enabled
  • F a s t F o r c i n g – Permits Redirecting any Normal Interrupt Source to the Fast Interrupt of the Processor

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

  • General Interrupt Mask – Provides Processor Synchronization on Events Without Triggering an Interrupt
  • Write Protected Registers

11.3 Block Diagram

Figure 11-1. Block Diagram

11.4 Application Block Diagram

Figure 11-2. Description of the Application Block AIC APB ARM Processor FIQ IRQ0-IRQn Embedded PeripheralEE PeripheralEmbedded Peripheral Embedded Up to Thirty-two Sources nFIQ nIRQ Advanced Interrupt Controller Embedded Peripherals External Peripherals (External Interrupts) Standalone Applications RTOS Drivers Hard Real Time Tasks OS-based Applications OS Drivers General OS Interrupt Handler

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

11.5 AIC Detailed Block Diagram

Figure 11-3. AIC Detailed Block Diagram

11.6 I/O Line Description

11.7 Product Dependencies

11.7.1 I/O Lines

The interrupt signals FIQ and IRQ0 to IRQn are normally multiplexed through the PIO control- lers. Depending on the features of the PIO controller used in the product, the pins must be programmed in accordance with their assigned interrupt function. This is not applicable when the PIO controller used in the product is transparent on the input path.

11.7.2 Power Management

The Advanced Interrupt Controller is continuously clocked. The Power Management Controller has no effect on the Advanced Interrupt Controller behavior. The assertion of the Advanced Interrupt Controller outputs, either nIRQ or nFIQ, wakes up the ARM processor while it is in Idle Mode. The General Interrupt Mask feature enables the AIC to FIQ PIO Controller Advanced Interrupt Controller IRQ0-IRQn PIOIRQ Embedded Peripherals External Source Input Stage Internal Source Input Stage Fast Forcing Interrupt Priority Controller Fast Interrupt Controller ARM Processor nFIQ nIRQ Power Management Controller Wake UpUser Interface APB Processor Clock Table 11-1. I/O Line Description Pin Name Pin Description Type FIQ Fast Interrupt Input IRQ0 - IRQn Interrupt 0 - Interrupt n Input Table 11-2. I/O Lines Instance Signal I/O Line Peripheral AIC FIQ PC31 A AIC IRQ PB18 A

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 wake up the processor without asserting the interr upt line of the processor, thus providing syn- chronization of the processor on an event.

11.7.3 Interrupt Sources

The Interrupt Source 0 is always located at FIQ. If the product does not feature an FIQ pin, the Interrupt Source 0 cannot be used. The Interrupt Source 1 is always located at System Interrupt. This is the result of the OR-wiring of the system peripheral interrupt lines. When a system interrupt occurs, the service routine must first distinguish the cause of the interrupt . This is performed by reading successively the status registers of the above mentioned system peripherals. The interrupt sources 2 to 31 can either be connected to the interrupt outputs of an embedded user peripheral or to external interrupt lines. The external interrupt lines can be connected directly, or through the PIO Controller. The PIO Controllers are considered as user peripherals in the scope of interrupt handling. Accordingly, the PIO Controller interrupt lines are connected to the Interrupt Sources 2 to 31. The peripheral identification defined at the product level corresponds to the interrupt source number (as well as the bit number controlling the clock of the peripheral). Consequently, to sim- plify the description of the functional operations and the user interface, the interrupt sources are named FIQ, SYS, and PID2 to PID31.

11.8 Functional Description

11.8.1 Interrupt Source Control

11.8.1.1 Interrupt Source Mode

The Advanced Interrupt Controller independently programs each interrupt source. The SRC- TYPE field of the corresponding AIC_SMR (Source Mode Register) selects the interrupt condition of each source. The internal interrupt sources wired on the interrupt outputs of the embedded peripherals can be programmed either in level-sensitive mode or in edge-triggered mode. The active level of the internal interrupts is not important for the user. The external interrupt sources can be programmed either in high level-sensitive or low level-sen- sitive modes, or in positive edge-triggered or negative edge-triggered modes.

11.8.1.2 Interrupt Source Enabling

Each interrupt source, including the FIQ in source 0, can be enabled or disabled by using the command registers; AIC_IECR (Interrupt Enable Command Register) and AIC_IDCR (Interrupt Disable Command Register). This set of registers conducts enabling or disabling in one instruc- tion. The interrupt mask can be read in the AIC_IMR register. A disabled interrupt does not affect servicing of other interrupts.

11.8.1.3 Interrupt Clearing and Setting

All interrupt sources programmed to be edge-triggered (including the FIQ in source 0) can be individually set or cleared by writing respectively the AIC_ISCR and AIC_ICCR registers. Clear- ing or setting interrupt sources programmed in level-sensitive mode has no effect.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 The clear operation is perfunctory, as the softwa re must perform an acti on to reinitialize the “memorization” circuitry activated when the source is programmed in edge-triggered mode. However, the set operation is available for auto-test or software debug purposes. It can also be used to execute an AIC-implementation of a software interrupt. The AIC features an automatic clear of the current interrupt when the AIC_IVR (Interrupt Vector Register) is read. Only the interrupt source being detected by the AIC as the current interrupt is affected by this operation. ( See “Priority Controller” on page 65. ) The automatic clear reduces the operations required by the interrupt service routine entry code to reading the AIC_IVR. Note that the automatic interrupt clear is disabled if the interrupt source has the Fast Forcing feature enabled as it is considered uniquely as a FIQ source. (For further details, See “Fast Forcing” on page 69.) The automatic clear of the interrupt source 0 is performed when AIC_FVR is read.

11.8.1.4 Interrupt Status

For each interrupt, the AIC operation originates in AIC_IPR (Interrupt Pending Register) and its mask in AIC_IMR (Interrupt Mask Register). AIC_IPR enables the actual activity of the sources, whether masked or not. The AIC_ISR register reads the number of the current interrupt (see “Priority Controller” on page 65) and the register AIC_CISR gives an image of the signals nIRQ and nFIQ driven on the processor. Each status referred to above can be used to optimize the interrupt handling of the systems. Figure 11-4. Internal Interrupt Source Input Stage Edge Detector Clear Set Source i AIC_IPR AIC_IMR AIC_IECR AIC_IDCR AIC_ISCR AIC_ICCR Fast Interrupt Controller or Priority Controller FF Lev el/ Edge AIC_SMRI (SRCTYPE)

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Figure 11-5. External Interrupt Source Input Stage

11.8.2 Interrupt Latencies

Global interrupt latencies depend on several parameters, including:

  • The time the software masks the interrupts.
  • Occurrence, either at the processor level or at the AIC level.
  • The execution time of the instruction in progress when the interrupt occurs.
  • The treatment of higher priority interrupts and the resynchronization of the hardware signals. This section addresses only the hardware resync hronizations. It gives details of the latency times between the event on an external interrupt leading in a valid interrupt (edge or level) or the assertion of an internal interrupt source and the assertion of the nIRQ or nFIQ line on the pro- cessor. The resynchronization time depends on the programming of the interrupt source and on its type (internal or external). For the standard interrupt, resynchronization times are given assuming there is no higher priority in progress. The PIO Controller multiplexing has no effect on the interrupt latencies of the external interrupt sources. Figure 11-6. External Interrupt Edge Triggered Source Edge Detector ClearSet Pos./Neg. AIC_ISCR AIC_ICCR Source i FF Level/ Edge High/Low AIC_SMRi SRCTYPE AIC_IPR AIC_IMR AIC_IECR AIC_IDCR Fast Interrupt Controller or Priority Controller Maximum FIQ Latency = 4 Cycles Maximum IRQ Latency = 4 Cycles nFIQ nIRQ MCK IRQ or FIQ (Positive Edge) IRQ or FIQ (Negative Edge)

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Figure 11-7. External Interrupt Level Sensitive Source Figure 11-8. Internal Interrupt Edge Triggered Source Figure 11-9. Internal Interrupt Level Sensitive Source

11.8.3 Normal Interrupt

11.8.3.1 Priority Controller

An 8-level priority controller drives the nIRQ line of the processor, depending on the interrupt conditions occurring on the interrupt sources 1 to 31 (except for those programmed in Fast Forcing). Maximum IRQ Latency = 3 Cycles Maximum FIQ Latency = 3 cycles MCK IRQ or FIQ (High Level) IRQ or FIQ (Low Level) nIRQ nFIQ MCK nIRQ Peripheral Interrupt Becomes Active Maximum IRQ Latency = 4.5 Cycles MCK nIRQ Maximum IRQ Latency = 3.5 Cycles Peripheral Interrupt Becomes Active

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Each interrupt source has a programmable priority level of 7 to 0, which is user-definable by writ- ing the PRIOR field of the corresponding AIC_SMR (Source Mode Register). Level 7 is the highest priority and level 0 the lowest. As soon as an interrupt condition occurs, as defined by the SRCTYPE field of the AIC_SMR (Source Mode Register), the nIRQ line is asserted. As a new interrupt condition might have hap- pened on other interrupt sources since the nIRQ has been asserted, the priority controller determines the current interrupt at the time the AIC_IVR (Interrupt Vector Register) is read. The read of AIC_IVR is the entry point of the interrupt handling which allows the AIC to consider that the interrupt has been taken into account by the software. The current priority level is defined as the priority level of the current interrupt. If several interrupt sources of equal priority are pending and enabled when the AIC_IVR is read, the interrupt with the lowest interrupt source number is serviced first. The nIRQ line can be asserted only if an interrupt condition occurs on an interrupt source with a higher priority. If an interrupt condition happens (or is pending) during the interrupt treatment in progress, it is delayed until the software indicates to the AIC the end of the current service by writing the AIC_EOICR (End of Interrupt Command Register). The write of AIC_EOICR is the exit point of the interrupt handling.

11.8.3.2 Interrupt Nesting

The priority controller utilizes interrupt nesting in order for the high priority interrupt to be handled during the service of lower priori ty interrupts. This requires the interrupt service routines of the lower interrupts to re-enable the interrupt at the processor level. When an interrupt of a higher priority happens during an already occurring interrupt service rou- tine, the nIRQ line is re-asserted. If the interrupt is enabled at the core level, the current execution is interrupted and the new interrupt service routine should read the AIC_IVR. At this time, the current interrupt number and its priority level are pushed into an embedded hardware stack, so that they are saved and restored when the higher priority interrupt servicing is finished and the AIC_EOICR is written. The AIC is equipped with an 8-level wide hardware stack in order to support up to eight interrupt nestings pursuant to having eight priority levels.

11.8.3.3 Interrupt Vectoring

The interrupt handler addresses corresponding to each interrupt source can be stored in the reg- isters AIC_SVR1 to AIC_SVR31 (Source Vector Register 1 to 31). When the processor reads AIC_IVR (Interrupt Vector Register), the value written into AIC_SVR corresponding to the cur- rent interrupt is returned. This feature offers a way to branch in one single instruction to the handler corresponding to the current interrupt, as AIC_IVR is mapped at the absolute address 0xFFFF F100 and thus acces- sible from the ARM interrupt vector at address 0x0000 0018 through the following instruction: LDR PC,[PC,# -&F20] When the processor executes this instruction, it loads the read value in AIC_IVR in its program counter, thus branching the execution on the correct interrupt handler. This feature is often not used when the application is based on an operating system (either real time or not). Operating systems often have a single entry point for all the interrupts and the first task performed is to discern the source of the interrupt.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 However, it is strongly recommended to port the operating system on AT91 products by support- ing the interrupt vectoring. This can be performed by defining all the AIC_SVR of the interrupt source to be handled by the operating system at the address of its interrupt handler. When doing so, the interrupt vectoring permits a critical inte rrupt to transfer the execution on a specific very fast handler and not onto the operating system’s general interrupt handler. This facilitates the support of hard real-time tasks (input/outputs of voice/audio buffers and software peripheral han- dling) to be handled efficiently and independently of the application running under an operating system.

11.8.3.4 Interrupt Handlers

This section gives an overview of the fast interrupt handling sequence when using the AIC. It is assumed that the programmer understands the architecture of the ARM processor, and espe- cially the processor interrupt modes and the associated status bits. It is assumed that: 1. The Advanced Interrupt Controller has been programmed, AIC_SVR registers are loaded with corresponding interrupt service routine addresses and interrupts are enabled. 2. The instruction at the ARM interrupt exception vector address is required to work with the vectoring LDR PC, [PC, # -&F20] When nIRQ is asserted, if the bit “I” of CPSR is 0, the sequence is as follows: 1. The CPSR is stored in SPSR_irq, the current value of the Program Counter is loaded in the Interrupt link register (R14_irq) and the Program Counter (R15) is loaded with 0x18. In the following cycle during fetch at address 0x1C, the ARM core adjusts R14_irq, dec- rementing it by four. 2. The ARM core enters Interrupt mode, if it has not already done so. 3. When the instruction loaded at address 0x18 is executed, the program counter is loaded with the value read in AIC_IVR. Reading the AIC_IVR has the following effects: – Sets the current interrupt to be the pending and enabled interrupt with the highest priority. The current level is the priority level of the current interrupt. – De-asserts the nIRQ line on the processor. Even if vectoring is not used, AIC_IVR must be read in order to de-assert nIRQ. – Automatically clears the interrupt, if it has been programmed to be edge-triggered. – Pushes the current level and the current interrupt number on to the stack. – Returns the value written in the AIC_SVR corresponding to the current interrupt. 4. The previous step has the effect of branc hing to the corresponding interrupt service routine. This should start by saving the link register (R14_irq) and SPSR_IRQ. The link register must be decremented by four when it is saved if it is to be restored directly into the program counter at the end of the interrupt. For example, the instruction SUB PC, LR, #4 may be used. 5. Further interrupts can then be unmasked by clearing the “I” bit in CPSR, allowing re- assertion of the nIRQ to be taken into account by the core. This can happen if an inter- rupt with a higher priority than the current interrupt occurs. 6. The interrupt handler can th en proceed as required, saving the registers that will be used and restoring them at the end. During this phase, an interrupt of higher priority than the current level will restart the sequence from step 1.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Note: If the interrupt is programmed to be level sensitiv e, the source of the interrupt must be cleared dur- ing this phase. 7. The “I” bit in CPSR must be set in order to mask interrupts before exiting to ensure that the interrupt is completed in an orderly manner. 8. The End of Interrupt Command Register (AIC_EOICR) must be written in order to indi- cate to the AIC that the current interrupt is finished. This causes the current level to be popped from the stack, restoring the previous current level if one exists on the stack. If another interrupt is pending, with lower or equal priority than the old current level but with higher priority than the new current level, the nIRQ line is re-asserted, but the inter- rupt sequence does not immediately start because the “I” bit is set in the core. SPSR_irq is restored. Finally, the saved value of the link register is restored directly into the PC. This has the effect of returning from the interrupt to whatever was being exe- cuted before, and of loading the CPSR with the stored SPSR, masking or unmasking the interrupts depending on the state saved in SPSR_irq. Note: The “I” bit in SPSR is significant. If it is set, it indicates that the ARM core was on the verge of masking an interrupt when the mask instruction was interrupted. Hence, when SPSR is restored, the mask instruction is completed (interrupt is masked).

11.8.4 Fast Interrupt

11.8.4.1 Fast Interrupt Source

The interrupt source 0 is the only source which can raise a fast interrupt request to the processor except if fast forcing is used. The interrupt so urce 0 is generally connected to a FIQ pin of the product, either directly or through a PIO Controller.

11.8.4.2 Fast Interrupt Control

The fast interrupt logic of the AIC has no priority controller. The mode of interrupt source 0 is programmed with the AIC_SMR0 and the field PRIOR of this register is not used even if it reads what has been written. The fi eld SRCTYPE of AIC_SMR0 enables programming the fast inter- rupt source to be positive-edge triggered or negative-edge triggered or high-level sensitive or low-level sensitive Writing 0x1 in the AIC_IECR (Interrupt Enable Command Register) and AIC_IDCR (Interrupt Disable Command Register) respectively enables and disables the fast interrupt. The bit 0 of AIC_IMR (Interrupt Mask Register) indicates whether the fast interrupt is enabled or disabled.

11.8.4.3 Fast Interrupt Vectoring

The fast interrupt handler address can be stor ed in AIC_SVR0 (Source Vector Register 0). The value written into this register is returned when the processor reads AIC_FVR (Fast Vector Reg- ister). This offers a way to branch in one single instruction to the interrupt handler, as AIC_FVR is mapped at the absolute address 0xFFFF F104 and thus accessible from the ARM fast inter- rupt vector at address 0x0000 001C through the following instruction: LDR PC,[PC,# -&F20] When the processor executes this instruction it loads the value read in AIC_FVR in its program counter, thus branching the execution on the fast interrupt handler. It also automatically per- forms the clear of the fast interrupt source if it is programmed in edge-triggered mode.

11.8.4.4 Fast Interrupt Handlers

This section gives an overview of the fast interrupt handling sequence when using the AIC. It is assumed that the programmer understands the architecture of the ARM processor, and espe- cially the processor interrupt modes and associated status bits.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Assuming that: 1. The Advanced Interrupt Controller has been programmed, AIC_SVR0 is loaded with the fast interrupt service routine address, and the interrupt source 0 is enabled. 2. The Instruction at address 0x1C (FIQ exception vector address) is required to vector the fast interrupt: LDR PC, [PC, # -&F20] 3. The user does not need nested fast interrupts. When nFIQ is asserted, if the bit “F” of CPSR is 0, the sequence is: 1. The CPSR is stored in SPSR_fiq, the current value of the program counter is loaded in the FIQ link register (R14_FIQ) and the program counter (R15) is loaded with 0x1C. In the following cycle, during fetch at address 0x20, the ARM core adjusts R14_fiq, decre- menting it by four. 2. The ARM core enters FIQ mode. 3. When the instruction loaded at address 0x1C is executed, the program counter is loaded with the value read in AIC_FVR. Reading the AIC_FVR has effect of automati- cally clearing the fast interrupt, if it has been programmed to be edge triggered. In this case only, it de-asserts the nFIQ line on the processor. 4. The previous step enables branching to the corresponding interrupt service routine. It is not necessary to save the link register R14_fiq and SPSR_fiq if nested fast interrupts are not needed. 5. The Interrupt Handler can then proceed as required. It is not necessary to save regis- ters R8 to R13 because FIQ mode has its own dedicated registers and the user R8 to R13 are banked. The other registers, R0 to R7, must be saved before being used, and restored at the end (before the next step). Note that if the fast interrupt is programmed to be level sensitive, the source of the interrupt must be cleared during this phase in order to de-assert the interrupt source 0. 6. Finally, the Link Register R14_fiq is restored into the PC after decrementing it by four (with instruction SUB PC, LR, #4 for example). This has the effect of returning from the interrupt to whatever was being executed before, loading the CPSR with the SPSR and masking or unmasking the fast interrupt depending on the state saved in the SPSR. Note: The “F” bit in SPSR is significant. If it is set, it indicates that the ARM core was just about to mask FIQ interrupts when the mask instruction was interrupted. Hence when the SPSR is restored, the interrupted instruction is completed (FIQ is masked). Another way to handle the fast interrupt is to map the interrupt service routine at the address of the ARM vector 0x1C. This method does not use the vectoring, so that reading AIC_FVR must be performed at the very beginning of the handler operation. However, this method saves the execution of a branch instruction.

11.8.4.5 Fast Forcing

The Fast Forcing feature of the advanced interrupt controller provides redirection of any normal Interrupt source on the fast interrupt controller. Fast Forcing is enabled or disabl ed by writing to the Fast Forcing Enable Register (AIC_FFER) and the Fast Forcing Disable Register (AIC_FF DR). Writing to these registers results in an update of the Fast Forcing Status Register (AIC_FFSR) that controls the feature for each inter- nal or external interrupt source. When Fast Forcing is disabled, the interrupt sources are handled as described in the previous pages.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 When Fast Forcing is enabled, the edge/level programming and, in certain cases, edge detec- tion of the interrupt s ource is still active but the source c annot trigger a normal interrupt to the processor and is not seen by the priority handler. If the interrupt source is programmed in level- sensitive mode and an active level is sampled, Fast Forcing results in the assertion of the nFIQ line to the core. If the interrupt source is programmed in edge-triggered mode and an active edge is detected, Fast Forcing results in the assertion of the nFIQ line to the core. The Fast Forcing feature does not affect the Source 0 pending bit in the Interrupt Pending Reg- ister (AIC_IPR). The FIQ Vector Register (AIC_FVR) reads the contents of the Source Vector Register 0 (AIC_SVR0), whatever the source of the fast interrupt may be. The read of the FVR does not clear the Source 0 when the fast forcing feature is used and the interrupt source should be cleared by writing to the Interrupt Clear Command Register (AIC_ICCR). All enabled and pending interrupt sources that have the fast forcing feature enabled and that are programmed in edge-triggered mode must be cleared by writing to the Interrupt Clear Command Register. In doing so, they are cleared independently and thus lost interrupts are prevented. The read of AIC_IVR does not clear the source that has the fast forcing feature enabled. The source 0, reserved to the fast interrupt, continues operating normally and becomes one of the Fast Interrupt sources. Figure 11-10. Fast Forcing

11.8.5 Protect Mode

The Protect Mode permits reading the Interrupt Vector Register without performing the associ- ated automatic operations. This is necessary when working with a debug system. When a debugger, working either with a Debug Monitor or the ARM processor's ICE, stops the applica- tions and updates the opened windows, it might read the AIC User Interface and thus the IVR. This has undesirable consequences:

  • If an enabled interrupt with a higher priority than the current one is pending, it is stacked.
  • If there is no enabled pending interrupt, the spurious vector is returned. Source 0 _ FIQ Input Stage Automatic Clear Input Stage Automatic Clear Source n AIC_IPR AIC_IMR AIC_FFSR AIC_IPR AIC_IMR Priority Manager nFIQ nIRQ Read IVR if Source n is the current interrupt and if Fast Forcing is disabled on Source n. Read FVR if Fast Forcing is disabled on Sources 1 to 31.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 In either case, an End of Interrupt command is necessary to acknowledge and to restore the context of the AIC. This operation is generally not performed by the debug system as the debug system would become strongly intrusive and cause the application to enter an undesired state. This is avoided by using the Protect Mode. Writing PROT in AIC_DCR (Debug Control Register) at 0x1 enables the Protect Mode. When the Protect Mode is enabled, the AIC performs interrupt stacking only when a write access is performed on the AIC_IVR. Therefore, the Interrupt Service Routines must write (arbitrary data) to the AIC_IVR just after reading it. The new context of the AIC, including the value of the Interrupt Status Register (AIC_ISR), is updated with the current interrupt only when AIC_IVR is written. An AIC_IVR read on its own (e.g., by a debugger), modifies neither the AIC context nor the AIC_ISR. Extra AIC_IVR reads perform the same operations. However, it is recommended to not stop the processor between the read and the write of AIC_IVR of the interrupt service routine to make sure the debugger does not modify the AIC context. To summarize, in normal operating mode, the read of AIC_IVR performs the following opera- tions within the AIC: 1. Calculates active interrupt (higher than current or spurious). 2. Determines and returns the vector of the active interrupt. 3. Memorizes the interrupt. 4. Pushes the current priority level onto the internal stack. 5. Acknowledges the interrupt. However, while the Protect Mode is activated, only operations 1 to 3 are performed when AIC_IVR is read. Operations 4 and 5 are only performed by the AIC when AIC_IVR is written. Software that has been written and debugged using the Protect Mode runs correctly in Normal Mode without modification. However, in Normal Mode the AIC_IVR write has no effect and can be removed to optimize the code.

11.8.6 Spurious Interrupt

The Advanced Interrupt Controller features protection against spurious interrupts. A spurious interrupt is defined as being the assertion of an interrupt source long enough for the AIC to assert the nIRQ, but no longer present when AIC_IVR is read. This is most prone to occur when:

  • An external interrupt source is programmed in level-sensitive mode and an active level occurs for only a short time.
  • An internal interrupt source is programmed in level sensitive and the output signal of the corresponding embedded peripheral is activated for a short time. (As in the case for the Watchdog.)
  • An interrupt occurs just a few cycles before the software begins to mask it, thus resulting in a pulse on the interrupt source. The AIC detects a spurious interrupt at the time the AIC_IVR is read while no enabled interrupt source is pending. When this happens, the AIC returns the value stored by the programmer in AIC_SPU (Spurious Vector Register). The pr ogrammer must store the address of a spurious interrupt handler in AIC_SPU as part of the application, to enable an as fast as possible return to the normal execution flow. This handler writes in AIC_EOICR and performs a return from interrupt.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

11.8.7 General Interrupt Mask

The AIC features a General Interrupt Mask bit to prevent interrupts from reaching the processor. Both the nIRQ and the nFIQ lines are driven to their inactive state if the bit GMSK in AIC_DCR (Debug Control Register) is set. However, this mask does not prevent waking up the processor if it has entered Idle Mode. This function facilitates synchronizing the processor on a next event and, as soon as the event occurs, performs subsequent operations without having to handle an interrupt. It is strongly recommended to use this mask with caution.

11.9 Write Protection Registers

To prevent any single software error that may corrupt AIC behavior, the registers listed below can be write-protected by setting the WPEN bit in the AIC Write Protect Mode Register (AIC_WPMR). If a write access in a write- protected register is detected, then the WPVS flag in the AIC Write Protect Status Register (AIC_WPSR) is set and the WPVSRC fi eld indicates in which register the write access has been attempted. The WPVS flag is automatically reset after reading the AIC Write Protect Status Register. The protected registers are:

  • “AIC Source Mode Register” on page 74
  • “AIC Source Vector Register” on page 75
  • “AIC Spurious Interrupt Vector Register” on page 87
  • “AIC Debug Control Register” on page 88

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

11.10 Advanced Interrupt Controller (AIC) User Interface

11.10.1 Base Address

The AIC is mapped at the address 0xFFFF F000. It has a total 4-Kbyte addressing space. This permits the vectoring fea- ture, as the PC-relative load/store instructions of the ARM processor support only a ± 4-Kbyte offset. Notes: 1. The reset value of this register depends on the level of the external interrupt source. All other sources are cleared at reset, thus not pending. 3. Values in the Version Register vary with the version of the IP block implementation. Table 11-3. Register Mapping Offset Register Name Access Reset 0x00 Source Mode Register 0 AIC_SMR0 Read-write 0x0 0x04 Source Mode Register 1 AIC_SMR1 Read-write 0x0 0x7C Source Mode Register 31 AIC_SMR31 Read-write 0x0 0x80 Source Vector Register 0 AIC_SVR0 Read-write 0x0 0x84 Source Vector Register 1 AIC_SVR1 Read-write 0x0 0xFC Source Vector Register 31 AIC_SVR31 Read-write 0x0 0x100 Interrupt Vector Register AIC_IVR Read-only 0x0 0x104 FIQ Interrupt Vector Register AIC_FVR Read-only 0x0 0x108 Interrupt Status Register AIC_ISR Read-only 0x0 0x10C Interrupt Pending Register(2) AIC_IPR Read-only 0x0 (1) 0x110 Interrupt Mask Register(2) AIC_IMR Read-only 0x0 0x114 Core Interrupt Status Register AIC_CISR Read-only 0x0 0x118 - 0x11C Reserved --- --- --- 0x120 Interrupt Enable Command Register (2) AIC_IECR Write-only --- 0x124 Interrupt Disable Command Register (2) AIC_IDCR Write-only --- 0x128 Interrupt Clear Command Register(2) AIC_ICCR Write-only --- 0x12C Interrupt Set Command Register(2) AIC_ISCR Write-only --- 0x130 End of Interrupt Command Register AIC_EOICR Write-only --- 0x134 Spurious Interrupt Vector Register AIC_SPU Read-write 0x0 0x138 Debug Control Register AIC_DCR Read-write 0x0 0x13C Reserved --- --- --- 0x140 Fast Forcing Enable Register (2) AIC_FFER Write-only --- 0x144 Fast Forcing Disable Register (2) AIC_FFDR Write-only --- 0x148 Fast Forcing Status Register(2) AIC_FFSR Read-only 0x0 0x14C - 0x1E0 Reserved --- --- --- 0x1E4 Write Protect Mode Register AIC_WPMR Read-write 0x0 0x1E8 Write Protect Status Register AIC_WPSR Read-only 0x0 0x1EC - 0x1FC Reserved

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

11.10.2 AIC Source Mode Register

Name: AIC_SMR0..AIC_SMR31 Address: 0xFFFFF000 Access Read-write Reset: 0x0 This register can only be written if the WPEN bit is cleared in AIC Write Protect Mode Register  PRIOR: Priority Level The priority level is programmable from 0 (lowest priority) to 7 (highest priority). The priority level is not used for the FIQ in the related SMR register AIC_SMR0.  SRCTYPE: Interrupt Source Type The active level or edge is not programmable for the internal interrupt sources. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 – SRCTYPE – – PRIOR Value Name Description 0x0 INT_LEVEL_SENSITIVE High level Sensitive for internal source Low level Sensitive for external source 0x1 INT_EDGE_TRIGGERED Positive edge triggered for internal source Negative edge triggered for external source 0x2 EXT_HIGH_LEVEL High level Sensitive for internal source High level Sensitive for external source 0x3 EXT_POSITIVE_EDGE Positive edge triggered for internal source Positive edge triggered for external source

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

11.10.3 AIC Source Vector Register

Name: AIC_SVR0..AIC_SVR31 Address: 0xFFFFF080 Access: Read-write Reset: 0x0 This register can only be written if the WPEN bit is cleared in AIC Write Protect Mode Register  VECTOR: Source Vector The user may store in these registers the addresses of the corresponding handler for each interrupt source. 31 30 29 28 27 26 25 24 VECTOR 23 22 21 20 19 18 17 16 VECTOR 15 14 13 12 11 10 9 8 VECTOR 76543210 VECTOR

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

11.10.4 AIC Interrupt Vector Register

Name: AIC_IVR Address: 0xFFFFF100 Access: Read-only Reset: 0x0  IRQV: Interrupt Vector Register The Interrupt Vector Register contains the vector programmed by the user in the Source Vector Register corresponding to the current interrupt. The Source Vector Register is indexed using the current interrupt number when the Interrupt Vector Register is read. When there is no current interrupt, the Interrupt Vector Register reads the value stored in AIC_SPU. 31 30 29 28 27 26 25 24 IRQV 23 22 21 20 19 18 17 16 IRQV 15 14 13 12 11 10 9 8 IRQV 76543210 IRQV

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

11.10.5 AIC FIQ Vector Register

Name: AIC_FVR Address: 0xFFFFF104 Access: Read-only Reset: 0x0  FIQV: FIQ Vector Register The FIQ Vector Register contains the vector programmed by the user in the Source Vector Register 0. When there is no fast interrupt, the FIQ Vector Register reads the value stored in AIC_SPU. 31 30 29 28 27 26 25 24 FIQV 23 22 21 20 19 18 17 16 FIQV 15 14 13 12 11 10 9 8 FIQV 76543210 FIQV

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

11.10.6 AIC Interrupt Status Register

Name: AIC_ISR Address: 0xFFFFF108 Access: Read-only Reset: 0x0  IRQID: Current Interrupt Identifier The Interrupt Status Register returns the current interrupt source number. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 ––– IRQID

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

11.10.7 AIC Interrupt Pending Register

Name: AIC_IPR Address: 0xFFFFF10C Access: Read-only Reset: 0x0  FIQ, SYS, PID2-PID31: Interrupt Pending 0 = Corresponding interrupt is not pending. 1 = Corresponding interrupt is pending. 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 76543210 PID7 PID6 PID5 PID4 PID3 PID2 SYS FIQ

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

11.10.8 AIC Interrupt Mask Register

Name: AIC_IMR Address: 0xFFFFF110 Access: Read-only Reset: 0x0  FIQ, SYS, PID2-PID31: Interrupt Mask 0 = Corresponding interrupt is disabled. 1 = Corresponding interrupt is enabled. 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 76543210 PID7 PID6 PID5 PID4 PID3 PID2 SYS FIQ

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

11.10.9 AIC Core Interrupt Status Register

Name: AIC_CISR Address: 0xFFFFF114 Access: Read-only Reset: 0x0  NFIQ: NFIQ Status 0 = nFIQ line is deactivated. 1 = nFIQ line is active.  NIRQ: NIRQ Status 0 = nIRQ line is deactivated. 1 = nIRQ line is active. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

11.10.10 AIC Interrupt Enable Command Register

Name: AIC_IECR Address: 0xFFFFF120 Access: Write-only  FIQ, SYS, PID2-PID31: Interrupt Enable 0 = No effect. 1 = Enables corresponding interrupt. 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 76543210 PID7 PID6 PID5 PID4 PID3 PID2 SYS FIQ

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

11.10.11 AIC Interrupt Disable Command Register

Name: AIC_IDCR Address: 0xFFFFF124 Access: Write-only  FIQ, SYS, PID2-PID31: Interrupt Disable 0 = No effect. 1 = Disables corresponding interrupt. 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 76543210 PID7 PID6 PID5 PID4 PID3 PID2 SYS FIQ

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

11.10.12 AIC Interrupt Clear Command Register

Name: AIC_ICCR Address: 0xFFFFF128 Access: Write-only  FIQ, SYS, PID2-PID31: Interrupt Clear 0 = No effect. 1 = Clears corresponding interrupt. 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 76543210 PID7 PID6 PID5 PID4 PID3 PID2 SYS FIQ

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

11.10.13 AIC Interrupt Set Command Register

Name: AIC_ISCR Address: 0xFFFFF12C Access: Write-only  FIQ, SYS, PID2-PID31: Interrupt Set 0 = No effect. 1 = Sets corresponding interrupt. 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 76543210 PID7 PID6 PID5 PID4 PID3 PID2 SYS FIQ

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

11.10.14 AIC End of Interrupt Command Register

Name: AIC_EOICR Address: 0xFFFFF130 Access: Write-only The End of Interrupt Command Register is used by the interrupt routine to indicate that the interrupt treatment is complete. Any value can be written because it is only necessary to make a write to this register location to signal the end of interrupt treatment. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

11.10.15 AIC Spurious Interrupt Vector Register

Name: AIC_SPU Address: 0xFFFFF134 Access: Read-write Reset: 0x0 This register can only be written if the WPEN bit is cleared in AIC Write Protect Mode Register  SIVR: Spurious Interrupt Vector Register The user may store the address of a spurious interrupt handler in this register. The written value is returned in AIC_IVR in case of a spurious interrupt and in AIC_FVR in case of a spurious fast interrupt. 31 30 29 28 27 26 25 24 SIVR 23 22 21 20 19 18 17 16 SIVR 15 14 13 12 11 10 9 8 SIVR 76543210 SIVR

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

11.10.16 AIC Debug Control Register

Name: AIC_DCR Address: 0xFFFFF138 Access: Read-write Reset: 0x0 This register can only be written if the WPEN bit is cleared in AIC Write Protect Mode Register  PROT: Protection Mode 0 = The Protection Mode is disabled. 1 = The Protection Mode is enabled.  GMSK: General Mask 0 = The nIRQ and nFIQ lines are normally controlled by the AIC. 1 = The nIRQ and nFIQ lines are tied to their inactive state. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

11.10.17 AIC Fast Forcing Enable Register

Name: AIC_FFER Address: 0xFFFFF140 Access: Write-only  SYS, PID2-PID31: Fast Forcing Enable 0 = No effect. 1 = Enables the fast forcing feature on the corresponding interrupt. 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 76543210 PID7 PID6 PID5 PID4 PID3 PID2 SYS –

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

11.10.18 AIC Fast Forcing Disable Register

Name: AIC_FFDR Address: 0xFFFFF144 Access: Write-only  SYS, PID2-PID31: Fast Forcing Disable 0 = No effect. 1 = Disables the Fast Forcing feature on the corresponding interrupt. 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 76543210 PID7 PID6 PID5 PID4 PID3 PID2 SYS –

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

11.10.19 AIC Fast Forcing Status Register

Name: AIC_FFSR Address: 0xFFFFF148 Access: Read-only  SYS, PID2-PID31: Fast Forcing Status 0 = The Fast Forcing feature is disabled on the corresponding interrupt. 1 = The Fast Forcing feature is enabled on the corresponding interrupt. 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 76543210 PID7 PID6 PID5 PID4 PID3 PID2 SYS –

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

11.10.20 AIC Write Protect Mode Register

Name: AIC_WPMR Address: 0xFFFFF1E4 Access: Read-write Reset: See Table 11-3  WPEN: Write Protect Enable 0 = Disables the Write Protect if WPKEY corresponds to 0x414943 ("AIC" in ASCII). 1 = Enables the Write Protect if WPKEY corresponds to 0x414943 ("AIC" in ASCII). Protects the registers:

  • “AIC Source Mode Register” on page 74
  • “AIC Source Vector Register” on page 75
  • “AIC Spurious Interrupt Vector Register” on page 87
  • “AIC Debug Control Register” on page 88  WPKEY: Write Protect KEY Should be written at value 0x414943 ("AIC" in ASCII). Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. 31 30 29 28 27 26 25 24 WPKEY 23 22 21 20 19 18 17 16 WPKEY 15 14 13 12 11 10 9 8 WPKEY 76543210

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

11.10.21 AIC Write Protect Status Register

Name: AIC_WPSR Address: 0xFFFFF1E8 Access: Read-only Reset: See Table 11-3  WPVS: Write Protect Violation Status 0 = No Write Protect Violation has occurred since the last read of the AIC_WPSR register. 1 = A Write Protect Violation has occurred since the last read of the AIC_WPSR register. If this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field WPVSRC.  WPVSRC: Write Protect Violation Source When WPVS is active, this field indicates the write-protected register (t hrough address offset or code) in which a write access has been attempted. Note: Reading AIC_WPSR automatically clears all fields. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WPVSRC 15 14 13 12 11 10 9 8 WPVSRC 76543210

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 12. Boot Strategies 12.1 12.1 SAM9CN12 only The SAM9CN12 embeds a Secure Boot allowing firmware stored in external Non-Volatile Mem- ory to be protected. The content of the external NVM is encrypted and signed base d using a 256-bit AES algorithm. Prior to booting from the externally stored firmware, the secure boot will authenticate the firm- ware, decrypt it and store it in on-chip memory. Access to the on-chip memory is prevented and the maximum size of the firmware should not exceed 24 kB. The programming of the external memory can only be done by the SAM9CN12 using a unique key stored in the on-chip OTP memory. Herewith the software is uniquely linked to each SAM9CN12 device. A direct copy of the NVM memory will not run on another SAM9CN12 devic e, improving the firmware protection even further. For software development the user should use the SAM9CN11 without secure boot and full access to on-chip memory for debug. Once the firmware development has been completed, the SAM9CN11 should be replaced by the SAM9CN12 and programmed via USB with Secure SAM- BA. Refer to the Secured Application Note "Secure Boot on SAM9CN12" for more details (NDA required). 12.2 12.2 SAM9CN11 and SAM9N12 only The system always boots at address 0x0. To ensure maximum boot possibilities, the memory layout can be changed thanks to the BMS pin. This allows the user to layout the ROM or an external memory to 0x0. The sampling of the BMS pin is done at reset. If BMS is detected at 0 , the controller boots on the memory connected to Chip Select 0 of the External Bus Interface. In this boot mode, the chip starts with its default parameters (all registers in their reset state), including as follows:

  • the main clock is the on-chip 12 MHz RC oscillator
  • the Static Memory Controller is configured with its default parameters The user software in the external memory performs a complete configuration:
  • Enable the 32,768 Hz oscillator if best accuracy is needed
  • Program the PMC (main oscillator enable or bypass mode)
  • Program and start the PLL
  • Reprogram the SMC setup, cycle, hold, mode timing registers for EBI CS0, to adapt them to the new clock
  • Switch the system clock to the new value If BMS is detected at 1 , the boot memory is the embedded ROM and the Boot Program described below is executed. (Section 12.2.1 “ROM Code”)

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

12.2.1 ROM Code

The ROM Code is a boot program contained in the embedded ROM. It is also called “First level bootloader”. The ROM Code performs several steps:

  • basic chip initialization: XTal or external clock frequency detection
  • attempt to retrieve a valid code from external non-volatile memories (NVM)
  • execution of a monitor called SAM-BA® Monitor, in case no valid application has been found on any NVM

12.2.2 Flow Diagram

The ROM Code implements the algorithm shown below in Figure 12-1. Figure 12-1. ROM Code Algorithm Flow Diagram

12.2.3 Chip Setup

At boot start-up, the processor clock (PCK) and the master clock (MCK) source is the 12 MHz Fast RC Oscillator. Initialization follows the steps described below: 1. Stack setup for ARM supervisor mode. 2. Main Oscillator Detection: the Main Clock is switched to the 32 kHz RC oscillator to allow external clock frequency to be measured. Then the Main Oscillator is enabled and set in bypass mode. If the MOSCSELS bit rises, an external clock is connected, and the next step is Main Clock Selection (3). If not, the bypass mode is cleared to attempt external quartz detection. This detection is successful when the MOSCXTS and MOSCSELS bits rise, else the 12 MHz Fast RC internal oscillator is used as the Main Clock. 3. Main Clock Selection: the Master Clock source is switched from the Slow Clock to the Main Oscillator without prescaler. The PMC Status Register is polled to wait for MCK Ready. PCK and MCK are now the Main Clock. 4. C variable initialization: non zero-initialized data is initialized in the RAM (copy from ROM to RAM). Zero-initialized data is set to 0 in the RAM. SAM-BA Monitor Copy and run it in internal SRAM Ye s Chip Setup Valid boot code found in one NVM No

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 5. PLLA initialization: PLLA is configured to get a PCK at 48 MHz and an MCK at 48 MHz. If an external clock or crystal frequency running at 12 MHz is found, then the PLLA is configured to allow communication on the USB link for the SAM-BA Monitor; else the Main Clock is switched to the internal 12 MHz Fast RC, but USB will not be activated. Providing a clock frequency not at 12 MHz but between 4 and 28 MHz will be considered by the ROM Code as 12 MHz, and PLL settings will be configured accordingly.

12.2.4 NVM Boot

12.2.4.1 NVM Boot Sequence

The boot sequence on external memory devices can be controlled using the Boot Sequence Register (BSCR). The 3 LSBs of the BSCR are available to control the sequence. The user can then choose to bypass some steps shown in Figure 12-2 “NVM Bootloader Sequence Diagram” according to the BSCR Value. Table 12-1. External Clock and Crystal frequencies allowed for Boot Sequence (in MHz) ≤ 41 2 ≥ 28 Boot on external memories Y es Y es Y es SAM-BA Monitor through DBGU Y es Y es Y es SAM-BA Monitor through USB No Y es No Table 12-2. Boot Sequence Register Values BSCR Value SPI0 NPCS0 SDCard NAND Flash SPI0 NPCS1 TWI EEPROM SAM-BA Monitor 0Y Y Y Y Y Y 1Y - Y Y Y Y 2Y - - Y Y Y 3Y - - Y Y Y 4Y - -- Y Y 5- - - - - Y 6- - - - - Y 7- - - - - Y

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Figure 12-2. NVM Bootloader Sequence Diagram S PI0 C S 0 F lash Boot S PI0 C S 1 F lash Boot Ye s Ye s TWI EEPROM Bo o t Ye s NAND Flash Boot Co p y f r o m NAND Flash to SRAM Ru n Ye s NAND Flash Bootloader No S D C ard Boot Co p y f r o m SD Car d t o SRAM Ru n Ye s S D C ard Bootloader No Device Set u p No No SAM - BA Monitor Co p y f r o m SPI Fl ash t o SRAM Co p y f r o m SPI Fl ash t o SRAM SPI Flash Bootloader SPI Flash Bootloader Ru n Ru n No Co p y f r o m TWI EEPROM t o SRAM TWI EEPROM BootloaderRu n

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

12.2.4.2 NVM Bootloader Program Description

Figure 12-3. NVM Bootloader Program Diagram The NVM bootloader program first initializes the PIOs related to the NVM device. Then it config- ures the right peripheral depending on the NVM and tries to access this memory. If the initialization fails, it restores the reset values for the PIO and the peripheral and then tries the same operations on the next NVM of the sequence. If the initialization is successful, the NVM bootloader program reads the beginning of the NVM and determines if the NVM contains valid code. If the NVM does not contain valid code, the NVM bootloader program restores the reset value for the peripherals and then tries the same operations on the next NVM of the sequence. En d V alid code detection in NVM Ye s C opy the valid code from external NV M to internal S R AM. Restore the reset values for the peripherals. P erform the R E MAP and s et the P C to 0 to jump to the downloaded application Initialize NVM NVM contains valid code Ye s St ar t Initialization OK ? Restore the reset values for the peripherals and Jump to next boot solution No No

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 If valid code is found, this code is loaded from NVM into internal SRAM and executed by branch- ing at address 0x0000_0000 after remap. This code may be the application code or a second- level bootloader. All the calls to functions are PC relative and do not use absolute addresses. Figure 12-4. Remap Action after Download Completion

12.2.4.3 Valid Code Detection

There are two kinds of valid code detection. ARM Exception Vectors Check The NVM bootloader program reads and analyzes the first 28 bytes corresponding to the first seven ARM exception vectors. Except for the sixth vector, these bytes must implement the ARM instructions for either branch or load PC with PC relative addressing. Figure 12-5. LDR Opcode Figure 12-6. B Opcode Unconditional instruction: 0xE for bits 31 to 28 Load PC with PC relative addressing instruction: – Rn = Rd = PC = 0xF – I==0 (12-bit immediate value) – P==1 (pre-indexed) – U offset added (U==1) or subtracted (U==0) –W = = 1 REMAP Internal ROM Internal ROM 0x0010_0000 0x0000_0000 Internal SRAM 0x0030_0000 Internal SRAM Internal ROM 0x0010_0000 0x0000_0000 Internal SRAM 0x0030_0000 31 28 27 24 23 20 19 16 15 12 11 0

111001 IP U1 W 0 R n R d O s e t

11101010 O s e t ( 2 4 b i t s )

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 The sixth vector, at offset 0x14, contains the size of the image to download. The user must replace this vector with the user’s own vector. This information is described below. Figure 12-7. Structure of the ARM Vector 6 The value has to be smaller than 24 kbytes. This size is the internal SRAM size minus the stack size used by the ROM Code at the end of the internal SRAM. Example An example of valid vectors follows: 00 ea000006 B 0x20 04 eafffffe B 0x04 08 ea00002f B _main 0c eafffffe B 0x0c 10 eafffffe B 0x10 14 00001234 B 0x14 <- Code size = 4660 bytes 18 eafffffe B 0x18 boot.bin File Check This method is the one used on FAT formatted SDCard. The boot program must be a file named “boot.bin” written in the root directory of the file system. Its size must not exceed the maxi- mum size allowed: 24 kbytes (0x6000).

12.2.4.4 Detailed Memory Boot Procedures

NAND Flash Boot: NAND Flash Detection After NAND Flash interface configuration, a reset command is sent to the memory. The Boot Program first tries to find valid software on a NAND Flash device connected to EBI CS3, with data lines connected to D0-D7, then on NAND Flash connected to D16-D23. Hardware ECC detection and correction are provided by the PMECC peripheral (refer to the PMECC section in the datasheet for more information). The Boot Program is able to retrieve NAND Flash parameters and ECC requirements using two methods as follows:

  • the detection of a specific header written at the beginning of the first page of NAND Flash, or
  • through the ONFI parameters for ONFI compliant memories. 31 0 Size of the code to download in bytes

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Figure 12-8. Boot NAND Flash Download End No No Copy the valid code from external NVM to internal SRAM. Read NAND Flash and PMECC parameters from the header Read NAND Flash and PMECC parameters from the ONFI Restore the reset values for the peripherals. Perform the REMAP and set the PC to 0 to jump to the downloaded application Initialize NAND Flash interface Send Reset command First page contains valid header NAND Flash is ONFI Compliant Start Restore the reset values for the peripherals and Jump to next bootable memory Yes Yes

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 NAND Flash Specific Header Detection This is the first method used to determine NAND Flash parameters. After Initialization and Reset command, the Boot Program reads the first page without ECC check, to determine if the NAND parameter header is present. The header is made of 52 times the same 32-bit word (for redun- dancy reasons) which must contain NAND and PMECC parameters used to correctly perform the read of the rest of the data in the NAND. This 32-bit word is described below:  usePmecc: Use PMECC 0 = Do not use PMECC to detect and correct the data. 1 = Use PMECC to detect and correct the data.  nbSectorPerPage: Number of sectors per page  spareSize: Size of the spare zone in bytes  eccBitReq: Number of ECC bits required  sectorSize: Size of the ECC sector 0 = for 512 bytes. 1 = for 1024 bytes per sector. Other value for future use.  eccOffset: Offset of the first ECC byte in the spare zone A value below 2 is not allowed and will be considered as 2.  key: value 0xC must be written here to validate the content of the whole word. If the header is valid, the Boot Program will continue with the detection of valid code. 31 30 29 28 27 26 25 24 key - eccOffset 23 22 21 20 19 18 17 16 eccOffset sectorSize 15 14 13 12 11 10 9 8 eccBitReq spareSize 76543210 spareSize nbSectorPerPage usePmecc

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 ONFI 2.2 Parameters In case no valid header has been found, the Boot Program will check if the NAND Flash is ONFI compliant, sending a Read Id command (0x90) with 0x20 as parameter for the address. If the NAND Flash is ONFI compliant, the Boot Program retrieves the following parameters with the help of the Get Parameter Page command:

  • Number of bytes per page (byte 80)
  • Number of bytes in spare zone (byte 84)
  • Number of ECC bit correction required (byte 112)
  • ECC sector size: by default set to 512 bytes, or 1024 bytes if the ECC bit capability above is 0xFF By default, ONFI NAND Flash detection will turn ON the usePmecc parameter, and ECC correc- tion algorithm is automatically activated. Once the Boot Program retrieves the parameter, using one of the two methods described above, it will read the first page again, with or without ECC, depending on the usePmecc parameter. Then it looks for a valid code programmed just after the header offset 0xD0. If the code is valid, the program is copied at the beginning of the internal SRAM. Note: Booting on 16-bit NAND Flash is not possible, only 8-bit NAND Flash memories are supported. NAND Flash Boot: PMECC Error Detection and Correction NAND Flash boot procedure uses PMECC to detect and correct errors during NAND Flash read operations in two cases:
  • when the usePmecc flag is set in the specific NAND header. If the flag is not set, no ECC correction is performed during NAND Flash page read.
  • when the NAND Flash has been detected using ONFI parameters. The ROM code embeds the software used in the process of ECC detection/correction: the Galois Field tables, and the function PMECC_CorrectionAlgo(). The user does not need to embed it in other software. This function can be called by user software when PMECC status returns errors after a read page command. Its address can be retrieved by reading the third vector of the ROM Code interrupt vector table, at address 0x100008. The API of this function is: unsigned int PMECC_CorrectionAlgo(AT91PS_PMECC pPMECC, AT91PS_PMERRLOC pPMERRLOC, PMECC_paramDesc_struct *PMECC_desc, unsigned int PMECC_status, unsigned int pageBuffer) pPMECC: pointer to the PMECC base address, pPMERRLOC: pointer to the PMERRLOC base address, PMECC_desc: pointer to the PMECC descriptor, PMECC_status: the status returned by the read of PMECCISR register;

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 pageBuffer: address of the buffer containing the page to be corrected. The PMECC descriptor structure is: typedef struct _PMECC_paramDesc_struct { unsigned int pageSize; unsigned int spareSize; unsigned int sectorSize; // 0 for 512, 1 for 1024 bytes unsigned int errBitNbrCapability; unsigned int eccSizeByte; unsigned int eccStartAddr; unsigned int eccEndAddr; unsigned int nandWR; unsigned int spareEna; unsigned int modeAuto; unsigned int clkCtrl; unsigned int interrupt; int tt; int mm; int nn; short *alpha_to; short *index_of; short partialSyn[100]; short si[100]; /* sigma table */ short smu[TT_MAX + 2][2 * TT_MAX + 1]; /* polynom order */ short lmu[TT_MAX + 1]; } PMECC_paramDesc_struct;

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 The Galois field tables are mapped in the ROM just after the ROM code, as described in Figure 12-9 below: Figure 12-9. Galois Field Table Mapping For a full description and an example of how to use the PMECC detection and correction fea- ture, refer to the software package dedicated to this device on Atmel’s web site. SD Card Boot The SD Card bootloader uses MCI0. It looks for a “ boot.bin ” file in the root directory of a FAT12/16/32 formatted SD Card. Supported SD Card Devices SD Card Boot supports all SD Card memories compliant with SD Memo ry Card Specification V2.0. This includes SDHC cards. SPI Flash Boot Two kinds of SPI Flash are supported: SPI Serial Flash and SPI DataFlash®. The SPI Flash bootloader tries to boot on SPI0 Chip Select 0, first looking for SPI Serial Flash, and then for SPI DataFlash. It uses only one valid code detection: analysis of ARM exception vectors. The SPI Flash read is done by means of a Continuous Read command from address 0x0. This command is 0xE8 for DataFlash and 0x0B for Serial Flash devices. ROM Code 0x0010_8000 0x0010_0000 Galois field tables for 1024-byte sectors correction Galois field tables for 512-byte sectors correction 0x0011_0000

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Supported DataFlash Devices The SPI Flash Boot program supports all Atmel DataFlash devices. Supported Serial Flash Devices The SPI Flash Boot program supports all SPI Se rial Flash devices responding correctly at both Get Status and Continuous Read commands. TWI EEPROM Boot The TWI EEPROM Bootloader uses the TWI0. It uses only one valid code detection. It analyzes the ARM exception vectors. Supported TWI EEPROM Devices TWI EEPROM Boot supports all I 2C-compatible TWI EEPROM memories using 7-bit device address 0x50.

12.2.4.5 Hardware and Software Constraints

The NVM drivers use several PIOs in peripheral mode to communicate with external memory devices. Care must be taken when these PIOs are used by the application. The devices con- nected could be unintentionally driven at boot time, and electrical conflicts between output pins used by the NVM drivers and the connected devices may occur. To assure correct functionality, it is recommended to plug in critical devices to other pins not used by NVM. Table 12-4 contains a list of pins that are driven during the boot program execution. These pins are driven during the boot sequence for a period of less than 1 second if no correct boot program is found. Table 12-3. DataFlash Device Device Density Page Size (bytes) Number of Pages AT45DB011 1 Mbit 264 512 AT45DB021 2 Mbits 264 1024 AT45DB041 4 Mbits 264 2048 AT45DB081 8 Mbits 264 4096 AT45DB161 16 Mbits 528 4096 AT45DB321 32 Mbits 528 8192 AT45DB642 64 Mbits 1056 8192

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Before performing the jump to the application in internal SRAM, all the PIOs and peripherals used in the boot program are set to their reset state.

12.2.5 SAM-BA Monitor

If no valid code has been found in NVM during the NVM bootloader sequence, the SAM-BA Monitor program is launched. The SAM-BA Monitor principle is to: – Initialize DBGU and USB – Check if USB Device enumeration has occurred – Check if characters have been received on the DBGU Once the communication interface is identified, the application runs in an infinite loop waiting for different commands as listed in Table 12-5. Table 12-4. PIO Driven during Boot Program Execution NVM Bootloader Peri pheral Pin PIO Line NAND EBI CS3 SMC NANDOE PIOD0 EBI CS3 SMC NANDWE PIOD1 EBI CS3 SMC NANDCS PIOD4 EBI CS3 SMC NAND ALE A21 EBI CS3 SMC NAND CLE A22 EBI CS3 SMC Cmd/Addr/Data D[16:0] SD Card MCI0 MCI0_CK PIOA17 MCI0 MCI0_D0 PIOA15 MCI0 MCI0_D1 PIOA18 MCI0 MCI0_D2 PIOA19 MCI0 MCI0_D3 PIOA20 SPI Flash SPI0 MOSI PIOA10 SPI0 MISO PIOA11 SPI0 SPCK PIOA13 SPI0 NPCS0 PIOA14 SPI0 NPCS1 PIOA7 TWI0 EEPROM TWI0 TWD0 PIOA30 TWI0 TWCK0 PIOA31 SAM-BA Monitor DBGU DRXD PIOA9 DBGU DTXD PIOA10

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Figure 12-10. SAM-BA Monitor Diagram

12.2.5.1 Command List

  • Mode commands: – Normal mode configures SAM-BA Monitor to send / receive data in binary format, – Terminal mode configures SAM-BA Monitor to send / receive data in ascii format.
  • Write commands: Write a byte ( O), a halfword (H) or a word (W) to the target. – Address: Address in hexadecimal. – Value: Byte, halfword or word to write in hexadecimal. – Output: ‘>’
  • Read commands: Read a byte (o), a halfword (h) or a word (w) from the target. Character(s) received on DBGU ? Run monitor Wait for command on the USB link Run monitor Wait for command on the DBGU link USB Enumeration Successful ? Ye s Ye s No No Init DBGU and USB No valid code in NVM Table 12-5. Commands Available through the SAM-BA Monitor Command Action Argument(s) Example N set Normal mode No argument N# T set Terminal mode No argument T# O write a byte Address, Value# O200001,CA# o read a byte Address,# o200001,# H write a half word Address, Value# H200002,CAFE# h read a half word Address,# h200002,# W write a word Address, Value# W200000,CAFEDECA# w read a word Address,# w200000,# S send a file Address,# S200000,# R receive a file Address, NbOfBytes# R200000,1234# G go Address# G200200# V display version No argument V#

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 – Address: Address in hexadecimal. – Output: The byte, halfword or word read in hexadecimal followed by ‘>’

  • Send a file (S): Send a file to a specified address. – Address: Address in hexadecimal. – Output: ‘>’ Note: There is a time-out on this command which is reached when the prompt ‘>’ appears before the end of the command execution.
  • Receive a file (R): Receive data into a file from a specified address – Address: Address in hexadecimal. – NbOfBytes: Number of bytes in hexadecimal to receive. – Output: ‘>’
  • G o (G): Jump to a specified address and execute the code. – Address: Address to jump in hexadecimal. – Output: ‘>’once returned from the program execution. If the executed program does not handle the link register at its entry and does not return, the prompt will not be displayed.
  • Get Version (V): Return the Boot Program version. – Output: version, date and time of ROM code followed by ‘>’.

12.2.5.2 DBGU Serial Port

Communication is performed through the DBGU serial port initialized to 115,200 Baud, 8 bits of data, no parity, 1 stop bit. Supported External Crystal/External Clocks The SAM-BA Monitor supports a frequency of 12 MHz to allow DBGU communication for both external crystal and external clock. Xmodem Protocol The Send and Receive File commands use the Xmodem protocol to communicate. Any terminal performing this protocol can be used to send th e application file to the target. The size of the binary file to send depends on the SRAM size embedded in the product. In all cases, the size of the binary file must be lower than the SRAM si ze because the Xmodem protocol requires some SRAM memory in order to work. The Xmodem protocol supported is the 128-byte l ength block. This protocol uses a two-charac- ter CRC16 to guarantee detection of a maximum bit error. Xmodem protocol with CRC is accurate provided both sender and receiver report successful transmission. Each block of the transfer looks like: <SOH><blk #><255-blk #><--128 data bytes--><checksum> in which: – <SOH> = 01 hex – <blk #> = binary number, starts at 01, increments by 1, and wraps 0FFH to 00H (not to 01) – <255-blk #> = 1’s complement of the blk#. – <checksum> = 2 bytes CRC16 Figure 12-11 shows a transmission using this protocol.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Figure 12-11. Xmodem Transfer Example

12.2.5.3 USB Device Port

Supported External Crystal / External Clocks The frequencies supported by SAM-BA Monitor to allow USB communication are 4, 8, 12 or 16 MHz crystal or external clock. USB Class The device uses the USB Communication Device Class (CDC) drivers to take advantage of the installed PC RS-232 software to talk over the USB. The CDC class is implemented in all releases of Windows ®, from Windows 98SE® to Windows XP®. The CDC document, available at www.usb.org, describes how to implement devices su ch as ISDN modems and virtual COM ports. The Vendor ID is Atmel’s vendor ID 0x03EB. The product ID is 0x6124. These references are used by the host operating system to mount the correct driver. On Windows systems, the INF files contain the correspondence between vendor ID and product ID. Enumeration Process The USB protocol is a master/slave protocol. The host starts the enumeration, sending requests to the device through the control endpoint. The device handles standard requests as defined in the USB Specification. Host Device SOH 01 FE Data[128] CR C CR C C ACK SOH 02 FD Data[128] CR C CR C ACK SOH 03 FC Data[100] CR C CR C ACK EOT ACK Table 12-6. Handled Standard Requests Request Definition GET_DESCRIPTOR Returns the current device configuration value. SET_ADDRESS Sets the device address for all future device access. SET_CONFIGURATION Sets the device configuration. GET_CONFIGURATION Returns the current device configuration value.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 The device also handles some class requests defined in the CDC class. Unhandled requests are stalled. Communication Endpoints There are two communication endpoints and endpoint 0 is used for the enumeration process. Endpoint 1 is a 64-byte Bulk OUT endpoint and endpoint 2 is a 64-byte Bulk IN endpoint. SAM- BA Boot commands are sent by the host through endpoint 1. If required, the message is split by the host into several data payloads by the host driver. If the command requires a response, the host can send IN transactions to pick up the response. GET_STATUS Returns status for the specified recipient. SET_FEATURE Used to set or enable a specific feature. CLEAR_FEATURE Used to clear or disable a specific feature. Table 12-7. Handled Class Requests Request Definition SET_LINE_CODING Configures DTE rate, stop bits, parity and number of character bits. GET_LINE_CODING Requests current DTE rate, stop bits, parity and number of character bits. SET_CONTROL_LINE_STATE RS-232 signal used to tell the DTE device is now present. Table 12-6. Handled Standard Requests (Continued) Request Definition

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 113 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 13. Boot Sequence Controller (BSC)

13.1 Description

The System Controller embeds a Boot Sequence Configuration Register to save timeout delays on boot. The boot sequence is programmable through the Boot Sequence Configuration Regis- ter (BSCR). This register is powered by VDDBU, the modification is saved and applied after the next reset. The register is taking Factory Value in case of battery removing. This register is programmable with user programs or SAM-BA and key-protected.

13.2 Embedded Characteristics

  • VDDBU powered register

13.3 Product Dependencies

  • Product-dependent order

13.4 Boot Sequence Controller (BSC) User Interface

Table 13-1. Register Mapping Offset Register Name Access Reset 0x0 Boot Sequence Configuration Register BSC_CR Read-write –

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 114 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

13.4.1 Boot Sequence Configuration Register

Name: BSC_CR Address: 0xFFFFFD54 Access: Read-write Factory Value:0x0000_0000  BOOT: Boot media sequence This value is defined in the product-dependent ROM code. It is only written if BOOTKEY carries the valid value. B O O T K E Y 0x6683 (BSC_KEY): valid key to write BSC_CR register; it needs to be written at the same time as the BOOT field. Other values disable the write access. This key field is write-only. 31 30 29 28 27 26 25 24 BOOTKEY 23 22 21 20 19 18 17 16 BOOTKEY 15 14 13 12 11 10 9 8 76543210 BOOT

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 14. Reset Controller (RSTC)

14.1 Description

The Reset Controller (RSTC), based on power-on reset cells, handles all the resets of the sys- tem without any external components. It reports which reset occurred last. The Reset Controller also drives independently or simultaneously the external reset and the peripheral and processor resets.

14.2 Embedded Characteristics

  • Manages All Resets of the System, Including – External Devices Through the NRST Pin – Processor Reset – Peripheral Set Reset – Backed-up Peripheral Reset
  • Based on 2 Embedded Power-on Reset Cells
  • Reset Source Status – Status of the Last Reset – Either General Reset, Wake-up Reset, Software Reset, User Reset, Watchdog Reset
  • External Reset Signal Shaping
  • A M B A™-compliant Interface – Interfaces to the ARM® Advanced Peripheral Bus

14.3 Block Diagram

Figure 14-1. Reset Controller Block Diagram NRST Startup Counter proc_nreset wd_fault periph_nreset backup_neset SLCK Reset State Manager Reset Controller rstc_irq NRST Manager exter_nresetnrst_out Main Supply POR WDRPROC user_reset Backup Supply POR

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

14.4 Functional Description

14.4.1 Reset Controller Overview

The Reset Controller is made up of an NRST Manager, a Startup Counter and a Reset State Manager. It runs at Slow Clock and generates the following reset signals:

  • proc_nreset: Processor reset line. It also resets the Watchdog Timer.
  • backup_nreset: Affects all the peripherals powered by VDDBU.
  • periph_nreset: Affects the whole set of embedded peripherals.
  • nrst_out: Drives the NRST pin. These reset signals are asserted by the Reset Controller, either on external events or on soft- ware action. The Reset State Manager controls the generation of reset signals and provides a signal to the NRST Manager when an assertion of the NRST pin is required. The NRST Manager shapes the NRST assertion during a programmable ti me, thus controlling external device resets. The startup counter waits for the complete crystal oscillator startu p. The wait de lay is given by the crystal oscillator startup time maximum value that can be foun d in the section Crystal Oscil- lator Characteristics in the Electrical Characteristics section of the product documentation. The Reset Controller Mode Register (RSTC_MR), allowing the configuration of the Reset Con- troller, is powered with VDDBU, so that its configuration is saved as long as VDDBU is on.

14.4.2 NRST Manager

After power-up, NRST is an output during the ERSTL time defined in the RSTC. When ERSTL elapsed, the pin behaves as an input and all the system is held in reset if NRST is tied to GND by an external signal. The NRST Manager samples the NRST input pin and drives this pin low when required by the Reset State Manager. Figure 14-2shows the block diagram of the NRST Manager. Figure 14-2. NRST Manager NRST Signal The NRST Manager handles the NRST input line asynchronously. When the line is low, a User Reset is immediately reported to the Reset State Manager. When the NRST goes from low to high, the internal reset is synchronized with the Slow Clock to provide a safe internal de-assertion of reset. Ex t er n al Reset Ti m er URSTS ERSTL exter_nreset RSTC_M R RSTC_SR NRSTL nrst_out NRST user_reset

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 The level of the pin NRST can be read at any ti me in the bit NRSTL (NRST level) in RSTC_SR. As soon as the pin NRST is asserted, the bit UR STS in RSTC_SR is set. This bit clears only when RSTC_SR is read.

14.4.2.1 NRST External Reset Control

The Reset State Manager asserts the signal ext_nreset to assert the NRST pin. When this occurs, the “nrst_out” signal is driven low by the NRST Manager for a time programmed by the field ERSTL in RSTC_MR. This assertion duration, named EXTERNAL_RESET_LENGTH, lasts 2(ERSTL+1) Slow Clock cycles. This gives the approximate duration of an assertion between 60 μs and 2 seconds. Note that ERSTL at 0 defines a two-cycle duration for the NRST pulse. This feature allows the Reset Controller to shape the NRST pin level, and thus to guarantee that the NRST line is driven low for a time compliant with potential external devices connected on the system reset. As the field is within RSTC_MR, which is backed -up, this field can be used to shape the system power-up reset for devices requiring a longer startup time than the Slow Clock Oscillator.

14.4.3 BMS Sampling

The product matrix manages a boot memory that depends on the level on the BMS pin at reset. The BMS signal is sampled three slow clock cycles after the Core Power-On-Reset output rising edge. Figure 14-3. BMS Sampling

14.4.4 Reset States

The Reset State Manager handles the different reset sources and generates the internal reset signals. It reports the reset status in the field RSTTYP of the Status Register (RSTC_SR). The update of the field RSTTYP is performed when the processor reset is released.

14.4.4.1 General Reset

A general reset occurs when VDDBU and VDDCORE are powered on. The backup supply POR cell output rises and is filtered with a Startup Counter, which operates at Slow Clock. The pur- pose of this counter is to make sure the Slow Clock oscillator is stable before starting up the device. The length of startup time is hardcoded to comply with the Slow Clock Oscillator startup time. SLCK Core Supply POR output BMS sampling delay = 3 cycles BMS Signal proc_nreset XXX H or L

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 After this time, the processor clock is released at Slow Clock and all the other signals remain valid for 3 cycles for proper processor and logic reset. Then, all the reset signals are released and the field RSTTYP in RSTC_SR reports a General Reset. As the RSTC_MR is reset, the NRST line rises 2 cycles after the backup_nreset, as ERSTL defaults at value 0x0. When VDDBU is detected low by the Backup Suppl y POR Cell, all resets signals are immedi- ately asserted, even if the Main Supply POR Cell does not report a Main Supply shutdown. VDDBU only activates the backup_nreset signal. The backup_nreset must be released so that any other reset can be generated by VDDCORE (Main Supply POR output). Figure 14-4 shows how the General Reset affects the reset signals. Figure 14-4. General Reset State

14.4.4.2 Wake-up Reset

The Wake-up Reset occurs when the Main Supply is down. When the Main Supply POR output is active, all the reset signals are asserted except backup_nreset. When the Main Supply pow- ers up, the POR output is resynchronized on Slow Clock. The processor clock is then re-enabled during 3 Slow Clock cycles, depending on the requirements of the ARM processor. At the end of this delay, the processor and other reset signals rise. The field RSTTYP in RSTC_SR is updated to report a Wake-up Reset. The “nrst_out” remains asserted for EXTERNAL_RESET_LENGTH cycles. As RSTC_MR is backed-up, the programmed number of cycles is applicable. SLCK periph_nreset proc_nreset Backup Supply POR output NRST (nrst_out) EXTERNAL RESET LENGTH = 2 cycles Startup Time MCK Processor Startup backup_nreset Any Freq. RSTTYP XXX 0x0 = General Reset XXX Main Supply POR output BMS Sampling

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Figure 14-5. When the Main Supply is detected falling, the reset signals are immediately asserted. This transition is syn- chronous with the output of the Main Supply POR.Wake-up Reset

14.4.4.3 User Reset

The User Reset is entered when a low level is detected on the NRST pin When a falling edge occurs on NRST (reset activation), internal reset lines are immediately asserted. The Processor Reset and the Peripheral Reset are asserted. The User Reset is left when NRST rises, after a two-cycle resynchronization time and a 3-cycle processor startup. The processor clock is re-enabled as soon as NRST is confirmed high. When the processor reset signal is released, the RSTTYP field of the Status Register (RSTC_SR) is loaded with the value 0x4, indicating a User Reset. The NRST Manager guarantees that the NRST line is asserted for EXTERNAL_RESET_LENGTH Slow Clock cycles, as programmed in the field ERSTL. How- ever, if NRST does not rise after EXTERN AL_RESET_LENGTH because it is driven low externally, the internal reset lines remain asserted until NRST actually rises. SLCK periph_nreset proc_nreset Main Supply POR output NRST (nrst_out) EXTERNAL RESET LENGTH = 4 cycles (ERSTL = 1) MCK Processor Startup backup_nreset Any Freq. Resynch. 2 cycles RSTTYP XXX 0x1 = WakeUp Reset XXX

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Figure 14-6. User Reset State

14.4.4.4 Software Reset

The Reset Controller offers several commands used to assert the different reset signals. These commands are performed by writing the Control Register (RSTC_CR) with the following bits at

  • PROCRST: Writing PROCRST at 1 resets the processor and the watchdog timer.
  • PERRST: Writing PERRST at 1 resets all the embedded peripherals, including the memory system, and, in particular, the Remap Command. The Peripheral Reset is generally used for debug purposes. Except for Debug purposes, PERRST must always be used in conjunction with PROCRST (PERRST and PROCRST set both at 1 simultaneously.)
  • EXTRST: Writing EXTRST at 1 asserts low the NRST pin during a time defined by the field ERSTL in the Mode Register (RSTC_MR). The software reset is entered if at least one of these bits is set by the software. All these com- mands can be performed independently or simultaneously. The software reset lasts 3 Slow Clock cycles. The internal reset signals are asserted as soon as the register write is performed. This is detected on the Master Clock (MCK). They are released when the software reset is left, i.e.; syn- chronously to SLCK. If EXTRST is set, the nrst_out signal is asserted depending on the programming of the field ERSTL. However, the resulting falling edge on NRST does not lead to a User Reset. If and only if the PROCRST bit is set, the Reset Controller reports the software status in the field RSTTYP of the Status Register (RSTC_SR). Other Software Resets are not reported in RSTTYP. SLCK periph_nreset proc_nreset NRST NRST (nrst_out) >= EXTERNAL RESET LENGTH MCK Processor Startup Any Freq. RSTTYP Any XXX Resynch. 2 cycles 0x4 = User Reset

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 As soon as a software operation is detected, the bit SRCMP (Software Reset Command in Prog- ress) is set in the Status Register (RSTC_SR). It is cleared as soon as the software reset is left. No other software reset can be performed while the SRCMP bit is set, and writing any value in RSTC_CR has no effect. Figure 14-7. Software Reset

14.4.4.5 Watchdog Reset

The Watchdog Reset is entered when a watchdog fault occurs. This state lasts 3 Slow Clock cycles. When in Watchdog Reset, assertion of the reset signals depends on the WDRPROC bit in WDT_MR:

  • If WDRPROC is 0, the Processor Reset and the Peripheral Reset are asserted. The NRST line is also asserted, depending on the programming of the field ERSTL. However, the resulting low level on NRST does not result in a User Reset state.
  • If WDRPROC = 1, only the processor reset is asserted. The Watchdog Timer is reset by the proc_nreset si gnal. As the watchdog fault always causes a processor reset if WDRSTEN is set, the Watc hdog Timer is always reset after a Watchdog Reset and the Watchdog is enabled by default and with a period set to a maximum. When the WDRSTEN in WDT_MR bit is reset, the watchdog fault has no impact on the reset controller. SLCK periph_nreset if PERRST=1 proc_nreset if PROCRST=1 Write RSTC_CR NRST (nrst_out) if EXTRST=1 EXTERNAL RESET LENGTH 8 cycles (ERSTL=2) MCK Processor Startup = 3 cycles Any Freq. RSTTYP Any XXX 0x3 = Software Reset Resynch. 1 to 2 cycles SRCMP in RSTC_SR

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Figure 14-8. Watchdog Reset

14.4.5 Reset State Priorities

The Reset State Manager manages the following priorities between the different reset sources, given in descending order:

  • Backup Reset
  • Wake-up Reset
  • User Reset
  • Watchdog Reset
  • Software Reset Particular cases are listed below:
  • When in User Reset: – A watchdog event is impossible because the Watchdog Timer is being reset by the proc_nreset signal. – A software reset is impossible, since the processor reset is being activated.
  • When in Software Reset: – A watchdog event has priority over the current state. – The NRST has no effect.
  • When in Watchdog Reset: – The processor reset is active and so a Software Reset cannot be programmed. – A User Reset cannot be entered.

14.4.6 Reset Controller Status Register

The Reset Controller status register (RSTC_SR) provides several status fields:

  • RSTTYP field: This field gives the type of the last reset, as explained in previous sections. Only if WDRPROC = 0 SLCK periph_nreset proc_nreset wd_fault NRST (nrst_out) EXTERNAL RESET LENGTH 8 cycles (ERSTL=2) MCK Processor Startup = 3 cycles Any Freq. RSTTYP Any XXX 0x2 = Watchdog Reset

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

  • SRCMP bit: This field indicates that a Software Reset Command is in progress and that no further software reset should be performed until the end of the current one. This bit is automatically cleared at the end of the current software reset.
  • NRSTL bit: The NRSTL bit of the Status Register gives the level of the NRST pin sampled on each MCK rising edge.
  • URSTS bit: A high-to-low transition of the NRST pin sets the URSTS bit of the RSTC_SR register. This transition is also detected on the Master Clock (MCK) rising edge (see Figure 14-9). Reading the RSTC_SR status register resets the URSTS bit. Figure 14-9. Reset Controller Status and Interrupt MCK NRST NRSTL 2 cycle resynchronization 2 cycle resynchronization URSTS read RSTC_SRPeripheral Access rstc_irq if (URSTEN = 0) and (URSTIEN = 1)

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

14.5 Reset Controller (RSTC) User Interface

Note: 1. The reset value of RSTC_SR either reports a General Reset or a Wake-up Reset depending on last rising power supply. Table 14-1. Register Mapping Offset Register Name Access Reset Back-up Reset 0x00 Control Register RSTC_CR Write-only - 0x04 Status Register RSTC_SR Read-only 0x0000_0001 0x0000_0000 0x08 Mode Register RSTC_MR Read-write - 0x0000_0000

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

14.5.1 Reset Controller Control Register

Name: RSTC_CR Address: 0xFFFFFE00 Access: Write-only  PROCRST: Processor Reset 0 = No effect. 1 = If KEY is correct, resets the processor.  PERRST: Peripheral Reset 0 = No effect. 1 = If KEY is correct, resets the peripherals.  EXTRST: External Reset 0 = No effect. 1 = If KEY is correct, asserts the NRST pin. K E Y : P a s s w o r d Should be written at value 0xA5. Writing any other value in this field aborts the write operation. 31 30 29 28 27 26 25 24 KEY 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 –––– E XTRST P ERRST – P ROCRST

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

14.5.2 Reset Controller Status Register

Name: RSTC_SR Address: 0xFFFFFE04 Access: Read-only  URSTS: User Reset Status 0 = No high-to-low edge on NRST happened since the last read of RSTC_SR. 1 = At least one high-to-low transition of NRST has been detected since the last read of RSTC_SR.  RSTTYP: Reset Type Reports the cause of the last processor reset. Reading this RSTC_SR does not reset this field.  NRSTL: NRST Pin Level Registers the NRST Pin Level at Master Clock (MCK).  SRCMP: Software Reset Command in Progress 0 = No software command is being performed by the reset controller. The reset controller is ready for a software command. 1 = A software reset command is being performed by the reset controller. The reset controller is busy. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 RSTTYP Reset Type Comments 0 0 0 General Reset Both VDDCORE and VDDBU rising 0 0 1 Wake Up Reset VDDCORE rising 0 1 0 Watchdog Reset Watchdog fault occurred 0 1 1 Software Reset Processor reset required by the software 1 0 0 User Reset NRST pin detected low

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

14.5.3 Reset Controller Mode Register

Name: RSTC_MR Address: 0xFFFFFE08 Access: Read-write  ERSTL: External Reset Length This field defines the external reset length. The external reset is asserted during a time of 2 (ERSTL+1) Slow Clock cycles. This allows assertion duration to be programmed between 60 μs and 2 seconds. K E Y : P a s s w o r d Should be written at value 0xA5. Writing any other value in this field aborts the write operation. 31 30 29 28 27 26 25 24 KEY 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 –––– ERSTL 76543210

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 129 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 15. Real TIme Clock (RTC)

15.1 Description

The Real-time Clock (RTC) peripheral is designed for very low power consumption. It combines a complete time-of-day clock with alarm and a two-hundred-year Gregorian calen- dar, complemented by a programmable periodic interrupt. The alarm and calendar registers are accessed by a 32-bit data bus. The time and calendar values are coded in binary-coded decimal (BCD) format. The time format can be 24-hour mode or 12-hour mode with an AM/PM indicator. Updating time and calendar fields and configuri ng the alarm fields are performed by a parallel capture on the 32-bit data bus. An entry control is performed to avoid loading registers with incompatible BCD format data or with an incompatible date according to the current month/year/century.

15.2 Embedded Characteristics

  • Low Power Consumption
  • Full Asynchronous Design
  • Two Hundred Y ear Gregorian Calendar
  • Programmable Periodic Interrupt
  • Time, Date and Alarm 32-bit Parallel Load

15.3 Block Diagram

Figure 15-1. RTC Block Diagram

15.4 Product Dependencies

15.4.1 Power Management

The Real-time Clock is cont inuously clocked at 32768 Hz. The Power Management Controller has no effect on RTC behavior. Bus Interface

32768 Divider TimeSlow Clock: SLCK

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 130 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

15.4.2 Interrupt

Within the System Controller, the RTC interrupt is OR-wired with all the other module interrupts. Only one System Controller interrupt line is connected on one of the internal sources of the inter- rupt controller. RTC interrupt requires the interrupt controller to be programmed first. When a System Controller interrupt occurs, the service routine must first determine the cause of the interrupt. This is done by reading each status register of the System Controller peripherals successively.

15.5 Functional Description

The RTC provides a full binary-coded decimal (B CD) clock that includes century (19/20), year (with leap years), month, date, day, hours, minutes and seconds. The valid year range is 1900 to 2099 in Gregorian mode, a two-hundred-year calendar. The RTC can operate in 24-hour mode or in 12-hour mode with an AM/PM indicator. Corrections for leap years are included (all years divisible by 4 being leap years). This is correct up to the year 2099.

15.5.1 Reference Clock

The reference clock is Slow Clock (SLCK). It can be driven internally or by an external 32.768 kHz crystal. During low power modes of the processor, the osc illator runs and power consumption is critical. The crystal selection has to take into account the current consumption for power saving and the frequency drift due to temperature effect on the circuit for time accuracy.

15.5.2 Timing

The RTC is updated in real time at one-second intervals in normal mode for the counters of sec- onds, at one-minute intervals for the counter of minutes and so on. Due to the asynchronous operation of the RTC with respect to the rest of the chip, to be certain that the value read in the RTC registers (century, year, month, date, day, hours, minutes, sec- onds) are valid and stable, it is necessary to read these registers twice. If the data is the same both times, then it is valid. Therefore, a minimu m of two and a maximum of three accesses are required.

15.5.3 Alarm

The RTC has five programmable fields: month, date, hours, minutes and seconds. Each of these fields can be enabled or disabled to match the alarm condition:

  • If all the fields are enabled, an alarm flag is generated (the corresponding flag is asserted and an interrupt generated if enabled) at a given month, date, hour/minute/second.
  • If only the “seconds” field is enabled, then an alarm is generated every minute. Depending on the combination of fields enabled, a large number of possibilities are available to the user ranging from minutes to 365/366 days.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 131 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

15.5.4 Error Checking

Verification on user interface data is performed when accessing the century, year, month, date, day, hours, minutes, seconds and alarms. A check is performed on illegal BCD entries such as illegal date of the month with regard to the year and century configured. If one of the time fields is not correct, the data is not loaded into the register/counter and a flag is set in the validity register. The user can not reset this flag. It is reset as soon as an acceptable value is programmed. This avoids any further side effects in the hardware. The same procedure is done for the alarm. The following checks are performed: 1. Century (check if it is in range 19 - 20) 2. Y ear (BCD entry check) 3. Date (check range 01 - 31) 4. Month (check if it is in BCD range 01 - 12, check validity regarding “date”) 5. Day (check range 1 - 7) 6. Hour (BCD checks: in 24-hour mode, check range 00 - 23 and check that AM/PM flag is not set if RTC is set in 24-hour mode; in 12-hour mode check range 01 - 12) 7. Minute (check BCD and range 00 - 59) 8. Second (check BCD and range 00 - 59) Note: If the 12-hour mode is selected by means of the RTC_MODE register, a 12-hour value can be pro- grammed and the returned value on RTC_TIME will be the corresponding 24-hour value. The entry control checks the value of the AM/PM indicator (bit 22 of RTC_TIME register) to determine the range to be checked.

15.5.5 Updating Time/Calendar

To update any of the time/calendar fields, the user must first stop the RTC by setting the corre- sponding field in the Control Register. Bit UPDTIM must be set to update time fields (hour, minute, second) and bit UPDCAL must be set to update calendar fields (century, year, month, date, day). Then the user must poll or wait for the interrupt (if enabled) of bit ACKUPD in the Status Regis- ter. Once the bit reads 1, it is mandatory to clear this flag by writing the corresponding bit in RTC_SCCR. The user can now write to the appropriate Time and Calendar register. Once the update is finished, the user must reset (0) UPDTIM and/or UPDCAL in the Control When entering programming mode of the calendar fields, the time fields remain enabled. When entering the programming mode of the time fields, both time and calendar fields are stopped. This is due to the location of the calendar logic circuity (downstream for low-power consider- ations). It is highly recommended to prepare all the fields to be updated before entering programming mode. In successive update operations, the user must wait at least one second after resetting the UPDTIM/UPDCAL bit in the RTC_CR (Control Register) before setting these bits again. This is done by waiting for the SE C flag in the Status Register before setting UPDTIM/UPDCAL bit. After resetting UPDTIM/UPDCAL, the SEC flag must also be cleared.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 132 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Figure 15-2. Update Sequence Prepare TIme or Calendar Fields Set UPDTIM and/or UPDCAL bit(s) in RTC_CR Read RTC_SR ACKUPD = 1 ? Clear ACKUPD bit in RTC_SCCR Update Time and/or Calendar values in RTC_TIMR/RTC_CALR Clear UPDTIM and/or UPDCAL bit in RTC_CR No Yes Begin End Polling or IRQ (if enabled)

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 133 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

15.6 Real Time Clock (RTC) User Interface

Note: if an offset is not listed in the table it must be considered as reserved. Table 15-1. Register Mapping Offset Register Name Access Reset 0x00 Control Register RTC_CR Read-write 0x0 0x04 Mode Register RTC_MR Read-write 0x0 0x08 Time Register RTC_TIMR Read-write 0x0 0x0C Calendar Register RTC_CALR Read-write 0x01210720 0x10 Time Alarm Register RTC_TIMALR Read-write 0x0 0x14 Calendar Alarm Register RTC_CALALR Read-write 0x01010000 0x18 Status Register RTC_SR Read-only 0x0 0x1C Status Clear Command R egister RTC_SCCR Write-only – 0x20 Interrupt Enable Register RTC_IER Write-only – 0x24 Interrupt Disable Re gister RTC_IDR Write-only – 0x28 Interrupt Mask Register RTC_IMR Read-only 0x0 0x2C Valid Entry Register RTC_VER Read-only 0x0 0x30–0xF8 Reserved Register – – – 0xFC Reserved Register – – –

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 134 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

15.6.1 RTC Control Register

Name: RTC_CR Address: 0xFFFFFEB0 Access: Read-write  UPDTIM: Update Request Time Register 0 = No effect. 1 = Stops the RTC time counting. Time counting consists of second, minute and hour counters. Time counters can be programmed once this bit is set and acknowledged by the bit ACKUPD of the Status Register.  UPDCAL: Update Request Calendar Register 0 = No effect. 1 = Stops the RTC calendar counting. Calendar counting consists of day, date, month, year and century counters. Calendar counters can be programmed once this bit is set.  TIMEVSEL: Time Ev ent Selection The event that generates the flag TIMEV in RTC_SR (Status Register) depends on the value of TIMEVSEL.  CALEVSEL: Calendar Event Selection The event that generates the flag CALEV in RTC_SR depends on the value of CALEVSEL 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 Value Name Description

0 MINUTE Minute change

1 HOUR Hour change

2 MIDNIGHT Every day at midnight

3 NOON Every day at noon

0 WEEK Week change (every Monday at time 00:00:00)

1 MONTH Month change (every 01 of each month at time 00:00:00)

2 YEAR Y ear change (every January 1 at time 00:00:00)

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 135 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

15.6.2 RTC Mode Register

Name: RTC_MR Address: 0xFFFFFEB4 Access: Read-write  HRMOD: 12-/24-hour Mode 0 = 24-hour mode is selected. 1 = 12-hour mode is selected. All non-significant bits read zero. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 136 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

15.6.3 RTC Time Register

Name: RTC_TIMR Address: 0xFFFFFEB8 Access: Read-write  SEC: Current Second The range that can be set is 0 - 59 (BCD). The lowest four bits encode the units. The higher bits encode the tens.  MIN: Current Minute The range that can be set is 0 - 59 (BCD). The lowest four bits encode the units. The higher bits encode the tens.  HOUR: Current Hour The range that can be set is 1 - 12 (BCD) in 12-hour mode or 0 - 23 (BCD) in 24-hour mode.  AMPM: Ante Meridiem Post Meridiem Indicator This bit is the AM/PM indicator in 12-hour mode. 0 = AM. 1 = PM. All non-significant bits read zero. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 –A MPM HOUR 15 14 13 12 11 10 9 8 –M IN 76543210 –S EC

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 137 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

15.6.4 RTC Calendar Register

Name: RTC_CALR Address: 0xFFFFFEBC Access: Read-write  CENT: Current Century The range that can be set is 19 - 20 (BCD). The lowest four bits encode the units. The higher bits encode the tens.  YEAR: Current Year The range that can be set is 00 - 99 (BCD). The lowest four bits encode the units. The higher bits encode the tens.  MONTH: Current Month The range that can be set is 01 - 12 (BCD). The lowest four bits encode the units. The higher bits encode the tens.  DAY: Current Day in Current Week The range that can be set is 1 - 7 (BCD). The coding of the number (which number represents which day) is user-defined as it has no effect on the date counter.  DATE: Current Day in Current Month The range that can be set is 01 - 31 (BCD). The lowest four bits encode the units. The higher bits encode the tens. All non-significant bits read zero. 31 30 29 28 27 26 25 24 –– DATE 23 22 21 20 19 18 17 16 DAY MONTH 15 14 13 12 11 10 9 8 YEAR 76543210 –C ENT

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 138 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

15.6.5 RTC Time Alarm Register

Name: RTC_TIMALR Address: 0xFFFFFEC0 Access: Read-write  SEC: Second Alarm This field is the alarm field corresponding to the BCD-coded second counter.  SECEN: Second Alarm Enable 0 = The second-matching alarm is disabled. 1 = The second-matching alarm is enabled.  MIN: Minute Alarm This field is the alarm field corresponding to the BCD-coded minute counter.  MINEN: Minute Alarm Enable 0 = The minute-matching alarm is disabled. 1 = The minute-matching alarm is enabled.  HOUR: Hour Alarm This field is the alarm field corresponding to the BCD-coded hour counter.  AMPM: AM/PM Indicator This field is the alarm field corresponding to the BCD-coded hour counter.  HOUREN: Hour Alarm Enable 0 = The hour-matching alarm is disabled. 1 = The hour-matching alarm is enabled. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 HOUREN AMPM HOUR 15 14 13 12 11 10 9 8 MINEN MIN 76543210 SECEN SEC

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 139 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

15.6.6 RTC Calendar Alarm Register

Name: RTC_CALALR Address: 0xFFFFFEC4 Access: Read-write  MONTH: Month Alarm This field is the alarm field corresponding to the BCD-coded month counter.  MTHEN: Month Alarm Enable 0 = The month-matching alarm is disabled. 1 = The month-matching alarm is enabled. D A T E : D a t e A l a r m This field is the alarm field corresponding to the BCD-coded date counter.  DATEEN: Date Alarm Enable 0 = The date-matching alarm is disabled. 1 = The date-matching alarm is enabled. 31 30 29 28 27 26 25 24 DATEEN – DATE 23 22 21 20 19 18 17 16 MTHEN – – MONTH 15 14 13 12 11 10 9 8 76543210

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 140 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

15.6.7 RTC Status Register

Name: RTC_SR Address: 0xFFFFFEC8 Access: Read-only  ACKUPD: Acknowledge for Update 0 = Time and calendar registers cannot be updated. 1 = Time and calendar registers can be updated.  ALARM: Alarm Flag 0 = No alarm matching condition occurred. 1 = An alarm matching condition has occurred.  SEC: Second Event 0 = No second event has occurred since the last clear. 1 = At least one second event has occurred since the last clear.  TIMEV: Time Event 0 = No time event has occurred since the last clear. 1 = At least one time event has occurred since the last clear. The time event is selected in the TIMEVSEL field in RT C_CR (Control Register) and can be any one of the following events: minute change, hour change, noon, midnight (day change).  CALEV: Calendar Event 0 = No calendar event has occurred since the last clear. 1 = At least one calendar event has occurred since the last clear. The calendar event is selected in the CALEVSEL field in RTC_CR and can be any one of the following events: week change, month change and year change. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 – – – CALEV TIMEV SEC ALARM ACKUPD

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 141 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

15.6.8 RTC Status Clear Command Register

Name: RTC_SCCR Address: 0xFFFFFECC Access: Write-only  ACKCLR: Acknowledge Clear 0 = No effect. 1 = Clears corresponding status flag in the Status Register (RTC_SR).  ALRCLR: Alarm Clear 0 = No effect. 1 = Clears corresponding status flag in the Status Register (RTC_SR).  SECCLR: Second Clear 0 = No effect. 1 = Clears corresponding status flag in the Status Register (RTC_SR).  TIMCLR: Time Clear 0 = No effect. 1 = Clears corresponding status flag in the Status Register (RTC_SR).  CALCLR: Calendar Clear 0 = No effect. 1 = Clears corresponding status flag in the Status Register (RTC_SR). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 – – – CALCLR TIMCLR SECCLR ALRCLR ACKCLR

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 142 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

15.6.9 RTC Interrupt Enable Register

Name: RTC_IER Address: 0xFFFFFED0 Access: Write-only  ACKEN: Acknowledge Update Interrupt Enable 0 = No effect. 1 = The acknowledge for update interrupt is enabled.  ALREN: Alarm Interrupt Enable 0 = No effect. 1 = The alarm interrupt is enabled.  SECEN: Second Event Interrupt Enable 0 = No effect. 1 = The second periodic interrupt is enabled.  TIMEN: Time Event Interrupt Enable 0 = No effect. 1 = The selected time event interrupt is enabled.  CALEN: Calendar Event Interrupt Enable 0 = No effect.

  • 1 = The selected calendar event interrupt is enabled. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 – – – CALEN TIMEN SECEN ALREN ACKEN

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 143 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

15.6.10 RTC Interrupt Disable Register

Name: RTC_IDR Address: 0xFFFFFED4 Access: Write-only  ACKDIS: Acknowledge Update Interrupt Disable 0 = No effect. 1 = The acknowledge for update interrupt is disabled.  ALRDIS: Alarm Interrupt Disable 0 = No effect. 1 = The alarm interrupt is disabled.  SECDIS: Second Event Interrupt Disable 0 = No effect. 1 = The second periodic interrupt is disabled.  TIMDIS: Time Event Interrupt Disable 0 = No effect. 1 = The selected time event interrupt is disabled.  CALDIS: Calendar Event Interrupt Disable 0 = No effect. 1 = The selected calendar event interrupt is disabled. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 – – – CALDIS TIMDIS SECDIS ALRDIS ACKDIS

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 144 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

15.6.11 RTC Interrupt Mask Register

Name: RTC_IMR Address: 0xFFFFFED8 Access: Read-only  ACK: Acknowledge Update Interrupt Mask 0 = The acknowledge for update interrupt is disabled. 1 = The acknowledge for update interrupt is enabled.  ALR: Alarm Interrupt Mask 0 = The alarm interrupt is disabled. 1 = The alarm interrupt is enabled.  SEC: Second Event Interrupt Mask 0 = The second periodic interrupt is disabled. 1 = The second periodic interrupt is enabled.  TIM: Time Event Interrupt Mask 0 = The selected time event interrupt is disabled. 1 = The selected time event interrupt is enabled.  CAL: Calendar Event Interrupt Mask 0 = The selected calendar event interrupt is disabled. 1 = The selected calendar event interrupt is enabled. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 ––– C AL T IM S EC A LR A CK

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 145 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

15.6.12 RTC Valid Entry Register

Name: RTC_VER Address: 0xFFFFFEDC Access: Read-only  NVTIM: Non-valid Time 0 = No invalid data has been detected in RTC_TIMR (Time Register). 1 = RTC_TIMR has contained invalid data since it was last programmed.  NVCAL: Non-valid Calendar 0 = No invalid data has been detected in RTC_CALR (Calendar Register). 1 = RTC_CALR has contained invalid data since it was last programmed.  NVTIMALR: Non-valid Time Alarm 0 = No invalid data has been detected in RTC_TIMALR (Time Alarm Register). 1 = RTC_TIMALR has contained invalid data since it was last programmed.  NVCALALR: Non-valid Calendar Alarm 0 = No invalid data has been detected in RTC_CALALR (Calendar Alarm Register). 1 = RTC_CALALR has contained invalid data since it was last programmed. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 –––– N VCALALR N VTIMALR N VCAL N VTIM

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 146 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 16. Periodic Interval Timer (PIT)

16.1 Description

The Periodic Interval Timer (PIT) provides the operating system’s scheduler interrupt. It is designed to offer maximum accuracy and efficient management, even for systems with long response time.

16.2 Embedded Characteristics

  • 20-bit Programmable Counter plus 12-bit Interval Counter
  • Reset-on-read Feature
  • Both Counters Work on Master Clock/16
  • A M B A™-compliant Interface – Interfaces to the ARM® Advanced Peripheral Bus

16.3 Block Diagram

Figure 16-1. Periodic Interval Timer 20-bit Counter MCK/16 PIV PIT_MR CPIV PIT_PIVR PICNT 12-bit Adder read PIT_PIVR CPIV PICNTPIT_PIIR PITSPIT_SR set reset PITIEN PIT_MR pit_irq 1 0 MCK Prescaler

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

16.4 Functional Description

The Periodic Interval Timer aims at providing periodic interrupts for use by operating systems. The PIT provides a programmable overflow counter and a reset-on-read feature. It is built around two counters: a 20-bit CPIV counter and a 12-bit PICNT counter. Both counters work at Master Clock /16. The first 20-bit CPIV counter increments from 0 up to a programmable overflow value set in the field PIV of the Mode Register (PIT_MR). When the counter CPIV reaches this value, it resets to 0 and increments the Periodic Interval Counter, PICNT. The status bit PITS in the Status Regis- ter (PIT_SR) rises and triggers an interrupt, provided the interrupt is enabled (PITIEN in PIT_MR). Writing a new PIV value in PIT_MR does not reset/restart the counters. When CPIV and PICNT values are obtained by reading the Periodic Interval Value Register (PIT_PIVR), the overflow counter (PICNT) is rese t and the PITS is cleared, thus acknowledging the interrupt. The value of PICNT gives the number of periodic intervals elapsed since the last read of PIT_PIVR. When CPIV and PICNT values are obtained by reading the Periodic Interval Image Register (PIT_PIIR), there is no effect on the counters CPIV and PICNT, nor on the bit PITS. For exam- ple, a profiler can read PIT_PIIR without clearing any pending interrupt, whereas a timer interrupt clears the interrupt by reading PIT_PIVR. The PIT may be enabled/disabled using the PITE N bit in the PIT_MR register (disabled on reset). The PITEN bit only becomes effective when the CPIV value is 0. Figure 16-2 illustrates the PIT counting. After the PIT Enable bit is re set (PITEN= 0), the CPIV goes on counting until the PIV value is reached, and is then reset. PIT restarts counting, only if the PITEN is set again. The PIT is stopped when the core enters debug state.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Figure 16-2. Enabling/Disabling PIT with PITEN MCK Prescaler PIVPIV - 10 PITEN CPIV 1 restarts MCK Prescaler 0 1 APB cycle read PIT_PIVR 0PICNT PITS (PIT_SR) MCK APB Interface APB cycle

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

16.5 Periodic Interval Time r (PIT) User Interface

Table 16-1. Register Mapping Offset Register Name Access Reset 0x00 Mode Register PIT_MR Read-write 0x000F_FFFF 0x04 Status Register PIT_SR Read-only 0x0000_0000 0x08 Periodic Interval Value Register PIT_PIVR Read-only 0x0000_0000 0x0C Periodic Interval Image Register PIT_PIIR Read-only 0x0000_0000

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

16.5.1 Periodic Interval Timer Mode Register

Name: PIT_MR Address: 0xFFFFFE30 Access: Read/Write  PIV: Periodic Interval Value Defines the value compared with the primary 20-bit counter of the Periodic Interval Timer (CPIV). The period is equal to (PIV + 1).  PITEN: Period Interval Timer Enabled 0 = The Periodic Interval Timer is disabled when the PIV value is reached. 1 = The Periodic Interval Timer is enabled.  PITIEN: Periodic Interval Timer Interrupt Enable 0 = The bit PITS in PIT_SR has no effect on interrupt. 1 = The bit PITS in PIT_SR asserts interrupt. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 –––– PIV 15 14 13 12 11 10 9 8 PIV 76543210 PIV

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

16.5.2 Periodic Interval Timer Status Register

Name: PIT_SR Address: 0xFFFFFE34 Access: Read-only  PITS: Periodic Interval Timer Status 0 = The Periodic Interval timer has not reached PIV since the last read of PIT_PIVR. 1 = The Periodic Interval timer has reached PIV since the last read of PIT_PIVR. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

16.5.3 Periodic Interval Timer Value Register

Name: PIT_PIVR Address: 0xFFFFFE38 Access: Read-only Reading this register clears PITS in PIT_SR.  CPIV: Current Periodic Interval Value Returns the current value of the periodic interval timer.  PICNT: Periodic Interval Counter Returns the number of occurrences of periodic intervals since the last read of PIT_PIVR. 31 30 29 28 27 26 25 24 PICNT 23 22 21 20 19 18 17 16 PICNT CPIV 15 14 13 12 11 10 9 8 CPIV 76543210 CPIV

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

16.5.4 Periodic Interval Timer Image Register

Name: PIT_PIIR Address: 0xFFFFFE3C Access: Read-only  CPIV: Current Periodic Interval Value Returns the current value of the periodic interval timer.  PICNT: Periodic Interval Counter Returns the number of occurrences of periodic intervals since the last read of PIT_PIVR. 31 30 29 28 27 26 25 24 PICNT 23 22 21 20 19 18 17 16 PICNT CPIV 15 14 13 12 11 10 9 8 CPIV 76543210 CPIV

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 17. Watchdog Timer (WDT)

17.1 Description

The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. It features a 12-bit down counter that allows a watchdog period of up to 16 seconds (slow clock at 32.768 kHz). It can generate a general reset or a processor reset only. In addition, it can be stopped while the processor is in debug mode or idle mode.

17.2 Embedded Characteristics

  • 12-bit Key-protected Programmable Counter
  • Provides Reset or Interrupt Signals to the System
  • Counter May Be Stopped While the Processor is in Debug State or in Idle Mode
  • A M B A ™-compliant Interface – Interfaces to the ARM® Advanced Peripheral Bus

17.3 Block Diagram

Figure 17-1. Watchdog Timer Block Diagram = 0 set resetread WDT_SR or reset wdt_fault (to Reset Controller) set reset WDFIEN wdt_int WDT_MR SLCK1/128 12-bit Down Counter Current Value WDD WDT_MR <= WDD WDV WDRSTT WDT_MR WDT_CR reload WDUNF WDERR reload write WDT_MR WDT_MR WDRSTEN

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

17.4 Functional Description

The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. It is supplied with VDDCORE. It restarts with initial values on processor reset. The Watchdog is built around a 12-bit down counter, which is loaded with the value defined in the field WDV of the Mode Register (WDT_MR). The Watchdog Timer uses the Slow Clock divided by 128 to establish the maximum Watchdog period to be 16 seconds (with a typical Slow Clock of 32.768 kHz). After a Processor Reset, the value of WDV is 0xFFF, corresponding to the maximum value of the counter with the external reset generation enabled (field WDRSTEN at 1 after a Backup Reset). This means that a default Watchdog is running at reset, i.e., at power-up. The user must either disable it (by setting the WDDIS bit in WD T_MR) if he does not expect to use it or must reprogram it to meet the maximum Watchdog period the application requires. The Watchdog Mode Register (WDT_MR) can be written only once. Only a processor reset resets it. Writing the WDT_MR register reloads the timer with the newly programmed mode parameters. In normal operation, the user reloads the Watchdog at regular intervals before the timer under- flow occurs, by writing the Control Register (WDT_CR) with the bit WDRSTT to 1. The Watchdog counter is then immediately reloaded from WDT_MR and restarted, and the Slow Clock 128 divider is reset and restarted. The WDT_CR register is write-protected. As a result, writing WDT_CR without the correct hard-coded key has no effect. If an underflow does occur, the “wdt_fault” signal to the Reset Controller is asserted if the bit WDRSTEN is set in the Mode Register (WDT_MR). Moreover, the bit WDUNF is set in the Watchdog Status Register (WDT_SR). To prevent a software deadlock that continuously triggers the Watchdog, the reload of the Watchdog must occur while the Watchdog counter is within a window between 0 and WDD, WDD is defined in the WatchDog Mode Register WDT_MR. Any attempt to restart the Watchdog while the Watchdog counter is between WDV and WDD results in a Watchdog error, even if the Watchdog is disabled. The bit WDERR is updated in the WDT_SR and the “wdt_fault” signal to the Reset Controller is asserted. Note that this feature can be disabled by programming a WDD value greater than or equal to the WDV value. In such a configuration, restarti ng the Watchdog Timer is permitted in the whole range [0; WDV] and does not generate an error. This is the default configuration on reset (the WDD and WDV values are equal). The status bits WDUNF (Watchdog Underflow ) and WDERR (Watchdog Error) trigger an inter- rupt, provided the bit WDFIEN is set in the mode register. The signal “wdt_fault” to the reset controller causes a Watchdog reset if the WDRSTEN bit is set as already explained in the reset controller programmer Datasheet. In that case, the processor and the Watchdog Timer are reset, and the WDERR and WDUNF flags are reset. If a reset is generated or if WDT_SR is read, the status bits are reset, the interrupt is cleared, and the “wdt_fault” signal to the reset controller is deasserted. Writing the WDT_MR reloads and restarts the down counter. While the processor is in debug state or in idle mode, the counter may be stopped depending on the value programmed for the bits WDIDLEHLT and WDDBGHLT in the WDT_MR.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Figure 17-2. Watchdog Behavior WDV WDD WDT_CR = WDRSTT Watchdog Fault Normal behavior Watchdog Error Watchdog Underflow FFF if WDRSTEN is 1 if WDRSTEN is 0 Forbidden Window Permitted Window

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

17.5 Watchdog Timer (WDT) User Interface

Table 17-1. Register Mapping Offset Register Name Access Reset 0x00 Control Register WDT_CR Write-only - 0x04 Mode Register WDT_MR Read-write Once 0x3FFF_2FFF 0x08 Status Register WDT_SR Read-only 0x0000_0000

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

17.5.1 Watchdog Timer Control Register

Name: WDT_CR Address: 0xFFFFFE40 Access: Write-only  WDRSTT: Watchdog Restart 0: No effect. 1: Restarts the Watchdog. K E Y : P a s s w o r d Should be written at value 0xA5. Writing any other value in this field aborts the write operation. 31 30 29 28 27 26 25 24 KEY 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

17.5.2 Watchdog Timer Mode Register

Name: WDT_MR Address: 0xFFFFFE44 Access: Read-write Once  WDV: Watchdog Counter Value Defines the value loaded in the 12-bit Watchdog Counter.  WDFIEN: Watchdog Fault Interrupt Enable 0: A Watchdog fault (underflow or error) has no effect on interrupt. 1: A Watchdog fault (underflow or error) asserts interrupt.  WDRSTEN: Watchdog Reset Enable 0: A Watchdog fault (underflow or error) has no effect on the resets. 1: A Watchdog fault (underflow or error) triggers a Watchdog reset.  WDRPROC: Watchdog Reset Processor 0: If WDRSTEN is 1, a Watchdog fault (underflow or error) activates all resets. 1: If WDRSTEN is 1, a Watchdog fault (underflow or error) activates the processor reset.  WDD: Watchdog Delta Value Defines the permitted range for reloading the Watchdog Timer. If the Watchdog Timer value is less than or equal to WDD, writing WDT_CR with WDRSTT = 1 restarts the timer. If the Watchdog Timer value is greater than WDD, writing WDT_CR with WDRSTT = 1 causes a Watchdog error.  WDDBGHLT: Watchdog Debug Halt 0: The Watchdog runs when the processor is in debug state. 1: The Watchdog stops when the processor is in debug state.  WDIDLEHLT: Watchdog Idle Halt 0: The Watchdog runs when the system is in idle mode. 1: The Watchdog stops when the system is in idle state.  WDDIS: Watchdog Disable 0: Enables the Watchdog Timer. 1: Disables the Watchdog Timer. 31 30 29 28 27 26 25 24 WDIDLEHLT WDDBGHLT WDD 23 22 21 20 19 18 17 16 WDD 15 14 13 12 11 10 9 8 WDDIS WDRPROC WDRSTEN WDFIEN WDV 76543210 WDV

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

17.5.3 Watchdog Timer Status Register

Name: WDT_SR Address: 0xFFFFFE48 Access: Read-only  WDUNF: Watchdog Underflow 0: No Watchdog underflow occurred since the last read of WDT_SR. 1: At least one Watchdog underflow occurred since the last read of WDT_SR.  WDERR: Watchdog Error 0: No Watchdog error occurred since the last read of WDT_SR. 1: At least one Watchdog error occurred since the last read of WDT_SR. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 163 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 18. Shutdown Controller (SHDWC)

18.1 Description

The Shutdown Controller controls the pow er supplies VDDIO and VDDCORE and the wake-up detection on debounced input lines.

18.2 Embedded Characteristics

  • Shutdown and Wake-up Logic – Software Assertion of the SHDW Output Pin – Programmable De-assertion from the WKUP Input Pins
  • AMBA-compliant Interface – Interfaces to the ARM Advanced Peripheral Bus

18.3 Block Diagram

Figure 18-1. Shutdown Controller Block Diagram

18.4 I/O Lines Description

SHDW_MR SHDW_MR SHDW_CR CPTWK0 WAKEUP0 RTCWK SHDW_SR SHDW_SR set set reset reset read SHDW_SR read SHDW_SR SLCK Table 18-1. I/O Lines Description Name Description Type WKUP0 Wake-up 0 input Input SHDN Shutdown output Output

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 164 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

18.5 Product Dependencies

18.5.1 Power Management

The Shutdown Controller is continuously clock ed by Slow Clock. The Power Management Con- troller has no effect on the behavior of the Shutdown Controller.

18.6 Functional Description

The Shutdown Controller manages the main power supply. To do so, it is supplied with VDDBU and manages wake-up input pins and one output pin, SHDN. A typical application connects the pin SHDN to the shutdown input of the DC/DC Converter pro- viding the main power supplies of the system, and especially VDDCORE and/or VDDIO. The wake-up inputs (WKUP0) connect to any push-buttons or signal that wake up the system. The software is able to control the pin S HDN by writing the Shutdown Control Register (SHDW_CR) with the bit SHDW at 1. The shutdow n is taken into account only 2 slow clock cycles after the write of SHDW_CR. This register is password-protected and so the value written should contain the correct key for the command to be taken into account. As a result, the system should be powered down. A level change on WKUP0 is used as wake-up. Wake-up is configured in the Shutdown Mode Register (SHDW_MR). The transition detector can be programmed to detect either a positive or negative transition or any level change on WKUP 0. The detection can also be disabled. Pro- gramming is performed by defining WKMODE0. Moreover, a debouncing circuit can be programmed for WKUP0. The debouncing circuit filters pulses on WKUP0 shorter than the programmed number of 16 SLCK cycles in CPTWK0 of the SHDW_MR register. If the programmed level change is detected on a pin, a counter starts. When the counter reaches the value programmed in the corresponding field, CPTWK0, the SHDN pin is released. If a new input change is detected before the counter reaches the corre- sponding value, the counter is stopped and cleared. WAKEUP0 of the Status Register (SHDW_SR) reports the detection of the programmed events on WKUP0 with a reset after the read of SHDW_SR. The Shutdown Controller can be programmed so as to activate the wake-up using the RTC alarm (the detection of the rising edge of the RTC alarm is synchronized with SLCK). This is done by writing the SHDW_MR register using the RTCWKEN field. When enabled, the detection of the RTC alarm is reported in the RTCWK bit of the SHDW_SR Status register. It is reset after the read of SHDW_SR. When using the RTC alarm to wake up the system, the user must ensure that the RTC alarm status flag is cleared before shutting down the system.Otherwise, no rising edge of the status flag may be detected and the wake-up fails fail.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 165 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

18.7 Shutdown Controller (SHDWC) User Interface

Table 18-2. Register Mapping Offset Register Name Access Reset 0x00 Shutdown Control Register SHDW_CR Write-only - 0x04 Shutdown Mode Register SHDW_MR Read-write 0x0000_0303 0x08 Shutdown Status Register SHDW_SR Read-only 0x0000_0000

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 166 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

18.7.1 Shutdown Control Register

Name: SHDW_CR Address: 0xFFFFFE10 Access: Write-only  SHDW: Shutdown Command 0 = No effect. 1 = If KEY is correct, asserts the SHDN pin. K E Y : P a s s w o r d Should be written at value 0xA5. Writing any other value in this field aborts the write operation. 31 30 29 28 27 26 25 24 KEY 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 167 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

18.7.2 Shutdown Mode Register

Name: SHDW_MR Address: 0xFFFFFE14 Access: Read/Write  WKMODE0: Wake-up Mode 0  CPTWK0: Counter on Wake-up 0 Defines the number of 16 Slow Clock cycles, the level detection on the corresponding input pin shall last before the wake- up event occurs. Because of the internal synchronization of WKUP0, the SHDN pin is released (CPTWK x 16 + 1) Slow Clock cycles after the event on WKUP.  RTCWKEN: Real-time Clock Wake-up Enable 0 = The RTC Alarm signal has no effect on the Shutdown Controller. 1 = The RTC Alarm signal forces the de-assertion of the SHDN pin. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 –– – – 76543210 CPTWK0 – – WKMODE0 WKMODE[1:0] Wake-up Input Transition Selection 0 0 None. No detection is performed on the wake-up input 0 1 Low to high level 1 0 High to low level 1 1 Both levels change

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 168 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

18.7.3 Shutdown Status Register

Name: SHDW_SR Address: 0xFFFFFE18 Access: Read-only  WAKEUP0: Wake-up 0 Status 0 = No wake-up event occurred on the corresponding wake-up input since the last read of SHDW_SR. 1 = At least one wake-up event occurred on the corresponding wake-up input since the last read of SHDW_SR.  RTCWK: Real-time Clock Wake-up 0 = No wake-up alarm from the RTC occurred since the last read of SHDW_SR. 1 = At least one wake-up alarm from the RTC occurred since the last read of SHDW_SR. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 169 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 19. General Purpose Backup Registers (GPBR)

19.1 Description

The System Controller embeds Four general-purpose backup registers.

19.2 Embedded Characteristics

  • Four 32-bit General Purpose Backup Registers

19.3 General Purpose Backup Regist ers (GPBR) User Interface

Table 19-1. Register Mapping Offset Register Name Access Reset 0x0 General Purpose Backup Register 0 SYS_GPBR0 Read-write – 0xc General Purpose Backup Register 3 SYS_GPBR3 Read-write –

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 170 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

19.3.1 General Purpose Backup Register x

Name: SYS_GPBRx Address: 0xFFFFFE60 Access: Read-write  GPBR_VALUE: Value of GPBR x 31 30 29 28 27 26 25 24 GPBR_VALUE 23 22 21 20 19 18 17 16 GPBR_VALUE 15 14 13 12 11 10 9 8 GPBR_VALUE 76543210 GPBR_VALUE

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 171 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 20. Slow Clock Controller (SCKC)

20.1 Description

The System Controller embeds a Slow Clock Controller. The slow clock can be generated either by an external 32,768 Hz crystal oscillator or by the on- chip 32 kHz RC oscillator. The 32,768 Hz crystal oscillator can be bypassed by setting the bit OSC32BYP to accept an external slow clock on XIN32. The internal 32 kHz RC oscillator and the 32,768 Hz oscillator can be enabled by setting to 1, respectively, RCEN bit and OSC32EN bit in the System Controller user interface. The OSCSEL command selects the slow clock source.

20.2 Embedded Characteristics

  • 32 kHz RC Oscillator or 32,768 Hz Oscillator Selector
  • V D D B U P o w e r e d

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 172 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

20.3 Block Diagram

Figure 20-1. Block Diagram RCEN, OSC32EN, OSCSEL and OSC32BYP bits are located in the Slow Clock Control Register (SCKCR) located at address 0xFFFFFE50 in the backed up part of the System Controller and so are preserved while VDDBU is present. After a VDDBU power on reset, the default configuration is RCEN = 1, OSC32EN = 0 and OSCSEL = 0, allowing the system to start on the internal 32 kHz RC oscillator. The programmer controls the slow clock switching by software and so must take precautions during the switching phase.

20.3.1 Switch from Internal 32 kHz RC Oscillator to the 32,768 Hz Crystal Oscillator

To switch from the internal 32 kHz RC oscillator to the 32,768 Hz crystal oscillator, the program- mer must execute the following sequence:

  • Switch the master clock to a source different from slow clock (PLL or Main Oscillator) through the Power Management Controller.
  • Enable the 32,768 Hz oscillator by setting the bit OSC32EN to 1.
  • Wait 32,768 Hz Startup Time for clock stabilization (software loop).
  • Switch from internal 32 kHz RC oscillator to 32,768 Hz oscillator by setting the bit OSCSEL to 1.
  • Wait 5 slow clock cycles for internal resynchronization.
  • Disable the 32 kHz RC oscillator by setting the bit RCEN to 0.

20.3.2 Bypass the 32,768 Hz Oscillator

The following steps must be added to bypass the 32,768 Hz oscillator:

  • An external clock must be connected on XIN32.
  • Enable the bypass path OSC32BYP bit set to 1.
  • Disable the 32,768 Hz oscillator by setting the bit OSC32EN to 0. On Chip RC OSC Slow Clock SLCK XIN32 XOUT32 Slow Clock Oscillator OSC32EN RCEN OSCSEL OSC32BYP

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 173 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

20.3.3 Switch from the 32,768 Hz Crystal Oscillator to Internal 32 kHz RC Oscillator

The same procedure must be followed to switch from a 32,768 Hz crystal to the internal 32 kHz RC oscillator:

  • Switch the master clock to a source different from slow clock (PLL or Main Oscillator).
  • Enable the internal 32 kHz RC oscillator for low power by setting the bit RCEN to 1
  • Wait internal 32 kHz RC oscillator Startup Time for clock stabilization (software loop).
  • Switch from 32,768 Hz oscillator to internal 32 kHz RC oscillator by setting the bit OSCSEL to 0.
  • Wait 5 slow clock cycles for internal resynchronization.
  • Disable the 32,768 Hz oscillator by setting the bit OSC32EN to 0.

20.4 Slow Clock Configurati on (SCKC) User Interface

Table 20-1. Register Mapping Offset Register Name Access Reset 0x0 Slow Clock Configuration Register SCKC_CR Read-write 0x0000_0001

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 174 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

20.4.1 Slow Clock Configuration Register

Name: SCKC_CR Address: 0xFFFFFE50 Access: Read-write Reset: 0x0000_0001  RCEN: Internal 32 kHz RC Oscillator 0: 32 kHz RC oscillator is disabled. 1: 32 kHz RC oscillator is enabled.  OSC32EN: 32,768 Hz Oscillator 0: 32,768 Hz oscillator is disabled. 1: 32,768 Hz oscillator is enabled.  OSC32BYP: 32,768Hz Oscillator Bypass 0: 32,768 Hz oscillator is not bypassed. 1: 32,768 Hz oscillator is bypassed, accept an external slow clock on XIN32.  OSCSEL: Slow Clock Selector 0 (RC): Slow clock is internal 32 kHz RC oscillator. 1 (XTAL): Slow clock is 32,768 Hz oscillator. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76 5 43210 – – – – OSCSEL OSC32BYP OSC32EN RCEN

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 175 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 21. Clock Generator

21.1 Description

The Clock Generator User Interface is embedded within the Power Management Controller and is described in Section 22.12 ”Power Management Controller (PMC) User Interface” . However, the Clock Generator registers are named CKGR_.

21.2 Embedded Characteristics

The Clock Generator is made up of:

  • One Low Power 32768 Hz Slow Clock Oscillator with bypass mode
  • One Low-Power 32 kHz RC oscillator
  • One Low-Power 12 MHz RC oscillator
  • One 16 MHz Main Oscillator, which can be bypassed.
  • One 400 to 800 MHz programmable PLLA, capable to provide the clock MCK to the processor, and to the peripherals. This PLL has an input divider to offer a wider range of output frequencies from the 16 MHz input, the only limitation being the lowest input frequency shall be higher or equal to 2 MHz.
  • One 100 MHz programmable PLLB dedicated to USB Full Speed operations. This PLL has an input divider to offer a wider range of output frequencies from the 16 MHz input, the only limitation being the lowest input frequency shall be higher or equal to 2 MHz.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 176 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

21.3 Block Diagram

Figure 21-1. Clock Generator Block Diagram Pow er Management C ontroller XIN XOUT Main Clock MAINCK Co n t r o lSt at u s PLLA and Divider PLLA Clock PLLACK 16M Main Oscillator On Chip 32K R C OSC Sl o w Cl o ck SLCK XIN32 XOUT32 S low C lock Oscillator Cl o ck Gen er at o r RCENOSCSEL OSC32EN OSC32BYP On Chip 12M R C OSC MOS CR CE N M OSCSEL PLLB and Divider PLLBCK USB Clocks

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 177 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

21.4 Slow Clock Selection

The slow clock can be generated either by an external 32,768 Hz crystal or by the on-chip 32 kHz RC oscillator. The 32,768 Hz crystal oscillator can be bypassed by setting the bit OSC32BYP to accept an external slow clock on XIN32. The internal 32 kHz RC oscillator and the 32,768 Hz oscillator can be enabled by setting to 1, respectively, RCEN bit and OSC32EN bit in the System Controller user interface. The OSCSEL command selects the slow clock source. Figure 21-2. Slow Clock RCEN, OSC32EN,OSCSEL and OSC32BYP bits are located in the Slow Clock Control Register (SCKCR) located at address 0xFFFFFE50 in the backed up part of the System Controller and so are preserved while VDDBU is present. After a VDDBU power on reset, the default configuration is RCEN = 1, OSC32EN = 0 and OSC- SEL = 0, BYPASS = 0, allowing the system to start on the internal 32 kHz RC oscillator. The programmer controls the slow clock switching by software and so must take precautions during the switching phase.

21.4.1 Switch from Internal 32 kHz RC Oscillator to the 32,768 Hz Crystal

To switch from internal 32 kHz RC oscillator to the 32,768 Hz crystal, the programmer must exe- cute the following sequence:

  • Switch the master clock to a source different from slow clock (PLL or Main Oscillator) through the Power Management Controller.
  • Enable the 32,768 Hz oscillator by setting the bit OSC32EN to 1.
  • Wait 32,768 Hz Startup Time for clock stabilization (software loop).
  • Switch from internal 32 kHz RC to 32,768 Hz oscillator by setting the bit OSCSEL to 1.
  • Wait 5 slow clock cycles for internal resynchronization.
  • Disable the 32 kHz RC oscillator by setting the bit RCEN to 0.
  • Switch the master clock back to the slow clock domain On Chip RC OSC Slow Clock SLCK XIN32 XOUT32 Slow Clock Oscillator OSC32EN RCEN OSCSEL OSC32BYP

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 178 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

21.4.2 Bypass the 32768 Hz Oscillator

The following step must be added to bypass the 32768 Hz Oscillator.

  • An external clock must be connected on XIN32.
  • Enable the bypass path OSC32BYP bit set to 1.
  • Disable the 32768 Hz oscillator by setting the bit OSC32EN to 0.

21.4.3 Switch from the 32,768 Hz Crystal to Internal 32 kHz RC Oscillator

The same procedure must be followed to switch from a 32,768 Hz crystal to the internal 32 kHz RC oscillator.

  • Switch the master clock to a source different from slow clock (PLL or Main Oscillator).
  • Enable the internal 32 kHz RC oscillator for low power by setting the bit RCEN to 1
  • Wait internal 32 kHz RC Startup Time for clock stabilization (software loop).
  • Switch from 32768 Hz oscillator to inte rnal RC by setting the bit OSCSEL to 0.
  • Wait 5 slow clock cycles for internal resynchronization.
  • Disable the 32768 Hz oscillator by setting the bit OSC32EN to 0.
  • Switch the master clock back to the slow clock domain

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 179 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

21.4.4 Slow Clock Configuration Register

Name: SCKCR Address: 0xFFFFFE50 Access: Read-write Reset: 0x0000_0001  RCEN: Internal 32 kHz RC 0: 32 kHz RC is disabled 1: 32 kHz RC is enabled  OSC32EN: 32768 Hz oscillator 0: 32768 Hz oscillator is disabled 1: 32768 Hz oscillator is enabled  OSC32BYP: 32768 Hz oscillator bypass 0: 32768 Hz oscillator is not bypassed 1: 32768 Hz oscillator is bypassed, accept an external slow clock on XIN32  OSCSEL: Slow clock selector 0: Slow clock is internal 32 kHz RC 1: Slow clock is 32768 Hz oscillator 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 –––– O SCSEL O SC32BYP O SC32EN R CEN

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 180 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

21.5 Main Clock

Figure 21-3. Main Clock Block Diagram The Main Clock has two sources:

  • 12 MHz Fast RC Oscillator which starts very quickly and is used at startup
  • 3 to 20 MHz Crystal Oscillator, which can be bypassed 21.5.1 12 MHz Fast RC Oscillator After reset, the 12 MHz Fast RC Oscillator is enabled and it is selected as the source of MCK. MCK is the default clock selected to start up the system. Please refer to the “DC Characteristics” section of the product datasheet. The software can disable or enable the 12 MHz Fast RC Oscillator with the MOSCRCEN bit in the Clock Generator Main Oscillator Register (CKGR_MOR). When disabling the Main Clock by clearing the MOSCRCEN bit in CKGR_MOR, the MOSCRCS bit in the Power Management Controller Status Register (PMC_SR) is automatically cleared, indicating the Main Clock is off. Setting the MOSCRCS bit in the Power Management Controller Interrupt Enable Register (PMC_IER) can trigger an interrupt to the processor. XIN XOUT MOSCXTEN MOSCXTCNT MOSCXTS Main Clock Frequency Counter MAINF MAINRDY SLCK Slow Clock 3-20 MHz Crystal Oscillator 3-20 MHz Crystal Oscillator Counter MOSCRCEN

12 MHz

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 181 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 21.5.2 3 to 20 MHz Crystal Oscillator After reset, the 3 to 20 MHz Crystal Oscillator is disabled and it is not selected as the source of MAINCK. The user can select the 3 to 20 MHz crystal oscillator to be the source of MAINCK, as it provides a more accurate frequency. The software enables or disables the main oscillator so as to reduce power consumption by clearing the MOSCXTEN bit in the Main Oscillator Register (CKGR_MOR). When disabling the main oscillator by clearing the MOSCXTEN bit in CKGR_MOR, the MOSCXTS bit in PMC_SR is automatically cleared, indicating the Main Clock is off. When enabling the main oscillator, the user must initiate the main oscillator counter with a value corresponding to the startup time of the oscillat or. This startup time depends on the crystal fre- quency connected to the oscillator. When the MOSCXTEN bit and the MOSCXTCNT are written in CKGR_MOR to enable the main oscillator, the MOSCXTS bit in the Power Management Controller Status Register (PMC_SR) is cleared and the counter starts counting down on the slow clock divided by 8 from the MOSCX- TCNT value. Since the MOSCXTCNT value is c oded with 8 bits, the maximum startup time is about 62 ms. When the counter reaches 0, the MOSCXTS bit is set, indicating that the main clock is valid. Setting the MOSCXTS bit in PMC_IMR can trigger an interrupt to the processor.

21.5.3 Main Clock Oscillator Selection

The user can select either the 12 MHz Fast RC Oscillator or the 3 to 20 MHz Crystal Oscillator to be the source of Main Clock. The advantage of the 12 MHz Fast RC Oscillator is to have fast startup time, this is why it is selected by default (to start up the system) and when entering in Wait Mode. The advantage of the 3 to 20 MHz Crystal Oscillator is that it is very accurate. The selection is made by writing the MOSCSEL bit in the Main Oscillator Register (CKGR_MOR). The switch of the Main Clock source is glitch free, so there is no need to run out of SLCK, PLLACK or UPLLCK in order to change the selection. The MOSCSELS bit of the Power Management Controller Status Register (PMC_SR) allows knowing when the switch sequence is done. Setting the MOSCSELS bit in PMC_IMR can trigger an interrupt to the processor.

21.5.4 Software Sequence to Detect the Presence of Fast Crystal

The frequency meter carried on CKGR_MCFR register is operating on the selected main clock and not on fast crystal clock nor fast RC Oscillator clock. Therefore, to check for the presence of a fast cr ystal clock, it is necessary to switch the main clock on fast crystal clock. The following software sequence order must be followed: – MCK must select the slow clock (CSS=0 in PLL_MCKR register). – Wait for the MCKRDY flag in PLL_SR register to be 1. – The fast crystal must be enabled by programming 1 in MOSCXTEN field in CKGR_MOR register with MOSCXTST field being programmed to the appropriate value (see electrical characteristics chapter).

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 182 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 – Wait for the MOSCXTS flag to be 1 in PLL_SR register to get the end of startup period of the fast crystal oscillator. – Then, MOSCSEL must be programmed to 1 in CKGR_MOR register to select fast main crystal oscillator for main clock. – The MOSCSEL must be read until its value equals 1. – Then MOSCSELS status flag must be checked in PLL_SR register. At this point, 2 cases may occur (either MOSCSELS = 0 or MOSCSELS = 1). – If MOSCSELS = 1, there is a valid crystal connected and its frequency can be determined by initiating a frequency measure by programming RCMEAS in CKGR_MCFR register. – If MOSCSELS = 0, there is no fast crystal clock (either no crystal connected or an out of specification crystal clock). – A frequency measure can reinforce this status by initiating a frequency measure by programming RCMEAS in CKGR_MCFR register. – If MOSCSELS = 0, the selection of the main clock must be programmed back to main RC oscillator by writing MOSCSEL to 0 prior to disable the fast crystal oscillator. – If MOSCSELS = 0, the crystal oscillato r can be disabled (MOSCXTEN = 0 in CKGR_MOR register).

21.5.5 Main Clock Frequency Counter

The device features a Main Clock frequency counter that provides the frequency of the Main Clock. The Main Clock frequency counter is reset and starts incrementing at the Main Clock speed after the next rising edge of the Slow Clock in the following cases:

  • when the 12 MHz Fast RC Oscillator clock is selected as the source of Main Clock and when this oscillator becomes stable (i.e., when the MOSCRCS bit is set)
  • when the 3 to 20 MHz Crystal Oscillator is sele cted as the source of Main Clock and when this oscillator becomes stable (i.e., when the MOSCXTS bit is set)
  • when the Main Clock Oscillator selection is modified Then, at the 16th falling edge of Slow Clock, the MAINFRDY bit in the Clock Generator Main Clock Frequency Register (CKGR_MCFR) is set and the counter stops counting. Its value can be read in the MAINF field of CKGR_MCFR and gi ves the number of Main Clock cycles during 16 periods of Slow Clock, so that the frequency of the 12 MHz Fast RC Oscillator or 3 to 20 MHz Crystal Oscillator can be determined.

21.6 Divider and PLL Block

The PLL embeds an input divider to increase the accuracy of the resulting clock signals. How- ever, the user must respect the PLL minimum input frequency when programming the divider. Figure 21-4 shows the block diagram of the divider and PLL block.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 183 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Figure 21-4. Divider and PLL Block Diagram

21.6.1 Divider and Phase Lock Loop Programming

The divider can be set between 1 and 255 in steps of 1. When a divider field (DIV) is set to 0, the output of the corresponding divider and the PLL out put is a continuous signal at level 0. On reset, each DIV field is set to 0, thus the corresponding PLL input clock is set to 0. The PLL allows multiplication of the divider’s outputs. The PLL clock signal has a frequency that depends on the respective source signal frequency and on the parameters DIV and MUL. The factor applied to the source signal frequency is (MUL + 1)/DIV. When MUL is written to 0, the corresponding PLL is disabled and its power consumption is saved. Re-enabling the PLL can be performed by writing a value higher than 0 in the MUL field. Whenever the PLL is re-enabled or one of its parameters is changed, the LOCK bit (LOCKA or LOCKB) in PMC_SR is automatically cleared. The values written in the PLLCOUNT field (PLLA- COUNT or PLLBCOUNT) in CKGR_PLLR (CKGR_PLLAR or CKGR_PLLBR), are loaded in the PLL counter. The PLL counter then decrements at the speed of the Slow Clock until it reaches 0. At this time, the LOCK bit is set in PMC_SR and can trigger an interrupt to the processor. The user has to load the number of Slow Clock cycles required to cover the PLL transient time into the PLLCOUNT field. During the PLLA or PLLB initialization, the PMC_PLLICPR register must be programmed correctly. The PLLA clock can be divided by 2 by writing the PLLADIV2 bit in PMC_MCKR register. Divider B DIVB PLL B MULB DIVA PLL A Co u n t er PLLBCOUNT LOCKB PLL A Co u n t er PLLACOUNT LOCKA MULA OUTB OUTA SLCK PLLA CK PLLBCK Divider A PLL B MAINCK

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 184 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 22. Power Management Controller (PMC)

22.1 Description

The Power Management Controller (PMC) optimizes power consumption by controlling all sys- tem and user peripheral clocks. The PMC enables/disables the clock inputs to many of the peripherals and the Core.

22.2 Embedded Characteristics

The Power Management Controller provides all the clock signals to the system. PMC input clocks:

  • PLLACK: From PLLA
  • PLLBCK: From PLLB and dedicated to USB clock generation.
  • SLCK: slow clock from external 32 kHz oscillator or internal 32 kHz RC
  • MAINCK: Main Clock from external 16 MHz oscillator or internal 12 MHz RC PMC output clocks:
  • Processor Clock PCK.
  • Master Clock MCK, in particular to the Matrix, the memory interfaces, the peripheral bridge. The divider can be 2, 3 or 4.
  • Each peripheral embeds its own divider, programmable in the PMC User Interface.
  • 133 MHz DDR system clock Note: DDR system clock is not available when Ma ster Clock (MCK) equals Processor Clock (PCK).
  • LCD pixel clock that can use DDR system clock or MCK, the choice is done in the LCD user interface.
  • UHP Clock (UHPCK), required by USB Host Port operations.
  • UDP Clock (UDPCK), required by USB Device Port operations.
  • Two programmable clock outputs: PCK0 and PCK1 This allows software control of five flexible operating modes:
  • Normal Mode, processor and peripherals running at a programmable frequency
  • Idle Mode, processor stopped waiting for an interrupt
  • Slow Clock Mode, processor and peripherals running at low frequency
  • Standby Mode, mix of Idle and Backup Mode, peripheral running at low frequency, processor stopped waiting for an interrupt
  • Backup Mode, Main Power Supplies off, VDDBU powered by a battery

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 185 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

22.3 Block Diagram

Figure 22-1. General Clock Block Diagram

22.4 Master Clock Controller

The Master Clock Controller provides selection and division of the Master Clock (MCK). MCK is the clock provided to all the peripherals and the memory controller. The Master Clock is selected from one of the clocks provided by the Clock Generator. Selecting the Slow Clock provides a Slow Clock signal to the whole device. Selecting the Main Clock saves power consumption of the PLLs. The Master Clock Controller is made up of a cloc k selector and a prescaler. It also contains a Master Clock divider which allows the processor clock to be faster than the Master Clock. The Master Clock selection is made by writi ng the CSS field (Clock Source Selection) in PMC_MCKR (Master Clock Register). The prescaler supports the division by a power of 2 of the selected clock between 1 and 64. The PRES field in PMC_MCKR programs the prescaler. Each time PMC_MCKR is written to define a ne w Master Clock, the MCKR DY bit is cleared in PMC_SR. It reads 0 until the Master Clock is established. Then, the MCKRDY bit is set and can trigger an interrupt to the processor. This feature is useful when switching from a high-speed clock to a lower one to inform the software when the change is actually done.

22.5 Processor Clock Controller

The PMC features a Processor Clock Controller (PCK) that implements the Processor Idle Mode. The Processor Clock can be disabled by writing the System Clock Disable Register (PMC_SCDR). The status of this clock (at least for debug purposes) can be read in the System Clock Status Register (PMC_SCSR). The Processor Clock (PCK) is enabled after a reset and is automatically re-enabled by any enabled interrupt. The Processor Idle Mode is ac hieved by disabling the Processor Clock and entering Wait for Interrupt Mode. The Processor Clock is automatically re-enabled by any 2x MCK DDRCK/2 MCK periph_clk[..] int SLCK MAINCK PLLACK PCKProcessor Clock Controller Master Clock Controller Peripherals Clock Controller ON/OFF /1 /2 /3 /4 SLCK MAINCK Prescaler /1,/2,/4,...,/64 Programmable Clock Controller pck[..] ON/OFF /1,/2 Divider X /1 /1.5 /2 Divider PLLBCK PLLBCK Prescaler

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 186 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 enabled fast or normal interrupt, or by the reset of the product. Note: The ARM Wait for Interrupt mode is entered by a CP15 coprocessor operation. Refer to the Atmel application note, Optimiz- ing Power Consumption for AT91SAM9261-based Systems, lit. number 6217. (http://www.atmel.com/dyn/resources/prod_documents/doc6217.pdf) When the Processor Clock is disabled, the current instruct ion is finished before the clock is stopped, but this does not pre- vent data transfers from other masters of the system bus.

22.6 USB Device and Host Clocks

The USB Source Clock is always generated from the PLL B output. If using the USB, the user must program the PLL to generate a 48 MHz, a 96 MHz or a 192 MHz signal with an accuracy of ± 0.25% depending on the USBDIV bit in CKGR_PLLBR. When the PLL B output is stable, i.e., the LOCKB is set: The USB host clock can be enabled by setting the UHP bit in PMC_SCER. To save power on this peripheral when it is not used, the user can set the UHP bit in PMC_SCDR. The UHP bit in PMC_SCSR gives the activity of this clock. The USB host port require both the 12/48 MHz signal and the Master Clock. The Master Clock may be controlled via the Master Clock Controller. The USB device clock can be enabled by setting the UDP bit in PMC_SCER. To save power on this peripheral when it is not used, the user can set the UDP bit in PMC_SCDR. The UDP bit in PMC_SCSR gives the activity of this clock. The USB device port require both the 48 MHz signal and the Master Clock. The Master Clock may be controlled via the Master Clock Controller. USB Clock Controller

22.7 LP-DDR/DDR2 Clock

The Power Management Controller controls the clocks of the DDR memory. The DDR clock can be enabled and disabled wit h DDRCK bit respectively in PMC_SCER and PMC_SDER registers. At reset DDR clock is disabled to save power consumption. In the case MDIV = ‘00’, (PCK = MCK) and DDRCK clock is not available. If Input clock is PLLACK/PLLADIV2 the DDR Controller can drive DDR2 and LP-DDR at up to 133MHz with MDIV = ‘11’. To save PLLA power consumption, the user can choose UPLLCK an Input clock for the system. In this case the DDR Controller can drive LD-DDR at up to 120MHz.

22.8 Peripheral Clock Controller

The Power Management Controller controls the cl ocks of each embedded peripheral by means of the Peripheral Clock Controller. The user can individually enable and disable the clock on the USB Source Clock UDP Clock (UDPCK) UDP USBDIV Divider /1,/2,/4 UHP Clock (UHPCK) UHP

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 187 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 peripherals and select a division factor from MCK. This is done through the Peripheral Control Register (PMC_PCR). In order to save power consumption, the division factor can be 1, 2, 4 or 8. PMC_PCR is a regis- ter that features a command and acts like a mailbo x. To write the division factor on a particular peripheral, the user needs to write a WRITE comm and, the peripheral ID and the chosen divi- sion factor. To read the current division factor on a particular peripheral, the user just needs to write the READ command and the peripheral ID. Code Example to select divider 8 for peripheral 2 and enable its clock: write_register(PMC_PCR,0x10031002) Code Example to read the divider of peripheral 4: write_register(PMC_PCR,0x00000004) When a peripheral clock is disabled, the clock is immediately stopped. The peripheral clocks are automatically disabled after a reset. In order to stop a peripheral, it is recommended that the system software wait until the peripheral has executed its last programmed operation before disabling the clock. This is to avoid data cor- ruption or erroneous behavior of the system. The bit number within the Peripheral Control registers is the Peripheral Identifier defined at the product level. Generally, the bit number corresponds to the interrupt source number assigned to the peripheral.

22.9 Programmable Clock Output Controller

The PMC controls 2 signals to be output on external pins PCKx. Each signal can be indepen- dently programmed via the PMC_PCKx registers. PCKx can be independently selected between the Slow clock, the Master Clock, the PLLACK/PLLADIV2, the UTMI PLL output and the main clock by writing the CSS field in PMC_PCKx. Each output signal can also be divided by a power of 2 between 1 and 64 by writing the PRES (Prescaler) field in PMC_PCKx. Each output signal can be enabled and disabled by writing 1 in the corresponding bit, PCKx of PMC_SCER and PMC_SCDR, respectively. Status of the active programmable output clocks are given in the PCKx bits of PMC_SCSR (System Clock Status Register). Moreover, like the PCK, a status bit in PMC_SR indicates that the Programmable Clock is actu- ally what has been programmed in the Programmable Clock registers. As the Programmable Clock Controller does not manage with glitch prevention when switching clocks, it is strongly recommended to disable the Programmable Clock before any configuration change and to re-enable it after the change is actually performed.

22.10 Programming Sequence

  1. Enabling the 12 MH z Main Oscillator: The main oscillator is enabled by setting the MOSCEN field in the CKGR_MOR register. In some cases it may be advantageous to define a start-up time. This can be achieved by writ- ing a value in the OSCOUNT field in the CKGR_MOR register.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 188 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Once this register has been correctly configured, the user must wait for MOSCS field in the PMC_SR register to be set. This can be done either by polling the status register or by wait- ing the interrupt line to be raised if the associated interrupt to MOSCS has been enabled in the PMC_IER register. 2. Setting PLLA and divider: All parameters needed to configure PLLA and t he divider are located in the CKGR_PLLAR register. The DIVA field is used to control the divider itself. A value between 0 and 255 can be pro- grammed. Divider output is divider input divided by DIVA parameter. By default DIVA parameter is set to 0 which means that divider is turned off. The OUTA field is used to select the PLLA output frequency range. The MULA field is the PLLA multiplier factor. This parameter can be programmed between 0 and 254. If MULA is set to 0, PLLA will be turned off, otherwise the PLLA output frequency is PLLA input frequency multiplied by (MULA + 1). The PLLACOUNT field specifies the number of slow clock cycles before LOCKA bit is set in the PMC_SR register after CKGR_PLLAR register has been written. Once the PMC_PLLAR register has been written, the user must wait for the LOCKA bit to be set in the PMC_SR register. This can be done either by polling the status register or by wait- ing the interrupt line to be raised if the associated interrupt to LOCKA has been enabled in the PMC_IER register. All parameters in CKGR_PLLAR can be programmed in a single write operation. If at some stage one of the following parameters, MULA, DIVA is modified, LOCKA bit will go low to indicate that PLLA is not ready yet. When PLLA is locked, LOCKA will be set again. The user is constrained to wait for LOCKA bit to be set before using the PLLA output clock. Code Example: write_register(CKGR_PLLAR,0x00040805) If PLLA and divider are enabled, the PLLA input clock is the main clock. PLLA output clock is PLLA input clock multiplied by 5. Once CK GR_PLLAR has been written, LOCKA bit will be set after eight slow clock cycles. 3. Setting PLL B and divider B: All parameters needed to configure PLL B and divider B are located in the CKGR_PLLBR register. The DIVB field is used to control divider B itself. A value between 0 and 255 can be pro- grammed. Divider B output is divider B input divided by DIVB parameter. By default DIVB parameter is set to 0 which means that divider B is turned off. The OUTB field is used to select the PLL B output frequency range. The MULB field is the PLL B multiplier factor. This parameter can be programmed between 0 and 2047. If MULB is set to 0, PLL B will be turned off, otherwis e the PLL B output fre- quency is PLL B input frequency multiplied by (MULB + 1).

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 189 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 The PLLBCOUNT field specifies the number of slow clock cycles before LOCKB bit is set in the PMC_SR register after CKGR_PLLBR register has been written. Once the PMC_PLLB register has been written, the user must wait for the LOCKB bit to be set in the PMC_SR register. This can be done either by polling the status register or by wait- ing the interrupt line to be raised if the associated interrupt to LOCKB has been enabled in the PMC_IER register. All parameters in CKGR_PLLBR can be programmed in a single write operation. If at some stage one of the following parameters, MULB, DIVB is modified, LOCKB bit will go low to indicate that PLL B is not ready yet. When PLL B is locked, LOCKB will be set again. The user is constrained to wait for LOCKB bit to be set before using the PLL A output clock. The USBDIV field is used to control the additional divider by 1, 2 or 4, which generates the USB clock(s). Code Example: write_register(CKGR_PLLBR,0x00040805) If PLL B and divider B are enabled, the PLL B in put clock is the main clock. PLL B output clock is PLL B input clock multiplied by 5. Once CKGR_PLLBR has been written, LOCKB bit will be set after eight slow clock cycles. 4. Selection of Master Clock and Processor Clock The Master Clock and the Processor Clock are configurable via the PMC_MCKR register. The CSS field is used to select the clock sour ce of the Master Clock and Processor Clock dividers. By default, the selected clock source is main clock. The PRES field is used to control the Mast er/Processor Clock prescaler. The user can choose between different values (1, 2, 4, 8, 16, 32, 64). Prescaler output is the selected clock source divided by PRES parameter. By default, PRES parameter is set to 1 which means that the input clock of the Master Clock and Processor Clock dividers is equal to slow clock. The MDIV field is used to control the Master Clock divider. It is possible to choose between different values (0, 1, 2, 3). The Master Clock output is Master/Processor Clock Prescaler output divided by 1, 2, 4 or 3, depending on the value programmed in MDIV. The PLLADIV2 field is used to control the PLLA Clock divider. It is possible to choose between different values (0, 1). The PMC PLLA Clock input is divid ed by 1 or 2, depending on the value programmed in PLLADIV2. By default, MDIV and PLLADIV2 are set to 0, which indicates that Processor Clock is equal to the Master Clock. Once the PMC_MCKR register has been written, the user must wait for the MCKRDY bit to be set in the PMC_SR register. This can be done either by polling the status register or by waiting for the interrupt line to be raised if the associated interrupt to MCKRDY has been enabled in the PMC_IER register.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 190 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 The PMC_MCKR register must not be programmed in a single write operation. The pre- ferred programming sequence for the PMC_MCKR register is as follows:

  • If a new value for CSS field corresponds to PLLA Clock, – Program the PRES field in the PMC_MCKR register. – Wait for the MCKRDY bit to be set in the PMC_SR register. – Program the CSS field in the PMC_MCKR register. – Wait for the MCKRDY bit to be set in the PMC_SR register.
  • If a new value for CSS field corresponds to Main Clock or Slow Clock, – Program the CSS field in the PMC_MCKR register. – Wait for the MCKRDY bit to be set in the PMC_SR register. – Program the PRES field in the PMC_MCKR register. – Wait for the MCKRDY bit to be set in the PMC_SR register. If at some stage one of the following parameters, CSS or PRES, is modified, the MCKRDY bit will go low to indicate that the Master Clock and the Processor Clock are not ready yet. The user must wait for MCKRDY bit to be set again before using the Master and Processor Clocks. Note: IF PLLA clock was selected as the Master Clock and the user decides to modify it by writing in CKGR_PLLAR, the MCKRDY flag will go low while PLLA is unlocked. Once PLLA is locked again, LOCK goes high and MCKRDY is set. While PLLA is unlocked, the Master Clock selection is automatically changed to Main Clock. For further information, see Section 22.11.2. “Clock Switching Waveforms” on page 193. Code Example: write_register(PMC_MCKR,0x00000001) wait (MCKRDY=1) write_register(PMC_MCKR,0x00000011) wait (MCKRDY=1) The Master Clock is main clock divided by 16. The Processor Clock is the Master Clock. 5. Selection of Programmable clocks Programmable clocks are controlled via registers; PMC_SCER, PMC_SCDR and PMC_SCSR. Programmable clocks can be enabled and/or disabled via the PMC_SCER and PMC_SCDR registers. Depending on the system used, 2 programmable cl ocks can be enabled or dis- abled. The PMC_SCSR provides a clear indi cation as to which Programmable clock is enabled. By default all Programmable clocks are disabled. PMC_PCKx registers are used to configure programmable clocks. The CSS and CSSMCK fields are used to sele ct the programmable clock divider source. Five clock options are available: main clock, slow clock, master clock, PLLACK, UPLLCK. By default, the clock source selected is slow clock. The PRES field is used to control the programmable clock prescaler. It is possible to choose between different values (1, 2, 4, 8, 16, 32, 64). Programmable clock output is prescaler

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 191 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 input divided by PRES parameter. By default, the PRES parameter is set to 1 which means that master clock is equal to slow clock. Once the PMC_PCKx register has been programmed, The corresponding programmable clock must be enabled and the user is constrai ned to wait for the PCKRDYx bit to be set in the PMC_SR register. This can be done either by polling the status register or by waiting the interrupt line to be raised if the associated interrupt to PCKRDYx has been enabled in the PMC_IER register. All parameters in PMC_ PCKx can be programmed in a single write operation. If the CSS and PRES parameters are to be modified, the corresponding programmable clock must be disabled first. The parameters can then be modified. Once this has been done, the user must re-enable the programmable clock and wait for the PCKRDYx bit to be set. Code Example: write_register(PMC_PCK0,0x00000015) Programmable clock 0 is main clock divided by 32. 6. Enabling Peripheral Clocks Once all of the previous steps have been completed, the peripheral clocks can be enabled and/or disabled via registers PMC_PCER and PMC_PCDR. Depending on the system used, 19 peripheral clocks can be enabled or disabled. The PMC_PCR provides a clear view as to which peripheral clock is enabled. Note: Each enabled peripheral clock corresponds to Master Clock. Code Examples: write_register(PMC_PCER,0x00000110) Peripheral clocks 4 and 8 are enabled. write_register(PMC_PCDR,0x00000010) Peripheral clock 4 is disabled.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 192 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

22.11 Clock Switching Details

22.11.1 Master Clock Switching Timings

Table 22-1 and Table 22-2 give the worst case ti mings required for the Master Clock to switch from one selected clock to another one. This is in the event that the prescaler is de-activated. When the prescaler is activated, an additional time of 64 clock cycles of the new selected clock has to be added. Notes: 1. PLL designates either the PLLA or the UPLL Clock. 2. PLLCOUNT designates either PLLACOUNT or UPLLCOUNT. Table 22-1. Clock Switching Timings (Worst Case) From Main Clock SLCK PLL Clock To Main Clock – 4 x SLCK + 2.5 x Main Clock 3 x PLL Clock + 4 x SLCK + 1 x Main Clock SLCK 0.5 x Main Clock + 4.5 x SLCK – 3 x PLL Clock + 5 x SLCK PLL Clock 0.5 x Main Clock + 4 x SLCK + PLLCOUNT x SLCK + 2.5 x PLLx Clock 2.5 x PLL Clock + 5 x SLCK + PLLCOUNT x SLCK 2.5 x PLL Clock + 4 x SLCK + PLLCOUNT x SLCK Table 22-2. Clock Switching Timings between Two PLLs (Worst Case) From PLLA Clock PLLB Clock To PLLA Clock 2.5 x PLLA Clock + 4 x SLCK + PLLACOUNT x SLCK 3 x PLLA Clock + 4 x SLCK + 1.5 x PLLA Clock PLLB Clock 3 x PLLB Clock + 4 x SLCK + 1.5 x PLLB Clock 2.5 x PLLB Clock + 4 x SLCK + PLLBCOUNT x SLCK

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 193 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

22.11.2 Clock Switching Waveforms

Figure 22-2. Switch Master Clock from Slow Clock to PLL Clock Figure 22-3. Switch Master Clock from Main Clock to Slow Clock Slow Clock LOCK MCKRDY Master Clock Write PMC_MCKR PLL Clock Slow Clock Main Clock MCKRDY Master Clock Write PMC_MCKR

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 195 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

22.12 Power Management Contro ller (PMC) User Interface

Table 22-3. Register Mapping Offset Register Name Access Reset 0x0000 System Clock Enable Register PMC_SCER Write-only N.A. 0x0004 System Clock Disable Register PMC_SCDR Write-only N.A. 0x0008 System Clock Status Register PMC_SCSR Read-only 0x0000_0005 0x0010 Peripheral Clock Enable Register PMC _PCER Write-only N.A. 0x0014 Peripheral Clock Disable Register PMC_PCDR Write-only – 0x0018 Peripheral Clock Status Register PMC_PCSR Read-only 0x0000_0000 0x000C - 0x0018 Reserved – – – 0x001C Reserved – – – 0x0020 Main Oscillator Register CKGR_MOR Read-write 0x0100_0001 0x0024 Main Clock Frequency Register CKGR_MCFR Read-write 0x0000_0000 0x0028 PLLA Register CKGR_PLLAR Read-write 0x0000_3F00 0x002C PLLB Register CKGR_PLLBR Read-write 0x0000_3F00 0x0030 Master Clock Register PMC_MCKR Read-write 0x0000_0001 0x0034 Reserved – – – 0x0038 USB Clock Register PMC_USB Read-write 0x0000_0000 0x003C Reserved – – – 0x0040 Programmable Clock 0 Register PMC_PCK0 Read-write 0x0000_0000 0x0044 Programmable Clock 1 Register PMC_PCK1 Read-write 0x0000_0000 0x0048 - 0x005C Reserved – – – 0x0060 Interrupt Enable Register PMC_IER Write-only N.A. 0x0064 Interrupt Disable Register PMC_IDR Write-only N.A. 0x0068 Status Register PMC_SR Read-only 0x0001_0008 0x006C Interrupt Mask Register PMC_IMR Read-only 0x0000_0000 0x0070 - 0x0078 Reserved – – – 0x0080 PLL Charge Pump Current Register PMC_PLLICPR Write-only 0x0100_0100 0x0084-0x00E0 Reserved – – – 0x00E4 Write Protect Mode Register PMC_WPMR Read-write 0x0000_0000 0x00E8 Write Protect Status Register PMC_WPSR Read-only 0x0000_0000 0x00EC-0x0108 Reserved – – – 0x010C Peripheral Control Register PMC_PCR Read-write 0x0000_0000

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 196 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

22.12.1 PMC System Clock Enable Register

Name: PMC_SCER Address: 0xFFFFFC00 Access: Write-only  DDRCK: DDR Clock Enable 0 = No effect. 1 = Enables the DDR clock.  LCDCK: LCD Clock Enable 0 = No effect. 1 = Enables the LCD clock.  UHP: USB Host OHCI Clocks Enable 0 = No effect. 1 = Enables the UHP48M and UHP12M OHCI clocks.  UDP: USB Device Clock Enable 0 = No effect. 1 = Enables the USB Device clock.  PCKx: Programmable Clock x Output Enable 0 = No effect. 1 = Enables the corresponding Programmable Clock output. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 UDP UHP – – LCDCK DDRCK – –

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 197 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

22.12.2 PMC System Clock Disable Register

Name: PMC_SCDR Address: 0xFFFFFC04 Access: Write-only  PCK: Processor Clock Disable 0 = No effect. 1 = Disables the Processor clock. This is used to enter the processor in Idle Mode.  DDRCK: DDR Clock Disable 0 = No effect. 1 = Disables the DDR clock.  LCDCK: LCD Clock Disable 0 = No effect. 1 = Disables the LCD clock.  UHP: USB Host OHCI Clock Disable 0 = No effect. 1 = Disables the UHP48M and UHP12M OHCI clocks.  UDP: USB Device Clock Enable 0 = No effect. 1 = Disables the USB Device clock.  PCKx: Programmable Clock x Output Disable 0 = No effect. 1 = Disables the corresponding Programmable Clock output. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 UDP UHP – – LCDCK DDRCK – PCK

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 198 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

22.12.3 PMC System Clock Status Register

Name: PMC_SCSR Address: 0xFFFFFC08 Access: Read-only  PCK: Processor Clock Status 0 = The Processor clock is disabled. 1 = The Processor clock is enabled.  DDRCK: DDR Clock Status 0 = The DDR clock is disabled. 1 = The DDR clock is enabled.  LCDCK: LCD Clock Status 0 = The LCD clock is disabled. 1 = The LCD clock is enabled.  UHP: USB Host Port Clock Status 0 = The UHP48M and UHP12M OHCI clocks are disabled. 1 = The UHP48M and UHP12M OHCI clocks are enabled.  UDP: USB Device Port Clock Status 0 = The USB Device clock is disabled. 1 = The USB Device clock is enabled.  PCKx: Programmable Clock x Output Status 0 = The corresponding Programmable Clock output is disabled. 1 = The corresponding Programmable Clock output is enabled. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 UDP UHP – – LCDCK DDRCK – PCK

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 199 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

22.12.4 PMC Peripheral Clock Enable Register

Name: PMC_PCER Address: 0xFFFFFC10 Access: Write-only  PIDx: Peripheral Clock x Enable 0 = No effect. 1 = Enables the corresponding peripheral clock. Note: PID2 to PID31 refer to identifiers as defined in the section “Peripheral Identifiers” in the product datasheet. Note: Programming the control bits of the Peripheral ID that ar e not implemented has no effect on the behavior of the PMC. 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 76543210 PID7 PID6 PID5 PID4 PID3 PID2 - -

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 200 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

22.12.5 PMC Peripheral Clock Disable Register

Name: PMC_PCDR Address: 0xFFFFFC14 Access: Write-only  PIDx: Peripheral Clock x Disable 0 = No effect. 1 = Disables the corresponding peripheral clock. Note: PID2 to PID31 refer to identifiers as defined in the section “Peripheral Identifiers” in the product datasheet. 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 76543210 PID7 PID6 PID5 PID4 PID3 PID2 - -

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 201 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

22.12.6 PMC Peripheral Clock Status Register

Name: PMC_PCSR Address: 0xFFFFFC18 Access: Read-only  PIDx: Peripheral Clock x Status 0 = The corresponding peripheral clock is disabled. 1 = The corresponding peripheral clock is enabled. Note: PID2 to PID31 refer to identifiers as defined in the section “Peripheral Identifiers” in the product datasheet. 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 76543210 PID7 PID6 PID5 PID4 PID3 PID2 – –

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 202 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

22.12.7 PMC Clock Generator Main Oscillator Register

Name: CKGR_MOR Address: 0xFFFFFC20 Access: Read-write K E Y : P a s s w o r d Should be written at value 0x37. Writing any other value in this field aborts the write operation.  MOSCXTEN: Main Crystal Oscillator Enable A crystal must be connected between XIN and XOUT. 0 = The Main Crystal Oscillator is disabled. 1 = The Main Crystal Oscillator is enabled. MOSCXTBY must be set to 0. When MOSCXTEN is set, the MOSCXTS flag is set once the Main Crystal Oscillator startup time is achieved.  MOSCXTBY: Main Crystal Oscillator Bypass 0 = No effect. 1 = The Main Crystal Oscillator is bypassed. MOSCXTEN must be set to 0. An external clock must be connected on XIN. When MOSCXTBY is set, the MOSCXTS flag in PMC_SR is automatically set. Clearing MOSCXTEN and MOSCXTBY bits allows resetting the MOSCXTS flag.  MOSCRCEN: Main On-Chip RC Oscillator Enable 0 = The Main On-Chip RC Oscillator is disabled. 1 = The Main On-Chip RC Oscillator is enabled. When MOSCRCEN is set, the MOSCRCS flag is set once the Main On-Chip RC Oscillator startup time is achieved.  MOSCXTST: Main Crystal Oscillator Start-up Time Specifies the number of Slow Clock cycles multiplied by 8 for the Main Crystal Oscillator start-up time.  MOSCSEL: Main Oscillator Selection 0 = The Main On-Chip RC Oscillator is selected. 1 = The Main Crystal Oscillator is selected.  CFDEN: Clock Failure Detector Enable 0 = The Clock Failure Detector is disabled. 1 = The Clock Failure Detector is enabled. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 KEY 15 14 13 12 11 10 9 8 MOSCXTST 76543210 –––– M OSCRCEN – MOSCXTBY MOSCXTEN

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 203 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

22.12.8 PMC Clock Generator Main Clock Frequency Register

Name: CKGR_MCFR Address: 0xFFFFFC24 Access: Read-write  MAINF: Main Clock Frequency Gives the number of Main Clock cycles within 16 Slow Clock periods.  MAINFRDY: Main Clock Ready 0 = MAINF value is not valid or the Main Oscillator is disabled. 1 = The Main Oscillator has been enabled previously and MAINF value is available.  RCMEAS: RC Measure This bit is write-only. 0 = No effect. 1 = Restart a measure of the main RC frequency. MAINF will carry the new frequency as soon as a low to high transition occurs on MAINFRDY flag. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 MAINF 76543210 MAINF

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 204 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

22.12.9 PMC Clock Generator PLLA Register

Name: CKGR_PLLAR Address: 0xFFFFFC28 Access: Read-write Possible limitations on PLLA input frequencies and multiplier factors should be checked before using the PMC. Warning: Bit 29 must always be set to 1 when programming the CKGR_PLLAR register.  DIVA: Divider A 0 = divider output is 0 1 = divider is bypassed 2 up to 255 = Divider output is the selected clock divided by DIVA  PLLACOUNT: PLLA Counter Specifies the number of slow clock cycles before the LOCKA bit is set in PMC_SR after CKGR_PLLAR is written.  OUTA: PLLA Clock Frequency Range To optimize clock performance, this field must be programmed as specified in “PLL Characteristics” in the Electrical Char- acteristics section of the product datasheet.  MULA: PLLA Multiplier 0 = The PLLA is deactivated. 1 up to 254 = The PLLA Clock frequency is the PLLA input frequency multiplied by MULA+ 1. 31 30 29 28 27 26 25 24 ––1–– MULA 23 22 21 20 19 18 17 16 MULA 15 14 13 12 11 10 9 8 OUTA PLLACOUNT 76543210 DIVA

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 205 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

22.12.10 PMC Clock Generator PLLB Register

Name: CKGR_PLLBR Address: 0xFFFFFC2C Access: Read-write Possible limitations on PLLB input frequencies and multiplier factors should be checked before using the PMC.  DIVB: Divider B 0 = divider output is 0 1 = divider is bypassed 2 up to 255 = Divider output is the selected clock divided by DIVB  PLLBCOUNT: PLLB Counter Specifies the number of slow clock cycles before the LOCKB bit is set in PMC_SR after CKGR_PLLBR is written.  OUTB: PLLB Clock Frequency Range To optimize clock performance, this field must be programmed as specified in “PLL Characteristics” in the Electrical Char- acteristics section of the product datasheet.  MULB: PLLB Multiplier 0 = The PLLB is deactivated. 1 up to 254 = The PLLB Clock frequency is the PLLB input frequency multiplied by MULB+1. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 MULB 15 14 13 12 11 10 9 8 OUTB PLLBCOUNT 76543210 DIVB

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 206 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

22.12.11 PMC Master Clock Register

Name: PMC_MCKR Address: 0xFFFFFC30 Access: Read-write  CSS: Master/Processor Clock Source Selection  PRES: Master/Processor Clock Prescaler 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 –P RES– – C SS Value Name Description

0 SLOW_CLK Slow Clock is selected

1 MAIN_CLK Main Clock is selected

2 PLLA_CLK PLLACK/PLLADIV2 is selected

3 PLLB_CLK PLLBCK is selected

0 CLOCK_DIV1 Selected clock

1 CLOCK_DIV2 Selected clock divided by 2

2 CLOCK_DIV4 Selected clock divided by 4

3 CLOCK_DIV8 Selected clock divided by 8

4 CLOCK_DIV16 Selected clock divided by 16

5 CLOCK_DIV32 Selected clock divided by 32

6 CLOCK_DIV64 Selected clock divided by 64

7 Reserved Reserved

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 207 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12  MDIV: Master Clock Division  PLLADIV2: PLLA divisor by 2 Value Name Description 0E Q_PCK Master Clock is Prescaler Output Clock divided by 1. Warning: DDRCK is not available. 1P CK_DIV2 Master Clock is Prescaler Output Clock divided by 2. DDRCK is equal to MCK. 2P CK_DIV4 Master Clock is Prescaler Output Clock divided by 4. DDRCK is equal to MCK. 3P CK_DIV3 Master Clock is Prescaler Output Clock divided by 3. DDRCK is equal to MCK. Value Name Description 0 NOT_DIV2 PLLA clock frequency is divided by 1. 1 DIV2 PLLA clock frequency is divided by 2.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 208 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

22.12.12 USB Clock Register

Name: PMC_USB Address: 0xFFFFFC38 Access: Read-write  USBS: USB OHCI Input Clock Selection 0 = USB Clock disabled. 1 = USB Clock Input is PLLB.  USBDIV: Divider for USB Clock USB Clock is Input Clock divided by USBDIV+1. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 –––– USBDIV 76543210

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 209 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

22.12.13 PMC Programmable Clock Register

Name: PMC_PCKx Address: 0xFFFFFC40 Access: Read-write  CSS: Master Clock Source Selection  PRES: Programmable Clock Prescaler 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 –P RES– C SS Value name Description

4 MCK_CLK Master Clock is selected

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 210 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

22.12.14 PMC Interrupt Enable Register

Name: PMC_IER Address: 0xFFFFFC60 Access: Write-only  MOSCXTS: Main Crystal Oscillator Status Interrupt Enable  LOCKA: PLLA Lock Interrupt Enable  LOCKB: PLLB Lock Interrupt Enable  MCKRDY: Master Clock Ready Interrupt Enable  PCKRDYx: Programmable Clock Ready x Interrupt Enable  MOSCSELS: Main Oscillator Selection Status Interrupt Enable  MOSCRCS: Main On-Chip RC Status Interrupt Enable  CFDEV: Clock Failure Detector Event Interrupt Enable 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ––––– C FDEV M OSCRCS M OSCSELS 15 14 13 12 11 10 9 8 76543210 –––– M CKRDY L OCKB L OCKA M OSCXTS

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 211 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

22.12.15 PMC Interrupt Disable Register

Name: PMC_IDR Address: 0xFFFFFC64 Access: Write-only  MOSCXTS: Main Crystal Oscillator Status Interrupt Disable  LOCKA: PLLA Lock Interrupt Disable  LOCKB: PLLB Lock Interrupt Disable  MCKRDY: Master Clock Ready Interrupt Disable  PCKRDYx: Programmable Clock Ready x Interrupt Disable  MOSCSELS: Main Oscillator Selection Status Interrupt Disable  MOSCRCS: Main On-Chip RC Status Interrupt Disable  CFDEV: Clock Failure Detector Event Interrupt Disable 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ––––– C FDEV M OSCRCS M OSCSELS 15 14 13 12 11 10 9 8 76543210 –––– M CKRDY L OCKB L OCKA M OSCXTS

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 212 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

22.12.16 PMC Status Register

Name: PMC_SR Address: 0xFFFFFC68 Access: Read-only  MOSCXTS: Main XTAL Oscillator Status 0 = Main XTAL oscillator is not stabilized. 1 = Main XTAL oscillator is stabilized.  LOCKA: PLLA Lock Status 0 = PLLA is not locked 1 = PLLA is locked.  LOCKB: PLLB Lock Status 0 = PLLB is not locked 1 = PLLB is locked.  MCKRDY: Master Clock Status 0 = Master Clock is not ready. 1 = Master Clock is ready.  OSCSELS: Slow Clock Oscillator Selection 0 = Internal slow clock RC oscillator is selected. 1 = External slow clock 32 kHz oscillator is selected.  PCKRDYx: Programmable Clock Ready Status 0 = Programmable Clock x is not ready. 1 = Programmable Clock x is ready.  MOSCSELS: Main Oscillator Selection Status 0 = Selection is in progress. 1 = Selection is done.  MOSCRCS: Main On-Chip RC Oscillator Status 0 = Main on-chip RC oscillator is not stabilized. 1 = Main on-chip RC oscillator is stabilized. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 – – – FOS CFDS CFDEV MOSCRCS MOSCSELS 15 14 13 12 11 10 9 8 76543210 OSCSELS – – – MCKRDY LOCKB LOCKA MOSCXTS

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 213 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12  CFDEV: Clock Failure Detector Event 0 = No clock failure detection of the main on-chip RC oscillator clock has occurred since the last read of PMC_SR. 1 = At least one clock failure detection of the main on-chip RC oscillator clock has occurred since the last read of PMC_SR.  CFDS: Clock Failure Detector Status 0 = A clock failure of the main on-chip RC oscillator clock is not detected. 1 = A clock failure of the main on-chip RC oscillator clock is detected.  FOS: Clock Failure Detector Fault Output Status 0 = The fault output of the clock failure detector is inactive. 1 = The fault output of the clock failure detector is active.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 214 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

22.12.17 PMC Interrupt Mask Register

Name: PMC_IMR Address: 0xFFFFFC6C Access: Read-only  MOSCXTS: Main Crystal Oscillator Status Interrupt Mask  LOCKA: PLLA Lock Interrupt Mask  LOCKB: PLLB Lock Interrupt Mask  MCKRDY: Master Clock Ready Interrupt Mask  PCKRDYx: Programmable Clock Ready x Interrupt Mask  MOSCSELS: Main Oscillator Selection Status Interrupt Mask  MOSCRCS: Main On-Chip RC Status Interrupt Mask  CFDEV: Clock Failure Detector Event Interrupt Mask 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ––––– C FDEV M OSCRCS M OSCSELS 15 14 13 12 11 10 9 8 76543210 –––– M CKRDY L OCKB L OCKA M OSCXTS

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 215 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

22.12.18 PLL Charge Pump Current Register

Name: PMC_PLLICPR Address: 0xFFFFFC80 Access: Write-only  ICPLLA: Charge Pump Current To optimize clock performance, this field must be programmed as specified in “PLL A Characteristics” in the Electrical Char- acteristics section of the product datasheet. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 216 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

22.12.19 PMC Write Protect Mode Register

Name: PMC_WPMR Address: 0xFFFFFCE4 Access: Read-write Reset: See Table 22-3  WPEN: Write Protect Enable 0 = Disables the Write Protect if WPKEY corresponds to 0x504D43 (“PMC” in ASCII). 1 = Enables the Write Protect if WPKEY corresponds to 0x504D43 (“PMC” in ASCII). Protects the registers:

  • “PMC System Clock Enable Register” on page 196
  • “PMC System Clock Disable Register” on page 197
  • “PMC Clock Generator Main Clock Frequency Register” on page 203
  • “PMC Clock Generator PLLA Register” on page 204
  • “PMC Master Clock Register” on page 206
  • “PMC Programmable Clock Register” on page 209
  • “PMC Programmable Clock Register” on page 209
  • “PLL Charge Pump Current Register” on page 215  WPKEY: Write Protect KEY Should be written at value 0x504D43 (“PMC” in ASCII). Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. 31 30 29 28 27 26 25 24 WPKEY 23 22 21 20 19 18 17 16 WPKEY 15 14 13 12 11 10 9 8 WPKEY 76543210

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 217 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

22.12.20 PMC Write Protect Status Register

Name: PMC_WPSR Address: 0xFFFFFCE8 Access: Read-only Reset: See Table 22-3  WPVS: Write Protect Violation Status 0 = No Write Protect Violation has occurred since the last read of the PMC_WPSR register. 1 = A Write Protect Violation has occurred since the last read of the PMC_WPSR register. If this violation is an unauthor- ized attempt to write a protected register, the associated violation is reported into field WPVSRC.  WPVSRC: Write Protect Violation Source When WPVS is active, this field indicates the write-protected register (t hrough address offset or code) in which a write access has been attempted. Reading PMC_WPSR automatically clears all fields. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WPVSRC 15 14 13 12 11 10 9 8 WPVSRC 76543210

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 218 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

22.12.21 PMC Peripheral Control Register

Name: PMC_PCR Address: 0xFFFFFD0C Access: Write-only  PID: Peripheral ID Peripheral ID selection from PID2 to PID31 PID2 to PID31 refer to identifiers as defined in the section “Peripheral Identifiers” in the product datasheet.  CMD: Command 0: Read mode 1: Write mode  DIV: Divisor value  EN: Enable 0: Selected Peripheral clock is disabled 1: Selected Peripheral clock is enabled 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 –– PID Value name Description

0 PERIPH_DIV_MCK Peripheral clock is MCK

1 PERIPH_DIV2_MCK Peripheral clock is MCK/2

2 PERIPH_DIV4_MCK Peripheral clock is MCK/4

3 PERIPH_DIV8_MCK Peripheral clock is MCK/8

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 219 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 23. Parallel Input/Output Controller (PIO)

23.1 Description

The Parallel Input/Output Controller (PIO) manages up to 32 fully programmable input/output lines. Each I/O line may be dedicated as a general-purpose I/O or be assigned to a function of an embedded peripheral. This assures effective optimization of the pins of a product. Each I/O line is associated with a bit number in all of the 32-bit registers of the 32-bit wide User Interface. Each I/O line of the PIO Controller features:

  • An input change interrupt enabling level change detection on any I/O line.
  • Additional Interrupt modes enabling rising edge, falling edge, low level or high level detection on any I/O line.
  • A glitch filter providing rejection of glitches lower than one-half of PIO clock cycle.
  • A debouncing filter providing rejection of unwanted pulses from key or push button operations.
  • Multi-drive capability similar to an open drain I/O line.
  • Control of the pull-up and pull-down of the I/O line.
  • Input visibility and output control. The PIO Controller also features a synchronous output providing up to 32 bits of data output in a single write operation.

23.2 Embedded Characteristics

  • Up to 32 Programmable I/O Lines
  • Fully Programmable through Set/Clear Registers
  • Multiplexing of Four Peripheral Functions per I/O Line
  • For each I/O Line (Whether Assigned to a Peripheral or Used as General Purpose I/O) – Input Change Interrupt – Programmable Glitch Filter – Programmable Debouncing Filter – Multi-drive Option Enables Driving in Open Drain – Programmable Pull Up on Each I/O Line – Pin Data Status Register, Supplies Visibility of the Level on the Pin at Any Time – Additional Interrupt Modes on a Programmable Event: Rising Edge, Falling Edge, Low Level or High Level – Lock of the Configuration by the Connected Peripheral
  • Synchronous Output, Provides Set and Clear of Several I/O lines in a Single Write
  • Write Protect Registers
  • Programmable Schmitt Trigger Inputs
  • Programmable I/O Delay
  • Programmable I/O Drive

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 220 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

23.3 Block Diagram

Figure 23-1. Block Diagram Figure 23-2. Application Block Diagram Embedded Peripheral Embedded Peripheral PIO Interrupt PIO Controller Up to 32 pins PMC Up to 32 peripheral IOs Up to 32 peripheral IOs PIO Clock APB Interrupt Controller Data, Enable PIN 31 PIN 1 PIN 0 Data, Enable On-Chip Peripherals PIO Controller On-Chip Peripheral Drivers Control & Command Driver Keyboard Driver Keyboard Driver General Purpose I/Os External Devices

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 221 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

23.4 Product Dependencies

23.4.1 Pin Multiplexing

Each pin is configurable, according to product definition as either a general-purpose I/O line only, or as an I/O line multiplexed with one or two peripheral I/Os. As the multiplexing is hard- ware defined and thus product-dependent, the hardware designer and programmer must carefully determine the configuration of the PIO controllers required by their application. When an I/O line is general-purpose only, i.e. not multiplexed with any peripheral I/O, programming of the PIO Controller regarding the assignment to a peripheral has no effect and only the PIO Con- troller can control how the pin is driven by the product.

23.4.2 External Interrupt Lines

The interrupt signals FIQ and IRQ0 to IRQn are most generally multiplexed through the PIO Controllers. However, it is not necessary to assign the I/O line to the interrupt function as the PIO Controller has no effect on inputs and the interrupt lines (FIQ or IRQs) are used only as inputs.

23.4.3 Power Management

The Power Management Controller controls the PIO Controller clock in order to save power. Writing any of the registers of the user interface does not require the PIO Controller clock to be enabled. This means that the configuration of the I/O lines does not require the PIO Controller clock to be enabled. However, when the clock is disabled, not all of t he features of the PIO Controller are available, including glitch filtering. Note that the Input Change Interrupt, Interrupt Modes on a programma- ble event and the read of the pin level require the clock to be validated. After a hardware reset, the PIO clock is disabled by default. The user must configure the Power Management Controller before any access to the input line information.

23.4.4 Interrupt Generation

For interrupt handling, the PIO Controllers are considered as user peripherals. This means that the PIO Controller interrupt lines are connected among the interrupt sources 2 to 31. Refer to the PIO Controller peripheral identifier in the produc t description to identify the interrupt sources dedicated to the PIO Controllers. The PIO Controller interrupt can be generated only if the PIO Controller clock is enabled.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 222 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

23.5 Functional Description

The PIO Controller features up to 32 fully-programmable I/O lines. Most of the control logic asso- ciated to each I/O is represented in Figure 23-3 . In this description each signal shown represents but one of up to 32 possible indexes. Figure 23-3. I/O Line Control Logic DQ DQ DFF Programmable Glitch or Debouncing Filter PIO_PDSR[0] PIO_ISR[0] PIO_IDR[0] PIO_IMR[0] PIO_IER[0] PIO Interrupt (Up to 32 possible inputs) PIO_ISR[31] PIO_IDR[31] PIO_IMR[31] PIO_IER[31] Pad PIO_PUDR[0] PIO_PUSR[0] PIO_PUER[0] PIO_MDDR[0] PIO_MDSR[0] PIO_MDER[0] PIO_CODR[0] PIO_ODSR[0] PIO_SODR[0] PIO_PDR[0] PIO_PSR[0] PIO_PER[0]PIO_ABCDSR1[0] PIO_ODR[0] PIO_OSR[0] PIO_OER[0] Resynchronization Stage Peripheral A Input Peripheral D Output Enable Peripheral A Output Enable EVENT DETECTORDFF PIO_IFDR[0] PIO_IFSR[0] PIO_IFER[0] PIO Clock Clock Divider PIO_IFSCSR[0] PIO_IFSCER[0] PIO_IFSCDR[0] PIO_SCDR Slow Clock Peripheral B Output Enable Peripheral C Output Enable Peripheral D Output Peripheral A Output Peripheral B Output Peripheral C Output PIO_ABCDSR2[0] Peripheral B Input Peripheral C Input Peripheral D Input

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 223 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

23.5.1 Pull-up and Pull-down Resistor Control

Each I/O line is designed with an embedded pull-up resistor and an embedded pull-down resis- tor. The pull-up resistor can be enabled or disabl ed by writing respectively PIO_PUER (Pull-up Enable Register) and PIO_PUDR (Pull-up Disable Resistor). Writing in these registers results in setting or clearing the corresponding bit in PIO_PUSR (Pull-up Status Register). Reading a 1 in PIO_PUSR means the pull-up is disabled and reading a 0 means the pull-up is enabled. The pull-down resistor can be enabled or disabled by writing respectively PIO_PPDER (Pull-down Enable Register) and PIO_PPDDR (Pull-down Disable Resistor). Writing in these registers results in setting or clearing the corresponding bit in PIO_PPDSR (Pull-down Status Register). Reading a 1 in PIO_PPDSR means the pull-up is disabled and reading a 0 means the pull-down is enabled. Enabling the pull-down resistor while the pull-up resistor is still enabled is not possible. In this case, the write of PIO_PPDER for the concerned I/O line is discarded. Likewise, enabling the pull-up resistor while the pull-down resistor is still enabled is not possible. In this case, the write of PIO_PUER for the concerned I/O line is discarded. Control of the pull-up resistor is possible regardless of the configuration of the I/O line. After reset, all of the pull-ups are enabled, i.e. PIO_PUSR resets at the value 0x0, and all the pull-downs are disabled, i.e. PIO_PPDSR resets at the value 0xFFFFFFFF.

23.5.2 I/O Line or Peripheral Function Selection

When a pin is multiplexed with one or two peripheral functions, the selection is controlled with the registers PIO_PER (PIO Enable Register) and PIO_PDR (PIO Disable Register). The regis- ter PIO_PSR (PIO Status Register) is the resu lt of the set and clear registers and indicates whether the pin is controlled by the corresponding peripheral or by the PIO Controller. A value of 0 indicates that the pin is controlled by the corresponding on-chip peripheral selected in the PIO_ABCDSR1 and PIO_ABCDSR2 (ABCD Select Regi sters). A value of 1 indicates the pin is controlled by the PIO controller. If a pin is used as a general purpose I/O line (not multiplexed with an on-chip peripheral), PIO_PER and PIO_PDR have no effect and PIO_PSR returns 1 for the corresponding bit. After reset, most generally, the I/O lines are controlled by the PIO controller, i.e. PIO_PSR resets at 1. However, in some events, it is important that PIO lines are controlled by the periph- eral (as in the case of memory chip select lines that must be driven inactive after reset or for address lines that must be driven low for booting out of an external memory). Thus, the reset value of PIO_PSR is defined at the product level, depending on the multiplexing of the device.

23.5.3 Peripheral A or B or C or D Selection

The PIO Controller provides multiplexing of up to four peripheral functions on a single pin. The selection is performed by writing PIO_ABCDSR1 and PIO_ABCDSR2 (ABCD Select Registers). For each pin:

  • the corresponding bit at level 0 in PIO_ABCDSR1 and the corresponding bit at level 0 in PIO_ABCDSR2 means peripheral A is selected.
  • the corresponding bit at level 1 in PIO_ABCDSR1 and the corresponding bit at level 0 in PIO_ABCDSR2 means peripheral B is selected.
  • the corresponding bit at level 0 in PIO_ABCDSR1 and the corresponding bit at level 1 in PIO_ABCDSR2 means peripheral C is selected.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 224 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

  • the corresponding bit at level 1 in PIO_ABCDSR1 and the corresponding bit at level 1 in PIO_ABCDSR2 means peripheral D is selected. Note that multiplexing of peripheral lines A, B, C and D only affects the output line. The periph- eral input lines are always connected to the pin input. After reset, PIO_ABCDSR1 and PIO_ABCDSR2 are 0, thus indicating that all the PIO lines are configured on peripheral A. However, peripheral A generally does not drive the pin as the PIO Controller resets in I/O line mode. Writing in PIO_ABCDSR1 and PIO_ABCDSR2 manages the multiplexing regardless of the con- figuration of the pin. However, assignment of a pin to a peripheral function requires a write in the peripheral selection registers (PIO_ABCDSR1 and PIO_ABCDSR2) in addition to a write in PIO_PDR.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 225 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

23.5.4 Output Control

When the I/0 line is assigned to a peripheral function, i.e. the corresponding bit in PIO_PSR is at 0, the drive of the I/O line is controlled by the peripheral. Peripheral A or B or C or D depending on the value in PIO_ABCDSR1 and PIO_ABCDS R2 (ABCD Select Registers) determines whether the pin is driven or not. When the I/O line is controlled by the PIO controller, the pin can be configured to be driven. This is done by writing PIO_OER (Output Enable Register) and PIO_ODR (Output Disable Register). The results of these write operations are detected in PIO_OSR (Output Status Register). When a bit in this register is at 0, the corresponding I/O line is used as an input only. When the bit is at 1, the corresponding I/O line is driven by the PIO controller. The level driven on an I/O line can be determined by writing in PIO_SODR (Set Output Data Register) and PIO_CODR (Clear Output Data Register). These write operations respectively set and clear PIO_ODSR (Output Data Status Register), which represents the data driven on the I/O lines. Writing in PIO_OER and PIO_ODR manage s PIO_OSR whether the pin is configured to be controlled by the PIO controller or assigned to a peripheral function. This enables configura- tion of the I/O line prior to setting it to be managed by the PIO Controller. Similarly, writing in PIO_SODR and PIO_CODR effects PIO_ODSR. This is important as it defines the first level driven on the I/O line.

23.5.5 Synchronous Data Output

Clearing one (or more) PIO line(s) and setting another one (or more) PIO line(s) synchronously cannot be done by using PIO_SODR and PIO_CODR registers. It requires two successive write operations into two different registers. To overcome this, the PIO Controller offers a direct con- trol of PIO outputs by single write access to PIO_ODSR (Output Data Status Register).Only bits unmasked by PIO_OWSR (Output Write Status Register) are written. The mask bits in PIO_OWSR are set by writing to PIO_OWER (Output Write Enable Register) and cleared by writing to PIO_OWDR (Output Write Disable Register). After reset, the synchronous data output is disabled on all the I/O lines as PIO_OWSR resets at 0x0.

23.5.6 Multi Drive Control (Open Drain)

Each I/O can be independently programmed in Open Drain by using the Multi Drive feature. This feature permits several drivers to be connected on the I/O line which is driven low only by each device. An external pull-up resistor (or enabling of the internal one) is generally required to guar- antee a high level on the line. The Multi Drive feature is controlled by PIO_MDER (Multi-driver Enable Register) and PIO_MDDR (Multi-driver Disable Register). The Multi Drive can be selected whether the I/O line is controlled by the PIO controller or assigned to a peripheral function. PIO_MDSR (Multi-driver Status Register) indicates the pins that are configured to support external drivers. After reset, the Multi Drive feature is disabled on all pins, i.e. PIO_MDSR resets at value 0x0.

23.5.7 Output Line Timings

Figure 23-4 shows how the outputs are driven either by writing PIO_SODR or PIO_CODR, or by directly writing PIO_ODSR. This last case is va lid only if the corresponding bit in PIO_OWSR is set. Figure 23-4 also shows when the feedback in PIO_PDSR is available.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 226 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Figure 23-4. Output Line Timings

23.5.8 Inputs

The level on each I/O line can be read through PIO_PDSR (Pin Data Status Register). This reg- ister indicates the level of the I/O lines regardless of their configuration, whether uniquely as an input or driven by the PIO controller or driven by a peripheral. Reading the I/O line levels requires the clock of the PIO controller to be enabled, otherwise PIO_PDSR reads the levels present on the I/O line at the time the clock was disabled.

23.5.9 Input Glitch and Debouncing Filters

Optional input glitch and debouncing filters are independently programmable on each I/O line. The glitch filter can filter a g litch with a duration of less than 1/2 Master Clock (MCK) and the debouncing filter can filter a pulse of less than 1/2 Period of a Programmable Divided Slow Clock. The selection between glitch filtering or debounce filtering is done by writing in the registers PIO_IFSCDR (PIO Input Filter Slow Clock Disable Register) and PIO_IFSCER (PIO Input Filter Slow Clock Enable Register). Writing PIO_IF SCDR and PIO_IFSCER respectively, sets and clears bits in PIO_IFSCSR. The current selection status can be checked by reading the register PIO_IFSCSR (Input Filter Slow Clock Status Register).

  • If PIO_IFSCSR[i] = 0: The glitch filter can filter a glitch with a duration of less than 1/2 Period of Master Clock.
  • If PIO_IFSCSR[i] = 1: The debouncing filter can filter a pulse with a duration of less than 1/2 Period of the Programmable Divided Slow Clock. For the debouncing filter, the Period of the Divided Slow Clock is performed by writing in the DIV field of the PIO_SCDR (Slow Clock Divider Register) Tdiv_slclk = ((DIV+1)*2).Tslow_clock When the glitch or debouncing filter is enabled, a glitch or pulse with a duration of less than 1/2 Selected Clock Cycle (Selected Clock represents MCK or Divided Slow Clock depending on PIO_IFSCDR and PIO_IFSCER programming) is autom atically rejected, while a pulse with a duration of 1 Selected Clock (MCK or Divided Slow Clock) cycle or more is accepted. For pulse durations between 1/2 Selected Clock cycle and 1 Selected Clock cycle the pulse may or may 2 cycles APB Access 2 cycles APB Access MCK Write PIO_SODR Write PIO_ODSR at 1 PIO_ODSR PIO_PDSR Write PIO_CODR Write PIO_ODSR at 0

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 228 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

23.5.10 Input Edge/Level Interrupt

The PIO Controller can be programmed to generate an interrupt when it detects an edge or a level on an I/O line. The Input Edge/Level Interrupt is controlled by writing PIO_IER (Interrupt Enable Register) and PIO_IDR (Interrupt Disable Register), which respectively enable and dis- able the input change interrupt by setting and clearing the corresponding bit in PIO_IMR (Interrupt Mask Register). As Input change detection is possible only by comparing two succes- sive samplings of the input of the I/O line, t he PIO Controller clock must be enabled. The Input Change Interrupt is available, regardless of the configuration of the I/O line, i.e. configured as an input only, controlled by the PIO Controller or assigned to a peripheral function. By default, the interrupt can be generated at any time an edge is detected on the input. Some additional Interrupt modes can be enabled/disabled by writing in the PIO_AIMER (Addi- tional Interrupt Modes Enable Register) and PIO_AIMDR (Additional Interrupt Modes Disable Register). The current state of this sele ction can be read through the PIO_AIMMR (Additional Interrupt Modes Mask Register) These Additional Modes are:

  • Rising Edge Detection
  • Falling Edge Detection
  • Low Level Detection
  • High Level Detection In order to select an Additional Interrupt Mode:
  • The type of event detection (Edge or Level) must be selected by writing in the set of registers; PIO_ESR (Edge Select Register) and PIO_LSR (Level Select Register) which enable respectively, the Edge and Level Detection. The current status of this selection is accessible through the PIO_ELSR (Edge/Level Status Register).
  • The Polarity of the event detection (Rising/Falling Edge or High/Low Level) must be selected by writing in the set of registers; PIO_FELLSR (Falling Edge /Low Level Select Register) and PIO_REHLSR (Rising Edge/High Level Select Register) which allow to select Falling or Rising Edge (if Edge is selected in the PIO_ELSR) Edge or High or Low Level Detection (if Level is selected in the PIO_ELSR). The current status of this selection is accessible through the PIO_FRLHSR (Fall/Rise - Low/High Status Register). When an input Edge or Level is detected on an I/O line, the corresponding bit in PIO_ISR (Inter- rupt Status Register) is set. If the correspo nding bit in PIO_IMR is set, the PIO Controller interrupt line is asserted. The interrupt signals of the thirty-two channels are ORed-wired together to generate a single interrupt signal to the Advanced Interrupt Controller (AIC). When the software reads PIO_ISR, all the interrupts are automatically cleared. This signifies that all the interrupts that are pending when PIO_ISR is read must be handled. When an Interrupt is enabled on a “Level”, the interrupt is generated as long as the interrupt source is not cleared, even if some read accesses in PIO_ISR are performed.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 229 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Figure 23-7. Event Detector on Input Lines (Figure represents line 0)

23.5.10.1 Example

If generating an interrupt is required on the following:

  • Rising edge on PIO line 0
  • Falling edge on PIO line 1
  • Rising edge on PIO line 2
  • Low Level on PIO line 3
  • High Level on PIO line 4
  • High Level on PIO line 5
  • Falling edge on PIO line 6
  • Rising edge on PIO line 7
  • Any edge on the other lines The configuration required is described below.

23.5.10.2 Interrupt Mode Configuration

All the interrupt sources are enabled by writing 32’hFFFF_FFFF in PIO_IER. Then the Additional Interrupt Mode is enabled for line 0 to 7 by writing 32’h0000_00FF in PIO_AIMER.

23.5.10.3 Edge or Level Detection Configuration

Lines 3, 4 and 5 are configured in Level detection by writing 32’h0000_0038 in PIO_LSR. The other lines are configured in Edge detection by default, if they have not been previously con- figured. Otherwise, lines 0, 1, 2, 6 and 7 must be configured in Edge detection by writing 32’h0000_00C7 in PIO_ESR. 23.5.10.4 Falling/Rising Edge or Low/ High Level Detection Configuration. Lines 0, 2, 4, 5 and 7 are configured in Rising Edge or High Level detection by writing 32’h0000_00B5 in PIO_REHLSR. Event Detector Edge Detector Falling Edge Detector Rising Edge Detector PIO_FELLSR[0] PIO_FRLHSR[0] PIO_REHLSR[0] Low Level Detector High Level Detector PIO_ESR[0] PIO_ELSR[0] PIO_LSR[0] PIO_AIMDR[0] PIO_AIMMR[0] PIO_AIMER[0] Event detection on line 0 Resynchronized input on line 0

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 230 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 The other lines are configured in Falling Edge or Low Level detection by default, if they have not been previously configured. Otherwise, lines 1, 3 and 6 must be configured in Falling Edge/Low Level detection by writing 32’h0000_004A in PIO_FELLSR. Figure 23-8. Input Change Interrupt Timings if there are no Additional Interrupt Modes

23.5.11 I/O Lines Lock

When an I/O line is controlled by a peripheral (particularly the Pulse Width Modulation Controller PWM), it can become locked by the action of th is peripheral via an input of the PIO controller. When an I/O line is locked, the write of the corresponding bit in the registers PIO_PER, PIO_PDR, PIO_MDER, PIO_MDDR, P IO_PUDR, PIO_PUER, PIO_ABCDSR1 and PIO_ABCDSR2 is discarded in order to lock its configuration. The user can know at anytime which I/O line is locked by reading the PIO Lock Status register PIO_LOCKSR. Once an I/O line is locked, the only way to unlock it is to apply a hardware reset to the PIO Controller.

23.5.12 Programmable I/O Delays

The PIO interface consists of a series of signal s driven by peripherals or directly by software. The simultaneous switching outputs on these busses may lead to a peak of current in the inter- nal and external power supply lines. In order to reduce the current peak in such cases, additional propagation delays can be adjusted independently for pad buffers by means of configuration registers, PIO_DELAY. The additional programmable delays for each supporting range from 0 to 4 ns (Worst Case PVT). The delay can differ between I/Os supporting this feature. Delay can be modified per pro- gramming for each I/O. The minimal additional delay that can be programmed on a PAD supporting this feature is 1/16 of the maximum programmable delay. Only PADs PA[15:11], and PA[20:18] can be configured. When programming 0x0 in fields, no delay is added (reset value) and the propagation delay of the pad buffers is the inherent delay of the pad buffer. When programming 0xF in fields, the propagation delay of the corresponding pad is maximal. MCK Pin Level Read PIO_ISR APB Access PIO_ISR APB Access

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 231 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Figure 23-9. Programmable I/O Delays

23.5.13 Programmable I/O Drive

It is possible to configure the I/O drive for pads PA[31:0], PB[18:0], PC[31:0]. For any details, refer to the product electrical characteristics.

23.5.14 Programmable Schmitt Trigger

It is possible to configure each input for the Schmitt Trigger. By default the Schmitt trigger is active. Disabling the Schmitt Trigger is requested when using the QTouch™ Library.

23.5.15 Write Protection Registers

To prevent any single software error that may corrupt PIO behavior, certain address spaces can be write-protected by setting the WPEN bit in the “PIO Write Protect Mode Register” (PIO_WPMR). If a write access to the protected registers is detected, then the WPVS flag in the PIO Write Pro- tect Status Register (PIO_WPSR) is set and the field WPVSRC indicates in which register the write access has been attempted. The WPVS flag is reset by writing the PIO Write Protect Mode Register (PIO_WPMR) with the appropriate access key, WPKEY. The protected registers are:

  • “PIO Enable Register” on page 237
  • “PIO Disable Register” on page 237
  • “PIO Output Enable Register” on page 238
  • “PIO Output Disable Register” on page 239
  • “PIO Input Filter Enable Register” on page 240
  • “PIO Input Filter Disable Register” on page 240
  • “PIO Multi-driver Enable Register” on page 245
  • “PIO Multi-driver Disable Register” on page 246
  • “PIO Pull Up Disable Register” on page 247 DELAY1 Programmable Delay Line PIO PAout[0] PAin[0] DELAY2 Programmable Delay Line DELAYx Programmable Delay Line PAout[1] PAin[1] PAout[2] PAin[2]

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 232 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

  • “PIO Pull Up Enable Register” on page 247
  • “PIO Peripheral ABCD Select Register 1” on page 249
  • “PIO Peripheral ABCD Select Register 2” on page 250
  • “PIO Output Write Enable Register” on page 255
  • “PIO Output Write Disable Register” on page 255
  • “PIO Pad Pull Down Disable Register” on page 253
  • “PIO Pad Pull Down Status Register” on page 254

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 233 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

23.6 I/O Lines Programming Example

The programing example as shown in Table 23-1 below is used to obtain the following configuration.

  • 4-bit output port on I/O lines 0 to 3, (should be written in a single write operation), open-drain, with pull-up resistor
  • Four output signals on I/O lines 4 to 7 (to drive LEDs for example), driven high and low, no pull-up resistor, no pull-down resistor
  • Four input signals on I/O lines 8 to 11 (to read push-button states for example), with pull-up resistors, glitch filters and input change interrupts
  • Four input signals on I/O line 12 to 15 to read an external device status (polled, thus no input change interrupt), no pull-up resistor, no glitch filter
  • I/O lines 16 to 19 assigned to peripheral A functions with pull-up resistor
  • I/O lines 20 to 23 assigned to peripheral B functions with pull-down resistor
  • I/O line 24 to 27 assigned to peripheral C with Input Change Interrupt, no pull-up resistor and no pull-down resistor
  • I/O line 28 to 31 assigned to peripheral D, no pull-up resistor and no pull-down resistor Table 23-1. Programming Example Register Value to be Written PIO_PER 0x0000_FFFF PIO_PDR 0xFFFF_0000 PIO_OER 0x0000_00FF PIO_ODR 0xFFFF_FF00 PIO_IFER 0x0000_0F00 PIO_IFDR 0xFFFF_F0FF PIO_SODR 0x0000_0000 PIO_CODR 0x0FFF_FFFF PIO_IER 0x0F00_0F00 PIO_IDR 0xF0FF_F0FF PIO_MDER 0x0000_000F PIO_MDDR 0xFFFF_FFF0 PIO_PUDR 0xFFF0_00F0 PIO_PUER 0x000F_FF0F PIO_PPDDR 0xFF0F_FFFF PIO_PPDER 0x00F0_0000 PIO_ABCDSR1 0xF0F0_0000 PIO_ABCDSR2 0xFF00_0000 PIO_OWER 0x0000_000F PIO_OWDR 0x0FFF_ FFF0

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 234 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

23.7 Parallel Input/Output Cont roller (PIO) User Interface

Each I/O line controlled by the PIO Controller is associated with a bit in each of the PIO Control- ler User Interface registers. Each register is 32 bits wide. If a parallel I/O line is not defined, writing to the corresponding bits has no effect. Undefined bits read zero. If the I/O line is not mul- tiplexed with any peripheral, the I/O line is controlled by the PIO Controller and PIO_PSR returns 1 systematically. Table 23-2. Register Mapping Offset Register Name Access Reset 0x0000 PIO Enable Register PIO_PER Write-only – 0x0004 PIO Disable Register PIO_PDR Write-only – 0x0008 PIO Status Register PIO_PSR Read-only (1) 0x000C Reserved 0x0010 Output Enable Register PIO_OER Write-only – 0x0014 Output Disable Register PIO_ODR Write-only – 0x0018 Output Status Regist er PIO_OSR Read-only 0x0000 0000 0x001C Reserved 0x0020 Glitch Input Filter Enab le Register PIO_IFER Write-only – 0x0024 Glitch Input Filter Disab le Register PIO_IFDR Write-only – 0x0028 Glitch Input Filt er Status Register PIO_IFSR Read-only 0x0000 0000 0x002C Reserved 0x0030 Set Output Data R egister PIO_SODR Write-only – 0x0034 Clear Output Data Register PIO_CODR Write-only 0x0038 Output Data Status Register PIO_ODSR Read-only or (2) Read-write 0x003C Pin Data Status Register PIO_PDSR Read-only (3) 0x0040 Interrupt Enable Register PIO_IER Write-only – 0x0044 Interrupt Disable Register PIO_IDR Write-only – 0x0048 Interrupt Mask Register PIO_IMR Read-only 0x00000000 0x004C Interrupt Status Register (4) PIO_ISR Read-only 0x00000000 0x0050 Multi-driver Enable Register PIO_MDER Write-only – 0x0054 Multi-driver Disable Register PIO_MDDR Write-only – 0x0058 Multi-driver Status R egister PIO_MDSR Read-only 0x00000000 0x005C Reserved 0x0060 Pull-up Disable Register PIO_PUDR Write-only – 0x0064 Pull-up Enable Register PIO_PUER Write-only – 0x0068 Pad Pull-up Status Register PIO_PUSR Read-only (1) 0x006C Reserved

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 235 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 0x0070 Peripheral Select Register 1 PIO_ABCDSR1 Read-write 0x00000000 0x0074 Peripheral Select Register 2 PIO_ABCDSR2 Read-write 0x00000000 0x0078 to 0x007C Reserved 0x0080 Input Filter Slow Clock Disa ble Register PIO_IFSCDR Write-only – 0x0084 Input Filter Slow Clock Enable Register PIO_IFSCER Write-only – 0x0088 Input Filter Slow Clock Status Register PIO_IFSCSR Read-only 0x00000000 0x008C Slow Clock Divider Debouncing Register PIO_SCDR Read-write 0x00000000 0x0090 Pad Pull-down Disable Register PIO_PPDDR Write-only – 0x0094 Pad Pull-down Enable Register PIO_PPDER Write-only – 0x0098 Pad Pull-down Status Register PIO_PPDSR Read-only (1) 0x009C Reserved 0x00A0 Output Write Enab le PIO_OWER Write-only – 0x00A4 Output Write Disable PIO_OWDR Write-only – 0x00A8 Output Write Status Register PIO_OWSR Read-only 0x00000000 0x00AC Reserved 0x00B0 Additional Interrupt Modes Enable Register PIO_AIMER Write-only – 0x00B4 Additional Interrupt Modes Disables Register PIO_AIMDR Write-only – 0x00B8 Additional Interrupt Modes Mask Register PIO_AIMMR Read-only 0x00000000 0x00BC Reserved 0x00C0 Edge Select Register PIO_ESR Write-only – 0x00C4 Level Select Register PIO_LSR Write-only – 0x00C8 Edge/Level Status Regi ster PIO_ELSR Read-only 0x00000000 0x00CC Reserved 0x00D0 Falling Edge/Low Level Select Register PIO_FELLSR Write-only – 0x00D4 Rising Edge/ High Level Select Register PIO_REHLSR Write-only – 0x00D8 Fall/Rise - Low/High Status Register PIO_FRLHSR Read-only 0x00000000 0x00DC Reserved 0x00E0 Lock Status PIO_LOCKSR Read-only 0x00000000 0x00E4 Write Protect Mode Register PIO_WPMR Read-write 0x0 0x00E8 Write Protect Status Register PIO_WPSR Read-only 0x0 0x00EC to 0x00F8 Reserved 0x0100 Schmitt Trigger Register PIO_SCHMITT Read-write 0x00000000 0x0104- 0x010C Reserved 0x0110 IO Delay Register PIO_DELAYR Read-write 0x00000000 Table 23-2. Register Mapping (Continued) Offset Register Name Access Reset

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 236 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Notes: 1. Reset value depends on the product implementation. 2. PIO_ODSR is Read-only or Read/Write depending on PIO_OWSR I/O lines. 3. Reset value of PIO_PDSR depends on the level of the I/O line s. Reading the I/O line levels requires the clock of the PIO Controller to be enabled, otherwise PIO_PDSR reads the levels present on the I/O line at the time the clock was disabled. 4. PIO_ISR is reset at 0x0. However, the first read of the register may read a different value as input changes may have occurred. Note: if an offset is not listed in the table it must be considered as reserved. 0x0114 I/O Drive Register 1 PIO_DRIVER1 Read-write 0x00000000 0x0118 I/O Drive Register 2 PIO_DRIVER2 Read-write 0x00000000 0x011C Reserved Table 23-2. Register Mapping (Continued) Offset Register Name Access Reset

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 237 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

23.7.1 PIO Enable Register

Name: PIO_PER Address: 0xFFFFF400 (PIOA), 0xFFFFF600 (PIOB), 0xFFFFF800 (PIOC), 0xFFFFFA00 (PIOD) Access: Write-only This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register” .  P0-P31: PIO Enable 0: No effect. 1: Enables the PIO to control the corresponding pin (disables peripheral control of the pin).

23.7.2 PIO Disable Register

Name: PIO_PDR Address: 0xFFFFF404 (PIOA), 0xFFFFF604 (PIOB), 0xFFFFF804 (PIOC), 0xFFFFFA04 (PIOD) Access: Write-only This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register” .  P0-P31: PIO Disable 0: No effect. 1: Disables the PIO from controlling the corresponding pin (enables peripheral control of the pin). 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 238 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

23.7.3 PIO Status Register

Name: PIO_PSR Address: 0xFFFFF408 (PIOA), 0xFFFFF608 (PIOB), 0xFFFFF808 (PIOC), 0xFFFFFA08 (PIOD) Access: Read-only  P0-P31: PIO Status 0: PIO is inactive on the corresponding I/O line (peripheral is active). 1: PIO is active on the corresponding I/O line (peripheral is inactive).

23.7.4 PIO Output Enable Register

Name: PIO_OER Address: 0xFFFFF410 (PIOA), 0xFFFFF610 (PIOB), 0xFFFFF810 (PIOC), 0xFFFFFA10 (PIOD) Access: Write-only This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register” .  P0-P31: Output Enable 0: No effect. 1: Enables the output on the I/O line. 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 239 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

23.7.5 PIO Output Disable Register

Name: PIO_ODR Address: 0xFFFFF414 (PIOA), 0xFFFFF614 (PIOB), 0xFFFFF814 (PIOC), 0xFFFFFA14 (PIOD) Access: Write-only This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register” .  P0-P31: Output Disable 0: No effect. 1: Disables the output on the I/O line.

23.7.6 PIO Output Status Register

Name: PIO_OSR Address: 0xFFFFF418 (PIOA), 0xFFFFF618 (PIOB), 0xFFFFF818 (PIOC), 0xFFFFFA18 (PIOD) Access: Read-only  P0-P31: Output Status 0: The I/O line is a pure input. 1: The I/O line is enabled in output. 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 240 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

23.7.7 PIO Input Filter Enable Register

Name: PIO_IFER Address: 0xFFFFF420 (PIOA), 0xFFFFF620 (PIOB), 0xFFFFF820 (PIOC), 0xFFFFFA20 (PIOD) Access: Write-only This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register” .  P0-P31: Input Filter Enable 0: No effect. 1: Enables the input glitch filter on the I/O line.

23.7.8 PIO Input Filter Disable Register

Name: PIO_IFDR Address: 0xFFFFF424 (PIOA), 0xFFFFF624 (PIOB), 0xFFFFF824 (PIOC), 0xFFFFFA24 (PIOD) Access: Write-only This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register” .  P0-P31: Input Filter Disable 0: No effect. 1: Disables the input glitch filter on the I/O line. 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 241 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

23.7.9 PIO Input Filter Status Register

Name: PIO_IFSR Address: 0xFFFFF428 (PIOA), 0xFFFFF628 (PIOB), 0xFFFFF828 (PIOC), 0xFFFFFA28 (PIOD) Access: Read-only  P0-P31: Input Filer Status 0: The input glitch filter is disabled on the I/O line. 1: The input glitch filter is enabled on the I/O line.

23.7.10 PIO Set Output Data Register

Name: PIO_SODR Address: 0xFFFFF430 (PIOA), 0xFFFFF630 (PIOB), 0xFFFFF830 (PIOC), 0xFFFFFA30 (PIOD) Access: Write-only  P0-P31: Set Output Data 0: No effect. 1: Sets the data to be driven on the I/O line. 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 242 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

23.7.11 PIO Clear Output Data Register

Name: PIO_CODR Address: 0xFFFFF434 (PIOA), 0xFFFFF634 (PIOB), 0xFFFFF834 (PIOC), 0xFFFFFA34 (PIOD) Access: Write-only  P0-P31: Clear Output Data 0: No effect. 1: Clears the data to be driven on the I/O line.

23.7.12 PIO Output Data Status Register

Name: PIO_ODSR Address: 0xFFFFF438 (PIOA), 0xFFFFF638 (PIOB), 0xFFFFF838 (PIOC), 0xFFFFFA38 (PIOD) Access: Read-only or Read-write  P0-P31: Output Data Status 0: The data to be driven on the I/O line is 0. 1: The data to be driven on the I/O line is 1. 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 243 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

23.7.13 PIO Pin Data Status Register

Name: PIO_PDSR Address: 0xFFFFF43C (PIOA), 0xFFFFF63C (PIOB), 0xFFFFF83C (PIOC), 0xFFFFFA3C (PIOD) Access: Read-only  P0-P31: Output Data Status 0: The I/O line is at level 0. 1: The I/O line is at level 1.

23.7.14 PIO Interrupt Enable Register

Name: PIO_IER Address: 0xFFFFF440 (PIOA), 0xFFFFF640 (PIOB), 0xFFFFF840 (PIOC), 0xFFFFFA40 (PIOD) Access: Write-only  P0-P31: Input Change Interrupt Enable 0: No effect. 1: Enables the Input Change Interrupt on the I/O line. 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 244 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

23.7.15 PIO Interrupt Disable Register

Name: PIO_IDR Address: 0xFFFFF444 (PIOA), 0xFFFFF644 (PIOB), 0xFFFFF844 (PIOC), 0xFFFFFA44 (PIOD) Access: Write-only  P0-P31: Input Change Interrupt Disable 0: No effect. 1: Disables the Input Change Interrupt on the I/O line.

23.7.16 PIO Interrupt Mask Register

Name: PIO_IMR Address: 0xFFFFF448 (PIOA), 0xFFFFF648 (PIOB), 0xFFFFF848 (PIOC), 0xFFFFFA48 (PIOD) Access: Read-only  P0-P31: Input Change Interrupt Mask 0: Input Change Interrupt is disabled on the I/O line. 1: Input Change Interrupt is enabled on the I/O line. 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 245 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

23.7.17 PIO Interrupt Status Register

Name: PIO_ISR Address: 0xFFFFF44C (PIOA), 0xFFFFF64C (PIOB), 0xFFFFF84C (PIOC), 0xFFFFFA4C (PIOD) Access: Read-only  P0-P31: Input Change Interrupt Status 0: No Input Change has been detected on the I/O line since PIO_ISR was last read or since reset. 1: At least one Input Change has been detected on the I/O line since PIO_ISR was last read or since reset.

23.7.18 PIO Multi-driver Enable Register

Name: PIO_MDER Address: 0xFFFFF450 (PIOA), 0xFFFFF650 (PIOB), 0xFFFFF850 (PIOC), 0xFFFFFA50 (PIOD) Access: Write-only This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register” .  P0-P31: Multi Drive Enable. 0: No effect. 1: Enables Multi Drive on the I/O line. 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 246 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

23.7.19 PIO Multi-driver Disable Register

Name: PIO_MDDR Address: 0xFFFFF454 (PIOA), 0xFFFFF654 (PIOB), 0xFFFFF854 (PIOC), 0xFFFFFA54 (PIOD) Access: Write-only This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register” .  P0-P31: Multi Drive Disable. 0: No effect. 1: Disables Multi Drive on the I/O line.

23.7.20 PIO Multi-driver Status Register

Name: PIO_MDSR Address: 0xFFFFF458 (PIOA), 0xFFFFF658 (PIOB), 0xFFFFF858 (PIOC), 0xFFFFFA58 (PIOD) Access: Read-only  P0-P31: Multi Drive Status. 0: The Multi Drive is disabled on the I/O line. The pin is driven at high and low level. 1: The Multi Drive is enabled on the I/O line. The pin is driven at low level only. 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 247 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

23.7.21 PIO Pull Up Disable Register

Name: PIO_PUDR Address: 0xFFFFF460 (PIOA), 0xFFFFF660 (PIOB), 0xFFFFF860 (PIOC), 0xFFFFFA60 (PIOD) Access: Write-only This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register” .  P0-P31: Pull Up Disable. 0: No effect. 1: Disables the pull up resistor on the I/O line.

23.7.22 PIO Pull Up Enable Register

Name: PIO_PUER Address: 0xFFFFF464 (PIOA), 0xFFFFF664 (PIOB), 0xFFFFF864 (PIOC), 0xFFFFFA64 (PIOD) Access: Write-only This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register” .  P0-P31: Pull Up Enable. 0: No effect. 1: Enables the pull up resistor on the I/O line. 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 248 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

23.7.23 PIO Pull Up Status Register

Name: PIO_PUSR Address: 0xFFFFF468 (PIOA), 0xFFFFF668 (PIOB), 0xFFFFF868 (PIOC), 0xFFFFFA68 (PIOD) Access: Read-only  P0-P31: Pull Up Status. 0: Pull Up resistor is enabled on the I/O line. 1: Pull Up resistor is disabled on the I/O line. 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 249 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

23.7.24 PIO Peripheral A BCD Select Register 1

Name: PIO_ABCDSR1 Access: Read-write This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register” .  P0-P31: Peripheral Select. If the same bit is set to 0 in PIO_ABCDSR2: 0: Assigns the I/O line to the Peripheral A function. 1: Assigns the I/O line to the Peripheral B function. If the same bit is set to 1 in PIO_ABCDSR2: 0: Assigns the I/O line to the Peripheral C function. 1: Assigns the I/O line to the Peripheral D function. 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 250 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

23.7.25 PIO Peripheral A BCD Select Register 2

Name: PIO_ABCDSR2 Access: Read-write This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register” .  P0-P31: Peripheral Select. If the same bit is set to 0 in PIO_ABCDSR1: 0: Assigns the I/O line to the Peripheral A function. 1: Assigns the I/O line to the Peripheral C function. If the same bit is set to 1 in PIO_ABCDSR1: 0: Assigns the I/O line to the Peripheral B function. 1: Assigns the I/O line to the Peripheral D function. 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 251 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

23.7.26 PIO Input Filter Slow Clock Disable Register

Name: PIO_IFSCDR Address: 0xFFFFF480 (PIOA), 0xFFFFF680 (PIOB), 0xFFFFF880 (PIOC), 0xFFFFFA80 (PIOD) Access: Write-only  P0-P31: PIO Clock Glitch Filtering Select. 0: No Effect. 1: The Glitch Filter is able to filter glitches with a duration < Tmck/2.

23.7.27 PIO Input Filter Slow Clock Enable Register

Name: PIO_IFSCER Address: 0xFFFFF484 (PIOA), 0xFFFFF684 (PIOB), 0xFFFFF884 (PIOC), 0xFFFFFA84 (PIOD) Access: Write-only  P0-P31: Debouncing Filtering Select. 0: No Effect. 1: The Debouncing Filter is able to filter pulses with a duration < Tdiv_slclk/2. 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 252 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

23.7.28 PIO Input Filter Slow Clock Status Register

Name: PIO_IFSCSR Address: 0xFFFFF488 (PIOA), 0xFFFFF688 (PIOB), 0xFFFFF888 (PIOC), 0xFFFFFA88 (PIOD) Access: Read-only  P0-P31: Glitch or Debouncing Filter Selection Status 0: The Glitch Filter is able to filter glitches with a duration < Tmck2. 1: The Debouncing Filter is able to filter pulses with a duration < Tdiv_slclk/2.

23.7.29 PIO Slow Clock Divider Debouncing Register

Name: PIO_SCDR Address: 0xFFFFF48C (PIOA), 0xFFFFF68C (PIOB), 0xFFFFF88C (PIOC), 0xFFFFFA8C (PIOD) Access: Read-write  DIVx: Slow Clock Divider Selection for Debouncing Tdiv_slclk = 2*(DIV+1)*Tslow_clock. 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 –– DIV 76543210 DIV

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 253 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

23.7.30 PIO Pad Pull Down Disable Register

Name: PIO_PPDDR Address: 0xFFFFF490 (PIOA), 0xFFFFF690 (PIOB), 0xFFFFF890 (PIOC), 0xFFFFFA90 (PIOD) Access: Write-only This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register” .  P0-P31: Pull Down Disable. 0: No effect. 1: Disables the pull down resistor on the I/O line.

23.7.31 PIO Pad Pull Down Enable Register

Name: PIO_PPDER Address: 0xFFFFF494 (PIOA), 0xFFFFF694 (PIOB), 0xFFFFF894 (PIOC), 0xFFFFFA94 (PIOD) Access: Write-only This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register” .  P0-P31: Pull Down Enable. 0: No effect. 1: Enables the pull down resistor on the I/O line. 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 254 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

23.7.32 PIO Pad Pull Down Status Register

Name: PIO_PPDSR Address: 0xFFFFF498 (PIOA), 0xFFFFF698 (PIOB), 0xFFFFF898 (PIOC), 0xFFFFFA98 (PIOD) Access: Read-only This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register” .  P0-P31: Pull Down Status. 0: Pull Down resistor is enabled on the I/O line. 1: Pull Down resistor is disabled on the I/O line. 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 255 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

23.7.33 PIO Output Write Enable Register

Name: PIO_OWER Address: 0xFFFFF4A0 (PIOA), 0xFFFFF6A0 (PIOB), 0xFFFFF8A0 (PIOC), 0xFFFFFAA0 (PIOD) Access: Write-only This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register” .  P0-P31: Output Write Enable. 0: No effect. 1: Enables writing PIO_ODSR for the I/O line.

23.7.34 PIO Output Write Disable Register

Name: PIO_OWDR Address: 0xFFFFF4A4 (PIOA), 0xFFFFF6A4 (PIOB), 0xFFFFF8A4 (PIOC), 0xFFFFFAA4 (PIOD) Access: Write-only This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register” .  P0-P31: Output Write Disable. 0: No effect. 1: Disables writing PIO_ODSR for the I/O line. 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 256 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

23.7.35 PIO Output Write Status Register

Name: PIO_OWSR Address: 0xFFFFF4A8 (PIOA), 0xFFFFF6A8 (PIOB), 0xFFFFF8A8 (PIOC), 0xFFFFFAA8 (PIOD) Access: Read-only  P0-P31: Output Write Status. 0: Writing PIO_ODSR does not affect the I/O line. 1: Writing PIO_ODSR affects the I/O line.

23.7.36 PIO Additional Interrupt Modes Enable Register

Name: PIO_AIMER Address: 0xFFFFF4B0 (PIOA), 0xFFFFF6B0 (PIOB), 0xFFFFF8B0 (PIOC), 0xFFFFFAB0 (PIOD) Access: Write-only  P0-P31: Additional Interrupt Modes Enable. 0: No effect. 1: The interrupt source is the event described in PIO_ELSR and PIO_FRLHSR. 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 257 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

23.7.37 PIO Additional Interrupt Modes Disable Register

Name: PIO_AIMDR Address: 0xFFFFF4B4 (PIOA), 0xFFFFF6B4 (PIOB), 0xFFFFF8B4 (PIOC), 0xFFFFFAB4 (PIOD) Access: Write-only  P0-P31: Additional Interrupt Modes Disable. 0: No effect. 1: The interrupt mode is set to the default interrupt mode (Both Edge detection).

23.7.38 PIO Additional Interrupt Modes Mask Register

Name: PIO_AIMMR Address: 0xFFFFF4B8 (PIOA), 0xFFFFF6B8 (PIOB), 0xFFFFF8B8 (PIOC), 0xFFFFFAB8 (PIOD) Access: Read-only  P0-P31: Peripheral CD Status. 0: The interrupt source is a Both Edge detection event 1: The interrupt source is described by the registers PIO_ELSR and PIO_FRLHSR 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 258 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

23.7.39 PIO Edge Select Register

Name: PIO_ESR Address: 0xFFFFF4C0 (PIOA), 0xFFFFF6C0 (PIOB), 0xFFFFF8C0 (PIOC), 0xFFFFFAC0 (PIOD) Access: Write-only  P0-P31: Edge In terrupt Selection. 0: No effect. 1: The interrupt source is an Edge detection event.

23.7.40 PIO Level Select Register

Name: PIO_LSR Address: 0xFFFFF4C4 (PIOA), 0xFFFFF6C4 (PIOB), 0xFFFFF8C4 (PIOC), 0xFFFFFAC4 (PIOD) Access: Write-only  P0-P31: Level Interrupt Selection. 0: No effect. 1: The interrupt source is a Level detection event. 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 259 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

23.7.41 PIO Edge/Level Status Register

Name: PIO_ELSR Address: 0xFFFFF4C8 (PIOA), 0xFFFFF6C8 (PIOB), 0xFFFFF8C8 (PIOC), 0xFFFFFAC8 (PIOD) Access: Read-only  P0-P31: Edge/Level Interrupt source selection. 0: The interrupt source is an Edge detection event. 1: The interrupt source is a Level detection event.

23.7.42 PIO Falling Edge/Low Level Select Register

Name: PIO_FELLSR Address: 0xFFFFF4D0 (PIOA), 0xFFFFF6D0 (PIOB), 0xFFFFF8D0 (PIOC), 0xFFFFFAD0 (PIOD) Access: Write-only  P0-P31: Falling Edge/Low Level Interrupt Selection. 0: No effect. 1: The interrupt source is set to a Falling Edge detection or Low Level detection event, depending on PIO_ELSR. 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 260 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

23.7.43 PIO Rising Edge/High Level Select Register

Name: PIO_REHLSR Address: 0xFFFFF4D4 (PIOA), 0xFFFFF6D4 (PIOB), 0xFFFFF8D4 (PIOC), 0xFFFFFAD4 (PIOD) Access: Write-only  P0-P31: Rising Edge /High Level Interrupt Selection. 0: No effect. 1: The interrupt source is set to a Rising Edge detection or High Level detection event, depending on PIO_ELSR.

23.7.44 PIO Fall/Rise - Low/High Status Register

Name: PIO_FRLHSR Address: 0xFFFFF4D8 (PIOA), 0xFFFFF6D8 (PIOB), 0xFFFFF8D8 (PIOC), 0xFFFFFAD8 (PIOD) Access: Read-only  P0-P31: Edge /Level Interrupt Source Selection. 0: The interrupt source is a Falling Edge detection (if PIO_ELSR = 0) or Low Level detection event (if PIO_ELSR = 1). 1: The interrupt source is a Rising Edge detection (if PIO_ELSR = 0) or High Level detection event (if PIO_ELSR = 1). 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 261 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

23.7.45 PIO Lock Status Register

Name: PIO_LOCKSR Address: 0xFFFFF4E0 (PIOA), 0xFFFFF6E0 (PIOB), 0xFFFFF8E0 (PIOC), 0xFFFFFAE0 (PIOD) Access: Read-only  P0-P31: Lock Status. 0: The I/O line is not locked. 1: The I/O line is locked. 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 262 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

23.7.46 PIO Write Protect Mode Register

Name: PIO_WPMR Address: 0xFFFFF4E4 (PIOA), 0xFFFFF6E4 (PIOB), 0xFFFFF8E4 (PIOC), 0xFFFFFAE4 (PIOD) Access: Read-write Reset: See Table 23-2 For more information on Write Protection Registers, refer to Section 23.7 ”Parallel Input/Output Controller (PIO) User Interface”.  WPEN: Write Protect Enable 0: Disables the Write Protect if WPKEY corresponds to 0x50494F (“PIO” in ASCII). 1: Enables the Write Protect if WPKEY corresponds to 0x50494F (“PIO” in ASCII). Protects the registers: “PIO Enable Register” on page 237 “PIO Disable Register” on page 237 “PIO Output Enable Register” on page 238 “PIO Output Disable Register” on page 239 “PIO Input Filter Enable Register” on page 240 “PIO Input Filter Disable Register” on page 240 “PIO Multi-driver Enable Register” on page 245 “PIO Multi-driver Disable Register” on page 246 “PIO Pull Up Disable Register” on page 247 “PIO Pull Up Enable Register” on page 247 “PIO Peripheral ABCD Select Register 1” on page 249 “PIO Peripheral ABCD Select Register 2” on page 250 “PIO Output Write Enable Register” on page 255 “PIO Output Write Disable Register” on page 255 “PIO Pad Pull Down Disable Register” on page 253 “PIO Pad Pull Down Status Register” on page 254  WPKEY: Write Protect KEY Should be written at value 0x50494F (“PIO” in ASCII). Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. 31 30 29 28 27 26 25 24 WPKEY 23 22 21 20 19 18 17 16 WPKEY 15 14 13 12 11 10 9 8 WPKEY 76543210

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 263 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

23.7.47 PIO Write Protect Status Register

Name: PIO_WPSR Address: 0xFFFFF4E8 (PIOA), 0xFFFFF6E8 (PIOB), 0xFFFFF8E8 (PIOC), 0xFFFFFAE8 (PIOD) Access: Read-only Reset: See Table 23-2  WPVS: Write Protect Violation Status 0: No Write Protect Violation has occurred since the last read of the PIO_WPSR register. 1: A Write Protect Violation has occurred since the last read of the PIO_WPSR register. If this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field WPVSRC.  WPVSRC: Write Protect Violation Source When WPVS is active, this field indicates the write-protected register (t hrough address offset or code) in which a write access has been attempted. Note: Reading PIO_WPSR automatically clears all fields. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WPVSRC 15 14 13 12 11 10 9 8 WPVSRC 76543210

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 264 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

23.7.48 PIO Schmitt Trigger Register

Name: PIO_SCHMITT Address: 0xFFFFF500 (PIOA), 0xFFFFF700 (PIOB), 0xFFFFF900 (PIOC), 0xFFFFFB00 (PIOD) Access: Read-write Reset: See Figure 23-2  SCHMITTx [x=0..31]: 0: Schmitt Trigger is enabled. 1= Schmitt Trigger is disabled. 31 30 29 28 27 26 25 24 SCHMITT31 SCHMITT30 SCHMITT29 SCHMITT28 SCHMITT27 SCHMITT26 SCHMITT25 SCHMITT24 23 22 21 20 19 18 17 16 SCHMITT23 SCHMITT22 SCHMITT21 SCHMITT20 SCHMITT19 SCHMITT18 SCHMITT17 SCHMITT16 15 14 13 12 11 10 9 8 SCHMITT15 SCHMITT14 SCHMITT13 SCHMITT12 SCHMITT11 SCHMITT10 SCHMITT9 SCHMITT8 76543210 SCHMITT7 SCHMITT6 SCHMITT5 SCHMITT4 SCHMITT3 SCHMITT2 SCHMITT1 SCHMITT0

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 265 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

23.7.49 PIO I/O Delay Register

Name: PIO_DELAYR Address: 0xFFFFF510 (PIOA), 0xFFFFF710 (PIOB), 0xFFFFF910 (PIOC), 0xFFFFFB10 (PIOD) Access: Read-write Reset: See Figure 23-2  Delay x: Gives the number of elements in the delay line associated to pad x. 31 30 29 28 27 26 25 24 Delay7 Delay6 23 22 21 20 19 18 17 16 Delay5 Delay4 15 14 13 12 11 10 9 8 Delay3 Delay2 76543210 Delay1 Delay0

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 266 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

23.7.50 PIO I/O Drive Register 1

Name: PIO_DRIVER1 Address: 0xFFFFF514 (PIOA), 0xFFFFF714 (PIOB), 0xFFFFF914 (PIOC), 0xFFFFFB14 (PIOD) Access: Read-write Reset: 0x0  LINEx [x=0..15]: Drive of PIO line x 31 30 29 28 27 26 25 24 LINE15 LINE14 LINE13 LINE12 23 22 21 20 19 18 17 16 LINE11 LINE10 LINE9 LINE8 15 14 13 12 11 10 9 8 LINE7 LINE6 LINE5 LINE4 76543210 LINE3 LINE2 LINE1 LINE0 Value Name Description

0 HI_DRIVE High drive

1 ME_DRIVE Medium drive

2 LO_DRIVE Low drive

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 267 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

23.7.51 PIO I/O Drive Register 2

Name: PIO_DRIVER2 Address: 0xFFFFF518 (PIOA), 0xFFFFF718 (PIOB), 0xFFFFF918 (PIOC), 0xFFFFFB18 (PIOD) Access: Read-write Reset: 0x0  LINEx [x=16..31]: Drive of PIO line x 31 30 29 28 27 26 25 24 LINE31 LINE30 LINE29 LINE28 23 22 21 20 19 18 17 16 LINE27 LINE26 LINE25 LINE24 15 14 13 12 11 10 9 8 LINE23 LINE22 LINE21 LINE20 76543210 LINE19 LINE18 LINE17 LINE16 Value Name Description

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 268 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 24. Debug Unit (DBGU)

24.1 Description

The Debug Unit provides a single entry point from the processor for access to all the debug capabilities of Atmel’s ARM-based systems. The Debug Unit features a two-pin UART that can be used for several debug and trace purposes and offers an ideal medium for in-situ programming solutions and debug monitor communica- tions. The Debug Unit two-pin UART can be used stand-alone for general purpose serial communication. Moreover, the association with DMA controller channels permits packet han- dling for these tasks with processor time reduced to a minimum. The Debug Unit also makes the Debug Communication Channel (DCC) signals provided by the In-circuit Emulator of the ARM processor visible to the software. These signals indicate the sta- tus of the DCC read and write registers and generate an interrupt to the ARM processor, making possible the handling of the DCC under interrupt control. Chip Identifier registers permit recognition of t he device and its revision. These registers inform as to the sizes and types of the on-chip memories, as well as the set of embedded peripherals. Finally, the Debug Unit features a Force NTRST capability that enables the software to decide whether to prevent access to the system via th e In-circuit Emulator. Th is permits protection of the code, stored in ROM.

24.2 Embedded Characteristics

  • System Peripheral to Facilitate Debug of Atmel® ARM®-based Systems
  • Composed of Four Functions –T w o - p i n U A R T – Debug Communication Channel (DCC) Support – Chip ID Registers – ICE Access Prevention
  • T w o - p i n U A R T – Implemented Features are USART Compatible – Independent Receiver and Transmitter with a Common Programmable Baud Rate Generator – Even, Odd, Mark or Space Parity Generation – Parity, Framing and Overrun Error Detection – Automatic Echo, Local Loopback and Remote Loopback Channel Modes – Interrupt Generation – Support for Two DMA Channels with Connection to Receiver and Transmitter
  • Debug Communication Channel Support – Offers Visibility of COMMRX and COMMTX Signals from the ARM Processor – Interrupt Generation
  • Chip ID Registers – Identification of the Device Revision, Sizes of the Embedded Memories, Set of Peripherals

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

  • ICE Access Prevention – Enables Software to Prevent System Access Through the ARM Processor’s ICE – Prevention is Made by Asserting the NTRST Line of the ARM Processor’s ICE

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

24.3 Block Diagram

Figure 24-1. Debug Unit Functional Block Diagram Figure 24-2. Debug Unit Application Example (Peripheral) DMA Controller Baud Rate Generator DCC Handler ICE Access Handler Transmit Receive Chip ID Interrupt Control Peripheral Bridge Parallel Input/ Output DTXD DRXD Power Management Controller ARM Processor force_ntrst COMMRX COMMTX MCK nTRST Power-on Reset dbgu_irq APB Debug Unit Table 24-1. Debug Unit Pin Description Pin Name Description Type DRXD Debug Receive Data Input DTXD Debug Transmit Data Output Debug Unit RS232 Drivers Programming Tool Trace Console Debug Console Boot Program Debug Monitor Trace Manager

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

24.4 Product Dependencies

24.4.1 I/O Lines

Depending on product integration, the Debug Unit pins may be multiplexed with PIO lines. In this case, the programmer must first configure the corresponding PIO Controller to enable I/O lines operations of the Debug Unit.

24.4.2 Power Management

Depending on product integration, the Debug Unit clock may be controllable through the Power Management Controller. In this case, the programmer must first configure the PMC to enable the Debug Unit clock. Usually, the peripheral identifier used for this purpose is 1.

24.4.3 Interrupt Source

Depending on product integration, the Debug Unit interrupt line is connected to one of the inter- rupt sources of the Advanced Interrupt Controller. Interrupt handling requires programming of the AIC before configuring the Debug Unit. Usually, the Debug Unit interrupt line connects to the interrupt source 1 of the AIC, which may be shared with the real-time clock, the system timer interrupt lines and other system peripheral interrupts, as shown in Figure 24-1 . This sharing requires the programmer to determine the source of the interrupt when the source 1 is triggered.

24.5 UART Operations

The Debug Unit operates as a UART, (asynchronous mode only) and supports only 8-bit charac- ter handling (with parity). It has no clock pin. The Debug Unit's UART is made up of a receiver and a transmitter that operate independently, and a common baud rate generator. Receiver timeout and transmitter time guard are not imple- mented. However, all the implemented features are compatible with those of a standard USART.

24.5.1 Baud Rate Generator

The baud rate generator provides the bit period clock named baud rate clock to both the receiver and the transmitter. The baud rate clock is the master clock divided by 16 times the value (CD) written in DBGU_BRGR (Baud Rate Generator Register). If DBGU_BRGR is set to 0, the baud rate clock is disabled and the Debug Unit's UART remains inactive. The maximum allowable baud rate is Master Clock divided by 16. The minimum allow able baud rate is Master Clock divided by (16 x 65536). Table 24-2. I/O Lines Instance Signal I/O Line Peripheral DBGU DRXD PA9 A DBGU DTXD PA10 A Baud Rate MCK

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Figure 24-3. Baud Rate Generator

24.5.2 Receiver

24.5.2.1 Receiver Rese t, Enable and Disable

After device reset, the Debug Unit receiver is disabled and must be enabled before being used. The receiver can be enabled by writing the control register DBGU_CR with the bit RXEN at 1. At this command, the receiver starts looking for a start bit. The programmer can disable the receiver by writ ing DBGU_CR with the bit RXDIS at 1. If the receiver is waiting for a start bit, it is immedi ately stopped. However, if the receiver has already detected a start bit and is receiving the data, it waits for the stop bit before actually stopping its operation. The programmer can also put the receiver in its reset state by writing DBGU_CR with the bit RSTRX at 1. In doing so, the receiver immediat ely stops its current operations and is disabled, whatever its current state. If RSTRX is applied when data is being processed, this data is lost.

24.5.2.2 Start Detection and Data Sampling

The Debug Unit only supports asynchronous operations, and this affects only its receiver. The Debug Unit receiver detects the start of a rece ived character by sampling the DRXD signal until it detects a valid start bit. A low level (space) on DRXD is interpreted as a valid start bit if it is detected for more than 7 cycles of the sampling clock, which is 16 times the baud rate. Hence, a space that is longer than 7/16 of the bit period is detected as a valid start bit. A space which is 7/16 of a bit period or shorter is ignored and the receiver continues to wait for a valid start bit. When a valid start bit has been detected, the receiver samples the DRXD at the theoretical mid- point of each bit. It is assumed that each bit last s 16 cycles of the sampling clock (1-bit period) so the bit sampling point is eight cycles (0.5-bit period) after the start of the bit. The first sampling point is therefore 24 cycles (1.5-bit periods) after the falling edge of the start bit was detected. Each subsequent bit is sampled 16 cycles (1-bit period) after the previous one. MCK 16-bit Counter Baud Rate Clock CD CD OUT Divide by 16 Receiver Sampling Clock

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Figure 24-4. Start Bit Detection Figure 24-5. Character Reception

24.5.2.3 Receiver Ready

When a complete character is received, it is transferred to the DBGU_RHR and the RXRDY sta- tus bit in DBGU_SR (Status Register) is set. The bit RXRDY is automatically cleared when the receive holding register DBGU_RHR is read. Figure 24-6. Receiver Ready

24.5.2.4 Receiver Overrun

If DBGU_RHR has not been read by the software (o r the Peripheral Data Controller or DMA Controller) since the last transfer, the RXRDY bit is still set and a new character is received, the OVRE status bit in DBGU_SR is set. OVRE is cleared when the software writes the control reg- ister DBGU_CR with the bit RSTSTA (Reset Status) at 1. Figure 24-7. Receiver Overrun

24.5.2.5 Parity Error

Each time a character is received, the receiver calculates the parity of the received data bits, in accordance with the field PAR in DBGU_MR. It then compares the result with the received parity Sampling Clock DRXD True Start Detection Baud Rate Clock D0 D1 D2 D3 D4 D5 D6 D7 DRXD True Start Detection Sampling Parity Bit Stop Bit Example: 8-bit, parity enabled 1 stop 1 bit period 0.5 bit period D0 D1 D2 D3 D4 D5 D6 D7 PS S D0 D1 D2 D3 D4 D5 D6 D7 PDRXD Read DBGU_RHR RXRDY D0 D1 D2 D3 D4 D5 D6 D7 PS S D0 D1 D2 D3 D4 D5 D6 D7 PDRXD RSTSTA RXRDY OVRE stop stop

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 bit. If different, the parity error bit PARE in DBGU_SR is set at the same time the RXRDY is set. The parity bit is cleared when the control register DBGU_CR is written with the bit RSTSTA (Reset Status) at 1. If a new character is received before the reset status command is written, the PARE bit remains at 1. Figure 24-8. Parity Error

24.5.2.6 Receiver Framing Error

When a start bit is detected, it generates a character reception when all the data bits have been sampled. The stop bit is also sampled and when it is detected at 0, the FRAME (Framing Error) bit in DBGU_SR is set at the same time the RXRDY bit is set. The bit FRAME remains high until the control register DBGU_CR is written with the bit RSTSTA at 1. Figure 24-9. Receiver Framing Error

24.5.3 Transmitter

24.5.3.1 Transmitter Reset, Enable and Disable

After device reset, the Debug Unit transmitter is disabled and it must be enabled before being used. The transmitter is enabled by writing the control register DBGU_CR with the bit TXEN at 1. From this command, the transmitter waits for a ch aracter to be written in the Transmit Holding Register DBGU_THR before actually starting the transmission. The programmer can disable the transmitter by writing DBGU_CR with the bit TXDIS at 1. If the transmitter is not operating, it is immediately stopped. However, if a character is being pro- cessed into the Shift Register and/or a character has been written in the Transmit Holding Register, the characters are completed before the transmitter is actually stopped. The programmer can also put the transmitter in its reset state by writing the DBGU_CR with the bit RSTTX at 1. This immediately stops the transmitter, whether or not it is processing characters.

24.5.3.2 Transmit Format

The Debug Unit transmitter drives the pin DTXD at the baud rate clock speed. The line is driven depending on the format defined in the Mode Register and the data stored in the Shift Register. One start bit at level 0, then the 8 data bits, from the lowest to the highest bit, one optional parity bit and one stop bit at 1 are consecutively shifte d out as shown on the following figure. The field stopD0 D1 D2 D3 D4 D5 D6 D7 PSDRXD RSTSTA RXRDY PARE Wrong Parity Bit D0 D1 D2 D3 D4 D5 D6 D7 PSDRXD RSTSTA RXRDY FRAME Stop Bit Detected at 0 stop

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 PARE in the mode register DBGU_MR defines whether or not a parity bit is shifted out. When a parity bit is enabled, it can be selected between an odd parity, an even parity, or a fixed space or mark bit. Figure 24-10. Character Transmission

24.5.3.3 Transmitter Control

When the transmitter is enabled, the bit TXRDY (Transmitter Ready) is set in the status register DBGU_SR. The transmission starts when the programmer writes in the Transmit Holding Regis- ter DBGU_THR, and after the written character is transferred from DBGU_THR to the Shift Register. The bit TXRDY remains high until a second character is written in DBGU_THR. As soon as the first character is completed, the last character written in DBGU_THR is transferred into the shift register and TXRDY rises again, showing that the holding register is empty. When both the Shift Register and the DBGU_THR are empty, i.e., all the characters written in DBGU_THR have been processed, the bit TXEMPTY rises after the last stop bit has been completed. Figure 24-11. Transmitter Control

24.5.4 DMA Support

Both the receiver and the transmitter of the Debug Unit’s UART are connected to a DMA Con- troller (DMAC) channel. The DMA Controller channels are programmed via registers that are mapped within the DMAC user interface. D0 D1 D2 D3 D4 D5 D6 D7 DTXD Start Bit Parity Bit Stop Bit Example: Parity enabled Baud Rate Clock DBGU_THR Shift Register DTXD TXRDY TXEMPTY Data 0 Data 1 Data 0 Data 0 Data 1 Data 1S S PP Write Data 0 in DBGU_THR Write Data 1 in DBGU_THR stopstop

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

24.5.5 Test Modes

The Debug Unit supports three tests modes. These modes of operation are programmed by using the field CHMODE (Channel Mode) in the mode register DBGU_MR. The Automatic Echo mode allows bit-by-bit retransmission. When a bit is received on the DRXD line, it is sent to the DTXD line. The transm itter operates normally, but has no effect on the DTXD line. The Local Loopback mode allows the transmitted characters to be received. DTXD and DRXD pins are not used and the output of the transmitter is internally connected to the input of the receiver. The DRXD pin level has no effect and the DTXD line is held high, as in idle state. The Remote Loopback mode directly connects the DRXD pin to the DTXD line. The transmitter and the receiver are disabled and have no effect. This mode allows a bit-by-bit retransmission. Figure 24-12. Test Modes

24.5.6 Debug Communication Channel Support

The Debug Unit handles the signals COMMRX and COMMTX that come from the Debug Com- munication Channel of the ARM Processor and are driven by the In-circuit Emulator. The Debug Communication Channel contains two registers that are accessible through the ICE Breaker on the JTAG side and through the coprocessor 0 on the ARM Processor side. As a reminder, the following instructions ar e used to read and write the Debug Communication Channel: Receiver Transmitter Disabled RXD TXD Receiver Transmitter Disabled RXD TXD VDD Disabled Receiver Transmitter Disabled RXD TXD Disabled Automatic Echo Local Loopback Remote Loopback VDD

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 MRC p14, 0, Rd, c1, c0, 0 Returns the debug communication data read register into Rd MCR p14, 0, Rd, c1, c0, 0 Writes the value in Rd to the debug communication data write register. The bits COMMRX and COMMTX, which indicate, respectively, that the read register has been written by the debugger but not yet read by the processor, and that the write register has been written by the processor and not yet read by the debugger, are wired on the two highest bits of the status register DBGU_SR. These bits can generate an interrupt. This feature permits han- dling under interrupt a debug link between a debug monitor running on the target system and a debugger.

24.5.7 Chip Identifier

The Debug Unit features two chip identifier registers, DBGU_CIDR (Chip ID Register) and DBGU_EXID (Extension ID). Both registers contain a hard-wired value that is read-only. The first register contains the following fields:

  • EXT - shows the use of the extension identifier register
  • NVPTYP and NVPSIZ - identifies the type of embedded non-volatile memory and its size
  • ARCH - identifies the set of embedded peripherals
  • SRAMSIZ - indicates the size of the embedded SRAM
  • EPROC - indicates the embedded ARM processor
  • VERSION - gives the revision of the silicon The second register is device-dependent and reads 0 if the bit EXT is 0.

24.5.8 ICE Access Prevention

The Debug Unit allows blockage of access to the system through the ARM processor's ICE interface. This feature is implemented via th e register Force NTRST (DBGU_FNR), that allows assertion of the NTRST signal of the ICE Interface. Writing the bit FNTRST (Force NTRST) to 1 in this register prevents any activity on the TAP controller. On standard devices, the bit FNTRST resets to 0 and thus does not prevent ICE access. This feature is especially useful on custom ROM devices for customers who do not want their on-chip code to be visible.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

24.6 Debug Unit (DBGU) User Interface

Table 24-3. Register Mapping Offset Register Name Access Reset 0x0000 Control Register DBGU_CR Write-only – 0x0004 Mode Register DBGU_MR Read-write 0x0 0x0008 Interrupt Enable Register DBGU_IER Write-only – 0x000C Interrupt Disable Register DBGU_IDR Write-only – 0x0010 Interrupt Mask Register DBGU_IMR Read-only 0x0 0x0014 Status Register DBGU_SR Read-only – 0x0018 Receive Holding Register DBGU_RHR Read-only 0x0 0x001C Transmit Holding Register DBGU_THR Write-only – 0x0020 Baud Rate Generator Register DBGU_BRGR Read-write 0x0 0x0024 - 0x003C Reserved – – – 0x0040 Chip ID Register DBGU_CIDR Read-only – 0x0044 Chip ID Extension Register DBGU_EXID Read-only – 0x0048 Force NTRST Register DBGU_FNR Read-write 0x0 0x004C - 0x00FC Reserved – – –

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

24.6.1 Debug Unit Control Register

Name: DBGU_CR Address: 0xFFFFF200 Access: Write-only  RSTRX: Reset Receiver 0 = No effect. 1 = The receiver logic is reset and disabled. If a character is being received, the reception is aborted.  RSTTX: Reset Transmitter 0 = No effect. 1 = The transmitter logic is reset and disabled. If a character is being transmitted, the transmission is aborted.  RXEN: Receiver Enable 0 = No effect. 1 = The receiver is enabled if RXDIS is 0.  RXDIS: Receiver Disable 0 = No effect. 1 = The receiver is disabled. If a character is being processed and RSTRX is not set, the character is completed before the receiver is stopped.  TXEN: Transmitter Enable 0 = No effect. 1 = The transmitter is enabled if TXDIS is 0.  TXDIS: Transmitter Disable 0 = No effect. 1 = The transmitter is disabled. If a character is bei ng processed and a character has been written the DBGU_THR and RSTTX is not set, both characters are completed before the transmitter is stopped.  RSTSTA: Reset Status Bits 0 = No effect. 1 = Resets the status bits PARE, FRAME and OVRE in the DBGU_SR. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 TXDIS TXEN RXDIS RXEN RSTTX RSTRX ––

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

24.6.2 Debug Unit Mode Register

Name: DBGU_MR Address: 0xFFFFF204 Access: Read-write  PAR: Parity Type  CHMODE: Channel Mode 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 CHMODE –– PAR – 76543210 Value Name Description 0b000 EVEN Even Parity 0b001 ODD Odd Parity 0b010 SPACE Space: Parity forced to 0 0b011 MARK Mark: Parity forced to 1 0b1xx NONE No Parity Value Name Description 0b00 NORM Normal Mode 0b01 AUTO Automatic Echo 0b10 LOCLOOP Local Loopback 0b11 REMLOOP Remote Loopback

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

24.6.3 Debug Unit Interrupt Enable Register

Name: DBGU_IER Address: 0xFFFFF208 Access: Write-only  RXRDY: Enable RXRDY Interrupt  TXRDY: Enable TXRDY Interrupt  OVRE: Enable Overrun Error Interrupt  FRAME: Enable Framing Error Interrupt  PARE: Enable Parity Error Interrupt  TXEMPTY: Enable TXEMPTY Interrupt  COMMTX: Enable COMMTX (from ARM) Interrupt  COMMRX: Enable COMMRX (from ARM) Interrupt 0 = No effect. 1 = Enables the corresponding interrupt. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 PARE FRAME OVRE –– – TXRDY RXRDY

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

24.6.4 Debug Unit Interrupt Disable Register

Name: DBGU_IDR Address: 0xFFFFF20C Access: Write-only  RXRDY: Disable RXRDY Interrupt  TXRDY: Disable TXRDY Interrupt  OVRE: Disable Overrun Error Interrupt  FRAME: Disable Framing Error Interrupt  PARE: Disable Parity Error Interrupt  TXEMPTY: Disable TXEMPTY Interrupt  COMMTX: Disable COMMTX (from ARM) Interrupt  COMMRX: Disable COMMRX (from ARM) Interrupt 0 = No effect. 1 = Disables the corresponding interrupt. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 PARE FRAME OVRE –– – TXRDY RXRDY

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

24.6.5 Debug Unit Interrupt Mask Register

Name: DBGU_IMR Address: 0xFFFFF210 Access: Read-only  RXRDY: Mask RXRDY Interrupt  TXRDY: Disable TXRDY Interrupt  OVRE: Mask Overrun Error Interrupt  FRAME: Mask Framing Error Interrupt  PARE: Mask Parity Error Interrupt  TXEMPTY: Mask TXEMPTY Interrupt  COMMTX: Mask COMMTX Interrupt  COMMRX: Mask COMMRX Interrupt 0 = The corresponding interrupt is disabled. 1 = The corresponding interrupt is enabled. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 PARE FRAME OVRE –– – TXRDY RXRDY

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

24.6.6 Debug Unit Status Register

Name: DBGU_SR Address: 0xFFFFF214 Access: Read-only  RXRDY: Receiver Ready 0 = No character has been received since the last read of the DBGU_RHR or the receiver is disabled. 1 = At least one complete character has been received, transferred to DBGU_RHR and not yet read.  TXRDY: Transmitter Ready 0 = A character has been written to DBGU_THR and not yet transferred to the Shift Register, or the transmitter is disabled. 1 = There is no character written to DBGU_THR not yet transferred to the Shift Register.  OVRE: Overrun Error 0 = No overrun error has occurred since the last RSTSTA. 1 = At least one overrun error has occurred since the last RSTSTA.  FRAME: Framing Error 0 = No framing error has occurred since the last RSTSTA. 1 = At least one framing error has occurred since the last RSTSTA.  PARE: Parity Error 0 = No parity error has occurred since the last RSTSTA. 1 = At least one parity error has occurred since the last RSTSTA.  TXEMPTY: Transmitter Empty 0 = There are characters in DBGU_THR, or characters being processed by the transmitter, or the transmitter is disabled. 1 = There are no characters in DBGU_THR and there are no characters being processed by the transmitter.  COMMTX: Debug Communication Channel Write Status 0 = COMMTX from the ARM processor is inactive. 1 = COMMTX from the ARM processor is active.  COMMRX: Debug Communication Channel Read Status 0 = COMMRX from the ARM processor is inactive. 1 = COMMRX from the ARM processor is active. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 PARE FRAME OVRE –– – TXRDY RXRDY

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

24.6.7 Debug Unit Receiver Holding Register

Name: DBGU_RHR Address: 0xFFFFF218 Access: Read-only  RXCHR: Received Character Last received character if RXRDY is set. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 RXCHR

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

24.6.8 Debug Unit Transmit Holding Register

Name: DBGU_THR Address: 0xFFFFF21C Access: Write-only  TXCHR: Character to be Transmitted Next character to be transmitted after the current character if TXRDY is not set. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 TXCHR

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

24.6.9 Debug Unit Baud Ra te Generator Register

Name: DBGU_BRGR Address: 0xFFFFF220 Access: Read-write  CD: Clock Divisor 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 CD 76543210 CD Value Name Description

0 DISABLED DBGU Disabled

2 to 65535 – MCK / (CD x 16)

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

24.6.10 Debug Unit Chip ID Register

Name: DBGU_CIDR Address: 0xFFFFF240 Access: Read-only  VERSION: Version of the Device Values depend upon the version of the device.  EPROC: Embedded Processor  NVPSIZ: Nonvolatile Program Memory Size 31 30 29 28 27 26 25 24 EXT NVPTYP ARCH 23 22 21 20 19 18 17 16 ARCH SRAMSIZ 15 14 13 12 11 10 9 8 NVPSIZ2 NVPSIZ 76543210 EPROC VERSION Value Name Description

1 ARM946ES ARM946ES

2 ARM7TDMI ARM7TDMI

3 CM3 Cortex-M3

4 ARM920T ARM920T

5 ARM926EJS ARM926EJS

18 K 8 K bytes

4– Reserved 5 64K 64K bytes 6– Reserved 7 128K 128K bytes 8– Reserved 9 256K 256K bytes 10 512K 512K bytes 11 – Reserved 12 1024K 1024K bytes

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12  NVPSIZ2 Second Nonvolatile Program Memory Size  SRAMSIZ: Internal SRAM Size 13 – Reserved 14 2048K 2048K bytes 15 – Reserved Value Name Description 0N ONE N one 4– Reserved 5 64K 64K bytes 6R eserved 7 128K 128K bytes 8– Reserved 9 256K 256K bytes 10 512K 512K bytes 11 – Reserved 12 1024K 1024K bytes 13 – Reserved 14 2048K 2048K bytes 15 – Reserved Value Name Description 0– Reserved

11 K 1 K bytes

22 K 2 K bytes

36 K 6 K bytes

54 K 4 K bytes

88 K 8 K bytes

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12  ARCH: Architecture Identifier 13 256K 256K bytes 14 96K 96K bytes 15 512K 512K bytes Value Name Description 0x19 AT91SAM9xx AT91SAM9xx Series 0x29 AT91SAM9XExx AT91SAM9XExx Series 0x34 AT91x34 AT91x34 Series 0x37 CAP7 CAP7 Series 0x39 CAP9 CAP9 Series 0x3B CAP11 CAP11 Series 0x40 AT91x40 AT91x40 Series 0x42 AT91x42 AT91x42 Series 0x55 AT91x55 AT91x55 Series 0x60 AT91SAM7Axx AT91SAM7Axx Series 0x61 AT91SAM7AQxx AT91SAM7AQxx Series 0x63 AT91x63 AT91x63 Series 0x70 AT91SAM7Sxx AT91SAM7Sxx Series 0x71 AT91SAM7XCxx AT91SAM7XCxx Series 0x72 AT91SAM7SExx AT91SAM7SExx Series 0x73 AT91SAM7Lxx AT91SAM7Lxx Series 0x75 AT91SAM7Xxx AT91SAM7Xxx Series 0x76 AT91SAM7SLxx AT91SAM7SLxx Series 0x80 ATSAM3UxC ATSAM3UxC Series (100-pin version) 0x81 ATSAM3UxE ATSAM3UxE Series (144-pin version) 0x83 ATSAM3AxC ATSAM3AxC Series (100-pin version) 0x84 ATSAM3XxC ATSAM3XxC Series (100-pin version) 0x85 ATSAM3XxE ATSAM3XxE Series (144-pin version) 0x86 ATSAM3XxG ATSAM3XxG Series (208/217-pin version) 0x88 ATSAM3SxA ATSAM3SxA Series (48-pin version) 0x89 ATSAM3SxB ATSAM3SxB Series (64-pin version) 0x8A ATSAM3SxC ATSAM3SxC Series (100-pin version) 0x92 AT91x92 AT91x92 Series 0x93 ATSAM3NxA ATSAM3NxA Series (48-pin version) 0x94 ATSAM3NxB ATSAM3NxB Series (64-pin version) 0x95 ATSAM3NxC ATSAM3NxC Series (100-pin version) 0x98 ATSAM3SDxA ATSAM3SDxA Series (48-pin version) Value Name Description

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12  NVPTYP: Nonvolatile Program Memory Type  EXT: Extension Flag 0 = Chip ID has a single register definition without extension 1 = An extended Chip ID exists. 0x99 ATSAM3SDxB ATSAM3SDxB Series (64-pin version) 0x9A ATSAM3SDxC ATSAM3SDxC Series (100-pin version) 0xA5 – Reserved 0xF0 AT75Cxx AT75Cxx Series Value Name Description 0R O M R O M

1 ROMLESS ROMless or on-chip Flash

4 SRAM SRAM emulating ROM

2 FLASH Embedded Flash Memory

3 ROM_FLASH

ROM and Embedded Flash Memory NVPSIZ is ROM size NVPSIZ2 is Flash size Value Name Description

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

24.6.11 Debug Unit Chip ID Extension Register

Name: DBGU_EXID Address: 0xFFFFF244 Access: Read-only  EXID: Chip ID Extension Reads 0 if the bit EXT in DBGU_CIDR is 0. 31 30 29 28 27 26 25 24 EXID 23 22 21 20 19 18 17 16 EXID 15 14 13 12 11 10 9 8 EXID 76543210 EXID

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

24.6.12 Debug Unit Force NTRST Register

Name: DBGU_FNR Address: 0xFFFFF248 Access: Read-write  FNTRST: Force NTRST 0 = NTRST of the ARM processor’s TAP controller is driven by the power_on_reset signal. 1 = NTRST of the ARM processor’s TAP controller is held low. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7654321 0

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 295 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 25. UMC Fuse Controller

25.1 Description

The Fuse Controller supports software fuse programming through a 32-bit register, only fuses set to level “1” are programmed. It reads the fuse states on startup and stores them into 32-bit registers. The first 8 Fuse Status registers (FUSE_SRx) can be masked and will read as a value of “0” regardless of the fuse state when masked.

25.2 Embedded Characteristics

  • Software Fuse Programming
  • User Write Access for Fuse
  • Part of Fuse can be Masked After Read

25.3 Block Diagram

Figure 25-1. Fuse Controller Block Diagram Fuse Cells Fuse Controller Fuse States Fuse States Controls Controls

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 296 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

25.4 Functional Description

25.4.1 Fuse Reading

The fuse states are automatically read on CORE startup and are available for reading in the 10 Fuse Status (FUSE_SRx) registers. The fuse states of bits 31 to 0 will be available at FUSE_SR0, the fuse states of bits 63 to 32 will be available at FUSE_SR1 and so on. FUSE_SRx registers can be updated manually by using the RRQ bit of the Fuse Control register (FUSE_CR). RS and WS bits of the Fuse Index register (FUSE_IR) must be at level one before issuing the read request. Figure 25-2. Fuse Read

25.4.2 Fuse Programming

All the fuses can be written by software. To program fuses, strictly follow the order of the sequence instructions as provided below: 1. Select the word to write, using the SELW field of the Fuse_Index register (FUSE_IR). 2. Write the word to program in the Fuse_Data register (FUSE_DR). 3. Check that RS and WS bits of the Fuse_Index register are at level one (no read and no write pending). 4. Write the WRQ bit of the Fuse_Control register (FUSE_CR) to begin the fuse program- ming. The KEY field must be written at the same time with a value 0xFB to make the write request valid. Writing the WRQ bit will clear the WS bit. 5. Check the WS bit of FUSE_SRx, when WS has a value of “1” the fuse write process is over. Only fuses to be set to level “1” are written. outdated Clock FUSE_SRx RRQ WS RS up to date

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 297 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Figure 25-3. Fuse Write

25.4.3 Fuse Masking

It is possible to mask the first 8 FUSE_SRx register s so that they will be read at a value of “0”, regardless of the fuse state. To activate fuse masking on the first 8 FUSE_SRx registers, the MSK bit of the Fuse Mode reg- ister (FUSE_MR) must be written to level “1”. Th e MSK bit is write-only. Solely a general reset can disable fuse masking. 00XX XX Fuse[31:0] Fuse[63:32] Clock WSEL DATA WRQ WS RS

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 298 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

25.5 Fuse Controller (FUSE) User Interface

Table 25-1. Register Mapping Offset Register Name Access Reset 0x00 Fuse Control Register FUSE_CR Read-write – 0x04 Fuse Mode Register FUSE_MR Write-only – 0x08 Fuse Index Register FUSE_IR Read-write 0x00000000 0x0C Fuse Data Register FUSE_DR Read-write – 0x10 Fuse Status Register 0 FUSE_SR0 Read-only 0x00000000 0x14 Fuse Status Register 1 FUSE_SR1 Read-only 0x00000000 0x34 Fuse Status Register 9 FUSE_SR9 Read-only 0x00000000 0x38 - 0xDC Reserved – – – 0xE0 - 0xFC Reserved – – –

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 299 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

25.5.1 Fuse Control Register

Name: FUSE_CR Address: 0xFFFFDC00 Access: Read-write  WRQ: Write Request 0 = No effect. 1 = Request the word DATA to be programmed, ignored if KEY field is not filled with 0xFB.  RRQ: Read Request 0 = No effect. 1 = Request the fuses to be read and FUSE_SRx registers are updated, ignored if KEY field is not filled with 0xFB.  KEY: Key code This KEY code is needed to set the WRQ bit. 0xFB (VALID): valid key. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 KEY 76543210

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 300 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

25.5.2 Fuse Mode Register

Name: FUSE_MR Address: 0xFFFFDC04 Access: Write-only  MSK: Mask Fuse Status Registers 0 = No effect. 1 = Mask the first 8 FUSE_SRx registers. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 301 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

25.5.3 Fuse Index Register

Name: FUSE_IR Address: 0xFFFFDC08 Access: Read-write  WS: Write Status 0 = Write is pending or no write has been requested since general reset. 1 = Write of fuses is done.  RS: Read Status 0 = Read is pending or no read has been requested since general reset. 1 = Read of fuses is done.  WSEL: Word Selection 0-15 = Select the word to write. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 –––– WSEL 76543210

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 302 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

25.5.4 Fuse Data Register

Name: FUSE_DR Address: 0xFFFFDC0C Access: Read-write  DATA: Data to Program Data to program. Only bits of with a value of “1” will be programmed. 31 30 29 28 27 26 25 24 DATA 23 22 21 20 19 18 17 16 DATA 15 14 13 12 11 10 9 8 DATA 76543210 DATA

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 303 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

25.5.5 Fuse Status Register

Name: FUSE_SRx [x=0..9] Address: 0xFFFFDC10 Access: Read-only  FUSE: Fuse Status Indicates the status of corresponding fuses: 0 = unprogrammed. 1 = programmed. 31 30 29 28 27 26 25 24 FUSE 23 22 21 20 19 18 17 16 FUSE 15 14 13 12 11 10 9 8 FUSE 76543210 FUSE

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 304 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 26. Bus Matrix (MATRIX)

26.1 Description

The Bus Matrix implements a multi-layer AHB, based on the AHB-Lite protocol, that enables par- allel access paths between multiple AHB master s and slaves in a system, thus increasing the overall bandwidth. The Bus Matrix interconnects up to 16 AHB masters to up to 16 AHB slaves. The normal latency to connect a master to a slave is one cycle except for the default master of the accessed slave which is connected directly (zero cycle latency). The Bus Matrix user interface is compliant with ARM Advanced Peripheral Bus and provides a Chip Configuration User Interface with Registers that allow the Bus Matrix to support application specific features.

26.2 Embedded Characteristics

  • 6-layer Matrix, handling requests from 6 masters
  • Programmable Arbitration strategy – Fixed-priority Arbitration – Round-Robin Arbitration, either with no default master, last accessed default master or fixed default master
  • Burst Management – Breaking with Slot Cycle Limit Support – Undefined Burst Length Support
  • One Address Decoder provided per Master – Three different slaves may be assigned to each decoded memory area: one for internal ROM boot, one after remap
  • Boot Mode Select – Non-volatile Boot Memory can be internal ROM or external memory on EBI_NCS0
  • Remap Command – Allows Remapping of an Internal SRAM in Place of the Boot Non-Volatile Memory (ROM or External Flash) – Allows Handling of Dynamic Exception Vectors

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

26.3 Matrix Masters

The Bus Matrix of the AT91SAM9CN12 product manages 6 masters, which means that each master can perform an access concurrently with others, to an available slave. Each master has its own decoder, which is defined specifically for each master. In order to sim- plify the addressing, all the masters have the same decodings.

26.4 Matrix Slaves

The Bus Matrix of the AT91SAM9CN12 product manages 5 slaves. Each slave has its own arbi- ter, allowing a different arbitration per slave.

26.5 Master to Slave Access

All the Masters can normally access all the Slaves. However, some paths do not make sense, for example allowing access from the USB Device High speed DMA to the Internal Peripherals. Thus, these paths are forbidden or simply not wired, and shown as “-” in the following table. Table 26-1. List of Bus Matrix Masters Master 0 ARM926 Instruction Master 1 ARM926 Data Master 2&3 DMA Controller Master 4 USB Host DMA Master 5 LCD DMA Table 26-2. List of Bus Matrix Slaves Slave 0 Internal SRAM Slave 1 Internal ROM USB Host User Interface Slave 2 External Bus Interface Slave 3 Peripheral Bridge 0 Slave 4 Peripheral Bridge 1 Table 26-3. AT91SAM9CN12 Master to Slave Access Masters 0 1 2&3 4 5 Slaves ARM926 Instruction ARM926 Data DMA USB Host DMA LCD DMA

0 Internal SRAM X X X X X

1 Internal ROM

USB Host User Interface XX X - -

2 External Bus Interface X X X X X

3 Peripheral Bridge 0 X X X - -

4 Peripheral Bridge 1 X X X - -

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

26.6 Memory Mapping

The Bus Matrix provides one decoder for every AHB master interface. The decoder offers each AHB master several memory mappings. In fact, depending on the product, each memory area may be assigned to several slaves. Booting at the same address while using different AHB slaves (i.e. external RAM, internal ROM or internal Flash, etc.) becomes possible. The Bus Matrix user interface provides Mast er Remap Control Register (MATRIX_MRCR) that performs remap action for every master independently.

26.7 Special Bus Granting Mechanism

The Bus Matrix provides some speculative bus granting techniques in order to anticipate access requests from some masters. This mechanism reduces latency at first access of a burst or single transfer as long as the slave is free from any other master access, but does not provide any ben- efit as soon as the slave is continuously accessed by more than one master, since arbitration is pipelined and then has no negative effect on the slave bandwidth or access latency. This bus granting mechanism sets a different default master for every slave. At the end of the current access, if no other re quest is pending, the slave remains connected to its associated default master. A slave can be as sociated with three kinds of default masters: no default master, last access master and fixed default master. To change from one kind of default master to another, the Bus Matrix user interface provides the Slave Configuration Registers, one for each slave, that set a default master for each slave. The Slave Configuration Register contains two fields: DEFMSTR_TYPE and FIXED_DEFMSTR. The 2-bit DEFMSTR_TYPE field selects the default master type (no default, last access master, fixed default master), whereas the 4-bit FIXED_DEFMSTR field selects a fixed default master pro- vided that DEFMSTR_TYPE is set to fi xed default master. Please refer to Section 26.10.2 “Bus Matrix Slave Configuration Registers” on page 314.

26.7.1 No Default Master

After the end of the current access, if no other request is pending, the slave is disconnected from all masters. No Default Master suits low-power mode. This configuration incurs one latency clock cycle for the first access of a burst after bus Idle. Arbitration without default master may be used for masters that perform significant bursts or sev- eral transfers with no Idle in between, or if the slave bus bandwidth is widely used by one or more masters. This configuration provides no benefit on access latency or bandwidth when reaching maximum slave bus throughput whatever is the number of requesting masters.

26.7.2 Last Access Master

After the end of the current access, if no other request is pending, the slave remains connected to the last master that performed an access request. This allows the Bus Matrix to remove the one latency cycle for the last master that accessed the slave. Other non privileged masters still get one lat ency clock cycle if they want to access the same slave. This technique is useful for masters that mainly perform single accesses or short bursts with some Idle cycles in between. This configuration provides no benefit on access latency or bandwidth when reaching maximum slave bus throughput whatever is the number of requesting masters.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

26.7.3 Fixed Default Master

After the end of the current access, if no other request is pending, the slave connects to its fixed default master. Unlike last access master, the fixed master does not change unless the user modifies it by a software action (field FIXED_DEFMSTR of the related MATRIX_SCFG). This allows the Bus Matrix arbiters to remove the one latency clock cycle for the fixed default master of the slave. Every request attempted by this fixed default master will not cause any arbi- tration latency whereas other non privileged masters will still get one latency cycle. This technique is useful for a master that mainly perform single accesses or short bursts with some Idle cycles in between. This configuration provides no benefit on access latency or bandwidth when reaching maximum slave bus throughput whatever is the number of requesting masters.

26.8 Arbitration

The Bus Matrix provides an arbitration mechanism that reduces latency when conflict cases occur, i.e. when two or more masters try to access the same slave at the same time. One arbiter per AHB slave is provided, thus arbitrating each slave differently. The Bus Matrix provides the user with t he possibility of choosing between 2 arbitration types or mixing them for each slave: 1. Round-Robin Arbitration (default) 2. Fixed Priority Arbitration The resulting algorithm may be complemented by selecting a default master configuration for each slave. When a re-arbitration must be done, specific conditions apply. See Section 26.8.1 “Arbitration Scheduling” on page 308.

26.8.1 Arbitration Scheduling

Each arbiter has the ability to arbitrate between two or more different master requests. In order to avoid burst breaking and also to provide the maximum throughput for slave interfaces, arbitra- tion may only take place during the following cycles: 1. Idle Cycles: When a slave is not connected to any master or is connected to a master which is not currently accessing it. 2. Single Cycles: When a slave is currently doing a single access. 3. End of Burst Cycles: When the current cycle is the last cycle of a burst transfer. For defined length burst, predicted end of burst matches the size of the transfer but is man- aged differently for undefined length burst. See “Undefined Length Burst Arbitration” on page 308 4. Slot Cycle Limit: When the slot cycle counte r has reached the limit value indicating that the current master access is too long and must be broken. See “Slot Cycle Limit Arbi- tration” on page 309

26.8.1.1 Undefined Length Burst Arbitration

In order to optimize AHB burst lengths and arbitration, it may be interesting to set a maximum for undefined length bursts (INCR). The Bus Matrix prov ides specific logic in order to re-arbitrate before the end of the INCR transfer. A predicted end of burst is used as a defined length burst transfer and can be selected from among the following Undefined Length Burst Type (ULBT) possibilities:

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 1. Unlimited: No predicted end of burst is generated and therefore INCR burst transfer will not be broken by this way, but will be able to complete unless broken at the Slot Cycle Limit. This is normally the default and should be let as is in order to be able to allow full

1 Kilobyte AHB intra-boundary 256-beat word bursts performed by some ATMEL AHB

masters. 2. 1-beat bursts: Predicted end of burst is generated at each single transfer inside the INCR transfer. 3. 4-beat bursts: Predicted end of burst is generated at the end of each 4-beat boundary inside INCR transfer. 4. 8-beat bursts: Predicted end of burst is generated at the end of each 8-beat boundary inside INCR transfer. 5. 16-beat bursts: Predicted end of burst is generated at the end of each 16-beat bound- ary inside INCR transfer. 6. 32-beat bursts: Predicted end of burst is generated at the end of each 32-beat bound- ary inside INCR transfer. 7. 64-beat bursts: Predicted end of burst is generated at the end of each 64-beat bound- ary inside INCR transfer. 8. 128-beat bursts: Predicted end of burst is generated at the end of each 128-beat boundary inside INCR transfer. Use of undefined length 16-beat bursts or less is discouraged since this generally decreases significantly overall bus bandwidth due to arbitration and slave latencies at each first access of a burst. If the master does not permanently and continuous ly request the same slave or has an intrinsi- cally limited average throughput, the ULBT should be let at its default unlimited value, knowing that the AHB specification natively limits all word bursts to 256 beats and double-word bursts to 128 beats because of its 1 Kilobyte address boundaries. Unless duly needed the ULBT should be let to its default 0 value for power saving. This selection can be done through the field ULBT of the Master Configuration Registers (MATRIX_MCFG).

26.8.1.2 Slot Cycle Limit Arbitration

The Bus Matrix contains specific logic to break long accesses, such as back to back undefined length bursts or very long bursts on a very sl ow slave (e.g., an external low speed memory). At each arbitration time a counter is loaded with t he value previously written in the SLOT_CYCLE field of the related Slave Configuration Regist er (MATRIX_SCFG) and decreased at each clock cycle. When the counter elapses, the arbiter has the ability to re-arbitrate at the end of the cur- rent AHB bus access cycle. Unless some master has a very tight access latency constraint which could lead to data overflow or underflow due to a badly undersized internal fifo with respect to its throughput, the Slot Cycle Limit should be disabled (SLOT_CYCLE = 0) or let to its default maximum value in order not to inefficiently break long bursts performed by some ATMEL masters. However, the Slot Cycle Limit should not be disabled in the very particular case of a master capable of accessing the slave by performing ba ck to back undefined length bursts shorter than the number of ULBT beats with no Idle cycle in between, since in this case the arbitration could be frozen all along the bursts sequence.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 In most cases this feature is not needed and should be disabled for power saving. Warning: This feature cannot prevent any slave from locking its access indefinitely.

26.8.2 Arbitration Priority Scheme

The bus Matrix arbitration scheme is organized in priority pools. Round-Robin priority is used inside the highest and lowest priority pools, whereas fix level prior- ity is used between priority pools and inside the intermediate priority pools. For each slave, each master x is assigned to one of the slave priority pools through the Priority Registers for Slaves (MxPR fields of MATRIX_PRAS and MATRIX_PRBS). When evaluating masters requests, this programmed priority level always takes precedence. After reset, all the masters are belonging to the lowest priority pool (MxPR = 0) and so are granted bus access in a true Round-Robin fashion. The highest priority pool must be specifically reserved for masters requiring very low access latency. If more than one master belong to this pool, these will be granted bus access in a biased Round-Robin fashion which allow tight and deterministic maximum access latency from AHB bus request. In fact, at worst, any currently high priority master request will be granted after the current bus master access is ended and the other high priority pool masters, if any, have been granted once each. The lowest priority pool shares the remaining bus bandwidth between AHB Masters. Intermediate priority pools allow fine priority tuning. Typically, a moderately latency critical mas- ter or a bandwidth only critical master will use such a priority level. The higher the priority level (MxPR value), the higher the master priority. All combination of MxPR values are allowed for all masters and slaves. For example some mas- ters might be assigned to the highest priority pool (round-robin) and the remaining masters to the lowest priority pool (round-robin), with no master for intermediate fix priority levels. If more than one master is requesting the slave bus, whatever are the respective masters priori- ties, no master will be granted the slave bus for two consecutiv e runs. A master can only get back to back grants as long as it is the only requesting master.

26.8.2.1 Fixed Priority Arbitration

This arbitration algorithm is the first and only applied between masters from distinct priority pools. It is also used inside priority pools other than the highest and lowest ones (intermediate priority pools). It allows the Bus Matrix arbiters to dispatch the requests from different masters to the same slave by using the fixed priority defined by the user in the MxPR field for each master inside the MATRIX_PRAS and MATRIX_PRBS Priority Registers. If two or more master requests are active at the same time, the master with the highest priority number MxPR is serviced first. Inside intermediate priority pools, if two or more master requests with the same priority are active at the same time, the master with the highest number is serviced first.

26.8.2.2 Round-Robin Arbitration

This algorithm is only used inside the highest and lo west priority pools. It allows the Bus Matrix arbiters to dispatch the requests from different masters to the same slave in a fair way. If two or more master requests are active at the same time inside the priority pool, they are serviced in a round-robin increasing master number order.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

26.9 Write Protect Registers

To prevent any single software error that may corrupt MATRIX behavior, the entire MATRIX address space from address offset 0x000 to 0x1FC can be write-protected by setting the WPEN bit in the MATRIX Write Protect Mode Register (MATRIX_WPMR). If a write access to anywhere in the MATRIX address space from address offset 0x000 to 0x1FC is detected, then the WPVS flag in the MATRIX Write Protect Status Register (MATRIX_WPSR) is set and the field WPVSRC indicates in which register the write access has been attempted. The WPVS flag is reset by writing the MATRIX Write Protect Mode Register (MATRIX_WPMR) with the appropriate access key WPKEY.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

26.10 Bus Matrix (MATRIX) User Interface

Table 26-4. Register Mapping Offset Register Name Access Reset 0x0000 Master Configuration Register 0 MATRIX_MCFG0 Read-write 0x00000001 0x0004 Master Configuration Register 1 MATRIX_MCFG1 Read-write 0x00000000 0x0008 Master Configuration Register 2 MATRIX_MCFG2 Read-write 0x00000000 0x000C Master Configuration Register 3 MATRIX_MCFG3 Read-write 0x00000000 0x0010 Master Configuration Register 4 MATRIX_MCFG4 Read-write 0x00000000 0x0014 Master Configuration Register 5 MATRIX_MCFG5 Read-write 0x00000000 0x0018 - 0x003C Reserved – – – 0x0040 Slave Configuration Register 0 MATRIX_SCFG0 Read-write 0x000001FF 0x0044 Slave Configuration Register 1 MATRIX_SCFG1 Read-write 0x000001FF 0x0048 Slave Configuration Register 2 MATRIX_SCFG2 Read-write 0x000001FF 0x004C Slave Configuration Register 3 MATRIX_SCFG3 Read-write 0x000001FF 0x0050 Slave Configuration Register 4 MATRIX_SCFG4 Read-write 0x000001FF 0x0054 - 0x007C Reserved – – – 0x0080 Priority Register A for Slave 0 MATRIX_PRAS0 Read-write 0x00000000 0x0084 Reserved – – – 0x0088 Priority Register A for Slave 1 MATRIX_PRAS1 Read-write 0x00000000 0x008C Reserved – – – 0x0090 Priority Register A for Slave 2 MATRIX_PRAS2 Read-write 0x00000000 0x0094 Reserved – – – 0x0098 Priority Register A for Slave 3 MATRIX_PRAS3 Read-write 0x00000000 0x009C Reserved – – – 0x00A0 Priority Register A for Slave 4 MATRIX_PRAS4 Read-write 0x00000000 0x00A4 - 0x00FC Reserved – – – 0x0100 Master Remap Control Register MATRIX_MRCR Read-write 0x00000000 0x0104 - 0x010C Reserved – – – 0x0110 - 0x01E0 Chip Configuration Registers – – – 0x01E4 Write Protect Mode Regist er MATRIX_WPMR Read-write 0x00000000 0x01E8 Write Protect Status Register MATRIX_WPSR Read-only 0x00000000

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

26.10.1 Bus Matrix Master Configuration Registers

Name: MATRIX_MCFG0...MATRIX_MCFG5 Address: 0xFFFFDE00 [0], 0xFFFFDE04 [1], 0xFFFFDE08 [2], 0xFFFFDE0C [3], 0xFFFFDE10 [4], 0xFFFFDE14 [5] Access: Read-write  ULBT: Undefined Length Burst Type 0: Unlimited Length Burst No predicted end of burst is generated and therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the lat- est, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts. 1: Single Access The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst. 2: 4-beat Burst The undefined length burst is split into 4-beat bursts, allowing re-arbitration at each 4-beat burst end. 3: 8-beat Burst The undefined length burst is split into 8-beat bursts, allowing re-arbitration at each 8-beat burst end. 4: 16-beat Burst The undefined length burst is split into 16-beat bursts, allowing re-arbitration at each 16-beat burst end. 5: 32-beat Burst The undefined length burst is split into 32-beat bursts, allowing re-arbitration at each 32-beat burst end. 6: 64-beat Burst The undefined length burst is split into 64-beat bursts, allowing re-arbitration at each 64-beat burst end. 7: 128-beat Burst The undefined length burst is split into 128-beat bursts, allowing re-arbitration at each 128-beat burst end. Unless duly needed the ULBT should be let to its default 0 value for power saving. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

26.10.2 Bus Matrix Slave Configuration Registers

Name: MATRIX_SCFG0...MATRIX_SCFG4 Address: 0xFFFFDE40 [0], 0xFFFFDE44 [1], 0xFFFFDE48 [2], 0xFFFFDE4C [3], 0xFFFFDE50 [4] Access: Read-write  SLOT_CYCLE: Maximum Bus Gr ant Duration for Masters When SLOT_CYCLE AHB clock cycles have elapsed since the last arbitration, a new arbitration takes place so as to let an other master access this slave. If an other master is requesting the slave bus, then the current master burst is broken. If SLOT_CYCLE = 0, the Slot Cycle Limit feature is disabl ed and bursts always complete unless broken according to the ULBT. This limit has been placed in order to enforce arbitration so as to meet potential latency constraints of masters waiting for slave access or in the particular case of a master performing back to back undefined length bursts indefinitely freezing the arbitration. This limit must not be small. Unreasonably small values break every burst and the Bus Matrix arbitrates without performing any data transfer. The default maximum value is usually an optimal conservative choice.  DEFMSTR_TYPE: Default Master Type 0: No Default Master At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters. This results in a one clock cycle latency for the first access of a burst transfer or for a single access. 1: Last Default Master At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it. This results in not having one clock cycle latency when the last master tries to access the slave again. 2: Fixed Default Master At the end of the current slave access, if no other master r equest is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field. This results in not having one clock cycle latency when the fixed master tries to access the slave again.  FIXED_DEFMSTR: Fixed Default Master This is the number of the Default Master for this slave. Only used if DEFMSTR_TYPE is 2. Specifying the number of a mas- ter which is not connected to the selected slave is equivalent to setting DEFMSTR_TYPE to 0. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 – – FIXED_DEFMSTR DEFMSTR_TYPE 15 14 13 12 11 10 9 8 76543210 SLOT_CYCLE

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

26.10.3 Bus Matrix Priority Registers A For Slaves

Name: MATRIX_PRAS0...MATRIX_PRAS4 Addresses: 0xFFFFDE80 [0], 0xFFFFDE88 [1], 0xFFFFDE90 [2], 0xFFFFDE98 [3], 0xFFFFDEA0 [4] Access: Read-write  MxPR: Master x Priority Fixed priority of Master x for accessing the selected slave. The higher the number, the higher the priority. All the masters programmed with the same MxPR value for the slave make up a priority pool. Round-Robin arbitration is used inside the lowest (MxPR = 0) and highest (MxPR = 3) priority pools. Fixed priority is used inside intermediate priority pools (MxPR = 1) and (MxPR = 2). See “Arbitration Priority Scheme” on page 310 for details. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 –– M 5PR –– M 4PR 15 14 13 12 11 10 9 8 –– M 3PR –– M 2PR 76543210 –– M 1PR –– M 0PR

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

26.10.4 Bus Matrix Master Remap Control Register

Name: MATRIX_MRCR Address: 0xFFFFDF00 Access: Read-write  RCBx: Remap Command Bit for Master x 0: Disable remapped address decoding for the selected Master 1: Enable remapped address decoding for the selected Master 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 – – RCB5 RCB4 RCB3 RCB2 RCB1 RCB0

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

26.10.5 Chip Configuration User Interface

Table 26-5. Chip Configuration User Interface Offset Register Name Access Reset Value 0x0110 - 0x0114 Reserved – – – 0x0118 EBI Chip Select Assignment Re gister CCFG_EBICSA Read-write 0x00000000 0x011C - 0x01FC Reserved – – –

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

26.10.5.1 EBI Chip Select Assignment Register

Name: CCFG_EBICSA Access: Read/Write Reset: 0x0000_0000  EBI_CS1A: EBI Chip Select 1 Assignment 0 = EBI Chip Select 1 is assigned to the Static Memory Controller. 1 = EBI Chip Select 1 is assigned to the DDR2SDR Controller.  EBI_CS3A: EBI Chip Select 3 Assignment 0 = EBI Chip Select 3 is only assigned to the Static Memory Controller and EBI_NCS3 behaves as defined by the SMC. 1 = EBI Chip Select 3 is assigned to the Static Memory Controller and the NAND Flash Logic is activated.  EBI_DBPUC: EBI Data Bus Pull-Up Configuration 0 = EBI D0 - D15 Data Bus bits are internally pulled-up to the VDDIOM power supply. 1 = EBI D0 - D15 Data Bus bits are not internally pulled-up.  EBI_DBPDC: EBI Data Bus Pull-Down Configuration 0 = EBI D0 - D15 Data Bus bits are internally pulled-down to the GND. 1 = EBI D0 - D15 Data Bus bits are not internally pulled-down.  EBI_DRIVE: EBI I/O Drive Configuration 0 = LOW drive. Data Bus + Memory load capacitance < TBD pF. 1 = HIGH drive (default). Data Bus + Memory load capacitance < TBD pF.  NFD0_ON_D16: NAND Flash databus selection 0 = NAND Flash I/Os are connected to D0-D15. VDDNF must be equal to VDDIOM (default). 1 = NAND Flash I/Os are connected to D16-D31. VDDNF can be different from or equal to VDDIOM. This can be used if the SMC connects to the NAND Flash only. Using this function with another device on the SMC will lead to an unpredictable behavior of that device. In that case, the default value must be selected. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Table 26-6. Connection examples with various VDDNF and VDDIOM NFD0_ON_D16 signals VDDIOM VDDNF External Memory

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

26.10.6 Write Protect Mode Register

Name: MATRIX_WPMR Address: 0xFFFFDFE4 Access: Read-write For more details on MATRIX_WPMR, refer to Section 26.9 “Write Protect Registers” on page 311.  WPEN: Write Protect ENable 0 = Disables the Write Protect if WPKEY corresponds to 0x4D4154 (“MAT” in ASCII). 1 = Enables the Write Protect if WPKEY corresponds to 0x4D4154 (“MAT” in ASCII). Protects the entire MATRIX address space from address offset 0x000 to 0x1FC.  WPKEY: Write Protect KEY (Write-only) Should be written at value 0x4D4154 (“MAT” in ASCII). Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. 31 30 29 28 27 26 25 24 WPKEY 23 22 21 20 19 18 17 16 WPKEY 15 14 13 12 11 10 9 8 WPKEY 76543210

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

26.10.7 Write Protect Status Register

Name: MATRIX_WPSR Address: 0xFFFFDFE8 Access: Read-only For more details on MATRIX_WPSR, refer to Section 26.9 “Write Protect Registers” on page 311.  WPVS: Write Protect Violation Status 0: No Write Protect Violation has occurred since the last write of the MATRIX_WPMR. 1: At least one Write Protect Violation has occurred since the last write of the MATRIX_WPMR.  WPVSRC: Write Protect Violation Source When WPVS is active, this field indicates the register address offset in which a write access has been attempted. Otherwise it reads as 0. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WPVSRC 15 14 13 12 11 10 9 8 WPVSRC 76543210

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 27. External Memories

27.1 Description

The External Bus Interface (EBI) is designed to ensure the successful data transfer between several external devices and the embedded Memory Controller of an ARM-based device. The Static Memory, DDR, SDRAM and ECC Controllers are all featured external Memory Con- trollers on the EBI. These external Memory Controllers are capable of handling several types of external memory and peripheral devices, such as SRAM, PROM, EPROM, EEPROM, Flash, DDR2 and SDRAM. The EBI operates with 1.8V or 3.3V Power Supply (VDDIOM). The EBI also supports the NAND Flash protocols via integrated circuitry that greatly reduces the requirements for external components. Furthermore, the EBI handles data transfers with up to six external devices, each assigned to six address spaces defined by the embedded Memory Controller. Data transfers are performed through a 16-bit or 32-bit data bus, an address bus of up to 26 bits, up to six chip select lines (NCS[5:0]) and several control pins that are generally multiplexed between the different external Memory Controllers.

27.2 Embedded Characteristics

32-bit Wide Interface, Supporting:

  • 16-bit DDR2/LPDDR, 32-bit SDRAM/LPSDR
  • Static Memories
  • NAND Flash with Multi-bit ECC

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

27.3 EBI Block Diagram

Figure 27-1. Organization of the External Bus Interface External Bus Interface D[15:0] A[15:2], A19 PIO MUX Logic User Interface Chip Select Assignor Static Memory Controller DDR2 LPDDR SDRAM Controller Bus Matrix APB AHB Address Decoders A16/BA0 A0/NBS0 A1/NWR2/NBS2/DQM2 A17/BA1 NCS0 NRD NCS1/SDCS NWR0/NWE NWR1/NBS1 NWR3/NBS3/DQM3 SDCK, SDCK#, SDCKE DQM[1:0] DQS[1:0] RAS, CAS SDWE, SDA10 D[31:16] A[25:20] NCS4 NCS5 NCS2 NWAIT NANDOE NANDWE NAND Flash Logic PMECC PMERRLOC Controllers A21/NANDALE A22/NANDCLE NCS3/NANDCS A18/BA2

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

27.4 I/O Lines Description

The connection of some signals through the MUX logic is not direct and depends on the Memory Controller in use at the moment. Table 27-2 on page 325 details the connections between the two Memory Controllers and the EBI pins. Table 27-1. EBI I/O Lines Description Name Function Type Active Level EBI EBI_D0 - EBI_D31 Data Bus I/O EBI_A0 - EBI_A25 Address Bus Output EBI_NWAIT External Wait Signal Input Low SMC EBI_NCS0 - EBI_NCS5 Chip Select Lines Output Low EBI_NWR0 - EBI_NWR3 Wri te Signals Output Low EBI_NRD Read Signal Output Low EBI_NWE Write Enable Output Low EBI_NBS0 - EBI_NBS3 Byte Mask Signals Output Low EBI for NAND Flash Support EBI_NANDCS NAND Flash Chip Select Line Output Low EBI_NANDOE NAND Flash Output Enable Output Low EBI_NANDWE NAND Flash Write Enable Output Low DDR2/SDRAM Controller EBI_SDCK, EBI_SDCK# DDR2/SDRAM Differential Clock Output EBI_SDCKE DDR2/SDRAM Clock Enable Output High EBI_SDCS DDR2/SDRAM Controller Chip Select Line Output Low EBI_BA0 - 2 Bank Select Output EBI_SDWE DDR2/SDRAM Write Enable Output Low EBI_RAS - EBI_CAS Row and Column Signal Output Low EBI_SDA10 SDRAM Address 10 Line Output Table 27-2. EBI Pins and Memory Controllers I/O Lines Connections EBIx Pins SDRAM I/O Lines SMC I/O Lines EBI_NWR1/NBS1/CFIOR NBS1 NWR1 EBI_A0/NBS0 Not Supported SMC_A0 EBI_A1/NBS2/NWR2 Not Supported SMC_A1 EBI_A[11:2] SDRAMC_A[9:0] SMC_A[11:2] EBI_SDA10 SDRAMC_A10 Not Supported EBI_A12 Not Supported SMC_A12 EBI_A[14:13] SDRAMC_A[12:11] SMC_A[14:13] EBI_A[25:15] Not Supported SMC_A[25:15]

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

27.5 Application Example

27.5.1 Hardware Interface

Table 27-3 on page 326 details the connections to be applied between the EBI pins and the external devices for each Memory Controller. Notes: 1. NWR1 enables upper byte writes. NWR0 enables lower byte writes. 2. NWRx enables corresponding byte x writes. (x = 0,1,2 or 3) 3. NBS0 and NBS1 enable respectively lower and upper bytes of the lower 16-bit word. 4. NBS2 and NBS3 enable respectively lower and upper bytes of the upper 16-bit word. 5. D25-31 and A20, A23-A25, NCS2, NCS4 , NCS5 are multiplexed on PD15-PD31. Table 27-3. EBI Pins and External Static Device Connections Signals: EBI_ Pins of the Interfaced Device 8-bit Static Device 2 x 8-bit Static Devices 16-bit Static Device 4 x 8-bit Static Devices 2 x 16-bit Static Devices 32-bit Static Device Controller SMC D0 - D7 D0 - D7 D0 - D7 D0 - D7 D0 - D7 D0 - D7 D0 - D7 D8 - D15 – D8 - D15 D8 - D15 D8 - D15 D8 - 15 D8 - 15 D16 - D24 – – – D16 - D23 D16 - D23 D16 - D23 D25 - D31(5)) – – – D24 - D31 D24 - D31 D24 - D31 A0/NBS0 A0 – NLB – NLB(3) BE0 A1/NWR2/NBS2/DQM2 A1 A0 A0 WE(2) NLB(4) BE2 NCS0 CS CS CS CS CS CS NCS1/DDRSDCS CS CS CS CS CS CS NCS2(5) CS CS CS CS CS CS NCS3/NANDCS CS CS CS CS CS CS NCS4(5) CS CS CS CS CS CS NCS5(5) CS CS CS CS CS CS NRD OE OE OE OE OE OE NWR0/NWE WE WE(1) WE WE(2) WE WE NWR1/NBS1 – WE(1) NUB WE(2) NUB(3) BE1 NWR3/NBS3/DQM3 – – – WE (2) NUB(4) BE3

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Table 27-4. EBI Pins and External Device Connections Signals: EBI_ Power supply Pins of the Interfaced Device DDR2/LPDDR SDR/LPSDR NAND Flash Controller DDRC SDRAMC NFC D0 - D15 VDDIOM D0 - D15 D0 - D15 NFD0-NFD15 (1) D16 - D31 VDDNF – D16 - D31 NFD0-NFD15 (1) A0/NBS0 VDDIOM – – – A1/NWR2/NBS2/DQM2 VDDIOM – DQM2 – DQM0-DQM1 VDDIOM DQM0-DQM1 DQM0-DQM1 – DQS0-DQS1 VDDIOM DQS0-DQS1 – – A2 - A10 VDDIOM A[0:8] A[0:8] – A11 VDDIOM A9 A9 – SDA10 VDDIOM A10 A10 – A12 VDDIOM – – – A13 - A14 VDDIOM A[11:12] A[11:12] – A15 VDDIOM A13 – – A16/BA0 VDDIOM BA0 BA0 – A17/BA1 VDDIOM BA1 BA1 – A18/BA2 VDDIOM BA2 BA2 – A19 VDDIOM – – – A20 VDDIOM – – – A21/NANDALE VDDNF – – ALE A22/NANDCLE VDDNF – – CLE A23 - A24 VDDIOM – – – A25 VDDIOM – – – NCS0 VDDIOM – – – NCS1/DDRSDCS VDDIOM DDRCS SDCS – NCS2 VDDIOM – – – NCS3/NANDCS VDDNF – – CE NCS4 VDDIOM – – – NCS5 VDDIOM – – – NANDOE VDDNF – – OE NANDWE VDDNF – – WE NRD VDDIOM – – – NWR0/NWE VDDIOM – – – NWR1/NBS1 VDDIOM – – – NWR3/NBS3/DQM3 VDDIOM – DQM3 – SDCK VDDIOM CK CK – SDCK# VDDIOM CK# – –

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Note: 1. A switch, NFD0_ON_D16, enables the user to select NAND Flash path on D0-D7 or D16-D24 depending on memory power supplies. This switch is located in the EBICSA register in the Bus Matrix user interface.

27.5.2 Connection Examples

Figure 27-2 shows an example of connections between the EBI and external devices. Figure 27-2. EBI Connections to Memory Devices SDCKE VDDIOM CKE CKE – RAS VDDIOM RAS RAS – CAS VDDIOM CAS CAS – SDWE VDDIOM WE WE – Pxx VDDNF – – CE Pxx VDDNF – – RDY Table 27-4. EBI Pins and External Device Connections (Continued) Signals: EBI_ Power supply Pins of the Interfaced Device DDR2/LPDDR SDR/LPSDR NAND Flash Controller DDRC SDRAMC NFC EBI D0-D31 A2-A15 RAS CAS SDCK SDCKE SDWE A0/NBS0 2M x 8 SDRAM D0-D7 A0-A9, A11 RAS CAS CLK CKE WE DQM CS BA0 BA1 NWR1/NBS1 A1/NWR2/NBS2 NWR3/NBS3 NCS1/SDCS D0-D7 D8-D15 A16/BA0 A17/BA1 A18-A25 A10 SDA10 SDA10 A2-A11, A13 NCS0 NCS2 NCS3 NCS4 NCS5 A16/BA0 A17/BA1 2M x 8 SDRAM D0-D7 A0-A9, A11 RAS CAS CLK CKE WE DQM CS BA0 BA1 A10 SDA10 A2-A11, A13 A16/BA0 A17/BA1 2M x 8 SDRAM D0-D7 A0-A9, A11 RAS CAS CLK CKE WE DQM CS BA0 BA1 D16-D23 D24-D31 A10 SDA10 A2-A11, A13 A16/BA0 A17/BA1 2M x 8 SDRAM D0-D7 A0-A9, A11 RAS CAS CLK CKE WE DQM CS BA0 BA1 A10 SDA10 A2-A11, A13 A16/BA0 A17/BA1 NBS0 NBS1 NBS3 NBS2 NRD/NOE NWR0/NWE 128K x 8 SRAM 128K x 8 SRAM D0-D7 D0-D7A0-A16 A0-A16A1-A17 A1-A17 CS CS OE WE D0-D7 D8-D15 OE WENRD/NOE A0/NWR0/NBS0 NRD/NOE NWR1/NBS1 SDWE SDWESDWE SDWE

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

27.6 Product Dependencies

27.6.1 I/O Lines

The pins used for interfacing the External Bus Interface may be multiplexed with the PIO lines. The programmer must first program the PIO controller to assign the External Bus Interface pins to their peripheral function. If I/O lines of the External Bus Interface are not used by the applica- tion, they can be used for other purposes by the PIO Controller.

27.7 Functional Description

The EBI transfers data between the internal AHB Bus (handled by the Bus Matrix) and the exter- nal memories or peripheral devices. It controls the waveforms and the parameters of the external address, data and control buses and is composed of the following elements:

  • the Static Memory Controller (SMC)
  • the DDR2/SDRAM Controller (DDR2SDRC)
  • the Programmable Multi-bit ECC Controller (PMECC)
  • a chip select assignment feature that assigns an AHB address space to the external devices
  • a multiplex controller circuit that shares the pins between the different Memory Controllers
  • programmable NAND Flash support logic

27.7.1 Bus Multiplexing

The EBI offers a complete set of control signal s that share the 32-bit data lines, the address lines of up to 26 bits and the control signals through a multiplex logic operating in function of the memory area requests. Multiplexing is specifically organized in or der to guarantee the maintenance of the address and output control lines at a stable state while no external access is being performed. Multiplexing is also designed to respect the data float times defined in the Memory Controllers. Furthermore, refresh cycles of the DDR2 and SDRAM are executed independently by the DDR2SDR Control- ler without delaying the other external Memory Controller accesses.

27.7.2 Pull-up Control

The EBI_CSA registers in the Chip Configuration User Interface permit enabling of on-chip pull- up resistors on the data bus lines not multiplexed with the PIO Controller lines. The pull-up resis- tors are enabled after reset. Setting the EBIx_DBPUC bit disables the pull-up resistors on the D0 to D15 lines. Enabling the pull-up resistor on the D16-D31 lines can be performed by program- ming the appropriate PIO controller.

27.7.3 Drive level

The EBI I/Os accept two drive level, HIGH and LOW. This allows to avoid overshoots and give the best performances according to the bus load and external memories. The voltage ranges and the slew rates are dete rmined by programming EBI_DRIVE field in the Chip Configuration registers located in the Matrix User Interface. At reset the selected current drive is HIGH.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

27.7.4 Power supplies

The product embeds a dual power supply for EBI. VDDNF for NAND Flash signals and VDDIOM for others. This allows to use an 1.8V or 3.3V NAND Flash inde pendently of SDRAM power supply. A switch, NFD0_ON_D16, enables the user to select NAND Flash path on D0-D15 or D16-D32 depending on memory power supplies. This switch is located in the register EBICSA in the Bus Matrix user interface. In the following example the NAND Flash and the external RAM (DDR2 or LPDDR or 16-bit LPSDR) are in the same power supply range, (NFD0_ON_D16 = 0) D[15:0] ALE A[22:21] CLE D[15:0] EBI NAND Flash (1.8V) DDR2 or LPDDR or 16-bit LPSDR (1.8V) D[15:0] D[15:0] ALE A[22:21] CLE D[15:0] EBI NAND Flash (3.3V) 32bit SDRAM (3.3V) D[15:0] D[31:16]D[31:16]

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 In the following example the NAND Flash and the external RAM (DDR2 or LPDDR or 16bit LPSDR) are NOT in the same power supply range (NFD0_ON_D16 = 1). This can be used if the SMC connects to the NAND Flash only. Using this function with another device on the SMC will lead to an unpredictable behavior of that device. In that case, the default value must be selected. At reset NFD0_ON_D16 = 1 and NAND Flash bus is connected to D16-D31.

27.7.5 Static Memory Controller

For information on the Static Memory Controller, refer to the Static Memory Controller section.

27.7.6 DDR2SDRAM Controller

For information on the DDR2SDR Controller, refer to the DDR2SDRC section.

27.7.7 Programmable Multi-bit ECC Controller

For information on the PMECC Controller, refer to the PMECC section.

27.7.8 NAND Flash Support

External Bus Interfaces 1 integrate circuitry that interfaces to NAND Flash devices.

27.7.8.1 External Bus Interface

The NAND Flash logic is driven by the Static Memory Controller on the NCS3 address space. Programming the EBI_CSA field in the EBI_CSA Register in the Chip Configuration User Inter- face to the appropriate value enables the NAND Flash logic. For details on this register, refer to the Bus Matrix Section. Access to an external NAND Flash device is then made by accessing the address space reserved to NCS3 (i.e., between 0x4000 0000 and 0x4FFF FFFF). The NAND Flash Logic drives the read and write command signals of the SMC on the NANDOE and NANDWE signals when the NCS3 signal is active. NANDOE and NANDWE are invalidated as soon as the transfer address fails to lie in the NCS3 address space. See Figure 27-3 on page 332 for more information. For details on these waveforms, refer to the Static Memory Controller section. D[15:0] ALE A[22:21] CLE D[15:0] EBI NAND Flash (3.3V) DDR2 or LPDDR or 16-bit LPSDR (1.8V) D[15:0] D[31:16]

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

27.7.8.2 NAND Flash Signals

The address latch enable and command latch enable signals on the NAND Flash device are driven by address bits A22 and A21 of the EBI address bus. The command, address or data words on the data bus of the NAND Flash device are distinguished by using their address within the NCSx address space. The chip enable (CE) signal of the device and the ready/busy (R/B) signals are connected to PIO lines. The CE si gnal then remains asserted even when NCSx is not selected, preventing the device from returning to standby mode. Figure 27-3. NAND Flash Application Example

27.8 Implementation Examples

The following hardware configurations are given for illustration only. The user should refer to the memory manufacturer web site to check current device availability. D[7:0] ALE NANDWE NANDOE NOE NWE A[22:21] CLE AD[7:0] PIO R/B EBI CE NAND Flash PIO NCSx/NANDCS Not Connected

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 27.8.1 2x8-bit DDR2 on EBI

27.8.1.1 Hardware Configuration

27.8.1.2 Software Configuration

  • Assign EBI_CS1 to the DDR2 controller by setti ng the EBI_CS1A bit in the EBI Chip Select Register located in the bus matrix memory space.
  • Initialize the DDR2 Controller depending on the DDR2 device and system bus frequency. The DDR2 initialization sequence is described in the sub-section “DDR2 Device Initialization” of the DDRSDRC section. In this case VDDNF can be different from VD DIOM. NAND Flash device can be 3.3V or 1.8V and wired on D16-D31 data bus. NFD0_ON_D16 is to be set to 1.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 27.8.2 16-bit LPDDR on EBI

27.8.2.1 Hardware Configuration

27.8.2.2 Software Configuration

The following configuration has to be performed:

  • Assign EBI_CS1 to the DDR2 controller by setting the bit EBI_CS1A in the EBI Chip Select Register located in the bus matrix memory space.
  • Initialize the DDR2 Controller depending on the LPDDR device and system bus frequency. The LPDDR initialization sequence is described in the section “Low-power DDR1-SDRAM Initial- ization” in “DDR/SDR SDRAM Controller (DDRSDRC)”. In this case VDDNF can be different from VD DIOM. NAND Flash device can be 3.3V or 1.8V and wired on D16-D31 data bus. NFD0_ON_D16 is to be set to 1.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 27.8.3 16-bit SDRAM

27.8.3.1 Hardware Configuration

27.8.3.2 Software Configuration

The following configuration has to be performed:

  • Assign the EBI CS1 to the SDRAM controller by setting the bit EBI_CS1A in the EBI Chip Select Assignment Register located in the bus matrix memory space.
  • Initialize the SDRAM Controller depending on the SDRAM device and system bus frequency. The Data Bus Width is to be programmed to 16 bits. The SDRAM initialization sequence is described in the section “SDRAM Device Initialization” in “SDRAM Controller (SDRAMC)”. In this case VDDNF can be different from VD DIOM. NAND Flash device can be 3.3V or 1.8V and wired on D16-D31 data bus. NFD0_ON_D16 is to be set to 1.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 27.8.4 2x16-bit SDRAM

27.8.4.1 Hardware Configuration

27.8.4.2 Software Configuration

The following configuration has to be performed:

  • Assign the EBI CS1 to the SDRAM controller by setting the bit EBI_CS1A in the EBI Chip Select Assignment Register located in the bus matrix memory space.
  • Initialize the SDRAM Controller depending on the SDRAM device and system bus frequency. The Data Bus Width is to be programmed to 32 bits. The data lines D[16..31] are multiplexed with PIO lines and thus the dedicated PIOs must be programmed in peripheral mode in the PIO controller. The SDRAM initialization sequence is described in the section “SDRAM Device Initialization” in “SDRAM Controller (SDRAMC)”. In this case, VDDNF must be equal to VDDIOM. The NAND Flash device must be 3.3V and wired on D0-D15 data bus. NFD0_ON_D16 must be set to 0. A10 A11 A13 DQM0 DQM2 BA0 CAS D10 BA1 D12 D14 D15 CLK D23 D19 D18 D30 DQM1 D24 D26 A14 D31 D22 D28 D17 D25 D27 D16 D21 DQM3 D29 D20 A13 SDA10 A10 A11 A14 CKE RAS WE SDA10 D13 D11 SDCS BA0 BA1 CLK CKE CAS RAS WE A[1..14] D[0..31] VDDIOMVDDIOM VDDIOM VDDIOM

256 Mbits 256 Mbits

N.C140 CLK38 CKE37 DQML15 DQMH39 CAS17 RAS18 WE16 CS19 VDDQ 9 VDDQ 43 VDDQ 49 VSSQ 6 VSSQ 12 VSSQ 46 VSSQ 52 VDD 14 VSS 54 A1135 BA121 100NF 100NF 100NF 100NF C12 100NF C12 100NF 100NF 100NF R3 470K 470K 100NF 100NF C14 100NF C14 100NF MT48LC16M16A2 MN1 MT48LC16M16A2P-75IT MT48LC16M16A2 MN1 MT48LC16M16A2P-75IT A023 A124 A225 A326 A429 A530 A631 A732 A833 A934 A1022 BA020 A1236 DQ0 2 DQ1 4 DQ2 5 DQ3 7 DQ4 8 DQ5 10 DQ6 11 DQ7 13 DQ8 42 DQ9 44 DQ10 45 DQ11 47 DQ12 48 DQ13 50 DQ14 51 DQ15 53 VDD 1 VSS 28 VSS 41 VDDQ 3VDD 27 N.C140 CLK38 CKE37 DQML15 DQMH39 CAS17 RAS18 WE16 CS19 VDDQ 9 VDDQ 43 VDDQ 49 VSSQ 6 VSSQ 12 VSSQ 46 VSSQ 52 VDD 14 VSS 54 A1135 BA121 470K 470K R2 0RR2 0R 100NF 100NF C10 100NF C10 100NF

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 27.8.5 8-bit NAND Flash with NFD0_ON_D16 = 0

27.8.5.1 Hardware Configuration

27.8.5.2 Software Configuration

The following configuration has to be performed:

  • Set NFD0_ON_D16 = 0 in the EBI Chip Select Assignment Register located in the bus matrix memory space
  • Assign the EBI CS3 to the NAND Flash by setting the bit EBI_CS3A in the EBI Chip Select Assignment Register
  • Reserve A21/A22 for ALE/CLE functions. Address and Command Latches are controlled respectively by setting to 1 the address bits A21 and A22 during accesses.
  • Configure a PIO line as an input to manage the Ready/Busy signal.
  • Configure Static Memory Controller CS3 Setup, Pulse, Cycle and Mode accordingly to NAND Flash timings, the data bus width and the system bus frequency. NANDOE NANDWE (ANY PIO) (ANY PIO) ALE CLE D[0..7] 3V3 3V3 2 Gb TSOP48 PACKAGE U1 K9F2G08U0MU1 K9F2G08U0M WE18 N.C6 VCC 37 CE9 RE8 N.C20 WP19 N.C5 N.C1 N.C2 N.C3 N.C4 N.C21 N.C22 N.C23 N.C24 R/B7 N.C26 N.C 27N.C 28 I/O0 29 N.C 34N.C 35 VSS 36 PRE 38N.C 39 VCC 12 VSS 13 ALE17 N.C11 N.C10 N.C14 N.C15 CLE16 N.C25 N.C 33 I/O1 30 I/O3 32I/O2 31 N.C 47 N.C 46 N.C 45 I/O7 44I/O6 43I/O5 42I/O4 41 N.C 40 N.C 48R2 10KR2 10K 100NF 100NF R1 10KR1 10K 100NF 100NF

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 27.8.6 16-bit NAND Flash with NFD0_ON_D16 = 0

27.8.6.1 Hardware Configuration

27.8.6.2 Software Configuration

The software configuration is the same as for an 8-bit NAND Flash except for the data bus width programmed in the mode register of the Static Memory Controller. D14 D11 D12 D10 D13 D15 NANDOE NANDWE (ANY PIO) ALE CLE D[0..15] (ANY PIO) 3V3 3V3 2 Gb TSOP48 PACKAGE R1 10KR1 10K R2 10KR2 10K 100NF 100NF 100NF 100NF U1 MT29F2G16AABWP-ETU1 MT29F2G16AABWP-ET WE18 N.C6 VCC 37 CE9 RE8 N.C20 WP19 N.C5 N.C1 N.C2 N.C3 N.C4 N.C21 N.C22 N.C23 N.C24 R/B7 I/O0 26 I/O8 27 I/O1 28 I/O9 29 N.C34 N.C35 N.C 36PRE 38N.C 39 VCC 12 VSS 13 ALE17 N.C11 N.C10 N.C14 N.C15 CLE16 VSS 25 I/O11 33 I/O2 30 I/O3 32 I/O10 31 I/O15 47 I/O7 46 I/O14 45 I/O6 44 I/O13 43 I/O5 42 I/O12 41 I/O4 40 VSS 48

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 27.8.7 8-bit NAND Flash with NFD0_ON_D16 = 1

27.8.7.1 Hardware Configuration

Figure 27-4.

27.8.7.2 Software Configuration

The following configuration has to be performed:

  • Set NFD0_ON_D16 = 1 in the EBI Chip Select Assignment Register located in the bus matrix memory space.
  • Assign the EBI CS3 to the NAND Flash by setting the bit EBI_CS3A in the EBI Chip Select Assignment Register.
  • Configure the PIOD controller to assign the required PIOD[23..0] to EBI function.
  • Reserve A21 / A22 for ALE / CLE functions. Address and Command Latches are controlled respectively by setting to 1 the address bit A21 and A22 during accesses.
  • Configure a PIO line as an input to manage the Ready/Busy signal.
  • Configure Static Memory Controller CS3 Setup, Pulse, Cycle and Mode accordingly to NAND Flash timings, the data bus width and the system bus frequency.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 27.8.8 16-bit NAND Flash with NFD0_ON_D16 = 1

27.8.8.1 Hardware Configuration

27.8.8.2 Software Configuration

The software configuration is the same as for an 8-bit NAND Flash except for the data bus width programmed in the mode register of the Static Memory Controller.

27.8.9 NOR Flash on NCS0

27.8.9.1 Hardware Configuration

27.8.9.2 Software Configuration

The default configuration for the Static Memory Controller, byte select mode, 16-bit data bus, Read/Write controlled by Chip Select, allows boot on 16-bit non-volatile memory at slow clock. For another configuration, configure the Static Memory Controller CS0 Setup, Pulse, Cycle and Mode depending on Flash timings and system bus frequency. A21 A22 A15 A12 A13 A11 A10 A14 A16 D14 D11 D12 D10 D13 D15 A17 A20 A18 A19 D[0..15] A[1..22] NRST NWE NCS0 NRD 3V3 3V3 TSOP48 PACKAGE 100NF 100NF 100NF 100NF AT49BV6416 AT49BV6416 A025 A124 A223 A322 A421 A520 A619 A718 A88 A97 A106 A115 A124 A133 A142 A151 A1648 A1717 A1816 A219 A2010 A1915 WE11 RESET12 WP14 OE28 CE26 VPP13 DQ0 29 DQ1 31 DQ2 33 DQ3 35 DQ4 38 DQ5 40 DQ6 42 DQ7 44 DQ8 30 DQ9 32 DQ10 34 DQ11 36 DQ12 39 DQ13 41 DQ14 43 DQ15 45 VCCQ 47 VSS 27VSS 46 VCC 37

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 341 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 28. Programmable Multibit ECC Controller (PMECC) for MLC Devices

28.1 Description

The PMECC Controller is a programmable binary BCH (Bose, Chaudhuri and Hocquenghem) encoder/decoder. This controller can be used to generate redundancy information for both Sin- gle-Level Cell (SLC) and Multi-level Cell (MLC) NAND Flash devices. It supports redundancy for correction of 2, 4, 8, 12 or 24 bits of error per sector of data.

28.2 Embedded Characteristics

  • Multibit Error Correcting Code.
  • Algorithm based on binary shortened Bose, Chaudhuri and Hocquenghem (BCH) codes.
  • Programmable Error Correcting Capability: 2, 4, 8, 12 and 24 bit of errors per sector.
  • Programmable Sector Size: 512 bytes or 1024 bytes.
  • Programmable Number of Sectors per page: 1, 2, 4 or 8 sectors of data per page.
  • Programmable Spare Area Size.
  • Supports Spare Area ECC Protection.
  • Supports 8 kbytes page size using 1024 bytes per sector and 4 kbytes page size using 512 bytes per sector.
  • Configurable through APB interface
  • Multibit Error Detection is Interrupt Driven.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 342 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

28.3 Block Diagram

Figure 28-1. Block Diagram

28.4 Functional Description

The NAND Flash sector size is programmable and can be set to 512 bytes or 1024 bytes. The PMECC module generates redundancy at encoding time, when a NAND write page operation is performed. The redundancy is appended to the page and written in the spare area. This opera- tion is performed by the processor. It moves the content of the PMECCx registers into the NAND Flash memory. The number of re gisters depends on the selected error correction capability, refer to Table 28-1 on page 345 . This operation is executed for each sector. At decoding time, the PMECC module generates the remainder of the received codeword by minimal polynomials. When all polynomial remainders for a given sector are set to zero, no error occurred. When the polynomial remainders are other than zero, the codeword is corrupted and further processing is required. The PMECC module generates an interrupt indicating that an error occurred. The processor must read the PMECCISR register. This register indicates which sector is corrupted. To find the error location within a sector, the processor must execute the decoding steps as follows: 1. Syndrome computation 2. Find the error locator polynomials User Interface Programmable BCH Algorithm Static Memory Controller APB MLC/SLC NAND Flash device PMECC Controller 8-Bit Data Bus Control Bus

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 343 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 3. Find the roots of the error locator polynomial All decoding steps involve finite field computation. It means that a library of finite field arithmetic must be available to perform addition, multiplication and inversion. The finite field arithmetic operations can be performed through the use of a memory mapped lookup table, or direct soft- ware implementation. The software implementat ion presented is bas ed on lookup tables. Two tables named gf_log and gf_antilog are used. If alpha is the primitive element of the field, then a power of alpha is in the field. Assume beta = alpha ^ index, then beta belongs to the field, and gf_log(beta) = gf_log(alpha ^ index) = index. The gf_antilog tables provide exponent inverse of the element, if beta = alpha ^ index, then gf_antilog(index) = beta. The first step consists of the syndrome computation. The PMECC module computes the remain- ders and software must substitute the power of the primitive element. The procedure implementation is given in Section 28.5.1 “Remainder Substitution Procedure” on page 349. The second step is the most software intensive. It is the Berlekamp’s iterative algorithm for find- ing the error-location polynomial. The procedure implementation is given in Section 28.5.2 “Find the Error Location Polynomial Sigma(x)” on page 350. The Last step is finding the root of the error lo cation polynomial. This step can be very software intensive. Indeed, there is no straightforward method of finding the roots, except by evaluating each element of the field in the error location polynomial. However a hardware accelerator can be used to find the roots of the polynomial. The Programmable Multibit Error Correction Code Location (PMERRLOC) module provides this kind of hardware acceleration.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 344 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Figure 28-2. Software/Hardware Multibit Error Correction Dataflow NAND Flash PROGRAM PAGE Operation Configure PMECC : error correction capability sector size/page size NAND write field set to true spare area desired layout Move the NAND Page to external Memory whether using DMA or Processor Copy redundancy from PMECC user interface to user defined spare area. using DMA or Processor. PMECC computes redundancy as the data is written into external memory NAND Flash READ PAGE Operation Configure PMECC : error correction capability sector size/page size NAND write field set to false spare area desired layout Move the NAND Page from external Memory whether using DMA or Processor PMECC computes polynomial remainders as the data is read from external memory PMECC modules indicate if at least one error is detected. If a sector is corrupted use the substitute() function to determine the syndromes. When the table of syndromes is completed, use the get_sigma() function to get the error location polynomial. Find the error positions finding the roots of the error location polynomial. And correct the bits. This step can be hardware assisted using the PMERRLOC module. Hardware Accelerator Software Hardware Accelerator Software

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 345 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

28.4.1 MLC/SLC Write Page Operation using PMECC

When an MLC write page operation is performed, the PMECC controller is configured with the NANDWR field of the PMECCFG register set to one. When the NAND spare area contains file system information and redundancy (PMECCx), the spare area is error protected, then the SPA- REEN bit of the PMECCFG register is set to one. When the NAND spare area contains only redundancy information, the SPAREEN bit is set to zero. When the write page operation is terminated, the user writes the redundancy in the NAND spare area. This operation can be done with DMA assistance.

28.4.1.1 SLC/MLC Write Operation with Spare Enable Bit Set

When the SPAREEN field of the PMECC_CFG register is set to one, the spare area of the page is encoded with the stream of data of the last sector of the page. This mode is entered by writing one in the DATA field of the PMECC_CTRL register. When the encoding process is over, the redundancy is written to the spare area in user mode, USER field of the PMECC_CTRL must be set to one. Table 28-1. Relevant Redundancy Registers BCH_ERR field sector size set to 512 bytes sector size set to 1024 bytes

0 PMECC_ECC0 PMECC_ECC0

1 PMECC_ECC0, PMECC_ECC1 PMECC_ECC0, PMECC_ECC1

2 PMECC_ECC0, PMECC_ECC1,

PMECC_ECC2, PMECC_ECC3 PMECC_ECC0, PMECC_ECC1, PMECC_ECC2, PMECC_ECC3 PMECC_ECC0, PMECC_ECC1, PMECC_ECC2, PMECC_ECC3, PMECC_ECC4, PMECC_ECC5, PMECC_ECC6 PMECC_ECC0, PMECC_ECC1, PMECC_ECC2, PMECC_ECC3, PMECC_ECC4, PMECC_ECC5, PMECC_ECC6 PMECC_ECC0, PMECC_ECC1, PMECC_ECC2, PMECC_ECC3, PMECC_ECC4, PMECC_ECC5, PMECC_ECC6, PMECC_ECC7, PMECC_ECC8, PMECC_ECC9 PMECC_ECC0, PMECC_ECC1, PMECC_ECC2, PMECC_ECC3, PMECC_ECC4, PMECC_ECC5, PMECC_ECC6, PMECC_ECC7, PMECC_ECC8, PMECC_ECC9, PMECC_ECC10 Table 28-2. Number of relevant ECC bytes per sector, copied from LSbyte to MSbyte BCH_ERR field sector size set to 512 bytes sector size set to 1024 bytes 0 4 bytes 4 bytes 1 7 bytes 7 bytes 2 13 bytes 14 bytes 3 20 bytes 21 bytes 4 39 bytes 42 bytes

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 346 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Figure 28-3. NAND Write Operation with Spare Encoding

28.4.1.2 MLC/SLC Write Operation with Spare Area Disabled

When the SPAREEN field of PMECC_CFG is set to zero the spare area is not encoded with the stream of data. This mode is entered by wr iting one to the DATA field of the PMECC_CTRL register. Figure 28-4. NAND Write Operation Sector 0 512 or 1024 bytes Sector 1 Sector 2 Sector 3 Spare pagesize = n * sectorsize sparesize ecc_area start_addr end_addr ECC computation enable signal Write NAND operation with SPAREEN set to one Sector 0 512 or 1024 bytes Sector 1 Sector 2 Sector 3 pagesize = n * sectorsize ECC computation enable signal Write NAND operation with SPAREEN set to zero

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 347 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

28.4.2 MLC/SLC Read Page Operation using PMECC

28.4.2.1 MLC/SLC Read Operation with Spare Decoding

When the spare area is protected, the spare area contains valid data. As the redundancy may be included in the middle of the information stream, the user programs the start address and the end address of the ECC area. The controller will automatically skip the ECC area. This mode is entered by writing one in the DATA field of the PMECC_CTRL register. When the page has been fully retrieved from NAND, the ECC area is read using the user mode by writing one to the USER field of the PMECC_CTRL register. Figure 28-5. Read Operation with Spare Decoding Table 28-3. Relevant Remainders Registers BCH_ERR field Sector size set to 512 by tes Sector size set to 1024 bytes

0 PMECC_REM0 PMECC_REM0

1 PMECC_REM0, PMECC_REM1 PMECC_REM0, PMECC_REM1

2 PMECC_REM0, PMECC_REM1,

PMECC_REM2, PMECC_REM3, PMECC_REM0, PMECC_REM1, PMECC_REM2, PMECC_REM3 PMECC_REM0, PMECC_REM1, PMECC_REM2, PMECC_REM3, PMECC_REM4, PMECC_REM5, PMECC_REM6, PMECC_REM7 PMECC_REM0, PMECC_REM1, PMECC_REM2, PMECC_REM3, PMECC_REM4, PMECC_REM5, PMECC_REM6, PMECC_REM7 PMECC_REM0, PMECC_REM1, PMECC_REM2, PMECC_REM3, PMECC_REM4, PMECC_REM5, PMECC_REM6, PMECC_REM7, PMECC_REM8, PMECC_REM9, PMECC_REM10, PMECC_REM11 PMECC_REM0, PMECC_REM1, PMECC_REM2, PMECC_REM3, PMECC_REM4, PMECC_REM5, PMECC_REM6, PMECC_REM7, PMECC_REM8, PMECC_REM9, PMECC_REM10, PMECC_REM11 Sector 0 512 or 1024 bytes Sector 1 Sector 2 Sector 3 Spare pagesize = n * sectorsize sparesize ecc_area start_addr end_addr Remainder computation enable signal Read NAND operation with SPAREEN set to One and AUTO set to Zero

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 348 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

28.4.2.2 MLC/SLC Read Operation

If the spare area is not protected with the error correcting code, the redundancy area is retrieved directly. This mode is entered by writing one in the DATA field of the PMECC_CTRL register. When AUTO field is set to one the ECC is retrieved automatically, otherwise the ECC must be read using user mode. Figure 28-6. Read Operation

28.4.2.3 MLC/SLC User Read ECC Area

This mode allows a manual retrieve of the ECC. This mode is entered writing one in the USER field of the PMECC_CTRL register. Figure 28-7. User Read Mode Sector 0 512 or 1024 bytes Sector 1 Sector 2 Sector 3 Spare pagesize = n * sectorsize sparesize ecc_area start_addr end_addr Remainder computation enable signal Read NAND operation with SPAREEN set to Zero and AUTO set to One ECC_SEC0 ECC_SEC1 ECC_SEC2 ECC_SEC3 ECC ecc_area_size ecc_area end_addraddr = 0 Partial Syndrome computation enable signal

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 349 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

28.5 Software Implementation

28.5.1 Remainder Substitution Procedure

The substitute function evaluates the polynomial remainder, with different values of the field primitive elements. The finite field arithmetic addition operation is performed with the Exclusive or. The finite field arithmetic multiplication ope ration is performed through the gf_log, gf_antilog lookup tables. The REM2NP1 and REMN2NP3 fields of the PMECC_REMx registers contain only odd remain- ders. Each bit indicates whether the coefficient of the polynomial remainder is set to zero or not. NB_ERROR_MAX defines the maximum value of the error correcting capability. NB_ERROR defines the error correcting capability selected at encoding/decoding time. NB_FIELD_ELEMENTS defines the number of elements in the field. si[] is a table that holds the current syndrome value, an element of that table belongs to the field. This is also a shared variable for the next step of the decoding operation. oo[] is a table that contains the degree of the remainders. int substitute() int i; int j; for (i = 1; i < 2 * NB_ERROR_MAX; i++) si[i] = 0; for (i = 1; i < 2*NB_ERROR; i++) for (j = 0; j < oo[i]; j++) if (REM2NPX[i][j]) si[i] = gf_antilog[(i * j)%NB_FIELD_ELEMENTS] ^ si[i]; return 0;

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 350 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

28.5.2 Find the Error Location Polynomial Sigma(x)

The sample code below gives a Berlekamp iterativ e procedure for finding the value of the error location polynomial. The input of the procedure is the si[] table defined in the remainder substitution procedure. The output of the procedure is the error location polynomial named smu (sigma mu). The poly- nomial coefficients belong to the field. The smu[ NB_ERROR+1][] is a table that contains all these coefficients. NB_ERROR_MAX defines the maximum value of the error correcting capability. NB_ERROR defines the error correcting capability selected at encoding/decoding time. NB_FIELD_ELEMENTS defines the number of elements in the field. int get_sigma() int i; int j; int k; /* mu */ int mu[NB_ERROR_MAX+2]; /* sigma ro */ int sro[2*NB_ERROR_MAX+1]; /* discrepancy */ int dmu[NB_ERROR_MAX+2]; /* delta order */ int delta[NB_ERROR_MAX+2]; /* index of largest delta */ int ro; int largest; int diff; /* */ /* First Row */ /* */ /* Mu */ mu[0] = -1; /* Actually -1/2 */ /* Sigma(x) set to 1 */ for (i = 0; i < (2*NB_ERROR_MAX+1); i++) smu[0][i] = 0; smu[0][0] = 1; /* discrepancy set to 1 */ dmu[0] = 1; /* polynom order set to 0 */ lmu[0] = 0; /* delta set to -1 */ delta[0] = (mu[0] * 2 - lmu[0]) >> 1; /* */ /* Second Row */

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 351 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 /* */ /* Mu */ mu[1] = 0; /* Sigma(x) set to 1 */ for (i = 0; i < (2*NB_ERROR_MAX+1); i++) smu[1][i] = 0; smu[1][0] = 1; /* discrepancy set to Syndrome 1 */ dmu[1] = si[1]; /* polynom order set to 0 */ lmu[1] = 0; /* delta set to 0 */ delta[1] = (mu[1] * 2 - lmu[1]) >> 1; for (i=1; i <= NB_ERROR; i++) mu[i+1] = i << 1; /* */ /* */ /* Compute Sigma (Mu+1) */ /* And L(mu) */ /* check if discrepancy is set to 0 */ if (dmu[i] == 0) /* copy polynom */ for (j=0; j<2*NB_ERROR_MAX+1; j++) smu[i+1][j] = smu[i][j]; /* copy previous polynom order to the next */ lmu[i+1] = lmu[i]; else ro = 0; largest = -1; /* find largest delta with dmu != 0 */ for (j=0; j<i; j++) if (dmu[j]) if (delta[j] > largest) largest = delta[j]; ro = j;

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 352 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 /* initialize signal ro */ for (k = 0; k < 2*NB_ERROR_MAX+1; k ++) sro[k] = 0; /* compute difference */ diff = (mu[i] - mu[ro]); /* compute X ^ (2(mu-ro)) */ for (k = 0; k < (2*NB_ERROR_MAX+1); k ++) sro[k+diff] = smu[ro][k]; /* multiply by dmu * dmu[ro]^-1 */ for (k = 0; k < 2*NB_ERROR_MAX+1; k ++) /* dmu[ro] is not equal to zero by definition */ /* check that operand are different from 0 */ if (sro[k] && dmu[i]) /* galois inverse */ sro[k] = gf_antilog[(gf_log[dmu[i]] + (NB_FIELD_ELEMENTS- gf_log[dmu[ro]]) + gf_log[sro[k]]) % NB_FIELD_ELEMENTS]; /* multiply by dmu * dmu[ro]^-1 */ for (k = 0; k < 2*NB_ERROR_MAX+1; k++) smu[i+1][k] = smu[i][k] ^ sro[k]; if (smu[i+1][k]) /* find the order of the polynom */ lmu[i+1] = k << 1; /* */ /* */ /* End Compute Sigma (Mu+1) */ /* And L(mu) */ /* In either case compute delta */ delta[i+1] = (mu[i+1] * 2 - lmu[i+1]) >> 1; /* In either case compute the discrepancy */ for (k = 0 ; k <= (lmu[i+1]>>1); k++)

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 353 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 if (k == 0) dmu[i+1] = si[2*(i-1)+3]; /* check if one operand of the multiplier is null, its index is -1 */ else if (smu[i+1][k] && si[2*(i-1)+3-k]) dmu[i+1] = gf_antilog[(gf_log[smu[i+1][k]] + gf_log[si[2*(i-1)+3-k]])%nn] ^ dmu[i+1]; return 0;

28.5.3 Find the Error Position

The output of the get_sigma() procedure is a polynomial stored in the smu[NB_ERROR+1][] table. The error position is the roots of that po lynomial. The degree of this polynomial is very important information, as it gives the number of errors. The PMERRLOC module provides a hardware accelerator for this step.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 354 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

28.6 Programmable Multibit ECC Controller (PMECC) User Interface

Table 28-4. Register Mapping Offset Register Name Access Reset 0x00000000 PMECC Configuration Register PMECC_CFG Read-write 0x00000000 0x00000004 PMECC Spare Area Size Register PMECC_SAREA Read-write 0x00000000 0x00000008 PMECC Start Address Register PMECC_SADDR Read-write 0x00000000 0x0000000C PMECC End Address Register PMECC_EADDR Read-write 0x00000000 0x00000010 PMECC Clock Control Register PMECC_CLK Read-write 0x00000000 0x00000014 PMECC Control Register PMECC_CTRL Write-only 0x00000000 0x00000018 PMECC Status Register PMECC_SR Read-only 0x00000000 0x0000001C PMECC Interrupt Enable register PMECC_IER Write-only 0x00000000 0x00000020 PMECC Interrupt Disable Register PMECC_IDR Write-only – 0x00000024 PMECC Interrupt Mask Register PMECC_IMR Read-only 0x00000000 0x00000028 PMECC Interrupt Status Register PMECC_ISR Read-only 0x00000000 0x0000002C Reserved – – – 0x040+sec_num*(0x40)+0x00 PMECC ECC 0 Register PMECC_ECC0 Read-only 0x00000000 0x040+sec_num*(0x40)+0x04 PMECC ECC 1 Register PMECC_ECC1 Read-only 0x00000000 0x040+sec_num*(0x40)+0x08 PMECC ECC 2 Register PMECC_ECC2 Read-only 0x00000000 0x040+sec_num*(0x40)+0x0C PMECC ECC 3 Register PMECC_ECC3 Read-only 0x00000000 0x040+sec_num*(0x40)+0x10 PMECC ECC 4 Register PMECC_ECC4 Read-only 0x00000000 0x040+sec_num*(0x40)+0x14 PMECC ECC 5 Register PMECC_ECC5 Read-only 0x00000000 0x040+sec_num*(0x40)+0x18 PMECC ECC 6 Register PMECC_ECC6 Read-only 0x00000000 0x040+sec_num*(0x40)+0x1C PMECC ECC 7 Register PMECC_ECC7 Read-only 0x00000000 0x040+sec_num*(0x40)+0x20 PMECC ECC 8 Register PMECC_ECC8 Read-only 0x00000000 0x040+sec_num*(0x40)+0x24 PMECC ECC 9 Register PMECC_ECC9 Read-only 0x00000000 0x040+sec_num*(0x40)+0x28 PMECC ECC 10 Register PMECC_ECC10 Read-only 0x00000000 0x240+sec_num*(0x40)+0x00 PMECC REM 0 Register PMECC_REM0 Read-only 0x00000000 0x240+sec_num*(0x40)+0x04 PMECC REM 1 Register PMECC_REM1 Read-only 0x00000000 0x240+sec_num*(0x40)+0x08 PMECC REM 2 Register PMECC_REM2 Read-only 0x00000000 0x240+sec_num*(0x40)+0x0C PMECC REM 3 Register PMECC_REM3 Read-only 0x00000000 0x240+sec_num*(0x40)+0x10 PMECC REM 4 Register PMECC_REM4 Read-only 0x00000000 0x240+sec_num*(0x40)+0x14 PMECC REM 5 Register PMECC_REM5 Read-only 0x00000000 0x240+sec_num*(0x40)+0x18 PMECC REM 6 Register PMECC_REM6 Read-only 0x00000000 0x240+sec_num*(0x40)+0x1C PMECC REM 7 Register PMECC_REM7 Read-only 0x00000000 0x240+sec_num*(0x40)+0x20 PMECC REM 8 Register PMECC_REM8 Read-only 0x00000000 0x240+sec_num*(0x40)+0x24 PMECC REM 9 Register PMECC_REM9 Read-only 0x00000000

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 355 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 0x240+sec_num*(0x40)+0x28 PMECC REM 10 Register PMECC_REM10 Read-only 0x00000000 0x240+sec_num*(0x40)+0x2C PMECC REM 11 Register PMECC_REM11 Read-only 0x00000000 0x440 - 0x5FC Reserved – – – Table 28-4. Register Mapping (Continued) Offset Register Name Access Reset

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 356 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

28.6.1 PMECC Configuration Register

Name: PMECC_CFG Address: 0xFFFFE000 Access: Read-write Reset: 0x00000000  BCH_ERR: Error Correct Capability  SECTORSZ: Sector Size 0: The ECC computation is based on a sector of 512 bytes. 1: The ECC computation is based on a sector of 1024 bytes.  PAGESIZE: Number of Sectors in the Page  NANDWR: NAND Write Access :0: NAND read access 1: NAND write access  SPAREEN: Spare Enable – for NAND write access: 0: the spare area is skipped 1: the spare area is protected with the last sector of data. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 NANDWR – – PAGESIZE 76543210 Value Name Description

0 BCH_ERR2 2 errors

1 BCH_ERR4 4 errors

2 BCH_ERR8 8 errors

3 BCH_ERR12 12 errors

4 BCH_ERR24 24 errors

0 PAGESIZE_1SEC 1 sector for main area (512 or 1024 bytes)

1 PAGESIZE_2SEC 2 sectors for main area (1024 or 2048 bytes)

2 PAGESIZE_4SEC 4 sectors for main area (2048 or 4096 bytes)

3 PAGESIZE_8SEC 8 errors for main area (4096 or 8192 bytes)

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 357 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 – for NAND read access: 0: the spare area is skipped. 1: the spare area contains protected data or only redundancy information.  AUTO: Automatic Mode Enable This bit is only relevant in NAND Read Mode, when spare enable is activated. 0: Indicates that the spare area is not protected. In that case the ECC computation takes into account the ECC area located in the spare area. (within the start address and the end address). 1: Indicates that the spare is error protected. In this case, the ECC computation takes into account the whole spare area minus the ECC area in the ECC computation operation.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 358 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

28.6.2 PMECC Spare Area Size Register

Name: PMECC_SAREA Address: 0xFFFFE004 Access: Read-write Reset: 0x00000000  SPARESIZE: Spare Area Size The spare area size is equal to (SPARESIZE+1) bytes. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 SPARESIZE

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 359 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

28.6.3 PMECC Start Address Register

Name: PMECC_SADDR Address: 0xFFFFE008 Access: Read-write Reset: 0x00000000  STARTADDR: ECC Area Start Address (byte oriented address) This field indicates the first byte address of the ECC area. Location 0 matches the first byte of the spare area. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 STARTADDR

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 360 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

28.6.4 PMECC End Address Register

Name: PMECC_EADDR Address: 0xFFFFE00C Access: Read-write Reset: 0x00000000  ENDADDR: ECC Area End Address (byte oriented address) This field indicates the last byte address of the ECC area. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 ENDADDR 76543210 ENDADDR

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 361 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

28.6.5 PMECC Clock Control Register

Name: PMECC_CLK Address: 0xFFFFE010 Access: Read-write Reset: 0x00000000  CLKCTRL: Clock Control Register The PMECC Module data path Setup Time is set to CLKCTRL+1. This field indicates the database setup times in number of clock cycles. At 133 Mhz, this field must be programmed with 2, indicating that the setup time is 3 clock cycles. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 362 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

28.6.6 PMECC Control Register

Name: PMECC_CTRL Address: 0xFFFFE014 Access: Write-only Reset: 0x00000000  RST: Reset the PMECC Module When set to one, this bit reset PMECC controller, configuration registers remain unaffected.  DATA: Start a Data Phase  USER: Start a User Mode Phase  ENABLE: PMECC Module Enable PMECC module must always be configured before being activated.  DISABLE: PMECC Module Disable PMECC module must always be configured after being deactivated. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 – – DISABLE ENABLE – USER DATA RST

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 363 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

28.6.7 PMECC Status Register

Name: PMECC_SR Address: 0xFFFFE018 Access: Read-only Reset: 0x00000000  BUSY: The Kernel of the PMECC is Busy  ENABLE: PMECC Module Status 0: the PMECC Module is disabled and can be configured. 1: the PMECC Module is enabled and the configuration registers cannot be written. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 364 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

28.6.8 PMECC Interrupt Enable Register

Name: PMECC_IER Address: 0xFFFFE01C Access: Write-only Reset: 0x00000000  ERRIE: Error Interrupt Enable 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 365 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

28.6.9 PMECC Interrupt Disable Register

Name: PMECC_IDR Address: 0xFFFFE020 Access: Write Reset: 0x00000000  ERRID: Error Interrupt Disable 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 366 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

28.6.10 PMECC Interrupt Mask Register

Name: PMECC_IMR Address: 0xFFFFE024 Access: Read-only Reset: 0x00000000  ERRIM: Error Interrupt Enable 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 367 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

28.6.11 PMECC Interrupt Status Register

Name: PMECC_ISR Address: 0xFFFFE028 Access: Read-only Reset: 0x00000000  ERRIS: Error Interrupt Status Register When set to one, bit i of the PMECCISR register indicates that sector i is corrupted. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 31 30 29 28 27 26 25 24 ERRIS

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 368 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

28.6.12 PMECC ECC x Register

Name: PMECC_ECCx [x=0..10] [sec_num=0..7] Address: 0xFFFFE040 [0][0] .. 0xFFFFE068 [10][0] 0xFFFFE080 [0][1] .. 0xFFFFE0A8 [10][1] 0xFFFFE0C0 [0][2] .. 0xFFFFE0E8 [10][2] 0xFFFFE100 [0][3] .. 0xFFFFE128 [10][3] 0xFFFFE140 [0][4] .. 0xFFFFE168 [10][4] 0xFFFFE180 [0][5] .. 0xFFFFE1A8 [10][5] 0xFFFFE1C0 [0][6] .. 0xFFFFE1E8 [10][6] 0xFFFFE200 [0][7] .. 0xFFFFE228 [10][7] Access: Read-only Reset: 0x00000000  ECC: BCH Redundancy This register contains the remainder of the division of the codeword by the generator polynomial. 31 30 29 28 27 26 25 24 ECC 23 22 21 20 19 18 17 16 ECC 15 14 13 12 11 10 9 8 ECC 76543210 ECC

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 369 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

28.6.13 PMECC Remainder x Register

Name: PMECC_REMx [x=0..11] [sec_num=0..7] Address: 0xFFFFE240 [0][0] .. 0xFFFFE26C [11][0] 0xFFFFE280 [0][1] .. 0xFFFFE2AC [11][1] 0xFFFFE2C0 [0][2] .. 0xFFFFE2EC [11][2] 0xFFFFE300 [0][3] .. 0xFFFFE32C [11][3] 0xFFFFE340 [0][4] .. 0xFFFFE36C [11][4] 0xFFFFE380 [0][5] .. 0xFFFFE3AC [11][5] 0xFFFFE3C0 [0][6] .. 0xFFFFE3EC [11][6] 0xFFFFE400 [0][7] .. 0xFFFFE42C [11][7] Access: Read-only Reset: 0x00000000  REM2NP1: BCH Remainder 2 * N + 1 When sector size is set to 512 bytes, bit REM2NP1[13] is not used and read as zero. If bit i of the REM2NP1 field is set to one then the coefficient of the X ^ i is set to one, otherwise the coefficient is zero.  REM2NP3: BCH Remainder 2 * N + 3 When sector size is set to 512 bytes, bit REM2NP3[29] is not used and read as zero. If bit i of the REM2NP3 field is set to one then the coefficient of the X ^ i is set to one, otherwise the coefficient is zero. 31 30 29 28 27 26 25 24 –– REM2NP3 23 22 21 20 19 18 17 16 REM2NP3 15 14 13 12 11 10 9 8 –– REM2NP1 76543210 REM2NP1

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 370 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 371 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 29. Programmable Multibit ECC Error Location Controller (PMERRLOC)

29.1 Description

The PMECC Error Location Controller provides hardware acceleration for determining roots of polynomials over two finite fields: GF(2^13) and GF(2^14). It integrates 24 fully programmable coefficients. These coefficients belong to GF(2^1 3) or GF(2^14). The coefficient programmed in the PMERRLOC_SIGMAx register is the coefficient of degree x in the polynomial.

29.2 Embedded Characteristics

  • Provides Hardware Acceleration for determining roots of polynomials defined over a finite field
  • Programmable Finite Field GF(2^13) or GF(2^14)
  • Finds Roots of Error Locator Polynomial
  • Programmable Number of Roots

29.3 Block Diagram

Figure 29-1. Block Diagram User Interface Programmable Searching Circuit APB PMECC Error Location Controller

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 372 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

29.4 Functional Description

The PMERRLOC search operation is started as soon as a write access is detected in the ELEN register and can be disabled by writing to the ELDIS register. The ENINIT field of the ELEN reg- ister shall be initialized with the number of Galois field elements to test. The set of the roots can be limited to a valid range. When the PMEERRLOC engine is searching for roots the BUSY field of the ELSR remains asserted. An interrupt is asserted at the end of the computation, and the DONE bit of the ELSIR register is set. The ERR_CNT field of the ELISR indicates the number of errors. The error posi- tion can be read in the PMERRLOCx registers. Table 29-1. ENINIT field value for a sector size of 512 bytes Error Correcting Capability ENINIT Value 2 4122 4 4148 8 4200 12 4252 24 4408 Table 29-2. ENINIT field value for a sector size of 1024 bytes Error Correcting Capability ENINIT Value 2 8220 4 8248 8 8304 12 8360 24 8528

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 373 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

29.5 Programmable Multibit ECC Error Location (PMERRLOC ) User Interface

Table 29-3. Register Mapping Offset Register Name Access Reset 0x000 Error Location Configuration Register PMERRLOC_ELCFG Read-write 0x00000000 0x004 Error Location Primitive Register PMERRLOC_ELPRIM Read-only 0x00000000 0x008 Error Location Enable Register PMERRLOC_ELEN Read-write 0x00000000 0x00C Error Location Disable Register PMERRLOC_ELDIS Read-write 0x00000000 0x010 Error Location Status Register PMERRLOC_ELSR Read-write 0x00000000 0x014 Error Location Interrupt Enable register PMERRLOC_ELIER Read-only 0x00000000 0x018 Error Location Interrupt Disable Register PMERRLOC_ELIDR Read-only 0x00000000 0x01C Error Location Interrupt Mask Register PMERRLOC_ELIMR Read-only 0x00000000 0x020 Error Location Interrupt Status Register PMERRLOC_ELISR Read-only 0x00000000 0x024 Reserved – – – 0x028 PMECC SIGMA 0 Register PMERRLOC_SIGMA0 Read-write 0x00000000 0x088 PMECC SIGMA 24 Register PMERRLOC_SIGMA24 Read-write 0x00000000 0x08C PMECC Error Location 0 Register PMERRLOC_EL0 Read-only 0x00000000 0x0E4 PMECC Error Location 23 Register PMERRLOC_EL23 Read-only 0x00000000 0xE8 - 0X1FC Reserved – – –

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 374 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

29.5.1 Error Location Configuration Register

Name: PMERRLOC_ELCFG Address: 0xFFFFE600 Access: Read-write Reset: 0x00000000  ERRNUM: Number of Errors  SECTORSZ: Sector Size 0: The ECC computation is based on a 512-byte sector. 1: The ECC computation is based on a 1024-byte sector. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 – – – ERRNUM 15 14 13 12 11 10 9 8 76543210

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 375 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

29.5.2 Error Location Primitive Register

Name: PMERRLOC_ELPRIM Address: 0xFFFFE604 Access: Read-only Reset: 0x00000000  PRIMITIV: Primitive Polynomial 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 PRIMITIV 76543210 PRIMITIV

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 376 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

29.5.3 Error Location Enable Register

Name: PMERRLOC_ELEN Address: 0xFFFFE608 Access: Read-write Reset: 0x00000000  ENINIT: Initial Number of Bits in the Codeword 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 –– ENINIT 76543210 ENINIT

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 377 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

29.5.4 Error Location Disable Register

Name: PMERRLOC_ELDIS Address: 0xFFFFE60C Access: Read-write Reset: 0x00000000  DIS: Disable Error Location Engine 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 378 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

29.5.5 Error Location Status Register

Name: PMERRLOC_ELSR Address: 0xFFFFE610 Access: Read-write Reset: 0x00000000  BUSY: Error Location Engine Busy 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 379 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

29.5.6 Error Location Interrupt Enable Register

Name: PMERRLOC_ELIER Address: 0xFFFFE614 Access: Read-only Reset: 0x00000000  DONE: Computation Terminated Interrupt Enable 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 380 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

29.5.7 Error Location Interrupt Disable Register

Name: PMERRLOC_ELIDR Address: 0xFFFFE618 Access: Read-only Reset: 0x00000000  DONE: Computation Terminated Interrupt Disable 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 381 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

29.5.8 Error Location Interrupt Mask Register

Name: PMERRLOC_ELIMR Address: 0xFFFFE61C Access: Read-only Reset: 0x00000000  DONE: Computation Terminated Interrupt Mask 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 382 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

29.5.9 Error Location Interrupt Status Register

Name: PMERRLOC_ELISR Address: 0xFFFFE620 Access: Read-only Reset: 0x00000000  DONE: Computation Terminated Interrupt Status  ERR_CNT: Error Counter value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 ––– ERR_CNT 76543210

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 383 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

29.5.10 Error Location SIGMAx Register

Name: PMERRLOC_SIGMAx [x=0..24] Address: 0xFFFFE628 Access: Read-Write Reset: 0x00000000  SIGMAx: Coefficient of degree x in the SIGMA polynomial. SIGMAx belongs to the finite field GF(2^13) when the sector size is set to 512 bytes. SIGMAx belongs to the finite field GF(2^14) when the sector size is set to 1024 bytes. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 –– SIGMAN 76543210 SIGMAN

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 384 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

29.5.11 PMECC Error Locationx Register

Name: PMERRLOC_ELx [x=0..23] Address: 0xFFFFE68C Access: Read-only Reset: 0x00000000  ERRLOCN: Error Position within the set {sector area, spare area}. ERRLOCN points to 0 when the first bit of the main area is corrupted. If the sector size is set to 512 bytes, the ERRLOCN points to 4096 when the last bit of the sector area is corrupted. If the sector size is set to 1024 bytes, the ERRLOCN points to 8192 when the last bit of the sector area is corrupted. If the sector size is set to 512 bytes, the ERRLOCN points to 4097 when the first bit of the spare area is corrupted. If the sector size is set to 1024 bytes, the ERRLOCN points to 8193 when the first bit of the spare area is corrupted. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 – – ERRLOCN 76543210 ERRLOCN

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 30. Static Memory Controller (SMC)

30.1 Description

The Static Memory Controller (SMC) generates the signals that control the access to the exter- nal memory devices or peripheral devices. It has 6 Chip Selects and a 26-bit address bus. The 32-bit data bus can be configured to interface with 8-, 16-, or 32-bit external devices. Separate read and write control signals allow for direct memory and peripheral interfacing. Read and write signal waveforms are fully parametrizable. The SMC can manage wait requests from external devices to extend the current access. The SMC is provided with an automatic slow clock mode. In slow clock mode, it switches from user- programmed waveforms to slow-rate specific waveforms on read and write signals. The SMC supports asynchronous burst read in page mode access for page size up to 32 bytes.

30.2 Embedded Characteristics

  • 6 Chip Selects Available
  • 64-Mbyte Address Space per Chip Select
  • 8-, 16- or 32-bit Data Bus
  • Word, Halfword, Byte Transfers
  • Byte Write or Byte Select Lines
  • Programmable Setup, Pulse And Hold Time for Read Signals per Chip Select
  • Programmable Setup, Pulse And Hold Time for Write Signals per Chip Select
  • Programmable Data Float Time per Chip Select
  • Compliant with LCD Module
  • External Wait Request
  • Automatic Switch to Slow Clock Mode
  • Asynchronous Read in Page Mode Supported: Page Size Ranges from 4 to 32 Bytes

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

30.3 I/O Lines Description

30.4 Multiplexed Signals

Table 30-1. I/O Line Description Name Description Type Active Level NCS[5:0] Static Memory Controller Chip Select Lines Output Low NRD Read Signal Output Low NWR0/NWE Write 0/Write Enable Signal Output Low A0/NBS0 Address Bit 0/Byte 0 Select Signal Output Low NWR1/NBS1 Write 1/Byte 1 Select Signal Output Low A1/NWR2/NBS2 Address Bit 1/Write 2/Byte 2 Select Signal Output Low NWR3/NBS3 Write 3/Byte 3 Select Signal Output Low A[25:2] Address Bus Output D[31:0] Data Bus I/O NWAIT External Wait Signal Input Low Table 30-2. Static Memory Controller (SMC) Multiplexed Signals Multiplexed Signals Related Function NWR0 NWE Byte-write or byte-select access, see “Byte Write or Byte Select Access” on page 388 A0 NBS0 8-bit or 16-/32-bit data bus, see “Data Bus Width” on page 388 NWR1 NBS1 Byte-write or byte-select access see “Byte Write or Byte Select Access” on page 388 A1 NWR2 NBS2 8-/16-bit or 32-bit data bus, see “Data Bus Width” on page 388. Byte-write or byte-select access, see “Byte Write or Byte Select Access” on page 388 NWR3 NBS3 Byte-write or byte-select access see “Byte Write or Byte Select Access” on page 388

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

30.5 Application Example

30.5.1 Hardware Interface

Figure 30-1. SMC Connections to Static Memory Devices

30.6 Product Dependencies

30.6.1 I/O Lines

The pins used for interfacing the Static Memory Controller may be multiplexed with the PIO lines. The programmer must first program the PIO controller to assign the Static Memory Con- troller pins to their peripheral function. If I/O Lines of the SMC are not used by the application, they can be used for other purposes by the PIO Controller. Static Memory Controller D0-D31 A2 - A25 A0/NBS0 NWR0/NWE NWR1/NBS1 A1/NWR2/NBS2 NWR3/NBS3 128K x 8 SRAM D0 - D7 A0 - A16 OE WE CS D0 - D7 D8-D15 A2 - A18 128K x 8 SRAM D0-D7 CS D16 - D23 D24-D31 128K x 8 SRAM D0-D7 CS NWR1/NBS1 NWR3/NBS3 NRD NWR0/NWE 128K x 8 SRAM D0 - D7 OE WE CS NRD A1/NWR2/NBS2 NCS0 NCS1 NCS2 NCS3 NCS4 NCS5 NCS6 NCS7 A2 - A18A0 - A16 NRD OE WE OE WE NRD A2 - A18 A0 - A16 A2 - A18A0 - A16

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

30.7 External Memory Mapping

The SMC provides up to 26 address lines, A[25:0]. This allows each chip select line to address up to 64 Mbytes of memory. If the physical memory device connected on one chip select is smaller than 64 Mbytes, it wraps around and appears to be repeated within this space. The SMC correctly handles any valid access to the memory device within the page (see Figure 30-2). A[25:0] is only significant for 8-bit memory, A[25:1] is used for 16-bit memory, A[25:2] is used for 32-bit memory. Figure 30-2. Memory Connections for Eight External Devices

30.8 Connection to External Devices

30.8.1 Data Bus Width

A data bus width of 8, 16, or 32 bits can be selected for each chip select. This option is con- trolled by the field DBW in SMC_MODE (Mode Register) for the corresponding chip select. Figure 30-3 shows how to connect a 512K x 8-bit memory on NCS2. Figure 30-4 shows how to connect a 512K x 16-bit memory on NCS2. Figure 30-5 shows two 16-bit memories connected as a single 32-bit memory

30.8.2 Byte Write or Byte Select Access

Each chip select with a 16-bit or 32-bit data bus can operate with one of two different types of write access: byte write or byte select access . This is controlled by the BAT field of the SMC_MODE register for the corresponding chip select. NRD NWE A[25:0] D[31:0] 8 or 16 or 32 Memory Enable Memory Enable Memory Enable Memory Enable Memory Enable Memory Enable Memory Enable Memory Enable Output Enable Write Enable A[25:0] D[31:0] or D[15:0] or D[7:0] NCS3 NCS0 NCS1 NCS2 NCS7 NCS4 NCS5 NCS6 NCS[0] - NCS[7] SMC

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

30.8.2.1 Byte Write Access

Byte write access supports one byte write signal per byte of the data bus and a single read signal. Note that the SMC does not allow boot in Byte Write Access mode.

  • For 16-bit devices: the SMC provides NWR0 and NWR1 write signals for respectively byte0 (lower byte) and byte1 (upper byte) of a 16-bit bus. One single read signal (NRD) is provided. Byte Write Access is used to connect 2 x 8-bit devices as a 16-bit memory.
  • For 32-bit devices: NWR0, NWR1, NWR2 and NWR3, are the write signals of byte0 (lower byte), byte1, byte2 and byte 3 (upper byte) respectively. One single read signal (NRD) is provided. Byte Write Access is used to connect 4 x 8-bit devices as a 32-bit memory. Byte Write option is illustrated on Figure 30-6.

30.8.2.2 Byte Select Access

In this mode, read/write operations can be enabled/disabled at a byte level. One byte-select line per byte of the data bus is provided. One NRD and one NWE signal control read and write.

  • For 16-bit devices: the SMC provides NBS0 and NBS1 selection signals for respectively byte0 (lower byte) and byte1 (upper byte) of a 16-bit bus. Byte Select Access is used to connect one 16-bit device.
  • For 32-bit devices: NBS0, NBS1, NBS2 and NBS3, are the selection signals of byte0 (lower byte), byte1, byte2 and byte 3 (upper byte) respectively. Byte Select Access is used to connect two 16-bit devices. Figure 30-7 shows how to connect two 16-bit devices on a 32-bit data bus in Byte Select Access mode, on NCS3 (BAT = Byte Select Access).

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Figure 30-6. Connection of 2 x 8-bit Devices on a 16-bit Bus: Byte Write Option

30.8.2.3 Signal Multiplexing

Depending on the BAT, only the write signals or the byte select signals are used. To save IOs at the external bus interface, control signals at the SMC interface are multiplexed. Table 30-3 shows signal multiplexing depending on the data bus width and the byte access type. For 32-bit devices, bits A0 and A1 are unused. For 16-bit devices, bit A0 of address is unused. When Byte Select Option is selected, NWR1 to NWR3 are unused. When Byte Write option is selected, NBS0 to NBS3 are unused. SMC A1 NWR0 NRD NCS[3] Write Enable Read Enable Memory Enable NWR1 Write Enable Read Enable Memory Enable D[7:0] D[7:0] D[15:8] D[15:8] A[24:2] A[23:1] A[23:1] A[0] A[0]

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Figure 30-7. Connection of 2x16-bit Data Bus on a 32-bit Data Bus (Byte Select Option) SMC NWE NRD NCS[3] Write Enable Read Enable Memory Enable NBS0 D[15:0] D[15:0] D[31:16] A[25:2] A[23:0] Write Enable Read Enable Memory Enable D[31:16] A[23:0] Low Byte Enable High Byte Enable Low Byte Enable High Byte EnableNBS1 NBS2 NBS3 Table 30-3. SMC Multiplexed Signal Translation Signal Name 32-bit Bus 16-bit Bus 8-bit Bus Device Type 1x32-bit 2x16-bit 4 x 8- bit 1x16-bit 2 x 8-bit 1 x 8-bit Byte Access Type (BAT) Byte Select Byte Select Byte Write Byte Select Byte Write NBS0_A0 NBS0 NBS0 NBS0 A0 NWE_NWR0 NWE NWE NWR0 NWE NWR0 NWE NBS1_NWR1 NBS1 NBS1 NWR1 NBS1 NWR1 NBS2_NWR2_A1 NBS2 NBS2 NWR2 A1 A1 A1 NBS3_NWR3 NBS3 NBS3 NWR3

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

30.9 Standard Read and Write Protocols

In the following sections, the byte access type is not considered. Byte select lines (NBS0 to NBS3) always have the same timing as the A address bus. NWE represents either the NWE sig- nal in byte select access type or one of the byte write lines (NWR0 to NWR3) in byte write access type. NWR0 to NWR3 have the same timings and protocol as NWE. In the same way, NCS represents one of the NCS[0..5] chip select lines.

30.9.1 Read Waveforms

The read cycle is shown on Figure 30-8. The read cycle starts with the address setting on the memory address bus, i.e.: {A[25:2], A1, A0} for 8-bit devices {A[25:2], A1} for 16-bit devices A[25:2] for 32-bit devices. Figure 30-8. Standard Read Cycle

30.9.1.1 NRD Waveform

The NRD signal is characterized by a setup timing, a pulse width and a hold timing. 1. NRD_SETUP: the NRD setup time is defined as the setup of address before the NRD falling edge; 2. NRD_PULSE: the NRD pulse length is the time between NRD falling edge and NRD rising edge; 3. NRD_HOLD: the NRD hold time is defined as the hold time of address after the NRD rising edge. A[25:2] NBS0,NBS1, NBS2,NBS3, A0, A1 NCS NRD_SETUP NRD_PULSE NRD_HOLD MCK NRD D[31:0] NCS_RD_SETUP NCS_RD_PULSE NCS_RD_HOLD NRD_CYCLE

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

30.9.1.2 NCS Waveform

Similarly, the NCS signal can be divided into a setup time, pulse length and hold time: 1. NCS_RD_SETUP: the NCS setup time is defined as the setup time of address before the NCS falling edge. 2. NCS_RD_PULSE: the NCS pulse length is the time between NCS falling edge and NCS rising edge; 3. NCS_RD_HOLD: the NCS hold time is defined as the hold time of address after the NCS rising edge.

30.9.1.3 Read Cycle

The NRD_CYCLE time is defined as the total duration of the read cycle, i.e., from the time where address is set on the address bus to the point where address may change. The total read cycle time is equal to: NRD_CYCLE = NRD_SETUP + NRD_PULSE + NRD_HOLD = NCS_RD_SETUP + NCS_RD_PULSE + NCS_RD_HOLD All NRD and NCS timings are defined separately for each chip select as an integer number of Master Clock cycles. To ensure that the NRD and NCS timings are coherent, user must define the total read cycle instead of the hold timing. NRD_CYCLE implicitly defines the NRD hold time and NCS hold time as: NRD_HOLD = NRD_CYCLE - NRD SETUP - NRD PULSE NCS_RD_HOLD = NRD_CYCLE - NCS_RD_SETUP - NCS_RD_PULSE

30.9.1.4 Null Delay Setup and Hold

If null setup and hold parame ters are programmed for NRD and/or NCS, NRD and NCS remain active continuously in case of consecutive read cycles in the same memory (see Figure 30-9).

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Figure 30-9. No Setup, No Hold On NRD and NCS Read Signals

30.9.1.5 Null Pulse

Programming null pulse is not permitted. Pulse must be at least set to 1. A null value leads to unpredictable behavior.

30.9.2 Read Mode

As NCS and NRD waveforms are defined independently of one other, the SMC needs to know when the read data is available on the data bus. The SMC does not compare NCS and NRD tim- ings to know which signal rises first. The R EAD_MODE parameter in the SMC_MODE register of the corresponding chip select indicates wh ich signal of NRD and NCS controls the read operation.

30.9.2.1 Read is Controlled by NRD (READ_MODE = 1):

Figure 30-10 shows the waveforms of a read operation of a typical asynchronous RAM. The read data is available tPACC after the falling edge of NRD, and turns to ‘Z’ after the rising edge of NRD. In this case, the READ_MODE must be set to 1 (read is controlled by NRD), to indicate that data is available with the rising edge of NRD. The SMC samples the read data internally on the rising edge of Master Clock that generates the rising edge of NRD, whatever the pro- grammed waveform of NCS may be. MCK NRD_PULSE NCS_RD_PULSE NRD_CYCLE NRD_PULSE NRD_PULSE NCS_RD_PULSE NCS_RD_PULSE NRD_CYCLE NRD_CYCLE A[25:2] NBS0,NBS1, NBS2,NBS3, A0, A1 NCS NRD D[31:0]

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Figure 30-10. READ_MODE = 1: Data is sampled by SMC before the rising edge of NRD

30.9.2.2 Read is Controlled by NCS (READ_MODE = 0)

Figure 30-11 shows the typical read cycle of an LCD module. The read data is valid t PACC after the falling edge of the NCS signal and remains va lid until the rising edge of NCS. Data must be sampled when NCS is raised. In that case, the READ_MODE must be set to 0 (read is controlled by NCS): the SMC internally samples the data on the rising edge of Master Clock that generates the rising edge of NCS, whatever the programmed waveform of NRD may be. Figure 30-11. READ_MODE = 0: Data is sampled by SMC before the rising edge of NCS Data Sampling tPACC MCK A[25:2] NBS0,NBS1, NBS2,NBS3, A0, A1 NCS NRDD[31:0] Data Sampling tPACC MCK D[31:0] A[25:2] NBS0,NBS1, NBS2,NBS3, A0, A1 NCS NRD

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

30.9.3 Write Waveforms

The write protocol is similar to the read protocol. It is depicted in Figure 30-12. The write cycle starts with the address setting on the memory address bus.

30.9.3.1 NWE Waveforms

The NWE signal is characterized by a setup timing, a pulse width and a hold timing. 1. NWE_SETUP: the NWE setup time is defined as the setup of address and data before the NWE falling edge; 2. NWE_PULSE: The NWE pulse length is the time between NWE falling edge and NWE rising edge; 3. NWE_HOLD: The NWE hold time is defined as the hold time of address and data after the NWE rising edge. The NWE waveforms apply to all byte-write lines in Byte Write access mode: NWR0 to NWR3.

30.9.3.2 NCS Waveforms

The NCS signal waveforms in write operation are not the same that those applied in read opera- tions, but are separately defined: 1. NCS_WR_SETUP: the NCS setup time is defined as the setup time of address before the NCS falling edge. 2. NCS_WR_PULSE: the NCS pulse length is the time between NCS falling edge and NCS rising edge; 3. NCS_WR_HOLD: the NCS hold time is defined as the hold time of address after the NCS rising edge. Figure 30-12. Write Cycle A[25:2] NBS0, NBS1, NBS2, NBS3, A0, A1 NCS NWE_SETUP NWE_PULSE NWE_HOLD MCK NWE NCS_WR_SETUP NCS_WR_PULSE NCS_WR_HOLD NWE_CYCLE

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

30.9.3.3 Write Cycle

The write_cycle time is defined as the total durat ion of the write cycle, that is, from the time where address is set on the address bus to the point where address may change. The total write cycle time is equal to: NWE_CYCLE = NWE_SETUP + NWE_PULSE + NWE_HOLD = NCS_WR_SETUP + NCS_WR_PULSE + NCS_WR_HOLD All NWE and NCS (write) timings are defined separately for each chip select as an integer num- ber of Master Clock cycles. To ensure that the NWE and NCS timings are coherent, the user must define the total wr ite cycle instead of the hold timing. This implicitly defines the NWE hold time and NCS (write) hold times as: NWE_HOLD = NWE_CYCLE - NWE_SETUP - NWE_PULSE NCS_WR_HOLD = NWE_CYCLE - NCS_WR_SETUP - NCS_WR_PULSE

30.9.3.4 Null Delay Setup and Hold

If null setup parameters are programmed for NWE and/or NCS, NWE and/or NCS remain active continuously in case of consecutive write cycles in the same memory (see Figure 30-13). How- ever, for devices that perform write operations on the rising edge of NWE or NCS, such as SRAM, either a setup or a hold must be programmed. Figure 30-13. Null Setup and Hold Values of NCS and NWE in Write Cycle

30.9.3.5 Null Pulse

Programming null pulse is not permitted. Pulse must be at least set to 1. A null value leads to unpredictable behavior. NCS MCK NWE, NWR0, NWR1, NWR2, NWR3 D[31:0] NWE_PULSE NCS_WR_PULSE NWE_CYCLE NWE_PULSE NCS_WR_PULSE NWE_CYCLE NWE_PULSE NCS_WR_PULSE NWE_CYCLE A[25:2] NBS0, NBS1, NBS2, NBS3, A0, A1

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

30.9.4 Write Mode

The WRITE_MODE parameter in the SMC_MODE register of the corresponding chip select indi- cates which signal controls the write operation.

30.9.4.1 Write is Controlled by NWE (WRITE_MODE = 1):

Figure 30-14 shows the waveforms of a write operation with WRITE_MODE set to 1. The data is put on the bus during the pulse and hold steps of the NWE signal. The internal data buffers are turned out after the NWE_SETUP time, and until the end of the write cycle, regardless of the programmed waveform on NCS. Figure 30-14. WRITE_MODE = 1. The write operation is controlled by NWE

30.9.4.2 Write is Controlled by NCS (WRITE_MODE = 0)

Figure 30-15 shows the waveforms of a write operation with WRITE_MODE set to 0. The data is put on the bus during the pulse and hold steps of the NCS signal. The internal data buffers are turned out after the NCS_WR_SETUP time, and until the end of the write cycle, regardless of the programmed waveform on NWE. MCK D[31:0] NCS A[25:2] NBS0, NBS1, NBS2, NBS3, A0, A1 NWE, NWR0, NWR1, NWR2, NWR3

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Figure 30-15. WRITE_MODE = 0. The write operation is controlled by NCS

30.9.5 Write Protected Registers

To prevent any single software error that may corrupt SMC behavior, the registers listed below can be write-protected by setting the WPEN bit in the SMC Write Protect Mode Register (SMC_WPMR). If a write access in a write-protected register is detected, then the WPVS flag in the SMC Write Protect Status Register (SMC_WPSR) is set and the field WPVSRC indicates in which register the write access has been attempted. The WPVS flag is automatically reset after reading the SMC Write Protect Status Register (SMC_WPSR). List of the write-protected registers:

  • Section 30.16.1 ”SMC Setup Register”
  • Section 30.16.2 ”SMC Pulse Register”
  • Section 30.16.3 ”SMC Cycle Register”
  • Section 30.16.4 ”SMC MODE Register”
  • Section 30.16.5 ”SMC DELAY I/O Register”

30.9.6 Coding Timing Parameters

All timing parameters are defined for one chip select and are grouped together in one SMC_REGISTER according to their type. The SMC_SETUP register groups the definition of all setup parameters:

  • NRD_SETUP, NCS_RD_SETUP, NWE_SETUP, NCS_WR_SETUP The SMC_PULSE register groups the definition of all pulse parameters:
  • NRD_PULSE, NCS_RD_PULSE, NWE_PULSE, NCS_WR_PULSE The SMC_CYCLE register groups the definition of all cycle parameters:
  • NRD_CYCLE, NWE_CYCLE MCK D[31:0] NCS NWE, NWR0, NWR1, NWR2, NWR3 A[25:2] NBS0, NBS1, NBS2, NBS3, A0, A1

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Table 30-4 shows how the timing parameters are coded and their permitted range.

30.9.7 Reset Values of Timing Parameters

Table 30-8, “Register Mapping,” on page 422 gives the default value of timing parameters at reset.

30.9.8 Usage Restriction

The SMC does not check the validity of the user-programmed parameters. If the sum of SETUP and PULSE parameters is larger than the corresponding CYCLE parameter, this leads to unpre- dictable behavior of the SMC. For read operations: Null but positive setup and hold of address and NRD and/or NCS can not be guaranteed at the memory interface because of the propagation delay of theses signals through external logic and pads. If positive setup and hold values must be verified, then it is strictly recommended to pro- gram non-null values so as to cover possible skews between address, NCS and NRD signals. For write operations: If a null hold value is programmed on NWE, the SMC can guarantee a positive hold of address, byte select lines, and NCS signal after the rising edge of NWE. This is true for WRITE_MODE = 1 only. See “Early Read Wait State” on page 402. For read and write operations: a null value for pulse parameters is forbidden and may lead to unpredictable behavior. In read and write cycles, the setup and hold time parameters are defined in reference to the address bus. For external devices that require setup and hold time between NCS and NRD sig- nals (read), or between NCS and NWE signals (write), these setup and hold times must be converted into setup and hold times in reference to the address bus.

30.10 Automatic Wait States

Under certain circumstances, the SMC automatica lly inserts idle cycles between accesses to avoid bus contention or operation conflict.

30.10.1 Chip Select Wait States

The SMC always inserts an idle cycle between 2 transfers on separate chip selects. This idle cycle ensures that there is no bus contention between the de-activation of one device and the activation of the next one. During chip select wait state, all control lines are turned inactive: NBS0 to NBS3, NWR0 to NWR3, NCS[0..5], NRD lines are all set to 1. Table 30-4. Coding and Range of Timing Parameters Coded Value Number of Bits Effective Value Permitted Range Coded Value Effective Value setup [5:0] 6 128 x setup[5] + setup[4:0] 0 ≤ ≤ 31 0 ≤ ≤ 128+31 pulse [6:0] 7 256 x pulse[6] + pulse[5:0] 0 ≤ ≤ 63 0 ≤ ≤ 256+63 cycle [8:0] 9 256 x cycle[8:7] + cycle[6:0] 0 ≤ ≤ 127 0 ≤ ≤ 256+127 0 ≤ ≤ 512+127 0 ≤ ≤ 768+127

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Figure 30-16 illustrates a chip select wait state between access on Chip Select 0 and Chip Select 2. Figure 30-16. Chip Select Wait State between a Read Access on NCS0 and a Write Access on NCS2

30.10.2 Early Read Wait State

In some cases, the SMC inserts a wait state cycle between a write access and a read access to allow time for the write cycle to end before the subsequent read cycle begins. This wait state is not generated in addition to a chip select wait state. The early read cycle thus only occurs between a write and read access to the same memory device (same chip select). An early read wait state is automatically inserted if at least one of the following conditions is valid:

  • if the write controlling signal has no hold time and the read controlling signal has no setup time (Figure 30-17).
  • in NCS write controlled mode (WRITE_MODE = 0), if there is no hold timing on the NCS signal and the NCS_RD_SETUP parameter is set to 0, regardless of the read mode (Figure 30-18). The write operation must end with a NCS rising edge. Without an Early Read Wait State, the write operation could not complete properly.
  • in NWE controlled mode (WRITE_MODE = 1) and if there is no hold timing (NWE_HOLD = 0), the feedback of the write control signal is used to control address, data, chip select and byte select lines. If the external write control signal is not inactivated as expected due to load capacitances, an Early Read Wait State is inserted and address, data and control signals are maintained one more cycle. See Figure 30-19. A[25:2] NBS0, NBS1, NBS2, NBS3, A0,A1 NCS0 NRD_CYCLE Chip Select Wait State NWE_CYCLE MCK NCS2 NRD NWE D[31:0] Read to Write Wait State

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Figure 30-19. Early Read Wait State: NWE-controlled Write with No Hold Followed by a Read with one Set-up Cycle

30.10.3 Reload User Configuration Wait State

The user may change any of the configuration parameters by writing the SMC user interface. When detecting that a new user configuration has been written in the user interface, the SMC inserts a wait state before starting the next access. The so called “Reload User Configuration Wait State” is used by the SMC to load the new set of parameters to apply to next accesses. The Reload Configuration Wait State is not applied in addition to the Chip Select Wait State. If accesses before and after re-programming the user interface are made to different devices (Chip Selects), then one single Chip Select Wait State is applied. On the other hand, if accesses before and after writing the user interface are made to the same device, a Reload Configuration Wait State is inserted, even if the change does not concern the current Chip Select.

30.10.3.1 User Procedure

To insert a Reload Configuration Wait State, the SMC detects a write access to any SMC_MODE register of the user interface. If the user only modifies timing registers (SMC_SETUP, SMC_PULSE, SMC_CYCLE registers) in the user interface, he must validate the modification by writing the SMC_MODE, even if no change was made on the mode parameters. The user must not change the configuration parameters of an SMC Chip Select (Setup, Pulse, Cycle, Mode) if accesses are performed on this CS during the modification. Any change of the Chip Select parameters, while fetching the code from a memory connected on this CS, may lead A[25:2] NBS0, NBS1, NBS2, NBS3, A0, A1 write cycle (WRITE_MODE = 1) Early Read wait state MCK NRD internal write controlling signal external write controlling signal (NWE) D[31:0] read cycle (READ_MODE = 0 or READ_MODE = 1) no hold read setup = 1

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 to unpredictable behavior. The instructions used to modify the parameters of an SMC Chip Select can be executed from the internal RAM or from a memory connected to another CS.

30.10.3.2 Slow Clock Mode Transition

A Reload Configuration Wait State is also inserted when the Slow Clock Mode is entered or exited, after the end of the current transfer (see “Slow Clock Mode” on page 415).

30.10.4 Read to Write Wait State

Due to an internal mechanism, a wait cycle is always inserted between consecutive read and write SMC accesses. This wait cycle is referred to as a read to write wait state in this document. This wait cycle is applied in add ition to chip select and reload user configuration wait states when they are to be inserted. See Figure 30-16 on page 402.

30.11 Data Float Wait States

Some memory devices are slow to release the external bus. For such devices, it is necessary to add wait states (data float wait states) after a read access:

  • before starting a read access to a different external memory
  • before starting a write access to the same device or to a different external one. The Data Float Output Time (t DF) for each external memory device is programmed in the TDF_CYCLES field of the SMC_MODE register for the corresponding chip select. The value of TDF_CYCLES indicates the number of data float wait cycles (between 0 and 15) before the external device releases the bus, and represents the time allowed for the data output to go to high impedance after the memory is disabled. Data float wait states do not delay internal memory accesses. Hence, a single access to an external memory with long t DF will not slow down the executio n of a program from internal memory. The data float wait states management depends on the READ_MODE and the TDF_MODE fields of the SMC_MODE register for the corresponding chip select.

30.11.1 READ_MODE

Setting the READ_MODE to 1 indicates to the SMC that the NRD signal is responsible for turn- ing off the tri-state buffers of the external memory device. The Data Float Period then begins after the rising edge of the NRD signal and lasts TDF_CYCLES MCK cycles. When the read operation is controlled by the NCS signal (READ_MODE = 0), the TDF field gives the number of MCK cycles during which the data bus remains busy after the rising edge of NCS. Figure 30-20 illustrates the Data Float Period in NRD-controlled mode (READ_MODE =1), assuming a data float period of 2 cycles (TDF_CYCLES = 2). Figure 30-21 shows the read oper- ation when controlled by NCS (READ_MODE = 0) and the TDF_CYCLES parameter equals 3.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

30.11.2 TDF Optimization Enabled (TDF_MODE = 1)

When the TDF_MODE of the SMC_MODE register is set to 1 (TDF optimization is enabled), the SMC takes advantage of the setup period of the next access to optimize the number of wait states cycle to insert. Figure 30-22 shows a read access controlled by NRD, followed by a write access controlled by NWE, on Chip Select 0. Chip Select 0 has been programmed with: NRD_HOLD = 4; READ_MODE = 1 (NRD controlled) NWE_SETUP = 3; WRITE_MODE = 1 (NWE controlled) TDF_CYCLES = 6; TDF_MODE = 1 (optimization enabled). Figure 30-22. TDF Optimization: No TDF wait states are inserted if the TDF period is over when the next access begins

30.11.3 TDF Optimization Disabled (TDF_MODE = 0)

When optimization is disabled, tdf wait states are inserted at the end of the read transfer, so that the data float period is ended when the second access begins. If the hold period of the read1 controlling signal overlaps the data float period, no additional tdf wait states will be inserted. Figure 30-23, Figure 30-24 and Figure 30-25 illustrate the cases:

  • read access followed by a read access on another chip select,
  • read access followed by a write access on another chip select,
  • read access followed by a write access on the same chip select, with no TDF optimization. A[25:2] NCS0 MCK NRD NWE D[31:0] Read to Write Wait State TDF_CYCLES = 6 read access on NCS0 (NRD controlled) NRD_HOLD= 4 NWE_SETUP= 3 write access on NCS0 (NWE controlled)

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Figure 30-23. TDF Optimization Disabled (TDF Mode = 0). TDF wait states between 2 read accesses on different chip selects Figure 30-24. TDF Mode = 0: TDF wait states between a read and a write access on different chip selects TDF_CYCLES = 6 TDF_CYCLES = 6 TDF_MODE = 0 (optimization disabled) A[25:2] read1 cycle Chip Select Wait State MCK read1 controlling signal (NRD) read2 controlling signal (NRD) D[31:0] read1 hold = 1 read 2 cycle read2 setup = 1

5 TDF WAIT STATES

NBS0, NBS1, NBS2, NBS3, A0, A1 TDF_CYCLES = 4 TDF_CYCLES = 4 TDF_MODE = 0 (optimization disabled) A[25:2] read1 cycle Chip Select Wait State Read to Write Wait State MCK read1 controlling signal (NRD) write2 controlling signal (NWE) D[31:0] read1 hold = 1 write2 cycle write2 setup = 1

2 TDF WAIT STATES

NBS0, NBS1, NBS2, NBS3, A0, A1

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Figure 30-25. TDF Mode = 0: TDF wait states between read and write accesses on the same chip select

30.12 External Wait

Any access can be extended by an external device using the NWAIT input signal of the SMC. The EXNW_MODE field of the SMC_MODE register on the corresponding chip select must be set to either to “10” (frozen mode) or “11” (ready mode). When the EXNW_MODE is set to “00” (disabled), the NWAIT signal is simply ignored on the correspo nding chip select. The NWAIT signal delays the read or write operation in regards to the read or write controlling signal, depending on the read and write modes of the corresponding chip select.

30.12.1 Restriction

When one of the EXNW_MODE is enabled, it is mandatory to program at least one hold cycle for the read/write controlling signal. For that reason, the NWAIT signal cannot be used in Page Mode ( “Asynchronous Page Mode” on page 418 ), or in Slow Clock Mode (“Slow Clock Mode” on page 415). The NWAIT signal is assumed to be a response of the external device to the read/write request of the SMC. Then NWAIT is examined by the SMC only in the pulse state of the read or write controlling signal. The assertion of the NWAIT signal outside the expected period has no impact on SMC behavior. TDF_CYCLES = 5 TDF_CYCLES = 5 TDF_MODE = 0 (optimization disabled) A[25:2] read1 cycle Read to Write Wait State MCK read1 controlling signal (NRD) write2 controlling signal (NWE) D[31:0] read1 hold = 1 write2 cycle write2 setup = 1

4 TDF WAIT STATES

NBS0, NBS1, NBS2, NBS3, A0, A1

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

30.12.2 Frozen Mode

When the external device asserts the NWAIT signal (active low), and after internal synchroniza- tion of this signal, the SMC state is frozen, i.e., SMC internal counters are frozen, and all control signals remain unchanged. When the resynchronized NWAIT signal is deasserted, the SMC completes the access, resuming the access from the point where it was stopped. See Figure 30- 26. This mode must be selected when the external device uses the NWAIT signal to delay the access and to freeze the SMC. The assertion of the NWAIT signal outside the expected period is ignored as illustrated in Figure 30-27. Figure 30-26. Write Access with NWAIT Assertion in Frozen Mode (EXNW_MODE = 10) EXNW_MODE = 10 (Frozen) WRITE_MODE = 1 (NWE_controlled) NWE_PULSE = 5 NCS_WR_PULSE = 7 A[25:2] MCK NWE NCS 43 2 1 1 101 4563 2 2 2 2 1 0 Write cycle D[31:0] NWAIT FROZEN STATE NBS0, NBS1, NBS2, NBS3, A0,A1 internally synchronized NWAIT signal

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Figure 30-27. Read Access with NWAIT Assertion in Frozen Mode (EXNW_MODE = 10) EXNW_MODE = 10 (Frozen) READ_MODE = 0 (NCS_controlled) NRD_PULSE = 2, NRD_HOLD = 6 NCS_RD_PULSE =5, NCS_RD_HOLD =3 A[25:2] MCK NCS NRD 55 5 22 0 21 0 21 0 Read cycle Assertion is ignored NWAIT internally synchronized NWAIT signal FROZEN STATE NBS0, NBS1, NBS2, NBS3, A0,A1

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

30.12.3 Ready Mode

In Ready mode (EXNW_MODE = 11), the SMC behaves differently. Normally, the SMC begins the access by down counting the setup and pulse counters of the read/write controlling signal. In the last cycle of the pulse phase, the resynchronized NWAIT signal is examined. If asserted, the SMC suspends the access as shown in Figure 30-28 and Figure 30-29 . After deassertion, the access is completed: the hold step of the access is performed. This mode must be selected when the external de vice uses deassertion of the NWAIT signal to indicate its ability to complete the read or write operation. If the NWAIT signal is deasserted before the end of the pulse, or asserted after the end of the pulse of the controlling read/write signal, it has no impact on the access length as shown in Fig- ure 30-29. Figure 30-28. NWAIT Assertion in Write Access: Ready Mode (EXNW_MODE = 11) EXNW_MODE = 11 (Ready mode) WRITE_MODE = 1 (NWE_controlled) NWE_PULSE = 5 NCS_WR_PULSE = 7 A[25:2] MCK NWE NCS 43 2 1 0 00 4563 2 1 1 1 0 Write cycle D[31:0] NWAIT internally synchronized NWAIT signal Wait STATE NBS0, NBS1, NBS2, NBS3, A0,A1

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Figure 30-29. NWAIT Assertion in Read Access: Ready Mode (EXNW_MODE = 11) EXNW_MODE = 11(Ready mode) READ_MODE = 0 (NCS_controlled) NRD_PULSE = 7 NCS_RD_PULSE =7 A[25:2] MCK NCS NRD 4563 2 0 0 4563 2 11 Read cycle Assertion is ignored NWAIT internally synchronized NWAIT signal Wait STATE Assertion is ignored NBS0, NBS1, NBS2, NBS3, A0,A1

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

30.12.4 NWAIT Latency and Read/Write Timings

There may be a latency between the assertion of the read/write controlling signal and the asser- tion of the NWAIT signal by the device. T he programmed pulse length of the read/write controlling signal must be at least equal to this latency plus the 2 cycles of resynchronization + 1 cycle. Otherwise, the SMC may enter the hold state of the access without detecting the NWAIT signal assertion. This is true in frozen mode as well as in ready mode. This is illustrated on Figure 30-30. When EXNW_MODE is enabled (ready or frozen), th e user must program a pulse length of the read and write controlling signal of at least: minimal pulse length = NWAIT latency + 2 resynchronization cycles + 1 cycle Figure 30-30. NWAIT Latency EXNW_MODE = 10 or 11 READ_MODE = 1 (NRD_controlled) NRD_PULSE = 5 A[25:2] MCK NRD 43 21 0 0 0 Read cycle minimal pulse length NWAIT latency NWAIT intenally synchronized NWAIT signal WAIT STATE 2 cycle resynchronization NBS0, NBS1, NBS2, NBS3, A0,A1

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

30.13 Slow Clock Mode

The SMC is able to automatically apply a set of “slow clock mode” read/write waveforms when an internal signal driven by the Power Management Controller is asserted because MCK has been turned to a very slow clock rate (typically 32kHz clock rate). In this mode, the user-pro- grammed waveforms are ignored and the slow clock mode waveforms are applied. This mode is provided so as to avoid reprogramming the User Interface with appropriate waveforms at very slow clock rate. When activated, the slow mode is active on all chip selects.

30.13.1 Slow Clock Mode Waveforms

Figure 30-31 illustrates the read and write operations in slow clock mode. They are valid on all chip selects. Table 30-5 indicates the value of read and write parameters in slow clock mode. Figure 30-31. Read/write Cycles in Slow Clock Mode A[25:2] NCS MCK NWE 1 NWE_CYCLE = 3 A[25:2] MCK NRD NRD_CYCLE = 2 NCS SLOW CLOCK MODE WRITE SLOW CLOCK MODE READ NBS0, NBS1, NBS2, NBS3, A0,A1 NBS0, NBS1, NBS2, NBS3, A0,A1 Table 30-5. Read and Write Timing Parameters in Slow Clock Mode Read Parameters Duration (cycles) Write Parameters Duration (cycles) NRD_SETUP 1 NWE_SETUP 1 NRD_PULSE 1 NWE_PULSE 1 NCS_RD_SETUP 0 NCS_WR_SETUP 0 NCS_RD_PULSE 2 NCS_WR_PULSE 3 NRD_CYCLE 2 NWE_CYCLE 3

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

30.13.2 Switching from (to) Slow Clock Mode to (from) Normal Mode

When switching from slow clock mode to the normal mode, the current slow clock mode transfer is completed at high clock rate, with the set of slow clock mode parameters.See Figure 30-32 on page 416. The external device may not be fast enough to support such timings. Figure 30-33 illustrates the recommended procedure to properly switch from one mode to the other. Figure 30-32. Clock Rate Transition Occurs while the SMC is Performing a Write Operation A[25:2] NCS MCK NWE NWE_CYCLE = 3 SLOW CLOCK MODE WRITE Slow Clock Mode internal signal from PMC 11 1 2 3 2 NWE_CYCLE = 7 NORMAL MODE WRITE Slow clock mode transition is detected: Reload Configuration Wait State This write cycle finishes with the slow clock mode set of parameters after the clock rate transition SLOW CLOCK MODE WRITE NBS0, NBS1, NBS2, NBS3, A0,A1

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Figure 30-33. Recommended Procedure to Switch from Slow Clock Mode to Normal Mode or from Normal Mode to Slow Clock Mode A[25:2] NCS MCK NWE SLOW CLOCK MODE WRITE Slow Clock Mode internal signal from PMC 2 3 2 NORMAL MODE WRITEIDLE STATE Reload Configuration Wait State NBS0, NBS1, NBS2, NBS3, A0,A1

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

30.14 Asynchronous Page Mode

The SMC supports asynchronous burst reads in page mode, providing that the page mode is enabled in the SMC_MODE register (PMEN field). The page size must be configured in the SMC_MODE register (PS field) to 4, 8, 16 or 32 bytes. The page defines a set of consecutive bytes into memory. A 4-byte page (resp. 8-, 16-, 32-byte page) is always aligned to 4-byte boundaries (resp. 8-, 16-, 32-byte boundaries) of memory. The MSB of data address defines the address of the page in memory, the LSB of address define the address of the data in the page as detailed in Table 30-6. With page mode memory devices, the first access to one page (t pa) takes longer than the subse- quent accesses to the page (t sa) as shown in Figure 30-34. When in page mode, the SMC enables the user to define different read timings for the first access within one page, and next accesses within the page. Notes: 1. A denotes the address bus of the memory device 2. For 16-bit devices, the bit 0 of address is ignored. For 32-bit devices, bits [1:0] are ignored.

30.14.1 Protocol and Timings in Page Mode

Figure 30-34 shows the NRD and NCS timings in page mode access. Figure 30-34. Page Mode Read Protocol (Address MSB and LSB are defined in Table 30-6) The NRD and NCS signals are held low during all read transfers, whatever the programmed val- ues of the setup and hold timings in the Us er Interface may be. Moreover, the NRD and NCS Table 30-6. Page Address and Data Address within a Page Page Size Page Address (1) Data Address in the Page(2) 4 bytes A[25:2] A[1:0] 8 bytes A[25:3] A[2:0] 16 bytes A[25:4] A[3:0] 32 bytes A[25:5] A[4:0] A[MSB] NCS MCK NRD D[31:0] NCS_RD_PULSE NRD_PULSENRD_PULSE tsatpa tsa A[LSB]

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 timings are identical. The pulse length of the first access to the page is defined with the NCS_RD_PULSE field of the SMC_PULSE register. The pulse length of subsequent accesses within the page are defined using the NRD_PULSE parameter. In page mode, the programming of the read timings is described in Table 30-7: The SMC does not check the coherency of timings. It will always apply the NCS_RD_PULSE timings as page access timing (t pa) and the NRD_PULSE for accesses to the page (t sa), even if the programmed value for tpa is shorter than the programmed value for tsa.

30.14.2 Byte Access Type in Page Mode

The Byte Access Type configuration remains active in page mode. For 16-bit or 32-bit page mode devices that require byte selection signals, configure the BAT field of the SMC_REGISTER to 0 (byte select access type).

30.14.3 Page Mode Restriction

The page mode is not compatible with the use of the NWAIT signal. Using the page mode and the NWAIT signal may lead to unpredictable behavior.

30.14.4 Sequential and Non-sequential Accesses

If the chip select and the MSB of addresses as defined in Table 30-6 are identical, then the cur- rent access lies in the same page as the previous one, and no page break occurs. Using this information, all data within the same page, sequential or not sequential, are accessed with a minimum access time (t sa). Figure 30-35 illustrates access to an 8-bit memory device in page mode, with 8-byte pages. Access to D1 causes a page access with a long access time pa). Accesses to D3 and D7, though they are not sequential accesses, only require a short access time (tsa). If the MSB of addresses are different, the SMC performs the access of a new page. In the same way, if the chip select is different from the previous access, a page break occurs. If two sequen- tial accesses are made to the page mode memory, but separated by an other internal or external peripheral access, a page break occurs on the second access because the chip select of the device was deasserted between both accesses. Table 30-7. Programming of Read Timings in Page Mode Parameter Value Definition READ_MODE ‘x’ No impact NCS_RD_SETUP ‘x’ No impact NCS_RD_PULSE t pa Access time of first access to the page NRD_SETUP ‘x’ No impact NRD_PULSE t sa Access time of subsequent accesses in the page NRD_CYCLE ‘x’ No impact

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Figure 30-35. Access to Non-sequential Data within the Same Page A[25:3] A[2], A1, A0 NCS MCK NRD Page address A1 A3 A7 D[7:0] NCS_RD_PULSE NRD_PULSENRD_PULSE D1 D3 D7

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

30.15 Programmable IO Delays

The external bus interface consists of a data bus, an address bus and control signals. The simul- taneous switching outputs on these busses may lead to a peak of current in the internal and external power supply lines. In order to reduce the peak of current in such cases, additional propagation delays can be adjusted independently for pad buffers by means of configuration registers, SMC_DELAY1-8. The additional programmable delays for each IO range from 0 to 4 ns (Worst Case PVT). The delay can differ between IOs supporting this feature. Delay can be modified per programming for each IO. The minimal additional delay that can be programmed on a PAD supporting this feature is 1/16 of the maximum programmable delay. When programming 0x0 in fields “Delay1 to De lay 8”, no delay is added (reset value) and the propagation delay of the pad buffers is the inherent delay of the pad buffer. When programming 0xF in field “Delay1” the propagation delay of the corresponding pad is maximal. SMC_DELAY1, SMC_DELAY2 allow to configur e delay on D[15:0], SMC_DELAY1[3:0] corre- sponds to D[0] and SMC_DELAY2[3:0] corresponds to D[8]. SMC_DELAY3, SMC_DELAY4 allow to configure delay on D[31:16], SMC_DELAY3[3:0] corre- sponds to D[16] and SMC_DELAY4[3:0] corresponds to D[24]. In case of multiplexing through the PIO controller, refer to the alternate function of D[31:16]. SMC_DELAY5, 6, 7 and 8 allow to configure delay on A[25:0], SMC_DELAY5[3:0] corresponds to A[0]. In case of multiplexing through the PIO controller, refer to the alternate function of A[25:0]. Figure 30-36. Programmable IO Delays DELAY1 D[0]Programmable Delay Line SMC D_out[0] D_in[0] DELAY2 D[1]Programmable Delay LineD_out[1] D_in[1] DELAYx D[n]Programmable Delay LineD_out[n] D_in[n] PIO A[m]Programmable Delay Line PIO DELAYy A[m]

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

30.16 Static Memory Contro ller (SMC) User Interface

The SMC is programmed using the registers listed in Table 30-8. For each chip select, a set of 4 registers is used to pro- gram the parameters of the exter nal device connected on it. In Table 30-8, “CS_number” denotes the chip select number. 16 bytes (0x10) are required per chip select. The user must complete writing the configuration by writing any one of the SMC_MODE registers. Table 30-8. Register Mapping Offset Register Name Access Reset 0x10 x CS_number + 0x00 SMC Setup Register SMC_SETUP Read-write 0x00000000 0x10 x CS_number + 0x04 SMC Pulse Register SMC_PULSE Read-write 0x01010101 0x10 x CS_number + 0x08 SMC Cycle Register SMC_CYCLE Read-write 0x00030003 0x10 x CS_number + 0x0C SMC Mode Register SMC_MODE Read-write 0x10001000 0xC0 SMC Delay on I/O SMC_DELAY1 Read-write 0x00000000 0xC4 SMC Delay on I/O SMC_DELAY2 Read-write 0x00000000 0xC8 SMC Delay on I/O SMC_DELAY3 Read-write 0x00000000 0xCC SMC Delay on I/O SMC_DELAY4 Read-write 0x00000000 0xD0 SMC Delay on I/O SMC_DELAY5 Read-write 0x00000000 0xD4 SMC Delay on I/O SMC_DELAY6 Read-write 0x00000000 0xD8 SMC Delay on I/O SMC_DELAY7 Read-write 0x00000000 0xDC SMC Delay on I/O SMC_DELAY8 Read-write 0x00000000 0xE4 SMC Write Protect Mode Register SMC_WPMR Read-write 0x00000000 0xE8 SMC Write Protect Status Register SMC_WPSR Read-only 0x00000000 0xEC-0xFC Reserved - - -

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

30.16.1 SMC Setup Register

Name: SMC_SETUP[0..5] Addresses: 0xFFFFEA00 [0], 0xFFFFEA10 [1], 0xFFFFEA20 [2], 0xFFFFEA30 [3], 0xFFFFEA40 [4], 0xFFFFEA50 [5] Access: Read-write  NWE_SETUP: NWE Setup Length The NWE signal setup length is defined as: NWE setup length = (128* NWE_SETUP[5] + NWE_SETUP[4:0]) clock cycles  NCS_WR_SETUP: NCS Setup Length in WRITE Access In write access, the NCS signal setup length is defined as: NCS setup length = (128* NCS_WR_SETUP[5] + NCS_WR_SETUP[4:0]) clock cycles  NRD_SETUP: NRD Setup Length The NRD signal setup length is defined in clock cycles as: NRD setup length = (128* NRD_SETUP[5] + NRD_SETUP[4:0]) clock cycles  NCS_RD_SETUP: NCS Setup Length in READ Access In read access, the NCS signal setup length is defined as: NCS setup length = (128* NCS_RD_SETUP[5] + NCS_RD_SETUP[4:0]) clock cycles 31 30 29 28 27 26 25 24 – – NCS_RD_SETUP 23 22 21 20 19 18 17 16 – – NRD_SETUP 15 14 13 12 11 10 9 8 – – NCS_WR_SETUP 76543210 – – NWE_SETUP

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

30.16.2 SMC Pulse Register

Name: SMC_PULSE[0..5] Addresses: 0xFFFFEA04 [0], 0xFFFFEA14 [1], 0xFFFFEA24 [2], 0xFFFFEA34 [3], 0xFFFFEA44 [4], 0xFFFFEA54 [5] Access: Read-write  NWE_PULSE: NWE Pulse Length The NWE signal pulse length is defined as: NWE pulse length = (256* NWE_PULSE[6] + NWE_PULSE[5:0]) clock cycles The NWE pulse length must be at least 1 clock cycle.  NCS_WR_PULSE: NCS Pulse Length in WRITE Access In write access, the NCS signal pulse length is defined as: NCS pulse length = (256* NCS_WR_PULSE[6] + NCS_WR_PULSE[5:0]) clock cycles The NCS pulse length must be at least 1 clock cycle.  NRD_PULSE: NRD Pulse Length In standard read access, the NRD signal pulse length is defined in clock cycles as: NRD pulse length = (256* NRD_PULSE[6] + NRD_PULSE[5:0]) clock cycles The NRD pulse length must be at least 1 clock cycle. In page mode read access, the NRD_PULSE parameter defines the duration of the subsequent accesses in the page.  NCS_RD_PULSE: NCS Pulse Length in READ Access In standard read access, the NCS signal pulse length is defined as: NCS pulse length = (256* NCS_RD_PULSE[6] + NCS_RD_PULSE[5:0]) clock cycles The NCS pulse length must be at least 1 clock cycle. In page mode read access, the NCS_RD_PULSE parameter defines the duration of the first access to one page. 31 30 29 28 27 26 25 24 – NCS_RD_PULSE 23 22 21 20 19 18 17 16 – NRD_PULSE 15 14 13 12 11 10 9 8 – NCS_WR_PULSE 76543210 –N WE_PULSE

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

30.16.3 SMC Cycle Register

Name: SMC_CYCLE[0..5] Addresses: 0xFFFFEA08 [0], 0xFFFFEA18 [1], 0xFFFFEA28 [2], 0xFFFFEA38 [3], 0xFFFFEA48 [4], 0xFFFFEA58 [5] Access: Read-write  NWE_CYCLE: Total Write Cycle Length The total write cycle length is the total duration in clock cycles of the write cycle. It is equal to the sum of the setup, pul se and hold steps of the NWE and NCS signals. It is defined as: Write cycle length = (NWE_CYCLE[8:7]*256 + NWE_CYCLE[6:0]) clock cycles  NRD_CYCLE: Total Read Cycle Length The total read cycle length is the total duration in clock cycles of the read cycle. It is equal to the sum of the setup, pulse and hold steps of the NRD and NCS signals. It is defined as: Read cycle length = (NRD_CYCLE[8:7]*256 + NRD_CYCLE[6:0]) clock cycles 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 NRD_CYCLE 15 14 13 12 11 10 9 8 76543210 NWE_CYCLE

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

30.16.4 SMC MODE Register

Name: SMC_MODE[0..5] Addresses: 0xFFFFEA0C [0], 0xFFFFEA1C [1], 0xFFFFEA2C [2], 0xFFFFEA3C [3], 0xFFFFEA4C [4], 0xFFFFEA5C [5] Access: Read-write  READ_MODE: 1: The read operation is controlled by the NRD signal. – If TDF cycles are programmed, the external bus is marked busy after the rising edge of NRD. – If TDF optimization is enabled (TDF_MODE =1), TDF wait states are inserted after the setup of NRD. 0: The read operation is controlled by the NCS signal. – If TDF cycles are programmed, the external bus is marked busy after the rising edge of NCS. – If TDF optimization is enabled (TDF_MODE =1), TDF wait states are inserted after the setup of NCS. W R I T E _ M O D E 1: The write operation is controlled by the NWE signal. – If TDF optimization is enabled (TDF_MODE =1), TDF wait states will be inserted after the setup of NWE. 0: The write operation is controlled by the NCS signal. – If TDF optimization is enabled (TDF_MODE =1), TDF wait states will be inserted after the setup of NCS.  EXNW_MODE: NWAIT Mode The NWAIT signal is used to extend the current read or writ e signal. It is only taken into account during the pulse phase of the read and writ e controlling signal. When the use of NWAIT is enable d, at least one cycle hold duration mu st be pro- grammed for the read and write controlling signal.

  • Disabled Mode: The NWAIT input signal is ignored on the corresponding Chip Select.
  • Frozen Mode: If asserted, the NWAIT signal freezes the current read or write cycle. After deassertion, the read/write cycle is resumed from the point where it was stopped. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 – – – TDF_MODE TDF_CYCLES 15 14 13 12 11 10 9 8 76543210 – – EXNW_MODE – – WRITE_MODE READ_MODE EXNW_MODE NWAIT Mode

00 D isabled

01 R eserved

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

  • Ready Mode: The NWAIT signal indicates the availability of the external device at the end of the pulse of the controlling read or write signal, to complete the access. If high, the access normally completes. If low, the access is extended until NWAIT returns high.  BAT: Byte Access Type This field is used only if DBW defines a 16- or 32-bit data bus.
  • 1: Byte write access type: – Write operation is controlled using NCS, NWR0, NWR1, NWR2, NWR3. – Read operation is controlled using NCS and NRD.
  • 0: Byte select access type: – Write operation is controlled using NCS, NWE, NBS0, NBS1, NBS2 and NBS3 – Read operation is controlled using NCS, NRD, NBS0, NBS1, NBS2 and NBS3  DBW: Data Bus Width  TDF_CYCLES: Data Float Time This field gives the integer number of clock cycles required by the external device to release the data after the rising edge of the read controlling signal. The SMC always provide one full cycle of bus turnaround after the TDF_CYCLES period. The external bus cannot be used by another chip select during TDF_CYCLES + 1 cycles. From 0 up to 15 TDF_CYCLES can be set.  TDF_MODE: TDF Optimization 1: TDF optimization is enabled. – The number of TDF wait states is optimized using the setup period of the next read/write access. 0: TDF optimization is disabled. – The number of TDF wait states is inserted before the next access begins.  PMEN: Page Mode Enabled 1: Asynchronous burst read in page mode is applied on the corresponding chip select. 0: Standard read is applied.  PS: Page Size If page mode is enabled, this field indicates the size of the page in bytes. DBW Data Bus Width 00 8 -bit bus 01 1 6-bit bus 10 3 2-bit bus

11 R eserved

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

30.16.5 SMC DELAY I/O Register

Name: SMC_DELAY 1-8 Addresses: 0xFFFFEAC0 [1] .. 0xFFFFEADC [8] Access: Read-write Reset: See Table 30-8  Delay x: Gives the number of elements in the delay line. 31 30 29 28 27 26 25 24 Delay8 Delay7 23 22 21 20 19 18 17 16 Delay6 Delay5 15 14 13 12 11 10 9 8 Delay4 Delay3 76543210 Delay2 Delay1

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

30.16.6 SMC Write Protect Mode Register

Name: SMC_WPMR Address: 0xFFFFEAE4 Access: Read-write Reset: See Table 30-8  WPEN: Write Protect Enable 0 = Disables the Write Protect if WPKEY corresponds to 0x534D43 (“SMC” in ASCII). 1 = Enables the Write Protect if WPKEY corresponds to 0x534D43 (“SMC” in ASCII). Protects the registers listed below:

  • Section 30.16.1 ”SMC Setup Register”
  • Section 30.16.2 ”SMC Pulse Register”
  • Section 30.16.3 ”SMC Cycle Register”
  • Section 30.16.4 ”SMC MODE Register”
  • Section 30.16.5 ”SMC DELAY I/O Register”  WPKEY: Write Protect KEY Should be written at value 0x534D43 (“SMC” in ASCII). Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. 31 30 29 28 27 26 25 24 WPKEY 23 22 21 20 19 18 17 16 WPKEY 15 14 13 12 11 10 9 8 WPKEY 76543210

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

30.16.7 SMC Write Protect Status Register

Name: SMC_WPSR Address: 0xFFFFEAE8 Access: Read-only Reset: See Table 30-8  WPVS: Write Protect Enable 0 = No Write Protect Violation has occurred since the last read of the SMC_WPSR register. 1 = A Write Protect Violation occurred since the last read of the SMC_WPSR register. If this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field WPVSRC.  WPVSRC: Write Protect Violation Source When WPVS is active, this field indicates the write-protected register (t hrough address offset or code) in which a write access has been attempted. Note: Reading SMC_WPSR automatically clears all fields. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WPVSRC 15 14 13 12 11 10 9 8 WPVSRC 76543210

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 431 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 31. DDR SDR SDRAM Co ntroller (DDRSDRC)

31.1 Description

The DDR SDR SDRAM Controller (DDRSDRC) is a multiport memory controller. It comprises four slave AHB interfaces. All simultaneous accesses (four independent AHB ports) are inter- leaved to maximize memory bandwidth and minimize transaction latency due to SDRAM protocol. The DDRSDRC extends the memory capabilities of a chip by providing the interface to an exter- nal 16-bit or 32-bit SDR-SDRAM device and external 16-bit DDR-SDRAM device. The page size supports ranges from 2048 to 16384 and the number of columns from 256 to 4096. It supports byte (8-bit), half-word (16-bit) and word (32-bit) accesses. The DDRSDRC supports a read or write burst length of 8 locations which frees the command and address bus to anticipate the next command, thus reducing latency imposed by the SDRAM protocol and improving the SDRAM bandwidth. Moreover it keeps track of the active row in each bank, thus maximizing SDRAM performance, e.g., the application may be placed in one bank and data in the other banks. So as to optimize performance, it is advisable to avoid accessing different rows in the same bank. The DDRSDRC supports a CAS latency of 2 or 3 and optimizes the read access depending on the frequency. The features of self refresh, power-down and deep power-down modes minimize the consump- tion of the SDRAM device. The DDRSDRC user interface is compliant with ARM Advanced Peripheral Bus (APB rev2). Note: The term “SDRAM device” regroups SDR-SDRAM, Low-power SDR-SDRAM, Low-power DDR1-SDRAM and DDR2-SDRAM devices.

31.2 Embedded Characteristics

  • AMBA Compliant Interface, interfaces Directly to the ARM Advanced High performance Bus (AHB) – Four AHB Interfaces, Management of All Accesses Maximizes Memory Bandwidth and Minimizes Transaction Latency – AHB Transfer: Word, Half Word, Byte Access
  • Supports DDR2-SDRAM, Low-power DDR1-S DRAM or DDR2-SDRAM, SDR-SDRAM and Low-power SDR-SDRAM
  • Numerous Configurations Supported – 2K, 4K, 8K, 16K Row Address Memory Parts – SDRAM with Four and Eight Internal Banks – SDR-SDRAM with 16- or 32-bit Data Path – DDR-SDRAM with 16-bit Data Path – One Chip Select for SDRAM Device (256 Mbyte Address Space)
  • Programming Facilities – Multibank Ping-pong Access (Up to or 4 Banks or 8 banks Opened at Same Time = Reduces Average Latency of Transactions) – Timing Parameters Specified by Software – Automatic Refresh Operation, Refresh Rate is Programmable

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 432 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 – Automatic Update of DS, TCR and PASR Parameters (Low-power SDRAM Devices)

  • Energy-saving Capabilities – Self-refresh, Power-down, Active Power-down and Deep Power-down Modes Supported
  • SDRAM Power-up Initialization by Software
  • CAS Latency of 2, 3 Supported
  • Reset Function Supported (DDR2-SDRAM)
  • ODT (On-die Termination) Not Supported
  • Auto Precharge Command Not Used
  • SDR-SDRAM with 16-bit Datapath and Eight Columns Not Supported
  • DDR2-SDRAM with Eight Internal Banks Supported
  • Linear and Interleaved Decoding Supported
  • SDR-SDRAM or Low-power DDR1-SDRAM with 2 Internal Banks Not Supported
  • Clock Frequency Change in Precharge Power-down Mode Not Supported
  • OCD (Off-chip Driver) Mode Not Supported

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 433 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

31.3 DDRSDRC Module Diagram

Figure 31-1. DDRSDRC Module Diagram DDRSDRC is partitioned in two blocks (see Figure 31-1):

  • An Interconnect-Matrix that manages concurrent accesses on the AHB bus between four AHB masters and integrates an arbiter.
  • A controller that translates AHB requests (Read/Write) in the SDRAM protocol. Memory Controller Finite State Machine SDRAM Signal Management Addr, DQM Data Asynchronous Timing Refresh Management DDR-SDR Devices Power Management DQS ras,cas,we cke clk/nclk odt DDR-SDR Controller Interconnect Matrix Input Stage Input Stage Input Stage Output Stage Arbiter APB AHB Slave Interface 0 AHB Slave Interfa ce 1 AHB Slave Interface 2 AHB Slave Interface 3 Input Stage Interface APB

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 434 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

31.4 Initialization Sequence

The addresses given are for example purposes only. The real address depends on implementa- tion in the product.

31.4.1 SDR-SDRAM Initialization

The initialization sequence is generated by so ftware. The SDR-SDRAM devices are initialized by the following sequence: 1. Program the memory device type into the Memory Device Register (see Section 31.7.8 on page 474). 2. Program the features of the SDR-SDRAM device into the Timing Register (asynchro- nous timing (trc, tras, etc.)), and into the Configuration Register (number of columns, rows, banks, cas latency) (see Section 31.7.3 on page 464, Section 31.7.4 on page 467 and Section 31.7.5 on page 469). 3. For low-power SDRAM, temperature-compensated self refresh (TCSR), drive strength (DS) and partial array self refresh (PASR) must be set in the Low-power Register (see Section 31.7.7 on page 472). A minimum pause of 200 μs is provided to precede any signal toggle. 4. A NOP command is issued to the SDR-SDRAM. Program NOP command into Mode Register, the application must set Mode to 1 in the Mode Register (See Section 31.7.1 on page 462). Perform a write access to any SDR-SDRAM address to acknowledge this command. Now the clock which drives SDR-SDRAM device is enabled. 5. An all banks precharge command is issued to the SDR-SDRAM. Program all banks precharge command into Mode Register, the application must set Mode to 2 in the Mode Register (See Section 31.7.1 on page 462). Perform a write access to any SDR- SDRAM address to acknowledge this command. 6. Eight auto-refresh (CBR) cycles are provided. Program the auto refresh command (CBR) into Mode Register, the application must set Mode to 4 in the Mode Register (see Section 31.7.1 on page 462).Performs a write access to any SDR-SDRAM loca- tion eight times to acknowledge these commands. 7. A Mode Register set (MRS) cycle is issued to program the parameters of the SDR- SDRAM devices, in particular CAS latency and burst length. The application must set Mode to 3 in the Mode Register (see Section 31.7.1 on page 462) and perform a write access to the SDR-SDRAM to acknowledge this command. The write address must be chosen so that BA[1:0] are set to 0. For example, with a 16-bit 128 MB SDR-SDRAM (12 rows, 9 columns, 4 banks) bank address, the SDRAM write access should be done at the address 0x20000000. Note: This address is for example purposes only. The real address is dependent on implementation in the product. 8. For low-power SDR-SDRAM initialization, an Extended Mode Register set (EMRS) cycle is issued to program the SDR-SDRAM parameters (TCSR, PASR, DS). The appli- cation must set Mode to 5 in the Mode Register (see Section 31.7.1 on page 462) and perform a write access to the SDR-SDRAM to acknowledge this command. The write address must be chosen so that BA[1] is set to 1 and BA[0] is set to 0. For example, with a 16-bit 128 MB SDRAM, (12 rows, 9 columns, 4 banks) bank address the SDRAM write access should be done at the address 0x20800000. 9. The application must go into Normal Mode, setting Mode to 0 in the Mode Register (see Section 31.7.1 on page 462) and perform a write access at any location in the SDRAM to acknowledge this command.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 435 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 10. Write the refresh rate into the count field in the DDRSDRC Refresh Timer register (see page 463). (Refresh rate = delay between refresh cycles). The SDR-SDRAM device requires a refresh every 15.625 μs or 7.81 μs. With a 100 MHz frequency, the refresh timer count register must to be set with (15.625*100 MHz) = 1562 i.e. 0x061A or (7.81*100 MHz) = 781 i.e. 0x030d After initialization, the SDR-SDRAM device is fully functional.

31.4.2 Low-power DDR1-SDRAM Initialization

The initialization sequence is generated by software. The low-power DDR1-SDRAM devices are initialized by the following sequence: 1. Program the memory device type into the Memory Device Register (see Section 31.7.8 on page 474). 2. Program the features of the low-power DDR1-SDRAM device into the Configuration Register: asynchronous timing (trc, tras, etc.), number of columns, rows, banks, cas 31.7.5 on page 469. 3. Program temperature compensated self refresh (tcr), Partial array self refresh (pasr) and Drive strength (ds) into the Low-power Register. See Section 31.7.7 on page 472. 4. An NOP command will be issued to the low-power DDR1-SDRAM. Program NOP com- mand into the Mode Register, the application must set Mode to 1 in the Mode Register (see Section 31.7.1 on page 462). Perform a write access to any DDR1-SDRAM address to acknowledge this command. Now clocks which drive DDR1-SDRAM device are enabled. A minimum pause of 200 μs will be provided to precede any signal toggle. 5. An all banks precharge command is issued to the low-power DDR1-SDRAM. Program all banks precharge command into the Mode Register, the application must set Mode to 2 in the Mode Register (See Section 31.7.1 on page 462). Perform a write access to any low-power DDR1-SDRAM address to acknowledge this command 6. Two auto-refresh (CBR) cycles are provid ed. Program the auto refresh command (CBR) into the Mode Register, the application must set Mode to 4 in the Mode Register (see Section 31.7.1 on page 462). Perform a write access to any low-power DDR1- SDRAM location twice to acknowledge these commands. 7. An Extended Mode Register set (EMRS) cycle is issued to program the low-power DDR1-SDRAM parameters (TCSR, PASR, DS). The application must set Mode to 5 in the Mode Register (see Section 31.7.1 on page 462) and perform a write access to the SDRAM to acknowledge this command. The write address must be chosen so that BA[1] is set to 1 BA[0] is set to 0. For example, with a 16-bit 128 MB SDRAM (12 rows, 9 columns, 4 banks) bank address, the low-power DDR1-SDRAM write access should be done at address 0x20800000. Note: This address is for example purposes only. The real address is dependent on implementation in the product. 8. A Mode Register set (MRS) cycle is issued to program the parameters of the low-power DDR1-SDRAM devices, in particular CAS latency, burst length. The application must set Mode to 3 in the Mode Register (see Section 31.7.1 on page 462) and perform a write access to the low-power DDR1-SDRAM to acknowledge this command. The write address must be chosen so that BA[1:0] bits are set to 0. For example, with a 16-bit 128 MB low-power DDR1-SDRAM (12 rows, 9 columns, 4 banks) bank address, the SDRAM write access should be done at the address 0x20000000. The application must go into Normal Mode, setting Mode to 0 in the Mode Register (see Section 31.7.1 on

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 436 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 page 462) and performing a write access at any location in the low-power DDR1- SDRAM to acknowledge this command. 9. Perform a write access to any low-power DDR1-S DRAM address. 10. Write the refresh rate into the count field in the DDRSDRC Refresh Timer register (see page 463). (Refresh rate = delay between refresh cycles). The low-power DDR1- SDRAM device requires a refresh every 15.625 μs or 7.81 μs. With a 100 MHz fre- quency, the refresh timer count register must to be set with (15.625*100 MHz) = 1562 11. After initialization, the low-power DDR1-SDRAM device is fully functional.

31.4.3 DDR2-SDRAM Initialization

The initialization sequence is generated by so ftware. The DDR2-SDRAM de vices are initialized by the following sequence: 1. Program the memory device type into the Memory Device Register (see Section 31.7.8 on page 474). 2. Program the features of DDR2-SDRAM device into the Timing Register (asynchronous timing (trc, tras, etc.)), and into the Configuration Register (number of columns, rows, banks, cas latency and output drive strength) (see Section 31.7.3 on page 464, Section 3. An NOP command is issued to the DDR2-SDRAM. Program the NOP command into the Mode Register, the application must set Mode to 1 in the Mode Register (see Sec- tion 31.7.1 on page 462). Perform a write access to any DDR2-SDRAM address to acknowledge this command. Now clocks which drive DDR2-SDRAM device are enabled. A minimum pause of 200 μs is provided to precede any signal toggle. 4. An NOP command is issued to the DDR2-SDRAM. Program the NOP command into the Mode Register, the application must set Mode to 1 in the Mode Register (see Sec- tion 31.7.1 on page 462). Perform a write access to any DDR2-SDRAM address to acknowledge this command. Now CKE is driven high. 5. An all banks precharge command is issued to the DDR2-SDRAM. Program all banks precharge command into the Mode Register, the application must set Mode to 2 in the Mode Register (See Section 31.7.1 on page 462). Perform a write access to any DDR2- SDRAM address to acknowledge this command 6. An Extended Mode Register set (EMRS2) cycle is issued to chose between commer- cial or high temperature operations. The application must set Mode to 5 in the Mode Register (see Section 31.7.1 on page 462) and perform a write access to the DDR2- SDRAM to acknowledge this command. The write address must be chosen so that BA[1] is set to 1 and BA[0] is set to 0. For example, with a 16-bit 128 MB DDR2- SDRAM (12 rows, 9 columns, 4 banks) bank address, the DDR2-SDRAM write access should be done at the address 0x20800000. Note: This address is for example purposes only. The real address is dependent on implementation in the product. 7. An Extended Mode Register set (EMRS3) cycle is issued to set the Extended Mode Register to “0”. The application must set Mode to 5 in the Mode Register (see Section 31.7.1 on page 462) and perform a write access to the DDR2-SDRAM to acknowledge this command. The write address must be chosen so that BA[1] is set to 1 and BA[0] is set to 1. For example, with a 16-bit 128 MB DDR2-SDRAM (12 rows, 9 columns, 4 banks) bank address, the DDR2-SDRAM write access should be done at the address 0x20C00000.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 437 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 8. An Extended Mode Register set (EMRS1) cycle is issued to enable DLL. The applica- tion must set Mode to 5 in the Mode Register (see Section 31.7.1 on page 462) and perform a write access to the DDR2-SDRAM to acknowledge this command. The write address must be chosen so that BA[1] is set to 0 and BA[0] is set to 1. For example, with a 16-bit 128 MB DDR2-SDRAM (12 rows, 9 columns, 4 banks) bank address, the DDR2-SDRAM write access should be done at the address 0x20400000. An additional 200 cycles of clock are required for locking DLL 9. Program DLL field into the Configuration Register (see Section 31.7.3 on page 464) to high (Enable DLL reset). 10. A Mode Register set (MRS) cycle is issued to reset DLL. The application must set Mode to 3 in the Mode Register (see Section 31.7.1 on page 462) and perform a write access to the DDR2-SDRAM to acknowledge this command. The write address must be chosen so that BA[1:0] bits are set to 0. For example, with a 16-bit 128 MB DDR2- SDRAM (12 rows, 9 columns, 4 banks) bank address, the SDRAM write access should be done at the address 0x20000000. 11. An all banks precharge command is issued to the DDR2-SDRAM. Program all banks precharge command into the Mode Register, the application must set Mode to 2 in the Mode Register (See Section 31.7.1 on page 462). Perform a write access to any DDR2- SDRAM address to acknowledge this command 12. Two auto-refresh (CBR) cycles are provided. Program the auto refresh command (CBR) into the Mode Register, the application must set Mode to 4 in the Mode Register (see Section 31.7.1 on page 462). Performs a write access to any DDR2-SDRAM loca- tion twice to acknowledge these commands. 13. Program DLL field into the Configuration Register (see Section 31.7.3 on page 464) to low (Disable DLL reset). 14. A Mode Register set (MRS) cycle is issued to program the parameters of the DDR2- SDRAM devices, in particular CAS latency, burst length and to disable DLL reset. The application must set Mode to 3 in the Mode Register (see Section 31.7.1 on page 462) and perform a write access to the DDR2-SDRAM to acknowledge this command. The write address must be chosen so that BA[1:0] are set to 0. For example, with a 16-bit

128 MB SDRAM (12 rows, 9 columns, 4 banks) bank address, the SDRAM write

access should be done at the address 0x20000000 15. Program OCD field into the Configuration Register (see Section 31.7.3 on page 464) to high (OCD calibration default). 16. An Extended Mode Register set (EMRS1) c ycle is issued to OCD default value. The application must set Mode to 5 in the Mode Register (see Section 31.7.1 on page 462) and perform a write access to the DDR2-SDRAM to acknowledge this command. The write address must be chosen so that BA[1] is set to 0 and BA[0] is set to 1. For exam- ple, with a 16-bit 128 MB DDR2-SDRAM (12 rows, 9 columns, 4 banks) bank address, the DDR2-SDRAM write access should be done at the address 0x20400000. 17. Program OCD field into the Configuration Register (see Section 31.7.3 on page 464) to low (OCD calibration mode exit). 18. An Extended Mode Register set (EMRS1) cycle is issued to enable OCD exit. The application must set Mode to 5 in the Mode Register (see Section 31.7.1 on page 462) and perform a write access to the DDR2-SDRAM to acknowledge this command. The write address must be chosen so that BA[1] is set to 0 and BA[0] is set to 1. For exam- ple, with a 16-bit 128 MB DDR2-SDRAM (12 rows, 9 columns, 4 banks) bank address, the DDR2-SDRAM write access should be done at the address 0x20400000.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 438 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 19. A mode Normal command is provided. Program the Normal mode into Mode Register (see Section 31.7.1 on page 462). Perform a write access to any DDR2-SDRAM address to acknowledge this command. 20. Perform a write access to any DDR2-SDRAM address. 21. Write the refresh rate into the count field in the Refresh Timer register (see page 463). (Refresh rate = delay between refresh cycles). The DDR2-SDRAM device requires a refresh every 15.625 μs or 7.81 μs. With a 133 MHz frequency, the refresh timer count register must to be set with (15.625*133 MHz) = 2079 i.e. 0x081f or (7.81*133 MHz) = 1039 i.e. 0x040f. After initialization, the DDR2-SDRAM devices are fully functional.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 439 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

31.5 Functional Description

31.5.1 SDRAM Controller Write Cycle

The DDRSDRC allows burst access or single access in normal mode (mode = 000). Whatever the access type, the DDRSDRC keeps track of the active row in each bank, thus maximizing performance. The SDRAM device is programmed with a burst length equal to 8. This determines the length of a sequential data input by the write command that is set to 8. The latency from write command to data input is fixed to 1 in the case of DDR-SDRAM devices. In the case of SDR-SDRAM devices, there is no latency from write command to data input. To initiate a single access, the DDRSDRC checks if the page access is already open. If row/bank addresses match with the previous row/bank addresses, the controller generates a write command. If the bank addresses are not identical or if bank addresses are identical but the row addresses are not identical, the controller generates a precharge command, activates the new row and initiates a write co mmand. To comply with SDRAM timing parameters, additional clock cycles are inserted between precharge/active (t RP) comm ands and active/write (t RCD) command. As the burst length is fixed to 8, in the case of single access, it has to stop the burst, otherwise seven invalid values may be written. In the case of SDR-SDRAM devices, a Burst Stop command is generated to interrupt the write operation. In the case of DDR-SDRAM devices, Burst Stop command is not supported for the burst write operation. In order to then interrupt the write operation, Dm must be set to 1 to mask invalid data (see Figure 31-2 on page 440 and Figure 31-5 on page 441) and DQS must continue to toggle. To initiate a burst access, the DDRSDRC uses the transfer type signal pr ovided by the master requesting the access. If the next access is a sequential write access, writing to the SDRAM device is carried out. If the next access is a write non-sequential access, then an automatic access break is inserted, the DDRSDRC generates a precharge command, activates the new row and initiates a write command. To comply with SDRAM timing parameters, additional clock cycles are inserted between precharge/acti ve (tRP) commands and active/write (tRCD) commands. For a definition of timing parameters, refer to Section 31.7.4 “DDRSDRC Timing Parameter 0 Register” on page 467. Write accesses to the SDRAM devices are burst oriented and the burst length is programmed to 8. It determines the maximum number of column locations that can be accessed for a given write command. When the write command is issued, 8 columns are selected. All accesses for that burst take place within these eight columns, thus the burst wraps within these 8 columns if a boundary is reached. These 8 columns are selected by addr[13:3]. addr[2:0] is used to select the starting location within the block. In the case of incrementing burst (INCR/INCR 4/INCR8/INCR16), the addresses can cross the 16-byte boundary of the SDRAM device. For example, in th e case of DDR-SDRAM devices, when a transfer (INCR4) starts at address 0x0C , the next access is 0x10, but since the burst length is programmed to 8, the next access is at 0x00. Since the boundary is reached, the burst is wrapping. The DDRSDRC takes this feature of the SDRAM device into account. In the case of transfer starting at address 0x04/0x08/0x0C (DDR-SDRAM devices) or starting at address 0x10/0x14/0x18/0x1C, two write commands are issued to avoid to wrap when the boundary is reached. The last write command is subject to DM input logic level. If DM is registered high, the corresponding data input is ignored and write access is not done. This avoi ds additional writing being done.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 444 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Figure 31-10. SINGLE Write Access Followed By A Read Access, DDR2 -SDRAM Device

31.5.2 SDRAM Controller Read Cycle

The DDRSDRC allows burst access or single access in normal mode (mode =000). Whatever access type, the DDRSDRC keeps track of the active row in each bank, thus maximizing perfor- mance of the DDRSDRC. The SDRAM devices are programmed with a burst length equal to 8 which determines the length of a sequential data output by the read command that is set to 8. The latency from read com- mand to data output is equal to 2 or 3. This value is programmed during the initialization phase (see Section 31.4.1 “SDR-SDRAM Initialization” on page 434). To initiate a single access, the DDRSDRC checks if the page access is already open. If row/bank addresses match with the previous row/bank addresses, the controller generates a read command. If the bank addresses are not identical or if bank addresses are identical but the row addresses are not identical, the controller generates a precharge command, activates the new row and initiates a read command. To comply with SDRAM timing parameters, additional clock cycles are inserted between precharge/ active (Trp) commands and active/read (Trcd) command. After a read command, additional wait states are generated to comply with cas latency. The DDRSDRC supports a cas latency of two, two and ha lf, and three (2 or 3 clocks delay). As the burst length is fixed to 8, in the case of single access or burst access inferior to 8 data requests, it has to stop the burst otherwise seven or X values could be read. Burst Stop Command (BST) is used to stop output during a burst read. To initiate a burst access, the DDRSDRC checks the transfer type signal . If the next accesses are sequential read accesses, reading to the SDRAM device is carried out. If the next access is a read non-sequential access, then an automatic page break can be inserted. If the bank addresses are not identical or if bank addresses are identical but the row addresses are not identical, the controller generates a precharge command, activates the new row and initiates a read command. In the case where the page access is already open, a read command is generated. Row a col a NOP PRCHG NOP ACT NOP WRITE NOP READ NOP Data masked SDCLK A[12:0] COMMAND BA[1:0] DQS[1:0] Da DbDa DbD[15:0] 3 0 3 DM[1:0] twtr

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 445 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 To comply with SDRAM timing parameters, addit ional clock cycles are inserted between pre- charge/active (Trp) commands and active/r ead (Trcd) commands. The DDRSDRC supports a cas latency of two, two and half, and three (2 or 3 clocks delay). During this delay, the controller uses internal signals to anticipate the next access and improve the performance of the control- ler. Depending on the latency(2/3), the DDRSDRC anticipates 2 or 3 read accesses. In the case of burst of specified length, accesses are not anticipated, but if the burst is broken (border, busy mode, etc.), the next access is treated as an incrementing burst of unspecified length, and in function of the latency(2/3), the DDRSDRC anticipates 2 or 3 read accesses. For a definition of timing parameters, refer to Section 31.7.3 “DDRSDRC Configuration Register” on page 464. Read accesses to the SDRAM are burst oriented and the burst length is programmed to 8. It determines the maximum number of column locations that can be accessed for a given read command. When the read command is issued, 8 columns are selected. All accesses for that burst take place within these eight columns, me aning that the burst wraps within these 8 col- umns if the boundary is reached. These 8 column s are selected by addr[13:3]; addr[2:0] is used to select the starting location within the block. In the case of incrementing burst (INCR/INCR 4/INCR8/INCR16), the addresses can cross the 16-byte boundary of the SDRAM device. For example, when a transfer (INCR4) starts at address 0x0C, the next access is 0x10, but since the burst length is programmed to 8, the next access is 0x00. Since the boundary is reach ed, the burst wraps. The DDRSDRC takes into account this feature of the SDRAM device. In th e case of DDR-SDRAM devices, transfers start at address 0x04/0x08/0x0C. In the case of SDR-SDRAM devices, transfers start at address 0x14/0x18/0x1C. Two read commands are issued to avoid wrapping when the boundary is reached. The last read command may generate ad ditional reading (1 read cmd = 4 DDR words or 1 read cmd = 8 SDR words). To avoid additional reading, it is possible to use the burst stop command to truncate the read burst and to decrease power consumption.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 448 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Figure 31-15. Burst Read Access, Latency = 3, DDR2-SDRAM Devices Figure 31-16. Burst Read Access, Latency = 2, SDR-SDRAM Devices

31.5.3 Refresh (Auto-refresh Command)

An auto-refresh command is used to refresh the DDRSDRC. Refresh addresses are generated internally by the SDRAM device and incremented after each auto-refresh automatically. The DDRSDRC generates these auto-refresh commands periodically. A timer is loaded with the value in the register DDRSDRC_TR that indicates the number of clock cycles between refresh cycles. When the DDRSDRC initiates a refresh of an SDRAM device, internal memory accesses are not delayed. However, if the CPU tries to access the SDRAM device, the slave indicates that the device is busy. A request of refresh does not interrupt a burst transfer in progress. Col a NOP READ NOP Latency = 3 SDCLK A[12:0] COMMAND BA[1:0] DQS[1:0] Da Db Dc Dd De Df Dg DhD[15:0] 3DM[1:0] Latency = 2 SDCLK col aA[12:0] NOP READ NOP BST NOPCOMMAND 0BA[1:0] DaDb DcDd DeDf Dg Dh D[31:0] FDM[3:0] DQS[1:0]

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 449 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

31.5.4 Power Management

31.5.4.1 Self Refresh Mode

This mode is activated by setting low-powe r command bits [LPCB] to ‘01’ in the DDRSDRC_LPR Register Self refresh mode is used to reduce power consumption, i.e., when no access to the SDRAM device is possible. In this case, power consumption is very low. In self refresh mode, the SDRAM device retains data without external clocking and provides its own internal clocking, thus performing its own auto-refresh cycles. All the inputs to the SDRAM device become “don’t care” except CKE, which remains low. As soon as the SDRAM device is selected, the DDRS- DRC provides a sequence of commands and exits self refresh mode. The DDRSDRC re-enables self refresh mode as soon as the SDRAM device is not selected. It is possible to define when self refresh mode will be enabled by setting the register LPR (see Sec- tion 31.7.7 “DDRSDRC Low-power Register” on page 472), timeout command bit:

  • 00 = Self refresh mode is enabled as soon as the SDRAM device is not selected
  • 01 = Self refresh mode is enabled 64 clock cycles after completion of the last access
  • 10 = Self refresh mode is enabled 128 clock cycles after completion of the last access As soon as the SDRAM device is no longe r selected, PRECHARGE ALL BANKS command is generated followed by a SELF-REFREFSH co mmand. If, between these two commands an SDRAM access is detected, SELF-REFREFSH command will be replaced by an AUTO- REFRESH command. According to the applica tion, more AUTO-REFRESH commands will be performed when the self refresh mode is enabled during the application. This controller also interfaces low-power SD RAM. These devices add a new feature: A single quarter, one half quarter or all banks of the SDRAM array can be enabled in self refresh mode. Disabled banks will be not refreshed in self refresh mode. This feature permits to reduce the self refresh current. The extended mode register controls this feature, it includes Temperature Com- pensated Self Refresh (TSCR), Partial Array Self Refresh (PASR) parameters and Drive Strength (DS). These parameters are set during the initialization phase. After initialization, as soon as PASR/DS/TCSR fields are modified, the Extended Mode Register in the memory of the external device is accessed automatica lly and PASR/DS/TCSR bits are updated before entry into self refresh mode if DDRSDRC does not share an external bus with another controller or during a refresh command, and a pending read or write access, if DDRSDRC does share an external bus with another controller. This type of update is a function of the UPD_MR bit (see Section 31.7.7 “DDRSDRC Low-power Register” on page 472). The low-power SDR-SDRAM must remain in self refresh mode for a minimum period of TRAS periods and may remain in self refresh mode for an indefinite period. (See Figure 31-17) The low-power DDR1-SDRAM must remain in self refresh mode for a minimum of TRFC periods and may remain in self refresh mode for an indefinite period. The DDR2-SDRAM must remain in self refres h mode for a minimum of TCKE periods and may remain in self refresh mode for an indefinite period.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 452 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Figure 31-21. Automatic Update During AUTO-REFRESH Command and SDRAM Access

31.5.4.2 Power-down Mode

This mode is activated by setting the low-power command bits [LPCB] to ‘10’. Power-down mode is used when no access to the SDRAM device is possible. In this mode, power consumption is greater than in self refresh mode. This state is similar to normal mode (No low-power mode/No self refresh mode), but the CKE pin is low and the input and output buffers are deactivated as soon the SDRAM device is no longer accessible. In contrast to self refresh mode, the SDRAM device cannot remain in low-power mode longer than the refresh period (64 ms). As no auto-refresh oper ations are performed in this mode, the DDRSDRC carries out the refresh operation. In order to exit low-power mode, a NOP command is required in the case of Low-power SDR-SDRAM and SDR-SDRAM devices . In the case of Low-power DDR1-SDRAM devices, the controller generates a NOP command during a delay of at least TXP. In addition, Low-power DDR1-SDRAM and DDR2-SDRAM must re main in power-down mode for a mini- mum period of TCKE periods. The exit procedure is faster than in self refresh mode. See Figure 31-22 on page 453 . The DDRSDRC returns to power-down mode as soon as the SDRAM device is not selected. It is possible to define when power-down mode is enabled by setting the register LPR, timeout com- mand bit.

  • 00 = Power-down mode is enabled as soon as the SDRAM device is not selected
  • 01 = Power-down mode is enabled 64 clock cycles after completion of the last access
  • 10 = Power-down mode is enabled 128 clock cycles after completion of the last access NOP NOPPRCHALL MRSARFSH NOP Trfc SDCLK A[12:0] COMMAND CKE BA[1:0] 2 NOP Update Extended mode register Trp Pasr-Tcr-Ds ACT Tmrd

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 453 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Figure 31-22. Power-down Entry/Exit, Timeout = 0

31.5.4.3 Deep Power-down Mode

The deep power-down mode is a new feature of the Low-power SDRAM. When this mode is activated, all internal voltage generators inside the device are stopped and all data is lost. This mode is activated by setting the low-power command bits [LPCB] to ‘11’. When this mode is enabled, the DDRSDRC leaves normal mode (mode == 000) and the controller is frozen. To exit deep power-down mode, the low-power bits (LPCB) must be set to “00”, an initialization sequence must be generated by software. See Section 31.4.2 “Low-power DDR1-SDRAM Ini- tialization” on page 435. Figure 31-23. Deep Power-down Mode Entry Entry power down mode Exit power down mode SDCLK A[12:0] READ BST NOP READCOMMAND CKE 0BA[1:0] DQS[1:0] Da DbD[15:0] 3DM[1:0] NOP READ BST NOP PRCHG NOP DEEPOWER NOP Trp Enter Deep Power-down Mode SDCLK A[12:0] COMMAND CKE BA[1:0] DQS[1:0] Da DbD[15:0] 3DM[1:0]

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 454 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

31.5.4.4 Reset Mode

The reset mode is a feature of the DDR2-SDRAM. This mode is activated by setting the low- power command bits (LPCB) to 11 and the clock frozen command bit (CLK_FR) to 1. When this mode is enabled, the DDRSDRC leaves normal mode (mode == 000) and the control- ler is frozen. Before enabling this mode, the end user must assume there is not an access in progress. To exit reset mode, the low-power command bits (LPCB) must be set to “00”, clock frozen com- mand bit (CLK_FR) set to 0 and an initialization sequence must be generated by software. See Section 31.4.3 “DDR2-SDRAM Initialization” on page 436.

31.5.5 Multi-port Functionality

The SDRAM protocol imposes a check of timings prior to performing a read or a write access, thus decreasing the performance of systems. An access to SDRAM is performed if banks and rows are open (or active). To activate a row in a particular bank, it has to de-active the last open row and open the new row. Two SDRAM commands must be performed to open a bank: Pre- charge and Active command with respect to Trp timing. Before performing a read or write command, Trcd timing must checked. This operation represents a significative loss. (see Figure 31-24). Figure 31-24. Trp and Trcd Timings The multi-port controller has been designed to mask these timings and thus improve the band- width of the system. DDRSDRC is a multi-port controller since four masters can simultaneously reach the controller. This feature improves the bandwidth of the system because it can detect four requests on the AHB slave inputs and thus anticipate the commands that follow, PRECHARGE and ACTIVE commands in bank X during current access in bank Y. This allows Trp and Trcd timings to be masked (see Figure 31-25). In the best case, all accesses are done as if the banks and rows were already open. The best condition is met when the four masters work in different banks. In NOP PRCHG NOP ACT NOP READ BST NOP Trp Trcd Latency =2 4 cycles before performing a read command SDCLK A[12:0] COMMAND BA[1:0] DQS[1:0] D[15:0] DM1:0] Da Db

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 455 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 the case of four simultaneous read accesses, when the four banks and associated rows are open, the controller reads with a continuous flow and masks the cas latency for each different access. To allow a continuous flow, the read command must be set at 2 or 3 cycles (cas latency) before the end of current access. This requires that the scheme of arbitration changes since the round-robin arbitration cannot be respected. If the controller anticipates a read access, and thus before the end of current access a master with a high priority arises, then this master will not serviced. The arbitration mechanism reduces latency when conflicts occur, i.e., when two or more masters try to access the SDRAM device at the same time. The arbitration type is round-robin arbitration. This algorithm dispatches the requests from differ- ent masters to the SDRAM device in a round-robin manner. If two or more master requests arise at the same time, the master with the lowest num ber is serviced first, then the others are ser- viced in a round-robin manner. To avoid burst breaking and to provide the maximum throughput for the SDRAM device, arbitration may only take place during the following cycles: 1. Idle cycles: When no master is connected to the SDRAM device. 2. Single cycles: When a slave is currently doing a single access. 3. End of Burst cycles: When the current cycle is the last cycle of a burst transfer. For bursts of defined length, predicted end of burst matches the size of the transfer. For bursts of undefined length, predicted end of burst is generated at the end of each four beat boundary inside the INCR transfer. 4. Anticipated Access: When an anticipate re ad access is done while current access is not complete, the arbitration scheme can be changed if the anticipated access is not the next access serviced by the arbitration scheme. Figure 31-25. Anticipate Precharge/Active Command in Bank 2 during Read Access in Bank 1 NOP READ NOP NOPPRECH ACT READ 1 12 Anticipate command, Precharge/Active Bank 2 Trp Read access in Bank 1 SDClK A[12:0] COMMAND BA[1:0] DQS[1:0] Da Db Dc Dd De Df Dg Dh Di Dj Dk DlD[15:0] 3DM1:0]

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 456 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

31.5.6 Write Protected Registers

To prevent any single software error that may corrupt DDRSDRC behavior, the registers listed below can be write-protected by setting the WPEN bit in the DDRSDRC Write Protect Mode Register (DDRSDRC_WPMR). If a write access in a write-pr otected register is detected, then the WPVS flag in the DDRSDRC Write Protect Status Register (DDRSDRC_WPSR) is set and the field WPVSRC indicates in which register the write access has been attempted. The WPVS flag is automatically reset after reading the DDRSDRC Write Protect Status Register (DDRSDRC_WPSR). Following is a list of the write protected registers:

  • “DDRSDRC Mode Register” on page 462
  • “DDRSDRC Refresh Timer Register” on page 463
  • “DDRSDRC Configuration Register” on page 464
  • “DDRSDRC Timing Parameter 0 Register” on page 467
  • “DDRSDRC Timing Parameter 1 Register” on page 469
  • “DDRSDRC Timing Parameter 2 Register” on page 470
  • “DDRSDRC Memory Device Register” on page 474
  • “DDRSDRC High Speed Register” on page 476

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 457 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

31.6 Software Interface/SDRAM Organization, Address Mapping

The SDRAM address space is organized into banks, rows and columns. The DDRSDRC maps different memory types depending on the values set in the DDRSDRC Configuration Register. See Section 31.7.3 “DDRSDRC Configuration Register” on page 464. The following figures illus- trate the relation between CPU addresses and columns, rows and banks addresses for 16-bit memory data bus widths and 32-bit memory data bus widths. The DDRSDRC supports address mapping in linear mode and interleaved mode. Linear mode is a method for address mapping where banks alternate at each last SDRAM page of current bank. Interleaved mode is a method for address mapping where banks alternate at each SDRAM end page of current bank. The DDRSDRC makes the SDRAM devices access protocol transparent to the user. Table 31-1 to Table 31-15 illustrate the SDRAM device memory mapping seen by the user in correlation with the device structure. Various configurations are illustrated.

31.6.1 SDRAM Address Mapping for 16-bit Memory Data Bus Width and Four Banks

Table 31-1. Linear Mapping for SDRAM Configuration, 2K Rows, 512/1024/2048/4096 Columns CPU Address Line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bk[1:0] Row[10:0] Column[8:0] M0 Bk[1:0] Row[10:0] Column[9:0] M0 Bk[1:0] Row[10:0] Column[10:0] M0 Bk[1:0] Row[10:0] Column[11:0] M0 Table 31-2. Linear Mapping for SDRAM Configuration: 4K Rows, 512/1024/2048/4096 Columns CPU Address Line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bk[1:0] Row[11:0] Column[8:0] M0 Bk[1:0] Row[11:0] Column[9:0] M0 Bk[1:0] Row[11:0] Column[10:0] M0 Bk[1:0] Row[11:0] Column[11:0] M0 Table 31-3. Linear Mapping for SDRAM Configuration: 8K Rows, 512/1024/2048/4096 Columns CPU Address Line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bk[1:0] Row[12:0] Column[8:0] M0

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 458 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Bk[1:0] Row[12:0] Column[9:0] M0 Bk[1:0] Row[12:0] Column[10:0] M0 Bk[1:0] Row[12:0] Column[11:0] M0 Table 31-3. Linear Mapping for SDRAM Configuration: 8K Rows, 512/1024/2048/4096 Columns CPU Address Line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 31-4. Linear Mapping for SDRAM Configuration: 16K Rows, 512/1024/2048 Columns CPU Address Line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bk[1:0] Row[13:0] Column[8:0] M0 Bk[1:0] Row[13:0] Column[9:0] M0 Bk[1:0] Row[13:0] Column[10:0] M0 Table 31-5. Interleaved Mapping for SDRAM Configuration, 2K Rows, 512/1024/2048/4096 Columns CPU Address Line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Row[10:0] Bk[1:0] Column[8:0] M0 Row[10:0] Bk[1:0] Column[9:0] M0 Row[10:0] Bk[1:0] Column[10:0] M0 Row[10:0] Bk[1:0] Column[11:0] M0 Table 31-6. Interleaved Mapping for SDRAM Configuration: 4K Rows, 512/1024/2048/4096 Columns CPU Address Line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Row[11:0] Bk[1:0] Column[8:0] M0 Row[11:0] Bk[1:0] Column[9:0] M0 Row[11:0] Bk[1:0] Column[10:0] M0 Row[11:0] Bk[1:0] Column[11:0] M0 Table 31-7. Interleaved Mapping for SDRAM Configuration: 8K Rows, 512/1024/2048/4096 Columns CPU Address Line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Row[12:0] Bk[1:0] Column[8:0] M0

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 459 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

31.6.2 SDRAM Address Mapping for 16-bit Memory Data Bus Width and Eight Banks

Row[12:0] Bk[1:0] Column[9:0] M0 Row[12:0] Bk[1:0] Column[10:0] M0 Row[12:0] Bk[1:0] Column[11:0] M0 Table 31-7. Interleaved Mapping for SDRAM Configuration: 8K Rows, 512/1024/2048/4096 Columns CPU Address Line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 31-8. Interleaved Mapping for SDRAM Configuration: 16K Rows, 512/1024/2048 Columns CPU Address Line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Row[13:0] Bk[1:0] Column[8:0] M0 Row[13:0] Bk[1:0] Column[9:0] M0 Row[13:0] Bk[1:0] Column[10:0] M0 Table 31-9. Linear Mapping for SDRAM Configuration: 8K Rows, 1024 Columns CPU Address Line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bk[2:0] Row[12:0] Column[9:0] M0 Table 31-10. Linear Mapping for SDRAM Configuration: 16K Rows, 1024 Columns CPU Address Line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bk[2:0] Row[13:0] Column[9:0] M0 Table 31-11. Interleaved Mapping for SDRAM Configuration: 8K Rows, 1024 Columns CPU Address Line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Row[12:0] Bk[2:0] Column[9:0] M0 Table 31-12. Interleaved Mapping for SDRAM Configuration: 16K Rows, 1024 Columns CPU Address Line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Row[12:0] Bk[2:0] Column[9:0] M0

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 460 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

31.6.3 SDR-SDRAM Address Mapping for 32-bit Memory Data Bus Width

Notes: 1. M[1:0] is the byte address inside a 32-bit word. 2. Bk[1] = BA1, Bk[0] = BA0 Table 31-13. SDR-SDRAM Configuration Mapping: 2K Rows, 256/512/1024/2048 Columns CPU Address Line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bk[1:0] Row[10:0] Column[7:0] M[1:0] Bk[1:0] Row[10:0] Column[8:0] M[1:0] Bk[1:0] Row[10:0] Column[9:0] M[1:0] Bk[1:0] Row[10:0] Column[10:0] M[1:0] Table 31-14. SDR-SDRAM Configuration Mapping: 4K Rows, 256/512/1024/2048 Columns CPU Address Line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bk[1:0] Row[11:0] Column[7:0] M[1:0] Bk[1:0] Row[11:0] Column[8:0] M[1:0] Bk[1:0] Row[11:0] Column[9:0] M[1:0] Bk[1:0] Row[11:0] Column[10:0] M[1:0] Table 31-15. SDR-SDRAM Configuration Mapping: 8K Rows, 256/512/1024/2048 Columns CPU Address Line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bk[1:0] Row[12:0] Column[7:0] M[1:0] Bk[1:0] Row[12:0] Column[8:0] M[1:0] Bk[1:0] Row[12:0] Column[9:0] M[1:0] Bk[1:0] Row[12:0] Column[10:0] M[1:0]

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 461 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

31.7 DDR SDR SDRAM Controller (DDRSDRC) User Interface

The User Interface is connected to the APB bus. The DDRSDRC is programmed using the registers listed in Table 31-16 Table 31-16. Register Mapping Offset Register Name Access Reset 0x00 DDRSDRC Mode Register DDRSDRC_MR Read-write 0x00000000 0x04 DDRSDRC Refresh Timer Register DDRSDRC_RTR Read-write 0x00000000 0x08 DDRSDRC Configuration Register DDRSDRC_CR Read-write 0x7024 0x0C DDRSDRC Timing Parameter 0 Register DDRSDRC_TPR0 Read-write 0x20227225 0x10 DDRSDRC Timing Parameter 1 Register DDRSDRC_TPR1 Read-write 0x3c80808 0x14 DDRSDRC Timing Parameter 2 Register DDRSDRC_TPR2 Read-write 0x2062 0x18 Reserved – – – 0x1C DDRSDRC Low-power Register DDRSDRC_LPR Read-write 0x10000 0x20 DDRSDRC Memory Device Register DDRSDRC_MD Read-write 0x10 0x24 DDRSDRC DLL Information Register DDRSDRC_DLL Read-only 0x00000001 0x2C DDRSDRC High Speed Register DDRSDRC_HS Read-write 0x0 0x54-0x58 Reserved - - - 0x60-0xE0 Reserved – – – 0xE4 DDRSDRC Write Protect Mode Register DDRSDRC_WPMR Read-write 0x00000000 0xE8 DDRSDRC Write Protect Status Register DDRSDRC_WPSR Read-only 0x00000000

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 462 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

31.7.1 DDRSDRC Mode Register

Name: DDRSDRC_MR Address: 0xFFFFE800 Access: Read-write Reset: See Table 31-16 This register can only be written if the bit WPEN is cleared in “DDRSDRC Write Protect Mode Register” on page 477.  MODE: DDRSDRC Command Mode This field defines the command issued by the DDRSDRC when the SDRAM device is accessed. This register is used to ini- tialize the SDRAM device and to activate deep power-down mode. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 MODE Description 000 Normal Mode. Any access to the DDRSDRC will be decoded normally. To activate this mode, command must be followed by a write to the SDRAM. 001 The DDRSDRC issues a NOP command when the SDRAM device is accessed regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM. 010 The DDRSDRC issues an “All Banks Precharge” command when the SDRAM device is accessed regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM. 011 The DDRSDRC issues a “Load Mode Register” command when the SDRAM device is accessed regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM. 100 The DDRSDRC issues an “Auto-Refresh” Command when the SDRAM device is accessed regardless of the cycle. Previously, an “All Banks Precharge” command must be issued. To activate this mode, command must be followed by a write to the SDRAM. 101 The DDRSDRC issues an “Extended Load Mode Register” command when the SDRAM device is accessed regardless of the cycle. To activate this mode, the “Extended Load Mode Register” command must be followed by a write to the SDRAM. The write in the SDRAM must be done in the appropriate bank.

110 Deep power mode: Access to deep power-down mode

111 Reserved

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 463 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

31.7.2 DDRSDRC Refresh Timer Register

Name: DDRSDRC_RTR Address: 0xFFFFE804 Access: Read-write Reset: See Table 31-16 This register can only be written if the bit WPEN is cleared in “DDRSDRC Write Protect Mode Register” on page 477.  COUNT: DDRSDRC Refresh Timer Count This 12-bit field is loaded into a timer which generates the refresh pulse. Each time the refresh pulse is generated, a refresh sequence is initiated. SDRAM devices require a refresh of all rows every 64 ms. The value to be loaded depends on th e DDRSDRC clock fre- quency (MCK: Master Clock) and the number of rows in the device. For example, for an SDRAM with 8192 rows and a 100 MHz Ma ster clock, the value of Refresh Timer Count bit is pro- grammed: (((64 x 10-3)/8192) x100 x106 = 781 or 0x030D. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 –––– COUNT 76543210 COUNT

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 464 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

31.7.3 DDRSDRC Configuration Register

Name: DDRSDRC_CR Address: 0xFFFFE808 Access: Read-write Reset: See Table 31-16 This register can only be written if the bit WPEN is cleared in “DDRSDRC Write Protect Mode Register” on page 477.  NC: Number of Column Bits The reset value is 9 column bits. SDR-SDRAM devices with eight columns in 16-bit mode are not supported.  NR: Number of Row Bits The reset value is 12 row bits. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 – DECOD – NB – ACTBST – EBISHARE 15 14 13 12 11 10 9 8 – OCD – – DIS_DLL DIC/DS 76543210 DLL CAS NR NC NC DDR - Column bits SDR - Column bits 00 98 01 10 9 10 11 10 11 12 11 NR Row bits 00 11 01 12 10 13 11 14

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 465 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12  CAS: CAS Latency The reset value is 2 cycles.  DLL: Reset DLL Reset value is 0. This field defines the value of Reset DLL. 0 = Disable DLL reset. 1 = Enable DLL reset. This value is used during the power-up sequence. Note: This field is found only in DDR2-SDRAM devices.  DIC/DS: Output Driver Impedance Control Reset value is 0. This field defines the output drive strength. 0 = Normal driver strength. 1 = Weak driver strength. This value is used during the power-up sequence. This parameter is found in the datasheet as DIC or DS. Note: This field is found only in DDR2-SDRAM devices.  DIS_DLL: Disable DLL Reset value is 0. 0 = Enable DLL 1 = Disable DLL Note: This field is found only in DDR2-SDRAM devices.  OCD: Off-chip Driver Reset value is 7. Note: OCD is NOT supported by the controller, but these values MUST be programmed during the initialization sequence. CAS DDR2 CAS Latency SDR CAS Latency

000 Reserved Reserved

001 Reserved Reserved

010 Reserved 2

100 Reserved Reserved

101 Reserved Reserved

110 Reserved Reserved

111 Reserved Reserved

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 466 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Note: This field is found only in DDR2-SDRAM devices.  EBISHARE: External Bus Interface is Shared The DDR controller embedded in the EBI is used at the same time as another memory controller (SMC,..) Reset value is 0. 0 = Only the DDR controller function is used. 1 = The DDR controller shares the EBI with another memory controller (SMC, NAND,..)  ACTBST: ACTIVE Bank X to Burst Stop Read Access Bank Y Reset value is 0. 0 = After an ACTIVE command in Bank X, BURST STOP command can be issued to another bank to stop current read access. 1 = After an ACTIVE command in Bank X, BURST STOP command cannot be issued to another bank to stop current read access. This field is unique to SDR-SDRAM, Low-power SDR-SDRAM and Low-power DDR1-SDRAM devices.  NB: Number of Banks The reset value is four banks. Note: Only DDR-SDRAM 2 devices support eight internal banks.  DECOD: Type of Decoding The reset value is 0: sequential decoding. 0 = Sequential Decoding. 1 = Interleaved Decoding. OCD

000 OCD calibration mode exit, maintain setting

111 OCD calibration default

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 467 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

31.7.4 DDRSDRC Timing Parameter 0 Register

Name: DDRSDRC_TPR0 Address: 0xFFFFE80C Access: Read-write Reset: See Table 31-16 This register can only be written if the bit WPEN is cleared in “DDRSDRC Write Protect Mode Register” on page 477.  TRAS: Active to Precharge Delay Reset Value is 5 cycles. This field defines the delay between an Activate Command and a Precharge Command in number of cycles. Number of cycles is between 0 and 15.  TRCD: Row to Column Delay Reset Value is 2 cycles. This field defines the delay between an Activate Comman d and a Read/Write Command in number of cycles. Number of cycles is between 0 and 15.  TWR: Write Recovery Delay Reset value is 2 cycles. This field defines the Write Recovery Time in number of cycles. Number of cycles is between 1 and 15.  TRC: Row Cycle Delay Reset value is 7 cycles. This field defines the delay between an Activate command and Refresh command in number of cycles. Number of cycles is between 0 and 15  TRP: Row Precharge Delay Reset Value is 2 cycles. This field defines the delay between a Precharge Command and another command in number of cycles. Number of cycles is between 0 and 15.  TRRD: Active bankA to Active bankB Reset value is 2 cycles. 31 30 29 28 27 26 25 24 TMRD REDUCE_WRRD TWTR 23 22 21 20 19 18 17 16 TRRD TRP 15 14 13 12 11 10 9 8 TRC TWR 76543210 TRCD TRAS

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 468 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 This field defines the delay between an Active command in BankA and an active command in bankB in number of cycles. Number of cycles is between 1 and 15.  TWTR: Internal Write to Read Delay Reset value is 0. This field is unique to Low-power DDR1-SDRAM devices and DDR2-SDRAM devices. This field defines the internal write to read command Time in number of cycles. Number of cycles is between 1 and 7.  REDUCE_WRRD: Reduce Write to Read Delay Reset value is 0. This field reduces the delay between write to read access for low-power DDR-SDRAM devices with a latency equal to 2. To use this feature, TWTR field must be equal to 0. Important to note is that some devices do not support this feature.  TMRD: Load Mode Register Command to Active or Refresh Command Reset Value is 2 cycles. This field defines the delay between a Load mode register command and an active or refresh command in number of cycles. Number of cycles is between 0 and 15.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 469 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

31.7.5 DDRSDRC Timing Parameter 1 Register

Name: DDRSDRC_TPR1 Address: 0xFFFFE810 Access: Read-write Reset: See Table 31-16 This register can only be written if the bit WPEN is cleared in “DDRSDRC Write Protect Mode Register” on page 477.  TRFC: Row Cycle Delay Reset Value is 8 cycles. This field defines the delay between a Refresh and an Activate command or Refresh command in number of cycles. Num- ber of cycles is between 0 and 31  TXSNR: Exit Self Refresh Delay to Non-read Command Reset Value is 8 cycles. This field defines the delay between cke set high and a non Read Command in number of cycles. Number of cycles is between 0 and 255. This field is used for SDR-SDRAM and DD R-SDRAM devices. In the case of SDR-SDRAM devices and Low-power DDR1-SDRAM, this field is equivalent to TXSR timing.  TXSRD: ExiT Self Refresh Delay to Read Command Reset Value is 200 cycles. This field defines the delay between cke set high and a Read Command in number of cycles. Number of cycles is between 0 and 255 cycles.This field is unique to DD R-SDRAM devices. In the case of a Low-power DDR1-SDRAM, this field must be written to 0.  TXP: Exit Power-down Delay to First Command Reset Value is 3 cycles. This field defines the delay between cke set high and a Valid Command in number of cycles. Number of cycles is between 0 and 15 cycles. This field is unique to Low-power DDR1-SDRAM devices and DDR2-SDRAM devices. 31 30 29 28 27 26 25 24 –––– TXP 23 22 21 20 19 18 17 16 TXSRD 15 14 13 12 11 10 9 8 TXSNR 76543210 ––– TRFC

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 470 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

31.7.6 DDRSDRC Timing Parameter 2 Register

Name: DDRSDRC_TPR2 Address: 0xFFFFE814 Access: Read-write Reset: See Table 31-16 This register can only be written if the bit WPEN is cleared in “DDRSDRC Write Protect Mode Register” on page 477.  TXARD: Exit Active Power Down Delay to Read Command in Mode “Fast Exit”. The Reset Value is 2 cycles. This field defines the delay between cke set high and a Read Command in number of cycles. Number of cycles is between 0 and 15. Note: This field is found only in DDR2-SDRAM devices.  TXARDS: Exit Active Power Down Delay to Read Command in Mode “Slow Exit”. The Reset Value is 6 cycles. This field defines the delay between cke set high and a Read Command in number of cycles. Number of cycles is between 0 and 15. Note: This field is found only in DDR2-SDRAM devices.  TRPA: Row Precharge All Delay The Reset Value is 0 cycle. This field defines the delay between a Precharge ALL ba nks Command and another command in number of cycles. Num- ber of cycles is between 0 and 15. Note: This field is found only in DDR2-SDRAM devices.  TRTP: Read to Precharge The Reset Value is 2 cycles. This field defines the delay between Read Command and a Precharge command in number of cycle. Number of cycles is between 0 and 7.  TFAW: Four Active window The Reset Value is 4 cycles. DDR2 devices with 8-banks (1Gb or larger) have an additional requirement: t FAW. This requires that no more than four ACTIVATE commands may be issued in any given tFAW (MIN) period. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 –– –– TFAW 15 14 13 12 11 10 9 8 TRTP TRPA 76543210 TXARDS TXARD

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 471 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Number of cycles is between 0 and 15. Note: This field is found only in DDR-SDRAM 2 devices with eight internal banks

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 472 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

31.7.7 DDRSDRC Low-power Register

Name: DDRSDRC_LPR Address: 0xFFFFE81C Access: Read-write Reset: See Table 31-16  LPCB: Low-power Command Bit Reset value is “00”. 00 = Low-power Feature is inhibited: no power-down, self refresh and Deep power mode are issued to the SDRAM device. 01 = The DDRSDRC issues a Self Refresh Command to the S DRAM device, the clock(s) is/are de-activated and the CKE signal is set low. The SDRAM device leaves the self refresh mode when accessed and enters it after the access. 10 = The DDRSDRC issues a Power-down Command to the SDRAM device after each access, the CKE signal is set low. The SDRAM device leaves the power-down mode when accessed and enters it after the access. 11 = The DDRSDRC issues a Deep Power-down Command to the Low-power SDRAM device.This mode is unique to Low-power SDRAM devices.  CLK_FR: Clock Frozen Command Bit Reset value is “0”. This field sets the clock low during power-down mode or during deep power-down mode. Some SDRAM devices do not support freezing the clock during power-down mode or during deep power-down mode. Refer to the SDRAM device datasheet for details on this. 1 = Clock(s) is/are frozen. 0 = Clock(s) is/are not frozen.  PASR: Partial Array Self Refresh Reset value is “0”. This field is unique to Low-power SDRAM. It is used to specify whether only one quarter, one half or all banks of the SDRAM array are enabled. Disabled banks are not refreshed in self refresh mode. The values of this field are dependant on Low-power SDRAM devices. After the initialization sequence, as soon as PASR field is modified, Extended Mode Register in the external device mem- ory is accessed automatically and PASR bits are updated. In function of the UPD_MR bit, update is done before entering in self refresh mode or during a refresh command and a pending read or write access. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 –– T IMEOUT – DS 76543210 – PASR CLK_FR LPCB

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 473 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12  DS: Drive Strength Reset value is “0”. This field is unique to Low-power SDRAM. It selects the driver strength of SDRAM output. After the initialization sequence, as soon as DS field is mo dified, Extended Mode Register is accessed automatically and DS bits are updated. In function of UPD_MR bit, update is done before entering in self refresh mode or during a refresh command and a pending read or write access.  TIMEOUT: Low Power Mode Reset value is “00”. This field defines when low-power mode is enabled.  APDE: Active Power Down Exit Time Reset value is “1”. This mode is unique to DDR2-SDRAM devices. This mode allows to determine the active power-down mode, which determines performance versus power saving. 0 = Fast Exit 1 = Slow Exit After the initialization sequence, as soon as APDE field is modified Extended Mode Register, located in the memory of the external device, is accessed automatically and APDE bits are updated. In function of the UPD_MR bit, update is done before entering in self refresh mode or during a refresh command and a pending read or write access  UPD_MR: Update Load Mode Register and Extended Mode Register Reset value is “0”. This bit is used to enable or disable automatic update of the Load Mode Register and Extended Mode Register. This update is function of DDRSDRC integration in a system. D DRSDRC can either share or not share an external bus with another controller. 00 The SDRAM controller activates the SDRAM low-power mode immediately after the end of the last transfer. 01 The SDRAM controller activates the SDRAM low-power mode 64 clock cycles after the end of the last transfer. 10 The SDRAM controller activates the SDRAM low-power mode 128 clock cycles after the end of the last transfer. 00 Update is disabled. 01 DDRSDRC shares external bus. Automatic update is done during a refresh command and a pending read or write access in SDRAM device. 10 DDRSDRC does not share external bus. Automatic update is done before entering in self refresh mode.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 474 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

31.7.8 DDRSDRC Memory Device Register

Name: DDRSDRC_MD Address: 0xFFFFE820 Access: Read-write Reset: See Table 31-16 This register can only be written if the bit WPEN is cleared in “DDRSDRC Write Protect Mode Register” on page 477.  MD: Memory Device Indicates the type of memory used. Reset value is for SDR-SDRAM device. 000 = SDR-SDRAM 001 = Low-power SDR-SDRAM 010 = Reserved 011 = Low-power DDR1-SDRAM 110 = DDR2-SDRAM  DBW: Data Bus Width Reset value is 16 bits. 0 = Data bus width is 32 bits (reserved for SDR-SDRAM device). 1 = Data bus width is 16 bits. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 ––– D BW – MD

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 475 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

31.7.9 DDRSDRC DLL Register

Name: DDRSDRC_DLL Address: 0xFFFFE824 Access: Read-only Reset: See Table 31-16 The DLL logic is internally used by the controller in order to delay DQS inputs. This is necessary to center the strobe time and the data valid window.  MDINC: DLL Master Delay Increment 0 = The DLL is not incrementing the Master delay counter. 1 = The DLL is incrementing the Master delay counter.  MDDEC: DLL Master Delay Decrement 0 = The DLL is not decrementing the Master delay counter. 1 = The DLL is decrementing the Master delay counter. M D O V F: DLL Master Delay Overflow Flag 0 = The Master delay counter has not reached its maximum value, or the Master is not locked yet. 1 = The Master delay counter has reached its maximum value, the Master delay counter increment is stopped and the DLL forces the Master lock. If this flag is set, it means the DDRSDRC clock frequency is too low compared to Master delay line number of elements. M D V A L: DLL Master Delay Value Value of the Master delay counter. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 MDVAL 76543210 ––––– M DOVF M DDEC M DINC

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 476 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

31.7.10 DDRSDRC Hi gh Speed Register

Name: DDRSDRC_HS Address: 0xFFFFE82C Access: Read-write Reset: See Table 31-16 This register can only be written if the bit WPEN is cleared in “DDRSDRC Write Protect Mode Register” on page 477.  DIS_ANTICIP_READ: Anticip Read Access 0 = anticip read access is enabled. 1 = anticip read access is disabled (default). DIS_ANTICIP_READ allows DDR2 read access optimization with multi-port. As this feature is based on the “bank open policy”, the software must map different buffers in different DDR2 banks to take advantage of that feature. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 AD ––

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 477 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

31.7.11 DDRSDRC Write Protect Mode Register

Name: DDRSDRC_WPMR Address: 0xFFFFE8E4 Access: Read-write Reset: See Table 31-16  WPEN: Write Protect Enable 0 = Disables the Write Protect if WPKEY corresponds to 0x444452 (“DDR” in ASCII). 1 = Enables the Write Protect if WPKEY corresponds to 0x444452 (“DDR” in ASCII). Protects the registers:

  • “DDRSDRC Mode Register” on page 462
  • “DDRSDRC Refresh Timer Register” on page 463
  • “DDRSDRC Configuration Register” on page 464
  • “DDRSDRC Timing Parameter 0 Register” on page 467
  • “DDRSDRC Timing Parameter 1 Register” on page 469
  • “DDRSDRC Timing Parameter 2 Register” on page 470
  • “DDRSDRC Memory Device Register” on page 474
  • “DDRSDRC High Speed Register” on page 476  WPKEY: Write Protect KEY Should be written at value 0x444452 (“DDR” in ASCII). Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. 31 30 29 28 27 26 25 24 WPKEY 23 22 21 20 19 18 17 16 WPKEY 15 14 13 12 11 10 9 8 WPKEY 76543210

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 478 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

31.7.12 DDRSDRC Write Protect Status Register

Name: DDRSDRC_WPSR Address: 0xFFFFE8E8 Access: Read-only Reset: See Table 31-16  WPVS: Write Protect Violation Status 0 = No Write Protect Violation has occurred since the last read of the DDRSDRC_WPSR register. 1 = A Write Protect Violation has occurred since the last read of the DDRSDRC_WPSR register. If this violation is an unau- thorized attempt to write a protected register, the associated violation is reported into field WPVSRC.  WPVSRC: Write Protect Violation Source When WPVS is active, this field indicates the write-protected register (t hrough address offset or code) in which a write access has been attempted. Note: Reading DDRSDRC_WPSR automatically clears all fields. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WPVSRC 15 14 13 12 11 10 9 8 WPVSRC 76543210

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 479 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 32. DMA Controller (DMAC)

32.1 Description

The DMA Controller (DMAC) is an AHB-central DMA controller core that transfers data from a source peripheral to a destination peripheral over one or more AMBA buses. One channel is required for each source/destination pair. In the most basic configuration, the DMAC has one master interface and one channel. The master interface reads the data from a source and writes it to a destination. Two AMBA transfers are required for each DMAC data transfer. This is also known as a dual-access transfer. The DMAC is programmed via the APB interface. The DMAC embeds 8 channels:

32.2 Embedded Characteristics

  • Two Masters
  • Embeds 8 channels
  • 16-byte FIFO for Channel 0 to 7
  • F e a t u r e s : – Linked List support with Status Write Back operation at End of Transfer – Word, HalfWord, Byte transfer support. – memory to memory transfer – Peripheral to memory – Memory to peripheral The DMA controller can handle the transfer between peripherals and memory and so receives the triggers from the peripherals below. The hardware interface numbers are also given in Table 32-1. DMAC Channel Number FIFO Size 01 6 11 6 21 6 31 6 41 6 51 6 61 6 71 6

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 480 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Table 32-1. DMA Channel definition Instance name T/R DMA Channel HW interface Number HSMCI RX/TX 0 SPI0 TX 1 SPI0 RX 2 SPI1 TX 3 SPI1 RX 4 USART0 TX 5 USART0 RX 6 USART1 TX 7 USART1 RX 8 USART2 TX 9 USART2 RX 10 USART3 TX 11 USART3 RX 12 TWI0 TX 13 TWI0 RX 14 TWI1 TX 15 TWI1 RX 16 UART0 TX 17 UART0 RX 18 UART1 TX 19 UART1 RX 20 SSC TX 21 SSC RX 22 ADC RX 23 DBGU TX 24 DBGU RX 25 AES TX 26 AES RX 27 SHA TX 28

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 481 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

32.3 Block Diagram

Figure 32-1. DMA Controller (DMAC) Block Diagram DMA Destination DMA Channel 0 DMA Destination Control State Machine Destination Pointer Management DMA Source Control State Machine Source Pointer Management DMA FIFO Controller DMA FIFO Up to 64 bytes DMA Channel 0 Read data path from source DMA Channel 0 Write data path to destination DMA Channel 1 DMA Channel 2 DMA Channel n External Triggers Soft Triggers DMA REQ/ACK Interface Trigger Manager DMA Interrupt Controller Status Registers Configuration Registers Atmel APB rev2 Interface DMA AHB Lite Master Interface 0 DMA AHB Lite Master Interface 1 DMA Global Control and Data Mux DMA Global Request Arbiter DMA Global Control and Data Mux DMA Global Request Arbiter DMA Destination Requests Pool DMA Write Datapath Bundles DMA Source Requests Pool DMA Read Datapath Bundles DMA Atmel APB Interface DMA Interrupt DMA Hardware Handshaking Interface AMBA AHB Layer 0 AMBA AHB Layer 1

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 482 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

32.4 Functional Description

32.4.1 Basic Definitions

Source peripheral: Device on an AMBA layer from where the DMAC reads data, which is then stored in the channel FIFO. The source peripheral teams up with a destination peripheral to form a channel. Destination peripheral: Device to which the DMAC writes the stored data from the FIFO (previ- ously read from the source peripheral). Memory: Source or destination that is always “ready” for a DMAC transfer and does not require a handshaking interface to interact with the DMAC. Programmable Arbitration Policy: Modified Round Robin and Fixed Priority are available by means of the ARB_CFG bit in the Global Confi guration Register (DMAC_GCFG). The fixed pri- ority is linked to the channel number. The highest DMAC channel number has the highest priority. Channel: Read/write datapath between a source peripheral on one configured AMBA layer and a destination peripheral on the same or different AMBA layer that occurs through the channel FIFO. If the source peripheral is not memory, then a source handshaking interface is assigned to the channel. If the destination peripheral is not memory, then a destination handshaking inter- face is assigned to the channel. Source and destination handshaking interfaces can be assigned dynamically by programming the channel registers. Master interface: DMAC is a master on the AHB bus reading data from the source and writing it to the destination over the AHB bus. Slave interface: The APB interface over which the DMAC is programmed. The slave interface in practice could be on the same layer as any of the master interfaces or on a separate layer. Handshaking interface: A set of signal registers that conform to a protocol and handshake between the DMAC and source or destination peripheral to control the transfer of a single or chunk transfer between them. This interface is used to request, acknowledge, and control a DMAC transaction. A channel can receive a r equest through one of two types of handshaking interface: hardware or software. Hardware handshaking interface: Uses hardware signals to control the transfer of a single or chunk transfer between the DMAC and the source or destination peripheral. Software handshaking interface: Uses software registers to control the transfer of a single or chunk transfer between the DMAC and the source or destination peripheral. No special DMAC handshaking signals are needed on the I/O of the peripheral. This mode is useful for interfacing an existing peripheral to the DMAC without modifying it. Flow controller: The device (either the DMAC or source/destination peripheral) that determines the length of and terminates a DMAC buffer transfer. If the length of a buffer is known before enabling the channel, then the DMAC should be programmed as the flow controller. If the length of a buffer is not known prior to enabling the channel, the source or destination peripheral needs to terminate a buffer transfer. In this mode, the peripheral is the flow controller. Transfer hierarchy: Figure 32-2 on page 483 illustrates the hierarchy between DMAC transfers, buffer transfers, chunk or single, and AMBA transfers (single or burst) for non-memory peripher- als. Figure 32-3 on page 483 shows the transfer hierarchy for memory.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 485 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Channel locking: Software can program a channel to keep the AHB master interface by locking the arbitration for the master bus interface for the duration of a DMAC transfer, buffer, or chunk. Bus locking: Software can program a channel to maintain control of the AMBA bus by asserting hmastlock for the duration of a DMAC transfer, buffer, or transaction (single or chunk). Channel locking is asserted for the duration of bus locking at a minimum.

32.4.2 Memory Peripherals

Figure 32-3 on page 483 shows the DMAC transfer hierarchy of the DMAC for a memory periph- eral. There is no handshaking interface with the DMAC, and therefore the memory peripheral can never be a flow controller. Once the channel is enabled, the transfer proceeds immediately without waiting for a transaction request. The alternative to not having a transaction-level hand- shaking interface is to allow the DMAC to at tempt AMBA transfers to the peripheral once the channel is enabled. If the peripheral slave cannot accept these AMBA transfers, it inserts wait states onto the bus until it is ready; it is not recommended that more than 16 wait states be inserted onto the bus. By using the handshaking interface, the peripheral can signal to the DMAC that it is ready to transmit/receive dat a, and then the DMAC can access the peripheral without the peripheral inserting wait states onto the bus.

32.4.3 Handshaking Interface

Handshaking interfaces are used at the transaction level to control the flow of single or chunk transfers. The operation of the handshaking interface is different and depends on whether the peripheral or the DMAC is the flow controller. The peripheral uses the handshaking interface to indicate to the DMAC that it is ready to trans- fer/accept data over the AMBA bus. A non-memory peripheral can request a DMAC transfer through the DMAC using one of two handshaking interfaces:

  • Hardware handshaking
  • Software handshaking Software selects between the hardware or software handshaking interface on a per-channel basis. Software handshaking is accomplished through memory-mapped registers, while hard- ware handshaking is accomplished using a dedicated handshaking interface.

32.4.3.1 Software Handshaking

When the slave peripheral requires the DMAC to perform a DMAC transaction, it communicates this request by sending an interrupt to the CPU or interrupt controller. The interrupt service routine then uses the software registers to initiate and control a DMAC transaction. These software registers are used to implement the software handshaking interface. The SRC_H2SEL/DST_H2SEL bit in the DMAC_CFGx channel c onfiguration register must be set to zero to enable software handshaking. When the peripheral is not the flow controller, then the last transaction register DMAC_LAST is not used, and the values in these registers are ignored. Chunk Transactions Writing a 1 to the DMAC_CREQ[2x] register starts a source chunk transaction request, where x is the channel number. Writing a 1 to the DMAC_CREQ[2x+1] register starts a destination chunk transfer request, where x is the channel number.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 486 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Upon completion of the chunk transaction, the hardware clears the DMAC_CREQ[ 2x] or DMAC_CREQ[2x+1]. Single Transactions Writing a 1 to the DMAC_SREQ[2x] register starts a source single transaction request, where x is the channel number. Writing a 1 to the DMAC_SREQ[2x+1] register starts a destination single transfer request, where x is the channel number. Upon completion of the chunk transaction, the hardware clears the DMAC_SREQ[x] or DMAC_SREQ[2x+1]. The software can poll the relevant channel bit in the DMAC_CREQ[2x]/DMAC_CREQ[2x+1] and DMAC_SREQ[x]/DMAC_SREQ[2x+1] registers. When both are 0, then either the requested chunk or single transaction has completed.

32.4.4 DMAC Transfer Types

A DMAC transfer may consist of single or multi-buffer transfers. On successive buffers of a multi-buffer transfer, the DMAC_SADDRx/DMAC_DADDRx registers in the DMAC are repro- grammed using either of the following methods:

  • Buffer chaining using linked lists
  • Replay mode
  • Contiguous address between buffers On successive buffers of a multi-buffer transfer, the DMAC_CTRLAx and DMAC_CTRLBx regis- ters in the DMAC are re-programmed using either of the following methods:
  • Buffer chaining using linked lists
  • Replay mode When buffer chaining using linked lists is the mu lti-buffer method of choice, and on successive buffers, the DMAC_DSCRx register in the DMAC is re-programmed using the following method:
  • Buffer chaining using linked lists A buffer descriptor (LLI) consists of foll owing registers, DMAC_SADDRx, DMAC_DADDRx, DMAC_DSCRx, DMAC_CTRLAx, DMAC_CTRLB x.These registers, along with the DMAC_CFGx register, are used by the DMAC to set up and describe the buffer transfer.

32.4.4.1 Multi-buffer Transfers

Buffer Chaining Using Linked Lists In this case, the DMAC re-programs the channel registers prior to the start of each buffer by fetching the buffer descriptor for that buffer from system memory. This is known as an LLI update. DMAC buffer chaining is supported by using a Descriptor Pointer register (DMAC_DSCRx) that stores the address in memory of the next buffer descriptor. Each buffer descriptor contains the corresponding buffer descriptor (DMA C_SADDRx, DMAC_DADDRx, DMAC_DSCRx, DMAC_CTRLAx DMAC_CTRLBx). To set up buffer chaining, a sequence of linked lists must be programmed in memory. The DMAC_SADDRx, DMAC_DADDRx, DMAC_DSCRx, DMAC_CTRLAx and DMAC_CTRLBx registers are fetched from system memory on an LLI update. The u pdated content of the DMAC_CTRLAx register is written back to memory on buffer completion. Figure 32-5 on page

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 487 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 487 shows how to use chained linked lists in memory to define multi-buffer transfers using buffer chaining. The Linked List multi-buffer transfer is init iated by programming DMAC_DSCRx with DSCRx(0) (LLI(0) base address) different from zero. Other fields and registers are ignored and overwritten when the descriptor is retrieved from memory. The last transfer descriptor must be written to memory with its next descriptor address set to 0. Figure 32-5. Multi Buffer Transfer Using Linked List Descriptor Integrity Check When the Descriptor Integrity Check is enabled, a cyclic redundancy check information is attached to the descriptor. When fetched from the memory, the descriptor is verified through the use of a CRC16-CCIT (0x1021 polynom) by the DMAC channel. If a CRC error is detected, then the DICERR flag is set in the DMAC_EBCISR re gister. The CRC16 is computed from MSB to LSB. The BTSIZE and DONE fields of the DMAC_CTRLAx register are ignored and set to zero. System Memory SADDRx= DSCRx(0) + 0x0 DADDRx= DSCRx(0) + 0x4 CTRLAx= DSCRx(0) + 0x8 CTRLBx= DSCRx(0) + 0xC DSCRx(1)= DSCRx(0) + 0x10 SADDRx= DSCRx(1) + 0x0 DADDRx= DSCRx(1) + 0x4 CTRLBx= DSCRx(1) + 0x8 CTRLBx= DSCRx(1) + 0xC DSCRx(2)= DSCRx(1) + 0x10 DSCRx(0) DSCRx(2) (points to 0 if LLI(1) is the last transfer descriptor DSCRx(1) LLI(0) LLI(1)

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 488 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Figure 32-6. Linked List with CRC16 Attached System Memory SADDRx= DSCRx(0) + 0x0 DADDRx= DSCRx(0) + 0x4 CTRLAx= DSCRx(0) + 0x8 CTRLBx= DSCRx(0) + 0xC DSCRx(1)= DSCRx(0) + 0x10 SADDRx= DSCRx(1) + 0x0 DADDRx= DSCRx(1) + 0x4 CTRLBx= DSCRx(1) + 0x8 CTRLBx= DSCRx(1) + 0xC DSCRx(2)= DSCRx(1) + 0x10 DSCRx(0) DSCRx(2) (points to 0 if LLI(1) is the last transfer descriptor DSCRx(1) LLI(0) LLI(1) CRCx(1)= DSCRx(0) + 0x14 CRCx(2)= DSCRx(1) + 0x14

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 489 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

32.4.4.2 Programming DMAC for Multiple Buffer Transfers

Notes: 1. USR means that the register field is manually programmed by the user. 2. CONT means that address are contiguous. 3. REP means that the register field is updat ed with its previous value. If the transfer is the first one, then the user must manu- ally program the value. 4. Channel stalled is true if the relevant BTC interrupt is not masked. 5. LLI means that the register field is updat ed with the content of the linked list item. Replay Mode of Channel Registers During automatic replay mode, the channel registers are reloaded with their initial values at the completion of each buffer and the new values used for the new buffer. Depending on the row number in Table 32-2 on page 489 , some or all of the DMAC_SADDRx, DMAC_DADDRx, DMAC_CTRLAx and DMAC_CTRLBx channel register s are reloaded from their initial value at the start of a buffer transfer. Contiguous Address Between Buffers In this case, the address between successive buffers is selected to be a continuation from the end of the previous buffer. Enabling the source or destination address to be contiguous between Table 32-2. Multiple Buffers Transfer Management Table Transfer Type AUTO SRC_REP DST_REP SRC_DSCR DST_DSCR BTSIZE DSCR SADDR DADDR Other Fields 1) Single Buffer or Last buffer of a multiple buffer transfer 0 – – – – USR 0 USR USR USR 2) Multi Buffer transfer with contiguous DADDR 0 – 0 0 1 LLI USR LLI CONT LLI 3) Multi Buffer transfer with contiguous SADDR 0 0 – 1 0 LLI USR CONT LLI LLI 4) Multi Buffer transfer with LLI support 0 – – 0 0 LLI USR LLI LLI LLI 5) Multi Buffer transfer with DADDR reloaded 0 – 1 0 1 LLI USR LLI REP LLI 6) Multi Buffer transfer with SADDR reloaded 0 1 – 1 0 LLI USR REP LLI LLI 7) Multi Buffer transfer with BTSIZE reloaded and contiguous DADDR 1 – 0 0 1 REP USR LLI CONT LLI 8) Multi Buffer transfer with BTSIZE reloaded and contiguous SADDR 1 0 – 1 0 REP USR CONT LLI LLI 9) Automatic mode channel is stalling BTsize is reloaded 1 0 0 1 1 REP USR CONT CONT REP 10) Automatic mode BTSIZE, SADDR and DADDR reloaded 1 1 1 1 1 REP USR REP REP REP 11) Automatic mode BTSIZE, SADDR reloaded and DADDR contiguous 1 1 0 1 1 REP USR REP CONT REP

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 490 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 buffers is a function of DMAC_C TRLAx.SRC_DSCR, DMAC_CFGx.DST_REP, DMAC_CFGx.SRC_REP and DMAC_CTRLAx.DST_DSCR registers. Suspension of Transfers Between Buffers At the end of every buffer transfer, an end of buffer interrupt is asserted if:

  • the channel buffer interrupt is unmasked, DMAC_EBCIMR.BTCx = ‘1’, where x is the channel number. Note: The Buffer Transfer Completed Interrupt is generated at the completion of the buffer transfer to the destination. At the end of a chain of multiple buffers, an end of linked list interrupt is asserted if:
  • the channel end of the Chained Buffer Transfer Completed Interrupt is unmasked, DMAC_EBCIMR.CBTCx = ‘1’, when n is the channel number.

32.4.4.3 Ending Multi-buffer Transfers

All multi-buffer transfers must end as shown in Row 1 of Table 32-2 on page 489. At the end of every buffer transfer, the DMAC samples the row number, and if the DMAC is in Row 1 state, then the previous buffer transferred was the last buffer and the DMAC transfer is terminated. For rows 9, 10 and 11 of Table 32-2 on page 489 , (DMAC_DSCRx = 0 and DMAC_CTRLBx.AUTO is set), multi-buffer DMAC transfers continue until the automatic mode is disabled by writing a ‘1’ in DM AC_CTRLBx.AUTO bit. This bit should be programmed to zero in the end of buffer interrupt service routine that services the next-to-last buffer transfer. This puts the DMAC into Row 1 state. For rows 2, 3, 4, 5, and 6 (DMAC_CRTLBx.AUTO cleared), the user must set up the last buffer descriptor in memory so that both LLI.DMAC_CTRLBx.SRC_DSCR and LLI.DMAC_CTRLBx.DST_DSCR are one and LLI.DMAC_DSCRx is set to 0. For rows 2, 3, 4, 5, and 6 (DMAC_CRTLBx.AUTO cleared), the user must set up the last buffer descriptor in memory so that LLI.DMAC_CTRLBx.SRC_DSCR is set to 0.

32.4.5 Programming a Channel

Four registers, the DMAC_DSCRx, the DMAC_CTRLAx, the DMAC_CTRLBx and DMAC_CFGx, need to be programmed to set up whether single or multi-buffer transfers take place, and which type of multi-buffer transfer is used. The different transfer types are shown in Table 32-2 on page 489. The “BTSIZE, SADDR and DADDR” columns in dicate where the values of DMAC_SARx, DMAC_DARx, DMAC_CTLx, and DMAC_LLPx are obtained for the next buffer transfer when multi-buffer DMAC transfers are enabled.

32.4.5.1 Programming Examples

Single-buffer Transfer (Row 1) 1. Read the Channel Handler Status Register DMAC_CHSR.ENAx Field to choose a free (disabled) channel. 2. Clear any pending interrupts on the channel from the previous DMAC transfer by read- ing the interrupt status register, DMAC_EBCISR. 3. Program the following channel registers:

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 491 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 a. Write the starting source address in the DMAC_SADDRx register for channel x. b. Write the starting destination address in the DMAC_DADDRx register for channel x. c. Write the next descriptor address in the DMA_DSCRx register for channel x with 0x0. d. Program DMAC_CTRLAx, DMAC_CTRLBx and DMAC_CFGx according to Row 1 as shown in Table 32-2 on page 489. Program the DMAC_CTRLBx register with both AUTO fields set to 0. e. Write the control information for the DMAC transfer in the DMAC_CTRLAx and DMAC_CTRLBx registers for channel x. For example, in the register, you can pro- gram the following: – i. Set up the transfer type (memory or non-memory peripheral for source and destination) and flow control device by programming the FC of the DMAC_CTRLBx register. – ii. Set up the transfer characteristics, such as: – Transfer width for the source in the SRC_WIDTH field. – Transfer width for the destination in the DST_WIDTH field. – Source AHB Master interface layer in the SIF field where source resides. – Destination AHB Master Interface layer in the DIF field where destination resides. – Incrementing/decrementing or fixed address for source in SRC_INC field. – Incrementing/decrementing or fixed address for destination in DST_INC field. f. Write the channel configuration information into the DMAC_CFGx register for chan- nel x. – i. Designate the handshaking interface type (hardware or software) for the source and destination peripherals. This is not required for memory. This step requires programming the SRC_H2SEL/DST_H2SEL bits, respectively. Writing a ‘1’ activates the hardware handshaking interface to handle source/destination requests. Writing a ‘0’ activates the software handshaking interface to handle source/destination requests. – ii. If the hardware handshaking interface is activated for the source or destination peripheral, assign a handshaking interface to the source and destination peripheral. This requires programming the SRC_PER and DST_PER bits, respectively. g. If source Picture-in-Picture mode is enabled (DMAC_CTRLBx.SRC_PIP is enabled), program the DMAC_SPIPx register for channel x. h. If destination Picture-in-Picture mode is enabled (DMAC_CTRLBx.DST_PIP is enabled), program the DMAC_DPIPx register for channel x. 4. After the DMAC selected channel has been programmed, enable the channel by writing a ‘1’ to the DMAC_CHER.ENAx bit, where x is the channel number. Make sure that bit 0 of DMAC_EN.ENABLE register is enabled. 5. Source and destination request single and chunk DMAC transactions to transfer the buffer of data (assuming non-memory peripherals). The DMAC acknowledges at the completion of every transaction (chunk and single) in the buffer and carries out the buf- fer transfer. 6. Once the transfer completes, the hardware sets the interrupts and disables the chan- nel. At this time, you can either respond to the Buffer Transfer Completed Interrupt or Chained Buffer Transfer Completed Interrupt, or poll for the Channel Handler Status

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 492 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Register (DMAC_CHSR.ENAx) bit until it is cleared by hardware, to detect when the transfer is complete. Multi-buffer Transfer with Linked List for Source and Linked List for Destination (Row 4) 1. Read the Channel Handler Status register to choose a free (disabled) channel. 2. Set up the chain of Linked List Items (otherwise known as buffer descriptors) in mem- ory. Write the control information in the LLI.DMAC_CTRLAx and LLI.DMAC_CTRLBx registers location of the buffer descriptor for each LLI in memory (see Figure 32-7 on page 494) for channel x. For example, in the register, you can program the following: a. Set up the transfer type (memory or non-memory peripheral for source and desti- nation) and flow control device by programming the FC of the DMAC_CTRLBx register. b. Set up the transfer characteristics, such as: – i. Transfer width for the source in the SRC_WIDTH field. – ii. Transfer width for the destination in the DST_WIDTH field. – iii. Source AHB master interface layer in the SIF field where source resides. – iv. Destination AHB master interface layer in the DIF field where destination resides. – v. Incrementing/decrementing or fixed address for source in SRC_INCR field. – vi. Incrementing/decrementing or fixed address for destination DST_INCR field. 3. Write the channel configuration information into the DMAC_CFGx register for channel x. a. Designate the handshaking interface type (hardware or software) for the source and destination peripherals. This is not required for memory. This step requires pro- gramming the SRC_H2SEL/DST_H2SEL bits, respectively. Writing a ‘1’ activates the hardware handshaking interface to handle source/destination requests for the specific channel. Writing a ‘0’ activates the software handshaking interface to han- dle source/destination requests. b. If the hardware handshaking interface is activated for the source or destination peripheral, assign the handshaking interface to the source and destination periph- eral. This requires programming the SRC_PER and DST_PER bits, respectively. 4. Make sure that the LLI.DMAC_CTRLBx register locations of all LLI entries in memory (except the last) are set as shown in Row 4 of Table 32-2 on page 489. The LLI.DMAC_CTRLBx register of the last Linked List Item must be set as described in Row 1 of Table 32-2. Figure 32-5 on page 487 shows a Linked List example with two list items. 5. Make sure that the LLI.DMAC_DSCRx register locations of all LLI entries in memory (except the last) are non-zero and point to the base address of the next Linked List Item. 6. Make sure that the LLI.DMAC_SADDRx/LLI. DMAC_DADDRx register locations of all LLI entries in memory point to the start source/destination buffer address preceding that LLI fetch. 7. Make sure that the LLI.DMAC_CTRLAx.DONE field of the LLI.DMAC_CTRLAx register locations of all LLI entries in memory are cleared. 8. If source Picture-in-Picture mode is enabled (DMAC_CTRLBx.SRC_PIP is enabled), program the DMAC_SPIPx register for channel x. 9. If destination Picture-in-Picture is enabled (DMAC_CTRLBx.DST_PIP is enabled), pro- gram the DMAC_DPIPx register for channel x. 10. Clear any pending interrupts on the channel from the previous DMAC transfer by read- ing the status register: DMAC_EBCISR.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 493 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 11. Program the DMAC_CTRLBx, DMAC_CFGx registers according to Row 4 as shown in Table 32-2 on page 489. 12. Program the DMAC_DSCRx register with DMAC_DSCRx(0), the pointer to the first Linked List item. 13. Finally, enable the channel by writing a ‘1’ to the DMAC_CHER.ENAx bit, where x is the channel number. The transfer is performed. 14. The DMAC fetches the first LLI from the location pointed to by DMAC_DSCRx(0). Note: The LLI.DMAC_SADDRx, LLI. DMAC_DADDRx, LLI.DMAC_DSCRx, LLI.DMAC_CTRLAx and LLI.DMAC_CTRLBx registers are fetched. The DMAC automatically reprograms the DMAC_SADDRx, DMAC_DADDRx, DMAC_DSCRx, DMAC_CTRLBx and DMAC_CTRLAx chan- nel registers from the DMAC_DSCRx(0). 15. Source and destination request single and chunk DMAC transactions to transfer the buffer of data (assuming non-memory peripheral). The DMAC acknowledges at the completion of every transaction (chunk and single) in the buffer and carries out the buf- fer transfer. 16. Once the buffer of data is transferred, the DMAC_CTRLAx register is written out to sys- tem memory at the same location and on the same layer (DMAC_DSCRx.DSCR_IF) where it was originally fetched, that is, the location of the DMAC_CTRLAx register of the linked list item fetched prior to the start of the buffer transfer. Only DMAC_CTRLAx register is written out because only the DMAC_CTRLAx.BTSIZE and DMAC_CTRLAX.DONE bits have been updated by DMAC hardware. Additionally, the DMAC_CTRLAx.DONE bit is asserted when the buffer transfer has completed. Note: Do not poll the DMAC_CTRLAx.DONE bit in the DMAC memory map. Instead, poll the asserted, then this buffer transfer has completed. This LLI.DMAC_CTRLAx.DONE bit was cleared at the start of the transfer. 17. The DMAC does not wait for the buffer interrupt to be cleared, but continues fetching the next LLI from the memory location pointed to by current DMAC_DSCRx register and automatically reprograms the DMAC_SADDRx, DMAC_DADDRx, DMAC_DSCRx, DMAC_CTRLAx and DMAC_CTRLBx channel registers. The DMAC transfer continues until the DMAC determines that the DMAC_CTRLBx and DMAC_DSCRx registers at the end of a buffer transfer match described in Row 1 of Table 32-2 on page 489. The DMAC then knows that the previous buffer transferred was the last buffer in the DMAC transfer. The DMAC transfer might look like that shown in Figure 32-7 on page 494.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 494 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Figure 32-7. Multi-buffer with Linked List Address for Source and Destination If the user needs to execute a DMAC transfer where the source and destination address are contiguous but the amount of data to be transferred is greater than the maximum buffer size DMAC_CTRLAx.BTSIZE, then this can be achieved using the type of multi-buffer transfer as shown in Figure 32-8 on page 495. SADDR(2) SADDR(1) SADDR(0) DADDR(2) DADDR(1) DADDR(0) Buffer 2 Buffer 1 Buffer 0 Buffer 0 Buffer 1 Buffer 2 Address of Source Layer Address of Destination Layer Source Buffers Destination Buffers

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 495 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Figure 32-8. Multi-buffer with Linked Address for Source and Destination Buffers are Contiguous The DMAC transfer flow is shown in Figure 32-9 on page 496. SADDR(2) SADDR(1) SADDR(0) DADDR(2) DADDR(1) DADDR(0) Buffer 2 Buffer 1 Buffer 0 Buffer 0 Buffer 1 Buffer 2 Address of Source Layer Address of Destination Layer Source Buffers Destination Buffers SADDR(3) Buffer 2 DADDR(3) Buffer 2

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 496 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Figure 32-9. DMAC Transfer Flow for Source and Destination Linked List Address Multi-buffer Transfer with Source Address Auto-reloaded and Destination Address Auto-reloaded (Row 10) 1. Read the Channel Handler Status register to choose an available (disabled) channel. 2. Clear any pending interrupts on the channel from the previous DMAC transfer by read- ing the interrupt status register. Program the following channel registers: Channel enabled by software LLI Fetch Hardware reprograms SADDRx, DADDRx, CTRLA/Bx, DSCRx DMAC buffer transfer Writeback of DMAC_CTRLAx register in system memory Is DMAC in Row 1 of DMAC State Machine Table? Channel disabled by hardware Chained Buffer Transfer Completed Interrupt generated here DMAC Chained Buffer Transfer Completed Interrupt generated here yes no

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 497 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 a. Write the starting source address in the DMAC_SADDRx register for channel x. b. Write the starting destination address in the DMAC_DADDRx register for channel x. c. Program DMAC_CTRLAx, DMAC_CTRLBx and DMAC_CFGx according to Row 10 as shown in Table 32-2 on page 489. Program the DMAC_DSCRx register with ‘0’. d. Write the control information for the DMAC transfer in the DMAC_CTRLAx and DMAC_CTRLBx register for channel x. For example, in the register, you can pro- gram the following: – i. Set up the transfer type (memory or non-memory peripheral for source and destination) and flow control device by programming the FC of the DMAC_CTRLBx register. – ii. Set up the transfer characteristics, such as: – Transfer width for the source in the SRC_WIDTH field. – Transfer width for the destination in the DST_WIDTH field. – Source AHB master interface layer in the SIF field where source resides. – Destination AHB master interface layer in the DIF field where destination resides. – Incrementing/decrementing or fixed address for source in SRC_INCR field. – Incrementing/decrementing or fixed address for destination in DST_INCR field. e. If source Picture-in-Pic ture mode is enabled (DMAC_CTRLBx.SPIP is enabled), program the DMAC_SPIPx register for channel x. f. If destination Picture-in-Picture is enabled (DMAC_CTRLBx.DPIP), program the DMAC_DPIPx register for channel x. g. Write the channel configuration information into the DMAC_CFGx register for chan- nel x. Ensure that the reload bits, DMAC_CFGx.SRC_REP , DMAC_CFGx.DST_REP and DMAC_CTRLBx.AUTO are enabled. – i. Designate the handshaking interface type (hardware or software) for the source and destination peripherals. This is not required for memory. This step requires programming the SRC_H2SEL/DST_h2SEL bits, respectively. Writing a ‘1’ activates the hardware handshaking interface to handle source/destination requests for the specific channel. Writing a ‘0’ activates the software handshaking interface to handle source/destination requests. – ii. If the hardware handshaking interface is activated for the source or destination peripheral, assign handshaking interface to the source and destination peripheral. This requires programming the SRC_PER and DST_PER bits, respectively. 3. After the DMAC selected channel has been programmed, enable the channel by writing a ‘1’ to the DMAC_CHER.ENAx bit where the channel number is. Make sure that bit 0 of the DMAC_EN register is enabled. 4. Source and destination request single and chunk DMAC transactions to transfer the buffer of data (assuming non-memory peripherals). The DMAC acknowledges on com- pletion of each chunk/single transaction and carries out the buffer transfer. 5. When the buffer transfer has completed, the DMAC reloads the DMAC_SADDRx, DMAC_DADDRx and DMAC_CTRLAx registers. The hardware sets the Buffer Transfer Completed Interrupt. The DMAC then samples the row number as shown in Table 32-2 on page 489. If the DMAC is in Row 1, then the DMAC transfer has completed. The hardware sets the Chained Buffer Transfer Completed Interrupt and disables the chan- nel. So you can either respond to the Buffer Transfer Completed Interrupt or Chained

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 498 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Buffer Transfer Completed Interrupt, or poll for the Channel Enable in the Channel Sta- tus Register (DMAC_CHSR.ENAx) until it is disabled, to detect when the transfer is complete. If the DMAC is not in Row 1, the next step is performed. 6. The DMAC transfer proceeds as follows: a. If the Buffer Transfer Completed Interrupt is unmasked (DMAC_EBCIMR.BTCx = ‘1’, where x is the channel number), the hardware sets the Buffer Transfer Com- pleted Interrupt when the buffer transfer has completed. It then stalls until the STALx bit of DMAC_CHSR register is cleared by software, writing ‘1’ to DMAC_CHER.KEEPx bit, where x is the channel number. If the next buffer is to be the last buffer in the DMAC transfer, then the buffer complete ISR (interrupt service routine) should clear the automatic mode bit in the DMAC_CTRLBx.AUTO bit. This puts the DMAC into Row 1 as shown in Table 32-2 on page 489. If the next buffer is not the last buffer in the DMAC transfer, then the reload bits should remain enabled to keep the DMAC in Row 4. b. If the Buffer Transfer Completed Interrupt is masked (DMAC_EBCIMR.BTCx = ‘0’, where x is the channel number), the hardware does not stall until it detects a write to the Buffer Transfer Completed Interrupt Enable register DMAC_EBCIER register, but starts the next buffer transfer immediately. In this case, the software must clear the automatic mode bit in the DMAC_CTRLB to put the DMAC into ROW 1 of Table 32-2 on page 489 before the last buffer of the DMAC transfer has completed. The transfer is similar to that shown in Figure 32-10 on page 498. The DMAC transfer flow is shown in Figure 32-11 on page 499. Figure 32-10. Multi-buffer DMAC Transfer with Source and Destination Address Auto-reloaded Address of Source Layer Address of Destination Layer Source Buffers Destination Buffers BlockN Block2 Block1 Block0 SADDR DADDR

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 499 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Figure 32-11. DMAC Transfer Flow for Source and Destination Address Auto-reloaded Multi-buffer Transfer with Source Address Auto-reloaded and Linked List Destination Address (Row 6) 1. Read the Channel Handler Status register to choose a free (disabled) channel. 2. Set up the chain of linked list items (otherwise known as buffer descriptors) in memory. Write the control information in the LLI.DMAC_CTRLAx and DMAC_CTRLBx registers location of the buffer descriptor for each LLI in memory for channel x. For example, in the register, you can program the following: a. Set up the transfer type (memory or non-memory peripheral for source and desti- nation) and flow control peripheral by programming the FC of the DMAC_CTRLBx register. b. Set up the transfer characteristics, such as: – i. Transfer width for the source in the SRC_WIDTH field. – ii. Transfer width for the destination in the DST_WIDTH field. – iii. Source AHB master interface layer in the SIF field where source resides. – iv. Destination AHB master interface layer in the DIF field where destination resides. – v. Incrementing/decrementing or fixed address for source in SRC_INCR field. – vi. Incrementing/decrementing or fixed address for destination DST_INCR field. Channel enabled by software Buffer Transfer Replay mode for SADDRx, DADDRx, CTRLAx, CTRLBx Channel disabled by hardware Buffer Transfer Completed Interrupt generated here DMAC Chained Buffer Transfer Completed Interrupt generated here yes no yes Stall until STALLx is cleared by writing to KEEPx field EBCIMR[x]=1? no Is DMAC in Row 1 of DMAC State Machine table?

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 500 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 3. Write the starting source address in the DMAC_SADDRx register for channel x. Note: The values in the LLI.DMAC_SADDRx register loca tions of each of the Linked List Items (LLIs) set up in memory, although fetched during an LLI fetch, are not used. 4. Write the channel configuration information into the DMAC_CFGx register for channel x. a. Designate the handshaking interface type (hardware or software) for the source and destination peripherals. This is not required for memory. This step requires pro- gramming the SRC_H2SEL/DST_H2SEL bits, respectively. Writing a ‘1’ activates the hardware handshaking interface to handle source/destination requests for the specific channel. Writing a ‘0’ activates the software handshaking interface source/destination requests. b. If the hardware handshaking interface is activated for the source or destination peripheral, assign handshaking interface to the source and destination peripheral. This requires programming the SRC_PER and DST_PER bits, respectively. 5. Make sure that the LLI.DMAC_CTRLBx register locations of all LLIs in memory (except the last one) are set as shown in Row 6 of Table 32-2 on page 489 while the LLI.DMAC_CTRLBx register of the last Linked List item must be set as described in Row 1 of Table 32-2. Figure 32-5 on page 487 shows a Linked List example with two list items. 6. Make sure that the LLI.DMAC_DSCRx register locations of all LLIs in memory (except the last one) are non-zero and point to the next Linked List Item. 7. Make sure that the LLI.DMAC_DADDRx register locations of all LLIs in memory point to the start destination buffer address proceeding that LLI fetch. 8. Make sure that the LLI.DMAC_CTLx.DONE field of the LLI.DMAC_CTRLA register locations of all LLIs in memory is cleared. 9. If source Picture-in-Picture is enabled (DMAC_CTRLBx.SPIP is enabled), program the DMAC_SPIPx register for channel x. 10. If destination Picture-in-Picture is enabled (DMAC_CTRLBx.DPIP is enabled), program the DMAC_DPIPx register for channel x. 11. Clear any pending interrupts on the channel from the previous DMAC transfer by read- ing to the DMAC_EBCISR register. 12. Program the DMAC_CTLx and DMAC_CFGx registers according to Row 6 as shown in Table 32-2 on page 489. 13. Program the DMAC_DSCRx register with DMAC_DSCRx(0), the pointer to the first Linked List item. 14. Finally, enable the channel by writing a ‘1’ to the DMAC_CHER.ENAx bit, where x is the channel number. The transfer is performed. Make sure that bit 0 of the DMAC_EN reg- ister is enabled. 15. The DMAC fetches the first LLI from the location pointed to by DMAC_DSCRx(0). Note: The LLI.DMAC_SADDRx, LLI.DMAC_DADDRx , LLI. DMAC_LLPx LLI.DMAC_CTRLAx and LLI.DMAC_CTRLBx registers are fetched. The LLI.DMAC_SADDRx register, although fetched, is not used. 16. Source and destination request single and chunk DMAC transactions to transfer the buffer of data (assuming non-memory peripherals). DMAC acknowledges at the com- pletion of every transaction (chunk and single) in the buffer and carries out the buffer transfer. 17. The DMAC_CTRLAx register is written out to the system memory. The DMAC_CTRLAx register is written out to the same location on the same layer (DMAC_DSCRx.DSCR_IF) where it was originally fetched, that is the location of the DMAC_CTRLAx register of the linked list item fetched prior to the start of the buffer

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 501 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 transfer. Only DMAC_CTRLAx register is written out, because only the DMAC_CTRLAx.BTSIZE and DMAC_CTRLAx.DONE fields have been updated by hardware within the DMAC. The LLI.DMAC_CTRLAx.DONE bit is asserted to indicate buffer completion. Therefore, the software can poll the LLI.DMAC_CTRLAx.DONE field of the DMAC_CTRLAx register in the LLi to ascertain when a buffer transfer has completed. Note: Do not poll the DMAC_CTRLAx.DONE bit in the DMAC memory map. Instead, poll the is asserted, then this buffer transfer has completed. This LLI.DMAC_CTRLA.DONE bit was cleared at the start of the transfer. 18. The DMAC reloads the DMAC_SADDRx register from the initial value. The hardware sets the Buffer Transfer Completed Interrupt. The DMAC samples the row number as shown in Table 32-2 on page 489. If the DMAC is in Row 1, then the DMAC transfer has completed. The hardware sets the Chained Buffer Transfer Completed Interrupt and disables the channel. Y ou can either respond to the Buffer Transfer Completed Interrupt or Chained Buffer Transfer Completed Interrupt, or poll for the Channel Enable. (DMAC_CHSR.ENAx) bit until it is cleared by hardware, to detect when the transfer is complete. If the DMAC is not in Row 1 as shown in Table 32-2 on page 489, the follow- ing step is performed. 19. The DMAC fetches the next LLI from the memory location pointed to by the current DMAC_DSCRx register, and automatically reprograms the DMAC_DADDRx, DMAC_CTRLAx, DMAC_CTRLBx and DMAC_DSCRx channel registers. Note that the DMAC_SADDRx is not re-programmed as the reloaded value is used for the next DMAC buffer transfer. If the next buffer is the last buffer of the DMAC transfer, then the DMAC_CTRLBx and DMAC_DSCRx registers just fetched from the LLI should match Row 1 of Table 32-2 on page 489. The DMAC transfer might look like that shown in Fig- ure 32-12 on page 501. Figure 32-12. Multi-buffer DMAC Transfer with Source Address Auto-reloaded and Linked List Destination Address The DMAC Transfer flow is shown in Figure 32-13 on page 502. Address of Source Layer Address of Destination Layer Source Buffers Destination Buffers SADDR Buffer0 Buffer1 Buffer2 BufferN DADDR(N) DADDR(1) DADDR(0) DADDR(2)

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 502 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Figure 32-13. DMAC Transfer Flow for Replay Mode at Source and Linked List Destination Address Multi-buffer Transfer with Source Address Auto-reloaded and Contiguous Destination Address (Row 11) 1. Read the Channel Handler Status register to choose a free (disabled) channel. 2. Clear any pending interrupts on the channel from the previous DMAC transfer by read- ing to the Interrupt Status Register. 3. Program the following channel registers: a. Write the starting source address in the DMAC_SADDRx register for channel x. b. Write the starting destination address in the DMAC_DADDRx register for channel x. c. Program DMAC_CTRLAx, DMAC_CTRLBx and DMAC_CFGx according to Row 11 as shown in Table 32-2 on page 489. Program the DMAC_DSCRx register with ‘0’. DMAC_CTRLBx.AUTO field is set to ‘1’ to enable automatic mode support. d. Write the control information for the DMAC transfer in the DMAC_CTRLBx and DMAC_CTRLAx register for channel x. For example, in this register, you can pro- gram the following: – i. Set up the transfer type (memory or non-memory peripheral for source and destination) and flow control device by programming the FC of the DMAC_CTRLBx register. – ii. Set up the transfer characteristics, such as: Channel enabled by software LLI Fetch yes no Hardware reprograms DADDRx, CTRLAx, CTRLBx, DSCRx DMAC buffer transfer Writeback of control status information in LLI Reload SADDRx Buffer Transfer Completed Interrupt generated here DMAC Chained Buffer Transfer Completed Interrupt generated here Channel disabled by hardware Is DMAC in Row 1 of DMAC State Machine Table?

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 503 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 – Transfer width for the source in the SRC_WIDTH field. – Transfer width for the destination in the DST_WIDTH field. – Source AHB master interface layer in the SIF field where source resides. – Destination AHB master interface master layer in the DIF field where destination resides. – Incrementing/decrementing or fixed address for source in SRC_INCR field. – Incrementing/decrementing or fixed address for destination in DST_INCR field. e. If source Picture-in-Picture is enabled (DMAC_CTRLBx.SPIP is enabled), program the DMAC_SPIPx register for channel x. f. If destination Picture-in-Picture is enabled (DMAC_CTRLBx.DPIP), program the DMAC_DPIPx register for channel x. g. Write the channel configuration information into the DMAC_CFGx register for chan- nel x. – i. Designate the handshaking interface type (hardware or software) for the source and destination peripherals. This is not required for memory. This step requires programming the SRC_H2SEL/DST_H2SEL bits, respectively. Writing a ‘1’ activates the hardware handshaking interface to handle source/destination requests for the specific channel. Writing a ‘0’ activates the software handshaking interface to handle source/destination requests. – ii. If the hardware handshaking interface is activated for the source or destination peripheral, assign the handshaking interface to the source and destination peripheral. This requires programming the SRC_PER and DST_PER bits, respectively. 4. After the DMAC channel has been programmed, enable the channel by writing a ‘1’ to the DMAC_CHER.ENAx bit, where x is the channel number. Make sure that bit 0 of the DMAC_EN.ENABLE register is enabled. 5. Source and destination request single and chunk DMAC transactions to transfer the buffer of data (assuming non-memory peripherals). The DMAC acknowledges at the completion of every transaction (chunk and single) in the buffer and carries out the buf- fer transfer. 6. When the buffer transfer has completed, the DMAC reloads the DMAC_SADDRx regis- ter. The DMAC_DADDRx register remains unchanged. The hardware sets the Buffer Transfer Completed Interrupt. The DMAC then samples the row number as shown in Table 32-2 on page 489. If the DMAC is in Row 1, then the DMAC transfer has com- pleted. The hardware sets the Chained Buffer Transfer Completed Interrupt and disables the channel. So you can either respond to the Buffer Transfer Completed Inter- rupt or Chained Buffer Transfer Completed Interrupt, or poll for the enable (ENAx) field in the Channel Status Register (DMAC_CHSR.ENAx bit) until it is cleared by hardware, to detect when the transfer is complete. If the DMAC is not in Row 1, the next step is performed. 7. The DMAC transfer proceeds as follows: a. If the Buffer Transfer Completed Interrupt is unmasked (DMAC_EBCIMR.BTCx = ‘1’, where x is the channel number), the hardware sets the Buffer Transfer Com- pleted Interrupt when the buffer transfer has completed. It then stalls until STALx bit of DMAC_CHSR is cleared by writing in the KEEPx field of DMAC_CHER register, where x is the channel number. If the next buffer is to be the last buffer in the DMAC transfer, then the buffer complete ISR (interrupt service routine) should clear the automatic mode bit, DMAC_CTRLBx.AUTO. This puts the DMAC into Row 1 as shown in Table 32-2 on page 489. If the next buffer is not the last buffer in the

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 504 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 DMAC transfer, then the automatic transfer mode bit should remain enabled to keep the DMAC in Row 11 as shown in Table 32-2 on page 489. b. If the Buffer Transfer Completed Interrupt is masked (DMAC_EBCIMR.BTCx = ‘0’, where x is the channel number), the hardware does not stall until it detects a write to the Buffer Transfer Completed Interrupt Enable register, but starts the next buffer transfer immediately. In this case, the software must clear the automatic mode bit, DMAC_CTRLBx.AUTO, to put the device into ROW 1 of Table 32-2 on page 489 before the last buffer of the DMAC transfer has completed. The transfer is similar to that shown in Figure 32-14 on page 504. The DMAC Transfer flow is shown in Figure 32-15 on page 505. Figure 32-14. Multi-buffer Transfer with Source Address Auto-reloaded and Contiguous Destination Address Address of Source Layer Address of Destination Layer Source Buffers Destination Buffers SADDR Buffer0 Buffer1 Buffer2 DADDR(1) DADDR(0) DADDR(2)

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 505 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Figure 32-15. DMAC Transfer Replay Mode is Enabled for the Source and Contiguous Destination Address Multi-buffer DMAC Transfer with Linked List for Source and Contiguous Destination Address (Row 2) 1. Read the Channel Handler Status register to choose a free (disabled) channel. 2. Set up the linked list in memory. Wr ite the control information in the LLI.DMAC_CTRLAx and LLI.DMAC_CTRLBx register location of the buffer descriptor for each LLI in memory for channel x. For example, in the register, you can program the following: a. Set up the transfer type (memory or non-memory peripheral for source and desti- nation) and flow control device by programming the FC of the DMAC_CTRLBx register. b. Set up the transfer characteristics, such as: – i. Transfer width for the source in the SRC_WIDTH field. – ii. Transfer width for the destination in the DST_WIDTH field. – iii. Source AHB master interface layer in the SIF field where source resides. – iv. Destination AHB master interface layer in the DIF field where destination resides. Channel enabled by software Buffer Transfer Replay mode for SADDRx, Contiguous mode for DADDRx CTRLAx, CTRLBx Channel disabled by hardware Buffer Transfer Completed Interrupt generated here Buffer Transfer Completed Interrupt generated here yes no no yes Stall until STALLx field is cleared by software writing KEEPx field DMA_EBCIMR[x]=1? Is DMAC in Row 1 of DMAC State Machine Table?

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 506 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 – v. Incrementing/decrementing or fixed address for source in SRC_INCR field. – vi. Incrementing/decrementing or fixed address for destination DST_INCR field. 3. Write the starting destination address in the DMAC_DADDRx register for channel x. Note: The values in the LLI.DMAC_DADDRx register location of each Linked List Item (LLI) in memory, although fetched during an LLI fetch, are not used. 4. Write the channel configuration information into the DMAC_CFGx register for channel x. a. Designate the handshaking interface type (hardware or software) for the source and destination peripherals. This is not required for memory. This step requires pro- gramming the SRC_H2SEL/DST_H2SEL bits, respectively. Writing a ‘1’ activates the hardware handshaking interface to handle source/destination requests for the specific channel. Writing a ‘0’ activates the software handshaking interface to han- dle source/destination requests. b. If the hardware handshaking interface is activated for the source or destination peripheral, assign the handshaking interface to the source and destination periph- erals. This requires programming the SRC_PER and DST_PER bits, respectively. 5. Make sure that all LLI.DMAC_CTRLBx register locations of the LLI (except the last) are set as shown in Row 2 of Table 32-2 on page 489, while the LLI.DMAC_CTRLBx regis- ter of the last Linked List item must be set as described in Row 1 of Table 32-2. Figure 32-5 on page 487 shows a Linked List example with two list items. 6. Make sure that the LLI.DMAC_DSCRx register locations of all LLIs in memory (except the last) are non-zero and point to the next Linked List Item. 7. Make sure that the LLI.DMAC_SADDRx register locations of all LLIs in memory point to the start source buffer address proceeding that LLI fetch. 8. Make sure that the LLI.DMAC_CTRLAx.DONE field of the LLI.DMAC_CTRLAx register locations of all LLIs in memory is cleared. 9. If source Picture-in-Picture is enabled (DMAC_CTRLBx.SPIP is enabled), program the DMAC_SPIPx register for channel x. 10. If destination Picture-in-Picture is enabled (DMAC_CTRLBx.DPIP is enabled), program the DMAC_DPIPx register for channel x. 11. Clear any pending interrupts on the channel from the previous DMAC transfer by read- ing the interrupt status register. 12. Program the DMAC_CTRLAx, DMAC_CTRLBx and DMAC_CFGx registers according to Row 2 as shown in Table 32-2 on page 489 13. Program the DMAC_DSCRx register with DMAC_DSCRx(0), the pointer to the first Linked List item. 14. Finally, enable the channel by writing a ‘1’ to the DMAC_CHER.ENAx bit. The transfer is performed. Make sure that bit 0 of the DMAC_EN register is enabled. 15. The DMAC fetches the first LLI from the location pointed to by DMAC_DSCRx(0). Note: The LLI.DMAC_SADDRx, LLI.DMAC_DADDRx, LLI.DMAC_DSCRx and LLI.DMAC_CTRLA/Bx registers are fetched. The LLI.DMAC_DADDRx register location of the LLI, although fetched, is not used. The DMAC_DADDRx register in the DMAC remains unchanged. 16. Source and destination requests single and chunk DMAC transactions to transfer the buffer of data (assuming non-memory peripherals). The DMAC acknowledges at the completion of every transaction (chunk and single) in the buffer and carries out the buf- fer transfer. 17. Once the buffer of data is transferred, the DMAC_CTRLAx register is written out to the system memory at the same location and on the same layer (DMAC_DSCRx.DSCR_IF) where it was originally fetched, that is, the location of the

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 507 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 DMAC_CTRLAx register of the linked list item fetched prior to the start of the buffer transfer. Only DMAC_CTRLAx register is written out because only the DMAC_CTRLAx.BTSIZE and DMAC_CTRLAX.DONE fields have been updated by DMAC hardware. Additionally, the DMAC_CTRLAx.DONE bit is asserted when the buf- fer transfer has completed. Note: Do not poll the DMAC_CTRLAx.DONE bit in the DMAC memory map. Instead, poll the asserted, then this buffer transfer has completed. This LLI.DMAC_CTRLAx.DONE bit was cleared at the start of the transfer. 18. The DMAC does not wait for the buffer interrupt to be cleared, but continues and fetches the next LLI from the memory location pointed to by the current DMAC_DSCRx register, then automatically reprograms the DMAC_SADDRx, DMAC_CTRLAx, DMAC_CTRLBx and DMAC_DSCRx channel registers. The DMAC_DADDRx register is left unchanged. The DMAC transfer continues until the DMAC samples the DMAC_CTRLAx, DMAC_CTRLBx and DMAC_DSCRx registers at the end of a buffer transfer match that described in Row 1 of Table 32-2 on page 489. The DMAC then knows that the previous buffer transferred was the last buffer in the DMAC transfer. The DMAC transfer might look like that shown in Figure 32-16 on page 507. Note that the desti- nation address is decrementing. Figure 32-16. DMAC Transfer with Linked List Source Address and Contiguous Destination Address The DMAC transfer flow is shown in Figure 32-17 on page 508. SADDR(2) SADDR(1) SADDR(0) DADDR(2) DADDR(1) DADDR(0) Buffer 2 Buffer 1 Buffer 0 Buffer 0 Buffer 1 Buffer 2 Address of Source Layer Address of Destination Layer Source Buffers Destination Buffers

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 508 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Figure 32-17. DMAC Transfer Flow for Linked List Source Address and Contiguous Destination Address

32.4.6 Disabling a Channel Prior to Transfer Completion

Under normal operation, the software enables a channel by writing a ‘1’ to the Channel Handler Enable Register, DMAC_CHER.ENAx, and the hardware disables a channel on transfer comple- tion by clearing the DMAC_CHSR.ENAx register bit. The recommended way for software to disable a channel without losing data is to use the SUSPx bit in conjunction with the EMPTx bit in the Channel Handler Status Register. Channel enabled by software LLI Fetch Hardware reprograms SADDRx, CTRLAx,CTRLBx, DSCRx DMAC buffer transfer Writeback of control information of LLI Is DMAC in Row 1 ? Channel disabled by hardware Buffer Transfer Completed Interrupt generated here DMAC Chained Buffer Transfer Completed Interrupt generated here yes no

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 509 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 1. If the software wishes to disable a channel n prior to the DMAC transfer completion, then it can set the DMAC_CHER.SUSPx bit to tell the DMAC to halt all transfers from the source peripheral. Therefore, the channel FIFO receives no new data. 2. The software can now poll the DMAC_CHSR.EMPTx bit until it indicates that the channel n FIFO is empty, where n is the channel number. 3. The DMAC_CHER.ENAx bit can then be cleared by software once the channel n FIFO is empty, where n is the channel number. When DMAC_CTRLAx.SRC_WIDTH is less than DMAC_CTRLAx.DST_WIDTH and the DMAC_CHSRx.SUSPx bit is high, the DMAC_CHS Rx.EMPTx is asserted once the contents of the FIFO does not permit a single word of DMAC_CTRLAx.DST_WIDTH to be formed. How- ever, there may still be data in the channel FIFO but not enough to form a single transfer of DMAC_CTLx.DST_WIDTH width. In this configuration, once the channel is disabled, the remain- ing data in the channel FIFO are not transferred to the destination peripheral. It is permitted to remove the channel from the suspension state by writing a ‘1’ to the DMAC_CHER.RESx field register. The DMAC transfer completes in the normal manner. n defines the channel number. Note: If a channel is disabled by software, an active single or chunk transaction is not guaranteed to receive an acknowledgement.

32.4.6.1 Abnormal Transfer Termination

A DMAC transfer may be terminated abruptly by so ftware by clearing the channel enable bit, DMAC_CHDR.ENAx, where x is the channel number. This does not mean that the channel is disabled immediately after the DMAC_CHSR.ENAx bit is cleared over the APB interface. Con- sider this as a request to disable the channel. The DMAC_CHSR.ENAx must be polled and then it must be confirmed that the channel is disabled by reading back 0. The software may terminate all channels abruptly by clearing the global enable bit in the DMAC Configuration Register (DMAC_EN.ENABLE bit). Again, this does not mean that all channels are disabled immediately after the DMAC_EN.ENABLE is cleared over the APB slave interface. Consider this as a request to disable all c hannels. The DMAC_CHSR.ENABLE must be polled and then it must be confirmed that all channels are disabled by reading back ‘0’. Note: If the channel enable bit is cleared while there is data in the channel FIFO, this data is not sent to the destination peripheral and is not present when the channel is re-enabled. For read sensitive source peripherals, such as a source FIFO, this data is therefore lost. When the source is not a read sensitive device (i.e., memory), disabling a channel without waiting for the channel FIFO to empty may be acceptable as the data is available from the source peripheral upon request and is not lost. Note: If a channel is disabled by software, an active single or chunk transaction is not guaranteed to receive an acknowledgement.

32.5 DMAC Software Requirements

  • There must not be any write operation to Channel registers in an active channel after the channel enable is made HIGH. If any channel parameters must be reprogrammed, this can only be done after disabling the DMAC channel.
  • When the destination peripheral has been defined as the flow controller, source single transfer requests are not serviced until the destination peripheral has asserted its Last Transfer Flag.
  • When the source peripheral has been defined as the flow controller, destination single transfer requests are not serviced until the source peripheral has asserted its Last Transfer Flag.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 510 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

  • When the destination peripheral has been defined as the flow controller, if the destination width is smaller than the source width, then a data loss may occur, and the loss is equal to the Source Single Transfer size in bytes- destination Single Transfer size in bytes.
  • When a Memory to Peripheral transfer occurs, if the destination peripheral has been defined as the flow controller, then a prefetch operation is performed. It means that data is extracted from the memory before any request from the peripheral is generated.
  • Y ou must program the DMAC_SADDRx and DMAC_DADDRx channel registers with a byte, half-word and word aligned address depending on the source width and destination width.
  • After the software disables a channel by writing into the channel disable register, it must re- enable the channel only after it has polled a 0 in the corresponding channel enable status register. This is because the current AHB Burst must terminate properly.
  • If you program the BTSIZE field in the DMAC_CTRLA as zero, and the DMAC has been defined as the flow controller, then the channel is automatically disabled.
  • When hardware handshaking interface protocol is fully implemented, a peripheral is expected to deassert any sreq or breq signals on receiving the ack signal irrespective of the request the ack was asserted in response to.
  • Multiple Transfers involving the same peripheral must not be programmed and enabled on different channels, unless this peripheral integrates several hardware handshaking interfaces.
  • When a Peripheral has been defined as the flow controller, the targeted DMAC Channel must be enabled before the Peripheral. If you do not ensure this and the First DMAC request is also the last transfer, the DMAC Channel might miss a Last Transfer Flag.
  • When the AUTO Field is set to TRUE, then the BTSIZE Field is automatically reloaded from its previous value. BTSIZE must be initialized to a non zero value if the first transfer is initiated with the AUTO field set to TRUE, even if LLI mode is enabled, because the LLI fetch operation will not update this field.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 511 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

32.6 Write Protection Registers

To prevent any single software error that may corrupt the DMAC behavior, the DMAC address space can be write-protected by setting the WPEN bit in the “DMAC Write Protect Mode Regis- ter” (DMAC_WPMR). If a write access to anywhere in the DMAC address space is detected, then the WPVS flag in the DMAC Write Protect Status Register (MCI_W PSR) is set, and the WPVSRC field indicates in which register the write access has been attempted. The WPVS flag is reset by writing the DMAC Write Protect Mode Register (DMAC_WPMR) with the appropriate access key, WPKEY. The protected registers are:

  • “DMAC Global Configuration Register” on page 513
  • “DMAC Enable Register” on page 514
  • “DMAC Channel x [x = 0..7] Source Address Register” on page 525
  • “DMAC Channel x [x = 0..7] Destination Address Register” on page 526
  • “DMAC Channel x [x = 0..7] Descriptor Address Register” on page 527
  • “DMAC Channel x [x = 0..7] Control A Register” on page 528
  • “DMAC Channel x [x = 0..7] Control B Register” on page 530
  • “DMAC Channel x [x = 0..7] Configuration Register” on page 532
  • “DMAC Channel x [x = 0..7] Source Picture-in-Picture Configuration Register” on page 534
  • “DMAC Channel x [x = 0..7] Destination Picture-in-Picture Configuration Register” on page 535

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 512 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

32.7 DMA Controller (DMAC) User Interface

Table 32-4. Register Mapping Offset Register Name Access Reset 0x000 DMAC Global Configuration Register DMAC_GCFG Read-write 0x10 0x004 DMAC Enable Register DMAC_EN Read-write 0x0 0x008 DMAC Software Single Request Register DMAC_SREQ Read-write 0x0 0x00C DMAC Software Chunk Transfer Request Register DMAC_CREQ Read-write 0x0 0x010 DMAC Software Last Transfer Flag Register DMAC_LAST Read-write 0x0 0x014 Reserved 0x018 DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Enable register. DMAC_EBCIER Write-only – 0x01C DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Disable register. DMAC_EBCIDR Write-only – 0x020 DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Mask Register. DMAC_EBCIMR Read-only 0x0 0x024 DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Status Register. DMAC_EBCISR Read-only 0x0 0x028 DMAC Channel Handler Enable Register DMAC_CHER Write-only – 0x02C DMAC Channel Handler Disable Register DMAC_CHDR Write-only – 0x030 DMAC Channel Handler Status Register DMAC_CHSR Read-only 0x00FF0000 0x034 Reserved – – – 0x038 Reserved – – – 0x03C+ch_num*(0x28)+(0x0) DMAC Channel Source Address Register DMAC_SADDR Read-write 0x0 0x03C+ch_num*(0x28)+(0x4) DMAC Channel Destinat ion Address Register DMAC_DADDR Read-write 0x0 0x03C+ch_num*(0x28)+(0x8) DMAC Channel Descriptor Address Register DMAC_DSCR Read-write 0x0 0x03C+ch_num*(0x28)+(0xC) DMAC Channel Control A Register DMAC_CTRLA Read-write 0x0 0x03C+ch_num*(0x28)+(0x10) DMAC Channel Control B Register DMAC_CTRLB Read-write 0x0 0x03C+ch_num*(0x28)+(0x14) DMAC Channel Confi guration Register DMAC_CFG Read-write 0x01000000 0x03C+ch_num*(0x28)+(0x18) DMAC Channel Source Picture-in-Picture Configuration Register DMAC_SPIP Read-write 0x0 0x03C+ch_num*(0x28)+(0x1C) DMAC Channel Destination Picture-in-Picture Configuration Register DMAC_DPIP Read-write 0x0 0x03C+ch_num*(0x28)+(0x20) Reserved – – – 0x03C+ch_num*(0x28)+(0x24) Reserved – – – 0x1E4 DMAC Write Protect Mode Register DMAC_WPMR Read-write 0x0 0x1E8 DMAC Write Protect Status Register DMAC_WPSR Read-only 0x0 0x01EC- 0x1FC Reserved – – –

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 513 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

32.7.1 DMAC Global Configuration Register

Name: DMAC_GCFG Address: 0xFFFFEC00 Access: Read-write Reset: 0x00000010 Note: Bit fields 0, 1, 2, 3, have a default value of 0. This should not be changed. This register can only be written if the WPEN bit is cleared in “DMAC Write Protect Mode Register” .  ARB_CFG: Arbiter Configuration 0 (FIXED): Fixed priority arbiter. 1 (ROUND_ROBIN): Modified round robin arbiter.  DICEN: Descriptor Integrity Check 0: Descriptor Integrity Check Interface is Disabled. 1: Descriptor Integrity Check Interface is Enabled. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 514 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

32.7.2 DMAC Enable Register

Name: DMAC_EN Address: 0xFFFFEC04 Access: Read-write Reset: 0x00000000 This register can only be written if the WPEN bit is cleared in “DMAC Write Protect Mode Register” .  ENABLE 0: DMA Controller is disabled. 1: DMA Controller is enabled. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 515 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

32.7.3 DMAC Software Single Request Register

Name: DMAC_SREQ Address: 0xFFFFEC08 Access: Read-write Reset: 0x00000000  DSREQx: Destination Request Request a destination single transfer on channel i.  SSREQx: Source Request Request a source single transfer on channel i. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 DSREQ7 SSREQ7 DSREQ6 SSREQ6 DSREQ5 SSREQ5 DSREQ4 SSREQ4 76543210 DSREQ3 SSREQ3 DSREQ2 SSREQ2 DSREQ1 SSREQ1 DSREQ0 SSREQ0

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 516 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

32.7.4 DMAC Software Chunk Transfer Request Register

Name: DMAC_CREQ Address: 0xFFFFEC0C Access: Read-write Reset: 0x00000000  DCREQx: Destination Chunk Request Request a destination chunk transfer on channel i.  SCREQx: Source Chunk Request Request a source chunk transfer on channel i. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 DCREQ7 SCREQ7 DCREQ6 SCRE Q6 DCREQ5 SCREQ5 DCREQ4 SCREQ4 76543210 DCREQ3 SCREQ3 DCREQ2 SCRE Q2 DCREQ1 SCREQ1 DCREQ0 SCREQ0

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 517 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

32.7.5 DMAC Software Last Transfer Flag Register

Name: DMAC_LAST Address: 0xFFFFEC10 Access: Read-write Reset: 0x00000000  DLASTx: Destination Last Writing one to DLASTx prior to writing one to DSREQx or DCREQx indicates that this destination request is the last transfer of the buffer.  SLASTx: Source Last Writing one to SLASTx prior to writing one to SSREQx or SCREQx indicates that this source request is the last transfer of the buffer. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 DLAST7 SLAST7 DLAST6 SLAST6 D LAST5 SLAST5 DLAST4 SLAST4 76543210 DLAST3 SLAST3 DLAST2 SLAST2 D LAST1 SLAST1 DLAST0 SLAST0

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 518 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

32.7.6 DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Enable Register

Name: DMAC_EBCIER Address: 0xFFFFEC18 Access: Write-only Reset: 0x00000000  BTCx: Buffer Transfer Completed [7:0] Buffer Transfer Completed Interrupt Enable Register. Set the relevant bit in the BTC field to enable the interrupt for channel  CBTCx: Chained Buffer Transfer Completed [7:0] Chained Buffer Transfer Completed Interrupt Enable Register. Set the relevant bit in the CBTC field to enable the interrupt for channel i.  ERRx: Access Error [7:0] Access Error Interrupt Enable Register. Set the relevant bit in the ERR field to enable the interrupt for channel i.  DICERRx: Descriptor Integrity Check Error [7:0] Descriptor Integrity Check Error Interrupt Enable Register. Se t the relevant bit in the DICERR field to enable the interrupt for channel i. 31 30 29 28 27 26 25 24 DICERR7 DICERR6 DICERR5 DICERR4 DICERR3 DICERR2 DICERR1 DICERR0 23 22 21 20 19 18 17 16 ERR7 ERR6 ERR5 ERR4 ERR3 ERR2 ERR1 ERR0 15 14 13 12 11 10 9 8 CBTC7 CBTC6 CBTC5 CBTC4 CBTC3 CBTC2 CBTC1 CBTC0 76543210 BTC7 BTC6 BTC5 BTC4 BTC3 BTC2 BTC1 BTC0

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 519 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

32.7.7 DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Disable Register

Name: DMAC_EBCIDR Address: 0xFFFFEC1C Access: Write-only Reset: 0x00000000  BTCx: Buffer Transfer Completed [7:0] Buffer transfer completed Disable Interrupt Register. When set, a bit of the BTC field disables the interrupt from the rele- vant DMAC channel.  CBTCx: Chained Buffer Transfer Completed [7:0] Chained Buffer transfer completed Disable Register. When set, a bit of the CBTC field disables the interrupt from the rele- vant DMAC channel.  ERRx: Access Error [7:0] Access Error Interrupt Disable Register. When set, a bit of t he ERR field disables the interrupt from the relevant DMAC channel.  DICERRx: Descriptor Integrity Check Error [7:0] Descriptor Integrity Check Error Interrupt Disable Register, When set, a bit of the DICERR field disables the interrupt from the relevant DMAC channel. 31 30 29 28 27 26 25 24 DICERR7 DICERR6 DICERR5 DICERR4 DICERR3 DICERR2 DICERR1 DICERR0 23 22 21 20 19 18 17 16 ERR7 ERR6 ERR5 ERR4 ERR3 ERR2 ERR1 ERR0 15 14 13 12 11 10 9 8 CBTC7 CBTC6 CBTC5 CBTC4 CBTC3 CBTC2 CBTC1 CBTC0 76543210 BTC7 BTC6 BTC5 BTC4 BTC3 BTC2 BTC1 BTC0

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 520 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

32.7.8 DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Mask Register

Name: DMAC_EBCIMR Address: 0xFFFFEC20 Access: Read-only Reset: 0x00000000  BTCx: Buffer Transfer Completed [7:0] 0: Buffer Transfer Completed Interrupt is disabled for channel i. 1: Buffer Transfer Completed Interrupt is enabled for channel i.  CBTCx: Chained Buffer Transfer Completed [7:0] 0: Chained Buffer Transfer interrupt is disabled for channel i. 1: Chained Buffer Transfer interrupt is enabled for channel i.  ERRx: Access Error [7:0] 0: Transfer Error Interrupt is disabled for channel i. 1: Transfer Error Interrupt is enabled for channel i.  DICERRx: Descriptor Integrity Check Error [7:0] 0: Descriptor Integrity Check Error Interrupt is disabled for channel i. 1: Descriptor Integrity Check Error Interrupt is enabled for channel i. 31 30 29 28 27 26 25 24 DICERR7 DICERR6 DICERR5 DICERR4 DICERR3 DICERR2 DICERR1 DICERR0 23 22 21 20 19 18 17 16 ERR7 ERR6 ERR5 ERR4 ERR3 ERR2 ERR1 ERR0 15 14 13 12 11 10 9 8 CBTC7 CBTC6 CBTC5 CBTC4 CBTC3 CBTC2 CBTC1 CBTC0 76543210 BTC7 BTC6 BTC5 BTC4 BTC3 BTC2 BTC1 BTC0

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 521 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

32.7.9 DMAC Error, Buffer Transfer and Chained Buffer Transfer Status Register

Name: DMAC_EBCISR Address: 0xFFFFEC24 Access: Read-only Reset: 0x00000000  BTCx: Buffer Transfer Completed [7:0] When BTC[i] is set, Channel i buffer transfer has terminated.  CBTCx: Chained Buffer Transfer Completed [7:0] When CBTC[i] is set, Channel i Chained buffer has terminated. LLI Fetch operation is disabled.  ERRx: Access Error [7:0] When ERR[i] is set, Channel i has detected an AHB Read or Write Error Access.  DICERRx: Descriptor Integrity Check Error [7:0] When DICERR[i] is set, Channel i has detected a Descriptor Integrity Check Error. 31 30 29 28 27 26 25 24 DICERR7 DICERR6 DICERR5 DICERR4 DICERR3 DICERR2 DICERR1 DICERR0 23 22 21 20 19 18 17 16 ERR7 ERR6 ERR5 ERR4 ERR3 ERR2 ERR1 ERR0 15 14 13 12 11 10 9 8 CBTC7 CBTC6 CBTC5 CBTC4 CBTC3 CBTC2 CBTC1 CBTC0 76543210 BTC7 BTC6 BTC5 BTC4 BTC3 BTC2 BTC1 BTC0

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 522 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

32.7.10 DMAC Channel Handler Enable Register

Name: DMAC_CHER Address: 0xFFFFEC28 Access: Write-only Reset: 0x00000000  ENAx: Enable [7:0] When set, a bit of the ENA field enables the relevant channel.  SUSPx: Suspend [7:0] When set, a bit of the SUSP field freezes the relevant channel and its current context.  KEEPx: Keep on [7:0] When set, a bit of the KEEP field resumes the current channel from an automatic stall state. 31 30 29 28 27 26 25 24 KEEP7 KEEP6 KEEP5 KEEP4 KEEP3 KEEP2 KEEP1 KEEP0 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 SUSP7 SUSP6 SUSP5 SUSP4 SUSP3 SUSP2 SUSP1 SUSP0 76543210 ENA7 ENA6 ENA5 ENA4 ENA3 ENA2 ENA1 ENA0

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 523 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

32.7.11 DMAC Channel Handler Disable Register

Name: DMAC_CHDR Address: 0xFFFFEC2C Access: Write-only Reset: 0x00000000  DISx: Disable [7:0] Write one to this field to disable the relevant DMAC Channel. The content of the FIFO is lost and the current AHB access is terminated. Software must poll DIS[7:0] field in the DMAC_CHSR register to be sure that the channel is disabled.  RESx: Resume [7:0] Write one to this field to resume the channel transfer restoring its context. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 RES7 RES6 RES5 RES4 RES3 RES2 RES1 RES0 76543210 DIS7 DIS6 DIS5 DIS4 DIS3 DIS2 DIS1 DIS0

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 524 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

32.7.12 DMAC Channel Handler Status Register

Name: DMAC_CHSR Address: 0xFFFFEC30 Access: Read-only Reset: 0x00FF0000  ENAx: Enable [7:0] A one in any position of this field indicates that the relevant channel is enabled.  SUSPx: Suspend [7:0] A one in any position of this field indicates that the channel transfer is suspended.  EMPTx: Empty [7:0] A one in any position of this field indicates that the relevant channel is empty.  STALx: Stalled [7:0] A one in any position of this field indicates that the relevant channel is stalling. 31 30 29 28 27 26 25 24 STAL7 STAL6 STAL5 STAL4 STAL3 STAL2 STAL1 STAL0 23 22 21 20 19 18 17 16 EMPT7 EMPT6 EMPT5 EMPT4 EMPT3 EMPT2 EMPT1 EMPT0 15 14 13 12 11 10 9 8 SUSP7 SUSP6 SUSP5 SUSP4 SUSP3 SUSP2 SUSP1 SUSP0 76543210 ENA7 ENA6 ENA5 ENA4 ENA3 ENA2 ENA1 ENA0

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 525 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 32.7.13 DMAC Channel x [x = 0..7] Source Address Register Name: DMAC_SADDRx [x = 0..7] Address: 0xFFFFEC3C [0], 0xFFFFEC64 [1], 0xFFFFEC8C [2], 0xFFFFECB4 [3], 0xFFFFECDC [4], 0xFFFFED04 [5], 0xFFFFED2C [6], 0xFFFFED54 [7] Access: Read-write Reset: 0x00000000 This register can only be written if the WPEN bit is cleared in “DMAC Write Protect Mode Register” .  SADDR: Channel x Source Address This register must be aligned with the source transfer width. 31 30 29 28 27 26 25 24 SADDR 23 22 21 20 19 18 17 16 SADDR 15 14 13 12 11 10 9 8 SADDR 76543210 SADDR

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 526 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 32.7.14 DMAC Channel x [x = 0..7] Destination Address Register Name: DMAC_DADDRx [x = 0..7] Address: 0xFFFFEC40 [0], 0xFFFFEC68 [1], 0xFFFFEC90 [2], 0xFFFFECB8 [3], 0xFFFFECE0 [4], 0xFFFFED08 [5], 0xFFFFED30 [6], 0xFFFFED58 [7] Access: Read-write Reset: 0x00000000 This register can only be written if the WPEN bit is cleared in “DMAC Write Protect Mode Register” .  DADDR: Channel x Destination Address This register must be aligned with the destination transfer width. 31 30 29 28 27 26 25 24 DADDR 23 22 21 20 19 18 17 16 DADDR 15 14 13 12 11 10 9 8 DADDR 76543210 DADDR

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 527 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 32.7.15 DMAC Channel x [x = 0..7] Descriptor Address Register Name: DMAC_DSCRx [x = 0..7] Address: 0xFFFFEC44 [0], 0xFFFFEC6C [1], 0xFFFFEC94 [2], 0xFFFFECBC [3], 0xFFFFECE4 [4], 0xFFFFED0C [5], 0xFFFFED34 [6], 0xFFFFED5C [7] Access: Read-write Reset: 0x00000000 This register can only be written if the WPEN bit is cleared in “DMAC Write Protect Mode Register” . D S C R _ I F  DSCR: Buffer Transfer Descriptor Address This address is word aligned. 31 30 29 28 27 26 25 24 DSCR 23 22 21 20 19 18 17 16 DSCR 15 14 13 12 11 10 9 8 DSCR 76543210 DSCR DSCR_IF Value Name Description

00 AHB_IF0 The buffer transfer descriptor is fetched via AHB-Lite Interface 0

01 AHB_IF1 The buffer transfer descriptor is fetched via AHB-Lite Interface 1

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 528 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 32.7.16 DMAC Channel x [x = 0..7] Control A Register Name: DMAC_CTRLAx [x = 0..7] Address: 0xFFFFEC48 [0], 0xFFFFEC70 [1], 0xFFFFEC98 [2], 0xFFFFECC0 [3], 0xFFFFECE8 [4], 0xFFFFED10 [5], 0xFFFFED38 [6], 0xFFFFED60 [7] Access: Read-write Reset: 0x00000000 This register can only be written if the WPEN bit is cleared in “DMAC Write Protect Mode Register” on page 536  BTSIZE: Buffer Transfer Size The transfer size relates to the number of transfers to be performed, that is, for writes it refers to the number of source width transfers to perform when DMAC is flow controller. For Reads, BTSIZE refers to the number of transfers completed on the Source Interface. When this field is set to 0, the DMAC module is automatically disabled when the relevant channel is enabled.  SCSIZE: Source Chunk Transfer Size.  DCSIZE: Destination Chunk Transfer Size 31 30 29 28 27 26 25 24 DONE – DST_WIDTH – – SRC_WIDTH 23 22 21 20 19 18 17 16 – DCSIZE – SCSIZE 15 14 13 12 11 10 9 8 BTSIZE 76543210 BTSIZE Value Name Description

000 CHK_1 1 data transferred

001 CHK_4 4 data transferred

010 CHK_8 8 data transferred

011 CHK_16 16 data transferred

100 CHK_32 32 data transferred

101 CHK_64 64 data transferred

110 CHK_128 128 data transferred

111 CHK_256 256 data transferred

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 529 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12  SRC_WIDTH: Transfer Width for the Source  DST_WIDTH: Transfer Width for the Destination D O N E 0: The transfer is performed. 1: If SOD field of DMAC_CFG register is set to true, then the DMAC is automatically disabled when an LLI updates the con- tent of this register. The DONE field is written back to memory at the end of the transfer.

00 BYTE the transfer size is set to 8-bit width

01 HALF_WORD the transfer size is set to 16-bit width

1X WORD the transfer size is set to 32-bit width Value Name Description 1X WORD the transfer size is set to 32-bit width Value Name Description

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 530 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 32.7.17 DMAC Channel x [x = 0..7] Control B Register Name: DMAC_CTRLBx [x = 0..7] Address: 0xFFFFEC4C [0], 0xFFFFEC74 [1], 0xFFFFEC9C [2], 0xFFFFECC4 [3], 0xFFFFECEC [4], 0xFFFFED14 [5], 0xFFFFED3C [6], 0xFFFFED64 [7] Access: Read-write Reset: 0x00000000 This register can only be written if the WPEN bit is cleared in “DMAC Write Protect Mode Register” .  SIF: Source Interface Selection Field  DIF: Destination Interface Selection Field  SRC_PIP: Source Picture-in-Picture Mode 0 (DISABLE): Picture-in-Picture mode is disabled. The source data area is contiguous. 1 (ENABLE): Picture-in-Picture mode is enabled. When the source PIP counter reaches the programmable boundary, the address is automatically incremented by a user defined amount.  DST_PIP: Destination Picture-in-Picture Mode 0 (DISABLE): Picture-in-Picture mode is disabled. The Destination data area is contiguous. 1 (ENABLE): Picture-in-Picture mode is enabled. When the Destination PIP counter reaches the programmable boundary the address is automatically incremented by a user-defined amount.  SRC_DSCR: Source Address Descriptor 0 (FETCH_FROM_MEM): Source address is updated when the descriptor is fetched from the memory. 1 (FETCH_DISABLE): Buffer Descriptor Fetch operation is disabled for the source. 31 30 29 28 27 26 25 24 AUTO IEN DST_INCR – – SRC_INCR 23 22 21 20 19 18 17 16 FC DST_DSCR – – – SRC_DSCR 15 14 13 12 11 10 9 8 76543210 –– D IF –– S IF Value Name Description

00 AHB_IF0 The source transfer is done via AHB-Lite Interface 0

01 AHB_IF1 The source transfer is done via AHB-Lite Interface 1

00 AHB_IF0 The destination transfer is done via AHB-Lite Interface 0

01 AHB_IF1 The destination transfer is done via AHB-Lite Interface 1

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 531 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12  DST_DSCR: Destination Address Descriptor 0 (FETCH_FROM_MEM): Destination address is updated when the descriptor is fetched from the memory. 1 (FETCH_DISABLE): Buffer Descriptor Fetch operation is disabled for the destination.  FC: Flow Control This field defines which device controls the size of the buffer transfer, also referred to as the Flow Controller.  SRC_INCR: Incrementing, Decrementing or Fixed Address for the Source  DST_INCR: Incrementing, Decrementing or Fixed Address for the Destination I E N If this bit is cleared, when the buffer transfer is completed, th e BTCx flag is set in the EBCISR status register. This bit is active low.  AUTO: Automatic Multiple Buffer Transfer 0 (DISABLE): Automatic multiple buffer transfer is disabled. 1 (ENABLE): Automatic multiple buffer transfer is enabled. This bit enables replay mode or contiguous mode when several buffers are transferred. Value Name Description

000 MEM2MEM_DMA_FC Memory-to-Memory Transfer DMAC is flow controller

001 MEM2PER_DMA_FC Memory-to-Peripheral Transfer DMAC is flow controller

010 PER2MEM_DMA_FC Peripheral-to-Memory Transfer DMAC is flow controller

011 PER2PER_DMA_FC Peripheral-to-Peripheral Transfer DMAC is flow controller

00 INCREMENTING The source address is incremented

01 DECREMENTING The source address is decremented

10 FIXED The source address remains unchanged

00 INCREMENTING The destinat ion address is incremented

01 DECREMENTING The destinat ion address is decremented

10 FIXED The destination address remains unchanged

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 532 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 32.7.18 DMAC Channel x [x = 0..7] Configuration Register Name: DMAC_CFGx [x = 0..7] Address: 0xFFFFEC50 [0], 0xFFFFEC78 [1], 0xFFFFECA0 [2], 0xFFFFECC8 [3], 0xFFFFECF0 [4], 0xFFFFED18 [5], 0xFFFFED40 [6], 0xFFFFED68 [7] Access: Read-write Reset: 0x0100000000 This register can only be written if the WPEN bit is cleared in “DMAC Write Protect Mode Register” on page 536  SRC_PER: Source with Peripheral identifier Channel x Source Request is associated with peripheral identifier coded SRC_PER handshaking interface.  DST_PER: Destination with Peripheral identifier Channel x Destination Request is associated with peripheral identifier coded DST_PER handshaking interface.  SRC_REP: Source Reloaded from Previous 0 (CONTIGUOUS_ADDR): When automatic mode is activated, source address is contiguous between two buffers. 1 (RELOAD_ADDR): When automatic mode is activated, the source address and the control register are reloaded from previous transfer.  SRC_H2SEL: Software or Hard ware Selection for the Source 0 (SW): Software handshaking interface is used to trigger a transfer request. 1 (HW): Hardware handshaking interface is used to trigger a transfer request.  SRC_PER_MSB: SRC_PER Most Significant Bits This field indicates the Most Significant bits of the SRC_PER field.  DST_REP: Destination Reloaded from Previous 0 (CONTIGUOUS_ADDR): When automatic mode is activated, destination address is contiguous between two buffers. 1 (RELOAD_ADDR): When automatic mode is activated, the destination and the control register are reloaded from the pre- vious transfer.  DST_H2SEL: Software or Hardware Selection for the Destination 0 (SW): Software handshaking interface is used to trigger a transfer request. 1 (HW): Hardware handshaking interface is used to trigger a transfer request. 31 30 29 28 27 26 25 24 – – FIFOCFG – AHB_PROT 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 DST_PER_MSB DST_H2SEL DST_REP SRC_PER_MSB SRC_H2SEL SRC_REP 76543210 DST_PER SRC_PER

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 533 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12  DST_PER_MSB: DST_PER Most Significant Bits This field indicates the Most Significant bits of the DST_PER field.  SOD: Stop On Done 0 (DISABLE): STOP ON DONE disabled, the descriptor fetch operation ignores DONE Field of CTRLA register. 1 (ENABLE): STOP ON DONE activated, the DMAC module is automatically disabled if DONE FIELD is set to 1.  LOCK_IF: Interface Lock 0 (DISABLE): Interface Lock capability is disabled 1 (ENABLE): Interface Lock capability is enabled  LOCK_B: Bus Lock 0 (DISABLE): AHB Bus Locking capability is disabled. 1(ENABLE): AHB Bus Locking capability is enabled.  LOCK_IF_L: Master Interface Arbiter Lock 0 (CHUNK): The Master Interface Arbiter is locked by the channel x for a chunk transfer. 1 (BUFFER): The Master Interface Arbiter is locked by the channel x for a buffer transfer.  AHB_PROT: AHB Protection AHB_PROT field provides additional information about a bus access and is primarily used to implement some level of protection.  FIFOCFG: FIFO Configuration HPROT[3] HPROT[2] HPROT[1] HPROT[0] Description

1 Data access

AHB_PROT[0] 0: User Access 1: Privileged Access AHB_PROT[1] 0: Not Bufferable 1: Bufferable AHB_PROT[2] 0: Not cacheable 1: Cacheable Value Name Description 00 ALAP_CFG The largest defined length AHB burst is performed on the destination AHB interface. 01 HALF_CFG When half FIFO size is available/fill ed, a source/destination request is serviced.

10 ASAP_CFG When there is enough space/data available to perform a single AHB access, then the

request is serviced.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 534 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 32.7.19 DMAC Channel x [x = 0..7] Source Picture-in-Picture Configuration Register Name: DMAC_SPIPx [x = 0..7] Address: 0xFFFFEC54 [0], 0xFFFFEC7C [1], 0xFFFFECA4 [2], 0xFFFFECCC [3], 0xFFFFECF4 [4], 0xFFFFED1C [5], 0xFFFFED44 [6], 0xFFFFED6C [7] Access: Read-write Reset: 0x00000000 This register can only be written if the WPEN bit is cleared in “DMAC Write Protect Mode Register” on page 536  SPIP_HOLE: Source Picture-in-Picture Hole This field indicates the value to add to the address when the programmable boundary has been reached.  SPIP_BOUNDARY: Source Picture-in-Picture Boundary This field indicates the number of source transfers to perform before the automatic address increment operation. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SPIP_BOUNDARY 15 14 13 12 11 10 9 8 SPIP_HOLE 76543210 SPIP_HOLE

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 535 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 32.7.20 DMAC Channel x [x = 0..7] Destination Picture-in-Picture Configuration Register Name: DMAC_DPIPx [x = 0..7] Address: 0xFFFFEC58 [0], 0xFFFFEC80 [1], 0xFFFFECA8 [2], 0xFFFFECD0 [3], 0xFFFFECF8 [4], 0xFFFFED20 [5], 0xFFFFED48 [6], 0xFFFFED70 [7] Access: Read-write Reset: 0x00000000 This register can only be written if the WPEN bit is cleared in “DMAC Write Protect Mode Register” on page 536  DPIP_HOLE: Destination Picture-in-Picture Hole This field indicates the value to add to the address when the programmable boundary has been reached.  DPIP_BOUNDARY: Destination Picture-in-Picture Boundary This field indicates the number of source transfers to perform before the automatic address increment operation. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DPIP_BOUNDARY 15 14 13 12 11 10 9 8 DPIP_HOLE 76543210 DPIP_HOLE

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 536 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

32.7.21 DMAC Write Protect Mode Register

Name: DMAC_WPMR Address: 0xFFFFEDE4 Access: Read-write Reset: See Table 32-4  WPEN: Write Protect Enable 0 = Disables the Write Protect if WPKEY corresponds to 0x444D4143 (“DMAC” in ASCII). 1 = Enables the Write Protect if WPKEY corresponds to 0x444D4143 (“DMAC” in ASCII). Protects the registers:

  • “DMAC Global Configuration Register” on page 513
  • “DMAC Enable Register” on page 514
  • “DMAC Channel x [x = 0..7] Source Address Register” on page 525
  • “DMAC Channel x [x = 0..7] Destination Address Register” on page 526
  • “DMAC Channel x [x = 0..7] Descriptor Address Register” on page 527
  • “DMAC Channel x [x = 0..7] Control A Register” on page 528
  • “DMAC Channel x [x = 0..7] Control B Register” on page 530
  • “DMAC Channel x [x = 0..7] Configuration Register” on page 532
  • “DMAC Channel x [x = 0..7] Source Picture-in-Picture Configuration Register” on page 534
  • “DMAC Channel x [x = 0..7] Destination Picture-in-Picture Configuration Register” on page 535  WPKEY: Write Protect KEY Should be written at value 0x50494F (“DMAC” in ASCII). Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. 31 30 29 28 27 26 25 24 WPKEY 23 22 21 20 19 18 17 16 WPKEY 15 14 13 12 11 10 9 8 WPKEY 76543210

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 537 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

32.7.22 DMAC Write Protect Status Register

Name: DMAC_WPSR Address: 0xFFFFEDE8 Access: Read-only Reset: See Table 32-4  WPVS: Write Protect Violation Status 0 = No Write Protect Violation has occurred since the last read of the DMAC_WPSR register. 1 = A Write Protect Violation has occurred since the last read of the DMAC_WPSR register. If this violation is an unauthor- ized attempt to write a protected register, the associated violation is reported into field WPVSRC.  WPVSRC: Write Protect Violation Source When WPVS is active, this field indicates the write-protected register (t hrough address offset or code) in which a write access has been attempted. Note: Reading DMAC_WPSR automatically clears all fields. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WPVSRC 15 14 13 12 11 10 9 8 WPVSRC 76543210

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 538 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 539 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 33. USB Device Port (UDP)

33.1 Description

The USB Device Port (UDP) is compliant with the Universal Serial Bus (USB) V2.0 full-speed device specification. Each endpoint can be configured in one of several USB transfer types. It can be associated with one or two banks of a dual-port RAM used to store the current data payload. If two banks are used, one DPR bank is read or written by the processor, while the other is read or written by the USB device peripheral. This feature is mandator y for isochronous endpoints. Thus the device maintains the maximum bandwidth (1M bytes/s) by working with endpoints with two banks of DPR. Note: 1. The Dual-Bank function provides two banks for an endpoint. This feature is used for ping-pong mode. Suspend and resume are automatically detected by the USB device, which notifies the proces- sor by raising an interrupt. Depending on the product, an external signal can be used to send a wake up to the USB host controller.

33.2 Embedded Characteristics

  • USB V2.0 Full-speed Complia nt, 12 Mbits per Second
  • Embedded USB V2.0 Full-speed Transceiver
  • 6 Endpoints
  • Embedded Dual-port RAM for Endpoints
  • Suspend/Resume Logic
  • Ping-pong Mode (2 Memory Banks) for Isochronous and Bulk Endpoints
  • Compatible With Embedded ARM7TDMI and ARM9TDMI Processor
  • Can be Directly Connected to the Atmel Implementation of the AMBA Peripheral Bus (APB) Table 33-1. USB Endpoint Description Endpoint Number Mnemonic Dual-Bank (1) Max. Endpoint Size Endpoint Type

0 EP0 No 64 Control/Bulk/Interrupt

1 EP1 Y es 64 Bulk/Iso/Interrupt

2 EP2 Y es 64 Bulk/Iso/Interrupt

3 EP3 No 64 Control/Bulk/Interrupt

4 EP4 Y es 512 Bulk/Iso/Interrupt

5 EP5 Y es 512 Bulk/Iso/Interrupt

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 540 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

33.3 Block Diagram

Figure 33-1. Block Diagram Access to the UDP is via the APB bus interface. Read and write to the data FI FO are done by reading and writing 8-bit values to APB registers. The UDP peripheral requires two clocks: one peripheral clock used by the Master Clock domain (MCK) and a 48 MHz clock (UDPCK) used by the 12 MHz domain. A USB 2.0 full-speed pad is embedded and controlled by the Serial Interface Engine (SIE).

33.3.1 Signal Description

33.4 Product Dependencies

For further details on the USB Device hardware implementation, see the specific Product Prop- erties document. The USB physical transceiver is integrated into the product. The bidirectional differential signals DDP and DDM are available from the product boundary. Atmel Bridge W r a p p e r W r a p p e r U s e r I n t e r f a c e Serial Interface Engine SIE MCK Master Clock Domain Dual Port RAM FIFO UDPCK Recovered 12 MHz Domain udp_int USB Device Embedded USB Transceiver DDP DDM APB to MCU Bus txoen eopn txd rxdm rxd rxdp Table 33-2. Signal Names Signal Name Description Type UDPCK 48 MHz clock input MCK Master clock input udp_int Interrupt line connected to the Interrupt Controller input DDP USB D+ line I/O DDM USB D- line I/O

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 541 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

33.4.1 I/O Lines

DDP and DDM are not controlled by any PIO controllers. The embedded USB physical trans- ceiver is controlled by the USB device peripheral. To reserve an I/O line to check VBUS, the program mer must first program the PIO controller to assign this I/O in input PIO mode.

33.4.2 Power Management

The USB device peripheral requires a 48 MHz cl ock. This clock must be generated by a PLL with an accuracy of ± 0.25%. Thus, the USB device receives two clocks from the Power Management Controller (PMC): the master clock, MCK, used to drive the peripheral user interface, and the UDPCK, used to inter- face with the bus USB signals (recovered 12 MHz domain). WARNING: The UDP peripheral clock in the Power Management Controller (PMC) must be enabled before any read/write operations to the UDP registers including the UDP_TXVC register.

33.4.3 Interrupt

The USB device interface has an interrupt line connected to the Interrupt Controller. Handling the USB device interrupt requires programming the Interrupt Controller before config- uring the UDP.

33.5 Typical Connection

Figure 33-2. Board Schematic to Interface Device Peripheral

33.5.1 USB Device Transceiver

The USB device transceiver is embedded in the product. A few discrete components are required as follows:

  • the application detects all device states as defined in chapter 9 of the USB specification; –V B U S m o n i t o r i n g Table 33-3. Peripheral IDs Instance ID UDP 23 REXT REXT DDM DDP PIO 27 K 47 K Type B Connector 5V Bus Monitoring

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 542 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

  • to reduce power consumption the host is disconnected
  • for line termination.

33.5.2 VBUS Monitoring

VBUS monitoring is required to detect host connection. VBUS monitoring is done using a stan- dard PIO with internal pullup disabled. When the host is switched off, it should be considered as a disconnect, the pullup must be disabled in order to prevent powering the host through the pull- up resistor. When the host is disconnected and the transceiver is enabled, then DDP and DDM are floating. This may lead to over consumption. A solution is to enable the integrated pulldown by disabling the transceiver (TXVDIS = 1) and then remove the pullup (PUON = 0). A termination serial resistor must be connected to DDP and DDM. The resistor value is defined in the electrical specification of the product (R EXT).

33.6 Functional Description

33.6.1 USB V2.0 Full-speed Introduction The USB V2.0 full-speed provides communication services between host and attached USB devices. Each device is offered with a collection of communication flows (pipes) associated with each endpoint. Software on the host communicates with a USB device through a set of commu- nication flows. Figure 33-3. Example of USB V2.0 Full-speed Communication Control The Control Transfer endpoint EP0 is always used when a USB device is first configured (USB v. 2.0 specifications). EP0 USB Host V2.0 Software Client 1 Software Client 2 Data Flow: Bulk Out Transfer Data Flow: Bulk In Transfer Data Flow: Control Transfer Data Flow: Control Transfer EP1 EP2 USB Device 2.0 Block 1 USB Device 2.0 Block 2 EP5 EP4 EP0 Data Flow: Isochronous In Transfer Data Flow: Isochronous Out Transfer USB Device endpoint configuration requires that in the first instance Control Transfer must be EP0.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 543 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 33.6.1.1 USB V2.0 Full-speed Transfer Types A communication flow is carried over one of four transfer types defined by the USB device.

33.6.1.2 USB Bus Transactions

Each transfer results in one or more transactions over the USB bus. There are three kinds of transactions flowing across the bus in packets: 1. Setup Transaction 2. Data IN Transaction 3. Data OUT Transaction

33.6.1.3 USB Transfer Event Definitions

As indicated below, transfers are sequential events carried out on the USB bus. Notes: 1. Control transfer must use endpoints with no ping-pong attributes. 2. Isochronous transfers must use endpoints with ping-pong attributes. 3. Control transfers can be aborted using a stall handshake. Table 33-4. USB Communication Flow Transfer Direction Bandwidth Supported Endpoint Size Error Detection Retrying Control Bidirectional Not guaranteed 8, 16, 32, 64 Y es Automatic Isochronous Unidirectional Guaranteed 512 Y es No Interrupt Unidirectional Not guaranteed ≤ 64 Y es Y es Bulk Unidirectional Not guaranteed 8, 16, 32, 64 Y es Y es Table 33-5. USB Transfer Events Control Transfers(1) (3)

  • Setup transaction > Data IN transactions > Status OUT transaction
  • Setup transaction > Data OUT transactions > Status IN transaction
  • Setup transaction > Status IN transaction Interrupt IN Transfer (device toward host)
  • Data IN transaction > Data IN transaction Interrupt OUT Transfer (host toward device)
  • Data OUT transaction > Data OUT transaction Isochronous IN Transfer(2) (device toward host)
  • Data IN transaction > Data IN transaction Isochronous OUT Transfer(2) (host toward device)
  • Data OUT transaction > Data OUT transaction Bulk IN Transfer (device toward host)
  • Data IN transaction > Data IN transaction Bulk OUT Transfer (host toward device)
  • Data OUT transaction > Data OUT transaction

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 544 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 A status transaction is a special type of host-to-device transaction used only in a control transfer. The control transfer must be performed using endpoints with no ping-pong attributes. According to the control sequence (read or write), the USB device sends or receives a status transaction. Figure 33-4. Control Read and Write Sequences Notes: 1. During the Status IN stage, the host waits for a zero length packet (Data IN transaction with no data) from the device using DATA1 PID. Refer to Chapter 8 of the Universal Serial Bus Specification, Rev. 2.0, for more information on the protocol layer. 2. During the Status OUT stage, the host emits a zero length packet to the device (Data OUT transaction with no data). 33.6.2 Handling Transactions with USB V2.0 Device Peripheral

33.6.2.1 Setup Transaction

Setup is a special type of host-to-device transaction used during control transfers. Control trans- fers must be performed using endpoints with no ping-pong attributes. A setup transaction needs to be handled as soon as possible by the firmware. It is used to transmit requests from the host to the device. These requests are then handled by the USB device and may require more argu- ments. The arguments are sent to the device by a Data OUT transaction which follows the setup transaction. These requests may also return data. The data is carried out to the host by the next Data IN transaction which follows the setup transaction. A status transaction ends the control transfer. When a setup transfer is received by the USB endpoint:

  • The USB device automatically acknowledges the setup packet
  • RXSETUP is set in the UDP_CSRx register
  • An endpoint interrupt is generated while the RXSETUP is not cleared. This interrupt is carried out to the microcontroller if interrupts are enabled for this endpoint. Thus, firmware must detect the RXSETUP polling the UDP_CSRx or catching an interrupt, read the setup packet in the FIFO, then clear the RXSETUP. RXSETUP cannot be cleared before the Control Read Setup TX Data OUT TX Data OUT TX Data Stage Control Write Setup Stage Setup Stage Setup TX Setup TXNo Data Control Data IN TX Data IN TX Status Stage Status Stage Status IN TX Status OUT TX Status IN TX Data Stage Setup Stage Status Stage

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 545 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 setup packet has been read in the FIFO. Otherwise, the USB device would accept the next Data OUT transfer and overwrite the setup packet in the FIFO. Figure 33-5. Setup Transaction Followed by a Data OUT Transaction

33.6.2.2 Data IN Transaction

Data IN transactions are used in control, is ochronous, bulk and interrupt transfers and conduct the transfer of data from the device to the host. Data IN transactions in isochronous transfer must be done using endpoints with ping-pong attributes. Using Endpoints Without Ping-pong Attributes To perform a Data IN transaction using a non ping-pong endpoint: 1. The application checks if it is possible to write in the FIFO by polling TXPKTRDY in the endpoint’s UDP_CSRx register (TXPKTRDY must be cleared). 2. The application writes the first packet of data to be sent in the endpoint’s FIFO, writing zero or more byte values in the endpoint’s UDP_FDRx register, 3. The application notifies the USB peripheral it has finished by setting the TXPKTRDY in the endpoint’s UDP_CSRx register. 4. The application is notified that the endpoint’s FIFO has been released by the USB device when TXCOMP in the endpoint’s UDP_CSRx register has been set. Then an interrupt for the corresponding endpoint is pending while TXCOMP is set. 5. The microcontroller writes the second packet of data to be sent in the endpoint’s FIFO, writing zero or more byte values in the endpoint’s UDP_FDRx register, 6. The microcontroller notifi es the USB peripheral it has finished by setting the TXPK- TRDY in the endpoint’s UDP_CSRx register. 7. The application clears the TXCOMP in the endpoint’s UDP_CSRx. After the last packet has been sent, the application must clear TXCOMP once this has been set. TXCOMP is set by the USB device when it has received an ACK PID signal for the Data IN packet. An interrupt is pending while TXCOMP is set. Warning: TX_COMP must be cleared after TX_PKTRDY has been set. RX_Data_BKO (UDP_CSRx) ACK PIDData OUTData OUT PID NAK PID ACK PIDData SetupSetup PID USB Bus Packets RXSETUP Flag Set by USB Device Cleared by Firmware Set by USB Device Peripheral FIFO (DPR) Content Data Setup DataXX XX OUT Interrupt Pending Setup Received Setup Handled by Firmware Data Out Received Data OUTData OUT PID

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 547 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 When using a ping-pong endpoint, the following procedures are required to perform Data IN transactions: 1. The microcontroller checks if it is possible to write in the FIFO by polling TXPKTRDY to be cleared in the endpoint’s UDP_CSRx register. 2. The microcontroller writes the first data payload to be sent in the FIFO (Bank 0), writing zero or more byte values in the endpoint’s UDP_FDRx register. 3. The microcontroller notifies the USB peripheral it has finished writing in Bank 0 of the FIFO by setting the TXPKTRDY in the endpoint’s UDP_CSRx register. 4. Without waiting for TXPKTRDY to be cleare d, the microcontroller writes the second data payload to be sent in the FIFO (Bank 1), writing zero or more byte values in the endpoint’s UDP_FDRx register. 5. The microcontroller is notified that the first Bank has been released by the USB device when TXCOMP in the endpoint’s UDP_CSRx register is set. An interrupt is pending while TXCOMP is being set. 6. Once the microcontroller has received TXCO MP for the first Bank, it notifies the USB device that it has prepared the second Bank to be sent, raising TXPKTRDY in the end- point’s UDP_CSRx register. 7. At this step, Bank 0 is available and the microcontroller can prepare a third data pay- load to be sent Figure 33-8. Data IN Transfer for Ping-pong Endpoint Warning: There is software critical path due to the fact that once the second bank is filled, the driver has to wait for TX_COMP to set TX_PKTRDY. If the delay between receiving TX_COMP is set and TX_PKTRDY is set too long, some Data IN packets may be NACKed, reducing the bandwidth. Warning: TX_COMP must be cleared after TX_PKTRDY has been set. Data INData IN Read by USB Device Read by USB DeviceBank 1 Bank 0 FIFO (DPR) TXCOMP Flag (UDP_CSRx) Interrupt Cleared by Firmware Set by USB Device TXPKTRDY Flag (UDP_MCSRx) ACKPID Data IN PID ACKPID Set by Firmware, Data Payload Written in FIFO Bank 1 Cleared by USB Device, Data Payload Fully Transmitted Data IN PID USB Bus Packets Set by USB Device Set by Firmware, Data Payload Written in FIFO Bank 0 Written by FIFO (DPR) Microcontroller Written by MicrocontrollerWritten by Microcontroller Microcontroller Load Data IN Bank 0 Microcontroller Load Data IN Bank 1 USB Device Send Bank 0 Microcontroller Load Data IN Bank 0 USB Device Send Bank 1 Interrupt Pending

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 548 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

33.6.2.3 Data OUT Transaction

Data OUT transactions are used in control, isochronous, bulk and interru pt transfers and con- duct the transfer of data from the host to the device. Data OUT transactions in isochronous transfers must be done using endpoints with ping-pong attributes. Data OUT Transaction Without Ping-pong Attributes To perform a Data OUT transaction, using a non ping-pong endpoint: 1. The host generates a Data OUT packet. 2. This packet is received by the USB device endpoint. While the FIFO associated to this endpoint is being used by the microcontroller, a NAK PID is returned to the host. Once the FIFO is available, data are written to the FIFO by the USB device and an ACK is automatically carried out to the host. 3. The microcontroller is notifie d that the USB device has received a data payload polling RX_DATA_BK0 in the endpoint’s UDP_CSRx register. An interrupt is pending for this endpoint while RX_DATA_BK0 is set. 4. The number of bytes available in the FIFO is made available by reading RXBYTECNT in the endpoint’s UDP_CSRx register. 5. The microcontroller carries out data received from the endpoint’s memory to its mem- ory. Data received is available by reading the endpoint’s UDP_FDRx register. 6. The microcontroller notifies the USB device that it has finished the transfer by clearing RX_DATA_BK0 in the endpoint’s UDP_CSRx register. 7. A new Data OUT packet can be accepted by the USB device. Figure 33-9. Data OUT Transfer for Non Ping-pong Endpoints An interrupt is pending while the flag RX_DAT A_BK0 is set. Memory transfer between the USB device, the FIFO and microcontroller memory can not be done after RX_DATA_BK0 has been cleared. Otherwise, the USB device would acce pt the next Data OUT transfer and overwrite the current Data OUT packet in the FIFO. Using Endpoints With Ping-pong Attributes During isochronous transfer, using an endpoint wit h ping-pong attributes is obligatory. To be able to guarantee a constant bandwidth, the micr ocontroller must read the previous data pay- ACK PID Data OUTNAK PIDPIDPIDPIDPID Data OUT2ACKData OUT Data OUT 1USB Bus Packets RX_DATA_BK0 Set by USB Device Cleared by Firmware, Data Payload Written in FIFO FIFO (DPR) Content Written by USB Device Microcontroller Read Data OUT 1 Data OUT 1 Data OUT 2 Host Resends the Next Data Payload Microcontroller Transfers Data Host Sends Data Payload Data OUT2 Data OUT2 Host Sends the Next Data Payload Written by USB Device (UDP_CSRx) Interrupt Pending

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 549 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 load sent by the host, while the current data payload is received by the USB device. Thus two banks of memory are used. While one is available for the microcontroller, the other one is locked by the USB device. Figure 33-10. Bank Swapping in Data OUT Transfers for Ping-pong Endpoints When using a ping-pong endpoint, the following procedures are required to perform Data OUT transactions: 1. The host generates a Data OUT packet. 2. This packet is received by the USB device endpoint. It is written in the endpoint’s FIFO Bank 0. 3. The USB device sends an ACK PID packet to the host. The host can immediately send a second Data OUT packet. It is accepted by the device and copied to FIFO Bank 1. 4. The microcontroller is notifi ed that the USB device has received a data payload, polling RX_DATA_BK0 in the endpoint’s UDP_CSRx register. An interrupt is pending for this endpoint while RX_DATA_BK0 is set. 5. The number of bytes available in the FIFO is made available by reading RXBYTECNT in the endpoint’s UDP_CSRx register. 6. The microcontroller transfers out data received from the endpoint’s memory to the microcontroller’s memory. Data received is made available by reading the endpoint’s UDP_FDRx register. 7. The microcontroller notifies the USB peripheral device that it has finished the transfer by clearing RX_DATA_BK0 in the endpoint’s UDP_CSRx register. 8. A third Data OUT packet can be accepted by the USB peripheral device and copied in the FIFO Bank 0. 9. If a second Data OUT packet has been received, the microcontroller is notified by the flag RX_DATA_BK1 set in the endpoint’s UDP_CSRx register. An interrupt is pending for this endpoint while RX_DATA_BK1 is set. 10. The microcontroller transfers out data received from the endpoint’s memory to the microcontroller’s memory. Data received is available by reading the endpoint’s UDP_FDRx register. USB Device USB Bus ReadWrite Write and Read at the Same Time 1st Data Payload 2nd Data Payload 3rd Data Payload 3rd Data Payload 2nd Data Payload 1st Data Payload Data IN Packet Data IN Packet Data IN Packet Microcontroller Endpoint 1 Bank 0 Endpoint 1 Bank 1 Endpoint 1 Bank 0 Endpoint 1 Bank 0 Endpoint 1 Bank 0 Endpoint 1 Bank 1

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 550 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 11. The microcontroller notifies the USB device it has finished the transfer by clearing RX_DATA_BK1 in the endpoint’s UDP_CSRx register. 12. A fourth Data OUT packet can be accepted by the USB device and copied in the FIFO Bank 0. Figure 33-11. Data OUT Transfer for Ping-pong Endpoint Note: An interrupt is pending while the RX_DATA_BK0 or RX_DATA_BK1 flag is set. Warning: When RX_DATA_BK0 and RX_DATA_BK1 are both set, there is no way to determine which one to clear first. Thus the software must keep an internal counter to be sure to clear alter- natively RX_DATA_BK0 then RX_DATA_BK1. This situation may occur when the software application is busy elsewhere and the two banks are filled by the USB host. Once the application comes back to the USB driver, the two flags are set.

33.6.2.4 Stall Handshake

A stall handshake can be used in one of two distinct occasions. (For more information on the stall handshake, refer to Chapter 8 of the Universal Serial Bus Specification, Rev 2.0.)

  • A functional stall is used when the halt feature associated with the endpoint is set. (Refer to Chapter 9 of the Universal Serial Bus Specification, Rev 2.0, for more information on the halt feature.)
  • To abort the current request, a protocol stall is used, but uniquely with control transfer. The following procedure generates a stall packet: 1. The microcontroller sets the FORCESTALL flag in the UDP_CSRx endpoint’s register. 2. The host receives the stall packet. A P Data OUT PID ACK Data OUT 3Data OUTData OUT 2Data OUTData OUT 1PID Data OUT 3Data OUT 1Data OUT1 Data OUT 2 Data OUT 2 PID PID PID ACK Cleared by Firmware USB Bus Packets RX_DATA_BK0 Flag RX_DATA_BK1 Flag Set by USB Device, Data Payload Written in FIFO Endpoint Bank 1 FIFO (DPR) Bank 0 Bank 1 Write by USB Device Write In Progress Read By Microcontroller Read By Microcontroller Set by USB Device, Data Payload Written in FIFO Endpoint Bank 0 Host Sends First Data Payload Microcontroller Reads Data 1 in Bank 0, Host Sends Second Data Payload Microcontroller Reads Data2 in Bank 1, Host Sends Third Data Payload Cleared by Firmware Write by USB Device FIFO (DPR) (UDP_CSRx) (UDP_CSRx) Interrupt Pending Interrupt Pending

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 552 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

33.6.2.5 Transmit Data Cancellation

Some endpoints have dual-banks whereas some endpoints have only one bank. The procedure to cancel transmission data held in these banks is described below. To see the organization of dual-bank availability refer to Table 33-1 ”USB Endpoint Description”. Endpoints Without Dual-Banks There are two possibilities: In one case, TXPKTRDY field in UDP_CSR has already been set. In the other instance, TXPKTRDY is not set.

  • TXPKTRDY is not set: – Reset the endpoint to clear the FIFO (pointers). (See Section 33.7.9 ”UDP Reset Endpoint Register”.)
  • TXPKTRDY has already been set: – Clear TXPKTRDY so that no packet is ready to be sent – Reset the endpoint to clear the FIFO (pointers). (See Section 33.7.9 ”UDP Reset Endpoint Register”.) Endpoints With Dual-Banks There are two possibilities: In one case, TXPKTRDY field in UDP_CSR has already been set. In the other instance, TXPKTRDY is not set.
  • TXPKTRDY is not set: – Reset the endpoint to clear the FIFO (pointers). (See Section 33.7.9 ”UDP Reset Endpoint Register”.)
  • TXPKTRDY has already been set: – Clear TXPKTRDY and read it back until actually read at 0. – Set TXPKTRDY and read it back until actually read at 1. – Clear TXPKTRDY so that no packet is ready to be sent. – Reset the endpoint to clear the FIFO (pointers). (See Section 33.7.9 ”UDP Reset Endpoint Register”.)

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33.6.3 Controlling Device States

A USB device has several possible states. Refer to Chapter 9 of the Universal Serial Bus Speci- fication, Rev 2.0. Figure 33-14. USB Device State Diagram Movement from one state to another depends on the USB bus state or on standard requests sent through control transactions via the default endpoint (endpoint 0). After a period of bus inactivity, the US B device enters Suspend Mode. Accepting Sus- pend/Resume requests from the USB host is mandatory. Constraints in Suspend Mode are very strict for bus-powered applications; devices may not consume more than 500 μA on the USB bus. While in Suspend Mode, the host may wake up a de vice by sending a resume signal (bus activ- ity) or a USB device may send a wake up request to the host, e.g., waking up a PC by moving a USB mouse. The wake up feature is not mandatory for all devices and must be negotiated with the host. Attached Suspended Suspended Suspended Suspended Hub Reset or Deconfigured Hub Configured Bus Inactive Bus Activity Bus Inactive Bus Activity Bus Inactive Bus Activity Bus Inactive Bus Activity Reset Reset Address Assigned Device Deconfigured Device Configured Powered Default Address Configured Power Interruption

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33.6.3.1 Not Powered State

Self powered devices can detect 5V VBUS using a PIO as described in the typical connection section. When the device is not connected to a host, device power consumption can be reduced by disabling MCK for the UD P, disabling UDPCK and disabl ing the transceiver. DDP and DDM lines are pulled down by 330 KΩ resistors.

33.6.3.2 Entering Attached State

To enable integrated pullup, the PUON bit in the UDP_TXVC register must be set. Warning: To write to the UDP_TXVC register, MCK clock must be enabled on the UDP. This is done in the Power Management Controller. After pullup connection, the device enters the powered state. In this state, the UDPCK and MCK must be enabled in the Power Management Controller. The transceiver can remain disabled.

33.6.3.3 From Powered State to Default State

After its connection to a USB host, the USB device waits for an end-of-bus reset. The unmask- able flag ENDBUSRES is set in the register UDP_ISR and an interrupt is triggered. Once the ENDBUSRES interrupt has been triggered, the device enters Default State. In this state, the UDP software must:

  • Enable the default endpoint, setting the EPEDS flag in the UDP_CSR[0] register and, optionally, enabling the interrupt for endpoint 0 by writing 1 to the UDP_IER register. The enumeration then begins by a control transfer.
  • Configure the interrupt mask register which has been reset by the USB reset detection
  • Enable the transceiver clearing the TXVDIS flag in the UDP_TXVC register. In this state UDPCK and MCK must be enabled. Warning: Each time an ENDBUSRES interrupt is triggered, the Interrupt Mask Register and UDP_CSR registers have been reset.

33.6.3.4 From Default State to Address State

After a set address standard device request, the USB host peripheral enters the address state. Warning: Before the device enters in address state, it must achieve the Status IN transaction of the control transfer, i.e., the UDP device sets its new address once the TXCOMP flag in the UDP_CSR[0] register has been received and cleared. To move to address state, the driver software sets the FADDEN flag in the UDP_GLB_STAT register, sets its new address, and sets the FEN bit in the UDP_FADDR register.

33.6.3.5 From Address State to Configured State

Once a valid Set Configuration standard request has been received and acknowledged, the device enables endpoints corresponding to the current configuration. This is done by setting the EPEDS and EPTYPE fields in the UDP_CSRx registers and, optionally, enabling corresponding interrupts in the UDP_IER register.

33.6.3.6 Entering in Suspend State

When a Suspend (no bus activity on the USB bus) is detected, the RXSUSP signal in the UDP_ISR register is set. This triggers an interrupt if the corresponding bit is set in the UDP_IMR

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 555 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 register.This flag is cleared by writing to the UDP_ICR register. Then the device enters Suspend Mode. In this state bus powered devices must drain less than 500uA from the 5V VBUS. As an exam- ple, the microcontroller switches to slow clock, disables the PL L and main osc illator, and goes into Idle Mode. It may also switch off other devices on the board. The USB device peripheral clocks can be s witched off. Resume event is asynchronously detected. MCK and UDPCK can be switched off in the Power Management controller and the USB transceiver can be disabled by setting the TXVDIS field in the UDP_TXVC register. Warning: Read, write operations to the UDP registers are allowed only if MCK is enabled for the UDP peripheral. Switching off MCK for the UDP peripheral must be one of the last operations after writing to the UDP_TXVC and acknowledging the RXSUSP.

33.6.3.7 Receiving a Host Resume

In suspend mode, a resume event on the USB bus line is detected asynchronously, transceiver and clocks are disabled (however the pullup shall not be removed). Once the resume is detected on the bus, the WAKEUP signal in the UDP_ISR is set. It may gen- erate an interrupt if the corresponding bit in the UDP_IMR register is set. This interrupt may be used to wake up the core, enable PLL and main oscillators and configure clocks. Warning: Read, write operations to the UDP registers are allowed only if MCK is enabled for the UDP peripheral. MCK for the UDP must be enabled before clea ring the WAKEUP bit in the UDP_ICR register and clearing TXVDIS in the UDP_TXVC register.

33.6.3.8 Sending a Device Remote Wakeup

In Suspend state it is possible to wake up the host sending an external resume.

  • The device must wait at least 5 ms after being entered in suspend before sending an external resume.
  • The device has 10 ms from the moment it starts to drain current and it forces a K state to resume the host.
  • The device must force a K state from 1 to 15 ms to resume the host To force a K state to the bus (DDM at 3.3V and DDP tied to GND), it is possible to use a transis- tor to connect a pullup on DDM. The K state is obtained by disabling the pullup on DDP and enabling the pullup on DDM. This should be under the control of the application. Figure 33-15. Board Schematic to Drive a K State 3V3 PIO 1.5 K 0: Force Wake UP (K State) 1: Normal Mode DM

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 556 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

33.7 USB Device Port (UDP) User Interface

WARNING: The UDP peripheral clock in the Power Management Controller (PMC) must be enabled before any read/write operations to the UDP registers, including the UDP_TXVC register. Notes: 1. Reset values are not defined for UDP_ISR. 2. See Warning above the ”Register Mapping” on this page. Table 33-6. Register Mapping Offset Register Name Access Reset 0x000 Frame Number Register UDP_FRM_NUM Read-only 0x0000_0000 0x004 Global State Register UDP_GLB_STAT Read-write 0x0000_0010 0x008 Function Address Register UDP_FADDR Read-write 0x0000_0100 0x00C Reserved – – – 0x010 Interrupt Enable Register UDP_IER Write-only 0x014 Interrupt Disable Register UDP_IDR Write-only 0x018 Interrupt Mask Register UDP_IMR Read-only 0x0000_1200 0x01C Interrupt Status Register UDP_ISR Read-only – (1) 0x020 Interrupt Clear Register UDP_ICR Write-only 0x024 Reserved – – – 0x028 Reset Endpoint Register UDP_RST_EP Read-write 0x0000_0000 0x02C Reserved – – – 0x030 Endpoint Control and Status Register 0 UDP_CSR0 Read-write 0x0000_0000 0x030 + 0x4 * 5 Endpoint Control and Status Register 5 UDP_CSR5 Read-write 0x0000_0000 0x050 Endpoint FIFO Data Register 0 UDP_FDR0 Read-write 0x0000_0000 0x050 + 0x4 * 5 Endpoint FIFO Data Register 5 UDP_FDR5 Read-write 0x0000_0000 0x070 Reserved – – – 0x074 Transceiver Control Register UDP_TXVC(2) Read-write 0x0000_0000 0x078 - 0xFC Reserved – – –

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 557 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

33.7.1 UDP Frame Number Register

Name: UDP_FRM_NUM Address: 0xF803C000 Access: Read-only  FRM_NUM[10:0]: Frame Number as Defined in the Packet Field Formats This 11-bit value is incremented by the host on a per frame basis. This value is updated at each start of frame. Value Updated at the SOF_EOP (Start of Frame End of Packet).  FRM_ERR: Frame Error This bit is set at SOF_EOP when the SOF packet is received containing an error. This bit is reset upon receipt of SOF_PID.  FRM_OK: Frame OK This bit is set at SOF_EOP when the SOF packet is received without any error. This bit is reset upon receipt of SOF_PID (Packet Identification). In the Interrupt Status Register, the SOF interrupt is updated upon receiving SOF_PID. This bit is set without waiting for EOP. Note: In the 8-bit Register Interfac e, FRM_OK is bit 4 of FRM_NUM_H and FRM_ERR is bit 3 of FRM_NUM_L. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 FRM_NUM

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 558 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

33.7.2 UDP Global State Register

Name: UDP_GLB_STAT Address: 0xF803C004 Access: Read-write This register is used to get and set the device state as specified in Chapter 9 of the USB Serial Bus Specification, Rev.2.0.  FADDEN: Function Address Enable Read: 0 = Device is not in address state. 1 = Device is in address state. Write: 0 = No effect, only a reset can bring back a device to the default state. 1 = Sets device in address state. This occurs after a successful Set Address request. Beforehand, the UDP_FADDR regis- ter must have been initialized with Set Address parameters. Set Address must complete the Status Stage before setting FADDEN. Refer to chapter 9 of the Universal Serial Bus Specification, Rev. 2.0 for more details.  CONFG: Configured Read: 0 = Device is not in configured state. 1 = Device is in configured state. Write: 0 = Sets device in a non configured state 1 = Sets device in configured state. The device is set in configured state when it is in address state and receives a successful Set Configuration request. Refer to Chapter 9 of the Universal Serial Bus Specification, Rev. 2.0 for more details. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 – – – RMWUPE RSMINPR ESR CONFG FADDEN

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33.7.3 UDP Function Address Register

Name: UDP_FADDR Address: 0xF803C008 Access: Read-write  FADD[6:0]: Function Address Value The Function Address Value must be programmed by firmware once the device receives a set address request from the host, and has achieved the status stage of the no-data control sequence. Refer to the Universal Serial Bus Specification, Rev. 2.0 for more information. After power up or reset, the function address value is set to 0.  FEN: Function Enable Read: 0 = Function endpoint disabled. 1 = Function endpoint enabled. Write: 0 = Disables function endpoint. 1 = Default value. The Function Enable bit (FEN) allows the microcontroller to enable or disable the function endpoints. The microcontroller sets this bit after receipt of a reset from the host. Once this bit is set, the USB device is able to accept and transfer data packets from and to the host. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 –F ADD

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33.7.4 UDP Interrupt Enable Register

Name: UDP_IER Address: 0xF803C010 Access: Write-only  EP0INT: Enable Endpoint 0 Interrupt  EP1INT: Enable Endpoint 1 Interrupt  EP2INT: Enable Endpoint 2Interrupt  EP3INT: Enable Endpoint 3 Interrupt  EP4INT: Enable Endpoint 4 Interrupt  EP5INT: Enable Endpoint 5 Interrupt 0 = No effect. 1 = Enables corresponding Endpoint Interrupt.  RXSUSP: Enable UDP Suspend Interrupt 0 = No effect. 1 = Enables UDP Suspend Interrupt.  RXRSM: Enable UDP Resume Interrupt 0 = No effect. 1 = Enables UDP Resume Interrupt.  SOFINT: Enable Start Of Frame Interrupt 0 = No effect. 1 = Enables Start Of Frame Interrupt.  WAKEUP: Enable UDP bus Wakeup Interrupt 0 = No effect. 1 = Enables USB bus Interrupt. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 – – WAKEUP – SOFINT EXTRSM RXRSM RXSUSP 76543210 EP5INT EP4INT EP3INT EP2INT EP1INT EP0INT

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 561 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

33.7.5 UDP Interrupt Disable Register

Name: UDP_IDR Address: 0xF803C014 Access: Write-only  EP0INT: Disable Endpoint 0 Interrupt  EP1INT: Disable Endpoint 1 Interrupt  EP2INT: Disable Endpoint 2 Interrupt  EP3INT: Disable Endpoint 3 Interrupt  EP4INT: Disable Endpoint 4 Interrupt  EP5INT: Disable Endpoint 5 Interrupt 0 = No effect. 1 = Disables corresponding Endpoint Interrupt.  RXSUSP: Disable UDP Suspend Interrupt 0 = No effect. 1 = Disables UDP Suspend Interrupt.  RXRSM: Disable UDP Resume Interrupt 0 = No effect. 1 = Disables UDP Resume Interrupt.  SOFINT: Disable Start Of Frame Interrupt 0 = No effect. 1 = Disables Start Of Frame Interrupt  WAKEUP: Disable USB Bus Interrupt 0 = No effect. 1 = Disables USB Bus Wakeup Interrupt. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 – – WAKEUP – SOFINT EXTRSM RXRSM RXSUSP 76543210 EP5INT EP4INT EP3INT EP2INT EP1INT EP0INT

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33.7.6 UDP Interrupt Mask Register

Name: UDP_IMR Address: 0xF803C018 Access: Read-only  EP0INT: Mask Endpoint 0 Interrupt  EP1INT: Mask Endpoint 1 Interrupt  EP2INT: Mask Endpoint 2 Interrupt  EP3INT: Mask Endpoint 3 Interrupt  EP4INT: Mask Endpoint 4 Interrupt  EP5INT: Mask Endpoint 5 Interrupt 0 = Corresponding Endpoint Interrupt is disabled. 1 = Corresponding Endpoint Interrupt is enabled.  RXSUSP: Mask UDP Suspend Interrupt 0 = UDP Suspend Interrupt is disabled. 1 = UDP Suspend Interrupt is enabled.  RXRSM: Mask UDP Resume Interrupt. 0 = UDP Resume Interrupt is disabled. 1 = UDP Resume Interrupt is enabled.  SOFINT: Mask Start Of Frame Interrupt 0 = Start of Frame Interrupt is disabled. 1 = Start of Frame Interrupt is enabled.  BIT12: UDP_IMR Bit 12 Bit 12 of UDP_IMR cannot be masked and is always read at 1. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 – – WAKEUP BIT12 SOFINT EXTRSM RXRSM RXSUSP 76543210 EP5INT EP4INT EP3INT EP2INT EP1INT EP0INT

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 563 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12  WAKEUP: USB Bus WAKEUP Interrupt 0 = USB Bus Wakeup Interrupt is disabled. 1 = USB Bus Wakeup Interrupt is enabled. Note: When the USB block is in suspend mode, the application may power down the USB logic. In this case, any USB HOST resume request that is made must be taken into account and, thus, the reset value of the RXRSM bit of the register UDP_IMR is enabled.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 564 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

33.7.7 UDP Interrupt Status Register

Name: UDP_ISR Address: 0xF803C01C Access: Read-only  EP0INT: Endpoint 0 Interrupt Status  EP1INT: Endpoint 1 Interrupt Status  EP2INT: Endpoint 2 Interrupt Status  EP3INT: Endpoint 3 Interrupt Status  EP4INT: Endpoint 4 Interrupt Status  EP5INT: Endpoint 5 Interrupt Status 0 = No Endpoint0 Interrupt pending. 1 = Endpoint0 Interrupt has been raised. Several signals can generate this interrupt. The reason can be found by reading UDP_CSR0: RXSETUP set to 1 RX_DATA_BK0 set to 1 RX_DATA_BK1 set to 1 TXCOMP set to 1 STALLSENT set to 1 EP0INT is a sticky bit. Interrupt remains valid until EP0INT is cleared by writing in the corresponding UDP_CSR0 bit.  RXSUSP: UDP Suspend Interrupt Status 0 = No UDP Suspend Interrupt pending. 1 = UDP Suspend Interrupt has been raised. The USB device sets this bit when it detects no activity for 3ms. The USB device enters Suspend mode. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 – – WAKEUP ENDBUSRES SOFINT EXTRSM RXRSM RXSUSP 76543210 EP5INT EP4INT EP3INT EP2INT EP1INT EP0INT

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 565 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12  RXRSM: UDP Resume Interrupt Status 0 = No UDP Resume Interrupt pending. 1 =UDP Resume Interrupt has been raised. The USB device sets this bit when a UDP resume signal is detected at its port. After reset, the state of this bit is undefined, the application must clear this bit by setting the RXRSM flag in the UDP_ICR register.  SOFINT: Start of Frame Interrupt Status 0 = No Start of Frame Interrupt pending. 1 = Start of Frame Interrupt has been raised. This interrupt is raised each time a SOF token has been detected. It can be used as a synchronization signal by using isochronous endpoints.  ENDBUSRES: End of BUS Reset Interrupt Status 0 = No End of Bus Reset Interrupt pending. 1 = End of Bus Reset Interrupt has been raised. This interrupt is raised at the end of a UDP reset sequence. The USB device must prepare to receive requests on the end- point 0. The host starts the enumeration, then performs the configuration.  WAKEUP: UDP Resume Interrupt Status 0 = No Wakeup Interrupt pending. 1 = A Wakeup Interrupt (USB Host Sent a RESUME or RESET) occurred since the last clear. After reset the state of this bit is undefined, the application must clear this bit by setting the WAKEUP flag in the UDP_ICR register.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 566 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

33.7.8 UDP Interrupt Clear Register

Name: UDP_ICR Address: 0xF803C020 Access: Write-only  RXSUSP: Clear UDP Suspend Interrupt 0 = No effect. 1 = Clears UDP Suspend Interrupt.  RXRSM: Clear UDP Resume Interrupt 0 = No effect. 1 = Clears UDP Resume Interrupt.  SOFINT: Clear Start Of Frame Interrupt 0 = No effect. 1 = Clears Start Of Frame Interrupt.  ENDBUSRES: Clear End of Bus Reset Interrupt 0 = No effect. 1 = Clears End of Bus Reset Interrupt.  WAKEUP: Clear Wakeup Interrupt 0 = No effect. 1 = Clears Wakeup Interrupt. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 – – WAKEUP ENDBUSRES SOFINT EXTRSM RXRSM RXSUSP 76543210

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33.7.9 UDP Reset En dpoint Register

Name: UDP_RST_EP Address: 0xF803C028 Access: Read-write  EP0: Reset Endpoint 0  EP1: Reset Endpoint 1  EP2: Reset Endpoint 2  EP3: Reset Endpoint 3  EP4: Reset Endpoint 4  EP5: Reset Endpoint 5 This flag is used to reset the FIFO associated with the endpoint and the bit RXBYTECOUNT in the register UDP_CSRx.It also resets the data toggle to DATA0. It is useful after removing a HALT c ondition on a BULK endpoint. Refer to Chapter Warning: This flag must be cleared at the end of the reset. It does not clear UDP_CSRx flags. 0 = No reset. 1 = Forces the corresponding endpoint FIF0 pointers to 0, therefore RXBYTECNT field is read at 0 in UDP_CSRx register. Resetting the endpoint is a two-step operation: 1. Set the corresponding EPx field. 2. Clear the corresponding EPx field. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 EP5 EP4 EP3 EP2 EP1 EP0

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 568 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

33.7.10 UDP Endpoint Control and Status Register

Name: UDP_CSRx [x = 0..5] Address: 0xF803C030 Access: Read-write WARNING: Due to synchronization between MCK and UDPCK, the soft ware application must wait for the end of the write operation before executing another write by polling the bits which must be set/cleared. #if defined ( __ICCARM__ ) #define nop() (__no_operation()) #elif defined ( __GNUC__ ) #endif /// Bitmap for all status bits in CSR that are not effected by a value 1. #define REG_NO_EFFECT_1_ALL AT91C_UDP_RX_DATA_BK0\\ | AT91C_UDP_STALLSENT\\ | AT91C_UDP_RXSETUP\\ | AT91C_UDP_TXCOMP /// Sets the specified bit(s) in the UDP_CSR register. /// \\param endpoint The endpoint number of the CSR to process. /// \\param flags The bitmap to set to 1. #define SET_CSR(endpoint, flags) \\ { \\ volatile unsigned int reg; \\ reg = AT91C_BASE_UDP->UDP_CSR[endpoint] ; \\ reg |= REG_NO_EFFECT_1_ALL; \\ reg |= (flags); \\ AT91C_BASE_UDP->UDP_CSR[endpoint] = reg; \\ for( nop_count=0; nop_count<15; nop_count++ ) {\\ nop();\\ 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RXBYTECNT 15 14 13 12 11 10 9 8 EPEDS – – – DTGLE EPTYPE 76543210 DIR RX_DATA_BK1 FORCESTALL TXPKTRDY STALLSENT/ ISOERROR RXSETUP RX_DATA_ BK0 TXCOMP

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 569 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 /// Clears the specified bit(s) in the UDP_CSR register. /// \\param endpoint The endpoint number of the CSR to process. /// \\param flags The bitmap to clear to 0. #define CLEAR_CSR(endpoint, flags) \\ { \\ volatile unsigned int reg; \\ reg = AT91C_BASE_UDP->UDP_CSR[endpoint]; \\ reg |= REG_NO_EFFECT_1_ALL; \\ reg &= ~(flags); \\ AT91C_BASE_UDP->UDP_CSR[endpoint] = reg; \\ for( nop_count=0; nop_count<15; nop_count++ ) {\\ nop();\\ In a preemptive environment, set or clear the flag and wait for a time of 1 UDPCK clock cycle and 1peripheral clock cycle. However, RX_DATA_BK0, TXPKTRDY, RX_DATA_BK1 require wait times of 3 UDPCK clock cycles and 5 peripheral clock cycles before accessing DPR.  TXCOMP: Generates an IN Packet with Data Previously Written in the DPR This flag generates an interrupt while it is set to one. Write (Cleared by the firmware): 0 = Clear the flag, clear the interrupt. 1 = No effect. Read (Set by the USB peripheral): 0 = Data IN transaction has not been acknowledged by the Host. 1 = Data IN transaction is achieved, acknowledged by the Host. After having issued a Data IN transaction setting TXPKTRDY, the device firmware waits for TXCOMP to be sure that the host has acknowledged the transaction.  RX_DATA_BK0: Receive Data Bank 0 This flag generates an interrupt while it is set to one. Write (Cleared by the firmware): 0 = Notify USB peripheral device that data have been read in the FIFO's Bank 0. 1 = To leave the read value unchanged. Read (Set by the USB peripheral): 0 = No data packet has been received in the FIFO's Bank 0. 1 = A data packet has been received, it has been stored in the FIFO's Bank 0. When the device firmware has polled this bit or has been interrupted by this signal, it must transfer data from the FIFO to the microcontroller memory. The number of bytes received is available in RXBYTCENT field. Bank 0 FIFO values are read

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 570 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 through the UDP_FDRx register. Once a transfer is done, the device firmware must release Bank 0 to the USB peripheral device by clearing RX_DATA_BK0. After setting or clearing this bit, a wait time of 3 UDPCK clock cycles and 3 peripheral cl ock cycles is required before accessing DPR.  RXSETUP: Received Setup This flag generates an interrupt while it is set to one. Read: 0 = No setup packet available. 1 = A setup data packet has been sent by the host and is available in the FIFO. Write: 0 = Device firmware notifies the USB peripheral device that it has read the setup data in the FIFO. 1 = No effect. This flag is used to notify the USB device firmware that a valid Setup data packet has been sent by the host and success- fully received by the USB device. The USB device firmware may transfer Setup data from the FIFO by reading the UDP_FDRx register to the microcontroller memory. Once a transfer has been done, RXSETUP must be cleared by the device firmware. Ensuing Data OUT transaction is not accepted while RXSETUP is set.  STALLSENT: Stall Sent (Control, Bulk Interrupt Endpoints)/ISOERROR (Isochronous Endpoints) This flag generates an interrupt while it is set to one. STALLSENT: This ends a STALL handshake. Read: 0 = The host has not acknowledged a STALL. 1 = Host has acknowledged the stall. Write: 0 = Resets the STALLSENT flag, clears the interrupt. 1 = No effect. This is mandatory for the device firmware to clear this flag. Otherwise the interrupt remains. handshake. ISOERROR: A CRC error has been detected in an isochronous transfer. Read: 0 = No error in the previous isochronous transfer. 1 = CRC error has been detected, data available in the FIFO are corrupted. Write: 0 = Resets the ISOERROR flag, clears the interrupt. 1 = No effect.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 571 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12  TXPKTRDY: Transmit Packet Ready This flag is cleared by the USB device. This flag is set by the USB device firmware. Read: 0 = There is no data to send. 1 = The data is waiting to be sent upon reception of token IN. Write: 0 = Can be used in the procedure to cancel transmission data. (See, Section 33.6.2.5 “Transmit Data Cancellation” on page 552) 1 = A new data payload has been written in the FIFO by the firmware and is ready to be sent. This flag is used to generate a Data IN transaction (device to host). Device firmware checks that it can write a data payload in the FIFO, checking that TXPKTRDY is cleared. Transfer to the FIFO is done by writing in the UDP_FDRx register. Once the data payload has been transferred to the FIFO, the firmwar e notifies the USB device setting TXPKTRDY to one. USB bus transactions can start. TXCOMP is set once the data payload has been received by the host. After setting or clearing this bit, a wait time of 3 UDPCK clock cycles and 3 peripheral cl ock cycles is required before accessing DPR.  FORCESTALL: Force Stall (used by Control, Bulk and Isochronous Endpoints) Read: 0 = Normal state. 1 = Stall state. Write: 0 = Return to normal state. 1 = Send STALL to the host. handshake. Control endpoints: During the data stage and status stage, this bit indicates that the microcontroller cannot complete the request. Bulk and interrupt endpoints: This bit notifies the host that the endpoint is halted. The host acknowledges the STALL, device firmware is notified by the STALLSENT flag.  RX_DATA_BK1: Receive Data Bank 1 (only used by endpoints with ping-pong attributes) This flag generates an interrupt while it is set to one. Write (Cleared by the firmware): 0 = Notifies USB device that data have been read in the FIFO’s Bank 1. 1 = To leave the read value unchanged.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 572 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Read (Set by the USB peripheral): 0 = No data packet has been received in the FIFO's Bank 1. 1 = A data packet has been received, it has been stored in FIFO's Bank 1. When the device firmware has polled this bit or has been interrupted by this signal, it must transfer data from the FIFO to microcontroller memory. The number of bytes received is available in RXBYTECNT field. Bank 1 FIFO values are read through UDP_FDRx register. Once a transfer is done, the device firmware must release Bank 1 to the USB device by clear- ing RX_DATA_BK1. After setting or clearing this bit, a wait time of 3 UDPCK clock cycles and 3 peripheral cl ock cycles is required before accessing DPR.  DIR: Transfer Direction (only available for control endpoints) Read-write 0 = Allows Data OUT transactions in the control data stage. 1 = Enables Data IN transactions in the control data stage. This bit must be set before UDP_CSRx/RXSETUP is cleared at the end of the setup stage. According to the request sent in the setup data packet, the data stage is either a device to host (DIR = 1) or host to device (DIR = 0) data transfer. It is not necessary to check this bit to reverse direction for the status stage.  EPTYPE[2:0]: Endpoint Type Read-Write  DTGLE: Data Toggle Read-only 0 = Identifies DATA0 packet. 1 = Identifies DATA1 packet. Refer to Chapter 8 of the Universal Serial Bus Specification, Rev. 2.0 for more information on DATA0, DATA1 packet definitions. Value Name Description

000 CTRL Control

001 ISO_OUT Isochronous OUT

101 ISO_IN Isochronous IN

010 BULK_OUT Bulk OUT

110 BULK_IN Bulk IN

011 INT_OUT Interrupt OUT

111 INT_IN Interrupt IN

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 573 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12  EPEDS: Endpoint Enable Disable Read: 0 = Endpoint disabled. 1 = Endpoint enabled. Write: 0 = Disables endpoint. 1 = Enables endpoint. Control endpoints are always enabled. Reading or writing this field has no effect on control endpoints. Note: After reset, all endpoints are configured as control endpoints (zero).  RXBYTECNT[10:0]: Number of Bytes Available in the FIFO Read-only When the host sends a data packet to the device, the USB device stores the data in the FIFO and notifies the microcon- troller. The microcontroller can load the data from the FIFO by reading RXBYTECENT bytes in the UDP_FDRx register.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 574 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

33.7.11 UDP FIFO Data Register

Name: UDP_FDRx [x = 0..5] Address: 0xF803C050 Access: Read-write  FIFO_DATA[7:0]: FIFO Data Value The microcontroller can push or pop values in the FIFO through this register. RXBYTECNT in the corresponding UDP_CSRx register is the number of bytes to be read from the FIFO (sent by the host). The maximum number of bytes to write is fixed by the Max Packet Size in the Standard Endpoint Descriptor. It can not be more than the physical memory size associated to the endpoint. Refer to the Universal Serial Bus Specification, Rev. 2.0 for more information. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 FIFO_DATA

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 575 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

33.7.12 UDP Transceiver Control Register

Name: UDP_TXVC Address: 0xF803C074 Access: Read-write WARNING: The UDP peripheral clock in the Power Management Controller (PMC) must be enabled before any read/write operations to the UDP registers including the UDP_TXVC register.  TXVDIS: Transceiver Disable When UDP is disabled, power consumption can be reduced significantly by disab ling the embedded transceiver. This can be done by setting TXVDIS field. To enable the transceiver, TXVDIS must be cleared.  PUON: Pullup On 0: The 1.5KΩ integrated pullup on DDP is disconnected. 1: The 1.5 KΩ integrated pullup on DDP is connected. NOTE: If the USB pullup is not connected on DDP, the user should not write in any UDP register other than the UDP_TXVC register. This is because if DDP and DDM are floating at 0, or pulled down, then SE0 is received by the device with the con- sequence of a USB Reset. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 576 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 577 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 34. USB Host Port (UHP)

34.1 Description

The USB Host Port (UHP) interfaces the USB with the host application. It handles Open HCI protocol (Open Host Controller Interface) as well as USB v2.0 Full-speed and Low-speed protocols. The USB Host Port integrates a root hub and transceivers on downstream ports. It provides sev- eral high-speed half-duplex serial communication ports at a baud rate of 12 Mbit/s. Up to 127 USB devices (printer, camera, mouse, keyboard, disk, etc.) and the USB hub can be connected to the USB host in the USB “tiered star” topology. The USB Host Port controller is fully complia nt with the OpenHCI spec ification. The USB Host Port User Interface (registers description) can be found in the Open HCI Rev 1.0 Specification OHCI USB stack driver can be easily ported to AT MEL’s architecture in the same way all exist- ing class drivers run without hardware specialization. This means that all standard class devices are automatically detected and available to the user application. As an example, integrating an HID (Human Interface Device) class driver provides a plug & play feature for all USB keyboards and mouses.

34.2 Embedded Characteristics

  • Compliant with OpenHCI Rev 1.0 Specification
  • Compliant with USB V2.0 Full-speed and Low-speed Specification
  • Supports Both Low-speed 1.5 Mbps and Full-speed 12 Mbps USB devices
  • Root Hub Integrated with 1 Downstream USB Ports
  • Embedded USB Transceivers
  • Supports Power Management

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 578 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

34.3 Block Diagram

Figure 34-1. Block Diagram Access to the USB host operational registers is achieved through the AHB bus slave interface. The OpenHCI host controller initializes master DMA transfers through the ASB bus master inter- face as follows:

  • Fetches endpoint descriptors and transfer descriptors
  • Access to endpoint data from system memory
  • Access to the HC communication area
  • Write status and retire transfer Descriptor Memory access errors (abort, misalignment) lead to an “UnrecoverableError” indicated by the corresponding flag in the host controller operational registers. The USB root hub is integrated in the USB host. Several USB downstream ports are available. The number of downstream ports can be determined by the software driver reading the root hub’s operational registers. Device connection is automatically detected by the USB host port logic. USB physical transceivers are integrated in the product and driven by the root hub’s ports. Over current protection on ports can be activated by the USB host controller. Atmel’s standard product does not dedicate pads to external over current protection. PORT S/M PORT S/M USB transceiver USB transceiver DP DM DP DM Embedded USB v2.0 Full-speed Transceiver Root Hub and Host SIE List Processor Block FIFO 64 x 8 HCI Slave Block OHCI Registers OHCI Root Hub RegistersAHB ED & TD Regsisters Control HCI Master Block Data uhp_int MCK UHPCK AHB Slave Master

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 579 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

34.4 Product Dependencies

34.4.1 I/O Lines

DPs and DMs are not controlled by any PIO controllers. The embedded USB physical transceiv- ers are controlled by the USB host controller.

34.4.2 Power Management

The USB host controller requires a 48 MHz clock. This clock must be generated by a PLL with a correct accuracy of ± 0.25%. Thus the USB device peripheral receives two clocks from the Power Management Controller (PMC): the master clock MCK used to drive the peripheral user interface (MCK domain) and the UHPCLK 48 MHz clock used to interface with the bus USB signals (Recovered 12 MHz domain).

34.4.3 Interrupt

The USB host interface has an interrupt line connected to the Advanced Interrupt Controller (AIC). Handling USB host interrupts requires programming the AIC before configuring the UHP.

34.5 Functional Description

Please refer to the Open Host Controller Interface Specification for USB Release 1.0.a.

34.5.1 Host Controller Interface

There are two communication channels between the Host Controller and the Host Controller Driver. The first channel uses a set of operational registers located on the USB Host Controller. The Host Controller is the target for all co mmunications on this channel. The operational regis- ters contain control, status and list pointer registers. They are mapped in the memory mapped area. Within the operational register set there is a pointer to a location in the processor address space named the Host Controller Communication Area (HCCA). The HCCA is the second com- munication channel. The host controller is the master for all communication on this channel. The HCCA contains the head pointers to the interrupt Endpoint Descrip tor lists, the head pointer to the done queue and status information associated with start-of-frame processing. The basic building blocks for communication across the interface are Endpoint Descriptors (ED, 4 double words) and Transfer Descriptors (TD, 4 or 8 double words). The host controller assigns an Endpoint Descriptor to each endpoint in the system. A queue of Transfer Descriptors is linked to the Endpoint Descriptor for the specific endpoint.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 580 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Figure 34-2. USB Host Communication Channels Operational Registers Mode HCCA Status Event Frame Int Ratio Control Bulk Host Controller Communications Area Interrupt 0 Interrupt 1 Interrupt 2 Interrupt 31 Done . . . . . . Open HCI Shared RAM Device Register in Memory Space Device Enumeration = Transfer Descriptor = Endpoint Descriptor . . .

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 581 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

34.5.2 Host Controller Driver

Figure 34-3. USB Host Drivers USB Handling is done through several layers as follows:

  • Host controller hardware and serial engine: Transmits and receives USB data on the bus.
  • Host controller driver: Drives the Host controller hardware and handles the USB protocol.
  • USB Bus driver and hub driver: Handles USB commands and enumeration. Offers a hardware independent interface.
  • Mini driver: Handles device specific commands.
  • Class driver: Handles standard devices. This acts as a generic driver for a class of devices, for example the HID driver. Host Controller Hardware HUB Driver Host Controller Driver USB Driver Mini Driver Class Driver Class Driver User Application Kernel Drivers User Space Hardware

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 582 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

34.6 Typical Connection

Figure 34-4. Board Schematic to Interface UHP Device Controller A termination serial resistor must be connected to HDP and HDM. The resistor value is defined in the electrical specification of the product (REXT). REXTHDMA or HDMB HDPA or HDPB 10nF100nF10μF 5V 0.20A Type A Connector REXT

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 583 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 35. High Speed MultiMedia Card Interface (HSMCI)

35.1 Description

The High Speed Multimedia Card Interface (HSMCI) supports the MultiMedia Card (MMC) Specification V4.3, the SD Memo ry Card Specification V2.0, th e SDIO V2.0 specification and CE-ATA V1.1. The HSMCI includes a command register, response registers, data registers, timeout counters and error detection logic that automatically handle the transmission of commands and, when required, the reception of the associated responses and data with a limited processor overhead. The HSMCI supports stream, block and multi block data read and write, and is compatible with the DMA Controller (DMAC), minimizing processor intervention for large buffer transfers. The HSMCI operates at a rate of up to Master Clock divided by 2 and supports the interfacing of 1 slot(s). Each slot may be used to interface with a High Speed MultiMediaCard bus (up to 30 Cards) or with an SD Memory Card. Only one slot can be selected at a time (slots are multi- plexed). A bit field in the SD Card Register performs this selection. The SD Memory Card communication is based on a 9-pin interface (clock, command, four data and three power lines) and the High Speed MultiMedia Card on a 7-pin interface (clock, com- mand, one data, three power lines and one reserved for future use). The SD Memory Card interface also supports High Speed MultiMedia Card operations. The main differences between SD and High Speed MultiMedia Cards are the initialization process and the bus topology. HSMCI fully supports CE-ATA Revision 1.1, bui lt on the MMC System Specification v4.0. The module includes dedicated hardware to issue the command completion signal and capture the host command completion signal disable.

35.2 Embedded Characteristics

  • Compatible with MultiMedia Card Specification Version 4.3
  • Compatible with SD Memory Card Specification Version 2.0
  • Compatible with SDIO Specification Version 2.0
  • Compatible with CE-ATA Specification 1.1
  • Cards Clock Rate Up to Master Clock Divided by 2
  • Boot Operation Mode Support
  • High Speed Mode Support
  • Embedded Power Management to Slow Down Clock Rate When Not Used
  • Supports 1 Multiplexed Slot(s) – Each Slot for either a High Speed MultiMediaCard Bus (Up to 30 Cards) or an SD Memory Card
  • Support for Stream, Block and Multi-block Data Read and Write
  • Supports Connection to DMA Controller (DMAC) – Minimizes Processor Intervention for Large Buffer Transfers
  • Built in FIFO (from 16 to 256 bytes) with Large Memory Aperture Supporting Incremental Access
  • Support for CE-ATA Completion Signal Disable Command
  • Protection Against Unexpected Modification On-the-Fly of the Configuration Registers

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 584 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

35.3 Block Diagram

Figure 35-1. Block Diagram

35.4 Application Block Diagram

Figure 35-2. Application Block Diagram HSMCI Interface Interrupt Control PIO DMAC APB Bridge PMC MCK HSMCI Interrupt MCCK(1) MCCDA(1) MCDA0(1) MCDA1(1) MCDA2(1) MCDA3(1) APB 2345617 MMC 2345617 8 SDCard Physical Layer HSMCI Interface Application Layer ex: File System, Audio, Security, etc. 9 1011 1213 8

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 585 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

35.5 Pin Name List

Notes: 1. I: Input, O: Output, PP: Push/Pull, OD: Open Drain. 2. When several HSMCI (x HSMCI) are embedded in a produc t, MCCK refers to HSMCIx_CK, MCCDA to HSMCIx_CDA, MCDAy to HSMCIx_DAy.

35.6 Product Dependencies

35.6.1 I/O Lines

The pins used for interfacing the High Speed MultiMedia Cards or SD Cards are multiplexed with PIO lines. The programmer must first program the PIO controllers to assign the peripheral func- tions to HSMCI pins.

35.6.2 Power Management

The HSMCI is clocked through the Power Management Controller (PMC), so the programmer must first configure the PMC to enable the HSMCI clock.

35.6.3 Interrupt

The HSMCI interface has an interrupt line connected to the Advanced Interrupt Controller (AIC). Handling the HSMCI interrupt requires programming the AIC before configuring the HSMCI.

35.7 Bus Topology

Figure 35-3. High Speed MultiMedia Memory Card Bus Topology Table 35-1. I/O Lines Description for 4-bit Configuration Pin Name(2) Pin Description Type(1) Comments MCCDA Command/response I/O/PP/OD CM D of an MMC or SDCard/SDIO MCCK Clock I/O CLK of an MMC or SD Card/SDIO MCDA0 - MCDA3 Data 0..3 of Slot A I/O/PP DAT[0..3] of an MMC DAT[0..3] of an SD Card/SDIO Table 35-2. Peripheral IDs Instance ID HSMCI 12 2345617 MMC 91 0 1 1 1 2 1 38

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 586 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 The High Speed MultiMedia Card communication is based on a 13-pin serial bus interface. It has three communication lines and four supply lines. Notes: 1. I: Input, O: Output, PP : Push/Pull, OD: Open Drain. 2. When several HSMCI (x HSMCI) are embedded in a product, MCCK refers to HSMCIx_CK, MCCDA to HSMCIx_CDA, MCDAy to HSMCIx_DAy. Figure 35-4. MMC Bus Connections (One Slot) Note: When several HSMCI (x HSMCI) are embedded in a product, MCCK refers to HSMCIx_CK, MCCDA to HSMCIx_CDA MCDAy to HSMCIx_DAy. Table 35-3. Bus Topology Pin Number Name Type (1) Description HSMCI Pin Name (2) (Slot z)

1 DAT[3] I/O/PP Data MCDz3

2 CMD I/O/PP/OD Command/response MCCDz

3 VSS1 S Supply voltage ground VSS

4 VDD S Supply voltage VDD

5 CLK I/O Clock MCCK

6 VSS2 S Supply voltage ground VSS

7 DAT[0] I/O/PP Data 0 MCDz0

8 DAT[1] I/O/PP Data 1 MCDz1

9 DAT[2] I/O/PP Data 2 MCDz2

10 DAT[4] I/O/PP Data 4 MCDz4

11 DAT[5] I/O/PP Data 5 MCDz5

12 DAT[6] I/O/PP Data 6 MCDz6

13 DAT[7] I/O/PP Data 7 MCDz7

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 587 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Figure 35-5. SD Memory Card Bus Topology The SD Memory Card bus includes the signals listed in Table 35-4. Notes: 1. I: input, O: output, PP: Push Pull, OD: Open Drain. 2. When several HSMCI (x HSMCI) are embedded in a product, MCCK refers to HSMCIx_CK, MCCDA to HSMCIx_CDA, MCDAy to HSMCIx_DAy. Figure 35-6. SD Card Bus Connections with One Slot Note: When several HSMCI (x HSMCI) are embedded in a product, MCCK refers to HSMCIx_CK, MCCDA to HSMCIx_CDA MCDAy to HSMCIx_DAy. When the HSMCI is configured to operate with SD memory cards, the width of the data bus can be selected in the HSMCI_SDCR register. Cleari ng the SDCBUS bit in this register means that the width is one bit; setting it means that the width is four bits. In the case of High Speed Multi- Media cards, only the data line 0 is used. The other data lines can be used as independent PIOs. Table 35-4. SD Memory Card Bus Signals Pin Number Name Type (1) Description HSMCI Pin Name(2) (Slot z)

1 CD/DAT[3] I/O/PP Card detect/ Data line Bit 3 MCDz3

2 CMD PP Command/response MCCDz

7 DAT[0] I/O/PP Data line Bit 0 MCDz0

8 DAT[1] I/O/PP Data line Bit 1 or Interrupt MCDz1

9 DAT[2] I/O/PP Data line Bit 2 MCDz2

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 588 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

35.8 High Speed MultiMediaCard Operations

After a power-on reset, the cards are initialized by a special message-based High Speed Multi- MediaCard bus protocol. Each message is represented by one of the following tokens:

  • Command: A command is a token that starts an operation. A command is sent from the host either to a single card (addressed command) or to all connected cards (broadcast command). A command is transferred serially on the CMD line.
  • Response: A response is a token which is sent from an addressed card or (synchronously) from all connected cards to the host as an answer to a previously received command. A response is transferred serially on the CMD line.
  • Data: Data can be transferred from the card to the host or vice versa. Data is transferred via the data line. Card addressing is implemented using a sess ion address assigned during the initialization phase by the bus controller to all currently connected cards. Their unique CID number identifies individual cards. The structure of commands, responses and data blocks is described in the High Speed MultiMe- dia-Card System Specification. See also Table 35-5 on page 589. High Speed MultiMediaCard bus data transfers are composed of these tokens. There are different types of operations. Addressed operations always contain a command and a response token. In addition, some operations have a data token; the others transfer their infor- mation directly within the command or response structure. In this case, no data token is present in an operation. The bits on the DAT and the CMD lines are transferred synchronous to the clock HSMCI Clock. Two types of data transfer commands are defined:
  • Sequential commands: These commands initiate a continuous data stream. They are terminated only when a stop command follows on the CMD line. This mode reduces the command overhead to an absolute minimum.
  • Block-oriented commands: These commands send a data block succeeded by CRC bits. Both read and write operations allow either single or multiple block transmission. A multiple block transmission is terminated when a stop co mmand follows on the CMD line similarly to the sequential read or when a multiple block transmission has a pre-defined block count (See “Data Transfer Operation” on page 591.). The HSMCI provides a set of registers to perform the entire range of High Speed MultiMedia Card operations.

35.8.1 Command - Response Operation

After reset, the HSMCI is disabled and becomes valid after setting the MCIEN bit in the HSMCI_CR Control Register. The PWSEN bit saves power by dividing the HSMCI clock by 2 PWSDIV + 1 when the bus is inactive. The two bits, RDPROOF and WRPROOF in the HSMCI Mode Register (HSMCI_MR) allow stopping the HSMCI Clock during read or write access if the internal FIFO is full. This will guar- antee data integrity, not bandwidth. All the timings for High Speed MultiMedia Card are defined in the High Speed MultiMediaCard System Specification.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 589 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 The two bus modes (open drain and push/pull) needed to process all the operations are defined in the HSMCI command register. The HSMCI_CMDR allows a command to be carried out. For example, to perform an ALL_SEND_CID command: The command ALL_SEND_CID and the fields and values for the HSMCI_CMDR Control Regis- ter are described in Table 35-5 and Table 35-6. Note: bcr means broadcast command with response. The HSMCI_ARGR contains the argument field of the command. To send a command, the user must perform the following steps:

  • Fill the argument register (HSMCI _ARGR) with the command argument.
  • Set the command register (HSMCI_CMDR) (see Table 35-6). The command is sent immediately after writing the command register. While the card maintains a busy indication (at the end of a STOP_TRANSMISSION command CMD12, for example), a new command shall not be sent. The NOTBUSY flag in the status regis- ter (HSMCI_SR) is asserted when the card releases the busy indication. If the command requires a response, it can be read in the HSMCI response register (HSMCI_RSPR). The response size can be from 48 bits up to 136 bits depending on the com- mand. The HSMCI embeds an error detection to prevent any corrupted data during the transfer. Host Command NID Cycles CID CMD S T Content CRC E Z ****** Z S T Content Z Z Z Table 35-5. ALL_SEND_CID Command Description CMD Index Type Argument Resp Abbreviation Command

Description

CMD2 bcr [31:0] stuff bits R2 ALL_SEND_CID Asks all cards to send their CID numbers on the CMD line Table 35-6. Fields and Values for HSMCI_CMDR Command Register Field Value CMDNB (command number) 2 (CMD2) RSPTYP (response type) 2 (R2: 136 bits response) SPCMD (special command) 0 (not a special command) OPCMD (open drain command) 1 MAXLAT (max latency for command to response) 0 (NID cycles ==> 5 cycles) TRCMD (transfer command) 0 (No transfer) TRDIR (transfer direction) X (available only in transfer command) TRTYP (transfer type) X (available only in transfer command) IOSPCMD (SDIO special command) 0 (not a special command)

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 590 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 The following flowchart shows how to send a command to the card and read the response if needed. In this example, the status register bits are polled but setting the appropriate bits in the interrupt enable register (HSMCI_IER) allows using an interrupt method. Figure 35-7. Command/Response Functional Flow Diagram RETURN OK RETURN ERROR(1) RETURN OK Set the command argument HSMCI_ARGR = Argument(1) Set the command HSMCI_CMDR = Command Read HSMCI_SR CMDRDY Status error flags? Read response if required Yes Wait for command ready status flag Check error bits in the status register (1) Does the command involve a busy indication? No Read HSMCI_SR NOTBUSY

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 591 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Note: 1. If the command is SEND_OP_COND, the CRC error flag is always present (refer to R3 res ponse in the High Speed MultiMe- dia Card specification).

35.8.2 Data Transfer Operation

The High Speed MultiMedia Card allows several r ead/write operations (single block, multiple blocks, stream, etc.). These kinds of transfer can be selected setting the Transfer Type (TRTYP) field in the HSMCI Command Register (HSMCI_CMDR). These operations can be done using the features of the DMA Controller. In all cases, the block length (BLKLEN field) must be defined either in the mode register HSMCI_MR, or in the Block Register HSMCI_BLKR. This field determines the size of the data block. Consequent to MMC Specification 3.1, two types of multiple block read (or write) transactions are defined (the host can use either one at any time):

  • Open-ended/Infinite Multiple block read (or write): The number of blocks for the read (or write) multiple block operation is not defined. The card will continuously transfer (o r program) data blocks until a stop transmission command is received.
  • Multiple block read (or write) with pre-defined block count (since version 3.1 and higher): The card will transfer (or prog ram) the requested number of data blocks and terminate the transaction. The stop command is not required at the end of this type of multiple block read (or write), unless terminated with an error. In order to start a multiple block read (or write) with pre-defined block count, the host must correctly program the HSMCI Block Register (HSMCI_BLKR). Otherwise the card will start an open-ended multiple block read. The BCNT field of the Block Register defines the number of blocks to transfer (from 1 to 65535 blocks). Programming the value 0 in the BCNT field corresponds to an infinite block transfer.

35.8.3 Read Operation

The following flowchart ( Figure 35-8 ) shows how to read a single block with or without use of DMAC facilities. In this example, a polling met hod is used to wait for the end of read. Similarly, the user can configure the interrupt enable regist er (HSMCI_IER) to trigger an interrupt at the end of read.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 592 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Figure 35-8. Read Functional Flow Diagram Notes: 1. It is assumed that this co mmand has been correctly sent (see Figure 35-7). 2. This field is also accessible in the HSMCI Block Register (HSMCI_BLKR). Read status register HSMCI_SR Send SELECT/DESELECT_CARD command(1) to select the card Send SET_BLOCKLEN command(1) Read with DMAC Number of words to read = 0 ? Poll the bit RXRDY = 0? Read data = HSMCI_RDR Number of words to read = Number of words to read -1 Send READ_SINGLE_BLOCK command(1) Ye s Set the DMAEN bit HSMCI_DMA |= DMAEN Set the block length (in bytes) HSMCI_BLKR |= (BlockLength << 16)(2) Configure the DMA channel X DMAC_SADDRx = Data Address DMAC_BTSIZE = BlockLength/4 DMACHEN[X] = TRUE Send READ_SINGLE_BLOCK command(1) Read status register HSMCI_SR Poll the bit XFRDONE = 0? Ye s RETURN RETURN Ye sNo No No Ye s No Number of words to read = BlockLength/4 Reset the DMAEN bit HSMCI_DMA &= ~DMAEN Set the block length (in bytes) HSMCI_MR l= (BlockLength<<16) (2) Set the block count (if neccessary) HSMCI_BLKR l= (BlockCount<<0)

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 593 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

35.8.4 Write Operation

In write operation, the HSMCI Mode Register (HSMCI_MR) is used to define the padding value when writing non-multiple block size. If the bit PADV is 0, then 0x00 value is used when padding data, otherwise 0xFF is used. If set, the bit DMAEN in the HSMCI_DMA register enables DMA transfer. The following flowchart ( Figure 35-9) shows how to write a single block with or without use of DMA facilities. Polling or interrupt method can be used to wait for the end of write according to the contents of the Interrupt Mask Register (HSMCI_IMR).

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 594 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Figure 35-9. Write Functional Flow Diagram Note: 1. It is assumed th at this command has been correctly sent (see Figure 35-7). 2. This field is also accessible in the HSMCI Block Register (HSMCI_BLKR). Send SELECT/DESELECT_CARD command(1) to select the card Send SET_BLOCKLEN command(1) Write using DMAC Send WRITE_SINGLE_BLOCK command(1) Configure the DMA channel X DMAC_DADDRx = Data Address to write DMAC_BTSIZE = BlockLength/4 Send WRITE_SINGLE_BLOCK command(1) Read status register HSMCI_SR Poll the bit XFRDONE = 0? Ye s No Ye s No Read status register HSMCI_SR Number of words to write = 0 ? Poll the bit TXRDY = 0? HSMCI_TDR = Data to write Number of words to write = Number of words to write -1 Ye s RETURN No Ye s No Number of words to write = BlockLength/4 DMAC_CHEN[X] = TRUE Reset theDMAEN bit HSMCI_DMA &= ~DMAEN Set the block length (in bytes) HSMCI_MR |= (BlockLength) <<16)(2) Set the block count (if necessary) HSMCI_BLKR |= (BlockCount << 0) Set the DMAEN bit HSMCI_DMA |= DMAEN Set the block length (in bytes) HSMCI_BLKR |= (BlockLength << 16)(2) RETURN

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 595 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 The following flowchart (Figure 35-10) shows how to manage read multiple block and write mul- tiple block transfers with the DMA Controller. Polling or interrupt method can be used to wait for the end of write according to the contents of the Interrupt Mask Register (HSMCI_IMR). Figure 35-10. Read Multiple Block and Write Multiple Block Notes: 1. It is assumed that this command has been correctly sent (see Figure 35-7). 2. Handle errors reported in HSMCI_SR. Send SELECT/DESELECT_CARD command(1) to select the card Send SET_BLOCKLEN command(1) Set the block length HSMCI_MR |= (BlockLength << 16) Set the DMAEN bit HSMCI_DMA |= DMAEN Configure the HDMA channel X DMAC_SADDRx and DMAC_DADDRx DMAC_BTSIZE = BlockLength/4 Send WRITE_MULTIPLE_BLOCK or READ_MULTIPLE_BLOCK command(1) Read status register DMAC_EBCISR and Poll Bit CBTC[X] New Buffer ?(2) No DMAC_CHEN[X] = TRUE Poll the bit XFRDONE = 1 No RETURN Ye s Send STOP_TRANSMISSION command(1) Ye s Read status register HSMCI_SR and Poll Bit FIFOEMPTY

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 596 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

35.8.5 WRITE_SINGLE_BLOCK Operation using DMA Controller

  1. Wait until the current command execution has successfully terminated. c. Check that CMDRDY and NOTBUSY fields are asserted in HSMCI_SR 2. Program the block length in the card. This value defines the value block_length. 3. Program the block length in the HSMCI configuration register with block_length value. 4. Program HSMCI_DMA register with the following fields: – OFFSET field with dma_offset. – CHKSIZE is user defined and set according to DMAC_DCSIZE. – DMAEN is set to true to enable DMA hardware handshaking in the HSMCI. This bit was previously set to false. 5. Issue a WRITE_SINGLE_BLOCK comman d writing HSMCI_ARG then HSMCI_CMDR. 6. Program the DMA Controller. a. Read the channel Register to choose an available (disabled) channel. b. Clear any pending interrupts on the channel from the previous DMAC transfer by reading the DMAC_EBCISR register. c. Program the channel registers. d. The DMAC_SADDRx register for channel x must be set to the location of the source data. When the first data location is not word aligned, the two LSB bits define the temporary value called dma_offset. The two LSB bits of DMAC_SADDRx must be set to 0. e. The DMAC_DADDRx register for channel x must be set with the starting address of the HSMCI_FIFO address. f. Program DMAC_CTRLAx register of channel x with the following field’s values: –DST_WIDTH is set to WORD. –SRC_WIDTH is set to WORD. –DCSIZE must be set according to the value of HSMCI_DMA, CHKSIZE field. –BTSIZE is programmed with CEILING((block_length + dma_offset) / 4), where the ceiling function is the function that returns the smallest integer not less than g. Program DMAC_CTRLBx register for channel x with the following field’s values: –DST_INCR is set to INCR, the block_length value must not be larger than the HSMCI_FIFO aperture. –SRC_INCR is set to INCR. –FC field is programmed with memory to peripheral flow control mode. –both DST_DSCR and SRC_DSCR are set to 1 (descriptor fetch is disabled). –DIF and SIF are set with their respective layer ID. If SIF is different from DIF , the DMA controller is able to prefetch data and write HSMCI simultaneously. h. Program DMAC_CFGx register for channel x with the following field’s values: –FIFOCFG defines the watermark of the DMAC channel FIFO. –DST_H2SEL is set to true to enable hardware handshaking on the destination. –DST_PER is programmed with the hardware handshaking ID of the targeted HSMCI Host Controller.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 597 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 i. Enable Channel x, writing one to DMAC_CHER[x]. The DMAC is ready and waiting for request. 7. Wait for XFRDONE in HSMCI_SR register.

35.8.6 READ_SINGLE_BLOCK Operation using DMA Controller

35.8.6.1 Block Length is Multiple of 4

  1. Wait until the current command execution has successfully completed. a. Check that CMDRDY and NOTBUSY are asserted in HSMCI_SR. 2. Program the block length in the card. This value defines the value block_length. 3. Program the block length in the HSMCI configuration register with block_length value. 4. Set RDPROOF bit in HSMCI_MR to avoid overflow. 5. Program HSMCI_DMA register with the following fields: – ROPT field is set to 0. – OFFSET field is set to 0. – CHKSIZE is user defined. – DMAEN is set to true to enable DMAC hardware handshaking in the HSMCI. This bit was previously set to false. 6. Issue a READ_SINGLE_BLOCK command. 7. Program the DMA controller. a. Read the channel Register to choose an available (disabled) channel. b. Clear any pending interrupts on the channel from the previous DMA transfer by reading the DMAC_EBCISR register. c. Program the channel registers. d. The DMAC_SADDRx register for channel x must be set with the starting address of the HSMCI_FIFO address. e. The DMAC_DADDRx register for channel x must be word aligned. f. Program DMAC_CTRLAx register of channel x with the following field’s values: –DST_WIDTH is set to WORD. –SRC_WIDTH is set to WORD. –SCSIZE must be set according to the value of HSMCI_DMA, CHKSIZE field. –BTSIZE is programmed with block_length/4. g. Program DMAC_CTRLBx register for channel x with the following field’s values: – DST_INCR is set to INCR. – SRC_INCR is set to INCR. – FC field is programmed with peripheral to memory flow control mode. – both DST_DSCR and SRC_DSCR are set to 1 (descriptor fetch is disabled). – DIF and SIF are set with their respective layer ID. If SIF is different from DIF , the DMA controller is able to prefetch data and write HSMCI simultaneously. h. Program DMAC_CFGx register for channel x with the following field’s values: –FIFOCFG defines the watermark of the DMA channel FIFO. –SRC_H2SEL is set to true to enable hardware handshaking on the destination. –SRC_PER is programmed with the hardware handshaking ID of the targeted HSMCI Host Controller.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 598 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 –Enable Channel x, writing one to DMAC_CHER[x]. The DMAC is ready and waiting for request. 8. Wait for XFRDONE in HSMCI_SR register.

35.8.6.2 Block Length is Not Multiple of 4 and Padding Not Used (ROPT field in HSMCI_DMA register set to 0)

In the previous DMA transfer flow (block length multiple of 4), the DMA controller is configured to use only WORD AHB access. When the block length is no longer a multiple of 4 this is no longer true. The DMA controller is programmed to copy exactly the block length number of bytes using 2 transfer descriptors. 1. Use the previous step until READ_SINGLE_BLOCK then 2. Program the DMA controller to use a two descriptors linked list. a. Read the channel Register to choose an available (disabled) channel. b. Clear any pending interrupts on the channel from the previous DMA transfer by reading the DMAC_EBCISR register. c. Program the channel registers in the Memory for the first descriptor. This descriptor will be word oriented. This descriptor is referred to as LLI_W, standing for LLI word oriented transfer. d. The LLI_W.DMAC_SADDRx field in memory must be set with the starting address of the HSMCI_FIFO address. e. The LLI_W.DMAC_DADDRx field in th e memory must be word aligned. f. Program LLI_W.DMAC_CTRLAx with the following field’s values: –DST_WIDTH is set to WORD. –SRC_WIDTH is set to WORD. –SCSIZE must be set according to the value of HSMCI_DMA, CHKSIZE field. –BTSIZE is programmed with block_length/4. If BTSIZE is zero, this descriptor is skipped later. g. Program LLI_W.DMAC_CTRLBx with the following field’s values: –DST_INCR is set to INCR –SRC_INCR is set to INCR –FC field is programmed with peripheral to memory flow control mode. –SRC_DSCR is set to zero. (descriptor fetch is enabled for the SRC) –DST_DSCR is set to one. (descriptor fetch is disabled for the DST) –DIF and SIF are set with their respective layer ID. If SIF is different from DIF , DMA controller is able to prefetch data and write HSMCI simultaneously. h. Program LLI_W.DMAC_CFGx register for channel x with the following field’s values: –FIFOCFG defines the watermark of the DMA channel FIFO. –DST_REP is set to zero meaning that address are contiguous. –SRC_H2SEL is set to true to enable hardware handshaking on the destination. –SRC_PER is programmed with the hardware handshaking ID of the targeted HSMCI Host Controller. i. Program LLI_W.DMAC_DSCRx with the address of LLI_B descriptor. And set DSCRx_IF to the AHB Layer ID. This operation actually links the Word oriented

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 599 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 descriptor on the second byte oriented descriptor. When block_length[1:0] is equal to 0 (multiple of 4) LLI_W.DMAC_DSCRx points to 0, only LLI_W is relevant. j. Program the channel registers in the Memory for the second descriptor. This descriptor will be byte oriented. This descriptor is referred to as LLI_B, standing for LLI Byte oriented. k. The LLI_B.DMAC_SADDRx field in memory must be set with the starting address of the HSMCI_FIFO address. l. The LLI_B.DMAC_DADDRx is not relevant if previous word aligned descriptor was enabled. If 1, 2 or 3 bytes are transferred that address is user defined and not word aligned. m. Program LLI_B.DMAC_CTRLAx with the following field’s values: –DST_WIDTH is set to BYTE. –SRC_WIDTH is set to BYTE. –SCSIZE must be set according to the value of HSMCI_DMA, CHKSIZE field. –BTSIZE is programmed with block_length[1:0]. (last 1, 2, or 3 bytes of the buffer). n. Program LLI_B.DMAC_CTRLBx with the following field’s values: –DST_INCR is set to INCR –SRC_INCR is set to INCR –FC field is programmed with peripheral to memory flow control mode. –Both SRC_DSCR and DST_DSCR are set to 1 (descriptor fetch is disabled) or Next descriptor location points to 0. –DIF and SIF are set with their respective layer ID. If SIF is different from DIF , DMA Controller is able to prefetch data and write HSMCI simultaneously. o. Program LLI_B.DMAC_CFGx memory location for channel x with the following field’s values: – FIFOCFG defines the watermark of the DMA channel FIFO. – SRC_H2SEL is set to true to enable hardware handshaking on the destination. – SRC_PER is programmed with the hardware handshaking ID of the targeted HSMCI Host Controller. p. Program LLI_B.DMAC_DSCR with 0. q. Program DMAC_CTRLBx register for channel x with 0. its content is updated with the LLI fetch operation. r. Program DMAC_DSCRx with the address of LLI_W if block_length greater than 4 else with address of LLI_B. s. Enable Channel x writing one to DMAC_C HER[x]. The DMAC is ready and waiting for request. 3. Wait for XFRDONE in HSMCI_SR register.

35.8.6.3 Block Length is Not Multiple of 4, with Padding Value (ROPT field in HSMCI_DMA register set to 1)

When the ROPT field is set to one, The DMA Controller performs only WORD access on the bus to transfer a non-multiple of 4 block length. Unlik e previous flow, in which the transfer size is rounded to the nearest multiple of 4. 1. Program the HSMCI Interface, see previous flow. – ROPT field is set to 1. 2. Program the DMA Controller

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 600 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 a. Read the channel Register to choose an available (disabled) channel. b. Clear any pending interrupts on the channel from the previous DMA transfer by reading the DMAC_EBCISR register. c. Program the channel registers. d. The DMAC_SADDRx register for channel x must be set with the starting address of the HSMCI_FIFO address. e. The DMAC_DADDRx register for channel x must be word aligned. f. Program DMAC_CTRLAx register of channel x with the following field’s values: –DST_WIDTH is set to WORD –SRC_WIDTH is set to WORD –SCSIZE must be set according to the value of HSMCI_DMA.CHKSIZE Field. –BTSIZE is programmed with CEILING(block_length/4). g. Program DMAC_CTRLBx register for channel x with the following field’s values: –DST_INCR is set to INCR –SRC_INCR is set to INCR –FC field is programmed with peripheral to memory flow control mode. –both DST_DSCR and SRC_DSCR are set to 1. (descriptor fetch is disabled) –DIF and SIF are set with their respective layer ID. If SIF is different from DIF , the DMA Controller is able to prefetch data and write HSMCI simultaneously. h. Program DMAC_CFGx register for channel x with the following field’s values: –FIFOCFG defines the watermark of the DMA channel FIFO. –SRC_H2SEL is set to true to enable hardware handshaking on the destination. –SRC_PER is programmed with the hardware handshaking ID of the targeted HSMCI Host Controller. –Enable Channel x writing one to DMAC_CHER[x]. The DMAC is ready and waiting for request. 3. Wait for XFRDONE in HSMCI_SR register.

35.8.7 WRITE_MULTIPLE_BLOCK

35.8.7.1 One Block per Descriptor

  1. Wait until the current command execution has successfully terminated. a. Check that CMDRDY and NOTBUSY are asserted in HSMCI_SR. 2. Program the block length in the card. This value defines the value block_length. 3. Program the block length in the HSMCI configuration register with block_length value. 4. Program HSMCI_DMA register with the following fields: – OFFSET field with dma_offset. – CHKSIZE is user defined. – DMAEN is set to true to enable DMAC hardware handshaking in the HSMCI. This bit was previously set to false. 5. Issue a WRITE_MULTIPLE_BLOCK command. 6. Program the DMA Controller to use a list of descriptors. Each descriptor transfers one block of data. Block n of data is transferred with descriptor LLI(n).

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 601 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 a. Read the channel Register to choose an available (disabled) channel. b. Clear any pending interrupts on the channel from the previous DMAC transfer by reading the DMAC_EBCISR register. c. Program a List of descriptors. d. The LLI(n).DMAC_SADDRx memory location for channel x must be set to the loca- tion of the source data. When the first data location is not word aligned, the two LSB bits define the temporary value called dma_offset. The two LSB bits of LLI(n).DMAC_SADDRx must be set to 0. e. The LLI(n).DMAC_DADDRx register for ch annel x must be set with the starting address of the HSMCI_FIFO address. f. Program LLI(n).DMAC_CTRLAx register of channel x with the following field’s values: –DST_WIDTH is set to WORD. –SRC_WIDTH is set to WORD. –DCSIZE must be set according to the value of HSMCI_DMA, CHKSIZE field. –BTSIZE is programmed with CEILING((block_length + dma_offset)/4). g. Program LLI(n).DMAC_CTRLBx register for channel x with the following field’s values: –DST_INCR is set to INCR. –SRC_INCR is set to INCR. –DST_DSCR is set to 0 (fetch operation is enabled for the destination). –SRC_DSCR is set to 1 (source address is contiguous). –FC field is programmed with memory to peripheral flow control mode. –Both DST_DSCR and SRC_DSCR are set to 1 (descriptor fetch is disabled). –DIF and SIF are set with their respective layer ID. If SIF is different from DIF , DMA Controller is able to prefetch data and write HSMCI simultaneously. h. Program LLI(n).DMAC_CFGx register for channel x with the following field’s values: –FIFOCFG defines the watermark of the DMA channel FIFO. –DST_H2SEL is set to true to enable hardware handshaking on the destination. –SRC_REP is set to 0. (contiguous memory access at block boundary) –DST_PER is programmed with the hardware handshaking ID of the targeted HSMCI Host Controller. i. If LLI(n) is the last descriptor, then LLI(n).DSCR points to 0 else LLI(n) points to the start address of LLI(n+1). j. Program DMAC_CTRLBx for channel register x with 0. Its content is updated with the LLI fetch operation. k. Program DMAC_DSCRx for channel register x with the address of the first descrip- tor LLI(0). l. Enable Channel x writing one to DMAC _CHER[x]. The DMA is ready and waiting for request. 7. Poll CBTC[x] bit in the DMAC_EBCISR Register. 8. If a new list of buffers shall be transferred, repeat step 6. Check and handle HSMCI errors. 9. Poll FIFOEMPTY field in the HSMCI_SR.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 602 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 10. Send The STOP_TRANSMISSION co mmand writing HSMCI_ARG then HSMCI_CMDR. 11. Wait for XFRDONE in HSMCI_SR register.

35.8.8 READ_MULTIPLE_BLOCK

35.8.8.1 Block Length is a Multiple of 4

  1. Wait until the current command execution has successfully terminated. a. Check that CMDRDY and NOTBUSY are asserted in HSMCI_SR. 2. Program the block length in the card. This value defines the value block_length. 3. Program the block length in the HSMCI configuration register with block_length value. 4. Set RDPROOF bit in HSMCI_MR to avoid overflow. 5. Program HSMCI_DMA register with the following fields: – ROPT field is set to 0. – OFFSET field is set to 0. – CHKSIZE is user defined. – DMAEN is set to true to enable DMAC hardware handshaking in the HSMCI. This bit was previously set to false. 6. Issue a READ_MULTIPLE_BLOCK command. 7. Program the DMA Controller to use a list of descriptors: a. Read the channel Register to choose an available (disabled) channel. b. Clear any pending interrupts on the channel from the previous DMA transfer by reading the DMAC_EBCISR register. c. Program the channel registers in the Memory with the first descriptor. This descrip- tor will be word oriented. This descriptor is referred to as LLI_W(n), standing for LLI word oriented transfer for block n. d. The LLI_W(n).DMAC_SADDRx field in memory must be set with the starting address of the HSMCI_FIFO address. e. The LLI_W(n).DMAC_DADDRx field in the memory must be word aligned. f. Program LLI_W(n).DMAC_CTRLAx with the following field’s values: –DST_WIDTH is set to WORD –SRC_WIDTH is set to WORD –SCSIZE must be set according to the value of HSMCI_DMA, CHKSIZE field. –BTSIZE is programmed with block_length/4. g. Program LLI_W(n).DMAC_CTRLBx with the following field’s values: –DST_INCR is set to INCR. –SRC_INCR is set to INCR. –FC field is programmed with peripheral to memory flow control mode. –SRC_DSCR is set to 0 (descriptor fetch is enabled for the SRC). –DST_DSCR is set to TRUE (descriptor fetch is disabled for the DST). –DIF and SIF are set with their respective layer ID. If SIF is different from DIF , the DMA Controller is able to prefetch data and write HSMCI simultaneously. h. Program LLI_W(n).DMAC_CFGx register for channel x with the following field’s values: –FIFOCFG defines the watermark of the DMA channel FIFO.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 603 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 –DST_REP is set to zero. Addresses are contiguous. –SRC_H2SEL is set to true to enable hardware handshaking on the destination. –SRC_PER is programmed with the hardware handshaking ID of the targeted HSMCI Host Controller. i. Program LLI_W(n).DMAC_DSCRx with the address of LLI_W(n+1) descriptor. And set the DSCRx_IF to the AHB Layer ID. This operation actually links descriptors together. If LLI_W(n) is the last descriptor then LLI_W(n).DMAC_DSCRx points to j. Program DMAC_CTRLBx register for channel x with 0. its content is updated with the LLI Fetch operation. k. Program DMAC_DSCRx register for channel x with the address of LLI_W(0). l. Enable Channel x writing one to DMAC _CHER[x]. The DMA is ready and waiting for request. 8. Poll CBTC[x] bit in the DMAC_EBCISR Register. 9. If a new list of buffer shall be transferred repeat step 6. Check and handle HSMCI errors. 10. Poll FIFOEMPTY field in the HSMCI_SR. 11. Send The STOP_TRANSMISSION command writing the HSMCI_ARG then the HSMCI_CMDR. 12. Wait for XFRDONE in HSMCI_SR register. 35.8.8.2 Block Length is Not Multiple of 4. (ROPT field in HSMCI_DMA register set to 0) Two DMA Transfer descriptors are used to perform the HSMCI block transfer. 1. Use the previous step to configure the HSMCI to perform a READ_MULTIPLE_BLOCK command. 2. Issue a READ_MULTIPLE_BLOCK command. 3. Program the DMA Controller to use a list of descriptors. a. Read the channel register to choose an available (disabled) channel. b. Clear any pending interrupts on the channel from the previous DMAC transfer by reading the DMAC_EBCISR register. c. For every block of data repeat the following procedure: d. Program the channel registers in the Memory for the first descriptor. This descriptor will be word oriented. This descriptor is referred to as LLI_W(n) standing for LLI word oriented transfer for block n. e. The LLI_W(n).DMAC_SADDRx field in memory must be set with the starting address of the HSMCI_FIFO address. f. The LLI_W(n).DMAC_DADDRx field in the memory must be word aligned. g. Program LLI_W(n).DMAC_CTRLAx with the following field’s values: –DST_WIDTH is set to WORD. –SRC_WIDTH is set to WORD. –SCSIZE must be set according to the value of HSMCI_DMA, CHKSIZE field. –BTSIZE is programmed with block_length/4. If BTSIZE is zero, this descriptor is skipped later. h. Program LLI_W(n).DMAC_CTRLBx with the following field’s values: –DST_INCR is set to INCR.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 604 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 –SRC_INCR is set to INCR. –FC field is programmed with peripheral to memory flow control mode. –SRC_DSCR is set to 0 (descriptor fetch is enabled for the SRC). –DST_DSCR is set to TRUE (descriptor fetch is disabled for the DST). –DIF and SIF are set with their respective layer ID. If SIF is different from DIF , the DMA Controller is able to prefetch data and write HSMCI simultaneously. i. Program LLI_W(n).DMAC_CFGx register for channel x with the following field’s values: –FIFOCFG defines the watermark of the DMA channel FIFO. –DST_REP is set to zero. Address are contiguous. –SRC_H2SEL is set to true to enable hardware handshaking on the destination. –SRC_PER is programmed with the hardware handshaking ID of the targeted HSMCI Host Controller. j. Program LLI_W(n).DMAC_DSCRx with the address of LLI_B(n) descriptor. And set the DSCRx_IF to the AHB Layer ID. This operation actually links the Word oriented descriptor on the second byte oriented descriptor. When block_length[1:0] is equal to 0 (multiple of 4) LLI_W(n).DMAC_DSCRx points to 0, only LLI_W(n) is relevant. k. Program the channel registers in the Memory for the second descriptor. This descriptor will be byte oriented. This descriptor is referred to as LLI_B(n), standing for LLI Byte oriented. l. The LLI_B(n).DMAC_SADDRx field in memory must be set with the starting address of the HSMCI_FIFO address. m. The LLI_B(n).DMAC_DADDRx is not relevant if previous word aligned descriptor was enabled. If 1, 2 or 3 bytes are transferred, that address is user defined and not word aligned. n. Program LLI_B(n).DMAC_CTRLAx with the following field’s values: –DST_WIDTH is set to BYTE. –SRC_WIDTH is set to BYTE. –SCSIZE must be set according to the value of HSMCI_DMA, CHKSIZE field. –BTSIZE is programmed with block_length[1:0]. (last 1, 2, or 3 bytes of the buffer). o. Program LLI_B(n).DMAC_CTRLBx with the following field’s values: – DST_INCR is set to INCR. – SRC_INCR is set to INCR. – FC field is programmed with peripheral to memory flow control mode. – Both SRC_DSCR and DST_DSCR are set to 1 (descriptor fetch is disabled) or Next descriptor location points to 0. – DIF and SIF are set with their respective layer ID. If SIF is different from DIF , the DMA Controller is able to prefetch data and write HSMCI simultaneously. p. Program LLI_B(n).DMAC_CFGx memory lo cation for channel x with the following field’s values: – FIFOCFG defines the watermark of the DMAC channel FIFO. – SRC_H2SEL is set to true to enable hardware handshaking on the destination. – SRC_PER is programmed with the hardware handshaking ID of the targeted HSMCI Host Controller

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 605 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 q. Program LLI_B(n).DMAC_DSCR with address of descriptor LLI_W(n+1). If LLI_B(n) is the last descriptor, then program LLI_B(n).DMAC_DSCR with 0. r. Program DMAC_CTRLBx register for channel x with 0, its content is updated with the LLI Fetch operation. s. Program DMAC_DSCRx with the address of LLI_W(0) if block_length is greater than 4 else with address of LLI_B(0). t. Enable Channel x writing one to DMAC_CHER[x]. The DMAC is ready and waiting for request. 4. Enable DMADONE interrupt in the HSMCI_IER register. 5. Poll CBTC[x] bit in the DMAC_EBCISR Register. 6. If a new list of buffers shall be transferred, repeat step 7. Check and handle HSMCI errors. 7. Poll FIFOEMPTY field in the HSMCI_SR. 8. Send The STOP_TRANSMISSION co mmand writing HSMCI_ARG then HSMCI_CMDR. 9. Wait for XFRDONE in HSMCI_SR register. 35.8.8.3 Block Length is Not a Multiple of 4. (ROPT field in HSMCI_DMA register set to 1) One DMA Transfer descriptor is used to perform the HSMCI block transfer, the DMA writes a rounded up value to the nearest multiple of 4. 1. Use the previous step to configure the HSMCI to perform a READ_MULTIPLE_BLOCK. 2. Set the ROPT field to 1 in the HSMCI_DMA register. 3. Issue a READ_MULTIPLE_BLOCK command. 4. Program the DMA controller to use a list of descriptors: a. Read the channel Register to choose an available (disabled) channel. b. Clear any pending interrupts on the channel from the previous DMAC transfer by reading the DMAC_EBCISR register. c. Program the channel registers in the Memory with the first descriptor. This descrip- tor will be word oriented. This descriptor is referred to as LLI_W(n), standing for LLI word oriented transfer for block n. d. The LLI_W(n).DMAC_SADDRx field in memory must be set with the starting address of the HSMCI_FIFO address. e. The LLI_W(n).DMAC_DADDRx field in the memory must be word aligned. f. Program LLI_W(n).DMAC_CTRLAx with the following field’s values: –DST_WIDTH is set to WORD. –SRC_WIDTH is set to WORD. –SCSIZE must be set according to the value of HSMCI_DMA, CHKSIZE field. –BTSIZE is programmed with Ceiling(block_length/4). g. Program LLI_W(n).DMAC_CTRLBx with the following field’s values: –DST_INCR is set to INCR –SRC_INCR is set to INCR –FC field is programmed with peripheral to memory flow control mode. –SRC_DSCR is set to 0. (descriptor fetch is enabled for the SRC) –DST_DSCR is set to TRUE. (descriptor fetch is disabled for the DST)

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 606 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 –DIF and SIF are set with their respective layer ID. If SIF is different from DIF , the DMA Controller is able to prefetch data and write HSMCI simultaneously. h. Program LLI_W(n).DMAC_CFGx register for channel x with the following field’s values: –FIFOCFG defines the watermark of the DMA channel FIFO. –DST_REP is set to zero. Address are contiguous. –SRC_H2SEL is set to true to enable hardware handshaking on the destination. –SRC_PER is programmed with the hardware handshaking ID of the targeted HSMCI Host Controller. i. Program LLI_W(n).DMAC_DSCRx with the address of LLI_W(n+1) descriptor. And set the DSCRx_IF to the AHB Layer ID. This operation actually links descriptors together. If LLI_W(n) is the last descriptor then LLI_W(n).DMAC_DSCRx points to j. Program DMAC_CTRLBx register for channel x with 0. its content is updated with the LLI Fetch operation. k. Program DMAC_DSCRx register for channel x with the address of LLI_W(0). l. Enable Channel x writing one to DMAC_C HER[x]. The DMAC is ready and waiting for request. 5. Poll CBTC[x] bit in the DMAC_EBCISR Register. 6. If a new list of buffers shall be transferred repeat step 7. Check and handle HSMCI errors. 7. Poll FIFOEMPTY field in the HSMCI_SR. 8. Send The STOP_TRANSMISSION command writing the HSMCI_ARG then the HSMCI_CMDR. 9. Wait for XFRDONE in HSMCI_SR register.

35.9 SD/SDIO Card Operation

The High Speed MultiMedia Card Interface allows processing of SD Memory (Secure Digital Memory Card) and SDIO (SD Input Output) Card commands. SD/SDIO cards are based on the Multi Media Card (MMC) format, but are physically slightly thicker and feature higher data transfer rates, a lock switch on the side to prevent accidental overwriting and security featur es. The physical form factor, pin assignment and data transfer protocol are forward-compatible with the High Speed MultiMedia Card with some additions. SD slots can actually be used for more than flash memory cards. Devices that support SDIO can use small devices designed for the SD form fact or, such as GPS receivers, Wi-Fi or Bluetooth adapters, modems, barcode readers, IrDA adapters, FM radio tuners, RFID readers, digital cam- eras and more. SD/SDIO is covered by numerous patents and trademarks, and licensing is only available through the Secure Digital Card Association. The SD/SDIO Card communication is based on a 9-pin interface (Clock, Command, 4 x Data and 3 x Power lines). The communication protocol is defined as a part of this specification. The main difference between the SD/SDIO Card and t he High Speed MultiMedia Card is the initial- ization process. The SD/SDIO Card Register (HSMCI_SDCR) allows selection of the Card Slot and the data bus width.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 607 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 The SD/SDIO Card bus allows dynamic configur ation of the number of data lines. After power up, by default, the SD/SDIO Card uses only DAT0 for data transfer. After initialization, the host can change the bus width (number of active data lines).

35.9.1 SDIO Data Transfer Type

SDIO cards may transfer data in either a multi-byte (1 to 512 bytes) or an optional block format (1 to 511 blocks), while the SD memory cards are fixed in the block transfer mode. The TRTYP field in the HSMCI Command Register (HSMCI_CMDR) allows to choose between SDIO Byte or SDIO Block transfer. The number of bytes/blocks to transfer is set through the BCNT field in the HSMCI Block Regis- ter (HSMCI_BLKR). In SDIO Block mode, the field BLKLEN must be set to the data block size while this field is not used in SDIO Byte mode. An SDIO Card can have multiple I/O or combined I/O and memory (called Combo Card). Within a multi-function SDIO or a Combo card, there are multiple devices (I/O and memory) that share access to the SD bus. In order to allow the sharing of access to the host among multiple devices, SDIO and combo cards can implement the optional concept of suspend/resume (Refer to the SDIO Specification for more details). To send a suspend or a resume command, the host must set the SDIO Special Command field (IOSPCMD) in the HSMCI Command Register.

35.9.2 SDIO Interrupts

Each function within an SDIO or Combo card may implement interrupts (Refer to the SDIO Specification for more details). In order to allow the SDIO card to interrupt the host, an interrupt function is added to a pin on the DAT[1] line to signal the card’s interrupt to the host. An SDIO interrupt on each slot can be enabled through the HSMCI Interrupt Enable Register. The SDIO interrupt is sampled regardless of the currently selected slot.

35.10 CE-ATA Operation

CE-ATA maps the streamlined ATA command set onto the MMC interface. The ATA task file is mapped onto MMC register space. CE-ATA utilizes five MMC commands:

  • GO_IDLE_STATE (CMD0): used for hard reset.
  • STOP_TRANSMISSION (CMD12): causes the ATA command currently executing to be aborted.
  • FAST_IO (CMD39): Used for single register access to the ATA taskfile registers, 8 bit access only.
  • RW_MULTIPLE_REGISTERS (CMD60): used to issue an ATA command or to access the control/status registers.
  • RW_MULTIPLE_BLOCK (CMD61): used to transfer data for an ATA command. CE-ATA utilizes the same MMC command s equences for initialization as traditional MMC devices.

35.10.1 Executing an ATA Polling Command

  1. Issue READ_DMA_EXT with RW_MULTIPLE_ REGISTER (CMD60) for 8kB of DATA. 2. Read the ATA status register until DRQ is set. 3. Issue RW_MULTIPLE_BLOCK (CMD61) to transfer DATA. 4. Read the ATA status register until DRQ && BSY are set to 0.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 608 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

35.10.2 Executing an ATA Interrupt Command

  1. Issue READ_DMA_EXT with RW_MULTIPLE_ REGISTER (CMD60) for 8kB of DATA with nIEN field set to zero to enable the command completion signal in the device. 2. Issue RW_MULTIPLE_BLOCK (CMD61) to transfer DATA. 3. Wait for Completion Signal Received Interrupt.

35.10.3 Aborting an ATA Command

If the host needs to abort an ATA command prior to the completion signal it must send a special command to avoid potential collision on t he command line. The SPCMD field of the HSMCI_CMDR must be set to 3 to issue the CE-ATA completion Signal Disable Command.

35.10.4 CE-ATA Error Recovery

Several methods of ATA command failure may occur, including:

  • No response to an MMC command, such as RW_MULTIPLE_REGISTER (CMD60).
  • CRC is invalid for an MMC command or response.
  • CRC16 is invalid for an MMC data packet.
  • ATA Status register reflects an error by setting the ERR bit to one.
  • The command completion signal does not arrive within a host specified time out period. Error conditions are expected to happen infreq uently. Thus, a robust error recovery mechanism may be used for each error event. The recommended error recovery procedure after a timeout is:
  • Issue the command completion signal disable if nIEN was cleared to zero and the RW_MULTIPLE_BLOCK (CMD61) response has been received.
  • Issue STOP_TRANSMISSION (CMD12) and successfully receive the R1 response.
  • Issue a software reset to the CE-ATA device using FAST_IO (CMD39). If STOP_TRANMISSION (CMD12) is successful , then the device is again ready for ATA com- mands. However, if the error recovery procedure does not work as expected or there is another timeout, the next step is to issue GO_IDLE_STATE (CMD0) to the device. GO_IDLE_STATE (CMD0) is a hard reset to the device and completely resets all device states. Note that after issuing GO_IDLE_STATE (CMD0), all device initialization needs to be completed again. If the CE-ATA device completes all MMC commands correctly but fails the ATA command with the ERR bit set in the ATA Status register , no error recovery action is required. The ATA command itself failed implying that the device could not complete the action requested, how- ever, there was no communication or protocol failure. After the device signals an error by setting the ERR bit to one in the ATA Status register, the host may attempt to retry the command.

35.11 HSMCI Boot Operation Mode

In boot operation mode, the processor can read boot data from the slave (MMC device) by keep- ing the CMD line low after power-on before issuing CMD1. The data can be read from either the boot area or user area, depending on register setting. Boot Procedure, Processor Mode 1. Configure the HSMCI data bus width programming SDCBUS Field in the HSMCI_SDCR register. The BOOT_BUS_WIDTH field located in the device Extended CSD register must be set accordingly. 2. Set the byte count to 512 bytes and the block count to the desired number of blocks, writing BLKLEN and BCNT fields of the HSMCI_BLKR Register.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 609 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 3. Issue the Boot Operation Request command by writing to the HSMCI_CMDR register with SPCMD field set to BOOTREQ, TRDIR set to READ and TRCMD set to “start data transfer”. 4. The BOOT_ACK field located in the HSMCI_CMDR register must be set to one, if the BOOT_ACK field of the MMC device located in the Extended CSD register is set to one. 5. Host processor can copy boot data sequentially as soon as the RXRDY flag is asserted. 6. When Data transfer is completed, host processor shall terminate the boot stream by writing the HSMCI_CMDR register with SPCMD field set to BOOTEND.

35.11.1 Boot Procedure DMA Mode

  1. Configure the HSMCI data bus width by programming SDCBUS Field in the HSMCI_SDCR register. The BOOT_BUS_WIDTH field in the device Extended CSD register must be set accordingly. 2. Set the byte count to 512 bytes and the block count to the desired number of blocks by writing BLKLEN and BCNT fields of the HSMCI_BLKR Register. 3. Enable DMA transfer in the HSMCI_DMA register. 4. Configure DMA controller, program the total amount of data to be transferred and enable the relevant channel. 5. Issue the Boot Operation Request command by writing to the HSMCI_CMDR register with SPCND set to BOOTREQ, TRDIR set to READ and TRCMD set to “start data transfer”. 6. DMA controller copies the boot partition to the memory. 7. When DMA transfer is completed, host processor shall terminate the boot stream by writing the HSMCI_CMDR register with SPCMD field set to BOOTEND.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 610 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

35.12 HSMCI Transfer Done Timings

35.12.1 Definition

The XFRDONE flag in the HSMCI_SR indicate s exactly when the read or write sequence is finished.

35.12.2 Read Access

During a read access, the XFRDONE flag behaves as shown in Figure 35-11. Figure 35-11. XFRDONE During a Read Access

35.12.3 Write Access

During a write access, the XFRDONE flag behaves as shown in Figure 35-12. Figure 35-12. XFRDONE During a Write Access CMD line HSMCI read CMD Card response CMDRDY flag Data 1st Block Last Block Not busy flag XFRDONE flag The CMDRDY flag is released 8 tbit after the end of the card response. CMD line Card response CMDRDY flag Data bus - D0 1st Block Not busy flag XFRDONE flag The CMDRDY flag is released 8 tbit after the end of the card response. Last Block 1st Block Last Block D0 is tied by the card D0 is released HSMCI write CMD

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 611 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

35.13 Write Protection Registers

To prevent any single software error that may corrupt HSMCI behavior, the entire HSMCI address space from address offset 0x000 to 0x00FC can be write-protected by setting the WPEN bit in the “HSMCI Write Protect Mode Register” (HSMCI_WPMR). If a write access to anywhere in the HSMCI address space from address offset 0x000 to 0x00FC is detected, then the WPVS flag in the HSMCI Write Protect Status Register (HSMCI_WPSR) is set and the field WPVSRC indicates in which register the write access has been attempted. The WPVS flag is reset by writing the HSMCI Write Protect Mode Register (HSMCI_WPMR) with the appropriate access key, WPKEY. The protected registers are:

  • “HSMCI Mode Register” on page 614
  • “HSMCI Data Timeout Register” on page 616
  • “HSMCI SDCard/SDIO Register” on page 617
  • “HSMCI Completion Signal Timeout Register” on page 623
  • “HSMCI DMA Configuration Register” on page 636
  • “HSMCI Configuration Register” on page 637

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 612 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

35.14 High Speed MultiMediaCard In terface (HSMCI) User Interface

Note: 1. The response register can be read by N accesses at the same HSMCI_RSPR or at consecutive addresses (0x20 to 0x2C). N depends on the size of the response. Table 35-7. Register Mapping Offset Register Name Access Reset 0x00 Control Register HSMCI_CR Write – 0x04 Mode Register HSMCI_MR Read-write 0x0 0x08 Data Timeout Register HSMCI_DTOR Read-write 0x0 0x0C SD/SDIO Card Register HSMCI_SDCR Read-write 0x0 0x10 Argument Register HSMCI_ARGR Read-write 0x0 0x14 Command Register HSMCI_CMDR Write – 0x18 Block Register HSMCI_BLKR Read-write 0x0 0x1C Completion Signal Timeout Register HSMCI_CSTOR Read-write 0x0 0x20 Response Register (1) HSMCI_RSPR Read 0x0 0x24 Response Register (1) HSMCI_RSPR Read 0x0 0x28 Response Register (1) HSMCI_RSPR Read 0x0 0x2C Response Register (1) HSMCI_RSPR Read 0x0 0x30 Receive Data Register HSMCI_RDR Read 0x0 0x34 Transmit Data Register HSMCI_TDR Write – 0x38 - 0x3C Reserved – – – 0x40 Status Register HSMCI_SR Read 0xC0E5 0x44 Interrupt Enable Register HSMCI_IER Write – 0x48 Interrupt Disable Register HSMCI_IDR Write – 0x4C Interrupt Mask Register HSMCI_IMR Read 0x0 0x50 DMA Configuration Register HSMCI_DMA Read-write 0x00 0x54 Configuration Register HSMCI_CFG Read-write 0x00 0x58-0xE0 Reserved – – – 0xE4 Write Protection Mode Register HSMCI_WPMR Read-write – 0xE8 Write Protection Status Register HSMCI_WPSR Read-only – 0xEC - 0xFC Reserved – – – 0x100-0x1FC Reserved – – – 0x200 FIFO Memory Aperture0 HSMCI_FIFO0 Read-write 0x0 0x5FC FIFO Memory Aperture255 HSMCI_FIFO255 Read-write 0x0

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 613 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

35.14.1 HSMCI Control Register

Name: HSMCI_CR Address: 0xF0008000 Access: Write-only  MCIEN: Multi-Media Interface Enable 0 = No effect. 1 = Enables the Multi-Media Interface if MCDIS is 0.  MCIDIS: Multi-Media Interface Disable 0 = No effect. 1 = Disables the Multi-Media Interface.  PWSEN: Power Save Mode Enable 0 = No effect. 1 = Enables the Power Saving Mode if PWSDIS is 0. Warning: Before enabling this mode, the user must set a value different from 0 in the PWSDIV field (Mode Register, HSMCI_MR).  PWSDIS: Power Save Mode Disable 0 = No effect. 1 = Disables the Power Saving Mode.  SWRST: Software Reset 0 = No effect. 1 = Resets the HSMCI. A software triggered hardware reset of the HSMCI interface is performed. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 SWRST – – – PWSDIS PWSEN MCIDIS MCIEN

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 614 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

35.14.2 HSMCI Mode Register

Name: HSMCI_MR Address: 0xF0008004 Access: Read-write This register can only be written if the WPEN bit is cleared in “HSMCI Write Protect Mode Register” on page 638.  CLKDIV: Clock Divider High Speed MultiMedia Card Inte rface clock (MCCK or HSMCI_CK) is Master Clock (MCK) divider by ({CLKDIV,CLKODD}+2).  PWSDIV: Power Saving Divider High Speed MultiMedia Card Interface clock is divided by 2(PWSDIV) + 1 when entering Power Saving Mode. Warning: This value must be different from 0 before enabling the Power Save Mode in the HSMCI_CR (HSMCI_PWSEN bit).  RDPROOF Read Proof Enable Enabling Read Proof allows to stop the HSMCI Clock during read access if the internal FIFO is full. This will guarantee data integrity, not bandwidth. 0 = Disables Read Proof. 1 = Enables Read Proof.  WRPROOF Write Proof Enable Enabling Write Proof allows to stop the HSMCI Clock during write access if the internal FIFO is full. This will guarantee data integrity, not bandwidth. 0 = Disables Write Proof. 1 = Enables Write Proof.  FBYTE: Force Byte Transfer Enabling Force Byte Transfer allow byte transfers, so that transfer of blocks with a size different from modulo 4 can be supported. Warning: BLKLEN value depends on FBYTE. 0 = Disables Force Byte Transfer. 1 = Enables Force Byte Transfer. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 – PADV FBYTE WRPROOF RDPROOF PWSDIV 76543210 CLKDIV

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 615 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12  PADV: Padding Value 0 = 0x00 value is used when padding data in write transfer. 1 = 0xFF value is used when padding data in write transfer. PADV may be only in manual transfer.  CLKODD: Clock divider is odd This field is the least significant bit of the clock divider and indicates the clock divider parity.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 616 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

35.14.3 HSMCI Data Timeout Register

Name: HSMCI_DTOR Address: 0xF0008008 Access: Read-write This register can only be written if the WPEN bit is cleared in “HSMCI Write Protect Mode Register” on page 638.  DTOCYC: Data Timeout Cycle Number These fields determine the maximum numb er of Master Clock cycles that the HSMCI waits between two data block trans- fers. It equals (DTOCYC x Multiplier).  DTOMUL: Data Timeout Multiplier Multiplier is defined by DTOMUL as shown in the following table: If the data time-out set by DTOCYC and DTOMUL has been exceeded, the Data Time-out Error flag (DTOE) in the HSMCI Status Register (HSMCI_SR) rises. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 – DTOMUL DTOCYC Value Name Description

01 DTOCYC

7 1048576 DTOCYC x 1048576

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 617 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

35.14.4 HSMCI SDCard/SDIO Register

Name: HSMCI_SDCR Address: 0xF000800C Access: Read-write This register can only be written if the WPEN bit is cleared in “HSMCI Write Protect Mode Register” on page 638.  SDCSEL: SDCard/SDIO Slot  SDCBUS: SDCard/SDIO Bus Width 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 SDCBUS –––– S DCSEL Value Name Description 0S LOTA Slot A is selected. 1S L O T B – 2S L O T C – 3S L O T D – Value Name Description 1 bit 1– Reserved 24 4 bit 38 8 bit

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 618 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

35.14.5 HSMCI Argument Register

Name: HSMCI_ARGR Address: 0xF0008010 Access: Read-write  ARG: Command Argument 31 30 29 28 27 26 25 24 ARG 23 22 21 20 19 18 17 16 ARG 15 14 13 12 11 10 9 8 ARG 76543210 ARG

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 619 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

35.14.6 HSMCI Command Register

Name: HSMCI_CMDR Address: 0xF0008014 Access: Write-only This register is write-protected while CM DRDY is 0 in HSMCI_SR. If an Interrupt command is sent, this register is only writeable by an interrupt response (field SPCMD). This means that the current command execution cannot be interrupted or modified.  CMDNB: Command Number This is the command index.  RSPTYP: Response Type  SPCMD: Special Command 31 30 29 28 27 26 25 24 –––– B OOT_ACK A TACS I OSPCMD 23 22 21 20 19 18 17 16 – – TRTYP TRDIR TRCMD 15 14 13 12 11 10 9 8 – – – MAXLAT OPDCMD SPCMD 76543210 RSPTYP CMDNB Value Name Description 0 NORESP No response. 1 48_BIT 48-bit response. 2 136_BIT 136-bit response.

3 R1B R1b response type

0 STD Not a special CMD. 1I NIT Initialization CMD: 74 clock cycles for initialization sequence.

2 SYNC Synchronized CMD:

Wait for the end of the current data block transfer before sending the pending command. 3C E_ATA CE-ATA Completion Signal disable Command. The host cancels the ability for the device to return a command completion signal on the command line. 4I T_CMD Interrupt command: Corresponds to the Interrupt Mode (CMD40).

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 620 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12  OPDCMD: Open Drain Command 0 (PUSHPULL) = Push pull command. 1 (OPENDRAIN) = Open drain command.  MAXLAT: Max Latency for Command to Response 0 (5) = 5-cycle max latency. 1 (64) = 64-cycle max latency.  TRCMD: Transfer Command  TRDIR: Transfer Direction 0 (WRITE) = Write. 1 (READ) = Read.  TRTYP: Transfer Type  IOSPCMD: SDIO Special Command

5 IT_RESP Interrupt response:

Corresponds to the Interrupt Mode (CMD40). 6B OR Boot Operation Request. Start a boot operation mode, the host processor can read boot data from the MMC device directly. 7E BO End Boot Operation. This command allows the host processor to terminate the boot operation mode. Value Name Description

0 NO_DATA No data transfer

1 START_DATA Start data transfer

2 STOP_DATA Stop data transfer

3– R eserved Value Name Description

0 SINGLE MMC/SDCard Single Block

1 MULTIPLE MMC/SDCard Multiple Block

2 STREAM MMC Stream

4 BYTE SDIO Byte

5 BLOCK SDIO Block

0 STD Not an SDIO Special Command

1 SUSPEND SDIO Suspend Command

2 RESUME SDIO Resume Command

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 621 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12  ATACS: ATA with Command Completion Signal 0 (NORMAL) = Normal operation mode. 1 (COMPLETION) = This bit indicates that a completion signal is expected within a programmed amount of time (HSMCI_CSTOR).  BOOT_ACK: Boot Operation Acknowledge. The master can choose to receive the boot acknowledge fr om the slave when a Boot Request command is issued. When set to one this field indicates that a Boot acknowledge is expected within a programmabl e amount of time defined with DTOMUL and DTOCYC fields located in the HSMCI_DTOR register. If the acknowledge pattern is not received then an acknowledge timeout error is raised. If the acknowledge pattern is corrupted then an acknowledge pattern error is set.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 622 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

35.14.7 HSMCI Block Register

Name: HSMCI_BLKR Address: 0xF0008018 Access: Read-write  BCNT: MMC/SDIO Block Count - SDIO Byte Count This field determines the number of data byte(s) or block(s) to transfer. The transfer data type and the authorized values for BCNT field are determined by the TR TYP field in the HSMCI Com- mand Register (HSMCI_CMDR): Warning: In SDIO Byte and Block modes, writing to the 7 last bits of BCNT field is forbidden and may lead to unpredictable results.  BLKLEN: Data Block Length This field determines the size of the data block. This field is also accessible in the HSMCI Mode Register (HSMCI_MR). Bits 16 and 17 must be set to 0 if FBYTE is disabled. Note: In SDIO Byte mode, BLKLEN field is not used. 31 30 29 28 27 26 25 24 BLKLEN 23 22 21 20 19 18 17 16 BLKLEN 15 14 13 12 11 10 9 8 BCNT 76543210 BCNT Value Name Description 0M U L T I P L E MMC/SDCARD Multiple Block From 1 to 65635: Value 0 corresponds to an infinite block transfer.

4 BYTE

From 1 to 512 bytes: Value 0 corresponds to a 512-byte transfer. Values from 0x200 to 0xFFFF are forbidden. 5B L O C K SDIO Block From 1 to 511 blocks: Value 0 corresponds to an infinite block transfer. Values from 0x200 to 0xFFFF are forbidden.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 623 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

35.14.8 HSMCI Completion Signal Timeout Register

Name: HSMCI_CSTOR Address: 0xF000801C Access: Read-write This register can only be written if the WPEN bit is cleared in “HSMCI Write Protect Mode Register” on page 638.  CSTOCYC: Completion Signal Timeout Cycle Number These fields determine the maximum numb er of Master Clock cycles that the HSMCI waits between two data block trans- fers. Its value is calculated by (CSTOCYC x Multiplier).  CSTOMUL: Completion Signal Timeout Multiplier These fields determine the maximum numb er of Master Clock cycles that the HSMCI waits between two data block trans- fers. Its value is calculated by (CSTOCYC x Multiplier). These fields determine the maximum number of Master Clock cycles that the HSMCI waits between the end of the data transfer and the assertion of the completion signal. The data transfer comprises data phase and the optional busy phase. If a non-DATA ATA command is issued, the HSMCI starts waiting immediately after the end of the response until the comple- tion signal. Multiplier is defined by CSTOMUL as shown in the following table: If the data time-out set by CSTOCYC and CSTOMUL has b een exceeded, the Completion Signal Time-out Error flag (CSTOE) in the HSMCI Status Register (HSMCI_SR) rises. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 – CSTOMUL CSTOCYC Value Name Description 0 1 CSTOCYC x 1 1 16 CSTOCYC x 16 2 128 CSTOCYC x 128 3 256 CSTOCYC x 256 4 1024 CSTOCYC x 1024 5 4096 CSTOCYC x 4096 6 65536 CSTOCYC x 65536 7 1048576 CSTOCYC x 1048576

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 624 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

35.14.9 HSMCI Response Register

Name: HSMCI_RSPR Address: 0xF0008020 Access: Read-only  RSP: Response Note: 1. The response register can be read by N accesses at the same HSMCI_RSPR or at consecutive addresses (0x20 to 0x2C). N depends on the size of the response.

35.14.10 HSMCI Receive Data Register

Name: HSMCI_RDR Address: 0xF0008030 Access: Read-only  DATA: Data to Read 31 30 29 28 27 26 25 24 RSP 23 22 21 20 19 18 17 16 RSP 15 14 13 12 11 10 9 8 RSP 76543210 RSP 31 30 29 28 27 26 25 24 DATA 23 22 21 20 19 18 17 16 DATA 15 14 13 12 11 10 9 8 DATA 76543210 DATA

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 625 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

35.14.11 HSMCI Transmit Data Register

Name: HSMCI_TDR Address: 0xF0008034 Access: Write-only  DATA: Data to Write 31 30 29 28 27 26 25 24 DATA 23 22 21 20 19 18 17 16 DATA 15 14 13 12 11 10 9 8 DATA 76543210 DATA

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 626 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

35.14.12 HSMCI Status Register

Name: HSMCI_SR Address: 0xF0008040 Access: Read-only  CMDRDY: Command Ready 0 = A command is in progress. 1 = The last command has been sent. Cleared when writing in the HSMCI_CMDR.  RXRDY: Receiver Ready 0 = Data has not yet been received since the last read of HSMCI_RDR. 1 = Data has been received since the last read of HSMCI_RDR.  TXRDY: Transmit Ready 0= The last data written in HSMCI_TDR has not yet been transferred in the Shift Register. 1= The last data written in HSMCI_TDR has been transferred in the Shift Register.  BLKE: Data Block Ended This flag must be used only for Write Operations. 0 = A data block transfer is not yet finished. Cleared when reading the HSMCI_SR. 1 = A data block transfer has ended, including the CRC16 Status transmission. the flag is set for each transmitted CRC Status. Refer to the MMC or SD Specification for more details concerning the CRC Status.  DTIP: Data Transfer in Progress 0 = No data transfer in progress. 1 = The current data transfer is still in progress, including CRC16 calculation. Cleared at the end of the CRC16 calculation.  NOTBUSY: HSMCI Not Busy A block write operation uses a simple busy signalling of the write operat ion duration on the data (DAT0) line: during a data transfer block, if the card does not have a free data receive buffer, the card indicates this condition by pulling down the data line (DAT0) to LOW. The card stops pulling down the data line as soon as at least one receive buffer for the defined data transfer block length becomes free. The NOTBUSY flag allows to deal with these different states. 0 = The HSMCI is not ready for new data transfer. Cleared at the end of the card response. 31 30 29 28 27 26 25 24 UNRE OVRE ACKRCVE ACKRCV XFRDONE FIFOEMPTY DMADONE BLKOVRE 23 22 21 20 19 18 17 16 CSTOE DTOE DCRCE RTOE RENDE RCRCE RDIRE RINDE 15 14 13 12 11 10 9 8 – – CSRCV SDIOWAIT – – – SDIOIRQA 76543210 – – NOTBUSY DTIP BLKE TXRDY RXRDY CMDRDY

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 627 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 1 = The HSMCI is ready for new data transfer. Set when the busy state on the data line has ended. This corresponds to a free internal data receive buffer of the card. Refer to the MMC or SD Specification for more details concerning the busy behavior. For all the read operations, the NOTBUSY flag is cleared at the end of the host command. For the Infinite Read Multiple Blocks, the NOTBUSY flag is set at the end of the ST OP_TRANSMISSION host command (CMD12). For the Single Block Reads, the NOTBUSY flag is set at the end of the data read block. For the Multiple Block Reads with pre-defined block count, the NOTBUSY flag is set at the end of the last received data block.  SDIOIRQA: SDIO Interrupt for Slot A 0 = No interrupt detected on SDIO Slot A. 1 = An SDIO Interrupt on Slot A occurred. Cleared when reading the HSMCI_SR.  SDIOWAIT: SDIO Read Wait Operation Status 0 = Normal Bus operation. 1 = The data bus has entered IO wait state.  CSRCV: CE-ATA Comple tion Signal Received 0 = No completion signal received since last status read operation. 1 = The device has issued a command completion signal on the command line. Cleared by reading in the HSMCI_SR register.  RINDE: Response Index Error 0 = No error. 1 = A mismatch is detected between the command index sent and the response index received. Cleared when writing in the HSMCI_CMDR.  RDIRE: Response Direction Error 0 = No error. 1 = The direction bit from card to host in the response has not been detected.  RCRCE: Response CRC Error 0 = No error. 1 = A CRC7 error has been detected in the response. Cleared when writing in the HSMCI_CMDR.  RENDE: Response End Bit Error 0 = No error. 1 = The end bit of the response has not been detected. Cleared when writing in the HSMCI_CMDR.  RTOE: Response Time-out Error 0 = No error. 1 = The response time-out set by MAXLAT in the HS MCI_CMDR has been exceeded. Cleared when writing in the HSMCI_CMDR.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 628 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12  DCRCE: Data CRC Error 0 = No error. 1 = A CRC16 error has been detected in the last data block. Cleared by reading in the HSMCI_SR register.  DTOE: Data Time-out Error 0 = No error. 1 = The data time-out set by DTOCYC and DTOMUL in HSMCI_DTOR has been exceeded. Cleared by reading in the HSMCI_SR register.  CSTOE: Completion Signal Time-out Error 0 = No error. 1 = The completion signal time-out set by CSTOCYC an d CSTOMUL in HSMCI_CSTOR has been exceeded. Cleared by reading in the HSMCI_SR register. Cleared by reading in the HSMCI_SR register.  BLKOVRE: DMA Block Overrun Error 0 = No error. 1 = A new block of data is received and the DMA controller has not started to move the current pending block, a block over- run is raised. Cleared by reading in the HSMCI_SR register.  DMADONE: DMA Transfer done 0 = DMA buffer transfer has not completed since the last read of HSMCI_SR register. 1 = DMA buffer transfer has completed.  FIFOEMPTY: FIFO empty flag 0 = FIFO contains at least one byte. 1 = FIFO is empty.  XFRDONE: Transfer Done flag 0 = A transfer is in progress. 1 = Command register is ready to operate and the data bus is in the idle state.  ACKRCV: Boot Operatio n Acknowledge Received 0 = No Boot acknowledge received since the last read of the status register. 1 = A Boot acknowledge signal has been received. Cleared by reading the HSMCI_SR register.  ACKRCVE: Boot Operation Acknowledge Error 0 = No error 1 = Corrupted Boot Acknowledge signal received.  OVRE: Overrun 0 = No error. 1 = At least one 8-bit received data has been lost (not read). Cleared when sending a new data transfer command. When FERRCTRL in HSMCI_CFG is set to 1, OVRE becomes reset after read.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 629 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12  UNRE: Underrun 0 = No error. 1 = At least one 8-bit data has been sent without valid information (not written). Cleared when sending a new data transfer command or when setting FERRCTRL in HSMCI_CFG to 1. When FERRCTRL in HSMCI_CFG is set to 1, UNRE becomes reset after read.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 630 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

35.14.13 HSMCI Interrupt Enable Register

Name: HSMCI_IER Address: 0xF0008044 Access: Write-only  CMDRDY: Command Ready Interrupt Enable  RXRDY: Receiver Ready Interrupt Enable  TXRDY: Transmit Ready Interrupt Enable  BLKE: Data Block Ended Interrupt Enable  DTIP: Data Transfer in Progress Interrupt Enable  NOTBUSY: Data Not Busy Interrupt Enable  SDIOIRQA: SDIO Interrupt for Slot A Interrupt Enable  SDIOIRQD: SDIO Interrupt for Slot D Interrupt Enable  SDIOWAIT: SDIO Read Wait Operation Status Interrupt Enable  CSRCV: Completion Signal Received Interrupt Enable  RINDE: Response Index Error Interrupt Enable  RDIRE: Response Direction Error Interrupt Enable  RCRCE: Response CRC Error Interrupt Enable  RENDE: Response End Bit Error Interrupt Enable  RTOE: Response Time-out Error Interrupt Enable  DCRCE: Data CRC Error Interrupt Enable  DTOE: Data Time-out Error Interrupt Enable  CSTOE: Completion Signal Timeout Error Interrupt Enable  BLKOVRE: DMA Block Overrun Error Interrupt Enable 31 30 29 28 27 26 25 24 UNRE OVRE ACKRCVE ACKRCV XFRDONE FIFOEMPTY DMADONE BLKOVRE 23 22 21 20 19 18 17 16 CSTOE DTOE DCRCE RTOE RENDE RCRCE RDIRE RINDE 15 14 13 12 11 10 9 8 – – CSRCV SDIOWAIT – – – SDIOIRQA 76543210 – – NOTBUSY DTIP BLKE TXRDY RXRDY CMDRDY

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 631 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12  DMADONE: DMA Transfer completed Interrupt Enable  FIFOEMPTY: FIFO empty Interrupt enable  XFRDONE: Transfer Done Interrupt enable  ACKRCV: Boot Acknowledge Interrupt Enable  ACKRCVE: Boot Acknowledge Error Interrupt Enable  OVRE: Overrun Interrupt Enable  UNRE: Underrun Interrupt Enable 0 = No effect. 1 = Enables the corresponding interrupt.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 632 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

35.14.14 HSMCI Interrupt Disable Register

Name: HSMCI_IDR Address: 0xF0008048 Access: Write-only  CMDRDY: Command Ready Interrupt Disable  RXRDY: Receiver Ready Interrupt Disable  TXRDY: Transmit Ready Interrupt Disable  BLKE: Data Block Ended Interrupt Disable  DTIP: Data Transfer in Progress Interrupt Disable  NOTBUSY: Data Not Busy Interrupt Disable  SDIOIRQA: SDIO Interrupt for Slot A Interrupt Disable  SDIOWAIT: SDIO Read Wait Operation Status Interrupt Disable  CSRCV: Completion Signal received interrupt Disable  RINDE: Response Index Error Interrupt Disable  RDIRE: Response Direction Error Interrupt Disable  RCRCE: Response CRC Error Interrupt Disable  RENDE: Response End Bit Error Interrupt Disable  RTOE: Response Time-out Error Interrupt Disable  DCRCE: Data CRC Error Interrupt Disable  DTOE: Data Time-out Error Interrupt Disable  CSTOE: Completion Signal Time out Error Interrupt Disable  BLKOVRE: DMA Block Overrun Error Interrupt Disable  DMADONE: DMA Transfer co mpleted Interrupt Disable 31 30 29 28 27 26 25 24 UNRE OVRE ACKRCVE ACKRCV XFRDONE FIFOEMPTY DMADONE BLKOVRE 23 22 21 20 19 18 17 16 CSTOE DTOE DCRCE RTOE RENDE RCRCE RDIRE RINDE 15 14 13 12 11 10 9 8 – – CSRCV SDIOWAIT – – – SDIOIRQA 76543210 – – NOTBUSY DTIP BLKE TXRDY RXRDY CMDRDY

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 633 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12  FIFOEMPTY: FIFO empty Interrupt Disable  XFRDONE: Transfer Done Interrupt Disable  ACKRCV: Boot Acknowledge Interrupt Disable  ACKRCVE: Boot Acknowledge Error Interrupt Disable  OVRE: Overrun Interrupt Disable  UNRE: Underrun In terrupt Disable 0 = No effect. 1 = Disables the corresponding interrupt.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 634 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

35.14.15 HSMCI Interrupt Mask Register

Name: HSMCI_IMR Address: 0xF000804C Access: Read-only  CMDRDY: Command Ready Interrupt Mask  RXRDY: Receiver Ready Interrupt Mask  TXRDY: Transmit Ready Interrupt Mask  BLKE: Data Block Ended Interrupt Mask  DTIP: Data Transfer in Progress Interrupt Mask  NOTBUSY: Data Not Busy Interrupt Mask  SDIOIRQA: SDIO Interrupt for Slot A Interrupt Mask  SDIOWAIT: SDIO Read Wait Operation Status Interrupt Mask  CSRCV: Completion Signal Received Interrupt Mask  RINDE: Response Index Error Interrupt Mask  RDIRE: Response Direction Error Interrupt Mask  RCRCE: Response CRC Error Interrupt Mask  RENDE: Response End Bit Error Interrupt Mask  RTOE: Response Time-out Error Interrupt Mask  DCRCE: Data CRC Error Interrupt Mask  DTOE: Data Time-out Error Interrupt Mask  CSTOE: Completion Signal Time-out Error Interrupt Mask  BLKOVRE: DMA Block Overrun Error Interrupt Mask  DMADONE: DMA Transfer Completed Interrupt Mask 31 30 29 28 27 26 25 24 UNRE OVRE ACKRCVE ACKRCV XFRDONE FIFOEMPTY DMADONE BLKOVRE 23 22 21 20 19 18 17 16 CSTOE DTOE DCRCE RTOE RENDE RCRCE RDIRE RINDE 15 14 13 12 11 10 9 8 – – CSRCV SDIOWAIT – – – SDIOIRQA 76543210 – – NOTBUSY DTIP BLKE TXRDY RXRDY CMDRDY

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 635 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12  FIFOEMPTY: FIFO Empty Interrupt Mask  XFRDONE: Transfer Done Interrupt Mask  ACKRCV: Boot Operation Acknow ledge Received Interrupt Mask  ACKRCVE: Boot Operation Acknowledge Error Interrupt Mask  OVRE: Overrun Interrupt Mask  UNRE: Underrun Interrupt Mask 0 = The corresponding interrupt is not enabled. 1 = The corresponding interrupt is enabled.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 636 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

35.14.16 HSMCI DMA Configuration Register

Name: HSMCI_DMA Address: 0xF0008050 Access: Read-write This register can only be written if the WPEN bit is cleared in “HSMCI Write Protect Mode Register” on page 638.  OFFSET: DMA Write Buffer Offset This field indicates the number of discarded bytes when the DMA writes the first word of the transfer.  CHKSIZE: DMA Channel Read and Write Chunk Size The CHKSIZE field indicates the number of data available when the DMA chunk transfer request is asserted.  DMAEN: DMA Hardware Handshaking Enable 0 = DMA interface is disabled. 1 = DMA Interface is enabled. Note: To avoid unpredictable behavior, DMA hardware handshak ing must be disabled when CPU transfers are performed.  ROPT: Read Optimization with padding 0: BLKLEN bytes are moved from the Memory Card to the system memory, two DMA descriptors are used when the trans- fer size is not a multiple of 4. 1: Ceiling(BLKLEN/4) * 4 bytes are moved from the Memory Card to the system memory, only one DMA descriptor is used. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 – – CHKSIZE – – OFFSET Value Name Description 00 1 1 data available 01 4 4 data available 10 8 8 data available 11 16 16 data available

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 637 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

35.14.17 HSMCI Configuration Register

Name: HSMCI_CFG Address: 0xF0008054 Access: Read-write This register can only be written if the WPEN bit is cleared in “HSMCI Write Protect Mode Register” on page 638.  FIFOMODE: HSMCI Internal FIFO control mode 0 = A write transfer starts when a sufficient amount of data is written into the FIFO. When the block length is greater than or equal to 3/4 of the HSMCI internal FIFO size, then the write transfer starts as soon as half the FIFO is filled. When the block length is greater than or equal to half the internal FIFO size, then the write transfer starts as soon as one quarter of the FIFO is filled. In other cases, the transfer starts as soon as the total amount of data is written in the internal FIFO. 1 = A write transfer starts as soon as one data is written into the FIFO.  FERRCTRL: Flow Error flag reset control mode 0= When an underflow/overflow condition flag is set, a new Write/Read command is needed to reset the flag. 1= When an underflow/overflow condition flag is set, a read status resets the flag.  HSMODE: High Speed Mode 0= Default bus timing mode. 1= If set to one, the host controller outputs command line and data lines on the rising edge of the card clock. The Host driver shall check the high speed support in the card registers.  LSYNC: Synchronize on the last block 0= The pending command is sent at the end of the current data block. 1= The pending command is sent at the end of the block transf er when the transfer length is not infinite. (block count shall be different from zero) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 638 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

35.14.18 HSMCI Write Protect Mode Register

Name: HSMCI_WPMR Address: 0xF00080E4 Access: Read-write  WP_EN: Write Protection Enable 0 = Disables the Write Protection if WP_KEY corresponds to 0x4D4349 (“MCI’ in ASCII). 1 = Enables the Write Protection if WP_KEY corresponds to 0x4D4349 (“MCI’ in ASCII).  WP_KEY: Write Protection Key password Should be written at value 0x4D4349 (ASCII code for “MCI”). Writing any other value in this field has no effect. Protects the registers:

  • “HSMCI Mode Register” on page 614
  • “HSMCI Data Timeout Register” on page 616
  • “HSMCI SDCard/SDIO Register” on page 617
  • “HSMCI Completion Signal Timeout Register” on page 623
  • “HSMCI DMA Configuration Register” on page 636
  • “HSMCI Configuration Register” on page 637 31 30 29 28 27 26 25 24 WP_KEY (0x4D => “M”) 23 22 21 20 19 18 17 16 WP_KEY (0x43 => C”) 15 14 13 12 11 10 9 8 WP_KEY (0x49 => “I”) 76543210 WP_EN

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 639 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

35.14.19 HSMCI Write Protect Status Register

Name: HSMCI_WPSR Address: 0xF00080E8 Access: Read-only  WP_VS: Write Protect ion Violation Status  WP_VSRC: Write Protection Violation SouRCe When WPVS is active, this field indicates the write-protected register (t hrough address offset or code) in which a write access has been attempted. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WP_VSRC 15 14 13 12 11 10 9 8 WP_VSRC 76543210 Value Name Description 0N ONE No Write Protection Violation occurred since the last read of this register (WP_SR) 1W RITE Write Protection detected unauthorized attempt to write a control register had occurred (since the last read.)

2 RESET Software reset had been performed while Write Protection was

enabled (since the last read). 3B OTH Both Write Protection violation and software reset with Write Protection enabled have occurred since the last read.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 640 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

35.14.20 HSMCI FIFOx Memory Aperture

Name: HSMCI_FIFOx[x=0..255] Address: 0xF0008200 Access: Read-write  DATA: Data to Read or Data to Write 31 30 29 28 27 26 25 24 DATA 23 22 21 20 19 18 17 16 DATA 15 14 13 12 11 10 9 8 DATA 76543210 DATA

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 641 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 36. Serial Peripheral Interface (SPI)

36.1 Description

The Serial Peripheral Interface (SPI) circuit is a synchronous serial data link that provides com- munication with external devices in Master or Slave Mode. It also enables communication between processors if an external processor is connected to the system. The Serial Peripheral Interface is essentially a shift register that serially transmits data bits to other SPIs. During a data transfer, one SPI system acts as the “master”' which controls the data flow, while the other devices act as “slaves'' whic h have data shifted into and out by the master. Different CPUs can take turn being masters (Multiple Master Protocol opposite to Single Master Protocol where one CPU is always the master while all of the others are always slaves) and one master may simultaneously shift data into multiple slaves. However, only one slave may drive its output to write data back to the master at any given time. A slave device is selected when the master asse rts its NSS signal. If multiple slave devices exist, the master generates a separate slave select signal for each slave (NPCS). The SPI system consists of two data lines and two control lines:

  • Master Out Slave In (MOSI): This data line supplies the output data from the master shifted into the input(s) of the slave(s).
  • Master In Slave Out (MISO): This data line supplies the output data from a slave to the input of the master. There may be no more than one slave transmitting data during any particular transfer.
  • Serial Clock (SPCK): This control line is driven by the master and regulates the flow of the data bits. The master may transmit data at a variety of baud rates; the SPCK line cycles once for each bit that is transmitted.
  • Slave Select (NSS): This control line allows slaves to be turned on and off by hardware.

36.2 Embedded Characteristics

  • Compatible with an Embedded 32-bit Microcontroller
  • Supports Communication with Serial External Devices – Four Chip Selects with External Decoder Support Allow Communication with Up to

15 Peripherals

– Serial Memories, such as DataFlash and 3-wire EEPROMs – Serial Peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and Sensors – External Co-processors

  • Master or Slave Serial Peripheral Bus Interface – 8- to 16-bit Programmable Data Length Per Chip Select – Programmable Phase and Polarity Per Chip Select – Programmable Transfer Delays Between Consecutive Transfers and Between Clock and Data Per Chip Select – Programmable Delay Between Consecutive Transfers – Selectable Mode Fault Detection
  • Connection to DMA Channel Capab ilities Optimizes Data Transfers – One channel for the Receiver, One Channel for the Transmitter

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36.3 Block Diagram

Figure 36-1. Block Diagram SPI Interface Interrupt Control PIO Peripheral Bridge DMA Ch.AHB Matrix PMC MCK SPI Interrupt SPCK MISO MOSI NPCS0/NSS NPCS1 NPCS2 NPCS3 APB

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36.4 Application Block Diagram

Figure 36-2. Application Block Diagram: Single Master/Multiple Slave Implementation

36.5 Signal Description

Table 36-1. Signal Description Pin Name Pin Description Type Master Slave MISO Master In Slave Out Input Output MOSI Master Out Slave In Output Input SPCK Serial Clock Output Input NPCS1-NPCS3 Peripheral Chip Selects Output Unused NPCS0/NSS Peripheral Chip Select/Slave Select Output Input SPI Master SPCK MISO MOSI NPCS0 NPCS1 NPCS2 SPCK MISO MOSI NSS Slave 0 SPCK MISO MOSI NSS Slave 1 SPCK MISO MOSI NSS Slave 2 NC NPCS3

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36.6 Product Dependencies

36.6.1 I/O Lines

The pins used for interfacing the compliant ex ternal devices may be multiplexed with PIO lines. The programmer must first program the PIO controllers to assign the SPI pins to their peripheral functions.

36.6.2 Power Management

The SPI may be clocked through the Power Management Controller (PMC), thus the program- mer must first configure the PMC to enable the SPI clock.

36.6.3 Interrupt

The SPI interface has an interrupt line connected to the Interrupt Controller. Handling the SPI interrupt requires programming the interrupt controller before configuring the SPI. Table 36-2. I/O Lines Instance Signal I/O Line Peripheral SPI0 SPI0_MISO PA11 A SPI0 SPI0_MOSI PA12 A SPI0 SPI0_NPCS0 PA14 A SPI0 SPI0_NPCS1 PA7 B SPI0 SPI0_NPCS2 PA1 B SPI0 SPI0_NPCS3 PB3 B SPI0 SPI0_SPCK PA13 A SPI1 SPI1_MISO PA21 B SPI1 SPI1_MOSI PA22 B SPI1 SPI1_NPCS0 PA8 B SPI1 SPI1_NPCS1 PA0 B SPI1 SPI1_NPCS2 PA31 B SPI1 SPI1_NPCS3 PA30 B SPI1 SPI1_SPCK PA23 B Table 36-3. Peripheral IDs Instance ID SPI0 13 SPI1 14

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36.7 Functional Description

36.7.1 Modes of Operation

The SPI operates in Master Mode or in Slave Mode. Operation in Master Mode is programmed by writing at 1 the MSTR bit in the Mode Register. The pins NPCS0 to NPCS3 are all configured as outputs, the SPCK pin is driven, the MISO line is wired on the receiver input and the MOSI line driven as an output by the transmitter. If the MSTR bit is written at 0, the SPI operates in Slave Mode. The MISO line is driven by the transmitter output, the MOSI line is wired on the re ceiver input, the SPCK pin is driven by the transmitter to synchronize the receiver. The NPCS0 pin becomes an input, and is used as a Slave Select signal (NSS). The pins NPCS1 to NPCS3 are not driven and can be used for other purposes. The data transfers are identically programmable for both modes of operations. The baud rate generator is activated only in Master Mode.

36.7.2 Data Transfer

Four combinations of polarity and phase are available for data transfers. The clock polarity is programmed with the CPOL bit in the Chip Select Register. The clock phase is programmed with the NCPHA bit. These two parameters determine the edges of the clock signal on which data is driven and sampled. Each of the two parameters has two possible states, resulting in four possi- ble combinations that are incompatible with one another. Thus, a master/slave pair must use the same parameter pair values to communicate. If multiple slaves are used and fixed in different configurations, the master must reconfigure itself each time it needs to communicate with a dif- ferent slave. Table 36-4 shows the four modes and corresponding parameter settings. Figure 36-3 and Figure 36-4 show examples of data transfers. Table 36-4. SPI Bus Protocol Mode SPI Mode CPOL NCPHA Shift SPCK Edge Capt ure SPCK Edge SPCK Inactive Level 0 0 1 Falling Rising Low 1 0 0 Rising Falling Low 2 1 1 Rising Falling High 3 1 0 Falling Rising High

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36.7.3 Master Mode Operations

When configured in Master Mode, the SPI operates on the clock generated by the internal pro- grammable baud rate generator. It fully controls the data transfers to and from the slave(s) connected to the SPI bus. The SPI drives the chip select line to the slave and the serial clock signal (SPCK). The SPI features two holding registers, the Transmit Data Register and the Receive Data Regis- ter, and a single Shift Register. The holding registers maintain the data flow at a constant rate. After enabling the SPI, a data transfer begins when the processor writes to the SPI_TDR (Trans- mit Data Register). The written data is immediat ely transferred in the Shift Register and transfer on the SPI bus starts. While the data in the Shift Register is shifted on the MOSI line, the MISO line is sampled and shifted in the Shift Register. Receiving data cannot occur without transmit- ting data. If receiving mode is not needed, for example when communicating with a slave receiver only (such as an LCD), the receive status flags in the status register can be discarded. Before writing the TDR, the PCS field in the SPI_MR register must be set in order to select a slave. After enabling the SPI, a data transfer begins when the processor writes to the SPI_TDR (Trans- mit Data Register). The written data is immediat ely transferred in the Shift Register and transfer on the SPI bus starts. While the data in the Shift Register is shifted on the MOSI line, the MISO line is sampled and shifted in the Shift Register. Transmission cannot occur without reception. Before writing the TDR, the PCS field must be set in order to select a slave. If new data is written in SPI_TDR during the transfer, it stays in it until the current transfer is completed. Then, the received data is transferred from the Shift Register to SPI_RDR, the data in SPI_TDR is loaded in the Shift Register and a new transfer starts. The transfer of a data written in SPI_TDR in the Shift Register is indicated by the TDRE bit (Transmit Data Register Empty) in the Status Register (SPI_SR). When new data is written in SPI_TDR, this bit is cleared. The TDRE bit is used to trigger the Transmit DMA channel. The end of transfer is indicated by the TXEMPTY flag in the SPI_SR register. If a transfer delay (DLYBCT) is greater than 0 for the last transfer, TXEMPTY is set after the completion of said delay. The master clock (MCK) can be switched off at this time. The transfer of received data from the Shift Register in SPI_RDR is indicated by the RDRF bit (Receive Data Register Full) in the Status Register (SPI_SR). When the received data is read, the RDRF bit is cleared. If the SPI_RDR (Receive Data Register) has not been read before new data is received, the Overrun Error bit (OVRES) in SPI_SR is set. As long as this flag is set, data is loaded in SPI_RDR. The user has to read the status register to clear the OVRES bit. Figure 36-5, shows a block diagram of the SPI when operating in Master Mode. Figure 36-6 on page 649 shows a flow chart describing how transfers are handled.

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36.7.3.1 Master Mode Block Diagram

Figure 36-5. Master Mode Block Diagram Shift Register SPCK MOSILSB MSBMISO SPI_RDR RD SPI Clock TDRE SPI_TDR TD RDRF OVRES SPI_CSR0..3 CPOL NCPHA BITS MCK Baud Rate Generator SPI_CSR0..3 SCBR NPCS3 NPCS0 NPCS2 NPCS1 NPCS0 PS SPI_MR PCS SPI_TDR PCS MODF Current Peripheral SPI_RDR PCS SPI_CSR0..3 CSAAT PCSDEC MODFDIS MSTR

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36.7.3.2 Master Mode Flow Diagram

Figure 36-6. Master Mode Flow Diagram SPI Enable CSAAT ? PS ? NPCS = SPI_TDR(PCS) NPCS = SPI_MR(PCS) Delay DLYBS Serializer = SPI_TDR(TD) TDRE = 1 Data Transfer SPI_RDR(RD) = Serializer RDRF = 1 TDRE ? NPCS = 0xF Delay DLYBCS Fixed peripheral Variable peripheral Delay DLYBCT CSAAT ? TDRE ? PS ? SPI_TDR(PCS) = NPCS ? no yes SPI_MR(PCS) = NPCS ? no NPCS = 0xF Delay DLYBCS NPCS = SPI_TDR(PCS) NPCS = 0xF Delay DLYBCS NPCS = SPI_MR(PCS), SPI_TDR(PCS) Fixed peripheral Variable peripheral - NPCS defines the current Chip Select - CSAAT, DLYBS, DLYBCT refer to the fields of the Chip Select Register corresponding to the Current Chip Select - When NPCS is 0xF, CSAAT is 0.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 650 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Figure 36-7 shows Transmit Data Register Empty (TDRE), Receive Data Register (RDRF) and Transmission Register Empty (TXEMPTY) status flags behavior within the SPI_SR (Status Reg- ister) during an 8-bit data transfer in fixed mode and no Peripheral Data Controller involved. Figure 36-7. Status Register Flags Behavior

36.7.3.3 Clock Generation

The SPI Baud rate clock is generated by dividing the Master Clock (MCK), by a value between 1 and 255. This allows a maximum operating baud rate at up to Master Clock and a minimum operating baud rate of MCK divided by 255. Programming the SCBR field at 0 is forbidden. Triggering a transfer while SCBR is at 0 can lead to unpredictable results. At reset, SCBR is 0 and the user has to program it at a valid value before performing the first transfer. The divisor can be defined independently for each chip select, as it has to be programmed in the SCBR field of the Chip Select Registers. This allows the SPI to automatically adapt the baud rate for each interfaced peripheral without reprogramming.

36.7.3.4 Transfer Delays

Figure 36-8 shows a chip select transfer change and consecutive transfers on the same chip select. Three delays can be programmed to modify the transfer waveforms:

  • The delay between chip selects, programmable only once for all the chip selects by writing the DL YBCS field in the Mode Register. Allows insertion of a delay between release of one chip select and before assertion of a new one. SPCK MOSI (from master) MISO (from slave) NPCS0 MSB MSB LSB LSB 1 2345 786 RDRF TDRE TXEMPTY Write in SPI_TDR RDR read shift register empty

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  • The delay before SPCK, independently programmable for each chip select by writing the field DL YBS. Allows the start of SPCK to be delayed after the chip select has been asserted.
  • The delay between consecutive transfers, independently programmable for each chip select by writing the DL YBCT field. Allows insertion of a delay between two transfers occurring on the same chip select These delays allow the SPI to be adapted to the interfaced peripherals and their speed and bus release time. Figure 36-8. Programmable Delays

36.7.3.5 Peripheral Selection

The serial peripherals are selected through the assertion of the NPCS0 to NPCS3 signals. By default, all the NPCS signals are high before and after each transfer.

  • Fixed Peripheral Select: SPI exchanges data with only one peripheral Fixed Peripheral Select is activated by writing the PS bit to zero in SPI_MR (Mode Register). In this case, the current peripheral is defined by the PCS field in SPI_MR and the PCS field in the SPI_TDR has no effect.
  • Variable Peripheral Select: Data can be exchanged with more than one peripheral without having to reprogram the NPCS field in the SPI_MR register. Variable Peripheral Select is activated by se tting PS bit to one. The PCS field in SPI_TDR is used to select the current peripheral. This means that the peripheral selection can be defined for each new data. The value to write in the SPI_TDR register as the following format. [xxxxxxx(7-bit) + LASTXFER(1-bit) (1)+ xxxx(4-bit) + PCS (4-bit) + DATA (8 to 16-bit)] with PCS equals to the chip select to assert as defined in Section 36.8.4 (SPI Transmit Data Register) and LASTXFER bit at 0 or 1 depending on CSAAT bit. Note: 1. Optional. CSAAT, LASTXFER and CSNAAT bits are discussed in Section 36.7.3.9 ”Peripheral Deselec- tion with DMAC” . If LASTXFER is used, the command must be issued before writing the last character. Instead of LASTXFER, the user can use the SPIDIS command. After the end of the DMA transfer, wait for the TXEMPTY flag, then write SPIDIS into the SPI_CR register (this will not change the configu- ration register values); the NP CS will be deactivated after the last character transfer. Then, another DMA transfer can be started if the SPIEN was previously written in the SPI_CR register. DLYBCS DLYBS DLYBCT DLYBCT Chip Select 1 Chip Select 2 SPCK

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36.7.3.6 SPI Direct Access Memory Controller (DMAC)

In both fixed and variable mode the Direct Memory Access Controller (DMAC) can be used to reduce processor overhead. The Fixed Peripheral Selection allows buffer transfers with a single peripheral. Using the DMAC is an optimal means, as the size of the data transfer between the memory and the SPI is either 8 bits or 16 bits. However, changing the peripheral selection requires the Mode Register to be reprogrammed. The Variable Peripheral Selection allows buffer transfers with multiple peripherals without repro- gramming the Mode Register. Data written in SPI_TDR is 32 bits wide and defines the real data to be transmitted and the peripheral it is destined to. Using the DMAC in this mode requires 32- bit wide buffers, with the data in the LSBs and the PCS and LASTXFER fields in the MSBs, how- ever the SPI still controls the number of bits (8 to16) to be transferred through MISO and MOSI lines with the chip select configuration registers. This is not the optimal means in term of mem- ory size for the buffers, but it provides a very effective means to exchange data with several peripherals without any intervention of the processor.

36.7.3.7 Peripheral Chip Select Decoding

The user can program the SPI to operate with up to 15 peripherals by decoding the four Chip Select lines, NPCS0 to NPCS3 with 1 of up to 16 decoder/demultiplexer. This can be enabled by writing the PCSDEC bit at 1 in the Mode Register (SPI_MR). When operating without decoding, the SPI makes sure that in any case only one chip select line is activated, i.e., one NPCS line driven low at a time. If two bits are defined low in a PCS field, only the lowest numbered chip select is driven low. When operating with decoding, the SPI directly outputs the value defined by the PCS field on NPCS lines of either the Mode Register or the Transmit Data Register (depending on PS). As the SPI sets a default value of 0xF on the chip select lines (i.e. all chip select lines at 1) when not processing any transfer, only 15 peripherals can be decoded. The SPI has only four Chip Select Registers, not 15. As a result, when decoding is activated, each chip select defines the characteristics of up to four peripherals. As an example, SPI_CRS0 defines the characteristics of the externally decoded peripherals 0 to 3, corresponding to the PCS values 0x0 to 0x3. Thus, the user has to make sure to connect compatible peripherals on the decoded chip select lines 0 to 3, 4 to 7, 8 to 11 and 12 to 14. Figure 36-9 below shows such an implementation. If the CSAAT bit is used, with or without the DMAC, the Mode Fault detection for NPCS0 line must be disabled. This is not needed for all other chip select lines since Mode Fault Detection is only on NPCS0.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 653 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Figure 36-9. Chip Select Decoding Application Block Diagram: Single Master/Multiple Slave Implementation

36.7.3.8 Peripheral Deselection without DMAC

During a transfer of more than one data on a Chip Select without the DMAC, the SPI_TDR is loaded by the processor, the flag TDRE rises as soon as the content of the SPI_TDR is trans- ferred into the internal shift register. When this flag is detected high, the SPI_TDR can be reloaded. If this reload by the processor occurs before the end of the current transfer and if the next transfer is performed on the same chip select as the current transfer, the Chip Select is not de-asserted between the two transfers. But depending on the application software handling the SPI status register flags (by interrupt or polli ng method) or servicing other interrupts or other tasks, the processor may not reload the SPI_TDR in time to keep the chip select active (low). A null Delay Between Consecutive Transfer (DLYBC T) value in the SPI_CSR register, will give even less time for the processor to reload t he SPI_TDR. With some SPI slave peripherals, requiring the chip select line to remain active (low) during a full set of transfers might lead to communication errors. To facilitate interfacing with such devices, the Chip Select Register [CSR0...CSR3] can be pro- grammed with the CSAAT bit (Chip Select Active After Transfer) at 1. This allows the chip select lines to remain in their current state (low = active) until transfer to another chip select is required. Even if the SPI_TDR is not reloa ded the chip select will remain active. To have the chip select line to raise at the end of the transfer the Last transfer Bit (LASTXFER) in the SPI_MR register must be set at 1 before writing the last data to transmit into the SPI_TDR.

36.7.3.9 Peripheral Deselection with DMAC

When the Direct Memory Access Controller is used, the chip select line will remain low during the whole transfer since the TDRE flag is managed by the DMAC itself. The reloading of the SPI_TDR by the DMAC is done as soon as TDRE flag is set to one. In this case the use of CSAAT bit might not be needed. However, it may happen that when other DMAC channels con- SPI Master SPCK MISO MOSI NPCS0 NPCS1 NPCS2 SPCK 1-of-n Decoder/Demultiplexer MISO MOSI NSS Slave 0 SPCK MISO MOSI NSS Slave 1 SPCK MISO MOSI NSS Slave 14 NPCS3

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 654 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 nected to other peripherals are in use as well, the SPI DMAC might be delayed by another (DMAC with a higher priority on the bus). Having DMAC buffers in slower memories like flash memory or SDRAM compared to fast internal SRAM, may lengthen the reload time of the SPI_TDR by the DMAC as well. This means that the SPI_TDR might not be reloaded in time to keep the chip select line low. In this case the chip select line may toggle between data transfer and according to some SPI Slave devices, the communication might get lost. The use of the CSAAT bit might be needed. When the CSAAT bit is set at 0, the NPCS does not rise in all cases between two transfers on the same peripheral. During a transfer on a Chip Select, the flag TDRE rises as soon as the con- tent of the SPI_TDR is transferred into the internal shifter. When this flag is detected the SPI_TDR can be reloaded. If this reload occurs before the end of the current transfer and if the next transfer is performed on the same chip select as the current transfer, the Chip Select is not de-asserted between the two transfers. This migh t lead to difficulties fo r interfacing with some serial peripherals requiring the chip select to be de-asserted after each transfer. To facilitate interfacing with such devices, the Chip Select Register can be programmed with the CSNAAT bit (Chip Select Not Active After Transfer) at 1. This allows to de-assert systematically the chip select lines during a time DLYBCS. (The value of the CSNAAT bit is taken into account only if the CSAAT bit is set at 0 for the same Chip Select). Figure 36-10 shows different peripheral deselection cases and the effect of the CSAAT and CSNAAT bits.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 655 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Figure 36-10. Peripheral Deselection

36.7.3.10 Mode Fault Detection

A mode fault is detected when the SPI is programmed in Master Mode and a low level is driven by an external master on the NPCS0/NSS signal. In this case, multi-master configuration, NPCS0, MOSI, MISO and SPCK pins must be configured in open drain (through the PIO control- ler). When a mode fault is detected, the MODF bit in the SPI_SR is set until the SPI_SR is read A NPCS[0..3] Write SPI_TDR TDRE NPCS[0..3] Write SPI_TDR TDRE NPCS[0..3] Write SPI_TDR TDRE DLYBCS PCS = A DLYBCS DLYBCT A PCS = B B DLYBCS PCS = A DLYBCS DLYBCT A PCS = B B DLYBCS DLYBCT PCS=A A DLYBCS DLYBCT A PCS = A AA DLYBCT AA CSAAT = 0 and CSNAAT = 0 DLYBCT AA CSAAT = 1 and CSNAAT= 0 / 1 A DLYBCS PCS = A DLYBCT AA CSAAT = 0 and CSNAAT = 1 NPCS[0..3] Write SPI_TDR TDRE PCS = A DLYBCT AA CSAAT = 0 and CSNAAT = 0

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 656 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 and the SPI is automatically disabled until re-enabled by writing the SPIEN bit in the SPI_CR (Control Register) at 1. By default, the Mode Fault detection circuitr y is enabled. The user can disable Mode Fault detection by setting the MODFDIS bit in the SPI Mode Register (SPI_MR).

36.7.4 SPI Slave Mode

When operating in Slave Mode, the SPI processes data bits on the clock provided on the SPI clock pin (SPCK). The SPI waits for NSS to go active before receiving the serial clock from an external master. When NSS falls, the clock is validated on the serializer, which processes the number of bits defined by the BITS field of the Chip Select Register 0 (SPI_CSR0). These bits are processed following a phase and a polarity defined respectively by the NCPHA and CPOL bits of the SPI_CSR0. Note that BITS, CPOL and NCPHA of the other Chip Select Registers have no effect when the SPI is programmed in Slave Mode. The bits are shifted out on the MISO line and sampled on the MOSI line. (For more information on BITS field, see also, the (Note:) below the register table; Section 36.8.9 “SPI Chip Select Register” on page 669.) When all the bits are processed, the received data is transferred in the Receive Data Register and the RDRF bit rises. If the SPI_RDR (Receive Data Register) has not been read before new data is received, the Overrun Error bit (OVRES) in SPI_SR is set. As long as this flag is set, data is loaded in SPI_RDR. The user has to read the status register to clear the OVRES bit. When a transfer starts, the data shifted out is the data present in the Shift Register. If no data has been written in the Transmit Data Register (SPI_TDR), the last data received is transferred. If no data has been received since the last reset, all bits are transmitted low, as the Shift Regis- ter resets at 0. When a first data is written in SPI_TDR, it is transferred immediately in the Shift Register and the TDRE bit rises. If new data is written, it remains in SPI_TDR until a transfer occurs, i.e. NSS falls and there is a valid clock on the SPCK pin. W hen the transfer occurs, the last data written in SPI_TDR is transferred in the Shift Register and the TDRE bit rises. This enables frequent updates of critical variables with single transfers. Then, a new data is loaded in the Shift Register from the Transmit Data Register. In case no character is ready to be transmitted, i.e. no character has been written in SPI_TDR since the last load from SPI_TDR to the Shift Register, the Shift Register is not modified and the last received character is retransmitted. Figure 36-11 shows a block diagram of the SPI when operating in Slave Mode.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 657 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Figure 36-11. Slave Mode Functional Bloc Diagram Shift Register SPCK SPIENS LSB MSB NSS MOSI SPI_RDR RD SPI Clock TDRE SPI_TDR TD RDRF OVRES SPI_CSR0 CPOL NCPHA BITS SPIEN SPIDIS MISO

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36.7.5 Write Protected Registers

To prevent any single software error that may corrupt SPI behavior, the registers listed below can be write-protected by setting the SPIWPEN bit in the SPI Write Protection Mode Register (SPI_WPMR). If a write access in a write-pr otected register is detected, then the SPIWPVS flag in the SPI Write Protection Status Register (SPI_WPSR) is set and the field SPIWPVSRC indicates in which register the write access has been attempted. The SPIWPVS flag is automatically reset after reading the SPI Wr ite Protection Status Register (SPI_WPSR). List of the write-protected registers: Section 36.8.2 ”SPI Mode Register” Section 36.8.9 ”SPI Chip Select Register”

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36.8 Serial Peripheral Inte rface (SPI) User Interface

Table 36-5. Register Mapping Offset Register Name Access Reset 0x00 Control Register SPI_CR Write-only --- 0x04 Mode Register SPI_MR Read-write 0x0 0x08 Receive Data Register SPI_RDR Read-only 0x0 0x0C Transmit Data Register SPI_TDR Write-only --- 0x10 Status Register SPI_SR Read-only 0x000000F0 0x14 Interrupt Enable Register SPI_IER Write-only --- 0x18 Interrupt Disable Register SPI_IDR Write-only --- 0x1C Interrupt Mask Register SPI_IMR Read-only 0x0 0x20 - 0x2C Reserved 0x30 Chip Select Register 0 SPI_CSR0 Read-write 0x0 0x34 Chip Select Register 1 SPI_CSR1 Read-write 0x0 0x38 Chip Select Register 2 SPI_CSR2 Read-write 0x0 0x3C Chip Select Register 3 SPI_CSR3 Read-write 0x0 0x4C - 0xE0 Reserved – – – 0xE4 Write Protection Control Register SPI_WPMR Read-write 0x0 0xE8 Write Protection Status Register SPI_WPSR Read-only 0x0 0x00E8 - 0x00F8 Reserved – – – 0x00FC Reserved – – –

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36.8.1 SPI Control Register

Name: SPI_CR Address: 0xF0000000 (0), 0xF0004000 (1) Access: Write-only  SPIEN: SPI Enable 0 = No effect. 1 = Enables the SPI to transfer and receive data.  SPIDIS: SPI Disable 0 = No effect. 1 = Disables the SPI. As soon as SPIDIS is set, SPI finishes its transfer. All pins are set in input mode and no data is received or transmitted. If a transfer is in progress, the transfer is finished before the SPI is disabled. If both SPIEN and SPIDIS are equal to one when the control register is written, the SPI is disabled.  SWRST: SPI Software Reset 0 = No effect. 1 = Reset the SPI. A software-triggered hardware reset of the SPI interface is performed. The SPI is in slave mode after software reset. DMAC channels are not affected by software reset.  LASTXFER: Last Transfer 0 = No effect. 1 = The current NPCS will be deasserted afte r the character written in TD has been transferred. When CSAAT is set, this allows to close the communication with the current serial peripheral by raising the corresponding NPCS line as soon as TD transfer has completed. Refer to Section 36.7.3.5 ”Peripheral Selection” for more details. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 SWRST ––––– S PIDIS S PIEN

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 661 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

36.8.2 SPI Mode Register

Name: SPI_MR Address: 0xF0000004 (0), 0xF0004004 (1) Access: Read-write  MSTR: Master/Slave Mode 0 = SPI is in Slave mode. 1 = SPI is in Master mode.  PS: Peripheral Select 0 = Fixed Peripheral Select. 1 = Variable Peripheral Select.  PCSDEC: Chip Select Decode 0 = The chip selects are directly connected to a peripheral device. 1 = The four chip select lines are connected to a 4- to 16-bit decoder. When PCSDEC equals one, up to 15 Chip Select signals can be generated with the four lines using an external 4- to 16-bit decoder. The Chip Select Registers define the characteristics of the 15 chip selects according to the following rules: SPI_CSR0 defines peripheral chip select signals 0 to 3. SPI_CSR1 defines peripheral chip select signals 4 to 7. SPI_CSR2 defines peripheral chip select signals 8 to 11. SPI_CSR3 defines peripheral chip select signals 12 to 14.  MODFDIS: Mode Fault Detection 0 = Mode fault detection is enabled. 1 = Mode fault detection is disabled.  WDRBT: Wait Data Read Before Transfer 0 = No Effect. In master mode, a transfer can be initiated whatever the state of the Receive Data Register is. 1 = In Master Mode, a transfer can start only if the Receive Data Register is empty, i.e. does not contain any unread data. This mode prevents overrun error in reception. 31 30 29 28 27 26 25 24 DL YBCS 23 22 21 20 19 18 17 16 –––– PCS 15 14 13 12 11 10 9 8 76543210 LLB – WDRBT MODFDIS – PCSDEC PS MSTR

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 662 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12  LLB: Local Loopback Enable 0 = Local loopback path disabled. 1 = Local loopback path enabled LLB controls the local loopback on the data serializer for te sting in Master Mode only. (MISO is internally connected on MOSI.)  PCS: Peripheral Chip Select This field is only used if Fixed Peripheral Select is active (PS = 0). If PCSDEC = 0: PCS = xxx0 NPCS[3:0] = 1110 PCS = xx01 NPCS[3:0] = 1101 PCS = x011 NPCS[3:0] = 1011 PCS = 0111 NPCS[3:0] = 0111 PCS = 1111 forbidden (no peripheral is selected) (x = don’t care) If PCSDEC = 1: NPCS[3:0] output signals = PCS.  DLYBCS: Delay Between Chip Selects This field defines the delay from NPCS inactive to the activation of another NPCS. The DLYBCS time guarantees non-over- lapping chip selects and solves bus contentions in case of peripherals having long data float times. If DLYBCS is less than or equal to six, six MCK periods will be inserted by default. Otherwise, the following equation determines the delay: Delay Between Chip Selects DLYBCS

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 663 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

36.8.3 SPI Receive Data Register

Name: SPI_RDR Address: 0xF0000008 (0), 0xF0004008 (1) Access: Read-only  RD: Receive Data Data received by the SPI Interface is stored in this register right-justified. Unused bits read zero.  PCS: Peripheral Chip Select In Master Mode only, these bits indicate the value on the NPCS pins at the end of a transfer. Otherwise, these bits read zero. Note: When using variable peripheral select mode (PS = 1 in SPI_MR) it is mandatory to also set the WDRBT field to 1 if the SPI_RDR PCS field is to be processed. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 –––– PCS 15 14 13 12 11 10 9 8 RD 76543210 RD

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 664 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

36.8.4 SPI Transmit Data Register

Name: SPI_TDR Address: 0xF000000C (0), 0xF000400C (1) Access: Write-only  TD: Transmit Data Data to be transmitted by the SPI Interface is stored in this register. Information to be transmitted must be written to the transmit data register in a right-justified format.  PCS: Peripheral Chip Select This field is only used if Variable Peripheral Select is active (PS = 1). If PCSDEC = 0: PCS = xxx0 NPCS[3:0] = 1110 PCS = xx01 NPCS[3:0] = 1101 PCS = x011 NPCS[3:0] = 1011 PCS = 0111 NPCS[3:0] = 0111 PCS = 1111 forbidden (no peripheral is selected) (x = don’t care) If PCSDEC = 1: NPCS[3:0] output signals = PCS  LASTXFER: Last Transfer 0 = No effect. 1 = The current NPCS will be deasserted afte r the character written in TD has been transferred. When CSAAT is set, this allows to close the communication with the current serial peripheral by raising the corresponding NPCS line as soon as TD transfer has completed. This field is only used if Variable Peripheral Select is active (PS = 1). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 –––– PCS 15 14 13 12 11 10 9 8 TD 76543210 TD

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 665 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

36.8.5 SPI Status Register

Name: SPI_SR Address: 0xF0000010 (0), 0xF0004010 (1) Access: Read-only  RDRF: Receive Data Register Full 0 = No data has been received since the last read of SPI_RDR 1 = Data has been received and the received data has been transferred from the serializer to SPI_RDR since the last read of SPI_RDR.  TDRE: Transmit Data Register Empty 0 = Data has been written to SPI_TDR and not yet transferred to the serializer. 1 = The last data written in the Transmit Data Register has been transferred to the serializer. TDRE equals zero when the SPI is disabled or at reset. The SPI enable command sets this bit to one.  MODF: Mode Fault Error 0 = No Mode Fault has been detected since the last read of SPI_SR. 1 = A Mode Fault occurred since the last read of the SPI_SR.  OVRES: Overrun Error Status 0 = No overrun has been detected since the last read of SPI_SR. 1 = An overrun has occurred since the last read of SPI_SR. An overrun occurs when SPI_RDR is loaded at least twice from the serializer since the last read of the SPI_RDR.  NSSR: NSS Rising 0 = No rising edge detected on NSS pin since last read. 1 = A rising edge occurred on NSS pin since last read.  TXEMPTY: Transmission Registers Empty 0 = As soon as data is written in SPI_TDR. 1 = SPI_TDR and internal shifter are empty. If a transfer delay has been defined, TXEMPTY is set after the completion of such delay.  SPIENS: SPI Enable Status 0 = SPI is disabled. 1 = SPI is enabled. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 –––– O VRES M ODF T DRE RDRF

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 666 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

36.8.6 SPI Interrupt Enable Register

Name: SPI_IER Address: 0xF0000014 (0), 0xF0004014 (1) Access: Write-only 0 = No effect. 1 = Enables the corresponding interrupt.  RDRF: Receive Data Register Full Interrupt Enable  TDRE: SPI Transmit Data Regi ster Empty Interrupt Enable  MODF: Mode Fault Error Interrupt Enable  OVRES: Overrun Error Interrupt Enable  NSSR: NSS Rising Interrupt Enable  TXEMPTY: Transmission Registers Empty Enable 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 –––– O VRES M ODF T DRE RDRF

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36.8.7 SPI Interrupt Disable Register

Name: SPI_IDR Address: 0xF0000018 (0), 0xF0004018 (1) Access: Write-only 0 = No effect. 1 = Disables the corresponding interrupt.  RDRF: Receive Data Register Full Interrupt Disable  TDRE: SPI Transmit Data Register Empty Interrupt Disable  MODF: Mode Fault Error Interrupt Disable  OVRES: Overrun Error Interrupt Disable  NSSR: NSS Rising Interrupt Disable  TXEMPTY: Transmission Registers Empty Disable 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 –––– O VRES M ODF T DRE RDRF

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 668 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

36.8.8 SPI Interrupt Mask Register

Name: SPI_IMR Address: 0xF000001C (0), 0xF000401C (1) Access: Read-only 0 = The corresponding interrupt is not enabled. 1 = The corresponding interrupt is enabled.  RDRF: Receive Data Register Full Interrupt Mask  TDRE: SPI Transmit Data Register Empty Interrupt Mask  MODF: Mode Fault Error Interrupt Mask  OVRES: Overrun Error Interrupt Mask  NSSR: NSS Rising Interrupt Mask  TXEMPTY: Transmission Registers Empty Mask 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 –––– O VRES M ODF T DRE RDRF

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 669 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

36.8.9 SPI Chip Select Register

Name: SPI_CSRx[x=0..3] Address: 0xF0000030 (0), 0xF0004030 (1) Access: Read/Write Note: SPI_CSRx registers must be written even if the user wants to use the defaults. The BITS field will not be updated with the trans- lated value unless the register is written.  CPOL: Clock Polarity 0 = The inactive state value of SPCK is logic level zero. 1 = The inactive state value of SPCK is logic level one. CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce the required clock/data relationship between master and slave devices.  NCPHA: Clock Phase 0 = Data is changed on the leading edge of SPCK and captured on the following edge of SPCK. 1 = Data is captured on the leading edge of SPCK and changed on the following edge of SPCK. NCPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. NCPHA is used with CPOL to produce the required clock/data relationship between master and slave devices.  CSNAAT: Chip Select Not Active Af ter Transfer (Ignored if CSAAT = 1) 0 = The Peripheral Chip Select does not rise between two transfers if the SPI_TDR is reloaded before the end of the first transfer and if the two transfers occur on the same Chip Select. 1 = The Peripheral Chip Select rises systematically after each transfer performed on the same slave. It remains active after the end of transfer for a minimal duration of: – (if DL YBCT field is different from 0) – (if DL YBCT field equals 0)  CSAAT: Chip Select Active After Transfer 0 = The Peripheral Chip Select Line rises as soon as the last transfer is achieved. 1 = The Peripheral Chip Select does not rise after the last transfer is achieved. It remains active until a new transfer is requested on a different chip select. 31 30 29 28 27 26 25 24 DL YBCT 23 22 21 20 19 18 17 16 DL YBS 15 14 13 12 11 10 9 8 SCBR 76543210 BITS CSAAT CSNAAT NCPHA CPOL DLYBCT DLYBCT 1+

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 670 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12  BITS: Bits Per Transfer (See the (Note:) below the register table; Section 36.8.9 “SPI Chip Select Register” on page 669.) The BITS field determines the number of data bits transferred. Reserved values should not be used.  SCBR: Serial Clock Baud Rate In Master Mode, the SPI Interface uses a modulus counter to derive the SPCK baud rate from the Master Clock MCK. The Baud rate is selected by writing a value from 1 to 255 in the SCBR field. The following equations determine the SPCK baud rate: Programming the SCBR field at 0 is forbidden. Triggering a transfer while SCBR is at 0 can lead to unpredictable results. At reset, SCBR is 0 and the user has to program it at a valid value before performing the first transfer. Note: If one of the SCBR fields inSPI_CSRx is set to 1, the other SCBR fields in SPI_CSRx must be set to 1 as well, if they are required to process transfers. If they are not used to transfer data, they can be set at any value.  DLYBS: Delay Before SPCK This field defines the delay from NPCS valid to the first valid SPCK transition. When DLYBS equals zero, the NPCS valid to SPCK transition is 1/2 the SPCK clock period. Otherwise, the following equations determine the delay: Value Name Description 0 8_BIT 8 bits for transfer 1 9_BIT 9 bits for transfer 2 10_BIT 10 bits for transfer 3 11_BIT 11 bits for transfer 4 12_BIT 12 bits for transfer 5 13_BIT 13 bits for transfer 6 14_BIT 14 bits for transfer 7 15_BIT 15 bits for transfer 8 16_BIT 16 bits for transfer 9– R e s e r v e d 10 – Reserved 11 – Reserved 12 – Reserved 13 – Reserved 14 – Reserved 15 – Reserved SPCK Baudrate MCK Delay Before SPCK DLYBS

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 671 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12  DLYBCT: Delay Between Consecutive Transfers This field defines the delay between two consecutive transfers with the same perip heral without removing the chip select. The delay is always inserted after each transfer and before removing the chip select if needed. When DLYBCT equals zero, no delay between consecutive transfers is inserted and the clock keeps its duty cycle over the character transfers. Otherwise, the following equation determines the delay: Delay Between Consecutive Transfers 32 DLYBCT×

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 672 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

36.8.10 SPI Write Protection Mode Register

Name: SPI_WPMR Address: 0xF00000E4 (0), 0xF00040E4 (1) Access: Read-write  SPIWPEN: SPI Write Protection Enable 0: The Write Protection is Disabled 1: The Write Protection is Enabled  SPIWPKEY: SPI Write Protection Key Password If a value is written in SPIWPEN, the value is taken into ac count only if SPIWPKEY is wri tten with “SPI” (SPI written in ASCII Code, ie 0x535049 in hexadecimal). 31 30 29 28 27 26 25 24 SPIWPKEY 23 22 21 20 19 18 17 16 SPIWPKEY 15 14 13 12 11 10 9 8 SPIWPKEY 76543210

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36.8.11 SPI Write Protection Status Register

Name: SPI_WPSR Address: 0xF00000E8 (0), 0xF00040E8 (1) Access: Read-only  SPIWPVS: SPI Write Prot ection Violation Status  SPIWPVSRC: SPI Write Prot ection Violation Source This Field indicates the APB Offset of the register concerned by the violation (SPI_MR or SPI_CSRx) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 SPIWPVSRC 76543210 SPIWPVS value Violation Type 0x1 The Write Protection has blocked a Write access to a protected register (since the last read). 0x2 Software Reset has been performed while Write Protection was enabled (since the last read or since the last write access on SPI_MR, SPI_IER, SPI_IDR or SPI_CSRx). 0x3 Both Write Protection violation and software reset with Write Protection enabled have occurred since the last read. 0x4 Write accesses have been detected on SPI_MR (while a chip select was active) or on SPI_CSRi (while the Chip Select “i” was active) since the last read. 0x5 The Write Protection has blocked a Write access to a protected register and write accesses have been detected on SPI_MR (while a chip select was active) or on SPI_CSRi (while the Chip Select “i” was active) since the last read. 0x6 Software Reset has been performed while Write Protection was enabled (since the last read or since the last write access on SPI_MR, SPI_IER, SPI_IDR or SPI_CSRx) and some write accesses have been detected on SPI_MR (while a chip select was active) or on SPI_CSRi (while the Chip Select “i” was active) since the last read. 0x7 - The Write Protection has blocked a Write access to a protected register. and - Software Reset has been performed while Write Protection was enabled. and - Write accesses have been detected on SPI_MR (while a chip select was active) or on SPI_CSRi (while the Chip Select “i” was active) since the last read.

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11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 675 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 37. Timer Counter (TC)

37.1 Description

The Timer Counter (TC) includes 6 identical 32-bit Timer Counter channels. Each channel can be independently programmed to perform a wide range of functions including frequency measurement, event counting, interval measurement, pulse generation, delay timing and pulse width modulation. Each channel has three external clock inputs, fi ve internal clock inputs and two multi-purpose input/output signals which can be configured by the user. Each channel drives an internal inter- rupt signal which can be programmed to generate processor interrupts. The Timer Counter block has two global registers which act upon all TC channels. The Block Control Register allows the channels to be started simultaneously with the same instruction. The Block Mode Register defines the external clock inputs for each channel, allowing them to be chained. Table 37-1 gives the assignment of the device Timer Counter clock inputs common to Timer Counter 0 to 2. Note: 1. When Slow Clock is selected for Master Clock (CSS = 0 in PMC Master CLock Register), TIMER_CLOCK5 input is Master Clock, i.e., Slow CLock modified by PRES and MDIV fields.

37.2 Embedded Characteristics

  • Provides 6 32-bit Timer Counter channels
  • Wide range of functions including: – Frequency measurement – Event counting – Interval measurement – Pulse generation – Delay timing – Pulse Width Modulation – Up/down capabilities
  • Each channel is user-configurable and contains: – Three external clock inputs – Five Internal clock inputs Table 37-1. Timer Counter Clock Assignment Name Definition TIMER_CLOCK1 MCK/2 TIMER_CLOCK2 MCK/8 TIMER_CLOCK3 MCK/32 TIMER_CLOCK4 MCK/128 TIMER_CLOCK5(1) SLCK

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 676 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 – Two multi-purpose input/output signals

  • Internal interrupt signal
  • Two global registers that act on all TC channels
  • Read of the Capture registers by the DMAC

37.3 Block Diagram

Figure 37-1. Timer Counter Block Diagram Timer/C ounter C hannel 0 Timer/C ounter C hannel 1 Timer/C ounter C hannel 2 SYNC P arallel I/O C ontroller TC1XC1S TC0XC0S TC2XC2S INT0 INT1 INT2 TIOA0 TIOA1 TIOA2 TIOB0 TIOB1 TIOB2 XC0 XC1 XC2 XC0 XC1 XC2 XC0 XC1 XC2 TCLK0 TCLK1 TCLK2 TCLK0 TCLK1 TCLK2 TCLK0 TCLK1 TCLK2 TIOA1 TIOA2 TIOA0 TIOA2 TIOA0 TIOA1 Interrupt C ontroller TCLK0 TCLK1 TCLK2 TIOA0 TIOB0 TIOA1 TIOB1 TIOA2 TIOB2 Timer C ounter TIOA TIOB TIOA TIOB TIOA TIOB SYNC SYNC TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 TIMER_CLOCK1 Table 37-2. Signal Name Description Block/Channel Signal Name Description Channel Signal XC0, XC1, XC2 External Clock Inputs TIOA Capture Mode: Timer Counter Input Waveform Mode: Timer Counter Output TIOB Capture Mode: Timer Counter Input Waveform Mode: Timer Counter Input/Output INT Interrupt Signal Output SYNC Synchronization Input Signal

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 677 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

37.4 Pin Name List

37.5 Product Dependencies

37.5.1 I/O Lines

The pins used for interfacing the compliant ex ternal devices may be multiplexed with PIO lines. The programmer must first program the PIO controllers to assign the TC pins to their peripheral functions.

37.5.2 Power Management

The TC is clocked through the Power Management Controller (PMC), thus the programmer must first configure the PMC to enable the Timer Counter clock. Table 37-3. TC pin list Pin Name Description Type TCLK0-TCLK2 External Clock Input Input TIOA0-TIOA2 I/O Line A I/O TIOB0-TIOB2 I/O Line B I/O Table 37-4. I/O Lines Instance Signal I/O Line Peripheral TC0 TCLK0 PA24 A TC0 TCLK1 PA25 A TC0 TCLK2 PA26 A TC0 TIOA0 PA21 A TC0 TIOA1 PA22 A TC0 TIOA2 PA23 A TC0 TIOB0 PA27 A TC0 TIOB1 PA28 A TC0 TIOB2 PA29 A TC1 TCLK3 PC4 C TC1 TCLK4 PC7 C TC1 TCLK5 PC14 C TC1 TIOA3 PC2 C TC1 TIOA4 PC5 C TC1 TIOA5 PC12 C TC1 TIOB3 PC3 C TC1 TIOB4 PC6 C TC1 TIOB5 PC13 C

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37.5.3 Interrupt

The TC has an interrupt line connected to the Interrupt Controller (IC). Handling the TC interrupt requires programming the IC before configuring the TC.

37.6 Functional Description

37.6.1 TC Description

The 6 channels of the Timer Counter are independent and identical in operation. The registers for channel programming are listed in Table 37-5 on page 691. 37.6.2 32-bit Counter Each channel is organized around a 32-bit counter. The value of the counter is incremented at each positive edge of the selected clock. When the counter has reached the value 0xFFFF and passes to 0x0000, an overflow occurs and the COVFS bit in TC_SR (Status Register) is set. The current value of the counter is accessible in real time by reading the Counter Value Regis- ter, TC_CV. The counter can be reset by a trigger. In this case, the counter value passes to 0x0000 on the next valid edge of the selected clock.

37.6.3 Clock Selection

At block level, input clock signals of each channel can either be connected to the external inputs TCLK0, TCLK1 or TCLK2, or be connected to t he internal I/O signals TIOA0, TIOA1 or TIOA2 for chaining by programming the TC_BMR (Block Mode). See Figure 37-2 ”Clock Chaining Selection”. Each channel can independently select an internal or external clock source for its counter:

  • Internal clock signals: TIMER_CL OCK1, TIMER_CLOCK2, TIMER_CLOCK3, TIMER_CLOCK4, TIMER_CLOCK5
  • External clock signals: XC0, XC1 or XC2 This selection is made by the TCCLKS bits in the TC Channel Mode Register. The selected clock can be inverted with the CLKI bit in TC_CMR. This allows counting on the opposite edges of the clock. The burst function allows the clock to be validat ed when an external signal is high. The BURST parameter in the Mode Register defines this signal (none, XC0, XC1, XC2). See Figure 37-3 ”Clock Selection” Note: In all cases, if an external clock is used, the du ration of each of its levels must be longer than the master clock period. The external clock frequency must be at least 2.5 times lower than the mas- ter clock

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 680 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

37.6.4 Clock Control

The clock of each counter can be controlled in two different ways: it can be enabled/disabled and started/stopped. See Figure 37-4.

  • The clock can be enabled or disabled by the user with the CLKEN and the CLKDIS commands in the Control Register. In Capture Mode it can be disabled by an RB load event if LDBDIS is set to 1 in TC_CMR. In Waveform Mode, it can be disabled by an RC Compare event if CPCDIS is set to 1 in TC_CMR. When disabled, the start or the stop actions have no effect: only a CLKEN command in the Control Register can re-enable the clock. When the clock is enabled, the CLKSTA bit is set in the Status Register.
  • The clock can also be started or stopped: a trigger (software, synchro, external or compare) always starts the clock. The clock can be stopped by an RB load event in Capture Mode (LDBSTOP = 1 in TC_CMR) or a RC compare event in Waveform Mode (CPCSTOP = 1 in TC_CMR). The start and the stop commands have effect only if the clock is enabled. Figure 37-4. Clock Control

37.6.5 TC Operating Modes

Each channel can independently operate in two different modes:

  • Capture Mode provides measurement on signals.
  • Waveform Mode provides wave generation. The TC Operating Mode is programmed with the WAVE bit in the TC Channel Mode Register. In Capture Mode, TIOA and TIOB are configured as inputs. In Waveform Mode, TIOA is always configured to be an output and TIOB is an output if it is not selected to be the external trigger.

37.6.6 Trigger

A trigger resets the counter and starts the counter clock. Three types of triggers are common to both modes, and a fourth external trigger is available to each mode. QS R S R Q CLKSTA CLKEN CLKDIS Stop Event Disable EventCounter Clock Selected Clock Trigger

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 681 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Regardless of the trigger used, it will be taken into account at the following active edge of the selected clock. This means that the counter value can be read differently from zero just after a trigger, especially when a low frequency signal is selected as the clock. The following triggers are common to both modes:

  • Software Trigger: Each channel has a software trigger, available by setting SWTRG in TC_CCR.
  • SYNC: Each channel has a synchronization signal SYNC. When asserted, this signal has the same effect as a software trigger. The SYNC signals of all channels are asserted simultaneously by writing TC_BCR (Block Control) with SYNC set.
  • Compare RC Trigger: RC is implemented in each channel and can provide a trigger when the counter value matches the RC value if CPCTRG is set in TC_CMR. The channel can also be configured to have an external trigger. In Capture Mode, the external trigger signal can be selected between TIOA and TIOB. In Waveform Mode, an external event can be programmed on one of the following signals: TIOB, XC0, XC1 or XC2. This external event can then be programmed to perform a trigger by setting ENETRG in TC_CMR. If an external trigger is used, the duration of the pulses must be longer than the master clock period in order to be detected.

37.6.7 Capture Operating Mode

This mode is entered by clearing the WAVE parameter in TC_CMR (Channel Mode Register). Capture Mode allows the TC channel to perform measurements such as pulse timing, fre- quency, period, duty cycle and phase on TIOA and TIOB sig nals which are considered as inputs. Figure 37-5 shows the configuration of the TC channel when programmed in Capture Mode.

37.6.8 Capture Registers A and B

Registers A and B (RA and RB) are used as capture registers. This means that they can be loaded with the counter value when a programmable event occurs on the signal TIOA. The LDRA parameter in TC_CMR defines the TIOA selected edge for the loading of register A, and the LDRB parameter defines the TIOA selected edge for the loading of Register B. RA is loaded only if it has not been loaded since the last trigger or if RB has been loaded since the last loading of RA. RB is loaded only if RA has been loaded since the last trigger or the last loading of RB. The RAB register provides the next unread value from Register A and Register B. It may be read by the DMAC after a request has been triggered upon loading Register A or Register B. Loading RA or RB before the read of the last value loaded sets the Overrun Error Flag (LOVRS) in TC_SR (Status Register). In this case, the old value is overwritten.

37.6.9 Trigger Conditions

In addition to the SYNC signal, the software trigger and the RC compare trigger, an external trig- ger can be defined. The ABETRG bit in TC_CMR selects TIOA or TIOB input signal as an external trigger. The ETRGEDG parameter defines the edge (rising, falling or both) det ected to generate an external trigger. If ETRGEDG = 0 (none), the external trigger is disabled.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 682 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Figure 37-5. Capture Mode TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 XC0 XC1 XC2 TCCLKS CLKI QS R S R Q CLKSTA CLKEN CLKDIS BURST TIOB Register C Capture Register A Capture Register B Compare RC = Counter ABETRG SWTRG ETRGEDG CPCTRG TC1_IMR Trig LDRBS LDRAS ETRGS TC1_SR LOVRS COVFS SYNC MTIOB TIOA MTIOA LDRA LDBSTOP If RA is not loaded or RB is Loaded If RA is Loaded LDBDIS CPCS INT Edge Detector Edge Detector LDRB Edge Detector CLK OVF RESET Timer/Counter Channel MCK Synchronous Edge Detection

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 683 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

37.6.10 Waveform Operating Mode

Waveform operating mode is entered by setting the WAVE parameter in TC_CMR (Channel Mode Register). In Waveform Operating Mode the TC channel generates 1 or 2 PWM signals with the same fre- quency and independently programmable duty cycles , or generates differe nt types of one-shot or repetitive pulses. In this mode, TIOA is configured as an output and TIOB is defined as an output if it is not used as an external event (EEVT parameter in TC_CMR). Figure 37-6 shows the configuration of the TC channel when programmed in Waveform Operat- ing Mode.

37.6.11 Waveform Selection

Depending on the WAVSEL parameter in TC_C MR (Channel Mode Register), the behavior of TC_CV varies. With any selection, RA, RB and RC can all be used as compare registers. RA Compare is used to control the TIOA output, RB Compare is used to control the TIOB output (if correctly configured) and RC Compare is used to control TIOA and/or TIOB outputs.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 684 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Figure 37-6. Waveform Mode TCCLKS CLKI QS R S R Q CLKSTA CLKEN CLKDIS CPCDIS BURST TIOB Register A Register B Register C Compare RA = Compare RB = Compare RC = CPCSTOP Counter EEVT EEVTEDG SYNC SWTRG ENETRG WAVSEL TC1_IMR Trig ACPC ACPA AEEVT ASWTRG BCPC BCPB BEEVT BSWTRG TIOA MTIOA TIOB MTIOB CPAS COVFS ETRGS TC1_SR CPCS CPBS CLK OVFRESET Output Controller Output Controller INT Edge Detector Timer/Counter Channel TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 XC0 XC1 XC2 WAVSEL MCK Synchronous Edge Detection

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 685 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

37.6.11.1 WAVSEL = 00

When WAVSEL = 00, the value of TC_CV is incr emented from 0 to 0xFFFF. Once 0xFFFF has been reached, the value of TC_CV is reset. Incrementation of TC_CV starts again and the cycle continues. See Figure 37-7. An external event trigger or a software trigger can reset the value of TC_CV. It is important to note that the trigger may occur at any time. See Figure 37-8. RC Compare cannot be programmed to generate a trigger in this configuration. At the same time, RC Compare can stop the counter clock (CPCSTOP = 1 in TC_CMR) and/or disable the counter clock (CPCDIS = 1 in TC_CMR). Figure 37-7. WAVSEL= 00 without trigger Time Counter Value RC RB RA TIOB TIOA Counter cleared by compare match with 0xFFFF 0xFFFF Waveform Examples

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 686 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Figure 37-8. WAVSEL= 00 with trigger

37.6.11.2 WAVSEL = 10

When WAVSEL = 10, the value of TC_CV is incremented from 0 to the value of RC, then auto- matically reset on a RC Compare. Once the value of TC_CV has been reset, it is then incremented and so on. See Figure 37-9. It is important to note that TC_CV can be reset at any time by an external event or a software trigger if both are programmed correctly. See Figure 37-10. In addition, RC Compare can stop the counter clock (CPCSTOP = 1 in TC_CMR) and/or disable the counter clock (CPCDIS = 1 in TC_CMR). Figure 37-9. WAVSEL = 10 Without Trigger Time Counter Value RC RB RA TIOB TIOA Counter cleared by compare match with 0xFFFF 0xFFFF Waveform Examples Counter cleared by trigger Time Counter Value RC RB RA TIOB TIOA Counter cleared by compare match with RC 0xFFFF Waveform Examples

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 687 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Figure 37-10. WAVSEL = 10 With Trigger

37.6.11.3 WAVSEL = 01

When WAVSEL = 01, the value of TC_CV is incremented from 0 to 0xFFFF. Once 0xFFFF is reached, the value of TC_CV is decremented to 0, then re-incremented to 0xFFFF and so on. See Figure 37-11. A trigger such as an external event or a software trigger can modify TC_CV at any time. If a trig- ger occurs while TC_CV is incrementing, TC_CV then decrements. If a trigger is received while TC_CV is decrementing, TC_CV then increments. See Figure 37-12. RC Compare cannot be programmed to generate a trigger in this configuration. At the same time, RC Compare can stop the counter clock (CPCSTOP = 1) and/or disable the counter clock (CPCDIS = 1). Time Counter Value RC RB RA TIOB TIOA Counter cleared by compare match with RC 0xFFFF Waveform Examples Counter cleared by trigger

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 688 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Figure 37-11. WAVSEL = 01 Without Trigger Figure 37-12. WAVSEL = 01 With Trigger

37.6.11.4 WAVSEL = 11

When WAVSEL = 11, the value of TC_CV is incremented from 0 to RC. Once RC is reached, the value of TC_CV is decremented to 0, then re-incremented to RC and so on. See Figure 37-13. A trigger such as an external event or a software trigger can modify TC_CV at any time. If a trig- ger occurs while TC_CV is incrementing, TC_CV then decrements. If a trigger is received while TC_CV is decrementing, TC_CV then increments. See Figure 37-14. RC Compare can stop the counter clock (CPCSTOP = 1) and/or disable the counter clock (CPCDIS = 1). Time Counter Value RC RB RA TIOB TIOA Counter decremented by compare match with 0xFFFF 0xFFFF Waveform Examples Time Counter Value TIOB TIOA Counter decremented by compare match with 0xFFFF 0xFFFF Waveform Examples Counter decremented by trigger Counter incremented by trigger R C RB RA

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 690 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

37.6.12 External Event/Trigger Conditions

An external event can be programmed to be detected on one of the clock sources (XC0, XC1, XC2) or TIOB. The external event selected can then be used as a trigger. The EEVT parameter in TC_CMR selects the external trigger. The EEVTEDG parameter defines the trigger edge for each of the possible external triggers (rising, falling or both). If EEVTEDG is cleared (none), no external event is defined. If TIOB is defined as an external event signal (EEVT = 0), TIOB is no longer used as an output and the compare register B is not used to generate waveforms and subsequently no IRQs. In this case the TC channel can only generate a waveform on TIOA. When an external event is defined, it can be used as a trigger by setting bit ENETRG in TC_CMR. As in Capture Mode, the SYNC signal and the software trigger are also available as triggers. RC Compare can also be used as a trigger depending on the parameter WAVSEL.

37.6.13 Output Controller

The output controller defines the output level changes on TIOA and TIOB following an event. TIOB control is used only if TIOB is defined as output (not as an external event). The following events control TIOA and TIOB: software trigger, external event and RC compare. RA compare controls TIOA and RB compare controls TIOB. Each of these events can be pro- grammed to set, clear or toggle the output as defined in the corresponding parameter in TC_CMR.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 691 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

37.7 Timer Counter (TC) User Interface

Notes: 1. Channel index ranges from 0 to 2. 2. Read-only if WAVE = 0 Table 37-5. Register Mapping Offset(1) Register Name Access Reset 0x00 + channel * 0x40 + 0x00 Channel Control Register TC_CCR Write-only – 0x00 + channel * 0x40 + 0x04 Channel Mode Register TC_CMR Read-write 0 0x00 + channel * 0x40 + 0x08 Reserved 0x00 + channel * 0x40 + 0x0C Register AB TC_RAB Read-only 0 0x00 + channel * 0x40 + 0x10 Counter Value TC_CV Read-only 0 0x00 + channel * 0x40 + 0x14 Register A TC_RA Read-write (2) 0 0x00 + channel * 0x40 + 0x18 Register B TC_RB Read-write (2) 0 0x00 + channel * 0x40 + 0x1C Register C TC_RC Read-write 0 0x00 + channel * 0x40 + 0x20 Status Register TC_SR Read-only 0 0x00 + channel * 0x40 + 0x24 Interrupt Enable Register TC_IER Write-only – 0x00 + channel * 0x40 + 0x28 Interrupt Disable Register TC_IDR Write-only – 0x00 + channel * 0x40 + 0x2C Interrupt Mask Register TC_IMR Read-only 0 0xC0 Block Control Register TC_BCR Write-only – 0xC4 Block Mode Register TC_BMR Read-write 0 0xD8 Reserved 0xE4 Reserved 0xFC Reserved – – –

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 692 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

37.7.1 TC Block Control Register

Name: TC_BCR Address: 0xF80080C0 (0), 0xF800C0C0 (1) Access: Write-only  SYNC: Synchro Command 0 = no effect. 1 = asserts the SYNC signal which generates a software trigger simultaneously for each of the channels. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 693 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

37.7.2 TC Block Mode Register

Name: TC_BMR Address: 0xF80080C4 (0), 0xF800C0C4 (1) Access: Read-write  TC0XC0S: External Clock Signal 0 Selection  TC1XC1S: External Clock Signal 1 Selection  TC2XC2S: External Clock Signal 2 Selection 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 – – TC2XC2S TC1XC1S TC0XC0S Value Name Description

0 TCLK0 Signal connected to XC0: TCLK0

1– R e s e r v e d

2 TIOA1 Signal connected to XC0: TIOA1

3 TIOA2 Signal connected to XC0: TIOA2

0 TCLK1 Signal connected to XC1: TCLK1

1– R e s e r v e d

2 TIOA0 Signal connected to XC1: TIOA0

3 TIOA2 Signal connected to XC1: TIOA2

0 TCLK2 Signal connected to XC2: TCLK2

1– R e s e r v e d

2 TIOA1 Signal connected to XC2: TIOA1

3 TIOA2 Signal connected to XC2: TIOA2

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 694 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

37.7.3 TC Channel Control Register

Name: TC_CCRx [x=0..2] 0xF800C080 (1)[2] Access: Write-only  CLKEN: Counter Clock Enable Command 0 = no effect. 1 = enables the clock if CLKDIS is not 1.  CLKDIS: Counter Clock Disable Command 0 = no effect. 1 = disables the clock.  SWTRG: Software Trigger Command 0 = no effect. 1 = a software trigger is performed: the counter is reset and the clock is started. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 ––––– S WTRG C LKDIS C LKEN

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 695 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

37.7.4 TC Channel Mode Register: Capture Mode

Name: TC_CMRx [x=0..2] (WAVE = 0) 0xF800C084 (1)[2] Access: Read-write  TCCLKS: Clock Selection  CLKI: Clock Invert 0 = counter is incremented on rising edge of the clock. 1 = counter is incremented on falling edge of the clock.  BURST: Burst Signal Selection  LDBSTOP: Counter Clock Stopped with RB Loading 0 = counter clock is not stopped when RB loading occurs. 1 = counter clock is stopped when RB loading occurs. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 – – – – LDRB LDRA 15 14 13 12 11 10 9 8 WAVE CPCTRG – – – ABETRG ETRGEDG 76543210 LDBDIS LDBSTOP BURST CLKI TCCLKS Value Name Description

0 TIMER_CLOCK1 Clock selected: TCLK1

1 TIMER_CLOCK2 Clock selected: TCLK2

2 TIMER_CLOCK3 Clock selected: TCLK3

3 TIMER_CLOCK4 Clock selected: TCLK4

4 TIMER_CLOCK5 Clock selected: TCLK5

5 XC0 Clock selected: XC0

6 XC1 Clock selected: XC1

7 XC2 Clock selected: XC2

0 NONE The clock is not gated by an external signal. 1 XC0 XC0 is ANDed with the selected clock. 2 XC1 XC1 is ANDed with the selected clock. 3 XC2 XC2 is ANDed with the selected clock.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 696 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12  LDBDIS: Counter Clock Disable with RB Loading 0 = counter clock is not disabled when RB loading occurs. 1 = counter clock is disabled when RB loading occurs.  ETRGEDG: External Trigger Edge Selection  ABETRG: TIOA or TIOB External Trigger Selection 0 = TIOB is used as an external trigger. 1 = TIOA is used as an external trigger.  CPCTRG: RC Compare Trigger Enable 0 = RC Compare has no effect on the counter and its clock. 1 = RC Compare resets the counter and starts the counter clock.  WAVE: Waveform Mode 0 = Capture Mode is enabled. 1 = Capture Mode is disabled (Waveform Mode is enabled).  LDRA: RA Loading Edge Selection  LDRB: RB Loading Edge Selection Value Name Description 0 NONE The clock is not gated by an external signal.

1 RISING Rising edge

2 FALLING Falling edge

3 EDGE Each edge

1 RISING Rising edge of TIOA

2 FALLING Falling edge of TIOA

3 EDGE Each edge of TIOA

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 697 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

37.7.5 TC Channel Mode Register: Waveform Mode

Name: TC_CMRx [x=0..2] (WAVE = 1) Access: Read-write  TCCLKS: Clock Selection  CLKI: Clock Invert 0 = counter is incremented on rising edge of the clock. 1 = counter is incremented on falling edge of the clock.  BURST: Burst Signal Selection  CPCSTOP: Counter Clock Stopped with RC Compare 0 = counter clock is not stopped when counter reaches RC. 1 = counter clock is stopped when counter reaches RC.  CPCDIS: Counter Clock Disable with RC Compare 0 = counter clock is not disabled when counter reaches RC. 1 = counter clock is disabled when counter reaches RC. 31 30 29 28 27 26 25 24 BSWTRG BEEVT BCPC BCPB 23 22 21 20 19 18 17 16 ASWTRG AEEVT ACPC ACPA 15 14 13 12 11 10 9 8 WAVE WAVSEL ENETRG EEVT EEVTEDG 76543210 CPCDIS CPCSTOP BURST CLKI TCCLKS Value Name Description 0 NONE The clock is not gated by an external signal. 1 XC0 XC0 is ANDed with the selected clock. 2 XC1 XC1 is ANDed with the selected clock. 3 XC2 XC2 is ANDed with the selected clock.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 698 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12  EEVTEDG: External Ev ent Edge Selection  EEVT: External Event Selection Signal selected as external event. Note: 1. If TIOB is chosen as the external event signal, it is configured as an input and no longer generates waveforms and subse- quently no IRQs.  ENETRG: External Event Trigger Enable 0 = the external event has no effect on the counter and its clock. In this case, the selected external event only controls the TIOA output. 1 = the external event resets the counter and starts the counter clock.  WAVSEL: Waveform Selection  WAVE: Waveform Mode 0 = Waveform Mode is disabled (Capture Mode is enabled). 1 = Waveform Mode is enabled.  ACPA: RA Compare Effect on TIOA Value Name Description 0N O N E N o n e Value Name Description TIOB Direction

0 TIOB TIOB(1) input

1 XC0 XC0 output

2 XC1 XC1 output

3 XC2 XC2 output

0 UP UP mode without automatic trigger on RC Compare

1 UPDOWN UPDOWN mode without automatic trigger on RC Compare

2 UP_RC UP mode with automatic trigger on RC Compare

3 UPDOWN_RC UPDOWN mode with autom atic trigger on RC Compare

1 SET Set

2 CLEAR Clear

3 TOGGLE Toggle

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 699 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12  ACPC: RC Compare Effect on TIOA  AEEVT: External Event Effect on TIOA  ASWTRG: Software Trigger Effect on TIOA  BCPB: RB Compare Effect on TIOB  BCPC: RC Compare Effect on TIOB Value Name Description 0N O N E N o n e

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 700 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12  BEEVT: External Event Effect on TIOB  BSWTRG: Software Trigger Effect on TIOB Value Name Description 0N O N E N o n e

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 701 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

37.7.6 TC Register AB

Name: TC_RABx [x=0..2] Address: 0xF800800C (0)[0], 0xF800804C (0)[1], 0xF800808C (0)[2], 0xF800C00C (1)[0], 0xF800C04C (1)[1], 0xF800C08C (1)[2] Access: Read-only  RAB: Register A or Register B RAB contains the next unread capture Register A or Regist er B value in real time. It is usually read by the DMAC after a request due to a valid load edge on TIOA.

37.7.7 TC Counter Value Register

Name: TC_CVx [x=0..2] 0xF800C090 (1)[2] Access: Read-only  CV: Counter Value CV contains the counter value in real time. 31 30 29 28 27 26 25 24 RAB 23 22 21 20 19 18 17 16 RAB 15 14 13 12 11 10 9 8 RAB 76543210 RAB 31 30 29 28 27 26 25 24 CV 23 22 21 20 19 18 17 16 CV 15 14 13 12 11 10 9 8 CV 76543210 CV

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 702 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

37.7.8 TC Register A

Name: TC_RAx [x=0..2] 0xF800C094 (1)[2] Access: Read-only if WAVE = 0, Read-write if WAVE = 1  RA: Register A RA contains the Register A value in real time. 31 30 29 28 27 26 25 24 RA 23 22 21 20 19 18 17 16 RA 15 14 13 12 11 10 9 8 RA 76543210 RA

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 703 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

37.7.9 TC Register B

Name: TC_RBx [x=0..2] 0xF800C098 (1)[2] Access: Read-only if WAVE = 0, Read-write if WAVE = 1  RB: Register B RB contains the Register B value in real time.

37.7.10 TC Register C

Name: TC_RCx [x=0..2] Address: 0xF800801C (0)[0], 0xF800805C (0)[1], 0xF800809C (0)[2], 0xF800C01C (1)[0], 0xF800C05C (1)[1], 0xF800C09C (1)[2] Access: Read-write  RC: Register C RC contains the Register C value in real time. 31 30 29 28 27 26 25 24 RB 23 22 21 20 19 18 17 16 RB 15 14 13 12 11 10 9 8 RB 76543210 RB 31 30 29 28 27 26 25 24 RC 23 22 21 20 19 18 17 16 RC 15 14 13 12 11 10 9 8 RC 76543210 RC

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 704 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

37.7.11 TC Status Register

Name: TC_SRx [x=0..2] 0xF800C0A0 (1)[2] Access: Read-only  COVFS: Counter Overflow Status 0 = no counter overflow has occurred since the last read of the Status Register. 1 = a counter overflow has occurred since the last read of the Status Register.  LOVRS: Load Overrun Status 0 = Load overrun has not occurred since the last read of the Status Register or WAVE = 1. 1 = RA or RB have been loaded at least twice without any read of the corresponding register since the last read of the Sta- tus Register, if WAVE = 0.  CPAS: RA Compare Status 0 = RA Compare has not occurred since the last read of the Status Register or WAVE = 0. 1 = RA Compare has occurred since the last read of the Status Register, if WAVE = 1.  CPBS: RB Compare Status 0 = RB Compare has not occurred since the last read of the Status Register or WAVE = 0. 1 = RB Compare has occurred since the last read of the Status Register, if WAVE = 1.  CPCS: RC Compare Status 0 = RC Compare has not occurred since the last read of the Status Register. 1 = RC Compare has occurred since the last read of the Status Register.  LDRAS: RA Loading Status 0 = RA Load has not occurred since the last read of the Status Register or WAVE = 1. 1 = RA Load has occurred since the last read of the Status Register, if WAVE = 0.  LDRBS: RB Loading Status 0 = RB Load has not occurred since the last read of the Status Register or WAVE = 1. 1 = RB Load has occurred since the last read of the Status Register, if WAVE = 0. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ––––– M TIOB M TIOA C LKSTA 15 14 13 12 11 10 9 8 76543210 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 705 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12  ETRGS: External Trigger Status 0 = external trigger has not occurred since the last read of the Status Register. 1 = external trigger has occurred since the last read of the Status Register.  CLKSTA: Clock Enabling Status 0 = clock is disabled. 1 = clock is enabled.  MTIOA: TIOA Mirror 0 = TIOA is low. If WAVE = 0, this means that TIOA pin is low. If WAVE = 1, this means that TIOA is driven low. 1 = TIOA is high. If WAVE = 0, this means that TIOA pin is high. If WAVE = 1, this means that TIOA is driven high.  MTIOB: TIOB Mirror 0 = TIOB is low. If WAVE = 0, this means that TIOB pin is low. If WAVE = 1, this means that TIOB is driven low. 1 = TIOB is high. If WAVE = 0, this means that TIOB pin is high. If WAVE = 1, this means that TIOB is driven high.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 706 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

37.7.12 TC Interrupt Enable Register

Name: TC_IERx [x=0..2] 0xF800C0A4 (1)[2] Access: Write-only  COVFS: Counter Overflow 0 = no effect. 1 = enables the Counter Overflow Interrupt.  LOVRS: Load Overrun 0 = no effect. 1 = enables the Load Overrun Interrupt.  CPAS: RA Compare 0 = no effect. 1 = enables the RA Compare Interrupt.  CPBS: RB Compare 0 = no effect. 1 = enables the RB Compare Interrupt.  CPCS: RC Compare 0 = no effect. 1 = enables the RC Compare Interrupt.  LDRAS: RA Loading 0 = no effect. 1 = enables the RA Load Interrupt.  LDRBS: RB Loading 0 = no effect. 1 = enables the RB Load Interrupt.  ETRGS: External Trigger 0 = no effect. 1 = enables the External Trigger Interrupt. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 707 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

37.7.13 TC Interrupt Disable Register

Name: TC_IDRx [x=0..2] 0xF800C0A8 (1)[2] Access: Write-only  COVFS: Counter Overflow 0 = no effect. 1 = disables the Counter Overflow Interrupt.  LOVRS: Load Overrun 0 = no effect. 1 = disables the Load Overrun Interrupt (if WAVE = 0).  CPAS: RA Compare 0 = no effect. 1 = disables the RA Compare Interrupt (if WAVE = 1).  CPBS: RB Compare 0 = no effect. 1 = disables the RB Compare Interrupt (if WAVE = 1).  CPCS: RC Compare 0 = no effect. 1 = disables the RC Compare Interrupt.  LDRAS: RA Loading 0 = no effect. 1 = disables the RA Load Interrupt (if WAVE = 0).  LDRBS: RB Loading 0 = no effect. 1 = disables the RB Load Interrupt (if WAVE = 0).  ETRGS: External Trigger 0 = no effect. 1 = disables the External Trigger Interrupt. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 708 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

37.7.14 TC Interrupt Mask Register

Name: TC_IMRx [x=0..2] Address: 0xF800802C (0)[0], 0xF800806C (0)[1], 0xF80080AC (0)[2], 0xF800C02C (1)[0], 0xF800C06C (1)[1], 0xF800C0AC (1)[2] Access: Read-only  COVFS: Counter Overflow 0 = the Counter Overflow Interrupt is disabled. 1 = the Counter Overflow Interrupt is enabled.  LOVRS: Load Overrun 0 = the Load Overrun Interrupt is disabled. 1 = the Load Overrun Interrupt is enabled.  CPAS: RA Compare 0 = the RA Compare Interrupt is disabled. 1 = the RA Compare Interrupt is enabled.  CPBS: RB Compare 0 = the RB Compare Interrupt is disabled. 1 = the RB Compare Interrupt is enabled.  CPCS: RC Compare 0 = the RC Compare Interrupt is disabled. 1 = the RC Compare Interrupt is enabled.  LDRAS: RA Loading 0 = the Load RA Interrupt is disabled. 1 = the Load RA Interrupt is enabled.  LDRBS: RB Loading 0 = the Load RB Interrupt is disabled. 1 = the Load RB Interrupt is enabled.  ETRGS: External Trigger 0 = the External Trigger Interrupt is disabled. 1 = the External Trigger Interrupt is enabled. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 38. Pulse Width Modulation Controller (PWM)

38.1 Description

The PWM macrocell controls several cha nnels independently. Each channel controls one square output waveform. Characteristics of the output waveform such as period, duty-cycle and polarity are configurable through the user interface. Each channel selects and uses one of the clocks provided by the clock generator. The cloc k generator provides several clocks resulting from the division of the PWM macrocell master clock. All PWM macrocell accesses are made through APB mapped registers. Channels can be synchronized, to generate non overlapped waveforms. All channels integrate a double buffering system in order to prevent an unexpected output waveform while modifying the period or the duty-cycle.

38.2 Embedded Characteristics

  • 4 channels, one 32-bit counter per channel
  • Common clock generator, providing Thirteen Different Clocks – A Modulo n counter providing eleven clocks – Two independent Linear Dividers working on modulo n counter outputs
  • Independent channel programming – Independent Enable Disable Commands – Independent Clock Selection – Independent Period and Duty Cycle, with Double Bufferization – Programmable selection of the output waveform polarity – Programmable center or left aligned output waveform

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

38.3 Block Diagram

Figure 38-1. Pulse Width Modulation Controller Block Diagram

38.4 I/O Lines Description

Each channel outputs one waveform on one external I/O line.

38.5 Product Dependencies

38.5.1 I/O Lines

The pins used for interfacing the PWM may be multiplexed with PIO lines. The programmer must first program the PIO controller to assign the desired PWM pins to their peripheral function. If I/O lines of the PWM are not used by the applicati on, they can be used for other purposes by the PIO controller. PWM Controller APB PWMx PWMx PWMx Channel Update Duty Cycle Counter PWM0 Channel PIO Interrupt ControllerPMC MCK Clock Generator APB Interface Interrupt Generator Clock Selector Period Update Duty Cycle Counter Clock Selector Period PWM0 PWM0 Comparator Comparator Table 38-1. I/O Line Description Name Description Type PWMx PWM Waveform Output for channel x Output

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 All of the PWM outputs may or may not be enabled. If an application requires only four channels, then only four PIO lines will be assigned to PWM outputs.

38.5.2 Power Management

The PWM is not continuously clocked. The programmer must first enable the PWM clock in the Power Management Controller (PMC) before using the PWM. However, if the application does not require PWM operations, the PWM clock can be stopped when not needed and be restarted later. In this case, the PWM will resume its operations where it left off. Configuring the PWM does not require the PWM clock to be enabled.

38.5.3 Interrupt Sources

The PWM interrupt line is connected on one of the internal sources of the Interrupt Controller. Using the PWM interrupt requires the Interrupt Controller to be programmed first. Note that it is not recommended to use the PWM interrupt line in edge sensitive mode.

38.6 Functional Description

The PWM macrocell is primarily composed of a clock generator module and 4 channels. – Clocked by the system clock, MCK, the clock generator module provides 13 clocks. – Each channel can independently choose one of the clock generator outputs. – Each channel generates an output waveform with attributes that can be defined independently for each channel through the user interface registers. Table 38-2. I/O Lines Instance Signal I/O Line Peripheral PWM PWM0 PB11 B PWM PWM0 PC10 C PWM PWM0 PC18 C PWM PWM1 PB12 B PWM PWM1 PC11 C PWM PWM1 PC19 C PWM PWM2 PB13 B PWM PWM2 PC20 C PWM PWM3 PB14 B PWM PWM3 PC21 C Table 38-3. Peripheral IDs Instance ID PWM 18

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

38.6.1 PWM Clock Generator

Figure 38-2. Functional View of the Clock Generator Block Diagram Caution: Before using the PWM macrocell, the programmer must first enable the PWM clock in the Power Management Controller (PMC). The PWM macrocell master clock, MCK, is divide d in the clock generator module to provide dif- ferent clocks available for all channels. Each channel can independently select one of the divided clocks. The clock generator is divided in three blocks: – a modulo n counter which provides 11 clocks: F MCK, FMCK/2, FMCK/4, FMCK/8, FMCK/16, FMCK/32, FMCK/64, FMCK/128, FMCK/256, FMCK/512, FMCK/1024 – two linear dividers (1, 1/2, 1/3, ... 1/255) that provide two separate clocks: clkA and clkB Each linear divider can independently divide one of the clocks of the modulo n counter. The selection of the clock to be divided is made ac cording to the PREA (PREB) field of the PWM Mode register (PWM_MR). The resulting clock clkA (clkB) is the clock selected divided by DIVA (DIVB) field value in the PWM Mode register (PWM_MR). After a reset of the PWM controller, DIVA (DIVB) and PREA (PREB) in the PWM Mode register are set to 0. This implies that after reset clkA (clkB) are turned off. modulo n counterMCK MCK/2 MCK/4 MCK/16 MCK/32 MCK/64 MCK/8 Divider A clkA DIVA PWM_MR MCK MCK/128 MCK/256 MCK/512 MCK/1024 PREA Divider B clkB DIVB PWM_MR PREB

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 At reset, all clocks provided by the modulo n counter are turned off except clock “clk”. This situa- tion is also true when the PWM master cl ock is turned off through the Power Management Controller.

38.6.2 PWM Channel

38.6.2.1 Block Diagram

Figure 38-3. Functional View of the Channel Block Diagram Each of the 4 channels is composed of three blocks:

  • A clock selector which selects one of the clocks provided by the clock generator described in Section 38.6.1 “PWM Clock Generator” on page 712.
  • An internal counter clocked by the output of the clock selector. This internal counter is incremented or decremented according to the channel configuration and comparators events. The size of the internal counter is 32 bits.
  • A comparator used to generate events according to the internal counter value. It also computes the PWMx output waveform according to the configuration.

38.6.2.2 Waveform Properties

The different properties of output waveforms are:

  • the internal clock selection. The internal channel counter is clocked by one of the clocks provided by the clock generator described in the previous section. This channel parameter is defined in the CPRE field of the PWM_CMRx register. This field is reset at 0.
  • the waveform period. This channel parameter is defined in the CPRD field of the PWM_CPRDx register. - If the waveform is left aligned, then the output waveform period depends on the counter source clock and can be calculated: By using the Master Clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024), the resulting period formula will be: By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes, respectively: or If the waveform is center aligned then the output waveform period depends on the counter Comparator PWMx output waveform Internal Counter Clock Selector inputs from clock generator inputs from APB bus Channel XC P R D×() X*CPRD *DIVA()

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 source clock and can be calculated: By using the Master Clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). The resulting period formula will be: By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes, respectively: or

  • the waveform duty cycle. This channel parameter is defined in the CDTY field of the PWM_CDTYx register. If the waveform is left aligned then: If the waveform is center aligned, then:
  • the waveform polarity. At the beginning of the period, the signal can be at high or low level. This property is defined in the CPOL field of the PWM_CMRx register. By default the signal starts by a low level.
  • the waveform alignment. The output waveform can be left or center aligned. Center aligned waveforms can be used to generate non overlapped waveforms. This property is defined in the CALG field of the PWM_CMRx register. The default mode is left aligned. Figure 38-4. Non Overlapped Center Aligned Waveforms Note: 1. See Figure 38-5 on page 716 for a detailed description of center aligned waveforms. When center aligned, the internal channel counter increases up to CPRD and.decreases down to 0. This ends the period. When left aligned, the internal channel counter increases up to CPRD and is reset. This ends the period. Thus, for the same CPRD value, the period for a center aligned channel is twice the period for a left aligned channel.

2 XC P R D× ×()

2*X *CPRD *DIVA() duty cycle period 1 fchannel_x_clock CDTY×⁄–() duty cycle period 2⁄() 1 fchannel_x_clock CDTY×⁄–() ) PWM0 PWM1 Period No overlap

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Waveforms are fixed at 0 when:

  • CDTY = CPRD and CPOL = 0
  • CDTY = 0 and CPOL = 1 Waveforms are fixed at 1 (once the channel is enabled) when:
  • CDTY = 0 and CPOL = 0
  • CDTY = CPRD and CPOL = 1 The waveform polarity must be set before enabling the channel. This immediately affects the channel output level. Changes on channel polari ty are not taken into account while the channel is enabled.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Figure 38-5. Waveform Properties PWM_MCKx CHIDx(PWM_SR) Center Aligned CPRD(PWM_CPRDx) CDTY(PWM_CDTYx) PWM_CCNTx Output Waveform PWMx CPOL(PWM_CMRx) = 0 Output Waveform PWMx CPOL(PWM_CMRx) = 1 CHIDx(PWM_ISR) Left Aligned CPRD(PWM_CPRDx) CDTY(PWM_CDTYx) PWM_CCNTx Output Waveform PWMx CPOL(PWM_CMRx) = 0 Output Waveform PWMx CPOL(PWM_CMRx) = 1 CHIDx(PWM_ISR) CALG(PWM_CMRx) = 0 CALG(PWM_CMRx) = 1 Period Period CHIDx(PWM_ENA) CHIDx(PWM_DIS)

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

38.6.3 PWM Controller Operations

38.6.3.1 Initialization

Before enabling the output channel, this chann el must have been configured by the software application:

  • Configuration of the clock generator if DIVA and DIVB are required
  • Selection of the clock for each channel (CPRE field in the PWM_CMRx register)
  • Configuration of the waveform alignment for each channel (CALG field in the PWM_CMRx register)
  • Configuration of the period for each channel (CPRD in the PWM_CPRDx register). Writing in PWM_CPRDx Register is possible while the channel is disabled. After validation of the channel, the user must use PWM_CUPDx Register to update PWM_CPRDx as explained below.
  • Configuration of the duty cycle for each channel (CDTY in the PWM_CDTYx register). Writing in PWM_CDTYx Register is possible while the channel is disabled. After validation of the channel, the user must use PWM_CUPDx Register to update PWM_CDTYx as explained below.
  • Configuration of the output waveform polarity for each channel (CPOL in the PWM_CMRx register)
  • Enable Interrupts (Writing CHIDx in the PWM_IER register)
  • Enable the PWM channel (Writing CHIDx in the PWM_ENA register) It is possible to synchronize different channels by enabling them at the same time by means of writing simultaneously several CHIDx bits in the PWM_ENA register.
  • In such a situation, all channels may have the same clock selector configuration and the same period specified.

38.6.3.2 Source Clock Selection Criteria

The large number of source clocks can make selection difficult. The relationship between the value in the Period Register (PWM_CPRDx) and the Duty Cycle Register (PWM_CDTYx) can help the user in choosing. The event number written in the Period Register gives the PWM accu- racy. The Duty Cycle quantum cannot be lower than 1/PWM_CPRDx value. The higher the value of PWM_CPRDx, the greater the PWM accuracy. For example, if the user sets 15 (in decimal) in PWM_CPRDx, the user is able to set a value between 1 up to 14 in PWM_CDTYx Register. The resulting duty cycle quantum cannot be lower than 1/15 of the PWM period.

38.6.3.3 Changing the Duty Cycle or the Period

It is possible to modulate the output waveform duty cycle or period. To prevent unexpected output waveform, the user must use the update register (PWM_CUPDx) to change waveform parameters while the channel is still enabled. The user can write a new period value or duty cycle value in the update re gister (PWM_CUPDx). This register holds the new value until the end of the current cycle and updates the value for the next cycle. Depending on the CPD field in the PWM_CMRx regist er, PWM_CUPDx either updates PWM_CPRDx or PWM_CDTYx. Note that even if the update register is used, the period must not be smaller than the duty cycle.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

38.6.3.4 Interrupts

Depending on the interrupt mask in the PWM_IMR register, an interrupt is generated at the end of the corresponding channel period. The interrupt remains active until a read operation in the PWM_ISR register occurs. A channel interrupt is enabled by setting the corresponding bit in the PWM_IER register. A chan- nel interrupt is disabled by setting the corresponding bit in the PWM_IDR register.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

38.7 Pulse Width Modulation Controller (PWM) User Interface

  1. Some registers are indexed with “ch_num” index ranging from 0 to 3. Table 38-4. Register Mapping(2) Offset Register Name Access Reset 0x00 PWM Mode Register PWM_MR Read-write 0 0x04 PWM Enable Register PWM_ENA Write-only - 0x08 PWM Disable Register PWM_DIS Write-only - 0x0C PWM Status Register PWM_SR Read-only 0 0x10 PWM Interrupt Enable Register PWM_IER Write-only - 0x14 PWM Interrupt Disable Register PWM_IDR Write-only - 0x18 PWM Interrupt Mask Register PWM_IMR Read-only 0 0x1C PWM Interrupt Status Register PWM_ISR Read-only 0 0x20 - 0xFC Reserved – – – 0x100 - 0x1FC Reserved 0x200 + ch_num * 0x20 + 0x00 PWM Channel Mode Register PWM_CMR Read-write 0x0 0x200 + ch_num * 0x20 + 0x04 PWM Channel Duty Cycle Register PWM_CDTY Read-write 0x0 0x200 + ch_num * 0x20 + 0x08 PWM Channel Period Register PWM_CPRD Read-write 0x0 0x200 + ch_num * 0x20 + 0x0C PWM Channel Counter Register PWM_CCNT Read-only 0x0 0x200 + ch_num * 0x20 + 0x10 PWM Channel Update Register PWM_CUPD Write-only -

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

38.7.1 PWM Mode Register

Name: PWM_MR Address: 0xF8034000 Access: Read/Write  DIVA, DIVB: CLKA, CLKB Divide Factor  PREA, PREB Values which are not listed in the table must be considered as “reserved”. 31 30 29 28 27 26 25 24 –––– PREB 23 22 21 20 19 18 17 16 DIVB 15 14 13 12 11 10 9 8 –––– PREA 76543210 DIVA Value Name Description

0 CLK_OFF CLKA, CLKB clock is turned off

1 CLK_DIV1 CLKA, CLKB clock is clock selected by PREA, PREB

2-255 – CLKA, CLKB clock is clock selected by PREA, PREB divided by DIVA, DIVB factor. Value Name Description

0000 MCK Master Clock

0001 MCKDIV2 Master Clock divided by 2

0010 MCKDIV4 Master Clock divided by 4

0011 MCKDIV8 Master Clock divided by 8

0100 MCKDIV16 Master Clock divided by 16

0101 MCKDIV32 Master Clock divided by 32

0110 MCKDIV64 Master Clock divided by 64

0111 MCKDIV128 Master Clock divided by 128

1000 MCKDIV256 Master Clock divided by 256

1001 MCKDIV512 Master Clock divided by 512

1010 MCKDIV1024 Master Clock divided by 1024

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

38.7.2 PWM Enable Register

Name: PWM_ENA Address: 0xF8034004 Access: Write-only  CHIDx: Channel ID 0 = No effect. 1 = Enable PWM output for channel x.

38.7.3 PWM Disable Register

Name: PWM_DIS Address: 0xF8034008 Access: Write-only  CHIDx: Channel ID 0 = No effect. 1 = Disable PWM output for channel x. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 –––– C HID3 C HID2 C HID1 C HID0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 –––– C HID3 C HID2 C HID1 C HID0

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

38.7.4 PWM Status Register

Name: PWM_SR Address: 0xF803400C Access: Read-only  CHIDx: Channel ID 0 = PWM output for channel x is disabled. 1 = PWM output for channel x is enabled. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 –––– C HID3 C HID2 C HID1 C HID0

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

38.7.5 PWM Interrupt Enable Register

Name: PWM_IER Address: 0xF8034010 Access: Write-only  CHIDx: Channel ID. 0 = No effect. 1 = Enable interrupt for PWM channel x.

38.7.6 PWM Interrupt Disable Register

Name: PWM_IDR Address: 0xF8034014 Access: Write-only  CHIDx: Channel ID. 0 = No effect. 1 = Disable interrupt for PWM channel x. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 –––– C HID3 C HID2 C HID1 C HID0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 –––– C HID3 C HID2 C HID1 C HID0

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

38.7.7 PWM Interrupt Mask Register

Name: PWM_IMR Address: 0xF8034018 Access: Read-only  CHIDx: Channel ID. 0 = Interrupt for PWM channel x is disabled. 1 = Interrupt for PWM channel x is enabled.

38.7.8 PWM Interrupt Status Register

Name: PWM_ISR Address: 0xF803401C Access: Read-only  CHIDx: Channel ID 0 = No new channel period has been achieved since the last read of the PWM_ISR register. 1 = At least one new channel period has been achieved since the last read of the PWM_ISR register. Note: Reading PWM_ISR automatically clears CHIDx flags. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 –––– C HID3 C HID2 C HID1 C HID0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 –––– C HID3 C HID2 C HID1 C HID0

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

38.7.9 PWM Channel Mode Register

Name: PWM_CMR[0..3] Addresses: 0xF8034200 [0], 0xF8034220 [1], 0xF8034240 [2], 0xF8034260 [3] Access: Read/Write  CPRE: Channel Pre-scaler Values which are not listed in the table must be considered as “reserved”.  CALG: Channel Alignment 0 = The period is left aligned. 1 = The period is center aligned.  CPOL: Channel Polarity 0 = The output waveform starts at a low level. 1 = The output waveform starts at a high level. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 –––– CPRE Value Name Description

1011 CLKA Clock A

1100 CLKB Clock B

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12  CPD: Channel Update Period 0 = Writing to the PWM_CUPDx will modify the duty cycle at the next period start event. 1 = Writing to the PWM_CUPDx will modify the period at the next period start event.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

38.7.10 PWM Channel Duty Cycle Register

Name: PWM_CDTY[0..3] Addresses: 0xF8034204 [0], 0xF8034224 [1], 0xF8034244 [2], 0xF8034264 [3] Access: Read/Write Only the first 32 bits (internal channel counter size) are significant.  CDTY: Channel Duty Cycle Defines the waveform duty cycle. This value must be defined between 0 and CPRD (PWM_CPRx). 31 30 29 28 27 26 25 24 CDTY 23 22 21 20 19 18 17 16 CDTY 15 14 13 12 11 10 9 8 CDTY 76543210 CDTY

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

38.7.11 PWM Channel Period Register

Name: PWM_CPRD[0..3] Addresses: 0xF8034208 [0], 0xF8034228 [1], 0xF8034248 [2], 0xF8034268 [3] Access: Read/Write Only the first 32 bits (internal channel counter size) are significant.  CPRD: Channel Period If the waveform is left-aligned, then the output waveform period depends on the counter source clock and can be calculated: – By using the Master Clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). The resulting period formula will be: – By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes, respectively: or If the waveform is center-aligned, then the output waveform period depends on the counter source clock and can be calculated: – By using the Master Clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). The resulting period formula will be: – By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes, respectively: or 31 30 29 28 27 26 25 24 CPRD 23 22 21 20 19 18 17 16 CPRD 15 14 13 12 11 10 9 8 CPRD 76543210 CPRD XC P R D×() CRPD DIVA×()

2 CPRD DIVA× ×()

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

38.7.12 PWM Channel Counter Register

Name: PWM_CCNT[0..3] Addresses: 0xF803420C [0], 0xF803422C [1], 0xF803424C [2], 0xF803426C [3] Access: Read-only  CNT: Channel Counter Register Internal counter value. This register is reset when:

  • the channel is enabled (writing CHIDx in the PWM_ENA register).
  • the counter reaches CPRD value defined in the PWM_ CPRDx register if the waveform is left aligned. 31 30 29 28 27 26 25 24 CNT 23 22 21 20 19 18 17 16 CNT 15 14 13 12 11 10 9 8 CNT 76543210 CNT

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

38.7.13 PWM Channel Update Register

Name: PWM_CUPD[0..3] Addresses: 0xF8034210 [0], 0xF8034230 [1], 0xF8034250 [2], 0xF8034270 [3] Access: Write-only  CUPD: Channel Update Register This register acts as a double buffer for the period or the duty cycle. This prevents an unexpected waveform when modify- ing the waveform period or duty-cycle. Only the first 32 bits (internal channel counter size) are significant. When CPD field of PWM_CMRx register = 0, the duty-cycle (CDTY of PWM_CDTYx register) is updated with the CUPD value at the beginning of the next period. When CPD field of PWM_CMRx register = 1, the period (CPRD of PWM_CPRDx register) is updated with the CUPD value at the beginning of the next period. 31 30 29 28 27 26 25 24 CUPD 23 22 21 20 19 18 17 16 CUPD 15 14 13 12 11 10 9 8 CUPD 76543210 CUPD

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 733 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 39. Two-wire Interface (TWI)

39.1 Description

The Atmel Two-wire Interface (TWI) interconnects components on a unique two-wire bus, made up of one clock line and one data line with speeds of up to 400 Kbits per second, based on a byte-oriented transfer format. It can be used with any Atmel Two-wire Interface bus Serial EEPROM and I²C compatible device such as Real Time Clock (RTC), Dot Matrix/Graphic LCD Controllers and Temperature Sensor, to name but a few. The TWI is programmable as a master or a slave with sequential or single-byte access. Multiple master capability is supported. 20 Arbitration of the bus is performed internally and puts the TWI in slave mode automatically if the bus arbitration is lost. A configurable baud rate generator permits the output data rate to be adapted to a wide range of core clock frequencies. Below, Table 39-1 lists the compatibility level of the Atmel Two-wire Interface in Master Mode and a full I2C compatible device. Note: 1. START + b000000001 + Ack + Sr

39.2 Embedded Characteristics

  • two TWIs
  • Compatible with Atmel Two-wire Interface Serial Memory and I²C Compatible Devices(1)
  • One, Two or Three Bytes for Slave Address
  • Sequential Read-write Operations
  • Master, Multi-master and Slave Mode Operation
  • Bit Rate: Up to 400 Kbits
  • General Call Supported in Slave mode
  • SMBUS Quick Command Supported in Master Mode
  • Connection to DMA Controller (D MAC) Channel Capabilities Optimizes Data Transfers in Master Mode Only Note: 1. See Table 39-1 for details on compatibility with I²C Standard. Table 39-1. Atmel TWI compatibility with I2C Standard I2C Standard Atmel TWI Standard Mode Speed (100 KHz) Supported Fast Mode Speed (400 KHz) Supported 7 or 10 bits Slave Addressing Supported START BYTE(1) Not Supported Repeated Start (Sr) Condition Supported ACK and NACK Management Supported Slope control and input filtering (Fast mode) Not Supported Clock stretching Supported Multi Master Capability Supported

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 734 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

39.3 List of Abbreviations

39.4 Block Diagram

Figure 39-1. Block Diagram Table 39-2. Abbreviations Abbreviation Description TWI Two-wire Interface A Acknowledge NA Non Acknowledge PS top SS tart Sr Repeated Start SADR Slave Address ADR Any address except SADR R Read WW rite APB Bridge PMC MCK Two-wire Interface PIO Interrupt Controller TWI Interrupt TWCK TWD

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 735 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

39.5 Application Block Diagram

Figure 39-2. Application Block Diagram

39.5.1 I/O Lines Description

39.6 Product Dependencies

39.6.1 I/O Lines

Both TWD and TWCK are bidirectional lines, connected to a positive supply voltage via a current source or pull-up resistor (see Figure 39-2 on page 735 ). When the bus is free, both lines are high. The output stages of devices connected to the bus must have an open-drain or open-col- lector to perform the wired-AND function. TWD and TWCK pins may be multiplexed with PI O lines. To enable the TWI, the programmer must perform the following step:

  • Program the PIO controller to dedicate TWD and TWCK as peripheral lines. The user must not program TWD and TWCK as open-drain. It is already done by the hardware. Host with TWI Interface TWD TWCK Atmel TWI Serial EEPROM I²C RTC I²C LCD Controller Slave 1 Slave 2 Slave 3 VDD I²C Temp. Sensor Slave 4 Rp: Pull up value as given by the I²C Standard Rp Rp Table 39-3. I/O Lines Description Pin Name Pin Description Type TWD Two-wire Serial Data Input/Output TWCK Two-wire Serial Clock Input/Output Table 39-4. I/O Lines Instance Signal I/O Line Peripheral TWI0 TWCK0 PA31 A TWI0 TWD0 PA30 A TWI1 TWCK1 PC1 C TWI1 TWD1 PC0 C

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 736 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

39.6.2 Power Management

  • Enable the peripheral clock. The TWI interface may be clocked through the Power Management Controller (PMC), thus the programmer must first configure the PMC to enable the TWI clock.

39.6.3 Interrupt

The TWI interface has an interrupt line connected to the Interrupt Controller. In order to handle interrupts, the Interrupt Controller must be programmed before configuring the TWI.

39.7 Functional Description

39.7.1 Transfer Format

The data put on the TWD line must be 8 bits long. Data is transferred MSB first; each byte must be followed by an acknowledgement. The number of bytes per transfer is unlimited (see Figure 39-4). Each transfer begins with a START condition and terminates with a STOP condition (see Figure 39-3).

  • A high-to-low transition on the TWD line while TWCK is high defines the START condition.
  • A low-to-high transition on the TWD line while TWCK is high defines a STOP condition. Figure 39-3. START and STOP Conditions Figure 39-4. Transfer Format

39.7.2 Modes of Operation

The TWI has different modes of operations:

  • Master transmitter mode
  • Master receiver mode Table 39-5. Peripheral IDs Instance ID TWI0 9 TWI1 10 TWD TWCK Start Stop TWD TWCK Start Address R/W Ack Data Ack Data Ack Stop

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 737 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

  • Multi-master transmitter mode
  • Multi-master receiver mode
  • Slave transmitter mode
  • Slave receiver mode These modes are described in the following chapters.

39.8 Master Mode

39.8.1 Definition

The Master is the device that starts a transfer, generates a clock and stops it.

39.8.2 Application Block Diagram

Figure 39-5. Master Mode Typical Application Block Diagram

39.8.3 Programming Master Mode

The following registers have to be programmed before entering Master mode: 1. DADR (+ IADRSZ + IADR if a 10 bit device is addressed): The device address is used to access slave devices in read or write mode. 2. CKDIV + CHDIV + CLDIV: Clock Waveform. 3. SVDIS: Disable the slave mode. 4. MSEN: Enable the master mode.

39.8.4 Master Transmitter Mode

After the master initiates a Start condition when writing into the Tran smit Holding Register, TWI_THR, it sends a 7-bit slave address, configured in the Master Mode register (DADR in TWI_MMR), to notify the slave device. The bit following the slave address indicates the transfer direction, 0 in this case (MREAD = 0 in TWI_MMR). The TWI transfers require the slave to acknowledge each received byte. During the acknowl- edge clock pulse (9th pulse), the master releases the data line (HIGH), enabling the slave to pull it down in order to generate the acknowledge. The master polls the data line during this clock pulse and sets the Not Acknowledge bit ( NACK) in the status register if the slave does not Host with TWI Interface TWD TWCK Atmel TWI Serial EEPROM I²C RTC I²C LCD Controller Slave 1 Slave 2 Slave 3 VDD I²C Temp. Sensor Slave 4 Rp: Pull up value as given by the I²C Standard Rp Rp

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 739 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Figure 39-8. Master Write with One Byte Internal Address and Multiple Data Bytes

39.8.5 Master Receiver Mode

The read sequence begins by setting the START bit. After the start condition has been sent, the master sends a 7-bit slave address to notify the slave device. The bit following the slave address indicates the transfer direction, 1 in this ca se (MREAD = 1 in TWI_MMR). During the acknowl- edge clock pulse (9th pulse), the master releases the data line (HIGH), enabling the slave to pull it down in order to generate the acknowledge. The master polls the data line during this clock pulse and sets the NACK bit in the status register if the slave does not acknowledge the byte. If an acknowledge is received, the master is then ready to receive data from the slave. After data has been received, the master sends an acknowle dge condition to notify the slave that the data has been received except for the last data, after the stop condition. See Figure 39-9. When the RXRDY bit is set in the status register, a character has been received in the receive-holding reg- ister (TWI_RHR). The RXRDY bit is reset when reading the TWI_RHR. When a single data byte read is performed, with or without internal address (IADR), the START and STOP bits must be set at the same time. See Figure 39-9. When a multiple data byte read is performed, with or without internal address (IADR), the STOP bit must be set after the next-to- Figure 39-9. Master Read with One Data Byte A DATA n AS DADR W DATA n+1 A PDATA n+2 A TXCOMP TXRDY Write THR (Data n) Write THR (Data n+1) Write THR (Data n+2) Last data sent STOP command performed (by writing in the TWI_CR) TWD IADR A TWCK AS DADR R DATA N P TXCOMP Write START & STOP Bit RXRDY Read RHR TWD

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 740 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Figure 39-10. Master Read with Multiple Data Bytes

39.8.6 Internal Address

The TWI interface can perform various transfe r formats: Transfers with 7-bit slave address devices and 10-bit slave address devices. 39.8.6.1 7-bit Slave Addressing When Addressing 7-bit slave devices, the internal address bytes are used to perform random address (read or write) accesses to reach one or more data bytes, within a memory page loca- tion in a serial memory, for example. When performing read operations with an internal address, the TWI performs a write operation to set the internal address into the slave device, and then switch to Master Receiver mode. Note that the second start condition (after sending the IADR) is sometimes called “repeated start” (Sr) in I 2C fully-compatible devices. See Figure 39-12. See Figure 39-11 and Figure 39-13 for Master Write operation with internal address. The three internal address bytes are configurable through the Master Mode register (TWI_MMR). If the slave device supports only a 7-bit address, i.e. no internal address, IADRSZ must be set to In the figures below the following abbreviations are used: NAS DADR R DATA n A A DATA (n+1) A DATA (n+m)DATA (n+m)-1 PTWD TXCOMP Write START Bit RXRDY Write STOP Bit after next-to-last data read Read RHR DATA n Read RHR DATA (n+1) Read RHR DATA (n+m)-1 Read RHR DATA (n+m)

  • S Start
  • S r Repeated Start
  • P Stop
  • W Write
  • R Read
  • A Acknowledge
  • N Not Acknowledge
  • D A D R Device Address
  • I A D R Internal Address

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 742 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

39.8.7 Using the DMA Controller (DMAC)

The use of the DMAC significantly reduces the CPU load. To assure correct implementation, respect the following programming sequence. 1. Initialize the DMAC (channels, memory pointers, size, etc.); 2. Configure the master mode (DADR, CKDIV, etc.). 3. Enable the DMAC. 4. Wait for the DMAC flag. 5. Disable the DMAC.

39.8.8 SMBUS Quick Command (Master Mode Only)

The TWI interface can perform a Quick Command: 1. Configure the master mode (DADR, CKDIV, etc.). 2. Write the MREAD bit in the TWI_MMR register at the value of the one-bit command to be sent. 3. Start the transfer by setting the QUICK bit in the TWI_CR. Figure 39-14. SMBUS Quick Command

39.8.9 Read-write Flowcharts

The following flowcharts shown in Figure 39-16 on page 744, Figure 39-17 on page 745, Figure 39-18 on page 746, Figure 39-19 on page 747 and Figure 39-20 on page 748 give examples for read and write operations. A polling or interrupt method can be used to check the status bits. The interrupt method requires that the interrupt enable register (TWI_IER) be configured first. TXCOMP TXRDY Write QUICK command in TWI_CR TWD AS DADR R/W P

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 743 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Figure 39-15. TWI Write Operation with Single Data Byte without Internal Address Set TWI clock (CLDIV, CHDIV, CKDIV) in TWI_CWGR (Needed only once) Set the Control register: - Master enable TWI_CR = MSEN + SVDIS Set the Master Mode register: - Device slave address (DADR) - Transfer direction bit Write ==> bit MREAD = 0 Load Transmit register TWI_THR = Data to send Read Status register TXRDY = 1? Read Status register TXCOMP = 1? Transfer finished Ye s Ye s BEGIN No No Write STOP Command TWI_CR = STOP

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 744 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Figure 39-16. TWI Write Operation with Single Data Byte and Internal Address BEGIN Set TWI clock (CLDIV, CHDIV, CKDIV) in TWI_CWGR (Needed only once) Set the Control register: - Master enable TWI_CR = MSEN + SVDIS Set the Master Mode register: - Device slave address (DADR) - Internal address size (IADRSZ) - Transfer direction bit Write ==> bit MREAD = 0 Load transmit register TWI_THR = Data to send Read Status register TXRDY = 1? Read Status register TXCOMP = 1? Transfer finished Set the internal address TWI_IADR = address Yes Yes No No Write STOP command TWI_CR = STOP

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 745 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Figure 39-17. TWI Write Operation with Multiple Data Bytes with or without Internal Address Set the Control register: - Master enable TWI_CR = MSEN + SVDIS Set the Master Mode register: - Device slave address - Internal address size (if IADR used) - Transfer direction bit Write ==> bit MREAD = 0 Internal address size = 0? Load Transmit register TWI_THR = Data to send Read Status register TXRDY = 1? Data to send? Read Status register TXCOMP = 1? END BEGIN Set the internal address TWI_IADR = address Ye s TWI_THR = data to send Ye s Ye s Ye s No No No Write STOP Command TWI_CR = STOP Set TWI clock (CLDIV, CHDIV, CKDIV) in TWI_CWGR (Needed only once)

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 746 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Figure 39-18. TWI Read Operation with Single Data Byte without Internal Address Set the Control register: - Master enable TWI_CR = MSEN + SVDIS Set the Master Mode register: - Device slave address - Transfer direction bit Read ==> bit MREAD = 1 Start the transfer TWI_CR = START | STOP Read status register RXRDY = 1? Read Status register TXCOMP = 1? END BEGIN Ye s Ye s Set TWI clock (CLDIV, CHDIV, CKDIV) in TWI_CWGR (Needed only once) Read Receive Holding Register No No

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 747 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Figure 39-19. TWI Read Operation with Single Data Byte and Internal Address Set the Control register: - Master enable TWI_CR = MSEN + SVDIS Set the Master Mode register: - Device slave address - Internal address size (IADRSZ) - Transfer direction bit Read ==> bit MREAD = 1 Read Status register TXCOMP = 1? END BEGIN Ye s Set TWI clock (CLDIV, CHDIV, CKDIV) in TWI_CWGR (Needed only once) Ye s Set the internal address TWI_IADR = address Start the transfer TWI_CR = START | STOP Read Status register RXRDY = 1? Read Receive Holding register No No

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 748 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Figure 39-20. TWI Read Operation with Multiple Data Bytes with or without Internal Address Internal address size = 0? Start the transfer TWI_CR = START Stop the transfer TWI_CR = STOP Read Status register RXRDY = 1? Last data to read but one? Read status register TXCOMP = 1? END Set the internal address TWI_IADR = address Ye s Ye s Ye s No Ye s Read Receive Holding register (TWI_RHR) No Set the Control register: - Master enable TWI_CR = MSEN + SVDIS Set the Master Mode register: - Device slave address - Internal address size (if IADR used) - Transfer direction bit Read ==> bit MREAD = 1 BEGIN Set TWI clock (CLDIV, CHDIV, CKDIV) in TWI_CWGR (Needed only once) No Read Status register RXRDY = 1? Ye s Read Receive Holding register (TWI_RHR) No

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 749 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

39.9 Multi-master Mode

39.9.1 Definition

More than one master may handle the bus at the same time without data corruption by using arbitration. Arbitration starts as soon as two or more masters place information on the bus at the same time, and stops (arbitration is lost) for the master that intends to send a logical one while the other master sends a logical zero. As soon as arbitration is lost by a master, it stops sending data and listens to the bus in order to detect a stop. When the stop is detected, the master who has lost arbitration may put its data on the bus by respecting arbitration. Arbitration is illustrated in Figure 39-22 on page 750.

39.9.2 Different Multi-master Modes

Two multi-master modes may be distinguished: 1. TWI is considered as a Master only and will never be addressed. 2. TWI may be either a Master or a Slave and may be addressed. Note: In both Multi-master modes arbitration is supported.

39.9.2.1 TWI as Master Only

In this mode, TWI is considered as a Master only (MSEN is always at one) and must be driven like a Master with the ARBLST (ARBitration Lost) flag in addition. If arbitration is lost (ARBLST = 1), the programmer must reinitiate the data transfer. If the user starts a transfer (ex.: DADR + START + W + Write in THR) and if the bus is busy, the TWI automatically waits for a STOP conditi on on the bus to initiate the transfer (see Figure 39- 21 on page 750). Note: The state of the bus (busy or free) is not indicated in the user interface.

39.9.2.2 TWI as Master or Slave

The automatic reversal from Master to Slave is not supported in case of a lost arbitration. Then, in the case where TWI may be either a Master or a Slave, the programmer must manage the pseudo Multi-master mode described in the steps below. 1. Program TWI in Slave mode (SADR + MS DIS + SVEN) and perform Slave Access (if TWI is addressed). 2. If TWI has to be set in Master mode, wait until TXCOMP flag is at 1. 3. Program Master mode (DADR + SVDIS + MSEN ) and start the transfer (ex: START + Write in THR). 4. As soon as the Master mode is enabled, TWI scans the bus in order to detect if it is busy or free. When the bus is considered as free, TWI initiates the transfer. 5. As soon as the transfer is initiated and until a STOP condition is sent, the arbitration becomes relevant and the user must monitor the ARBLST flag. 6. If the arbitration is lost (ARBLST is set to 1), the user must program the TWI in Slave mode in the case where the Master that won the arbitration wanted to access the TWI. 7. If TWI has to be set in Slave mode, wait until TXCOMP flag is at 1 and then program the Slave mode.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 751 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Figure 39-23. Multi-master Flowchart Programm the SLAVE mode: SADR + MSDIS + SVEN SVACC = 1 ? TXCOMP = 1 ? GACC = 1 ? Decoding of the programming sequence Prog seq OK ? Change SADR SVREAD = 1 ? Read Status Register RXRDY= 1 ? Read TWI_RHR TXRDY= 1 ?EOSACC = 1 ? Write in TWI_THR Need to perform a master access ? Program the Master mode DADR + SVDIS + MSEN + CLK + R / W Read Status Register ARBLST = 1 ? MREAD = 1 ? TXRDY= 0 ? Write in TWI_THRData to send ? RXRDY= 0 ? Read TWI_RHR Data to read? Read Status Register TXCOMP = 0 ? GENERAL CALL TREATMENT Ye s Ye s Ye s Ye s Ye s Ye s Ye s Ye s Ye s Ye s Ye s Ye s Ye s Ye s Stop Transfer TWI_CR = STOP No No No No No No No No No No No No No No No No START

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 752 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

39.10 Slave Mode

39.10.1 Definition

The Slave Mode is defined as a mode where the device receives the clock and the address from another device called the master. In this mode, the device never initiates and never completes the transmission (START, REPEATED_START and STOP conditions are always provided by the master).

39.10.2 Application Block Diagram

Figure 39-24. Slave Mode Typical Application Block Diagram

39.10.3 Programming Slave Mode

The following fields must be programmed before entering Slave mode: 1. SADR (TWI_SMR): The slave device address is used in order to be accessed by mas- ter devices in read or write mode. 2. MSDIS (TWI_CR): Disable the master mode. 3. SVEN (TWI_CR): Enable the slave mode. As the device receives the clock, values written in TWI_CWGR are not taken into account.

39.10.4 Receiving Data

After a Start or Repeated Start condition is detected and if the address sent by the Master matches with the Slave address programmed in the SADR (Slave ADdress) field, SVACC (Slave ACCess) flag is set and SVREAD (Slave READ) indicates the direction of the transfer. SVACC remains high until a STOP condition or a repeated START is detected. When such a condition is detected, EOSACC (End Of Slave ACCess) flag is set.

39.10.4.1 Read Sequence

In the case of a Read sequence (SVREAD is high), TWI transfers data written in the TWI_THR (TWI Transmit Holding Register) until a STOP condition or a REPEATED _START + an address different from SADR is detected. Note that at the end of the read sequence TXCOMP (Transmis- sion Complete) flag is set and SVACC reset. As soon as data is written in the TWI_THR, TXRDY (Transmit Holding Register Ready) flag is reset, and it is set when the shift register is empty and the sent data acknowledged or not. If the data is not acknowledged, the NACK flag is set. Host with TWI Interface TWD TWCK LCD Controller Slave 1 Slave 2 Slave 3 RR VDD Host with TWI Interface Host with TWI Interface Master

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 753 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Note that a STOP or a repeated START always follows a NACK. See Figure 39-25 on page 754.

39.10.4.2 Write Sequence

In the case of a Write sequence (SVREAD is low), the RXRDY (Receive Holding Register Ready) flag is set as soon as a character has been received in the TWI_RHR (TWI Receive Holding Register). RXRDY is reset when reading the TWI_RHR. TWI continues receiving data until a STOP condition or a REPEATED_START + an address dif- ferent from SADR is detected. Note that at the end of the write sequence TXCOMP flag is set and SVACC reset. See Figure 39-26 on page 754.

39.10.4.3 Clock Synchronization Sequence

In the case where TWI_THR or TWI_RHR is not written/read in time, TWI performs a clock synchronization. Clock stretching information is given by the SCLWS (Clock Wait state) bit. See Figure 39-28 on page 756 and Figure 39-29 on page 757.

39.10.4.4 General Call

In the case where a GENERAL CALL is performed, GACC (General Call ACCess) flag is set. After GACC is set, it is up to the programmer to interpret the meaning of the GENERAL CALL and to decode the new address programming sequence. See Figure 39-27 on page 755.

39.10.5 Data Transfer

39.10.5.1 Read Operation

The read mode is defined as a data requirement from the master. After a START or a REPEATED START condition is detected, the decoding of the address starts. If the slave address (SADR) is decoded, SVACC is set and SVREAD indicates the direc- tion of the transfer. Until a STOP or REPEATED START condition is detected, TWI continues sending data loaded in the TWI_THR register. If a STOP condition or a REPEATED START + an address different from SADR is detected, SVACC is reset. Figure 39-25 on page 754 describes the write operation.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 754 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Figure 39-25. Read Access Ordered by a MASTER Notes: 1. When SVACC is low, the state of SVREAD becomes irrelevant. 2. TXRDY is reset when data has been transmitted from TWI_THR to the shift register and set when this data has been acknowledged or non acknowledged.

39.10.5.2 Write Operation

The write mode is defined as a data transmission from the master. After a START or a REPEATED START, the decoding of the address starts. If the slave address is decoded, SVACC is set and SVREAD indicates the direction of the transfer (SVREAD is low in this case). Until a STOP or REPEATED START condition is detected, TWI stores the received data in the TWI_RHR register. If a STOP condition or a REPEATED START + an address different from SADR is detected, SVACC is reset. Figure 39-26 on page 754 describes the Write operation. Figure 39-26. Write Access Ordered by a MasterNotes: 1. When SVACC is low, the state of SVREAD becomes irrelevant. 2. RXRDY is set when data has been transmitted from the shift register to the TWI_RHR and reset when this data is read. Write THR Read RHR SVREAD has to be taken into account only while SVACC is active TWD TXRDY NACK SVACC SVREAD EOSVACC SADRS ADR R NA R A DATA A A DATA NA S/SrDATA NA P/S/Sr SADR matches, TWI answers with an ACK SADR does not match, TWI answers with a NACK ACK/NACK from the Master RXRDY Read RHR SVREAD has to be taken into account only while SVACC is active TWD SVACC SVREAD EOSVACC SADR does not match, TWI answers with a NACK SADRS ADR W NA W A DATA A A DATA NA S/SrDATA NA P/S/Sr SADR matches, TWI answers with an ACK

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 755 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

39.10.5.3 General Call

The general call is performed in order to change the address of the slave. If a GENERAL CALL is detected, GACC is set. After the detection of General Call, it is up to the programmer to decode the commands which come afterwards. In case of a WRITE command, the programmer has to decode the programming sequence and program a new SADR if the programming sequence matches. Figure 39-27 on page 755 describes the General Call access. Figure 39-27. Master Performs a General Call Note: This method allows the user to create an own programming sequence by choosing the program- ming bytes and the number of them. The programming sequence has to be provided to the master. 0000000 + W GENERAL CALL PS AGENERAL CALL Reset or write DADD A New SADRDATA1 A DATA2 AA New SADR Programming sequence TXD GCACC SVACC RESET command = 00000110X WRITE command = 00000100X Reset after read

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 756 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

39.10.5.4 Clock Synchronization

In both read and write modes, it may happen that TWI_THR/TW I_RHR buffer is not filled /emp- tied before the emission/reception of a new charac ter. In this case, to avoid sending/receiving undesired data, a clock stretching mechanism is implemented. Clock Synchronization in Read Mode The clock is tied low if the shift register is empty and if a STOP or REPEATED START condition was not detected. It is tied low until the shift register is loaded. Figure 39-28 on page 756 describes the clock synchronization in Read mode. Figure 39-28. Clock Synchronization in Read Mode Notes: 1. TXRDY is reset when data has been written in the TWI_ THR to the shift register and set when this data has been acknowl- edged or non acknowledged. 2. At the end of the read sequence, TXCOMP is set after a STOP or after a REPEATED_START + an address different from SADR. 3. SCLWS is automatically set when the cl ock synchronization mechanism is started. DATA1 The clock is stretched after the ACK, the state of TWD is undefined during clock stretching SCLWS SVACC SVREAD TXRDY TWCK TWI_THR TXCOMP The data is memorized in TWI_THR until a new value is written TWI_THR is transmitted to the shift register Ack or Nack from the master DATA0 DATA0 DATA2 CLOCK is tied low by the TWI as long as THR is empty S SADRS R DATA0A A DATA1 A DATA2 NA SXXXXXXX Write THR As soon as a START is detected

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 757 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Clock Synchronization in Write Mode The clock is tied low if the shift regi ster and the TWI_RHR is full. If a STOP or REPEATED_START condition was not detected, it is tied low until TWI_RHR is read. Figure 39-29 on page 757 describes the clock synchronization in Read mode. Figure 39-29. Clock Synchronization in Write Mode Notes: 1. At the end of the read sequence, TXCOMP is set after a STOP or after a REPEATED_START + an address different from SADR. 2. SCLWS is automatically set when the cl ock synchronization mechanism is started and automatically reset when the mecha- nism is finished.

39.10.5.5 Reversal after a Repeated Start

The master initiates the communication by a read command and finishes it by a write command. Figure 39-30 on page 757 describes the repeated start + reversal from Read to Write mode. Figure 39-30. Repeated Start + Reversal from Read to Write Mode 1. TXCOMP is only set at the end of the transmission because after the repeated start, SADR is detected again. Rd DATA0 Rd DATA1 Rd DATA2 SVACC SVREAD RXRDY SCLWS TXCOMP DATA1 DATA2 SCL is stretched on the last bit of DATA1 As soon as a START is detected TWCK TWD TWI_RHR CLOCK is tied low by the TWI as long as RHR is full DATA0 is not read in the RHR ADRS SADR W ADATA0A A DATA2DATA1 SNA S SADR R ADATA0A DATA1 SADRSrNA W A DATA2 A DATA3 A P Cleared after read DATA0 DATA1 DATA2 DATA3 SVACC SVREAD TWD TWI_THR TWI_RHR EOSACC TXRDY RXRDY TXCOMP As soon as a START is detected

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 758 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Reversal of Write to Read The master initiates the communication by a write command and finishes it by a read command. Figure 39-31 on page 758 describes the repeated start + reversal from Write to Read mode. Figure 39-31. Repeated Start + Reversal from Write to Read Mode Notes: 1. In this case, if TWI_THR has not bee n written at the end of the read command, the clock is automatically stretched before the ACK. 2. TXCOMP is only set at the end of the transmission because after the repeated start, SADR is detected again.

39.10.6 Read Write Flowcharts

The flowchart shown in Figure 39-32 on page 759 gives an example of read and write operations in Slave mode. A polling or interrupt method can be used to check the status bits. The interrupt method requires that the interrupt enable register (TWI_IER) be configured first. S SADR W ADATA0A DATA1 SADRSrA R A DATA2 A DATA3 NA P Cleared after read DATA0 DATA2 DATA3 DATA1 TXCOMP TXRDY RXRDY As soon as a START is detected Read TWI_RHR SVACC SVREAD TWD TWI_RHR TWI_THR EOSACC

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 759 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Figure 39-32. Read Write Flowchart in Slave Mode Set the SLAVE mode: SADR + MSDIS + SVEN SVACC = 1 ? TXCOMP = 1 ? GACC = 1 ? Decoding of the programming sequence Prog seq OK ? Change SADR SVREAD = 0 ? Read Status Register RXRDY= 0 ? Read TWI_RHR TXRDY= 1 ?EOSACC = 1 ? Write in TWI_THR END GENERAL CALL TREATMENT No No No No No No No No

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 760 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

39.11 Two-wire Interface (TWI) User Interface

Note: 1. All unlisted offset values are considered as “reserved”. Table 39-6. Register Mapping Offset Register Name Access Reset 0x00 Control Register TWI_CR Write-only N / A 0x04 Master Mode Register TWI_MMR Read-write 0x00000000 0x08 Slave Mode Register TWI_SMR Read-write 0x00000000 0x0C Internal Address Register TWI_IADR Read-write 0x00000000 0x10 Clock Waveform Generator Register TWI_CWGR Read-write 0x00000000 0x14 - 0x1C Reserved – – – 0x20 Status Register TWI_SR Read-only 0x0000F009 0x24 Interrupt Enable Register TWI_IER Write-only N / A 0x28 Interrupt Disable Register TWI_IDR Write-only N / A 0x2C Interrupt Mask Register TWI_IMR Read-only 0x00000000 0x30 Receive Holding Register TWI_RHR Read-only 0x00000000 0x34 Transmit Holding Register TWI_THR Write-only 0x00000000 0xEC - 0xFC(1) Reserved – – –

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 761 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

39.11.1 TWI Control Register

Name: TWI_CR Address: 0xF8010000 (0), 0xF8014000 (1) Access: Write-only Reset: 0x00000000  START: Send a START Condition 0 = No effect. 1 = A frame beginning with a START bit is transmitted according to the features defined in the mode register. This action is necessary when the TWI peripheral wants to read data from a slave. When configured in Master Mode with a write operation, a frame is sent as soon as the user writes a character in the Transmit Holding Register (TWI_THR).  STOP: Send a STOP Condition 0 = No effect. 1 = STOP Condition is sent just after completing the current byte transmission in master read mode. – In single data byte master read, the START and STOP must both be set. – In multiple data bytes master read, the STOP must be set after the last data received but one. – In master read mode, if a NACK bit is received, the STOP is automatically performed. – In master data write operation, a STOP condition will be sent after the transmission of the current data is finished.  MSEN: TWI Master Mode Enabled 0 = No effect. 1 = If MSDIS = 0, the master mode is enabled. Note: Switching from Slave to Master mo de is only permitted when TXCOMP = 1.  MSDIS: TWI Master Mode Disabled 0 = No effect. 1 = The master mode is disabled, all pending data is transmitted. The shifter and holding characters (if it contains data) are transmitted in case of write operation. In read operation, the character being transferred must be completely received before disabling. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 SWRST QUICK SVDIS SVEN MSDIS MSEN STOP START

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 762 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12  SVEN: TWI Slave Mode Enabled 0 = No effect. 1 = If SVDIS = 0, the slave mode is enabled. Note: Switching from Master to Slave mode is only permitted when TXCOMP = 1.  SVDIS: TWI Slave Mode Disabled 0 = No effect. 1 = The slave mode is disabled. The shifter and holding characters (if it contains data) are transmitted in case of read oper- ation. In write operation, the character being transferred must be completely received before disabling.  QUICK: SMBUS Quick Command 0 = No effect. 1 = If Master mode is enabled, a SMBUS Quick Command is sent.  SWRST: Software Reset 0 = No effect. 1 = Equivalent to a system reset.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 763 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

39.11.2 TWI Master Mode Register

Name: TWI_MMR Address: 0xF8010004 (0), 0xF8014004 (1) Access: Read-write Reset: 0x00000000  IADRSZ: Internal Device Address Size  MREAD: Master Read Direction 0 = Master write direction. 1 = Master read direction.  DADR: Device Address The device address is used to access slave devices in read or write mode. Those bits are only used in Master mode. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 –D ADR 15 14 13 12 11 10 9 8 76543210 Value Name Description

0 NONE No internal device address

1 1_BYTE One-byte internal device address 2 2_BYTE Two-byte internal device address 3 3_BYTE Three-byte internal device address

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 764 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

39.11.3 TWI Slave Mode Register

Name: TWI_SMR Address: 0xF8010008 (0), 0xF8014008 (1) Access: Read-write Reset: 0x00000000  SADR: Slave Address The slave device address is used in Slave mode in order to be accessed by master devices in read or write mode. SADR must be programmed before enabling the Slave mode or after a general call. Writes at other times have no effect. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 –S ADR 15 14 13 12 11 10 9 8 76543210

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 765 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

39.11.4 TWI Internal Address Register

Name: TWI_IADR Address: 0xF801000C (0), 0xF801400C (1) Access: Read-write Reset: 0x00000000  IADR: Internal Address 0, 1, 2 or 3 bytes depending on IADRSZ. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 IADR 15 14 13 12 11 10 9 8 IADR 76543210 IADR

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 766 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

39.11.5 TWI Clock Waveform Generator Register

Name: TWI_CWGR Address: 0xF8010010 (0), 0xF8014010 (1) Access: Read-write Reset: 0x00000000 TWI_CWGR is only used in Master mode.  CLDIV: Clock Low Divider The SCL low period is defined as follows:  CHDIV: Clock High Divider The SCL high period is defined as follows:  CKDIV: Clock Divider The CKDIV is used to increase both SCL high and low periods. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CKDIV 15 14 13 12 11 10 9 8 CHDIV 76543210 CLDIV Tlow CLDIV( 2CKDIV×() 4 )+ TMCK×= Thigh CHDIV( 2CKDIV×() 4 )+ TMCK×=

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 767 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

39.11.6 TWI Status Register

Name: TWI_SR Address: 0xF8010020 (0), 0xF8014020 (1) Access: Read-only Reset: 0x0000F009  TXCOMP: Transmission Completed (automatically set / reset) TXCOMP used in Master mode: 0 = During the length of the current frame. 1 = When both holding and shifter registers are empty and STOP condition has been sent. TXCOMP behavior in Master mode can be seen in Figure 39-8 on page 739 and in Figure 39-10 on page 740. TXCOMP used in Slave mode 0 = As soon as a Start is detected. 1 = After a Stop or a Repeated Start + an address different from SADR is detected. TXCOMP behavior in Slave mode can be seen in Figure 39-28 on page 756 , Figure 39-29 on page 757 , Figure 39-30 on page 757 and Figure 39-31 on page 758.  RXRDY: Receive Holding Register Ready (automatically set / reset) 0 = No character has been received since the last TWI_RHR read operation. 1 = A byte has been received in the TWI_RHR since the last read. RXRDY behavior in Master mode can be seen in Figure 39-10 on page 740. RXRDY behavior in Slave mode can be seen in Figure 39-26 on page 754 , Figure 39-29 on page 757 , Figure 39-30 on page 757 and Figure 39-31 on page 758.  TXRDY: Transmit Holding Register Ready (automatically set / reset) TXRDY used in Master mode 0 = The transmit holding register has not been transferred into shift register. Set to 0 when writing into TWI_THR register. 1 = As soon as a data byte is transferred from TWI_THR to inte rnal shifter or if a NACK error is detected, TXRDY is set at the same time as TXCOMP and NACK. TXRDY is also set when MSEN is set (enable TWI). TXRDY behavior in Master mode can be seen in Figure 39-8 on page 739. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 EOSACC SCLWS ARBLST NACK 76543210 – OVRE GACC SVACC SVREAD TXRDY RXRDY TXCOMP

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 768 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 TXRDY used in Slave mode: 0 = As soon as data is written in the TWI_THR, until this data has been transmitted and acknowledged (ACK or NACK). 1 = It indicates that the TWI_THR is empty and that data has been transmitted and acknowledged. If TXRDY is high and if a NACK has been detected, the tr ansmission will be stopped. Thus when TRDY = NACK = 1, the programmer must not fill TWI_THR to avoid losing it. TXRDY behavior in Slave mode can be seen in Figure 39-25 on page 754, Figure 39-28 on page 756, Figure 39-30 on page 757 and Figure 39-31 on page 758.  SVREAD: Slave Read (automatically set / reset) This bit is only used in Slave mode. When SVACC is low (no Slave access has been detected) SVREAD is irrelevant. 0 = Indicates that a write access is performed by a Master. 1 = Indicates that a read access is performed by a Master. SVREAD behavior can be seen in Figure 39-25 on page 754 , Figure 39-26 on page 754 , Figure 39-30 on page 757 and Figure 39-31 on page 758.  SVACC: Slave Access (automatically set / reset) This bit is only used in Slave mode. 0 = TWI is not addressed. SVACC is automatically cleared after a NACK or a STOP condition is detected. 1 = Indicates that the address decoding sequence has matched (A Master has sent SADR). SVACC remains high until a NACK or a STOP condition is detected. SVACC behavior can be seen in Figure 39-25 on page 754, Figure 39-26 on page 754, Figure 39-30 on page 757 and Fig- ure 39-31 on page 758.  GACC: General Call Access (clear on read) This bit is only used in Slave mode. 0 = No General Call has been detected. 1 = A General Call has been detected. After the detection of General Call, if need be, the programmer may acknowledge this access and decode the following bytes and respond according to the value of the bytes. GACC behavior can be seen in Figure 39-27 on page 755.  OVRE: Overrun Error (clear on read) This bit is only used in Master mode. 0 = TWI_RHR has not been loaded while RXRDY was set 1 = TWI_RHR has been loaded while RXRDY was set. Reset by read in TWI_SR when TXCOMP is set.  NACK: Not Acknowledged (clear on read) NACK used in Master mode 0 = Each data byte has been correctly received by the far-end side TWI slave component. 1 = A data byte has not been acknowledged by the slave component. Set at the same time as TXCOMP.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 769 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 NACK used in Slave Read mode: 0 = Each data byte has been correctly received by the Master. 1 = In read mode, a data byte has not been acknowledged by the Master. When NACK is set the programmer must not fill TWI_THR even if TXRDY is set, because it means that the Master will stop the data transfer or re initiate it. Note that in Slave Write mode all data are acknowledged by the TWI.  ARBLST: Arbitration Lost (clear on read) This bit is only used in Master mode. 0: Arbitration won. 1: Arbitration lost. Another master of the TWI bus has won the multi-master arbitration. TXCOMP is set at the same time.  SCLWS: Clock Wait State (automatically set / reset) This bit is only used in Slave mode. 0 = The clock is not stretched. 1 = The clock is stretched. TWI_THR / TWI_RHR buffer is not filled / emptied before the emission / reception of a new character. SCLWS behavior can be seen in Figure 39-28 on page 756 and Figure 39-29 on page 757.  EOSACC: End Of Slave Access (clear on read) This bit is only used in Slave mode. 0 = A slave access is being performing. 1 = The Slave Access is finished. End Of Slave Access is automatically set as soon as SVACC is reset. EOSACC behavior can be seen in Figure 39-30 on page 757 and Figure 39-31 on page 758

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 770 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

39.11.7 TWI Interrupt Enable Register

Name: TWI_IER Address: 0xF8010024 (0), 0xF8014024 (1) Access: Write-only Reset: 0x00000000  TXCOMP: Transmission Completed Interrupt Enable  RXRDY: Receive Holding Register Ready Interrupt Enable  TXRDY: Transmit Holding Register Ready Interrupt Enable  SVACC: Slave Access Interrupt Enable  GACC: General Call Access Interrupt Enable  OVRE: Overrun Error Interrupt Enable  NACK: Not Acknowledge Interrupt Enable  ARBLST: Arbitration Lost Interrupt Enable  SCL_WS: Clock Wait State Interrupt Enable  EOSACC: End Of Slave Access Interrupt Enable 0 = No effect. 1 = Enables the corresponding interrupt. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 EOSACC SCL_WS ARBLST NACK 76543210 – OVRE GACC SVACC – TXRDY RXRDY TXCOMP

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 771 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

39.11.8 TWI Interrupt Disable Register

Name: TWI_IDR Address: 0xF8010028 (0), 0xF8014028 (1) Access: Write-only Reset: 0x00000000  TXCOMP: Transmission Completed Interrupt Disable  RXRDY: Receive Holding Register Ready Interrupt Disable  TXRDY: Transmit Holding Register Ready Interrupt Disable  SVACC: Slave Access Interrupt Disable  GACC: General Call Access Interrupt Disable  OVRE: Overrun Error Interrupt Disable  NACK: Not Acknowledge Interrupt Disable  ARBLST: Arbitration Lost Interrupt Disable  SCL_WS: Clock Wait State Interrupt Disable  EOSACC: End Of Slave Access Interrupt Disable 0 = No effect. 1 = Disables the corresponding interrupt. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 EOSACC SCL_WS ARBLST NACK 76543210 – OVRE GACC SVACC – TXRDY RXRDY TXCOMP

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 772 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

39.11.9 TWI Interrupt Mask Register

Name: TWI_IMR Address: 0xF801002C (0), 0xF801402C (1) Access: Read-only Reset: 0x00000000  TXCOMP: Transmission Completed Interrupt Mask  RXRDY: Receive Holding Register Ready Interrupt Mask  TXRDY: Transmit Holding Register Ready Interrupt Mask  SVACC: Slave Access Interrupt Mask  GACC: General Call Access Interrupt Mask  OVRE: Overrun Error Interrupt Mask  NACK: Not Acknowledge Interrupt Mask  ARBLST: Arbitration Lost Interrupt Mask  SCL_WS: Clock Wait State Interrupt Mask  EOSACC: End Of Slave Access Interrupt Mask 0 = The corresponding interrupt is disabled. 1 = The corresponding interrupt is enabled. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 EOSACC SCL_WS ARBLST NACK 76543210 – OVRE GACC SVACC – TXRDY RXRDY TXCOMP

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 773 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

39.11.10 TWI Receive Holding Register

Name: TWI_RHR Address: 0xF8010030 (0), 0xF8014030 (1) Access: Read-only Reset: 0x00000000  RXDATA: Master or Slave Receive Holding Data 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 RXDATA

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 774 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

39.11.11 TWI Transmit Holding Register

Name: TWI_THR Address: 0xF8010034 (0), 0xF8014034 (1) Access: Read-write Reset: 0x00000000  TXDATA: Master or Slave Transmit Holding Data 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 TXDATA

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 775 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 40. Universal Synchronous Asynchronous Receiver Transmitter (USART)

40.1 Description

The Universal Synchronous Asynchronous Rece iver Transceiver (USART) provides one full duplex universal synchronous asynchronous serial link. Data frame format is widely programma- ble (data length, parity, number of stop bits) to support a maximum of standards. The receiver implements parity error, framing error and overrun error detection. The receiver time-out enables handling variable-length frames and the transmitter timeguard facilitates communications with slow remote devices. Multidrop communications are also supported through address bit han- dling in reception and transmission. The USART features three test modes: remote loopback, local loopback and automatic echo. The USART supports specific operating modes providing interfaces on RS485, LIN, and SPI buses, with ISO7816 T = 0 or T = 1 smart card slots and infrared transceivers. The hardware handshaking feature enables an out-of-band flow control by automatic management of the pins RTS and CTS. The USART supports the connection to the DM A Controller, which enables data transfers to the transmitter and from the receiver. The DMAC provides chained buffer management without any intervention of the processor.

40.2 Embedded Characteristics

  • Programmable Baud Rate Generator
  • 5- to 9-bit Full-duplex Synchronous or Asynchronous Serial Communications – 1, 1.5 or 2 Stop Bits in Asynchronous Mode or 1 or 2 Stop Bits in Synchronous Mode – Parity Generation and Error Detection – Framing Error Detection, Overrun Error Detection – MSB- or LSB-first – Optional Break Generation and Detection – By 8 or by 16 Over-sampling Receiver Frequency – Optional Hardware Handshaking RTS-CTS – Receiver Time-out and Transmitter Timeguard – Optional Multidrop Mode with Address Generation and Detection
  • RS485 with Driver Control Signal
  • ISO7816, T = 0 or T = 1 Protocols for Interfacing with Smart Cards – NACK Handling, Error Counter with Repetition and Iteration Limit
  • IrDA Modulation and Demodulation – Communication at up to 115.2 Kbps
  • SPI Mode –M a s t e r o r S l a v e – Serial Clock Programmable Phase and Polarity – SPI Serial Clock (SCK) Frequency up to Internal Clock Frequency MCK/6
  • LIN Mode – Compliant with LIN 1.3 and LIN 2.0 specifications

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 776 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 –M a s t e r o r S l a v e – Processing of frames with up to 256 data bytes – Response Data length can be configurable or defined automatically by the Identifier – Self synchronization in Slave node configuration – Automatic processing and verification of the “Synch Break” and the “Synch Field” – The “Synch Break” is detected even if it is partially superimposed with a data byte – Automatic Identifier parity calculation/sending and verification – Parity sending and verification can be disabled – Automatic Checksum calculation/sending and verification – Checksum sending and verification can be disabled – Support both “Classic” and “Enhanced” checksum types – Full LIN error checking and reporting – Frame Slot Mode: the Master allocates slots to the scheduled frames automatically. – Generation of the Wakeup signal

  • Test Modes – Remote Loopback, Local Loopback, Automatic Echo
  • Supports Connection of: – Two DMA Controller Channels (DMAC)
  • Offers Buffer Transfer without Processor Intervention

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 777 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

40.3 Block Diagram

Figure 40-1. USART Block Diagram Table 40-1. SPI Operating Mode PIN USART SPI Slave SPI Master RXD RXD MOSI MISO TXD TXD MISO MOSI RTS RTS – CS CTS CTS CS – (Peripheral) DMA Controller Channel Channel Interrupt Controller Receiver USART Interrupt RXD TXD SCK USART PIO Controller CTS RTS Transmitter Baud Rate Generator User Interface PMC MCK SLCK DIV MCK/DIV APB

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 778 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

40.4 Application Block Diagram

Figure 40-2. Application Block Diagram

40.5 I/O Lines Description

Table 40-2. I/O Line Description Name Description Type Active Level SCK Serial Clock I/O TXD Transmit Serial Data or Master Out Slave In (MOSI) in SPI Master Mode or Master In Slave Out (MISO) in SPI Slave Mode I/O RXD Receive Serial Data or Master In Slave Out (MISO) in SPI Master Mode or Master Out Slave In (MOSI) in SPI Slave Mode Input CTS Clear to Send or Slave Select (NSS) in SPI Slave Mode Input Low RTS Request to Send or Slave Select (NSS) in SPI Master Mode Output Low

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 779 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

40.6 Product Dependencies

40.6.1 I/O Lines

The pins used for interfacing the USART may be multiplexed with the PIO lines. The program- mer must first program the PIO controller to assign the desired USART pins to their peripheral function. If I/O lines of the USART are not used by the application, they can be used for other purposes by the PIO Controller. To prevent the TXD line from falling when the USART is di sabled, the use of an internal pull up is mandatory. If the hardware handshaking feature is used, the internal pull up on TXD must also be enabled.

40.6.2 Power Management

The USART is not continuously clocked. The programmer must first enable the USART Clock in the Power Management Controller (PMC) before using the USART. However, if the application does not require USART operations, the USART clock can be stopped when not needed and be restarted later. In this case, the USART will resume its operations where it left off. Configuring the USART does not require the USART clock to be enabled. Table 40-3. I/O Lines Instance Signal I/O Line Peripheral USART0 CTS0 PA3 A USART0 RTS0 PA2 A USART0 RXD0 PA1 A USART0 SCK0 PA4 A USART0 TXD0 PA0 A USART1 CTS1 PC28 C USART1 RTS1 PC27 C USART1 RXD1 PA6 A USART1 SCK1 PC29 C USART1 TXD1 PA5 A USART2 CTS2 PB1 B USART2 RTS2 PB0 B USART2 RXD2 PA8 A USART2 SCK2 PB2 B USART2 TXD2 PA7 A USART3 CTS3 PC25 B USART3 RTS3 PC24 B USART3 RXD3 PC23 B USART3 SCK3 PC26 B USART3 TXD3 PC22 B

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 780 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12

40.6.3 Interrupt

The USART interrupt line is connected on one of the internal sources of the Interrupt Controller Using the USART interrupt requires the Interrupt Controller to be programmed first. Note that it is not recommended to use the USART interrupt line in edge sensitive mode.

40.7 Functional Description

The USART is capable of managing several ty pes of serial synchronous or asynchronous communications. It supports the following communication modes:

  • 5- to 9-bit full-duplex asynchronous serial communication – MSB- or LSB-first – 1, 1.5 or 2 stop bits – Parity even, odd, marked, space or none – By 8 or by 16 over-sampling receiver frequency – Optional hardware handshaking – Optional break management – Optional multidrop serial communication
  • High-speed 5- to 9-bit full-duplex synchronous serial communication – MSB- or LSB-first – 1 or 2 stop bits – Parity even, odd, marked, space or none – By 8 or by 16 over-sampling frequency – Optional hardware handshaking – Optional break management – Optional multidrop serial communication
  • RS485 with driver control signal
  • ISO7816, T0 or T1 protocols for interfacing with smart cards – NACK handling, error counter with repetition and iteration limit, inverted data.
  • InfraRed IrDA Modulation and Demodulation
  • SPI Mode –M a s t e r o r S l a v e – Serial Clock Programmable Phase and Polarity – SPI Serial Clock (SCK) Frequency up to Internal Clock Frequency MCK/6
  • LIN Mode Table 40-4. Peripheral IDs Instance ID USART0 5 USART1 6 USART2 7 USART3 8

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 781 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 – Compliant with LIN 1.3 and LIN 2.0 specifications –M a s t e r o r S l a v e – Processing of frames with up to 256 data bytes – Response Data length can be configurable or defined automatically by the Identifier – Self synchronization in Slave node configuration – Automatic processing and verification of the “Synch Break” and the “Synch Field” – The “Synch Break” is detected even if it is partially superimposed with a data byte – Automatic Identifier parity calculation/sending and verification – Parity sending and verification can be disabled – Automatic Checksum calculation/sending and verification – Checksum sending and verification can be disabled – Support both “Classic” and “Enhanced” checksum types – Full LIN error checking and reporting – Frame Slot Mode: the Master allocates slots to the scheduled frames automatically. – Generation of the Wakeup signal

  • Test modes – Remote loopback, local loopback, automatic echo

40.7.1 Baud Rate Generator

The Baud Rate Generator provides the bit period clock named the Baud Rate Clock to both the receiver and the transmitter. The Baud Rate Generator clock source can be selected by setting the USCLKS field in the Mode Register (US_MR) between:

  • the Master Clock MCK
  • a division of the Master Clock, the divider being product dependent, but generally set to 8
  • the external clock, available on the SCK pin The Baud Rate Generator is based upon a 16-bit divider, which is programmed with the CD field of the Baud Rate Generator Register (US_BRGR). If CD is programmed to 0, the Baud Rate Generator does not generate any clock. If CD is programmed to 1, the divider is bypassed and becomes inactive. If the external SCK clock is selected, the duration of the low and high levels of the signal pro- vided on the SCK pin must be longer than a Master Clock (MCK) period. The frequency of the signal provided on SCK must be at least 3 times lower than MCK in USART mode, or 6 in SPI mode.

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 782 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Figure 40-3. Baud Rate Generator

40.7.1.1 Baud Rate in Asynchronous Mode

If the USART is programmed to operate in as ynchronous mode, the selected clock is first divided by CD, which is field programmed in the Baud Rate Generator Register (US_BRGR). The resulting clock is provided to the receiver as a sampling clock and then divided by 16 or 8, depending on the programming of the OVER bit in US_MR. If OVER is set to 1, the receiver sampling is 8 times higher than the baud rate clock. If OVER is cleared, the sampling is performed at 16 times the baud rate clock. The following formula performs the calculation of the Baud Rate. This gives a maximum baud rate of MCK divided by 8, assuming that MCK is the highest possi- ble clock and that OVER is programmed to 1. Baud Rate Calculation Example Table 40-5 shows calculations of CD to obtain a baud rate at 38400 bauds for different source clock frequencies. This table also shows the actual resulting baud rate and the error. MCK/DIV 16-bit Counter Baud Rate Clock CD CD Sampling Divider Sampling Clock Reserved MCK SCK USCLKS OVER SCK SYNC SYNC USCLKS = 3 FIDI Baudrate SelectedClock Table 40-5. Baud Rate Example (OVER = 0) Source Clock Expected Baud Rate Calculation Result CD Actual Baud Rate Error MHz Bit/s Bit/s 3 686 400 38 400 6.00 6 38 400.00 0.00% 4 915 200 38 400 8.00 8 38 400.00 0.00% 5 000 000 38 400 8.14 8 39 062.50 1.70% 7 372 800 38 400 12.00 12 38 400.00 0.00% 8 000 000 38 400 13.02 13 38 461.54 0.16%

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 783 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 The baud rate is calculated with the following formula: The baud rate error is calculated with the following formula. It is not recommended to work with an error higher than 5%.

40.7.1.2 Fractional Baud Rate in Asynchronous Mode

The Baud Rate generator previously defined is subject to the following limitation: the output fre- quency changes by only integer multiples of the reference frequency. An approach to this problem is to integrate a fractional N clock generator that has a high resolution. The generator architecture is modified to obtain Baud Rate changes by a fraction of the reference source clock. This fractional part is programmed with the FP field in the Baud Rate Generator Register (US_BRGR). If FP is not 0, the fractional part is activated. The resolution is one eighth of the clock divider. This feature is only available when using USART normal mode. The fractional Baud Rate is calculated using the following formula: The modified architecture is presented below: 12 000 000 38 400 19.53 20 37 500.00 2.40% 12 288 000 38 400 20.00 20 38 400.00 0.00% 14 318 180 38 400 23.30 23 38 908.10 1.31% 14 745 600 38 400 24.00 24 38 400.00 0.00% 18 432 000 38 400 30.00 30 38 400.00 0.00% 24 000 000 38 400 39.06 39 38 461.54 0.16% 24 576 000 38 400 40.00 40 38 400.00 0.00% 25 000 000 38 400 40.69 40 38 109.76 0.76% 32 000 000 38 400 52.08 52 38 461.54 0.16% 32 768 000 38 400 53.33 53 38 641.51 0.63% 33 000 000 38 400 53.71 54 38 194.44 0.54% 40 000 000 38 400 65.10 65 38 461.54 0.16% 50 000 000 38 400 81.38 81 38 580.25 0.47% Table 40-5. Baud Rate Example (OVER = 0) (Continued) Source Clock Expected Baud Rate Calculation Result CD Actual Baud Rate Error BaudRate MCK CD 16× ⁄= Error 1 ExpectedBaudRate ⎛⎞– = Baudrate SelectedClock

82 Over–() CD FP

11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 784 11063G–ATARM–09-Oct-12 SAM9N12/SAM9CN11/SAM9CN12 Figure 40-4. Fractional Baud Rate Generator

40.7.1.3 Baud Rate in Synchronous Mode or SPI Mode

If the USART is programmed to operate in synchronous mode, the selected clock is simply divided by the field CD in US_BRGR. In synchronous mode, if the external clock is selected (USCLKS = 3), the clock is provided directly by the signal on the USART SCK pin. No division is active. The value written in US_BRGR has no effect. The external clock frequency must be at least 3 times lower than the system clock. In synchronous mode master (USCLKS = 0 or 1, CLK0 set to 1), the receive part limits the SCK maximum frequency to MCK/3 in USART mode, or MCK/6 in SPI mode. When either the external clock SCK or the inte rnal clock divided (MCK/DIV) is selected, the value programmed in CD must be even if the user has to ensure a 50:50 mark/space ratio on the SCK pin. If the internal clock MCK is selected, the Baud Rate Generator ensures a 50:50 duty cycle on the SCK pin, even if the value programmed in CD is odd.

40.7.1.4 Baud Rate in ISO 7816 Mode

The ISO7816 specification defines the bit rate with the following formula: where:

  • B is the bit rate
  • Di is the bit-rate adjustment factor
  • Fi is the clock frequency division factor
  • f is the ISO7816 clock frequency (Hz) MCK/DIV 16-bit Counter Baud Rate Clock CD CD Sampling Divider Sampling Clock Reserved MCK SCK USCLKS OVER SCK SYNC SYNC USCLKS = 3 FIDIGlitch-free Logic Modulus Control FP FP BaudRate SelectedClock B Di

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