SAM-R21E_14 ATMEL | Alldatasheet
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Atmel-42223AS–SAM-R21_Summary–07/2014 SMART
Description
The Atmel® | SMART™ SAM R21 is a series of low-power microcontrollers using the 32-bit ARM® Cortex®-M0+ processor and an integrated ultra-low power 2.4GHz ISM band transceiver. SAM R21 devices are available in 32- and 48-pin packages with up to 256KB Flash, 32KB of SRAM and are operating at a maximum frequency of 48MHz and reach 2.14 Coremark/MHz. They are designed for simple and intuitive migration with identical peripheral modules, hex compatible code, identical linear address map and pin compatible migration paths between all devices in the product series. All devices include intelligent and flexible peripherals, Atmel Event System for inter-peripheral signaling, and support for capacitive touch button, slider and wheel user interfaces. The Atmel SAM R21 devices provide the following features: In-system programmable Flash, 12-channel direct memory access (DMA) controller, 12-channel Event System, programmable interrupt controller, up to 28 programmable I/O pins, ultra-low power 2.4GHz ISM band transceiver with a data rate of 250kB/s, 32-bit real-time clock and calendar, three 16-bit Timer/Counters (TC) and three 16-bit Timer/Counters for Control (TCC), where each TC can be configured to perform frequency and waveform generation, accurate program execution timing or input capture with time and frequency measurement of digital signals. The TCs can operate in 8- or 16-bit mode, selected TCs can be cascaded to form a 32-bit TC, and the three Timer/Counters for Control have extended functions optimized for motor, lighting and other control applications. The series provide one full-speed USB 2.0 embedded host and device interface; up to five Serial Communication Modules (SERCOM) that each can be configured to act as an USART, UART, SPI, I2C up 3.4MHz and LIN slave; up to eight channel 350ksps 12-bit ADC with programmable gain and optional oversampling and decimation supporting up to 16-bit resolution, two analog comparators with window mode, Peripheral Touch Controller supporting up to 48 buttons, sliders, wheels and proximity sensing; programmable Watchdog Timer, brown-out detector and power-on reset and two-pin Serial Wire Debug (SWD) program and debug interface. All devices have accurate and low-power external and internal oscillators. All oscillators can be used as a source for the system clock. Different clock domains can be independently configured to run at different frequencies, enabling power saving by running each peripheral at its optimal clock frequency, and thus maintaining a high CPU frequency while reducing power consumption. The SAM R21 devices have two software-selectable sleep modes, idle and standby. In idle mode the CPU is stopped while all other functions can be kept running. In standby all clocks and functions are stopped expect those selected to continue running. The device supports SleepWalking, which is the module's ability to wake itself up and wake up its own clock, and hence perform predefined tasks without waking up the CPU. The CPU can then be only woken on a need basis, e.g. a threshold is crossed or a result is ready. The Event System supports synchronous and asynchronous events, allowing peripherals to receive, react to and send events even in standby mode. The Flash program memory can be reprogrammed in-system through the SWD interface. The same interface can be used for non-intrusive on-chip debug of application code. A boot loader running in the device can use any communication interface to download and upgrade the application program in the Flash memory. The SAM R21 devices are supported with a full suite of program and system development tools, including C compilers, macro assemblers, program debugger/simulators, programmers and evaluation kits. Atmel SAM R21 E / SAM R21 G SMART ARM-Based Wireless Microcontroller PRELIMINARY DATASHEET SUMMARY
2Atmel | SMART SAM R21 [PRELIMINARY DATASHEET SUMMARY] Atmel-42223AS–SAM-R21_Summary–07/2014
Features
z ARM Cortex-M0+ CPU running at up to 48MHz z Single-cycle hardware multiplier z Micro Trace Buffer (MTB) z Memories z 256/128/64KB in-system self-programmable Flash z 32/16/8KB SRAM z System z Power-on reset (POR) and brown-out detection (BOD) z Internal and external clock options with 48MHz Digital Frequency Locked Loop (DFLL48M) and 48MHz to 96MHz Fractional Digital Phase Locked Loop (FDPLL96M) z External Interrupt Controller (EIC) z Up to 15 external interrupts z One non-maskable interrupt z Two-pin Serial Wire Debug (SWD) programming, test and debugging interface z Low Power z Idle and standby sleep modes z SleepWalking peripherals z Peripherals z 12-channel Direct Memory Access Controller (DMAC) z 12-channel Event System z Integrated Ultra Low Power Transceiver for 2.4GHz ISM Band z 250kB/s data rate z -99dBm RX Sensitivity; TX Output Power up to +4dBm z Hardware Assisted MAC (Auto-Acknowledge, Auto-Retry) z SFD-Detection; Spreading; De-Spreading; Framing; CRC-16 Computation z Antenna Diversity and TX/RX Control z 128 Byte TX/RX Frame Buffer z Integrated 16MHz Crystal Oscillator (external crystal needed) z PLL synthesizer with 5 MHz and 500 kHz channel spacing for 2.4GHz ISM band z Hardware Security (AES, True Random Generator) z Three 16-bit Timer/Counters (TC), configurable as either: z One 16-bit TC with compare/capture channels z One 8-bit TC with compare/capture channels z One 32-bit TC with compare/capture channels, by using two TCs z Three 16-bit Timer/Counters for Control (TCC), with extended functions: z Up to four compare channels with optional complementary output z Generation of synchronized pulse width modulation (PWM) pattern across port pins z Deterministic fault protection, fast decay and configurable dead-time between complementary output z Dithering that increase resolution with up to 5 bit and reduce quantization error z 32-bit Real Time Counter (RTC) with clock/calendar function z Watchdog Timer (WDT) z CRC-32 generator z One full-speed (12Mbps) Universal Serial Bus (USB) 2.0 interface z Embedded host and device function z Eight endpoints z Up to five Serial Communication Interfaces (SERCOM), each configurable to operate as either: z USART with full-duplex and single-wire half-duplex configuration z I2C up to 3.4MHz z SPI z LIN slave z One 12-bit, 350ksps Analog-to-Digital Converter (ADC) with up to eight external channels z Differential and single-ended input z 1/2x to 16x programmable gain stage z Automatic offset and gain error compensation z Oversampling and decimation in hardware to support 13-, 14-, 15- or 16-bit resolution z Two Analog Comparators (AC) with window compare function z Peripheral Touch Controller (PTC) z 48-channel capacitive touch and proximity sensing z I/O and Package z 16/28 programmable I/O pins z 32-pin and 48-pin QFN
3Atmel | SMART SAM R21 [PRELIMINARY DATASHEET SUMMARY] Atmel-42223AS–SAM-R21_Summary–07/2014 z Operating Voltage z 1.8V – 3.6V z Temperature Range z -40°C to 85°C Industrial z -40°C to 125°C Industrial
4Atmel | SMART SAM R21 [PRELIMINARY DATASHEET SUMMARY] Atmel-42223AS–SAM-R21_Summary–07/2014 1. Configuration Summary SAM R21G SAM R21E Pins 48 32 General Purpose I/O-pins (GPIOs) 28 16 Flash 256/128/64KB 256/128/64KB SRAM 32/16/8KB 32/16/8KB Timer Counter (TC) instances 3 3 Waveform output channels per TC instance 2 2 Timer Counter for Control (TCC) instances 3 3 Waveform output channels per TCC 4/4/2 4/4/2 DMA channels 12 12 USB interface 1 1 Serial Communication Interface (SERCOM) instances 5+1(1) 4+1(1) Inter-IC Sound (I2S) interface No No Analog-to-Digital Converter (ADC) channels 8 4 Analog Comparators (AC) 2 2 Digital-to-Analog Converter (DAC) channels No No Real-Time Counter (RTC) Yes Yes RTC alarms 1 1 RTC compare values 1 32-bit value or 2 16-bit values 1 32-bit value or 2 16-bit values External Interrupt lines 15 14 Peripheral Touch Controller (PTC) X and Y lines 8x6 6x2 Maximum CPU frequency 48MHz Packages QFN QFN 32.768kHz crystal oscillator (XOSC32K) Yes No Oscillators 16MHz crystal oscillator for 2.4GHz TRX (XOSCRF) 0.4-32MHz crystal oscillator (XOSC) 32.768kHz internal oscillator (OSC32K) 32kHz ultra-low-power internal oscillator (OSCULP32K) 8MHz high-accuracy internal oscillator (OSC8M) 48MHz Digital Frequency Locked Loop (DFLL48M) 96MHz Fractional Digital Phased Locked Loop (FDPLL96M) Event System channels 12 12 SW Debug Interface Yes Yes Watchdog Timer (WDT) Yes Yes
5Atmel | SMART SAM R21 [PRELIMINARY DATASHEET SUMMARY] Atmel-42223AS–SAM-R21_Summary–07/2014 Note: 1. SERCOM4 is internally connected to the AT86RF233.
6Atmel | SMART SAM R21 [PRELIMINARY DATASHEET SUMMARY] Atmel-42223AS–SAM-R21_Summary–07/2014 2. Ordering Information
2.1 SAM R21E
SAMR = SoC Microcontroller with RF Product Series 21 = Cortex M0+ CPU, USB Flash Memory 18 = 256KB 17 = 128KB 16 = 64KB Device Variant A = Default Variant Pin Count E = 32 Pins G = 48 Pins Package Carrier No character = Tray (Default) T = Tape and Reel Package Grade Package Type M = QFN U = -40 - 85°C Matte Sn Plating F= - 4 0 -1 2 5 ° C M a t t e S n P l a t i n g Ordering Code FLASH (bytes) SRAM (bytes) Package Carrier Type ATSAMR21E16A-MF 64K 8K QFN32 Tray ATSAMR21E16A-MFT Tape & Reel ATSAMR21E16A-MU Tray ATSAMR21E16A-MUT Tape & Reel ATSAMR21E17A-MF 128K 16K QFN32 Tray ATSAMR21E17A-MFT Tape & Reel ATSAMR21E17A-MU Tray ATSAMR21E17A-MUT Tape & Reel ATSAMR21E18A-MF 256K 32K QFN32 Tray ATSAMR21E18A-MFT Tape & Reel ATSAMR21E18A-MU Tray ATSAMR21E18A-MUT Tape & Reel
7Atmel | SMART SAM R21 [PRELIMINARY DATASHEET SUMMARY] Atmel-42223AS–SAM-R21_Summary–07/2014
2.2 SAM R21G
Ordering Code FLASH (bytes) SRAM (bytes) Package Carrier Type ATSAMR21G16A-MF 64K 8K QFN48 Tray ATSAMR21G16A-MFT Tape & Reel ATSAMR21G16A-MU Tray ATSAMR21G16A-MUT Tape & Reel ATSAMR21G17A-MF 128K 16K QFN48 Tray ATSAMR21G17A-MFT Tape & Reel ATSAMR21G17A-MU Tray ATSAMR21G17A-MUT Tape & Reel ATSAMR21G18A-MF 256K 32K QFN48 Tray ATSAMR21G18A-MFT Tape & Reel ATSAMR21G18A-MU Tray ATSAMR21G18A-MUT Tape & Reel
8Atmel | SMART SAM R21 [PRELIMINARY DATASHEET SUMMARY] Atmel-42223AS–SAM-R21_Summary–07/2014 3. Block Diagrams
3.1 MCU Block Diagram
Notes: 1. Some products have different number of SERCOM instances, Timer/Counter instances, PTC signals and ADC sig- nals. Refer to “Ordering Information” on page 6 for details. 2. The three TCC instances have different configurations , including the number of Waveform Output (WO) lines. 3. Refer to the PORT Function Multiplexing Table 5-1 for details about the available GCLK_IO and ADC signals. 4. Only available for SAM R21G. 6 x SERCOM 8 x Timer Counter REAL TIME COUNTER AHB-APB BRIDGE C M MHIGH SPEED BUS MATRIX PORT PORT WATCHDOG TIMER SERIAL WIRESWDIO S CORTEX-M0+ PROCESSOR Fmax 48 MHz SWCLK DEVICE SERVICE UNIT AHB-APB BRIDGE A 8-CHANNEL 12-bit ADC 350KSPS AIN[n] AIN[3..0] S SRAM CONTROLLER 32/16/8KB RAM M RESET CONTROLLER SLEEP CONTROLLER CLOCK CONTROLLER POWER MANAGER RESETN 3 x TIMER / COUNTER EVENT SYSTEM S 5x SERCOM
2 ANALOG
X[7..0] Y[5..0] PERIPHERAL TOUCH CONTROLLER PERIPHERAL ACCESS CONTROLLER AHB-APB BRIDGE B EXTERNAL INTERRUPT CONTROLLER PERIPHERAL ACCESS CONTROLLER PERIPHERAL ACCESS CONTROLLER EXTINT[15..1] NMI GCLK_IO[n] S XOUT XIN XOUT32 XIN32 XOSC32K XOSC PAD0 WO1 PAD1 PAD2 PAD3 WO0 VREFB 256/128/64KB NVM NVM CONTROLLER Cache M DMA USB FS DEVICE MINI-HOST DP DM 3x TIMER / COUNTER FOR CONTROL WOn IOBUS FDPLL96M DMA DMA DMA DMA MEMORY TRACE BUFFER S SOF 1KHZ WO0 WO1 (2) (3) (3) GENERIC CLOCK CONTROLLER (4)
9Atmel | SMART SAM R21 [PRELIMINARY DATASHEET SUMMARY] Atmel-42223AS–SAM-R21_Summary–07/2014
3.2 SAM R21 Interconnection
(Slave) SERCOM 4 XOSC RF /SEL MISO MOSI SCLK AVREG 2.4GHz TRX (analog) DIG3 AVSS AVSS XTAL1 XTAL2 EXTERNAL INTERRUPT CONTROLLER IRQ Control Logic GENERIC CLOCK CLKM AVSS ADC DVREG DVSS DVDD DEVDD RFP RFN PC16 PB00 PC18 PC19 PB30 PB31 TRX (digital) PORT SLP_TR RSTN DIG2 DIG1 DIG4
2.4 GHz RF
FECTRL0..1 AC XOSC 32K VREG DVDD GNDANA RFN RFP AVSS GNDANA XTAL1 XTAL2 GNDANA VDDIO AVDDAVDD EVDD VDDANA GNDANA PAD3 PAD0 PAD2 PAD1 VDDIN VDDCORE GND EXTINT0 PA20 PB15 GCLK_IO1 PTC PA09 PA08 PA13(2) PA12(2) PA14 PA15 FECTRL2..5 (1) Notes: RFCTRL DIG1..4 1. Paddle connected to digital ground DVSS, GND. 2. Only available for SAM R21G. 3. Dedicated SERCOM4 alternate pin function mapping for internally connected AT86RF233. 4. Die revision A uses GCLK_IO5. (3) (4)
10Atmel | SMART SAM R21 [PRELIMINARY DATASHEET SUMMARY] Atmel-42223AS–SAM-R21_Summary–07/2014 4. Pinout
4.1 SAM R21G - QFN48
Note: The large center pad underneath the QFN package is made of metal and internally connected to GND. It should be soldered and connected to the digital ground on the board to ensure good mechanical stability. It is not recommended to use the exposed paddle as a replacement of the regular GND pin. GND VDDIO 13 GND 14 PA08 15 PA09 16 GNDANA 17 RFP 18 RFN 19 GNDANA 20 PA12 21 PA13 22 PA14 23 PA15 24 PA1625 PA1726 PA1827 PA1928 GND29 DVDD30 PA2231 PA2332 PA2433 PA2534 GND35 VDDIO36 PB0348 PB0247 PA3146 PA3045 VDDIN44 VDDCORE43 PA2841 RESET40 PA2739 PB2338 PB2237 PA00 1 PA01 2 XTAL2 3 XTAL1 4 GNDANA 5 VDDANA 6 AVDD 7 GNDANA 8 PA04 9 PA05 10 PA06 11 PA07 12 DIGITAL PIN ANALOG PIN OSCILLATOR GROUND INPUT SUPPLY REGULATED OUTPUT SUPPLY RESET PIN RF PIN DIGITAL PIN/ OSCILLATOR
11Atmel | SMART SAM R21 [PRELIMINARY DATASHEET SUMMARY] Atmel-42223AS–SAM-R21_Summary–07/2014
4.2 SAM R21E - QFN32
Note: The large center pad underneath the QFN package is made of metal and internally connected to GND. It should be soldered and connected to the digital ground on the board to ensure good mechanical stability. It is not recommended to use the exposed paddle as a replacement of the regular GND pin. PA08 PA09 GNDANA RFP RFN GNDANA PA14 PA15 PA1617 PA1718 PA1819 PA1920 DVDD21 PA2422 PA2523 VDDIO24 PA3132 PA3031 VDDIN30 VDDCORE29 GND28 PA2827 RESET26 PA2725 XTAL2 1 XTAL1 2 GNDANA 3 VDDANA 4 AVDD 5 GNDANA 6 PA06 7 PA07 8 DIGITAL PIN ANALOG PIN OSCILLATOR GROUND INPUT SUPPLY REGULATED OUTPUT RESET PIN RF PIN DIGITAL PIN/ SUPPLY OSCILLATOR
12Atmel | SMART SAM R21 [PRELIMINARY DATASHEET SUMMARY] Atmel-42223AS–SAM-R21_Summary–07/2014 5. I/O Multiplexing and Considerations
5.1 Multiplexed Signals
Each pin is by default controlled by the PORT as a general purpose I/O and alternatively it can be assigned to one of the peripheral functions A, B, C, D, E, F, G or H. To enable a peripheral function on a pin, the Peripheral Multiplexer Enable bit in the Pin Configuration register corresponding to that pin (PINCFGn.PMUXEN, n = 0..31) in the PORT must be written to one. The selection of peripheral function A to H is done by writing to the Peripheral Multiplexing Odd and Even bits in the Peripheral Multiplexing register (PMUXn.PMUXE/O) in the PORT. Table 5-1 describes the peripheral signals multiplexed to the PORT I/O pins. Table 5-1. PORT Function Multiplexing Pin I/O Pin Supply Type A B(1)(2) C D E F G H SAMR21 E SAMR21 G EIC REF ADC AC PTC SERCOM (1)(2) SERCOM- ALT TC TCC FECTRL TCC SERCOM COM AC/ GCLK
1 PA00 VDDANA SERCOM1/
PAD[0] TCC2/WO[0]
2 PA01 VDDANA EXTINT[1] SERCOM1/
PAD[1] TCC2/WO[1]
9 PA04 VDDANA EXTINT[4] ADC/
VREFB AIN[4] AIN[0] Y[2] SERCOM0/ PAD[0] TCC0/WO[0]
10 PA05 VDDANA EXTINT[5] AIN[5] AIN[1] Y[3] SERCOM0/
PAD[1] TCC0/WO[1] 7 11 PA06 VDDANA EXTINT[6] AIN[6] AIN[2] Y[4] SERCOM0/ PAD[2] TCC1/WO[0] 8 12 PA07 VDDANA EXTINT[7] AIN[7] AIN[3] Y[5] SERCOM0/ PAD[3] TCC1/WO[1] 9 15 PA08 VDDIO I2C NMI AIN[16] X[0] SERCOM0/ PAD[0] SERCOM2/ PAD[0] TCC0/WO[0] FECTRL[0] 10 16 PA09 VDDIO I2C EXTINT[9] AIN[17] X[1] SERCOM0/ PAD[1] SERCOM2/ PAD[1] TCC0/WO[1] FECTRL[1]
21 PA12 VDDIO I2C EXTINT[12] SERCOM2/
PAD[0] TCC2/WO[0] FECTRL[2] AC/ CMP[0]
22 PA13 VDDIO I2C EXTINT[13] SERCOM2/
PAD[1] TCC2/WO[1] FECTRL[3] AC/ CMP[1] 15 23 PA14 VDDIO EXTINT[14] SERCOM2/ PAD[2] TC3/WO[0] FECTRL[4] GCLK_IO[0] 16 24 PA15 VDDIO EXTINT[15] SERCOM2/ PAD[3] TC3/WO[1] FECTRL[5] GCLK_IO[1] 17 25 PA16 VDDIO I2C X[4] SERCOM1/ PAD[0] SERCOM3/ PAD[0] TCC2/WO[0] TCC0/ WO[0] GCLK_IO[2] 18 26 PA17 VDDIO I2C EXTINT[1] X[5] SERCOM1/ PAD[1] SERCOM3/ PAD[1] TCC2/WO[1] TCC0/ WO[1] GCLK_IO[3] 19 27 PA18 VDDIO EXTINT[2] X[6] SERCOM1/ PAD[2] SERCOM3/ PAD[2] TC3/WO[0] TCC0/ WO[2] AC/ CMP[0] 20 28 PA19 VDDIO EXTINT[3] X[7] SERCOM1/ PAD[3] SERCOM3/ PAD[3] TC3/WO[1] TCC0/ WO[3] AC/ CMP[1]
31 PA22 VDDIO I2C EXTINT[6] X[10] SERCOM3/
PAD[0] SERCOM5/ PAD[0] TC4/WO[0] TCC0/ WO[4] GCLK_IO[6]
32 PA23 VDDIO I2C EXTINT[7] X[11] SERCOM3/
PAD[1] SERCOM5/ PAD[1] TC4/WO[1] TCC0/ WO[5] GCLK_IO[7] 22 33 PA24 VDDIO EXTINT[12] SERCOM3/ PAD[2] SERCOM5/ PAD[2] TC5/WO[0] TCC1/ WO[2] USB_DM 23 34 PA25 VDDIO EXTINT[13] SERCOM3/ PAD[3] SERCOM5/ PAD[3] TC5/WO[1] TCC1/ WO[3] USB_DP
13Atmel | SMART SAM R21 [PRELIMINARY DATASHEET SUMMARY] Atmel-42223AS–SAM-R21_Summary–07/2014 Notes: 1. All analog pin functions are on peripheral function B. Pe ripheral function B must be selected to disable the digital control of the pin. 2. Only some pins can be used in SERCOM I 2C mode. See the Type column for using a SERCOM pin in I2C mode. Refer to !!!CRs_ElChar_Top!!! for details on the I2C pin characteristics.
5.2 Internal Multiplexed Signals
PA20, PB00, PB15, PB30, PB31, PC16, PC18 and PC19 are by default controlled by the PORT as a general purpose I/O and alternatively it can be assigned to one of the peripheral functions A, B, C, D, E, F, G or H. To enable a peripheral function on a pin, the Peripheral Multiplexer Enable bit in the Pin Configuration register corresponding to that pin (PINCFGn.PMUXEN, n = 0-31) in the PORT must be written to one. The selection of peripheral function A to H is done by writing to the Peripheral Multiplexing Odd and Even bits in the Peripheral Multiplexing register (PMUXn.PMUXE/O) in the PORT. PA10, PA11, PB16 and PB17 cannot be configured as output ports. These ports are always connected to the RFCTRL inputs.
37 PB22 VDDIO EXTINT[6] SERCOM5/
PAD[2] GCLK_IO[0]
38 PB23 VDDIO EXTINT[7] SERCOM5/
PAD[3] GCLK_IO[1] 25 39 PA27 VDDIO EXTINT[15] SERCOM3/ PAD[0] GCLK_IO[0] 27 41 PA28 VDDIO EXTINT[8] SERCOM3/ PAD[1] GCLK_IO[0] 31 45 PA30 VDDIO EXTINT[10] SERCOM1/ PAD[2] TCC1/WO[0] SWCLK GCLK_IO[0] 32 46 PA31 VDDIO EXTINT[11] SERCOM1/ PAD[3] TCC1/WO[1]
47 PB02 VDDANA EXTINT[2] AIN[10] Y[8] SERCOM5/
PAD[0]
48 PB03 VDDANA EXTINT[3] AIN[11] Y[9] SERCOM5/
PAD[1] Table 5-1. PORT Function Multiplexing (Continued) Pin I/O Pin Supply Type A B(1)(2) C D E F G H SAMR21 E SAMR21 G EIC REF ADC AC PTC SERCOM (1)(2) SERCOM- ALT TC TCC FECTRL TCC SERCOM COM AC/ GCLK Internal Signal I/O Pin Supply Type A B C D E F G H EIC REF ADC AC PTC SERCOM SERCOM- ALT TC FECTRL TCC SERCOM COM AC/ GCLK DIG3 PA10 VDDIO Input EXTINT[10] DIG4 PA11 VDDIO Input EXTINT[11] SLP_TR PA20 VDDIO I/O IRQ PB00 VDDANA I/O EXTINT[0] RSTN PB15 VDDIO I/O DIG1 PB16 VDDIO Input EXTINT[0] DIG2 PB17 VDDIO Input EXTINT[1] MOSI PB30 VDDIO I/O SERCOM4/ PAD[2] SEL PB31 VDDIO I/O SERCOM4/ PAD[1]
14Atmel | SMART SAM R21 [PRELIMINARY DATASHEET SUMMARY] Atmel-42223AS–SAM-R21_Summary–07/2014 Note: 1. Die revision A uses GCLK/IO[5].
5.3 Other Functions
5.3.1 Oscillator Pinout
The oscillators are not mapped to the normal PORT functions and their multiplexing are controlled by registers in the System Controller (SYSCTRL). The integrated AT86RF233 16 MHz crystal oscillator is directly connected to pins and has no multiplexing functionality.
5.3.2 Serial Wire Debug Interface Pinout
Only the SWCLK pin is mapped to the normal PORT functions. A debugger cold-plugging or hot-plugging detection will automatically switch the SWDIO port to the SWDIO function. CLKM PC16 VDDIO I/O GCLK/ IO1 SCLK PC18 VDDIO I/O SERCOM4/ PAD[3] MISO PC19 VDDIO I/O SERCOM4/ PAD[0] Internal Signal I/O Pin Supply Type A B C D E F G H EIC REF ADC AC PTC SERCOM SERCOM- ALT TC FECTRL TCC SERCOM COM AC/ GCLK Oscillator Supply Signal I/O Pin XOSC VDDIO XIN PA14 XOUT PA15 XOSC32K VDDANA XIN32 PA00 XOUT32 PA01 Oscillator Supply Signal I/O Pin XOSCRF EVDD/VDDANA XTAL1 XTAL1 XTAL2 XTAL2 Signal Supply I/O Pin SWCLK VDDIO PA30 SWDIO VDDIO PA31
15Atmel | SMART SAM R21 [PRELIMINARY DATASHEET SUMMARY] Atmel-42223AS–SAM-R21_Summary–07/2014 6. Product Mapping Figure 6-1. Atmel | SMART SAM R21 Product Mapping This figure represents the full configuration of the Atmel | SMART SAM R21 with maximum Flash and SRAM capabilities and a full set of peripherals. Refer to the “Configuration Summary” on page 4 for details. Code SRAM Undefined Peripherals Reserved Undefined Reserved Global Memory Space 0x00000000 0x20000000 0x22008000 0x40000000 0x43000000 0x60000000 0x60000200 0xFFFFFFFF Internal SRAM SRAM AHB-APB Bridge A AHB-APB Bridge B AHB-APB Bridge C AHB-APB Internal Flash Reserved Code 0x00000000 0x00400000 0x1FFFFFFF 0x20000000 0x20008000 0x40000000 0x41000000 0x42000000 0x42FFFFFF Reserved PAC0 PM SYSCTRL GCLK WDT RTC EIC AHB-APB Bridge A 0x40000000 0x40000400 0x40000800 0x40000C00 0x40001000 0x40001400 0x40001800 0x40FFFFFF 0x40001C00 AHB-APB Bridge B Reserved PAC1 DSU NVMCTRL PORT 0x41000000 0x41002000 0x41004000 0x41004400 0x41FFFFFF 0x41004700 SERCOM5 PAC2 EVSYS SERCOM0 SERCOM1 SERCOM2 SERCOM3 SERCOM4 (1) AHB-APB Bridge C Reserved TCC0 TCC1 TCC2 TC3 TC4 TC5 Reserved ADC AC 0x42000000 0x42000400 0x42000800 0x42000C00 0x42001000 0x42001400 0x42001800 0x42002000 0x42001C00 0x42003000 0x42003400 0x42003800 0x42003C00 0x42004000 0x42004400 0x42004800 Reserved 0x40FFFFFF Reserved 0x42004C00 0x42002400 0x42002800 0x42002C00 PTC 0x42005400 0x42005000 Reserved RFCTRL 0x42005800 DMAC USB MTB 0x41004800 0x41005000 0x41006000 Note 1. SERCOM4 is internally connected to the AT86RF233.
16Atmel | SMART SAM R21 [PRELIMINARY DATASHEET SUMMARY] Atmel-42223AS–SAM-R21_Summary–07/2014 7. Processor And Architecture
7.1 Cortex M0+ Processor
The Atmel | SMART SAM R21 implements the ARM® Cortex™-M0+ processor, which is based on the ARMv6 Architecture and Thumb®-2 ISA. The Cortex M0+ is 100% instruction set compatible with its predecessor, the Cortex-M0 processor, and upward compatible to Cortex-M3 and M4 processors. For more information refer to www.arm.com.
7.1.1 Cortex M0+ Configuration
Note: 1. All software run in privileged mode only The ARM Cortex-M0+ core has two bus interfaces: z Single 32-bit AMBA®-3 AHB-Lite™ system interface that provides connections to peripherals and all system memory, including flash and RAM z Single 32-bit I/O port bus interfacing to the PORT with one-cycle loads and stores Features Configuration option Atmel | SMART SAM R21 configuration Interrupts External interrupts 0-32 32 Data endianness Little-endian or big-endian Little-endian SysTick timer Present or absent Present Number of watchpoint comparators 0, 1, 2 2 Number of breakpoint comparators 0, 1, 2, 3, 4 4 Halting debug support Present or absent Present Multiplier Fast or small Fast (single cycle) Single-cycle I/O port Present or absent Present Wake-up interrupt controller Supported or not supported Not supported Vector Table Offset Register Present or absent Present Unprivileged/Privileged support Present or absent Absent(1) Memory Protection Unit Not present or 8-region Not present Reset all registers Present or absent Absent Instruction fetch width 16-bit only or mostly 32-bit 32-bit
17Atmel | SMART SAM R21 [PRELIMINARY DATASHEET SUMMARY] Atmel-42223AS–SAM-R21_Summary–07/2014 8. Packaging Information
8.1 Thermal Considerations
8.1.1 Thermal Resistance Data
Table 8-1 summarizes the thermal resistance data depending on the package. Table 8-1. Thermal Resistance Data
8.1.2 Junction Temperature
The average chip-junction temperature, TJ, in °C can be obtained from the following: where: z θJA = package thermal resistance, Junction-to-ambient (°C/W), provided in Table 8-1. z θJC = package thermal resistance, Junction-to-case thermal resistance (°C/W), provided in Table 8-1. z θHEATSINK = cooling device thermal resistance (°C/W), provided in the device datasheet. z PD = device power consumption (W). z TA = ambient temperature (°C). From the first equation, the user can derive the estimated lifetime of the chip and decide if a cooling device is necessary or not. If a cooling device is to be fitted on the chip, the second equation should be used to compute the resulting average chip-junction temperature TJ in °C. Package Type θJA θJC 32-pin QFN 37.2 °C/W 3.1 °C/W 48-pin QFN 33 °C/W 11.4 °C/W
18Atmel | SMART SAM R21 [PRELIMINARY DATASHEET SUMMARY] Atmel-42223AS–SAM-R21_Summary–07/2014
8.2 Package Drawings
8.2.1 48-pin QFN Table 8-2. Device and Package Maximum Weight 100 mg Table 8-3. Package Characteristics Moisture Sensitivity Level MSL3 Table 8-4. Package Reference JEDEC Drawing Reference MO-220 JESD97 Classification E3
19Atmel | SMART SAM R21 [PRELIMINARY DATASHEET SUMMARY] Atmel-42223AS–SAM-R21_Summary–07/2014 8.2.2 32-pin QFN Table 8-5. Device and Package Maximum Weight 90 mg Table 8-6. Package Characteristics Moisture Sensitivity Level MSL3 Table 8-7. Package Reference JEDEC Drawing Reference MO-220 JESD97 Classification E3
20Atmel | SMART SAM R21 [PRELIMINARY DATASHEET SUMMARY] Atmel-42223AS–SAM-R21_Summary–07/2014
8.3 Soldering Profile
The following table gives the recommended soldering profile from J-STD-20. A maximum of three reflow passes is allowed per component. SVNREVISION Profile Feature Green Package Average Ramp-up Rate (217°C to peak) 3°C/s max Preheat Temperature 175°C +/-25°C 150-200°C Time Maintained Above 217°C 60-150s Time within 5°C of Actual Peak Temperature 30s Peak Temperature Range 260°C Ramp-down Rate 6°C/s max Time 25°C to Peak Temperature 8 minutes max
21Atmel | SMART SAM R21 [PRELIMINARY DATASHEET SUMMARY] Atmel-42223AS–SAM-R21_Summary–07/2014 Table of Contents
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