SAM-D20E

SAM-D20E_14 ATMEL | Alldatasheet

Document overview

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Technical content

Atmel-42129LS–SAM-D20_Summary–09/2014 SMART

Description

The Atmel® | SMART™ SAM D20 is a series of low-power microcontrollers using the 32-bit ARM® Cortex®-M0+ processor, and ranging from 32- to 64-pins with up to 256KB Flash and 32KB of SRAM. The SAM D20 devices operate at a maximum frequency of 48MHz and reach 2.14 Coremark/MHz. They are designed for simple and intuitive migration with identical peripheral modules, hex compatible code, identical linear address map and pin compatible migration paths between all devices in the product series. All devices include intelligent and flexible peripherals, Atmel Event System for inter-peripheral signaling, and support for capacitive touch button, slider and wheel user interfaces. The Atmel | SMART SAM D20 devices provide the following features: In-system programmable Flash, eight-channel Event System, programmable interrupt controller, up to 52 programmable I/O pins, 32-bit real-time clock and calendar, up to eight 16-bit Timer/Counters (TC). The timer/counters can be configured to perform frequency and waveform generation, program execution timing or input capture with time and frequency measurement of digital signals. The TCs can operate in 8- or 16-bit mode, or be cascaded to form a 32-bit TC. The series provide up to six Serial Communication Modules (SERCOM) that each can be configured to act as an USART, UART, SPI and I 2C up to 400kHz; up to twenty-channel 350ksps 12-bit ADC with programmable gain and optional oversampling and decimation supporting up to 16-bit resolution, one 10-bit 350ksps DAC, two analog comparators with window mode, Peripheral Touch Controller supporting up to 256 buttons, sliders, wheels, and proximity sensing; programmable Watchdog Timer, brown-out detector and power-on reset, and two-pin Serial Wire Debug (SWD) program and debug interface. All devices have accurate and low-power external and internal oscillators. All oscillators can be used as a source for the system clock. Different clock domains can be independently configured to run at different frequencies while enabling power saving by running each peripheral at its optimal clock frequency. The Atmel | SMART SAM D20 devices have two software-selectable sleep modes, idle and standby. In idle mode the CPU is stopped while all other functions can be kept running. In standby all clocks and functions are stopped expect those selected to continue running. The device supports SleepWalking. This feature allows the peripheral to wake up from sleep based on predefined conditions, and thus allows the CPU to wake up only when needed, e.g. when a threshold is crossed or a result is ready. The Event System supports synchronous and asynchronous events, allowing peripherals to receive, react to and send events even in standby mode. The Flash program memory can be reprogrammed in-system through the SWD interface. The same interface can be used for non-intrusive on-chip debug of application code. A boot loader running in the device can use any communication interface to download and upgrade the application program in the Flash memory. The Atmel | SMART SAM D20 devices are supported with a full suite of program and system development tools, including C compilers, macro assemblers, program debugger/simulators, programmers and evaluation kits Atmel SAM D20J / SAM D20G / SAM D20E SMART ARM-Based Microcontroller DATASHEET SUMMARY

2Atmel | SMART SAM D20 [DATASHEET Summary] Atmel-42129LS–SAM-D20_Summary–09/2014

Features

z ARM Cortex-M0+ CPU running at up to 48MHz z Single-cycle hardware multiplier z Memories z 16/32/64/128/256KB in-system self-programmable flash z 2/4/8/16/32KB SRAM z System z Power-on reset (POR) and brown-out detection (BOD) z Internal and external clock options with 48MHz Digital Frequency Locked Loop (DFLL48M) z External Interrupt Controller (EIC) z 16 external interrupts z One non-maskable interrupt z Two-pin Serial Wire Debug (SWD) programming, test and debugging interface z Low Power z Idle and standby sleep modes z SleepWalking peripherals z Peripherals z 8-channel Event System z Up to eight 16-bit Timer/Counters (TC), configurable as either: z One 16-bit TC with compare/capture channels z One 8-bit TC with compare/capture channels z One 32-bit TC with compare/capture channels, by using two TCs z 32-bit Real Time Counter (RTC) with clock/calendar function z Watchdog Timer (WDT) z CRC-32 generator z Up to six Serial Communication Interfaces (SERCOM), each configurable to operate as either: z USART with full-duplex and single-wire half-duplex configuration z I2C up to 400kHz z SPI z One 12-bit, 350ksps Analog-to-Digital Converter (ADC) with up to 20 channels z Differential and single-ended channels z 1/2x to 16x gain stage z Automatic offset and gain error compensation z Oversampling and decimation in hardware to support 13-, 14-, 15- or 16-bit resolution z 10-bit, 350ksps Digital-to-Analog Converter (DAC) z Two Analog Comparators with window compare function z Peripheral Touch Controller (PTC) z 256-Channel capacitive touch and proximity sensing z I/O z Up to 52 programmable I/O pins z Packages z 64-pin TQFP, QFN z 64-ball UFBGA z 48-pin TQFP, QFN z 45-ball WLCSP z 32-pin TQFP, QFN z Operating Voltage z 1.62V – 3.63V z Power Consumption z Down to 70µA/MHz in active mode z Down to 8µA running the Peripheral Touch Controller

3Atmel | SMART SAM D20 [DATASHEET Summary] Atmel-42129LS–SAM-D20_Summary–09/2014 1. Configuration Summary SAM D20J SAM D20G SAM D20E Number of pins 64 48 32 General Purpose I/O-pins (GPIOs) 52 38 26 Flash 256/128/64/32/16KB 256/128/64/32/16KB 256/128/64/32/16KB Maximum CPU frequency 48MHz Event System channels 8 8 8 Timer Counter (TC) 8 6 6 Waveform output channels for TC 2 2 2 Serial Communication Interface (SERCOM) 6 6 4 Analog-to-Digital Converter (ADC) channels 20 14 10 Analog comparators 2 2 2 Digital-to-Analog Converter (DAC) channels 1 1 1 Real-Time Counter (RTC) Yes Yes Yes RTC alarms 1 1 1 RTC compare values 1 32-bit value or 2 16-bit values 1 32-bit value or 2 16-bit values 1 32-bit value or 2 16-bit values External Interrupt lines 16 16 16 Peripheral Touch Controller (PTC) X and Y lines 16x16 12x10 10x6 Packages QFN TQFP UFBGA QFN TQFP WLCSP QFN TQFP Oscillators 32.768kHz crystal oscillator (XOSC32K) 0.4-32MHz crystal oscillator (XOSC) 32.768kHzinternal oscillator (OSC32K) 32kHz ultra-low-power internal oscillator (OSCULP32K) 8MHz high-accuracy internal oscillator (OSC8M) 48MHz Digital Frequency Locked Loop (DFLL48M) SW Debug Interface Yes Yes Yes Watchdog Timer (WDT) Yes Yes Yes

4Atmel | SMART SAM D20 [DATASHEET Summary] Atmel-42129LS–SAM-D20_Summary–09/2014 2. Ordering Information

2.1 SAM D20E

SAMD = General Purpose Microcontroller 20 = Cortex M0+ CPU, Basic Feature Set E = 32 Pins G = 48 Pins J = 64 Pins No character = Tray (Default) T = Tape and Reel U = -40 - 85 O C Matte Sn Plating N = -40 - 105 O C Matte Sn Plating A = TQFP M = QFN C = UFBGA U = WLCSP Product Series Flash Memory Density Device Variant A = Default Variant Pin Count Package Carrier Package Grade Package Type 18 = 256KB 17 = 128KB 16 = 64KB 15 = 32KB 14 = 16KB Ordering Code FLASH (bytes) SRAM (bytes) Package Carrier Type ATSAMD20E14A-AU 16K 2K TQFP32 Tray ATSAMD20E14A-AN ATSAMD20E14A-AUT Tape & Reel ATSAMD20E14A-ANT ATSAMD20E14A-MU QFN32 Tray ATSAMD20E14A-MN ATSAMD20E14A-MUT Tape & Reel ATSAMD20E14A-MNT

5Atmel | SMART SAM D20 [DATASHEET Summary] Atmel-42129LS–SAM-D20_Summary–09/2014 ATSAMD20E15A-AU 32K 4K TQFP32 Tray ATSAMD20E15A-AN ATSAMD20E15A-AUT Tape & Reel ATSAMD20E15A-ANT ATSAMD20E15A-MU QFN32 Tray ATSAMD20E15A-MN ATSAMD20E15A-MUT Tape & Reel ATSAMD20E15A-MNT ATSAMD20E16A-AU 64K 8K TQFP32 Tray ATSAMD20E16A-AN ATSAMD20E16A-AUT Tape & Reel ATSAMD20E16A-ANT ATSAMD20E16A-MU QFN32 Tray ATSAMD20E16A-MN ATSAMD20E16A-MUT Tape & Reel ATSAMD20E16A-MNT ATSAMD20E17A-AU 128K 16K TQFP32 Tray ATSAMD20E17A-AN ATSAMD20E17A-AUT Tape & Reel ATSAMD20E17A-ANT ATSAMD20E17A-MU QFN32 Tray ATSAMD20E17A-MN ATSAMD20E17A-MUT Tape & Reel ATSAMD20E17A-MNT ATSAMD20E18A-AU 256K 32K TQFP32 Tray ATSAMD20E18A-AN ATSAMD20E18A-AUT Tape & Reel ATSAMD20E18A-ANT ATSAMD20E18A-MU QFN32 Tray ATSAMD20E18A-MN ATSAMD20E18A-MUT Tape & Reel ATSAMD20E18A-MNT Ordering Code FLASH (bytes) SRAM (bytes) Package Carrier Type

6Atmel | SMART SAM D20 [DATASHEET Summary] Atmel-42129LS–SAM-D20_Summary–09/2014

2.2 SAM D20G

Ordering Code FLASH (bytes) SRAM (bytes) Package Carrier Type ATSAMD20G14A-AU 16K 2K TQFP48 Tray ATSAMD20G14A-AN ATSAMD20G14A-AUT Tape & Reel ATSAMD20G14A-ANT ATSAMD20G14A-MU QFN48 Tray ATSAMD20G14A-MN ATSAMD20G14A-MUT Tape & Reel ATSAMD20G14A-MNT ATSAMD20G15A-AU 32K 4K TQFP48 Tray ATSAMD20G15A-AN ATSAMD20G15A-AUT Tape & Reel ATSAMD20G15A-ANT ATSAMD20G15A-MU QFN48 Tray ATSAMD20G15A-MN ATSAMD20G15A-MUT Tape & Reel ATSAMD20G15A-MNT ATSAMD20G16A-AU 64K 8K TQFP48 Tray ATSAMD20G16A-AN ATSAMD20G16A-AUT Tape & Reel ATSAMD20G16A-ANT ATSAMD20G16A-MU QFN48 Tray ATSAMD20G16A-MN ATSAMD20G16A-MUT Tape & Reel ATSAMD20G16A-MNT

7Atmel | SMART SAM D20 [DATASHEET Summary] Atmel-42129LS–SAM-D20_Summary–09/2014

2.3 SAM D20J

Tape & Reel ATSAMD20G17A-ANT ATSAMD20G17A-MU QFN48 Tray ATSAMD20G17A-MN ATSAMD20G17A-MUT Tape & Reel ATSAMD20G17A-MNT ATSAMD20G17A-UUT WLCSP45 Tape & Reel ATSAMD20G18A-AU 256K 32K TQFP48 Tray ATSAMD20G18A-AN ATSAMD20G18A-AUT Tape & Reel ATSAMD20G18A-ANT ATSAMD20G18A-MU QFN48 Tray ATSAMD20G18A-MN ATSAMD20G18A-MUT Tape & Reel ATSAMD20G18A-MNT ATSAMD20G18A-UUT WLCSP45 Tape & Reel Ordering Code FLASH (bytes) SRAM (bytes) Package Carrier Type Ordering Code FLASH (bytes) SRAM (bytes) Package Carrier Type ATSAMD20J14A-AU 16K 2K TQFP64 Tray ATSAMD20J14A-AN ATSAMD20J14A-AUT Tape & Reel ATSAMD20J14A-ANT ATSAMD20J14A-MU QFN64 Tray ATSAMD20J14A-MN ATSAMD20J14A-MUT Tape & Reel ATSAMD20J14A-MNT

8Atmel | SMART SAM D20 [DATASHEET Summary] Atmel-42129LS–SAM-D20_Summary–09/2014 ATSAMD20J15A-AU 32K 4K TQFP64 Tray ATSAMD20J15A-AN ATSAMD20J15A-AUT Tape & Reel ATSAMD20J15A-ANT ATSAMD20J15A-MU QFN64 Tray ATSAMD20J15A-MN ATSAMD20J15A-MUT Tape & Reel ATSAMD20J15A-MNT ATSAMD20J16A-AU 64K 8K TQFP64 Tray ATSAMD20J16A-AN ATSAMD20J16A-AUT Tape & Reel ATSAMD20J16A-ANT ATSAMD20J16A-MU QFN64 Tray ATSAMD20J16A-MN ATSAMD20J16A-MUT Tape & Reel ATSAMD20J16A-MNT ATSAMD20J17A-AU 128K 16K TQFP64 Tray ATSAMD20J17A-AN ATSAMD20J17A-AUT Tape & Reel ATSAMD20J17A-ANT ATSAMD20J17A-MU QFN64 Tray ATSAMD20J17A-MN ATSAMD20J17A-MUT Tape & Reel ATSAMD20J17A-MNT ATSAMD20J17A-CU UFBGA64 Tray ATSAMD20J17A-CUT Tape & Reel Ordering Code FLASH (bytes) SRAM (bytes) Package Carrier Type

9Atmel | SMART SAM D20 [DATASHEET Summary] Atmel-42129LS–SAM-D20_Summary–09/2014 ATSAMD20J18A-AU 256K 32K TQFP64 Tray ATSAMD20J18A-AN ATSAMD20J18A-AUT Tape & Reel ATSAMD20J18A-ANT ATSAMD20J18A-MU QFN64 Tray ATSAMD20J18A-MN ATSAMD20J18A-MUT Tape & Reel ATSAMD20J18A-MNT ATSAMD20J18A-CU UFBGA64 Tray ATSAMD20J18A-CUT Tape & Reel Ordering Code FLASH (bytes) SRAM (bytes) Package Carrier Type

10Atmel | SMART SAM D20 [DATASHEET Summary] Atmel-42129LS–SAM-D20_Summary–09/2014 3. Block Diagram Notes: 1. Some products have different number of SERCOM instances, Ti mer/Counter instances, PTC signals and ADC signals. Refer to “Configuration Summary” on page 3 for details. 6 x SERCOM 8 x Timer Counter REAL TIME COUNTER AHB-APB BRIDGE C M SHIGH SPEED BUS MATRIX PORT PORT WATCHDOG TIMER SERIAL WIRESWDIO NVM CONTROLLER 256/128/64/32/16KB FLASH S ARM CORTEX-M0+ PROCESSOR Fmax 48MHz SWCLK DEVICE SERVICE UNIT AHB-APB BRIDGE A ADC AIN[19:0] VREFA AIN[3:0] S 32/16/8/4/2KB RAM M RESET CONTROLLER SLEEP CONTROLLER CLOCK CONTROLLER POWER MANAGER RESET 8 x TIMER COUNTER EVENT SYSTEM S 6 x SERCOM

2 ANALOG

X[15:0] Y[15:0] PERIPHERAL TOUCH CONTROLLER PERIPHERAL ACCESS CONTROLLER AHB-APB BRIDGE B VREFA VOUT DAC EXTERNAL INTERRUPT CONTROLLER PERIPHERAL ACCESS CONTROLLER PERIPHERAL ACCESS CONTROLLER EXTINT[15:0] NMI GCLK_IO[7:0] S PIN[3:0] WO[1:0] VREFB (See Note1) CMP1:0] ARM SINGLE CYCLE IOBUS CONTROLLER

11Atmel | SMART SAM D20 [DATASHEET Summary] Atmel-42129LS–SAM-D20_Summary–09/2014 4. Pinout

4.1 SAM D20J

4.1.1 QFP64

12Atmel | SMART SAM D20 [DATASHEET Summary] Atmel-42129LS–SAM-D20_Summary–09/2014

4.1.2 UFBGA64

13Atmel | SMART SAM D20 [DATASHEET Summary] Atmel-42129LS–SAM-D20_Summary–09/2014

4.2 SAM D20G

4.2.1 QFP48

14Atmel | SMART SAM D20 [DATASHEET Summary] Atmel-42129LS–SAM-D20_Summary–09/2014

4.2.2 WLCSP45

15Atmel | SMART SAM D20 [DATASHEET Summary] Atmel-42129LS–SAM-D20_Summary–09/2014

4.3 SAM D20E

16Atmel | SMART SAM D20 [DATASHEET Summary] Atmel-42129LS–SAM-D20_Summary–09/2014 5. I/O Multiplexing and Considerations

5.1 Multiplexed Signals

Each pin is by default controlled by the PORT as a general purpose I/O and alternatively it can be assigned to one of the peripheral functions A, B, C, D, E, F, G or H. To enable a peripheral function on a pin, the Peripheral Multiplexer Enable bit in the Pin Configuration register corresponding to that pin (PINCFGn.PMUXEN, n = 0-31) in the PORT must be written to one. The selection of peripheral function A to H is done by writing to the Peripheral Multiplexing Odd and Even bits in the Peripheral Multiplexing register (PMUXn.PMUXE/O) in the PORT. Table 5-1 describes the peripheral signals multiplexed to the PORT I/O pins. Table 5-1. PORT Function Multiplexing Pin I/O Pin Supply Pin Type A B(1) C D E F G H SAM D20E SAM D20G SAM D20J EIC REF ADC AC PTC DAC SERCOM(2) TC(3) AC/GCLK 1 1 1 PA00 VDDANA EXTINT[0] SERCOM1/ PAD[0] TC2/ WO[0] 2 2 2 PA01 VDDANA EXTINT[1] SERCOM1/ PAD[1] TC2/ WO[1] 3 3 3 PA02 VDDANA EXTINT[2] AIN[0] Y[0] VOUT 4 4 4 PA03 VDDANA EXTINT[3] ADC/VREFA DAC/VREFA AIN[1] Y[1]

5 PB04 VDDANA EXTINT[4] AIN[12] Y[10]

6 PB05 VDDANA EXTINT[5] AIN[13] Y[11]

9 PB06 VDDANA EXTINT[6] AIN[14] Y[12]

10 PB07 VDDANA EXTINT[7] AIN[15] Y[13]

7 11 PB08 VDDANA EXTINT[8] AIN[2] Y[14] SERCOM4/ PAD[0] TC4/ WO[0] 8 12 PB09 VDDANA EXTINT[9] AIN[3] Y[15] SERCOM4/ PAD[1] TC4/ WO[1] 5 9 13 PA04 VDDANA EXTINT[4] ADC/ VREFB AIN[4] AIN[0] Y[2] SERCOM0/ PAD[0] TC0/ WO[0] 6 10 14 PA05 VDDANA EXTINT[5] AIN[5] AIN[1] Y[3] SERCOM0/ PAD[1] TC0/ WO[1] 7 11 15 PA06 VDDANA EXTINT[6] AIN[6] AIN[2] Y[4] SERCOM0/ PAD[2] TC1/ WO[0] 8 12 16 PA07 VDDANA EXTINT[7] AIN[7] AIN[3] Y[5] SERCOM0/ PAD[3] TC1/ WO[1] 11 13 17 PA08 VDDIO I2C NMI AIN[16] X[0] SERCOM0/ PAD[0] SERCOM2/ PAD[0] TC0/ WO[0] 12 14 18 PA09 VDDIO I2C EXTINT[9] AIN[17] X[1] SERCOM0/ PAD[1] SERCOM2/ PAD[1] TC0/ WO[1] 13 15 19 PA10 VDDIO EXTINT[10] AIN[18] X[2] SERCOM0/ PAD[2] SERCOM2/ PAD[2] TC1/ WO[0] GCLK_O[4] 14 16 20 PA11 VDDIO EXTINT[11] AIN[19] X[3] SERCOM0/ PAD[3] SERCOM2/ PAD[3] TC1/ WO[1] GCLK_IO[5] 19 23 PB10 VDDIO EXTINT[10] SERCOM4/ PAD[2] TC5/ WO[0] GCLK_IO[4] 20 24 PB11 VDDIO EXTINT[11] SERCOM4/ PAD[3] TC5/ WO[1] GCLK_IO[5]

25 PB12 VDDIO I2C EXTINT[12] X[12] SERCOM4/

PAD[0] TC4/ WO[0] GCLK_IO[6]

26 PB13 VDDIO I2C EXTINT[13] X[13] SERCOM4/

PAD[1] TC4/ WO[1] GCLK_IO[7]

27 PB14 VDDIO EXTINT[14] X[14] SERCOM4/

PAD[2] TC5/ WO[0] GCLK_IO[0]

28 PB15 VDDIO EXTINT[15] X[15] SERCOM4/

PAD[3] TC5/ WO[1] GCLK_IO[1]

17Atmel | SMART SAM D20 [DATASHEET Summary] Atmel-42129LS–SAM-D20_Summary–09/2014 Note: 1. All analog pin functions are on peripheral function B. Peri pheral function B must be selected to disable the digital control of the pin. 2. Only some pins can be used in SERCOM I 2C mode. See the Type column for using a SERCOM pin in I2C mode. 3. Note that TC6 and TC7 are not supported on the SAM D20G. Refer to “Configuration Summary” on page 3 for details. 4. This function is only activat ed in the presence of a debugger 21 29 PA12 VDDIO I2C EXTINT[12] SERCOM2/ PAD[0] SERCOM4/ PAD[0] TC2/ WO[0] AC/CMP[0] 22 30 PA13 VDDIO I2C EXTINT[13] SERCOM2/ PAD[1] SERCOM4/ PAD[1] TC2/ WO[1] AC/CMP[1] 15 23 31 PA14 VDDIO EXTINT[14] SERCOM2/ PAD[2] SERCOM4/ PAD[2] TC3/ WO[0] GCLK_IO[0] 16 24 32 PA15 VDDIO EXTINT[15] SERCOM2/ PAD[3] SERCOM4/ PAD[3] TC3/ WO[1] GCLK_IO[1] 17 25 35 PA16 VDDIO I2C EXTINT[0] X[4] SERCOM1/ PAD[0] SERCOM3/ PAD[0] TC2/ WO[0] GCLK_IO[2] 18 26 36 PA17 VDDIO I2C EXTINT[1] X[5] SERCOM1/ PAD[1] SERCOM3/ PAD[1] TC2/ WO[1] GCLK_IO[3] 19 27 37 PA18 VDDIO EXTINT[2] X[6] SERCOM1/ PAD[2] SERCOM3/ PAD[2] TC3/ WO[0] AC/CMP[0] 20 28 38 PA19 VDDIO EXTINT[3] X[7] SERCOM1/ PAD[3] SERCOM3/ PAD[3] TC3/ WO[1] AC/CMP[1]

39 PB16 VDDIO I2C EXTINT[0] SERCOM5/

PAD[0] TC6/ WO[0] GCLK_IO[2]

40 PB17 VDDIO I2C EXTINT[1] SERCOM5/

PAD[1] TC6/ WO[1] GCLK_IO[3] 29 41 PA20 VDDIO EXTINT[4] X[8] SERCOM5/ PAD[2] SERCOM3/ PAD[2] TC7/ WO[0] GCLK_IO[4] 30 42 PA21 VDDIO EXTINT[5] X[9] SERCOM5/ PAD[3] SERCOM3/ PAD[3] TC7/ WO[1] GCLK_IO[5] 21 31 43 PA22 VDDIO I2C EXTINT[6] X[10] SERCOM3/ PAD[0] SERCOM5/ PAD[0] TC4/ WO[0] GCLK_IO[6] 22 32 44 PA23 VDDIO I2C EXTINT[7] X[11] SERCOM3/ PAD[1] SERCOM5/ PAD[1] TC4/ WO[1] GCLK_IO[7] 23 33 45 PA24 VDDIO EXTINT[12] SERCOM3/ PAD[2] SERCOM5/ PAD[2] TC5/ WO[0] 24 34 46 PA25 VDDIO EXTINT[13] SERCOM3/ PAD[3] SERCOM5/ PAD[3] TC5/ WO[1] 37 49 PB22 VDDIO EXTINT[6] SERCOM5/ PAD[2] TC7/ WO[0] GCLK_IO[0] 38 50 PB23 VDDIO EXTINT[7] SERCOM5/ PAD[3] TC7/ WO[1] GCLK_IO[1] 25 39 51 PA27 VDDIO EXTINT[15] GCLK_IO[0] 27 41 53 PA28 VDDIO EXTINT[8] GCLK_IO[0] 31 45 57 PA30 VDDIO EXTINT[10] SERCOM1/ PAD[2] TC1/ WO[0] SWCLK GCLK_IO[0] 32 46 58 PA31 VDDIO EXTINT[11] SERCOM1/ PAD[3] TC1/ WO[1] SWDIO(4)

59 PB30 VDDIO I2C EXTINT[14] SERCOM5/

PAD[0] TC0/ WO[0]

60 PB31 VDDIO I2C EXTINT[15] SERCOM5/

PAD[1] TC0/ WO[1]

61 PB00 VDDANA EXTINT[0] AIN[8] Y[6] SERCOM5/

PAD[2] TC7/ WO[0]

62 PB01 VDDANA EXTINT[1] AIN[9] Y[7] SERCOM5/

PAD[3] TC7/ WO[1] 47 63 PB02 VDDANA EXTINT[2] AIN[10] Y[8] SERCOM5/ PAD[0] TC6/ WO[0] 48 64 PB03 VDDANA EXTINT[3] AIN[11] Y[9] SERCOM5/ PAD[1] TC6/ WO[1] Table 5-1. PORT Function Multiplexing (Continued) Pin I/O Pin Supply Pin Type A B(1) C D E F G H SAM D20E SAM D20G SAM D20J EIC REF ADC AC PTC DAC SERCOM(2) TC(3) AC/GCLK

18Atmel | SMART SAM D20 [DATASHEET Summary] Atmel-42129LS–SAM-D20_Summary–09/2014

5.2 Other Functions

5.2.1 Oscillator Pinout

The oscillators are not mapped to the normal PORT functions and their multiplexing are controlled by registers in the System Controller (SYSCTRL).

5.2.2 Serial Wire Debug Interface Pinout

After reset, SWCLK functionality is selected for pin PA30 to allow for debugger probe detection. The application software can switch the SWCLK functionality of PA30 to GPIO (or other peripherals) during runtime. PA31, by default, is config- ured like other normal I/O pins and will automatically switch to SWDIO function when a debugger cold-plugging or hot- plugging is detected. When the device is put in debug mode, application software accesses to PA30 and PA31 PORT registers are ignored. Oscillator Supply Signal I/O Pin XOSC VDDIO XIN PA14 XOUT PA15 XOSC32K VDDANA XIN32 PA00 XOUT32 PA01 Signal Supply I/O Pin SWCLK VDDIO PA30 SWDIO VDDIO PA31

19Atmel | SMART SAM D20 [DATASHEET Summary] Atmel-42129LS–SAM-D20_Summary–09/2014 6. Product Mapping Figure 6-1. SAM D20 Product Mapping This figure represents the full configuration of the Atmel® SAM D20 with maximum flash and SRAM capabilities and a full set of peripherals. Refer to the “Configuration Summary” on page 3 for details. Code SRAM Undefined Peripherals Reserved Undefined Global Memory Space 0x00000000 0x20000000 0x20008000 0x40000000 0x43000000 0x60000000 0x60000200 0xFFFFFFFF Internal SRAM SRAM 0x20000000 0x20008000 AHB-APB Bridge A AHB-APB Bridge B AHB-APB Bridge C Peripherals 0x40000000 0x41000000 0x42000000 0x42FFFFFF Reserved PAC0 PM SYSCTRL GCLK WDT RTC EIC AHB-APB Bridge A 0x40000000 0x40000400 0x40000800 0x40000C00 0x40001000 0x40001400 0x40001800 0x40FFFFFF 0x40001C00 AHB-APB Bridge B Reserved PAC1 DSU NVMCTRL PORT 0x41000000 0x41002000 0x41004000 0x41004400 0x41FFFFFF 0x41004800 Internal flash Code 0x00000000 0x00040000 0x1FFFFFFF Reserved SERCOM5 PAC2 EVSYS SERCOM0 SERCOM1 SERCOM2 SERCOM3 SERCOM4 AHB-APB Bridge C TC7 TC0 TC1 TC2 TC3 TC4 TC5 TC6 ADC AC 0x42000000 0x42000400 0x42000800 0x42000C00 0x42001000 0x42001400 0x42001800 0x42002000 0x42001C00 0x42003000 0x42003400 0x42003800 0x42003C00 0x42004000 0x42004400 0x42004800 Reserved 0x42FFFFFF DAC 0x42004C00 0x42002400 0x42002800 0x42002C00 PTC 0x42005000 Reserved System 0xE0000000 SCS Reserved Reserved ROM Table Reserved System 0xE0000000 0xE000E000 0xE000F000 0xE00FF000 0xE0100000 0xFFFFFFFF

20Atmel | SMART SAM D20 [DATASHEET Summary] Atmel-42129LS–SAM-D20_Summary–09/2014 7. Processor and Architecture

7.1 Cortex-M0+ Processor

The Atmel® SAM D20 implements the ARM® Cortex®-M0+ processor, which is based on the ARMv6 architecture and Thumb®-2 ISA. The Cortex M0+ is 100% instruction set compatible with its predecessor, the Cortex-M0 processor, and upward compatible with the Cortex-M3 and Cortex-M4 processors. The ARM Cortex-M0+ implemented is revision r0p1. For more information, refer to www.arm.com.

7.1.1 Cortex-M0+ Configuration

Note: 1. All software run in privileged mode only The ARM Cortex-M0+ processor has two bus interfaces: z Single 32-bit AMBA® 3 AHB-Lite™ system interface that provides connections to peripherals and all system memory, including flash and RAM z Single 32-bit I/O port bus interfacing to the PORT with one-cycle loads and stores Feature Configurable Option SAM D20 Configuration Interrupts External interrupts 0-32 32 Data endianness Little-endian or big-endian Little-endian SysTick timer Present or absent Present Number of watchpoint comparators 0, 1, 2 2 Number of breakpoint comparators 0, 1, 2, 3, 4 4 Halting debug support Present or absent Present Multiplier Fast or small Fast (single cycle) Single-cycle I/O port Present or absent Present Wake-up interrupt controller Supported or not supported Not supported Vector Table Offset Register Present or absent Present Unprivileged/Privileged support Present or absent Absent Memory Protection Unit Not present or 8-region Not present Reset all registers Present or absent Absent(1) Instruction fetch width 16-bit only or mostly 32-bit 32-bit

21Atmel | SMART SAM D20 [DATASHEET Summary] Atmel-42129LS–SAM-D20_Summary–09/2014 8. Packaging Information

8.1 Thermal Considerations

8.1.1 Thermal Resistance Data

Table 8-1 summarizes the thermal resistance data depending on the package. Table 8-1. Thermal Resistance Data

8.1.2 Junction Temperature

The average chip-junction temperature, TJ, in °C can be obtained from the following equations: Equation 1 Equation 2 where: z θJA = package thermal resistance, Junction-to-ambient (°C/W), provided in Table 8-1 z θJC = package thermal resistance, Junction-to-case thermal resistance (°C/W), provided in Table 8-1 z θHEATSINK = cooling device thermal resistance (°C/W), provided in the manufacturer datasheet z PD = device power consumption (W) z TA = ambient temperature (°C) From “Equation 1” , the user can derive the estimated lifetime of the chip and decide if a cooling device is necessary or not. If a cooling device is to be fitted on the chip, “Equation 2” should be used to compute the resulting average chip- junction temperature TJ in °C. Package Type θJA θJC 32-pin TQFP 68°C/W 25.8°C/W 48-pin TQFP 78.8°C/W 12.3°C/W 64-pin TQFP 66.7°C/W 11.9°C/W 32-pin QFN 37.2°C/W 3.1°C/W 48-pin QFN 33°C/W 11.4°C/W 64-pin QFN 33.5°C/W 11.2°C/W TJ TA PD θJA×()+= TJ TA PD θHEATSINK θJC+()×()+=

22Atmel | SMART SAM D20 [DATASHEET Summary] Atmel-42129LS–SAM-D20_Summary–09/2014

8.2 Package Drawings

8.2.1 64-pin TQFP Table 8-2. Device and Package Maximum Weight Table 8-3. Package Characteristics Table 8-4. Package Reference 300 mg Moisture Sensitivity Level MSL3 JEDEC Drawing Reference MS-026 JESD97 Classification E3

23Atmel | SMART SAM D20 [DATASHEET Summary] Atmel-42129LS–SAM-D20_Summary–09/2014 8.2.2 64-pin QFN Note: The exposed die attached pad is not connected inside the device. Table 8-5. Device and Package Maximum Weight Table 8-6. Package Characteristics Table 8-7. Package Reference 200 mg Moisture Sensitivity Level MSL3 JEDEC Drawing Reference MO-220 JESD97 Classification E3

24Atmel | SMART SAM D20 [DATASHEET Summary] Atmel-42129LS–SAM-D20_Summary–09/2014 8.2.3 64-ball UFBGA Table 8-8. Device and Package Maximum Weight Table 8-9. Package Characteristics Table 8-10. Package Reference TBD mg Moisture Sensitivity Level MSL3 JEDEC Drawing Reference MO-280 JESD97 Classification E3

25Atmel | SMART SAM D20 [DATASHEET Summary] Atmel-42129LS–SAM-D20_Summary–09/2014 8.2.4 48-pin TQFP Table 8-11. Device and Package Maximum Weight Table 8-12. Package Characteristics Table 8-13. Package Reference 140 mg Moisture Sensitivity Level MSL3 JEDEC Drawing Reference MS-026 JESD97 Classification E3

26Atmel | SMART SAM D20 [DATASHEET Summary] Atmel-42129LS–SAM-D20_Summary–09/2014 8.2.5 48-pin QFN Note: The exposed die attached pad is not connected inside the device. Table 8-14. Device and Package Maximum Weight Table 8-15. Package Characteristics Table 8-16. Package Reference 140 mg Moisture Sensitivity Level MSL3 JEDEC Drawing Reference MO-220 JESD97 Classification E3

27Atmel | SMART SAM D20 [DATASHEET Summary] Atmel-42129LS–SAM-D20_Summary–09/2014 8.2.6 45-ball WLCSP Note: The exposed die attached pad is not connected inside the device. Table 8-17. Device and Package Maximum Weight Table 8-18. Package Characteristics Table 8-19. Package Reference TBD mg Moisture Sensitivity Level MSL3 JEDEC Drawing Reference MO-220 JESD97 Classification E3

28Atmel | SMART SAM D20 [DATASHEET Summary] Atmel-42129LS–SAM-D20_Summary–09/2014 8.2.7 32-pin TQFP Table 8-20. Device and Package Maximum Weight Table 8-21. Package Characteristics Table 8-22. Package Reference 100 mg Moisture Sensitivity Level MSL3 JEDEC Drawing Reference MS-026 JESD97 Classification E3

29Atmel | SMART SAM D20 [DATASHEET Summary] Atmel-42129LS–SAM-D20_Summary–09/2014 8.2.8 32-pin QFN Note: The exposed die attached pad is connected inside the device to GND and GNDANA connected together. Table 8-23. Device and Package Maximum Weight Table 8-24. Package Characteristics Table 8-25. Package Reference 90 mg Moisture Sensitivity Level MSL3 JEDEC Drawing Reference MO-220 JESD97 Classification E3

30Atmel | SMART SAM D20 [DATASHEET Summary] Atmel-42129LS–SAM-D20_Summary–09/2014

8.3 Soldering Profile

Table Table 8-26 gives the recommended soldering profile from J-STD-20. Table 8-26. Soldering Profile A maximum of three reflow passes is allowed per component. Profile Feature Green Package Average Ramp-up Rate (217°C to peak) 3°C/s max. Preheat Temperature 175°C ±25°C 150-200°C Time Maintained Above 217°C 60-150s Time within 5°C of Actual Peak Temperature 30s Peak Temperature Range 260°C Ramp-down Rate 6°C/s max Time 25°C to Peak Temperature 8 minutes max.

31Atmel | SMART SAM D20 [DATASHEET Summary] Atmel-42129LS–SAM-D20_Summary–09/2014 Table of Contents

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