SAK-XC822-1FRA

XC822 INFINEON | Alldatasheet

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V1.1 2010-10 Microcontrollers XC822/824 8-Bit Single-Chip Microcontroller

81726 Munich, Germany

© 2010 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

V1.1 2010-10 Microcontrollers XC822/824 8-Bit Single-Chip Microcontroller

Data Sheet V1.1, 2010-10 XC822/824 Data Sheet Revision History: V1.1 2010-10 Previous Versions: V1.0 Page Subjects (major changes since last revision) Page 3 Automotive variants were added in Table 2. We Listen to Your Comments Is there any information in this document that you feel is wrong, unclear or missing? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: mcdocu.comments@infineon.com

Data Sheet 1 V1.1, 2010-10 Table of Contents

Data Sheet 2 V1.1, 2010-10

Data Sheet 1 V1.1, 2010-10

1 Summary of Features

The XC822/824 has the following features:

• High-performance XC800 Core – compatible with sta ndard 8051 processor – two clocks per machine cycl e architecture (for memory access without wait state) – two data pointers
• On-chip memory – 8 Kbytes of Boot ROM, Li brary ROM and User routines – 256 bytes of RAM – 256 bytes of XRAM – 2/4 Kbytes of Flash (includes memory protection strategy)
• I/O port supply at 2.5 V - 5.5 V and core logic supply at 2.5 V (generated by embedded voltage regulator) Figure 1 XC822/824 Functional Units
• Power-on reset generation
• Brownout detection for IO s upply and core logic supply
• 48 MHz on-chip OSC for clock generation – Loss-of-Clock detection (more features on next page) Port 0 Port 1 Port 2 XC800 Core UART ADC 10-bit 4-channel Boot ROM 8K Bytes XRAM

256 Bytes

Data Sheet 2 V1.1, 2010-10 Features: (continued)

• Power saving modes – idle mode – power-down mode with wake-up capability via real-time clock interrupt – clock gating control to each peripheral
• Programmable 16-bit Watchd og Timer (WDT) running on independent oscillator with programmable window feature for refresh operation and warning prior to overflow
• Three ports – Up to 17 pins as digital I/O – 4 pin as digi tal/analog input
• 4-channel, 10-bit ADC – support up to 3 di fferential input channel – results filtering by data re duction or digital low-pass filter, for up to 13-bit results
• Up to 4 channels, Ou t of range comparator
• Three 16-bit timers – Timer 0 and Time r 1 (T0 and T1) – Timer 2 (T2)
• Periodic wake-up timer
• Multiplication/Division Unit for arithmetic operations (MDU)
• Capture and Compare unit fo r PWM signal generation (CCU6)
• A full-duplex or half-dupl ex serial interface (UART)
• Synchronous serial channel (SSC)
• Inter-IC (IIC) serial interface
• LED and Touch-sense Controller (LEDTSCU)
• On-chip debug support via single pin DAP interface (SPD)
• Packages: – PG-DSO-20 – PG-TSSOP-16
• Temperature range T – SAF (-40 to 85 °C) – SAX (-40 to 105 °C) – SAK (-40 to 125 °C)

Data Sheet 3 V1.1, 2010-10 XC822/824 Variant Devices The XC822/824 product family features devices with di fferent configurations, program memory sizes, packages op tions and temperature profil es, to offer cost-effective solutions for different application requirements. The list of XC822/824 device configurations are summarized in Table 1. The type of packages available are TSSOP-16 for XC822 and DSO-20 for XC824. Table 2 shows the device sales type available, based on above device. Table 1 Device Configuration Device Name MDU Module LEDTSCU Module XC822/824 No No XC822/824M Yes No XC822/824T No Yes XC822/824MT Yes Yes Table 2 Device Profile Sales Type Device Type Program Memory (Kbytes) Temp- erature Profile (°C) Package Type Quality Profile SAF-XC822T-0FRI Flash 2 -40 to 85 PG-TSSOP-16 Industrial SAF-XC822-1FRI Flash 4 -40 to 85 PG-TSSOP-16 Industrial SAF-XC822T-1FRI Flash 4 -40 to 85 PG-TSSOP-16 Industrial SAF-XC822M-1FRI Flash 4 -40 to 85 PG-TSSOP-16 Industrial SAF-XC822MT-1FRI Flash 4 -40 to 85 PG-TSSOP-16 Industrial SAF-XC824M-1FGI Flash 4 -40 to 85 PG-DSO-20 Industrial SAF-XC824MT-1FGI Flash 4 -40 to 85 PG-DSO-20 Industrial SAX-XC824M-1FGI Flash 4 -40 to 105 PG-DSO-20 Industrial SAK-XC824M-1FGI Flash 4 -40 to 125 PG-DSO-20 Industrial SAF-XC822-1FRA Flash 4 -40 to 85 PG-TSSOP-16 Automotive SAF-XC822MT-1FRA Flash 4 -40 to 85 PG-TSSOP-16 Automotive SAK-XC822-1FRA Flash 4 -40 to 1 25 PG-TSSOP-16 Automotive SAK-XC822MT-1FRA Flash 4 -40 to 125 PG-TSSOP-16 Automotive

Data Sheet 4 V1.1, 2010-10 As this document refe rs to all the derivati ves, some descripti on may not apply to a specific product. For simplicity, all versions are referred to by the term XC822/824 throughout this document.

Ordering Information

The ordering code for Infi neon Technologies microcontrollers provides an exact reference to the required product. This ordering code identifies:

• The derivative itself, i.e. its function se t, the temperature range, and the supply voltage
• The package and the type of delivery For the available orderi ng codes for the XC82 2/824, please refer to your responsible sales representative or your local distributor.

General Device Information Data Sheet 5 V1.1, 2010-10

2 General Device Information

Chapter 2 contains the block diagram, pin configurations, definitions and functions of the XC822/824.

2.1 Block Diagram

The block diagram of the XC822/824 is shown in Figure 2. Figure 2 XC822/824 Block Diagram ADC Port 0Port 1Port 2 MDU SSC RTC 8-Kbyte Boot ROM1) 256-byte RAM 64-byte monitor RAM 256-byte XRAM 2/4-Kbyte Flash XC800 Core T0 & T1 UART 1) Includes 1-Kbyte monitor ROM P0.0 - P0.6 P1.0 - P1.5 P2.0 – P2.3 Clock Generator

48 MHz

General Device Information Data Sheet 6 V1.1, 2010-10

2.2 Logic Symbol

The logic symbol of the XC822/824 is shown in Figure 3. Figure 3 XC822/8 24 Logic Symbol XC824 VDDP VSSPVDDC Port 0 7-Bit Port 1 6-Bit Port 2 4-Bit XC822 VDDP VSSPVDDC Port 0 7-Bit Port 1 2-Bit Port 2 4-Bit

General Device Information Data Sheet 7 V1.1, 2010-10

2.3 Pin Configuration

The pin configuration of the XC822 in Figure 4. Figure 4 XC822 Pin Configurat ion, PG-TSSOP-16 Package (top view) P1.0/SPD_1/RXD_2/T2EX_2/EXINT0_2/ COL0_0/COUT60_0/TXD_1 P0.6/SPD_0/RXD_1/SDA_0/MTSR_1/MRST_0/ EXINT0_1/T2EX_0/LINE6/TSIN6/TXD_0/ COL2_1/COLA_1 P0.5/RXD_0/RTCCLK/MTSR_0/MRST_1/ EXINT0_0/LINE5/TSIN5/COUT62_1/TXD_3/ COL1_1/EXF2_2 P0.1/T0_0/CC61_1/MTSR_3/MRST_2/ T13HR_0/CCPOS1_0/LINE1/TSIN1 P0.2/T1_0/CC62_1/SCL_1/CCPOS2_0/ LINE2/TSIN2 P0.0/T2_0/T13HR_1/MTSR_2/ MRST_3/T12HR_0/CCPOS0_0/LINE0/ TSIN0/COUT61_1 VDDP VSSP VDDC P2.1/CCPOS1_1/RXD_3/MTSR_4/T0_1/ EXINT1_1/AN1 P1.2/EXINT4/COL2_0/COUT61_0/ COUT63_0 P2.2/CCPOS2_1/T12HR_3/T13HR_3/ SCK_1/T1_1/EXINT2/AN2 P2.0/CCPOS0_1/T12HR_2/T13HR_2/T2EX_3/ T2_1/EXINT0_3/AN0 P2.3/CCPOS0_2/CTRAP_2/T2_2/EXINT3/AN3 XC822 P0.3/CC60_1/SDA_1/CTRAP_0/ LINE3/TSIN3 P0.4/T2EX_1/SCL_0/SCK_0/EXINT1_0/ CTRAP_1/LINE4/TSIN4/EXF2_0/COL0_1/ COL3_1/COLA_2

General Device Information Data Sheet 8 V1.1, 2010-10 The pin configuration of the XC824 in Figure 5. Figure 5 XC824 Pin Configurat ion, PG-DSO-20 Package (top view) XC824 P1.0/SPD_1/RXD_2/T2EX_2/EXINT0_2/ COL0_0/COUT60_0/TXD_1 P1.4/EXINT5/COL4/COUT62_0/ COUT63_1 P0.6/SPD_0/RXD_1/SDA_0/MTSR_1/ MRST_0/EXINT0_1/T2EX_0/LINE6/TSIN6/ TXD_0/COL2_1/COLA_1 P1.5/CC62_0/COL5/COLA_0 P2.1/CCPOS1_1/RXD_3/MTSR_4/T0_1/ EXINT1_1/AN1 P1.2/EXINT4/COL2_0/COUT61_0/ COUT63_0 P2.2/CCPOS2_1/T12HR_3/T13HR_3/ SCK_1/T1_1/EXINT2/AN2 P1.1/CC60_0/COL1_0/TXD_2 P2.0/CCPOS0_1/T12HR_2/T13HR_2/ T2EX_3/T2_1/EXINT0_3/AN0 P2.3/CCPOS0_2/CTRAP_2/T2_2/ EXINT3/AN3 P0.5/RXD_0/RTCCLK/MTSR_0/MRST_1/ EXINT0_0/LINE5/TSIN5/COUT62_1/TXD_3/ COL1_1/EXF2_2 P1.3/CC61_0/COL3_0/CC61_0/EXF2_1 P0.1/T0_0/CC61_1/MTSR_3/MRST_2/ T13HR_0/CCPOS1_0/LINE1/TSIN1 P0.2/T1_0/CC62_1/SCL_1/CCPOS2_0/ LINE2/TSIN2 P0.0/T2_0/T13HR_1/MTSR_2/MRST_3/ T12HR_0/CCPOS0_0/LINE0/TSIN0/COUT61_1 VDDP VSSP VDDC P0.3/CC60_1/SDA_1/CTRAP_0/ LINE3/TSIN3 P0.4/T2EX_1/SCL_0/SCK_0/EXINT1_0/ CTRAP_1/LINE4/TSIN4/EXF2_0/COL0_1/ COL3_1/COLA_2

General Device Information Data Sheet 9 V1.1, 2010-10

2.4 Pin Definitions and Functions

The functions and default states of the XC822/824 external pins are provided in Table 3. Table 3 Pin Definitions and Functions for XC822/824 Symbol Pin Number DSO20/ TSSOP16 Type Reset State Function P0 I/O Port 0 Port 0 is a bidirectional general purpose I/O port. It can be used as alternate functions for LEDTSCU, Timer 0, 1 and 2, SSC, CCU6, IIC, SPD and UART. P0.0 15/12 Hi-Z T2_0 Timer 2 Input T13HR_1 CCU6 Timer 13 Hardware Run Input MTSR_2 SSC Master Transmit Output/ Slave Receive Input MRST_3 SSC Master Receive Input T12HR_0 CCU6 Timer 12 Hardware Run Input CCPOS0_0 CCU6 Hall Input 0 TSIN0 Touch-sense Input 0 LINE0 LED Line 0 COUT61_1 Output of Capture/Compare Channel 1

General Device Information Data Sheet 10 V1.1, 2010-10 P0.1 16/13 Hi-Z T0_0 Timer 0 Input CC61_1 Input/Output of Capture/Compare channel 1 MTSR_3 SSC Slave Receive Input MRST_2 SSC Master Receive Input/ Slave Transmit Output T13HR_0 CCU6 Timer 13 Hardware Run Input CCPOS1_0 CCU6 Hall Input 1 TSIN1 Touch-sense Input 1 LINE1 LED Line 1 P0.2 17/14 Hi-Z T1_0 Timer 1 Input CC62_1 Input/Output of Capture/Compare channel 2 SCL_1 IIC Clock Line CCPOS2_0 CCU6 Hall Input 2 TSIN2 Touch-sense Input 2 LINE2 LED Line 2 P0.3 18/15 Hi-Z CC60_1 Input/O utput of Capture/Compare channel 0 SDA_1 IIC Data Line CTRAP_0 CCU6 Trap Input TSIN3 Touch-sense Input 3 LINE3 LED Line 3 Table 3 Pin Definitions and Functions for XC822/824 Symbol Pin Number DSO20/ TSSOP16 Type Reset State Function

General Device Information Data Sheet 11 V1.1, 2010-10 P0.4 19/16 PD T2EX_1 Timer 2 External Trigger Input SCK_0 SSC Clock Input/Output SCL_0 IIC Clock Line CTRAP_1 CCU6 Trap Input EXINT1_0 External Interrupt Input 1 TSIN4 Touch-sense Input 4 LINE4 LED Line 4 EXF2_0 Timer 2 Overflow Flag COL0_1 LED Column 0 COL3_1 LED Column 3 COLA_2 LED Column A P0.5 20/1 Hi-Z RXD_0 UART Receive Input RTCCLK RTC External Clock Input MTSR_0 SSC Master Transmit Output/ Slave Receive Input MRST_1 SSC Master Receive Input EXINT0_0 External Interrupt Input 0 TSIN5 Touch-sense Input 5 LINE5 LED Line 5 COUT62_1 Output of Capture/Compare Channel 2 TXD_3 UART Transmit Output/ 2-wire UART BSL Transmit Output COL1_1 LED Column 1 EXF2_2 Timer 2 Overflow Flag Table 3 Pin Definitions and Functions for XC822/824 Symbol Pin Number DSO20/ TSSOP16 Type Reset State Function

General Device Information Data Sheet 12 V1.1, 2010-10 P0.6 1/2 PU SPD_0 SPD Input/Output RXD_1 UART Receive Input/ UART BSL Receive Input SDA_0 IIC Data Line MTSR_1 SSC Slave Receive Input MRST_0 SSC Master Receive Input/ Slave Transmit Output EXINT0_1 External Interrupt Input 0 T2EX_0 Timer 2 Exte rnal Trigger Input TSIN6 Touch-sense Input 6 LINE6 LED Line 6 TXD_0 UART Transmit Output/ 1-wire UART BSL Transmit Output COL2_1 LED Column 2 COLA_1 LED Column A P1 I/O Port 1 Port 1 is a bidirectional general purpose I/O port. It can be used as alternate functions for CCU6, LEDTSCU, SPD, UART and Timer 2. P1.0 8/7 Hi-Z SPD_1 SPD Input/Output RXD_2 UART Receive Input T2EX_2 Timer 2 Exte rnal Trigger Input EXINT0_2 External Interrupt Input 0 COL0_0 LED Column 0 COUT60_0 Output of Capture/Compare Channel 0 TXD_1 UART Transmit Output Table 3 Pin Definitions and Functions for XC822/824 Symbol Pin Number DSO20/ TSSOP16 Type Reset State Function

General Device Information Data Sheet 13 V1.1, 2010-10 P1.1 9/- Hi-Z CC60_0 Input/Output of Capture/Compare channel 0 COL1_0 LED Column 1 TXD_2 UART Transmit Output P1.2 10/8 Hi-Z EXINT4 External Interrupt Input 4 COL2_0 LED Column 2 COUT61_0 Output of Capture/Compare channel 1 COUT63_0 Output of Capture/Compare channel 3 P1.3 11/- Hi-Z CC61_0 Input/Out put of Capture/Compare channel 1 COL3_0 LED Column 3 EXF2_1 Timer 2 Overflow Flag P1.4 2/- Hi-Z EXINT5 External Interrupt Input 5 COL4 LED Column 4 COUT62_0 Output of Capture/Compare channel 2 COUT63_1 Output of Capture/Compare channel 3 P1.5 3/- Hi-Z CC62_0 Input/Output of Capture/Compare channel 2 COL5 LED Column 5 COLA_0 LED Column A P2 I Port 2 Port 2 is a general purpose input-only port. It can be used as inputs for A/D Converter and out of range comparator, CCU6, Timer 2, SSC and UART. Table 3 Pin Definitions and Functions for XC822/824 Symbol Pin Number DSO20/ TSSOP16 Type Reset State Function

General Device Information Data Sheet 14 V1.1, 2010-10 P2.0 7/6 Hi-Z CCPOS0_1 CCU6 Hall Input 0 T12HR_2 CCU6 Timer 12 Hardware Run Input T13HR_2 CCU6 Timer 13 Hardware Run Input T2EX_3 Timer 2 Exte rnal Trigger Input T2_1 Timer 2 Input EXINT0_3 External Interrupt Input 0 AN0 Analog Input 0 / Out of range comparator channel 0 P2.1 6/5 Hi-Z CCPOS1_1 CCU6 Hall Input 1 RXD_3 UART Receive Input MTSR_4 Slave Receive Input T0_1 Timer 0 Input EXINT1_1 External Interrupt Input 1 AN1 Analog Input 1 / Out of range comparator channel 1 P2.2 5/4 Hi-Z CCPOS2_1 CCU6 Hall Input 2 T12HR_3 CCU6 Timer 12 Hardware Run Input T13HR_3 CCU6 Timer 13 Hardware Run Input SCK_1 SSC Clock Input/Output T1_1 Timer 1 Input EXINT2 External Interrupt Input 2 AN2 Analog Input 2 / Out of range comparator channel 2 Table 3 Pin Definitions and Functions for XC822/824 Symbol Pin Number DSO20/ TSSOP16 Type Reset State Function

General Device Information Data Sheet 15 V1.1, 2010-10

2.5 Memory Organization

The XC822/824 CPU operates in the following five address spaces:

• 8 Kbytes of Boot ROM, Li brary ROM and User routines
• 256 bytes of internal RAM
• 256 bytes of XRAM (XRAM can be read/written as program memory or external data memory)
• A 128-byte Special Function Register area
• 2/4 Kbytes of Flash Figure 6 illustrates the memory address spaces of the 2 Kbyte Flash devices. There are two 1-Kbyte sectors in this device. Figure 7 illustrates the memo ry address spaces of the 4 Kbyte Flash devices. This device has two 1-Kbyte sectors, two 512-byte sectors, two 256-byte sectors and four 128-byte sectors. Figure 8 shows the Flash sectorization for 2 Kbyte and 4 Kbyte Flash devices. P2.3 4/3 Hi-Z CCPOS0_2 CCU6 Hall Input 0 CTRAP_2 CCU6 Trap Input T2_2 Timer 2 Input EXINT3 External Interrupt Input 3 AN3 Analog Input 3 / Out of range comparator channel 3 V DDP 12/9 – I/O Port Supply (2.5 V - 5.5 V) VDDC 14/11 – Core Supply Output (2.5 V) VSSP/ VSSC 13/10 – I/O Port Ground/ Core Supply Ground Table 3 Pin Definitions and Functions for XC822/824 Symbol Pin Number DSO20/ TSSOP16 Type Reset State Function

General Device Information Data Sheet 16 V1.1, 2010-10 Figure 6 Memory Map of XC822/824 with 2 Kbytes of Flash memory 0000H 0800H F000H C000H E000H F100H FFFFH Flash Bank 0

2 KBytes

8 KBytes

256 Bytes F000H

Code Space External Data Space Internal Data Space Internal RAM Memory Map User Mode XRAM

2 KBytes 1)

In Debug Mode, this 64-byte address area is replaced by a 64-byte Monitor RAM. 40H 1) Physically one 2-Kbyte Flash bank , mapped to both address range .

General Device Information Data Sheet 17 V1.1, 2010-10 Figure 7 Memory Map of XC822/824 with 4 Kbytes of Flash memory 0000H 1000H F000H C000H E000H F100H FFFFH Flash Bank 0

4 KBytes

Code Space External Data Space Internal Data Space Internal RAM Memory Map User Mode XRAM

4 KBytes 1)

In Debug Mode, this 64-byte address area is replaced by a 64-byte Monitor RAM. 40H 1) Physically one 4-Kbyte Flash bank , mapped to both address range .

General Device Information Data Sheet 18 V1.1, 2010-10 Figure 8 Flash Bank Sectorization

2.6 JTAG ID

JTAG ID register is a read-only register located inside the JTAG module, and is used to recognize the device(s) connected to the JTAG interface. Its content is shifted out when INSTRUCTION register contains the IDCODE command (opcode 04H), and the same is also true immediately after reset. The JTAG ID register contents for the XC822/824 Flash devices are given in Table 4. Note: The asterisk (*) above denotes all possible device configurations. Table 4 JTAG ID Summary Device Type Device Name JTAG ID Flash XC822/824* 101B C083 H Sector 9: 128-byte Sector 5: 256-byte Sector 3: 512-byte Sector 1: 1-Kbyte 1) Sector 0: 1-Kbyte 1) Sector 7: 128-byte Sector 8: 128-byte Sector 6: 128-byte Sector 4: 256-byte Sector 2: 512-byte 1x Flash Bank 1) 2 Kbyte Flash devices only has sector 0 and sector 1.

General Device Information Data Sheet 19 V1.1, 2010-10

2.7 Chip Identification Number

The XC822/824 identity (ID) register is located at Page 1 of address B3 H. The value of ID register is 51 H. However, for easy identificati on of product variants, the Chip Identification Number, which is an unique number assigned to each product variant, is available. The differentiation is based on the product and variant type information. Two methods are provided to read a device’s Chip Identification number:

• In-application subr outine, GET_CHIP_INFO
• Boot-loader (BSL) mode A Table 5 lists the Chip Identification numbers of XC822/824 device variants. Table 5 Chip Identification Number Product Variant Chip Identification Number XC822T-0FRI 51080343 H XC822-1FRI 51080163 H XC822T-1FRI 51080143 H XC822M-1FRI 51080123 H XC822MT-1FRI 51080103 H XC824M-1FGI 51080122 H XC824MT-1FGI 51080102 H

Data Sheet 20 V1.1, 2010-10

3 Electrical Parameters

Chapter 3 provides the characteristics of th e electrical parameters which are implementation-specific for the XC822/824.

3.1 General Parameters

The general parameters are described here to aid the us ers in interpreting the parameters mainly in Section 3.2 and Section 3.3.

3.1.1 Parameter Interpretation

The parameters listed in this section represent part ly the characteristics of the XC822/824 and partly its requirements on the system. To aid interpreting the parameters easily when evaluating them for a design, they are indicated by the abbreviations in the “Symbol” column:

• CC – These parameters indicate Controller Characteristics, which are distinctive features of the XC822/824 and must be regarded for a system design.
• SR – These paramete rs indicate System Requirements, which must be provided by the microcontroller system in which the XC822/824 is designed in.

Data Sheet 21 V1.1, 2010-10

3.1.2 Absolute Maximum Rating

Maximum ratings are the extreme limits to which the XC822/8 24 can be subjected to without permanent damage. Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During absolute maximum rating overload conditions (VIN > VDDP or VIN < VSS) the voltage on VDDP pin with respect to ground ( VSS) must not exceed the values defined by the absolute maximum ratings. Table 6 Absolute Maximu m Rating Parameters Parameter Symbol Limit Values Unit Notes Min. Max. Ambient temperature TA -40 125 °C under bias Storage temperature TST -65 150 °C– Junction temperature TJ -40 150 °C under bias Voltage on power supply pin with respect to VSS VDDP -0.5 6 V Input current on any pin during overload condition IIN -10 10 mA Absolute sum of all input currents during overload condition Σ|IIN|– 5 0 m A

Data Sheet 22 V1.1, 2010-10

3.1.3 Operating Condition

The following operating conditions must not be exceed ed in order to ensure correct operation of the XC822/824. All parameters menti oned in the following tables refer to these operating conditions, unless otherwise noted. Table 7 Operating Condition Parameters Parameter Symbol Limit Values Unit Notes/ ConditionsMin. Max. Digital power supply voltage VDDP 3.0 5.5 V 2.5 3.0 V 1) In this voltage range, limited operations are available in active mode. Operations in power save modes are fully supported. CPU Clock Frequency fCCLK 22.5 25.6 MHz typ. 24 MHz 7.5 8.5 MHz typ. 8 MHz Ambient temperature TA -40 85 °C SAF-XC822/824... -40 105 °C SAX-XC824... -40 125 °C SAK-XC824...

Data Sheet 23 V1.1, 2010-10

3.2 DC Parameters

The electrical characteristics of the DC Parameters are detailed in this section.

3.2.1 Input/Output Characteristics

Table 8 provides the characteristics of the input/output pins of the XC822/XC824. Table 8 Input/Output Characteristics of XC822/XC824 (Operating Conditions apply) Parameter Symbol Limit Valu es Unit Test Conditions Min. Max. Output low voltage on port pins VOLP CC – 1.0 V IOL = 25 mA (5 V) IOL = 13 mA (3.3 V) –0 . 4 V IOL = 10 mA (5 V) IOL =5m A ( 3 . 3V ) Output high voltage on port pins VOHP CC VDDP - 1.0 –V IOH =- 1 5m A ( 5V ) IOH = -8 mA (3.3 V ) VDDP - 0.4 –V IOH = -5 mA (5 V) IOH = -2.5 mA (3.3 V) Input low voltage on port pins VILP SR – 0.3 × VDDP V CMOS Mode Input high voltage on port pins VIHP SR 0.7 × VDDP –V C M O S M o d e Input Hysteresis1) HYS CC 0.08 × VDDP –V C M O S M o d e ( 5 V ) 0.03 × VDDP – V CMOS Mode (3.3 V) 0.01 × VDDP – V CMOS Mode (2.5 V) Pull-up current on port pins IPUP CC – -20 µA VIH,min (5 V) -150 – µA VIL,max (5 V) –- 5 µA VIH,min (3.3 V) -100 – µA VIL,max (3.3 V)

Data Sheet 24 V1.1, 2010-10 Pull-down current on port pins IPDP CC – 20 µA VIL,max (5 V) 150 – µA VIH,min (5 V) –5 µA VIL,max (3.3 V) 100 – µA VIH,min (3.3 V) Input leakage current on port pins2) IOZP CC -1 1 µA0 < VIN < VDDP, TA ≤ 125 °C Overload current on any pin IOVP SR -5 5 mA 3) Absolute sum of overload currents IOV|S R– 2 5 m A 3) Voltage on any pin during VDDP power off VPO SR – 0.3 V 4) Maximum current per pin (excluding VDDP and VSS) IM SR -15 25 mA – Maximum current into VDDP IMVDDP SR – 80 mA 3) Maximum current out of VSS IMVSS SR – 80 mA 3) 1) Not subjected to production test, verified by design/characterization. Hysteresis is implemented to avoid meta stable states and switching due to internal ground bounce. It cannot be guaranteed that it suppresses switching due to external system noise. 2) An additional error current ( IINJ) will flow if an overload current flows through an adjacent pin. 3) Not subjected to production test, verified by design/characterization. 4) Not subjected to production test, verified by design/char acterization. However, for applications with strict low power-down current requirements, it is mandatory that no active voltage source is supplied at any GPIO pin when VDDP is powered off. Table 8 Input/Output Characteristics of XC822/XC824 (Operating Conditions apply) (cont’d) Parameter Symbol Limit Valu es Unit Test Conditions Min. Max.

Data Sheet 25 V1.1, 2010-10

3.2.2 Supply Threshold Characteristics

Table 9 provides the characteristics of the supply threshold in the XC822/824. Figure 9 Supply Threshold Parameters Table 9 Supply Threshold Paramete rs (Operating Conditions apply) Parameters Symbol Limit Values Unit Min. Typ. Max. VDDP prewarning voltage1)2) 1) Detection is enabled via SDCON register in active mode. It is automatically disabled in power down mode. Detection should be disabled for VDDP less than maximum of VDDPPW. 2) This parameter has a hysteresis of 50 mV. VDDPPW CC 3.0 3.6 4.5 V VDDP brownout voltage in active mode3)2) 3) Detection is enabled via SDCON register. Dete ction must be disabled for application with VDDP less than the specified values. VDDPBOA CC 2.65 2.75 2.87 V VDDP brownout voltage in power down mode2)3) VDDPBOPD CC 3.0 3.6 4.5 V VDDP system reset release voltage2)4) 4) V DDPSRR and VDDCSRR must be met before the system reset is released. VDDPSRR CC 2.7 2.8 2.92 V VDDC prewarning voltage2)5) 5) Detection is enabled via SDCON register in active mode. It is automatically disabled in power down mode. VDDCPW CC 2.3 2.4 2.48 V VDDC brownout voltage in active mode2) VDDCBOA CC 2.25 2.3 2.42 V VDDC brownout voltage in power down mode2) VDDCBOPD CC 1.35 1.5 1.95 V VDDC system reset release voltage2)4) VDDCSRR CC 2.28 2.3 2.47 V RAM data retention voltage VDDCRDR CC 1.1 – – V VDDP VDDC VDDPPW/VDDPBOPD VDDCSRR VDDCPW VDDCBOA VDDCRDR 5.0V 2.5V VDDCBOPD VDDPBOAVDDPSRR

Data Sheet 26 V1.1, 2010-10

3.2.3 ADC Characteristics

The values in Table 10 are given for an analog power supply of 5.0 V. The ADC can be used with an analog power supply down to 3 V. But in this case, analog parameters may show a reduced performances. In the reduced vo ltage mode (2.5 V < VDDP < 3 V), the ADC is not recommended to be used. Table 10 ADC Characteristics (O perating Conditions apply; VDDP = 5 V) Parameter Symbol Limit Valu es Unit Test Conditions / RemarksMin. Typ. Max. Analog reference voltage VAREF – VDDP – V Connect internally to VDDP Analog reference ground VAGND – VSSP – V Connect internally to VSSP Alternate analog reference ground VAGNDALT SR VSSP - 0.1 –2 . 5 1) V Connect to AN0 in differential mode, See Figure 10. Internal voltage reference VINTREF SR 1.19 1.23 1.28 V 3) Analog input voltage range VAIN SR VAGND – VAREF V– ADC clock fADCI 8 – 16 MHz internal analog clock Sample time tS CC (2 + INPCR0.STC) × tADCI µs– Conversion time tC CC See Section 3.2.3.1 µs– Total unadjusted error TUE2) CC – – ±1 LSB8 8-bit conversion with internal reference3) – – +4/-1 LSB10 10-bit conversion with internal reference3)4) – – +14/-2 LSB12 12-bit conversion using the Low Pass Filter 3) Differential Nonlinearity EADNL CC – – +1.5/ -1 LSB 10-bit conversion 3)

Data Sheet 27 V1.1, 2010-10 Integral Nonlinearity EAINL CC – – ±1.5 LSB 10-bit conversion 3) Offset EAOFF CC – +4 – LSB 10-bit conversion 3) Gain EAGAIN CC – -4 – LSB 10-bit conversion 3) Switched capacitance at an analog input CAINSW CC – 2 3 pF 3)5) Total capacitance at an analog input CAINT CC – – 12 pF 3)5) Input resistance of an analog input RAIN CC – 1.5 2 k Ω 3) 1) 1.2 V at VDDP =3 . 0V . 2) TUE is tested at VAREF = VDDP = 5.0 V and CPU clock (fSCLK, CCLK )=8M H z . 3) Not subject to production test, verified by design/characterization. 4) If a reduced positive reference voltage is used, TUE w ill increase. If the positive reference is reduced by a 5) The sampling capacity of the conversion C-Network is pre-charged to VAREF/2 before connecting the input to the C-Network. Because of the parasitic elements, the voltage measured at ANx is lower than VAREF/2. Table 10 ADC Characteristics (O perating Conditions apply; VDDP = 5 V) Parameter Symbol Limit Valu es Unit Test Conditions / RemarksMin. Typ. Max.

Data Sheet 29 V1.1, 2010-10

3.2.3.1 ADC Conversion Timing

Conversion time, tC = tADC × (1 + r × ( 3+n+S T C ) ) , w h e r e

• r=C T C+3 ,
• CTC = Conversion Time Control (GLOBCTR.CTC),
• STC = Sample Time Control (INPCR0.STC),
• n = 8 or 10 (for 8-bit and 10-bit conversion respectively), tADC =1/ fADC

3.2.3.2 Out of Range Comparator Characteristics

Table 11 below shows the Out of Range Comparator characteristics. Table 11 Out of Range Comparator Ch aracteristics (Operating Conditions apply) Parameter Symbol Limit Values Unit Remarks Min. Typ. Max. DC Switching Level VSenseDC SR 60 125 270 mV Above VDDP DC Hysteresis VSenseHys CC 30 – – mV 1) 1) Not subject to production test, verified by design/characterization. Pulse Width tSensePW SR 300 – – ns ANx > VDDP Switching Delay tSenseSD CC – – 400 ns ANx >= VDDP +3 5 0m V1) Pulse Switching Level tSensePSL SR – 250 – mV @ 300 nsec 1) SR – 60 – mV @ 800 usec 1)

Data Sheet 30 V1.1, 2010-10

3.2.4 Flash Memory Parameters

The XC822/824 is delivered with all Flash sectors erased (read all zeros). The data retention time of the XC822/824’s Flash memory (i.e. the time after which stored data can still be retrieved) depends on the number of times the Flash memory has been erased and programmed. Note: Flash memory parameters are not subject to production test but verified by design and/or characterization. Table 12 Flash Timing Parameters (Operating Conditions apply) Parameter Symbol Limit Values Unit Remarks Min. Typ. Max. Read access time (per byte) tACC CC – 125 – ns Programming time (per wordline) tPR CC – 2.2 – ms Erase time (one or more sectors) tER CC – 120 – ms Flash wait states NWSFLASH CC 0 CPU clock = 8 MHz 1C P U c l o c k = 2 4 M H z Table 13 Flash Data Retent ion and Endurance (Operating Conditions apply) Retention Endurance 1) 1) One cycle refers to the pr ogramming of all wordlines in a sector and erasing of sector. The Flash endurance data specified in Table 13 is valid only if the following conditions are fulfilled: - the maximum number of erase cycles per Flash sector must not exceed 100,000 cycles. - the maximum number of erase cycles per Flash bank must not exceed 300,000 cycles. - the maximum number of program cycles per Flash bank must not exceed 2,500,000 cycles. Size Remarks 20 years 1,000 cycl es up to 8 Kbytes 5 years 10,000 cycles 1 Kbyte 2 years 70,000 cycles 512 bytes 2 years 100,000 cycles 128 bytes

Data Sheet 31 V1.1, 2010-10 Table 14 Emulated Flash Data Retent ion and Endurance based on EEPROM Emulation ROM Library (Operating Conditions apply)1) 1) EEPROM Emulation ROM Library can only be used in the 4 Kbyte Flash variant. Retention Endurance 2) 2) These values show the maximum endurance. Maximum endurance is the maximum possible unique data write if each data update is only 31 bytes. Minimum endurance cycle is the maximum possible unique data write if each data update is the same as the emulation size. The minimum endurance cycle can be calculated using the formulae [(max. endurance)*(31)/(emulation size)]. Emulation Size Remarks 2 years 1,600,000 cycles 31 bytes 2 years 1,400,000 cycles 62 bytes 2 years 1,200,000 cycles 93 bytes 2 years 1,000,000 cycles 124 bytes

Data Sheet 32 V1.1, 2010-10

3.2.5 Power Supply Current

Table 15 provides the characteristics of the power supply current in the XC822/824. Table 15 Power Cons umption Parameters1) 2)(Operating Conditions apply) 1) The typical values are measured at TA =+2 5 °C and VDDP = 5 V and 3.3 V. 2) The maximum values are measured under worst case conditions ( TA =+1 2 5 °C and VDDC =5V ) . Parameter Symbol Limit Va lues Unit Test Condition Typ. Max. Active Mode IDDPA 21 25 mA 5 V / 3.3 V 3) 3) IDDPA (active mode) is measured with: CPU clock and input clock to all peripherals running at 24 MHz (CLKMODE=0). 14 18 mA 5 V / 3.3 V 4) 4) IDDPA (active mode) is measured with: CPU clock and input clock to all peripherals running at 8 MHz (CLKMODE=1). –5 m A 2 . 5 V 5) 5) This value is based on the maximum load capacity of EVR during VDDP = 2.5 V. Not subject to production test, verified by design/characterisation. Idle Mode IDDPI 16 20 mA 5 V / 3.3 V 6) 6) IDDPI (idle mode) is measured with: CPU clock disabled, watchdog timer disabled, input clock to all peripherals enabled and running at 24 MHz (CLKMODE=0). –5 m A 2 . 5 V 5) Power Down Mode 1 IPDP1 35 µA TA = 25° C7) 7) IPDP1 and IPDP2 is measured at 5 V and 3.3 V with: wake-up port is programmed to be input with either internal pull devices enabled or driven externally to ensure no floating inputs. –2 8 µA TA = 85° C7)8)9) 8) Not subject to production test, verified by design/characterisation. 9) IPDP1 and IPDP2 has a maximum values of 100 uA at TA = + 125 °C. Power Down Mode 2 IPDP2 57 µA TA = 25° C7) –3 0 µA TA = 85° C7)8)

Data Sheet 33 V1.1, 2010-10 Table 16 shows the maximum active current with in the device in the reduced voltage condition of 2.5 V < VDDP < 3.0 V. The active current consumption needs to be below the specified values as according to the V DDP voltage. If the conditions are not met, a brownout reset may be triggered. Table 17 provides the active current consumption of some modules operating at 8 MHz active mode, 3 V power supply at 25 ° C. The typical values shown are used as a reference guide for device operating in reduced voltage conditions. Table 16 Active Current Consumpti on in Reduced Voltage Condition VDDP 2 . 5V 2 . 6V 2 . 7V 2 . 8V Maximum active current 7m A 1 3m A 2 0m A 2 5m A Table 17 Typical Active Current Consumption1) 2) 1) Modules that are controllable by programming the register PMCON1. 2) Not subject to production test, verified by design/characterisation. Active Current Consumption Symbol Limit Values Unit Test Condition Typ. Baseload current3) 3) Baseload current is measured when the device is running in user mode with an endless loop in the flash memory. All modules in register PMCON1 are disabled. ICPUDDC 5850 µA Modules including Core, memories, UART, T0, T1 and EVR. Disable ADC analog (GLOBCTR.ANON = 0). ADC4) 4) ADC active current is measured with: module enable, ADC analog clock at 8MHz, running in parallel conversion request in autoscan mode for 4 channels IADCDDC 3390 µA Set PMCON1.ADC_DIS to 0 and GLOBECTR. ANON to 1 SSC5) 5) SSC active curremt is measured with: module enabled, running in loop back mode at a baud rate of 1 MBaud ISSCDDC 460 µA Set PMCON1.SSC_DIS to 0 CCU66) 6) CCU6 active current is measured with: module enabled, all timers running in 8 MHz, 6 PWM outputs are generated. ICCU6DDC 3320 µA Set PMCON1.CCU_DIS to 0 Timer 27) 7) Timer 2 active current is measured with: module enabled, timer running in 8 MHz IT2DDC 200 µA Set PMCON1.T2_DIS to 0 MDU8) 8) MDU active current is measured with: module enabled, division operation was performed. IMDUDDC 1260 µA Set PMCON1.MDU_DIS to 0 LEDTSCU9) ILEDDDC 520 µA Set PMCON1.LTS_DIS to 0 IIC10) IIICDDC 580 µA Set PMCON1.IIC_DIS to 0

Data Sheet 34 V1.1, 2010-10 9) LEDTSCU active curent is measured with : module enabled, counter running in 8 MHz. 10) IIC active current is measured with: module enabled , performing a master transmit with the master clock running at 400 KHz.

Data Sheet 35 V1.1, 2010-10

3.3 AC Parameters

The electrical characteristics of the AC Parameters are detailed in this section.

3.3.1 Testing Waveforms

The testing waveforms for ri se/fall time, output delay and output high impedance are shown in Figure 12, Figure 13 and Figure 14. Figure 12 Rise/Fall Time Parameters Figure 13 Testing Waveform, Output Delay Figure 14 Testing Waveform , Output High Impedance 10% 90% 10% 90% VSS VDDP tR tF VDDE / 2 Test Points VDDE / 2 VSS VDDP VLoad + 0.1 V VOH - 0.1 VTiming Reference PointsVLoad - 0.1 V VOL - 0.1 V

Data Sheet 36 V1.1, 2010-10

3.3.2 Output Rise/Fall Times

Table 18 provides the characteristics of the output rise/fall times in the XC822/824. Figure 15 Rise/Fall Times Parameters Table 18 Output Rise/Fall Times Para meters (Operating Conditions apply) Parameter Symbol Limit Valu es Unit Test Conditions Min. Max. Rise/fall times on Standard Pad1)2) 1) Rise/Fall time parameters are taken with 10% - 90% of supply. 2) Not all parameters are 100% tested, but are verified by design/characterisation and test correlation. tR, tF –1 0 n s 2 0 p F 3)4) (5 V & 3.3 V). 3) Additional rise/fall time valid for C L =2 0p F-C L = 100 pF @ 0.125 ns/pF at 5 V supply voltage. 4) Additional rise/fall time valid for C L =2 0p F-C L = 100 pF.@ 0.225 ns/pF at 3.3 V supply voltage. tR 10% 90% 10% 90% tF VSS VDDC

Data Sheet 37 V1.1, 2010-10

3.3.3 Oscillator Timing and Wake-up Timing

Table 19 provides the characteristics of the power-on reset, PLL and Wake-up timings in the XC822/824.

3.3.4 On-Chip Oscillator Characteristics

Table 20 provides the characteristics of the 48 MHz oscillator in the XC822/824. Table 19 Power-On Reset Wake-up Timing 1) (Operating Conditions apply) 1) Not subject to production test, verified by design/characterisation. Parameter Symbol Limit Va lues Unit Test Conditions Min. Typ. Max.

48 MHz Oscillator

t48MOSCST CC – – 13 µs

75 KHz Oscillator start-

t75KOSCST CC – – 800 µs Flash initialization time tFINT CC – 160 – µs Table 20 48 MHz Oscillator Characteri stics (Operating Conditions apply) Parameter Symbol Limit Valu es Unit Test Conditions Min. Typ. Max. Nominal frequency fNOM CC -0.5 % 48 +0.5% MHz under nominal conditions1) after trimming 1) Nominal condition: VDDC =2 . 5V , TA =+2 5 °C. Long term frequency deviation ∆fLT CC -2.0 – 3.0 % with respect to fNOM, over lifetime and temperature (0 °C to 85 °C) -4.5 – 4.5 % with respect to fNOM, over lifetime and temperature (-40 °C to 125 °C) Short term frequency deviation (over core supply voltage 2)) 2) Core voltage supply, VDDC = 2.5 V ± 7.5%. ∆fST CC -1 – 1 % with respect to fNOM, within one LIN message (< 10 ms … 100 ms)

Data Sheet 38 V1.1, 2010-10 Table 21 provides the characteristics of the 75 kHz oscillator in the XC822/824. Table 21 75 kHz Oscillator Characteri stics (Operating Conditions apply) Parameter Symbol Limit Values Unit Test Conditions Min. Typ. Max. Nominal frequency fNOM CC -1% 75 +1% KHz under nominal conditions 1) after trimming 1) Nominal condition: VDDC =2 . 5V , TA =+2 5 °C. Long term frequency deviation ∆fLT CC -4.5 – 4.5 % with respect to fNOM, over lifetime and temperature (-40 °C to 125 °C) Short term frequency deviation ∆fST CC -1.5 – 1.5 % with respect to fNOM, over core supply voltage of 2.5 V ± 7.5%

Data Sheet 39 V1.1, 2010-10

3.3.5 SSC Timing

3.3.5.1 SSC Master Mode Timing

Table 22 provides the SSC master mode timing in the XC822/824. Figure 16 SSC Master Mode Timing Table 22 SSC Master Mode Timing 1) (Operating Conditions apply; CL = 50 pF) 1) Not subject to production test, verified by design/characterisation. Parameter Symbol Limit Values Unit Min. Max. SCLK clock period t0 CC 2 * T SSC 2) T SSCmin =T CPU =1 /fCPU. When fCPU = 24 MHz, t0 = 83.3 ns. TCPU is the CPU clock period. –n s MTSR delay from SCLK t1 CC 0 6 ns MRST setup to SCLK t2 SR 20 – ns MRST hold from SCLK t3 SR 0 – ns SSC_Tmg1 SCLK1) MTSR1) t1 t1 MRST1) Data valid 1) This timing is based on the following setup: CON.PH = CON.PO = 0.

Data Sheet 40 V1.1, 2010-10

3.3.5.2 SSC Slave Mode Timing

Table 23 provides the SSC slave mode timing in the XC822/824. Figure 17 SSC Slave Mode Timing Table 23 SSC Slave Mode Timing 1) (Operating Conditions apply; CL = 50 pF) 1) Not subject to production test, verified by design/characterisation. Parameter Symbol Limit Values Unit Min. Max. SCLK clock period t0 SR 4 * T SSC 2) T SSCmin =T CPU =1 /fCPU. When fCPU = 24 MHz, t0 = 166.7 ns. TCPU is the CPU clock period. –n s MRST delay from SCLK t1 CC 0 20 ns MTSR setup to SCLK t2 SR 46 – ns MTSR hold from SCLK t3 SR 0 – ns SCLK1) MTSR1) MRST1) Data Valid 1) This timing is based on the following setup : CON.PH = CON.PO = 0.

Data Sheet 41 V1.1, 2010-10

3.3.6 SPD Timing

The SPD interface will work with standard SPD tools having a sample/output clock fre- quency deviation of +/- 5% or less. For further details please refer to application note AP24004 in section SPD Timing Requirements. Note: These parameters are no subject to pr oduct test but verifi ed by design and/or characterization. Note: Operating Conditions apply.

Package and Quality Declaration Data Sheet 42 V1.1, 2010-10

4 Package and Quality Declaration

Chapter 4 provides the information of the XC822/824 package and reliability section.

4.1 Package Parameters

Table 24 provides the thermal characteristic s of the packages used in XC822 and XC824 respectively. Table 24 Thermal Characte ristics of the Packages Parameter Symbol Limit Va lues Unit Package Types Min. Max. Thermal resistance junction case1) 1) The thermal resistances between the case and the ambient ( RTCA) , the lead and the ambient (RTLA) are to be combined with the thermal resistances between the junction and the case ( RTJC), the junction and the lead (RTJL) given above, in order to calculate the total t hermal resistance between the junction and the ambient (RTJA). The thermal resistances between the case and the ambient ( RTCA), the lead and the ambient ( RTLA) depend on the external system (PCB, case) characteristics, and are under user responsibility. The junction temperature can be calculated using the following equation: TJ=TA+RTJA × PD, where the RTJA is the total thermal resistance between the junction and the ambient. This total junction ambient resistance RTJA can be obtained from the upper four partial thermal resistances, by a) simply adding only the two thermal resistances (junction lead and lead ambient), or b) by taking all four resistances into account, depending on the precision needed. RTJC CC - 36.2 K/W PG-TSSOP-16-1 - 34.3 K/W PG-DSO-20-45 Thermal resistance junction lead1) RTJL CC - 356.6 K/W PG-TSSOP-16-1 - 36.2 K/W PG-DSO-20-45

Package and Quality Declaration Data Sheet 43 V1.1, 2010-10

4.2 Package Outline

Figure 18 and Figure 19 shows the package outlines of the XC822 (TSSOP-16) and XC824 (DSO-20) devices respectively. Figure 18 PG-TSSOP-16-1 Package Outline

Package and Quality Declaration Data Sheet 44 V1.1, 2010-10 Figure 19 PG-DSO-20-45 Package Outline

Package and Quality Declaration Data Sheet 45 V1.1, 2010-10

4.3 Quality Declaration

Table 25 shows the characteristics of the quality parameters in the XC822/824. Table 25 Quality Parameters Parameter Symbol Limit Values Unit Notes Min. Max. Operation Lifetime when the device is used at the three stated T J 1) This lifetime refers only to the time when device is powered-on. tOP1 - 1500 hours TJ =1 5 0°C - 15000 hours TJ =1 1 0°C - 1500 hours TJ =- 4 0°C Operation Lifetime when the device is used at the stated TJ tOP2 - 131400 hours TJ =2 7°C ESD susceptibility according to Human Body Model (HBM) VHBM - 2000 V Conforming to EIA/JESD22- A114-B ESD susceptibility according to Charged Device Model (CDM) pins VCDM - 500 V Conforming to JESD22-C101-C

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