SAFC501

C501 SIEMENS | Alldatasheet

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Data Sheet 04.97 Microcomputer Components C501 8-Bit CMOS Microcontroller

Siemens AG, Bereich Halbleiter, Marketing- Kommunikation, Balanstraße 73,

81541 München

Siemens AG 1997. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide (see address list). Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Siemens Office, Semiconductor Group. Siemens AG is an approved CECC manufacturer. Packing Please use the recycling operators known to you. We can also help you – get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs in- curred. Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems with the express written approval of the Semiconductor Group of Siemens AG. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain hu- man life. If they fail, it is reasonable to assume that the health of the user may be endangered. C501 Data Sheet Revision History : 1997-04-01 Page (previous version) Page (new version) Subjects (changes since last revision) general C501G-1E OTP version included 5-7 8, 9, 10 15-18 5-7 8, 9, 10 16-18 25-28 43, 44 Ordering information resorted and C501G-1E types added Table with literature hints added Pin configuration logic symbol for pins EA /Vpp and ALE/PROG updated Pin description for ALE/PROG and EA/Vpp completed Port 1, 3, 2 pin description: “bidirectional” replaced by “quasi- bidirectional” Block diagram updated for C501G-1E New design of register (PSW) description “Memory organization” added Actualized design of the SFR tables Reset value of T2CON corrected Description for the C501-1E OTP version added DC characteristics for C501-1E added Timing “External Clock Drive” now behind “Data Memory Cycle” AC characteristics for C501-1E added

Semiconductor Group 3 1997-04-01 8-Bit CMOS Microcontroller Preliminary C501 Fully compatible to standard 8051 microcontroller Versions for 12/24/40 MHz operating frequency Program memory : completely external (C501-L)

8 ROM (C501-1R)

8 OTP memory (C501-1E)

8 RAM

Three 16-bit timers / counters (timer 2 with up/down counter feature) USART Six interrupt sources, two priority levels Power saving modes Quick Pulse programming algorithm (C501-1E only) 2-Level program memory lock (C501-1E only) P-DIP-40, P-LCC-44, and P-MQFP-44 package Temperature ranges : SAB-C501 T A : 0 ˚C to 70 SAF-C501 T A : – 40 ˚C to 85 Figure 1 C501G Functional Units MCA03238 Port 0 Port 1 Port 2 Port 3 RAM 256 x 8 CPU USART Ι Power Saving 8K x 8 OTP (C501-1E) Modes 8K x 8 ROM (C501-1R) /OΙ Ι Ι/O

Semiconductor Group 4 1997-04-01 The C501-1R contains a non-volatile 8K 8 read-only program memory, a volatile 256 8 read/ write data memory, four ports, three 16-bit timers counters, a seven source, two priority level interrupt structure and a serial port. The C501-L is identical, except that it lacks the program memory on chip. The C501-1E contains a one-time programmable (OTP) program memory on chip. The term C501 refers to all versions within this specification unless otherwise noted. Further, the term C501 refers to all versions which are available in the different temperature ranges, marked with

Ordering Information

Type Ordering Code Package Description (8-Bit CMOS microcontroller) SAB-C501G-LN SAB-C501G-LP SAB-C501G-LM Q67120-C969 Q67120-C968 Q67127-C970 P-LCC-44 P-DIP-40 P-MQFP-44 for external memory (12 MHz) SAB-C501G-L24N SAB-C501G-L24P SAB-C501G-L24M Q67120-C1001 Q67120-C999 Q67127-C1014 P-LCC-44 P-DIP-40 P-MQFP-44 for external memory (24 MHz) SAB-C501G-L40N SAB-C501G-L40P SAB-C501G-L40M Q67120-C1002 Q67120-C1000 Q67127-C1009 P-LCC-44 P-DIP-40 P-MQFP-44 for external memory (40 MHz) SAF-C501G-L24N SAF-C501G-L24P Q67120-C1011 Q67120-C1010 P-LCC-44 P-MQFP-44 for external memory (24 MHz) ext. temp. – 40 ˚C to 85 ˚C SAB-C501G-1RN SAB-C501G-1RP SAB-C501G-1RM Q67120-DXXX Q67120-DXXX Q67127-DXXX P-LCC-44 P-DIP-40 P-MQFP-44 with mask-programmable ROM (12 MHz) SAB-C501G-1R24N SAB-C501G-1R24P SAB-C501G-1R24M Q67120-DXXX Q67120-DXXX Q67127-DXXX P-LCC-44 P-DIP-40 P-MQFP-44 with mask-programmable ROM (24 MHz) SAB-C501G-1R40N SAB-C501G-1R40P SAB-C501G-1R40M Q67120-DXXX Q67120-DXXX Q67127-DXXX P-LCC-44 P-DIP-40 P-MQFP-44 with mask-programmable ROM (40 MHz) SAF-C501G-1R24N SAF-C501G-1R24P Q67120-DXXX Q67120-DXXX P-LCC-44 P-DIP-40 with mask-programmable ROM (24 MHz) ext. temp. – 40 ˚C to 85 ˚C SAB-C501G-1EN SAB-C501G-1EP Q67120-C1054 Q67120-C1056 P-LCC-44 P-DIP-40 with OTP memory (12 MHz) SAF-C501G-1EN SAF-C501G-1EP Q67120-C2002 Q67120-C2003 P-LCC-44 P-DIP-40 with OTP memory (12 MHz)) ext. temp. – 40 ˚C to 85 SAB-C501G-1E24N SAB-C501G-1E24P Q67120-C2005 Q67120-C2006 P-LCC-44 P-DIP-40 with OTP memory (24 MHz) SAF-C501G-1E24N SAF-C501G-1E24P Q67120-C2008 Q67120-C2009 P-LCC-44 P-DIP-40 with OTP memory (24 MHz)) ext. temp. – 40 ˚C to 85

Semiconductor Group 5 1997-04-01 C501 Note: Versions for extended temperature range – 40 ˚C to 110 ˚C (SAH-C501G) on request. The ordering number of ROM types (DXXX extensions) is defined after program release (verification) of the customer. Additional Literature For further information about the C501 the following literature is available : Figure 2 Pin Configuration P-LCC-44 Package (Top view) Title Ordering Number C501 8-Bit CMOS Microcontroller User’s Manual B158-H6723-X-X-7600 C500 Microcontroller Family Architecture and Instruction Set User’s Manual B158-H6987-X-X-7600 C500 Microcontroller Family - Pocket Guide B158-H6986-X-X-7600 MCP03214 6 5 4 3 2 1 44 43 42 41 40 2827262524232221201918 397 P1.5 P1.6 P1.7 RxD/P3.0 N.C. TxD/P3.1 INT0/P3.2 INT1/P3.3 T0/P3.4 T1/P3.5 WR/P3.6 RD/P3.7 XTAL2 XTAL1 P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.5/A13 P2.6/A14 P2.7/A15 PSEN ALE/PROG EA/ P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 N.C P1.3 P1.4 C501 N.C. VCC VSS RESET P0.7/AD7 P1.2 P1.0/T2 P1.1/T2EX P2.4/A12 N.C. VPP

Semiconductor Group 6 1997-04-01 Figure 3 Pin Configuration P-DIP-40 Package (top view) MCP03215 XTAL1 XTAL2 P2.5/A13 SSV P1.7 P0.7/AD7RESET RxD/P3.0 ALE/PROG PSEN P2.7/A15 P2.6/A14T0/P3.4 T1/P3.5 P2.4/A12WR/P3.6 P2.3/A11 P2.2/A10 P2.1/A9 P2.0/A8 P1.3 P1.2 T2EX/P1.1 VCC P0.4/AD4 P0.3/AD3 P0.1/AD1 C501 RD/P3.7 TxD/P3.1 INT1/P3.3 INT0/P3.2 P1.4 P1.5 P1.6 T2/P1.0 P0.0/AD0 P0.2/AD2 P0.6/AD6 P0.5/AD5 EA/ PPV

Semiconductor Group 8 1997-04-01 Table 1 Pin Definitions and Functions Symbol Pin Number I/O*) Function P-LCC-44 P-DIP-40 P-MQFP-44 P1.0 – P1.7 2–9 1–8 40–44, 1–3, I/O Port 1 is a quasi-bidirectional I/O port with internal pull-up resistors. Port 1 pins that have 1s written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, port 1 pins being externally pulled low will source current ( I IL , in the DC character- istics) because of the internal pull-up resistors. Port 1 also contains the timer 2 pins as secondary function. The output latch corresponding to a secondary function must be pro-grammed to a one (1) for that function to operate. The secondary functions are assigned to the pins of port 1, as follows: P1.0 T2 Input to counter 2 P1.1 T2EX Capture - Reload trigger of timer 2 / Up-Down count *) I = Input O = Output

Semiconductor Group 9 1997-04-01 C501 P3.0 – P3.7 11, 13–19 10–17 5, 7–13 I/O Port 3 is a quasi-bidirectional I/O port with internal pull-up resistors. Port 3 pins that have 1s written to them are pulled high by the internal pull-up resistors, and in that state they can be used as inputs. As inputs, port 3 pins being externally pulled low will source current ( I IL , in the DC characteristics) because of the internal pull-up resistors. Port 3 also contains the interrupt, timer, serial port 0 and external memory strobe pins which are used by various options. The output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate. The secondary functions are assigned to the pins of port 3, as follows: P3.0 R D receiver data input (asyn- chronous) or data input output (synchronous) of serial interface 0 P3.1 T D transmitter data output (asynchronous) or clock output (synchronous) of the serial interface 0 P3.2 INT 0 interrupt 0 input/timer 0 gate control P3.3 INT1 interrupt 1 input/timer 1 gate control P3.4 T0 counter 0 input P3.5 T1 counter 1 input P3.6 WR the write control signal lat- ches the data byte from port 0 into the external data memory P3.7 RD the read control signal enables the external data memory to port 0 *) I = Input O = Output Table 1 Pin Definitions and Functions (cont’d) Symbol Pin Number I/O*) Function P-LCC-44 P-DIP-40 P-MQFP-44

Semiconductor Group 10 1997-04-01 XTAL2 20 18 14 – XTAL2 Output of the inverting oscillator amplifier. XTAL1 21 19 15 – XTAL1 Input to the inverting oscillator amplifier and input to the internal clock generator circuits. To drive the device from an external clock source, XTAL1 should be driven, while XTAL2 is left unconnected. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is divided down by a divide-by-two flip-flop. Minimum and maximum high and low times as well as rise fall times specified in the AC characteristics must be observed. P2.0 – P2.7 24–31 21–28 18–25 I/O Port 2 is a quasi-bidirectional I/O port with internal pull-up resistors. Port 2 pins that have 1s written to them are pulled high by the internal pull-up resistors, and in that state they can be used as inputs. As inputs, port 2 pins being externally pulled low will source current ( I IL , in the DC characteristics) because of the internal pull-up resistors. Port 2 emits the high- order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application it uses strong internal pull-up resistors when issuing 1s. During accesses to external data memory that use 8-bit addresses (MOVX @Ri), port 2 issues the contents of the P2 special function register. *) I = Input O = Output Table 1 Pin Definitions and Functions (cont’d) Symbol Pin Number I/O*) Function P-LCC-44 P-DIP-40 P-MQFP-44

Semiconductor Group 11 1997-04-01 C501 PSEN 32 29 26 O The Program Store Enable output is a control signal that enables the external program memory to the bus during external fetch operations. It is activated every six oscillator periods except during external data memory accesses. Remains high during internal program execution. RESET 10 9 4 I RESET A high level on this pin for two machine cycles while the oscillator is running resets the device. An internal diffused resistor to V SS permits power-on reset using only an external capacitor to V CC ALE/PROG 33 30 27 I/O The Address Latch Enable output is used for latching the low-byte of the address into external memory during normal operation. It is activated every six oscillator periods except during an external data memory access. For the C501-1E this pin is also the program pulse input (PROG ) during OTP memory programming. EA / V PP 35 31 29 I External Access Enable When held at high level, instructions are fetched from the internal ROM (C501-1R and C501-1E) when the PC is less than 2000H . When held at low level, the C501 fetches all instructions from external program memory. For the C501-L this pin must be tied low. This pin also receives the programming supply voltage VPP during OTP memory programming (C501-1E) only). *) I = Input O = Output Table 1 Pin Definitions and Functions (cont’d) Symbol Pin Number I/O*) Function P-LCC-44 P-DIP-40 P-MQFP-44

Semiconductor Group 12 1997-04-01 P0.0 – P0.7 43–36 39–32 37–30 I/O Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written to them float, and in that state can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program or data memory. In this application it uses strong internal pull-up resistors when issuing 1s. Port 0 also outputs the code bytes during program verification in the C501-1R and C501-1E. External pull-up resistors are required during program verification. VSS 22 20 16 – Circuit ground potential VCC 44 40 38 – Supply terminal for all operating modes N.C. 1, 12, 23, 34 – 6, 17, 28, 39 – No connection *) I = Input O = Output Table 1 Pin Definitions and Functions (cont’d) Symbol Pin Number I/O*) Function P-LCC-44 P-DIP-40 P-MQFP-44

Semiconductor Group 14 1997-04-01 CPU The C501 is efficient both as a controller and as an arithmetic processor. It has extensive facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results from an instruction set consisting of 44 % one-byte, 41 % two-byte, and 15% three-byte instructions. With a 12 MHz crystal, 58% of the instructions are executed in 1.0 ms 24 MHz: 500 ns, 40 MHz : 300 ns). Special Function Register PSW (Address D0H ) Reset Value : 00 H Bit Function CY Carry Flag Used by arithmetic instruction. AC Auxiliary Carry Flag Used by instructions which execute BCD operations. F0 General Purpose Flag RS1 RS0 Register Bank select control bits These bits are used to select one of the four register banks. OV Overflow Flag Used by arithmetic instruction. F1 General Purpose Flag P Parity Flag Set/cleared by hardware after each instruction to indicate an odd/even number of "one" bits in the accumulator, i.e. even parity. CY AC F0 RS1 RS0 OV F1 PD0 H PSW D7 H D6 H D5 H D4 H D3 H D2 H D1 H D0 H Bit No. MSB LSB RS1 RS0 Function 0 0 Bank 0 selected, data address 00 H -07H 0 1 Bank 1 selected, data address 08 H -0FH 1 0 Bank 2 selected, data address 10 H -17H 1 1 Bank 3 selected, data address 18 H -1FH

Semiconductor Group 16 1997-04-01 Special Function Registers The registers, except the program counter and the four general purpose register banks, reside in the special function register area. The 27 special function registers (SFRs) include pointers and registers that provide an interface between the CPU and the other on-chip peripherals. All SFRs with addresses where address bits The SFRs of the C501 are listed in table 2 and table 3. In table 2 they are organized in groups which refer to the functional blocks of the C501. Table 3 illustrates the contents of the SFRs in numeric order of their addresses.

Semiconductor Group 17 1997-04-01 C501 Table 2 Special Function Registers - Functional Blocks Block Symbol Name Address Contents after Reset CPU ACC B DPH DPL PSW SP Accumulator B-Register Data Pointer, High Byte Data Pointer, Low Byte Program Status Word Register Stack Pointer E0H F0H 83H 82H D0 H 81H 00H 00H 00H 00H 00H 07H Interrupt System IE IP Interrupt Enable Register Interrupt Priority Register A8 H B8 H 0X000000B XX000000 B Ports P0 Port 0 Port 1 Port 2 Port 3 80H 90H A0 H B0 H FFH FFH FFH FFH Serial Channel PCON 2) SBUF SCON Power Control Register Serial Channel Buffer Register Serial Channel Control Register 87H 99H 98H 0XXX0000 B XX H 00H Timer 0 / Timer 1 TCON TH0 TH1 TL0 TL1 TMOD Timer 0/1 Control Register Timer 0, High Byte Timer 1, High Byte Timer 0, Low Byte Timer 1, Low Byte Timer Mode Register 88H 8C H 8D H 8AH 8BH 89H 00H 00H 00H 00H 00H 00H Timer 2 T2CON T2MOD RC2H RC2L TH2 TL2 Timer 2 Control Register Timer 2 Mode Register Timer 2 Reload/Capture Register, High Byte Timer 2 Reload/Capture Register, Low Byt Timer 2 High Byte Timer 2 Low Byte C8 H C9 H CB H CA H CD H CC H 00H XXXXXXX0 B 00H 00H 00H 00H Pow. Sav. Modes PCON 2) Power Control Register 87 H 0XXX0000 B 1) Bit-addressable special function registers 2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks. 3) “X“ means that the value is undefined and the location is reserved

Semiconductor Group 18 1997-04-01 Table 3 Contents of the SFRs, SFRs in numeric order of their addresses Addr Register Content after Reset Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 80H 87H PCON 0XXX- 0000B SMOD – – – GF1 GF0 PDE IDLE 88H 2) TCON 00H TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 89H TMOD 00 H GATE C/T M1 M0 GATE C/T M1 M0 90H 98H 2) SCON 00H SM0 SM1 SM2 REN TB8 RB8 TI RI A0H A8H 2) IE 0X00- 0000B EA – ET2 ES ET1 EX1 ET0 EX0 B0H 2) P3 FFH RD WR T1 T0 INT1 INT0 TxD RxD B8H 2) IP XX00. 0000B – – PT2 PS PT1 PX1 PT0 PX0 C8 H 2) T2CON 00H TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2 C9 H T2MOD XXXX- XXX0 B D0 H 2) PSW 00H CY AC F0 RS1 RS0 OV F1 P E0H F0H 1) X means that the value is undefined and the location is reserved 2) Bit-addressable special function registers

Semiconductor Group 19 1997-04-01 C501 Timer / Counter 0 and 1 Timer/counter 0 and 1 can be used in four operating modes as listed in table 4. In the “timer” function (C/T = ‘0’) the register is incremented every machine cycle. Therefore the count rate is fOSC /12. In the “counter” function the register is incremented in response to a 1-to-0 transition at its corresponding external input pin (P3.4/T0, P3.5/T1). Since it takes two machine cycles to detect a falling edge the max. count rate is fOSC /24. External inputs INTO and INT1 (P3.2, P3.3) can be programmed to function as a gate to facilitate pulse width measurements. Figure 8 illustrates the input clock logic. Figure 8 Timer/Counter 0 and 1 Input Clock Logic Table 4 Timer/Counter 0 and 1 Operating Modes Mode Description TMOD Input Clock Gate C/T M1 M0 internal external (max) 0 8-bit timer/counter with a divide-by-32 prescaler XX00 fOSC /12 · 32 fOSC /24 · 32 1 16-bit timer/counter X X 1 1 fOSC /12 fOSC /24 2 8-bit timer/counter with 8-bit autoreload XX00 fOSC /12 fOSC /24

3 Timer/counter 0 used as one

8-bit timer/counter and one 8-bit timer Timer 1 stops XX11 fOSC /12 fOSC /24 12 fOSC /12 MCS01768 OSCf C/T TMOD Control Timer 0/1 Input Clock TCON TR 0/1 Gate TMOD P3.4/T0 P3.5/T1 max P3.2/INT0 P3.3/INT1 OSC /24f 1

Semiconductor Group 20 1997-04-01 Timer 2 Timer 2 is a 16-bit timer/counter with an up/down count feature. It can operate either as timer or as an event counter which is selected by bit C/T2 (T2CON.1). It has three operating modes as shown in table 5. Note: fl = falling edge Table 5 Timer/Counter 2 Operating Modes Mode T2CON T2MOD DCEN T2CON EXEN P1.1/ T2EX Remarks Input Clock R ·CLK or T·CLK CP/ RL2 TR2 internal external (P1.0/T2) 16-bit Auto- reload X X X fl reload upon overflow reload trigger (falling edge) Down counting Up counting fOSC /12 max fOSC /24 16-bit Cap- ture X X X fl 16 bit Timer/ Counter (only up-counting) capture TH2, TL2 fi RC2H, RC2L fOSC /12 max fOSC /24 Baud Rate Gene- rator X X X X X fl no overflow interrupt request (TF2) extra external interrupt (“Timer 2”) fOSC /2 max fOSC /24 off X X 0 X X X Timer 2 stops – –

Semiconductor Group 21 1997-04-01 C501 Serial Interface (USART) The serial port is full duplex and can operate in four modes (one synchronous mode, three asynchronous modes) as illustrated in table 6. The possible baudrates can be calculated using the formulas given in table 7. Table 6 USART Operating Modes Mode SCON Baudrate Description SM0 SM1 00 0 fOSC /12 Serial data enters and exits through R·D. T·D outputs the shift clock. 8-bit are transmitted/received (LSB first) 1 0 1 Timer 1/2 overflow rate 8-bit UART 10 bits are transmitted (through T·D) or received (R·D) 21 0 fOSC /32 or fOSC /64 9-bit UART 11 bits are transmitted (T·D) or received (R·D) 3 1 1 Timer 1/2 overflow rate 9-bit UART Like mode 2 except the variable baud rate Table 7 Formulas for Calculating Baudrates Baud Rate derived from Interface Mode Baudrate Oscillator 0 fOSC /12 (2SMOD · fOSC ) / 64 Timer 1 (16-bit timer) (8-bit timer with 8-bit autoreload) 1,3 1,3 (2SMOD · timer 1 overflow rate) /32 (2SMOD · fOSC ) / (32 · 12 · (256-TH1)) Timer 2 1,3 fOSC / (32 · (65536-(RC2H, RC2L))

Semiconductor Group 22 1997-04-01 Interrupt System The C501 provides 6 interrupt sources with two priority levels. Figure 9 gives a general overview of the interrupt sources and illustrates the request and control flags. Figure 9 Interrupt Request Sources Timer 2 Overflow Timer 1 Overflow MCS01783 TF0 ET0 P1.1/ T2EX P3.2/ INT0 EA High Priority Timer 0 Overflow TCON.5 PT0 Low Priority PT1 TCON.7 ET1 TF1 IE.1 IP.1 IP.3 T2CON.3 TF2 EXEN2 T2CON.7 PT2 EXF2 TI PS SCON.0 ES RI IE.5 IP.5 IP.4IE.4 IE0 EX0 TCON.1 PX0 ET2 IE.3 IT0 IT1 PX1 TCON.3 EX1 IE1 IE.0 IP.0 INT1 P3.3/ IE.7 TCON.0 TCON.2 SCON.1 T2CON.6 TCON.0 IE.2 IP.2 USART

Semiconductor Group 23 1997-04-01 C501 A low-priority interrupt can itself be interrupted by a high-priority interrupt, but not by another low- priority interrupt. A high-priority interrupt cannot be interrupted by any other interrupt source. If two requests of different priority level are received simultaneously, the request of higher priority is serviced. If requests of the same priority are received simultaneously, an internal polling sequence determines which request is serviced. Thus within each priority level there is a second priority structure determined by the polling sequence as shown in table 9. Table 8 Interrupt Sources and their Corresponding Interrupt Vectors Source (Request Flags) Vector Vector Address IE0 TF0 IE1 TF1 RI + TI TF2 + EXF2 External interrupt 0 Timer 0 interrupt External interrupt 1 Timer 1 interrupt Serial port interrupt Timer 2 interrupt 0003H 000BH 0013H 001BH 0023H 002BH Table 9 Interrupt Priority-Within-Level Interrupt Source Priority External Interrupt 0, Timer 0 Interrupt, External Interrupt 1, Timer 1 Interrupt, Serial Channel, Timer 2 Interrupt, IE0 TF0 IE1 TF1 RI + TI TF2 + EXF2 High fl Low

Semiconductor Group 24 1997-04-01 Power Saving Modes Two power down modes are available, the Idle Mode and Power Down Mode. The bits PDE and IDLE of the register PCON select the Power Down mode or the Idle mode, respectively. If the Power Down mode and the Idle mode are set at the same time, the Power Down mode takes precedence. Table 10 gives a general overview of the power saving modes. In the Power Down mode of operation, VCC can be reduced to minimize power consumption. It must be ensured, however, that VCC is not reduced before the Power Down mode is invoked, and that VCC is restored to its normal operating level, before the Power Down mode is terminated. The reset signal that terminates the Power Down mode also restarts the oscillator. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize (similar to power-on reset). Table 10 Power Saving Modes Overview Mode Entering Instruction Example Leaving by Remarks Idle mode ORL PCON, #01H – enabled interrupt – Hardware Reset CPU is gated off CPU status registers maintain their data. Peripherals are active Power-Down Mode ORL PCON, #02H Hardware Reset Oscillator is stopped, contents of on-chip RAM and SFR’s are maintained (leaving Power Down Mode means redefinition of SFR contents).

Semiconductor Group 25 1997-04-01 C501 OTP Operation The C501-1E is programmed by usng a modified Quick-Pulse ProgrammingTM 1) algorithm. It differs from older methods in the value used for VPP (programming supply voltage) and in the width and number of the ALE/PROG pulses. The C501-1E contains two signature bytes that can be read and used by a programming system to identify the device. The signature bytes identify the manufacturer of the device. Table 11 shows the logic levels for reading the signature byte, and for programming the program memory, the encryption table, and the security bits. The circuit configuration and waveforms for quick-pulse programming are shown in figures 10 to 12. Notes : 1. “0” = valid low for that pin, “1” = valid high for that pin. 2. VPP = 12.75 V – 0.25V 3. VCC = 5 V – 10% during programming and verification. 4. ALE/PROG receives 25 programming pulses while VPP is held at 12.75 V. Each programming pulse is low for 100 ms (– 10 ms) and high for a minimum of 10 ms. 1) Quick-Pulse ProgrammingTM is a trademark phrase of Intel Corporation Table 11 OTP Programming Modes Mode RESET PSEN ALE/ PROG EA /VPP P2.7 P2.6 P3.7 P3.6 Read signature 1 0 1 1 0000 Program code data 1 0 0 V PP 1011 Verify code data 1 0 1 1 0011 Progam encryption table 1 0 0 V PP 1010 Program security bit 1 1 0 0 V PP 1111 Program security bit 2 1 0 0 V PP 1100

device is executing internal address and program data transfers. figure 10. The code byte to be programmed into that location is applied to port 0. RESET, PSEN PROG signal is pulsed low 25 times as shown in figure 11. programmed, verification cycles will produce only encrypted data. memory and encryption table is disabled. However, the other security bit can still be programmed. PP source should be well regulated and free of glitches and overshoots. are required on port 0 for this operation.

Semiconductor Group 27 1997-04-01 C501 Figure 10 C501-1E OTP Memory Programming Configuration Figure 11 C501-1E ALE/PROG Waveform MCS03232 Port 1 RESET P3.6 P3.7 XTAL2 XTAL1 VSS CCV Port 0 VPPEA/ ALE/PROG PSEN P2.7 P2.6 P2.0 - P2.4 Programming Data +12.75 V 25 x 100 s A8 - A12 A0 - A7 4 - 6 MHz C501-1E +5 V Low Pulses µ MCT03234 ALE/PROG 10 s min.

25 Pulses

µµ µ

Semiconductor Group 28 1997-04-01 Figure 12 C501-1E OTP Memory Verification MCS03235 Port 1 RESET P3.6 P3.7 XTAL2 XTAL1 VSS CCV Port 0 VPPEA/ ALE/PROG PSEN P2.7 P2.6 P2.0 - P2.4 10 kΩ Programming Data Enable A8 - A12 A0 - A7 4 - 6 MHz C501-1E +5 V

Semiconductor Group 29 1997-04-01 C501 Absolute Maximum Ratings Note:Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage of the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for longer periods may affect device reliability. During overload conditions (VIN > VCC or VIN < VSS ) the Voltage on VCC pins with respect to ground (VSS ) must not exceed the values defined by the absolute maximum ratings.

Semiconductor Group 30 1997-04-01 DC Characteristics for C501-L / C501-1R VCC = 5 V + 10 %, – 15 %; VSS = 0 V; TA = 0 ˚C to 70 ˚C for the SAB-C501 TA = – 40 ˚C to 85 ˚C for the SAF-C501 Notes see page 32. Parameter Symbol Limit Values Unit Test Condition min. max. Input low voltage (except EA, RESET) VIL – 0.5 0.2 VCC – 0.1 V – Input low voltage (EA) VIL 1 – 0.5 0.2 VCC – 0.3 V – Input low voltage (RESET)VIL 2 – 0.5 0.2 VCC + 0.1 V – Input high voltage (except XTAL1, EA, RESET) VIH 0.2 VCC + 0.9VCC + 0.5 V – Input high voltage to XTAL1VIH 1 0.7 VCC VCC + 0.5 V Input high voltage to EA, RESET VIH 2 0.6 VCC VCC + 0.5 V – Output low voltage (ports 1, 2, 3) VOL – 0.45 V IOL = 1.6 mA 1) Output low voltage (port 0, ALE, PSEN VOL 1 – 0.45 V IOL = 3.2 mA 1) Output high voltage (ports 1, 2, 3) VOH 2.4 0.9 VCC V IOH = – 80 mA, IOH = – 10 mA Output high voltage (port 0 in external bus mode, ALE, PSEN VOH 1 2.4 0.9 VCC V IOH = – 800 mA 2), IOH = – 80 mA 2) Logic 0 input current (ports 1, 2, 3) IIL – 10 – 50 mA VIN = 0.45 V Logical 1-to-0 transition current (ports 1, 2, 3) ITL – 65 – 650 mA VIN = 2 V Input leakage current (port 0, EA) ILI – – 1 mA 0.45 < VIN < VCC Pin capacitance C IO –1 0 p F fC = 1 MHz, TA = 25 ˚C Power supply current: Active mode, 12 MHz 7) Idle mode, 12 MHz 7) Active mode, 24 MHz 7) Idle mode, 24 MHz 7) Active mode, 40 MHz 7) Idle mode, 40 MHz 7) Power Down Mode ICC ICC ICC ICC ICC ICC IPD 4.8 36.2 8.2 56.5 12.7 mA mA mA mA mA mA mA VCC = 5 V, 4) VCC = 5 V, 5) VCC = 5 V, 4) VCC = 5 V, 5) VCC = 5 V, 4) VCC = 5 V, 5) VCC = 2 … 5.5 V 3)

Semiconductor Group 31 1997-04-01 C501 DC Characteristics for C501-1E VCC = 5 V + 10 %, – 15 %; VSS = 0 V; TA = 0 ˚C to 70 ˚C for the SAB-C501 TA = – 40 ˚C to 85 ˚C for the SAF-C501 Notes see next page. Parameter Symbol Limit Values Unit Test Condition min. max. Input low voltage (except EA /VPP , RESET) VIL – 0.5 0.2 VCC – 0.1 V – Input low voltage (EA/VPP ) VIL 1 – 0.5 0.1 VCC – 0.1 V – Input low voltage (RESET)VIL 2 – 0.5 0.2 VCC + 0.1 V – Input high voltage (except XTAL1, EA/VPP , RESET) VIH 0.2 VCC + 0.9VCC + 0.5 V – Input high voltage to XTAL1VIH 1 0.7 VCC VCC + 0.5 V Input high voltage to EA/VPP , RESET VIH 2 0.6 VCC VCC + 0.5 V – Output low voltage (ports 1, 2, 3) VOL – 0.45 V IOL = 1.6 mA 1) Output low voltage (port 0, ALE/PROG , PSEN) VOL 1 – 0.45 V IOL = 3.2 mA 1) Output high voltage (ports 1, 2, 3) VOH 2.4 0.9 VCC V IOH = – 80 mA, IOH = – 10 mA Output high voltage (port 0 in external bus mode, ALE/PROG , PSEN) VOH 1 2.4 0.9 VCC V IOH = – 800 mA 2), IOH = – 80 mA 2) Logic 0 input current (ports 1, 2, 3) IIL – 10 – 50 mA VIN = 0.45 V Logical 1-to-0 transition current (ports 1, 2, 3) ITL – 65 – 650 mA VIN = 2 V Input leakage current (port 0, EA/VPP ) ILI – – 1 mA 0.45 < VIN < VCC Pin capacitance C IO –1 0 p F fC = 1 MHz, TA = 25 ˚C Power supply current: Active mode, 12 MHz 7) Idle mode, 12 MHz 7) Active mode, 24 MHz 7) Idle mode, 24 MHz 7) Power Down Mode ICC ICC ICC ICC IPD 36.2 mA mA mA mA mA VCC = 5 V, 4) VCC = 5 V, 5) VCC = 5 V, 4) VCC = 5 V, 5) VCC = 2 … 5.5 V 3)

Semiconductor Group 32 1997-04-01 Notes: 1) Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOL of ALE and port 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operation. In the worst case (capacitive loading > 100 pF), the noise pulse on ALE line may exceed 0.8 V. In such cases it may be desirable to qualify ALE with a schmitt-trigger, or use an address latch with a schmitt-trigger strobe input. 2) Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall bellow the 0.9 VCC specification when the address lines are stabilizing. 3) IPD (Power Down Mode) is measured under following conditions: EA = Port0 = VCC ; RESET = VSS ; XTAL2 = N.C.; XTAL1 = VSS ; all other pins are disconnected. 4) ICC (active mode) is measured with: XTAL1 driven with tCLCH , tCHCL = 5 ns, VIL = VSS + 0.5 V, VIH = VCC – 0.5 V; XTAL2 = N.C.; EA = Port0 = RESET= VCC ; all other pins are disconnected. ICC would be slightly higher if a crystal oscillator is used (appr. 1 mA). 5) ICC (Idle mode) is measured with all output pins disconnected and with all peripherals disabled; XTAL1 driven with tCLCH , tCHCL = 5 ns, VIL = VSS + 0.5 V, VIH = VCC – 0.5 V; XTAL2 = N.C.; RESET = EA = VSS ; Port0 = VCC ; all other pins are disconnected; 7) ICC max at other frequencies is given by: active mode: ICC = 1.27 x fOSC + 5.73 idle mode: ICC = 0.28 x fOSC + 1.45 (C501-L and C501-1R only) where fOSC is the oscillator frequency in MHz. ICC values are given in mA and measured at VCC = 5 V.

Semiconductor Group 33 1997-04-01 C501 AC Characteristics for C501-L / C501-1R / C501-1E VCC = 5 V + 10 %, – 15 %; VSS = 0 V TA = 0 ˚C to 70 ˚C for the SAB-C501 TA = – 40 ˚C to 85 ˚C for the SAF-C501 (C L for port 0, ALE and PSEN outputs = 100 pF; C L for all other outputs = 80 pF) Program Memory Characteristics *) Interfacing the C501 to devices with float times up to 75 ns is permissible. This limited bus contention will not cause any damage to port 0 Drivers. Parameter Symbol Limit Values Unit

12 MHz

1/tCLCL = 3.5 MHz to 12 MHz min. max. min. max. ALE pulse width tLHLL 127 – 2 tCLCL – 40 – ns Address setup to ALE tAVLL 43 – tCLCL – 40 – ns Address hold after ALE tLLAX 30 – tCLCL – 53 – ns ALE low to valid instr in tLLIV – 233 – 4 tCLCL – 100 ns ALE to PSEN tLLPL 58 – tCLCL – 25 – ns PSEN pulse width tPLPH 215 – 3 tCLCL – 35 – ns PSEN to valid instr in tPLIV – 150 – 3 tCLCL – 100 ns Input instruction hold after PSENtPXIX 0 – 0–n s Input instruction float after PSEN tPXIZ *) –6 3 – tCLCL – 20 ns Address valid after PSEN tPXAV *) 75 – tCLCL – 8 – ns Address to valid instr in tAVIV – 302 – 5 tCLCL – 115 ns Address float to PSEN tAZPL 0 – 0–n s

Semiconductor Group 34 1997-04-01 AC Characteristics for C501-L / C501-1R / C501-1E (cont’d) External Data Memory Characteristics External Clock Drive Characteristics Parameter Symbol Limit Values Unit 1/tCLCL = 3.5 MHz to 12 MHz min. max. min. max. RD pulse width tRLRH 400 – 6 tCLCL – 100 – ns WR pulse width tWLWH 400 – 6 tCLCL – 100 – ns Address hold after ALE tLLAX2 30 – tCLCL – 53 – ns RD to valid data in tRLDV – 252 – 5 tCLCL – 165 ns Data hold after RD tRHDX 0 – 0–n s Data float after RD tRHDZ –9 7 – 2 tCLCL – 70 ns ALE to valid data in tLLDV – 517 – 8 tCLCL – 150 ns Address to valid data in tAVDV – 585 – 9 tCLCL – 165 ns ALE to WR or RD tLLWL 200 300 3 tCLCL – 50 3 tCLCL + 50 ns Address valid to WR or RD tAVWL 203 – 4 tCLCL – 130 – ns WR or RD high to ALE high tWHLH 43 123 tCLCL – 40 tCLCL + 40 ns Data valid to WR transition tQVWX 33 – tCLCL – 50 – ns Data setup before WR tQVWH 433 – 7 tCLCL – 150 – ns Data hold after WR tWHQX 33 – tCLCL – 50 – ns Address float after RD tRLAZ – 0 –0n s Parameter Symbol Limit Values Unit Variable Clock Freq. = 3.5 MHz to 12 MHz min. max. Oscillator period tCLCL 83.3 285.7 ns High time tCHCX 20 tCLCL – tCLCX ns Low time tCLCX 20 tCLCL – tCHCX ns Rise time tCLCH –2 0 n s Fall time tCHCL –2 0 n s

Semiconductor Group 35 1997-04-01 C501 AC Characteristics for C501-L24 / C501-1R24 / C501-1E24 VCC = 5 V + 10 %, – 15 %; VSS = 0 V TA = 0 ˚C to 70 ˚C for the SAB-C501 TA = – 40 ˚C to 85 ˚C for the SAF-C501 (C L for port 0, ALE and PSEN outputs = 100 pF; C L for all other outputs = 80 pF) Program Memory Characteristics *) Interfacing the C501 to devices with float times up to 37 ns is permissible. This limited bus contention will not cause any damage to port 0 Drivers. Parameter Symbol Limit Values Unit

24 MHz

1/tCLCL = 3.5 MHz to 24 MHz min. max. min. max. ALE pulse width tLHLL 43 – 2 tCLCL – 40 – ns Address setup to ALE tAVLL 17 – tCLCL – 25 – ns Address hold after ALE tLLAX 17 – tCLCL – 25 – ns ALE low to valid instr in tLLIV –8 0 – 4 tCLCL – 87 ns ALE to PSEN tLLPL 22 – tCLCL – 20 – ns PSEN pulse width tPLPH 95 – 3 tCLCL – 30 – ns PSEN to valid instr in tPLIV –6 0 – 3 tCLCL – 65 ns Input instruction hold after PSENtPXIX 0 – 0–n s Input instruction float after PSEN tPXIZ *) –3 2 – tCLCL – 10 ns Address valid after PSEN tPXAV *) 37 – tCLCL – 5 – ns Address to valid instr in tAVIV – 148 – 5 tCLCL – 60 ns Address float to PSEN tAZPL 0 – 0–n s

Semiconductor Group 36 1997-04-01 AC Characteristics for C501-L24 / C501-1R24 / C501-1E24 (cont’d) External Data Memory Characteristics External Clock Drive Characteristics Parameter Symbol Limit Values Unit 1/tCLCL = 3.5 MHz to 24 MHz min. max. min. max. RD pulse width tRLRH 180 – 6 tCLCL – 70 – ns WR pulse width tWLWH 180 – 6 tCLCL – 70 – ns Address hold after ALE tLLAX2 15 – tCLCL – 27 – ns RD to valid data in tRLDV – 118 – 5 tCLCL – 90 ns Data hold after RD tRHDX 0 – 0–n s Data float after RD tRHDZ –6 3 – 2 tCLCL – 20 ns ALE to valid data in tLLDV – 200 – 8 tCLCL – 133 ns Address to valid data in tAVDV – 220 – 9 tCLCL – 155 ns ALE to WR or RD tLLWL 75 175 3 tCLCL – 50 3 tCLCL + 50 ns Address valid to WR or RD tAVWL 67 – 4 tCLCL – 97 – ns WR or RD high to ALE high tWHLH 17 67 tCLCL – 25 tCLCL + 25 ns Data valid to WR transition tQVWX 5– tCLCL – 37 – ns Data setup before WR tQVWH 170 – 7 tCLCL – 122 – ns Data hold after WR tWHQX 15 – tCLCL – 27 – ns Address float after RD tRLAZ – 0 –0n s Parameter Symbol Limit Values Unit Variable Clock Freq. = 3.5 MHz to 24 MHz min. max. Oscillator period tCLCL 41.7 285.7 ns High time tCHCX 12 tCLCL – tCLCX ns Low time tCLCX 12 tCLCL – tCHCX ns Rise time tCLCH –1 2 n s Fall time tCHCL –1 2 n s

Semiconductor Group 37 1997-04-01 C501 AC Characteristics for C501-L40 / C501-1R40 VCC = 5 V + 10 %, – 15 %; VSS = 0 V TA = 0 ˚C to 70 ˚C for the SAB-C501 TA = – 40 ˚C to 85 ˚C for the SAF-C501 (C L for port 0, ALE and PSEN outputs = 100 pF; C L for all other outputs = 80 pF) Program Memory Characteristics *) Interfacing the C501 to devices with float times up to 25ns is permissible. This limited bus contention will not cause any damage to port 0 Drivers. Parameter Symbol Limit Values Unit

40 MHz

1/tCLCL = 3.5 MHz to 40 MHz min. max. min. max. ALE pulse width tLHLL 35 – 2 tCLCL – 15 – ns Address setup to ALE tAVLL 10 – tCLCL – 15 – ns Address hold after ALE tLLAX 10 – tCLCL – 15 – ns ALE low to valid instr in tLLIV –5 5 – 4 tCLCL – 45 ns ALE to PSEN tLLPL 10 – tCLCL – 15 – ns PSEN pulse width tPLPH 60 – 3 tCLCL – 15 – ns PSEN to valid instr in tPLIV –2 5 – 3 tCLCL – 50 ns Input instruction hold after PSENtPXIX 0–0 – n s Input instruction float after PSEN tPXIZ *) –2 0 – tCLCL – 5 ns Address valid after PSEN tPXAV *) 20 – tCLCL – 5 – ns Address to valid instr in tAVIV –6 5 – 5 tCLCL – 60 ns Address float to PSEN tAZPL – 5 – – 5 – ns

Semiconductor Group 38 1997-04-01 AC Characteristics for C501-L40 / C501-1R40 (cont’d) External Data Memory Characteristics External Clock Drive Characteristics Parameter Symbol Limit Values Unit 1/tCLCL = 3.5 MHz to 40 MHz min. max. min. max. RD pulse width tRLRH 120 – 6 tCLCL – 30 – ns WR pulse width tWLWH 120 – 6 tCLCL – 30 – ns Address hold after ALE tLLAX2 10 – tCLCL – 15 – ns RD to valid data in tRLDV –7 5 – 5 tCLCL – 50 ns Data hold after RD tRHDX 0 – 0–n s Data float after RD tRHDZ –3 8 – 2 tCLCL – 12 ns ALE to valid data in tLLDV – 150 – 8 tCLCL – 50 ns Address to valid data in tAVDV – 150 – 9 tCLCL – 75 ns ALE to WR or RD tLLWL 60 90 3 tCLCL – 15 3 tCLCL + 15 ns Address valid to WR or RD tAVWL 70 – 4 tCLCL – 30 – ns WR or RD high to ALE high tWHLH 10 40 tCLCL – 15 tCLCL + 15 ns Data valid to WR transition tQVWX 5– tCLCL – 20 – ns Data setup before WR tQVWH 125 – 7 tCLCL – 50 – ns Data hold after WR tWHQX 5– tCLCL – 20 – ns Address float after RD tRLAZ – 0 –0n s Parameter Symbol Limit Values Unit Variable Clock Freq. = 3.5 MHz to 40 MHz min. max. Oscillator period tCLCL 25 285.7 ns High time tCHCX 10 tCLCL – tCLCX ns Low time tCLCX 10 tCLCL – tCHCX ns Rise time tCLCH –1 0 n s Fall time tCHCL –1 0 n s

Semiconductor Group 39 1997-04-01 C501 Figure 13 Program Memory Read Cycle MCT00096 ALE PSEN Port 2 LHLLt A8 - A15 A8 - A15 A0 - A7 Instr.IN A0 - A7Port 0 tAVLL PLPH t tLLPL tLLIV tPLIV tAZPL tLLAX tPXIZ tPXIX tAVIV tPXAV

Semiconductor Group 40 1997-04-01 Figure 14 Data Memory Read Cycle MCT00097 ALE PSEN Port 2 WHLHt Port 0 RD tLLDV tRLRHtLLWL tRLDV tAVLL tLLAX2 tRLAZ tAVWL tAVDV tRHDX tRHDZ A0 - A7 from Ri or DPL from PCL A0 - A7 Instr. INData IN A8 - A15 from PCHP2.0 - P2.7 or A8 - A15 from DPH

Semiconductor Group 42 1997-04-01 ROM Verification Characteristics for C501-1R ROM Verification Mode 1 Figure 17 ROM Verification Mode 1 Parameter Symbol Limit Values Unit min. max. Address to valid data tAVQV –4 8 tCLCL ns ENABLE to valid data tELQV –4 8 tCLCL ns Data float after ENABLE tEHQZ 04 8 tCLCL ns Oscillator frequency 1/ tCLCL 4 6 MHz MCT00049 tAVQV tEHQZtELQV Address Data OUT P1.0 - P1.7 P2.0 - P2.4 Port 0 P2.7 ENABLE Inputs: P2.5 - P2.6, PSEN = ALE, EA = RESET =P0.0 - P0.7 = D0 - D7Data: P2.0 - P2.4 = A8 - A12 Address: P1.0 - P1.7 = A0 - A7 V IH SSV VSS

Semiconductor Group 43 1997-04-01 C501 OTP Programming and Verification Characteristics VCC = 5 V – 10%, VSS = 0 V, TA = 21 ˚C to + 27 ˚C Parameter Symbol Limit Values Unit min. max. Programming supply voltage V PP 12.5 13.0 V Programming supply current I PP –5 0 m A Oscillator frequency 1 / tCLCL 4 6 MHz Address setup to ALE/PROG low tAVGL 48 tCLCL –n s Address hold after ALE/PROG tGHAX 48 tCLCL –n s Data setup to ALE/PROG low tDVGL 48 tCLCL –n s Data hold after ALE/PROG tGHDX 48 tCLCL –n s P2.7 (ENABLE) high to VPP tEHSH 48 tCLCL –n s VPP setup to ALE/PROG low tSHGL 10 – ms VPP hold after ALE/PROG low tGHSL 10 – ms ALE/PROG width tGLGH 90 110 ms Address to data valid tAVQV – 48 tCLCL ns ENABLE low to data valid tELQV – 48 tCLCL ns Data float after ENABLE tEHQZ 0 48 tCLCL ns ALE/PROG high to ALE/PROG low tGHGL 10 – ms

Semiconductor Group 44 1997-04-01 Figure 18 C501-1E OTP Memory Program/Read Cycle MCT03237 Programming Address Data Data Address tDVGL tAVGL tGLGH tSHGL tEHSH tELQV tEHQZ tGHSL tGHGL tGHAX tGHDX tAVQV Verification Logic 1 Logic 0 P1.0 - P1.7 P2.0 - P2.4 Port 0 ALE/PROG EA/ P2.7 ENABLE PPV

Semiconductor Group 46 1997-04-01 Package Outlines Figure 22 Plastic Package, P-DIP-40 for C501G-L / C501G-1R (Plastic Dual in-Line Package) GPD05883 Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information” Dimensions in mm

Semiconductor Group 47 1997-04-01 C501 Figure 23 GPL05882 Plastic Package, P-LCC-44 – SMD for C501G-L / C501G-1R / C501G-1E (Plastic Leaded Chip-Carrier) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information” Dimensions in mmSMD = Surface Mounted Device

Semiconductor Group 48 1997-04-01 Figure 24 GPM05957 Plastic Package, P-MQFP-44 – SMD for C501G-L / C501G-1R (Plastic Metric Quad Flat Package) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information” Dimensions in mmSMD = Surface Mounted Device