SAFC167

C167 SIEMENS | Alldatasheet

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High-Performance CMOS 16-Bit Microcontrollers Preliminary C167 16-Bit Microcontroller @ High Performance 16-bit CPU with 4-Stage Pipeline @ 100 ns Instruction Cycle Time at 20-MHz CPU Clock © 500 ns Multiplication (16 x 16 bits), 1 us Division (32 / 16 bit) @ Enhanced Boolean Bit Manipulation Facilities @ Additional Instructions to Support HLL and Operating Systems @ Register-Based Design with Multiple Variable Register Banks © Single-Cycle Context Switching Support © Up to 16 MBytes Linear Address Space for Code and Data @ 2 KBytes On-Chip RAM @ 8 KBytes On-Chip ROM @ Programmable External Bus Characteristics for Different Address Ranges @ 8-Bit or 16-Bit External Data Bus @ Multiplexed or Demultiplexed External Address/Data Buses © Five Programmable Chip-Select Signals @ Hold- and Hold-Acknowledge Bus Arbitration Support @ 1024 Bytes On-Chip Special Function Register Area @ Idle and Power Down Modes ‘@ 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via Penpheral Event Controller (PEC) @ 16-Priority-Level Interrupt System with 56 Sources, Sample-Rate down to 50 ns @ 16-Channel 10-bit A/D Converter with 9.7 ys Conversion Time @ Two 16-Channel Capture/Compare Units @ 4-Channel PWM Unit (up to 78 kHz) @ Two Multi-Functional General Purpose Timer Units with 5 Timers @ Two Serial Channels (Synchronous/Asynchronous and High-Speed-Synchronous) @ Programmable Watchdog Timer @ Upto 111 General Purpose /O Lines @ Supported by a Wealth of Development Tools like C-Compilers, Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers, Simulators, Logic Analyzer Disassemblers, Programming Boards © On-Chip Bootstrap Loader @ 144-Pin MOFP Package (EIAJ)

| SIEMENS C167 Introduction The C167 is anew derivative of the Siemens SAB 80C166 family of full featured single-chip CMOS microcontrollers. It combines high CPU performance (up to 10 million instructions per second) with high peripheral functionality and enhanced IO-capabilities. Yoo Mes XTALL Port 0 XTALZ K—> {et RSTIN Port 1 RSTOUT K—> 18st Port 2 yinr <=> ei cao Nui C167 Ko fat | iz | Port 4 | REMY > Pb Port 6 | 5 <—> 8a i Port 5 Port B 18.8 — <—> 8° wouatss | Figure 1 Logic Symbol Ordering Information . Type Ordering Code | Package Function SAB-C167-LM — |Q67120-C836 | P-MQFP-144-1 | 16-bit microcontroller with

2 KByte RAM

Temperature range 0 to +70 °C SAF-C167-LM — |Q67120-C910__| P-MQFP-144-1 | 16-bit microcontroller with Temperature range -40 to +85 °C

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_ SIEMENS c167 Pin Definitions and Functions Symbol | Pin Input (I) | Function _ Number | Output (0) P6.0- |1- vO Port 6 is an 8-bit bidirectional VO port. It is bit-wise P6.7 8 programmable for input or output via direction bits. For a pin ) configured as input, the output driver is put into high- impedance state. Port 6 outputs can be configured as push/ | pull or open drain drivers. | The following Port 6 pins also serve for alternate functions: 1 ce) P6.0 cso Chip Select 0 Output 5 0 P64 CS4__— Chip Select 4 Output 6 | | P65 HOLD External Master Hold Request Input 7 ° | P66 HULDA —_Hold Acknowledge Output 8 ° P67 BREQ _ Bus Request Output Pao- |9- vo Port 8 is an 8-bit bidirectional VO port. It is bit-wise P87 16 programmable for input or output via direction bits. For a pin | configured as input, the output driver is put into high- impedance state. Port 8 outputs can be configured as push/ | pull or open drain drivers. | The following Port 8 pins also serve for alternate functions: 9 | vo P8.0 CC16IO ~~ CAPCOM2: CC16 Cap.-In/Comp.Out 16 vo P87 C2310 CAPCOM2: CC23 Cap.-In’Comp.Out P7.0- |19- vo |Port 7 is an 8-bit bidirectional /O port. It is bit-wise P77 26 programmable for input or output via direction bits. For a pin | | configured as input, the output driver is put into high- impedance state. Port 7 outputs can be configured as push/ pull or open drain drivers. The following Port 7 pins also serve for alternate functions: | 19 ° P7.0 POUTO PWM Channel 0 Output 2 ©=«|0 P73 POUT3 PWM Channel 3 Output 23 vo P7.4 C2810 CAPCOM2: CC28 Cap.-In/Comp.Out 2 v0 P77 GC3110_ GAPCOM2: 6631 Cap.-In/Comp.Out

Pin Definitions and Functions (cont'd) Symbol | Pin Input (1) | Function Number | Output (0) P5.0- |27-36 Port 5 is a 16-bit input-only port with Schmitt-Tngger PS5.15 39-44 characteristics. The pins of Port 5 also serve as the (up to 16) analog input channels for the A/D converter, where P5.x equals ANx (Analog input channel x), or they serve as timer inputs: 39 P5.10 T6EUD GPT2 Timer T6 Ext.Up/Down Ctrl.Input 40 P5.11 TS5EUD GPT2 Timer TS Ext.Up/Down Ctrl.input at P5.12 T6IN GPT2 Timer T6 Count Input 42 P5.13 TSIN GPT2 Timer TS Count Input 43 P5.14 T4EUD = GPT1 Timer T4 Ext.Up/Down Ctrl.Input 44 P5.15. T2EUD = GPT1 Timer T2 Ext.Up/Down Ctrl.input P2.0- 47-54 | 0 Port 2 is a 16-bit bidirectional /O port. It is bit-wise P2.15 | 57-64 programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high- impedance state. Port 2 outputs can be configured as push/ pull or open drain drivers. The following Port 2 pins also serve for alternate functions: 47 fe} P2.0 CCOlIO = CAPCOM: CCO Cap.-In/Comp.Out 540 P27 CC7IO. CAPCOM: CC7 Cap.-In/Comp Out 57 vo P28 CC8iIO CAPCOM: CC8 Cap.-In/Comp.Out, | EXOIN Fast External Interrupt 0 Input 6 |vo P2.18 CC1SIO CAPCOM: CC15 Cap.-In/Comp.Out,

1 EX7IN Fast External Interrupt 7 Input

1 T7IN CAPCON2 Timer T7 Count Input

Pin Definitions and Functions (cont'd) Symbol | Pin Input (1) Function Number Output (0) P3.0- |65~-70, |VO Port 3 is a 15-bit (P3.14 is missing) bidirectional /O port. It is P3.13, | 73-80, | VO bit-wise programmable for input or output via direction bits. P315 81 ae) For a pin configured as input, the output driver is put into high- impedance state. Port 3 outputs can be configured as push/ | | pull or open drain drivers. The following Port 3 pins also serve for alternate functions: 65 | | P3.0 TOIN CAPCOM Timer TO Count Input 66 fe) |P3.1 T6OUT GPT2 Timer T6 Toggle Latch Output 67 j P32 CAPIN — GPT2 Register CAPREL Capture Input 68 ° P33 T3OUT GPT! Timer T3 Toggle Latch Output 69 1 P34 T3EUD GPT! Timer T3 Ext.Up/Down Ctrl.Input 70 1 P35 ‘TAIN GPT1 Timer T4 Input for / } Count/Gate/Reload/Capture 73 ! P3.6 T3IN GPT1 Timer T3 Count/Gate Input 74 | P37 T2iN GPT1 Timer T2 input for | Count/Gate/Reload/Capture 75 vo P38 MRST SSC Master-Rec./Slave-Transmit /O 76 vo P3.9 MTSR SSC Master-Transmit/Slave-Rec. O/| 7 ° P3.10 TxDO ASCO Clock/Data Output (Asyn./Syn.) !78 vo P3.11 RxDO —_ ASCO Data Input (Asyn.) or VO (Syn.) 79 fo) |P312 BHE Ext. Memory High Byte Enable Signal, ° | WRH Ext. Memory High Byte Write Strobe |80 vo P3.13_ SCLK SSC Master Clock Outp/Slave Cl. Inp. 81 fe) P3.15, CLKOUT System Clock Output (=CPU Clock) P4.0- (85-92 |V/0 Port 4 is an 8-bit bidirectional VO port. It is bit-wise P47 | | programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high- | impedance state. } In case of an external bus configuration, Port 4 can be used to ‘output the segment address lines: 85 Ke) P4.0 AIG Least Significant Segment Addr. Line 92 ° P47 A23 Most Significant Segment Addr. Line RD /95 ° External Memory Read Strobe. RD is activated for every external instruction or data read access. WR 96 ° | External Memory Write Strobe. In WA-mode this pin is WRE activated for every external data write access. in WRL-mode | this pin is activated for low byte data write accesses on a 16- bit bus, and for every data write access on an 8-bit bus. See | WRCFG in register SYSCON for mode selection. Semiconductor Group 674 MB 8235605 0061584 ebe

Pin Definitions and Functions (cont'd) Symbol | Pin Input (I) Function Number | Output (0) READY | 97 ! Ready Input. When the Ready function is enabled, a high level at this pin during an external memory access will force the insertion of memory cycle time waitstates until the pin returns to a low level. ALE Address Latch Enable Output. Can be used for latching the address into external memory or an address latch in the multiplexed bus modes. EA 99 I External Access Enable pin. A low level at this pin during and after Reset forces the C167 to begin instruction execution out of external memory. A high level forces execution out of the internal ROM. ROMless versions must have this pin tied to ‘0’. PORTO: vo PORTO consists of the two 8-bit bidirectional /O ports POL POL.O- |100- and POH. It is bit-wise programmable for input or output via POL.7, 107 direction bits. For a pin configured as input, the output driver POH.O- | 108, is put into high-impedance state. POH.7 114-117 In case of an external bus configuration, PORTO serves as the address (A) and address/data (AD) bus in multiplexed bus modes and as the data (D) bus in demultiplexed bus modes. Demultiplexed bus modes: Data Path Width: 8-bit 16-bit POL.O - POL.7: DO-D7 DO- 07 POH.0 — POH.7: vO D8- DIS Multiplexed bus modes: Data Path Width: 8-bit 16-bit POL.O -POL.7: ADO - AD7 ADO - AD7 POH. - POH.7: AB - A15 AD8 - AD15 PORT1: PORT1 consists of the two 8-bit bidirectional /O ports PiL PILO- |118- and P1H, It is bit-wise programmable for input or output via PIL7, 125 direction bits. For a pin configured as input, the output driver PIH.O- |128- is put into high-impedance state. PORT is used as the 16-bit PIH7 = | 135 address bus (A) in demultiplexed bus modes and also after switching from a demultiplexed bus mode to a multiplexed bus mode. The following PORT! pins also serve for alternate functions: 132 PIH.4 C2410 CAPCOM2: CC24 Capture Input 133 PIH.S CC251I0 CAPCOM2: CC25 Capture Input 134 PIH.6 CC26I0 CAPCOM2: CC26 Capture Input

135 PIH7 CC27I0 ~CAPCOM2: CC27 Capture Input

M@@® 4235605 0061585 177

Pin Definitions and Functions (cont'd)

1 Symbol | Pin Input (I) [Function

Number | Output (0) | . XTAL1 | 138 | XTAL1: — Input to the oscillator amplifier and input to the | | internal clock generator XTAL2 | 137 fe} XTAL2: — Output of the oscillator amplifier circuit. | To clock the device from an external source, drive XTAL1, while leaving XTAL2 unconnected. Minimum and maximum high/ow and rise/fall times specified in the AC Characteristics must be observed. RSTIN Reset Input with Schmitt-Trigger characteristics. A low level at this pin for a specified duration while the oscillator is running resets the C167. An internal pullup resistor permits power-on reset using only a capacitor connected to Ves. RSTOUT } 141 ° Internal Reset Indication Output. This pin is set to a low level when the part is executing either a hardware-, a software- or a [rang timer reset. RSTOUT remains low until the EINIT | (end of initialization) instruction is executed. NMI 142 I _ Non-Maskable Interrupt Input. A high to low transition at this | pin causes the CPU to vector to the NMI trap routine. When | the PWRDN (power down) instruction is executed, the NMI pin must be low in order to force the C167 to go into power down mode. If NMI is high, when PWRDN is executed, the | part will continue to run in normal mode. If not used, pin NMI should be pulled high externally. Vrpee : Reference voltage for the A/D converter. Vacwo 138 iB Reference ground for the A/D converter. Vor 84 j- Flash programming voltage. This pin accepts the ! | Programming voltage for flash versions of the C167. | Note: This pin is not connected (NC) on non-flash versions. Veo | 17,46, j- Digital Supply Voltage: | 56, 72, +5 V during normal operation and idle mode. | 82, 93, > 2.5 V during power down mode | 109, 126, 136, 144 Vg 18,45, |- Digital Ground. 55, 71, 83, 94, 110, | | 127, | 139, 143 Semiconductor Group 676 @™@ 46235605 00b1586 035

The architecture of the C167 combines advantages of both RISC and CISC processors and of advanced peripheral subsystems in a very well-balanced way. The following block diagram gives an overview of the different on-chip components and of the advanced, high bandwidth internal bus structure of the C167. Note: All time specifications refer to a CPU clock of 20 MHz (see definition in the AC Characteristics section). | eaaiaieneneneneteneneieieneheianenaheiannnnnnnnnnnnnnannnnennnnanaen | 1 #8 I a, i ' 2, 1 6 1 t aa a, t i —_ 1 6 _ PEC 1 i — Interrupt Controller * \\ bt 5 l Trey 1 1 L 6 yo-att|{ cer: || asc || sec [CAPCOM] [CAPCOM 1

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The memory space of the C167 is configured in a Von Neumann architecture which means that code memory, data memory, registers and I/O ports are organized within the same linear address space which includes 16 MBytes. The entire memory space can be accessed bytewise or wordwise. Particular portions of the on-chip memory have additionally been made directly bit addressable. The C167 contains 8 KBytes of on-chip mask-programmable ROM for code or constant data. The ROM can be mapped to either segment 0 or segment 1.

2 KBytes of on-chip RAM are provided as a storage for user defined variables, for the system stack,

general purpose register banks and even for code. A register bank can consist of up to 16 wordwide (RO to R15) and/or bytewide (RLO, RHO, ..., RL7, RH7) so-called General Purpose Registers (GPRs). 1024 bytes (2 * 512 bytes) of the address space are reserved for the Special Function Register areas (SFR space and ESFR space). SFRs are wordwide registers which are used for controlling and monitoring functions of the different on-chip units. 212 SFRs are currently implemented. Unused SFR addresses are reserved for future members of the C167 family. In order to meet the needs of designs where more memory is required than is provided on chip, up to 16 MBytes of external RAM and/or ROM can be connected to the microcontroller. External Bus Controller All of the external memory accesses are performed by a particular on-chip External Bus Controller (EBC). It can be programmed either to Single Chip Mode when no external memory is required, or to one of four different external memory access modes, which are as follows: — 16-/18-/20-/24-bit Addresses, 16-bit Data, Demultiplexed — 16-/18-/20-/24-bit Addresses, 16-bit Data, Multiplexed ~ 16-/18-/20-/24-bit Addresses, 8-bit Data, Multiplexed — 16-/18-/20-/24-bit Addresses, 8-bit Data, Demultiplexed In the demultiplexed bus modes, addresses are output on PORT1 and data is input/output on PORTO. In the multiplexed bus modes both addresses and data use PORTO for input/output. important timing characteristics of the external bus interface (Memory Cycle Time, Memory Tri- State Time, Length of ALE and Read Write Delay) have been made programmable to allow the user the adaption of a wide range of different types of memories. In addition, different address ranges may be accessed with different bus characteristics. Up to 5 external CS signals can be generated in order to save external glue logic. Access to very slow memories is supported via a particular ‘Ready’ function, A HOLD/HLDA protocol is available for bus arbitration. For applications which require less than 16 MBytes of external memory space, this address space can be restricted to 1 MByte, 256 KByte or to 64 KByte. In this case Port 4 outputs four, two or no address lines at all. It outputs all 8 address lines, if an address space of 16 MBytes is used. Semiconductor Group 678 WM 4235605 0061584 908

Central Processing Unit (CPU) The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit (ALU) and dedicated SFRs. Additional hardware has been spent for a separate multiply and divide unit, a bit-mask generator and a barrel shifter. Based on these hardware provisions, most of the C167’s instructions can be executed in just one machine cycle which requires 100 ns at 20-MHz CPU clock. For example, shift and rotate instructions are always processed during one machine cycle independent of the number of bits to be shifted. All multiple-cycle instructions have been optimized so that they can be executed very fast as well: branches in 2 cycles, a 16 x 16 bit multiplication in § cycles and a 32-/16 bit division in 10 cycles. Another pipeline optimization, the so-called ‘Jump Cache’, allows reducing the execution time of repeatedly performed jumps in a loop from 2 cycles to 1 cycle. 16 2 K 7) KBytes a RAM IBit—Mask Gen] General \\N on ee hy | \\\\ 8 2 _ I. Purpose Stage = KBytes KZ Pipetine it - i} | Registers ro , Ay By |FA [syscon 7] [BUSCON 0] BUSCOW | 38 BuScON 2 T-ADDRSEL]——SCSsCSSiK | BUSCON 3 wosozi 36 Figure 4 CPU Block Diagram Semiconductor Group 679 M@™® 4235605 0061589 644 me

| SIEMENS 167 The CPU disposes of an actual register context consisting of up to 16 wordwide GPRs which are physically allocated within the on-chip RAM area. A Context Pointer (CP) register determines the base address of the active register bank to be accessed by the CPU at a time. The number of register banks is only restricted by the available internal RAM space. For easy parameter passing, a register bank may overlap others. Assystem stack of up to 2048 bytes is provided as a storage for temporary data. The system stack is allocated in the on-chip RAM area, and it is accessed by the CPU via the stack pointer (SP) register. Two separate SFRs, STKOV and STKUN, are implicitly compared against the stack pointer value upon each stack access for the detection of a stack overflow or underflow. The high performance offered by the hardware implementation of the CPU can efficiently be utilized by a programmer via the highly efficient C167 instruction set which includes the following instruction classes: — Arithmetic Instructions — Logical Instructions — Boolean Bit Manipulation Instructions — Compare and Loop Control instructions ~ Shift and Rotate Instructions — Prioritize Instruction — Data Movement Instructions - System Stack Instructions — Jump and Call Instructions — Return instructions — System Control Instructions — Miscellaneous Instructions The basic instruction length is either 2 or 4 bytes. Possible operand types are bits, bytes and words. A variety of direct, indirect or immediate addressing modes are provided to specify the required operands. ‘Semiconductor Group 680 M@ 8235605 0061590 Sbb mm

With an interrupt response time within a range from just 250 ns to 600 ns (in case of internal program execution), the C167 is capable of reacting very fast to the occurrence of non-deterministic events. The architecture of the C167 supports several mechanisms for fast and flexible response to service requests that can be generated from various sources internal or external to the microcontroller. Any of these interrupt requests can be programmed to being serviced by the Interrupt Controller or by the Peripheral Event Controller (PEC). In contrast to a standard interrupt service where the current program execution is suspended and a branch to the interrupt vector table is performed, just one cycle is ‘stolen’ from the current CPU activity to perform a PEC service. A PEC service implies a single byte or word data transfer between any two memory locations with an additional increment of either the PEC source or the destination pointer. An individual PEC transfer counter is implicity decremented for each PEC service except when performing in the continuous transfer mode. When this counter reaches zero, a standard interrupt is performed to the corresponding source related vector location. PEC services are very well suited, for example, for supporting the transmission or reception of blocks of data, or for transferring A/D converted results to a memory table. The C167 has 8 PEC channels each of which offers such fast interrupt-driven data transfer capabilities. A separate control register which contains an interrupt request flag, an interrupt enable flag and an interrupt priority bitfield exists for each of the possible interrupt sources. Via its related register, each source can be programmed to one of sixteen interrupt priority levels. Once having been accepted —— by the CPU, an interrupt service can only be interrupted by a higher prioritized service request. For the standard interrupt processing, each of the possible interrupt sources has a dedicated vector location. Fast external interrupt inputs are provided to service external interrupts with high precision requirements. These fast interrupt inputs feature programmable edge detection (rising edge, falling edge or both edges). Software interrupts are supported by means of the ‘TRAP’ instruction in combination with an individual trap (interrupt) number. The following table shows all of the possible C167 interrupt sources and the corresponding hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers: Note: The four last nodes in the table (X-Peripheral nodes) are prepared to accept interrupt requests from integrated X-Bus peripherals. Nodes, where no X-Peripherals are connected, may be used to generate software controlled interrupt requests by setting the respective XPniR bit. Semiconductor Group 681 M@™ 8235605 0061591 4To a

PEC Service Request | Flag Flag Vector Location | Number CAPCOM RegisterO | CCOIR 104 CAPCOM Register 1 CIR CCIE My CAPCOM Register 2 | CC2IR Cale | CC2INT yo CAPCOM Register4 | CC4IR__—_—[ CC4IE CCAINT 14 CAPCOM Register 6 CAPCOM Regier _[CoaIR_|CC8IE _|cCaNT | ov0060, | 184 CAPCOM Register 184 CAPCOM Register 10 | CC10IR CCIOINT [0000684 | 1Ay CAPCOM Register 11 | CC11IR CCHINT [O0;006Cy [1By CAPCOMRegister12 |CC12IR |CCI2IE _|CC12INT 000070, | 1Cy CAPCOM Register13CC13IR_—|CCI3IE | CCISINT [0000744 | 104 CAPCOM Register 14 CC14IR__|CCI4IE | CC14INT _|00°0078, | 1Ey CAPCOM Register 17 on CAPCOM Reger1@[GoraiR_|ocrae —_|ccxainT —[oo00Cey 324 CAPCOM Register 19 O0'00CC, |33y ; CAPCOM Register 20 | CC20IR By CAPCOM Register 21 | CC21IR Sy CAPCOM Register 22 lec2atR” ~ecaaie ‘| CC22INT 364 CAPCOM Register 23. | CC23IR 374 CAPCOM Register 24 cc24iR CC24IE CC24INT | 00'00E0,, 38, CAPCOM Register 25 CC2sIR | CC25IE CC2SINT 00'00E4,, 39, CAPCOM Reger 2 em CAPCOM Register 27 CC27INT |00';00EC, | 3By CAPCOM Register 28 |CC28IR_ ‘| CC28IE OO'00EO, | 3Cy CAPCOM Register 29 |CC29IR_|CC29IE_ 000110, | 44, CAPCOM Register30 |CC30IR_—_|CC30IE_|CC30INT 000114, | 454 CAPCOMRegister31 |CC31IR |CC31IE |CC31INT |00°0118, | 46, CAPCOM Timer 0 00'0080, | 204 Semiconductor Group 682 M@ 6235605 0061592 3395

PEC Service Request Flag Vector Number CAPCOM Timer 1 THINT 00'0084, | 214 CAPCOM Timer 7 THE O000F4, | 3Dy CAPCOM Timer 8 0008, (SE, GPT Tner2 224 GPT Tiner3 24 Pre Timer 5 2y GPT2 Timer 6 TélR 264 GPT2 CAPREL Register 00'008C, [271 AD Conversion Compiete | ADCIR 00'00A0,, | 284 AUD Overrun Error ” icon [ance _ oe 00'00A4, 29, ASCO Transmit Buffer _|SOTBIR _|SOTBIE | SOTBINT [00011Cy [474 A300 Ero soem _|socie_|soewT —_[ovane0y [20 SSC Transmit ~_ [soir 24 SSC Receive SCRIR 2 ssCérer =i SER ye X-Peripheral Node 3 XP3IR By Semiconductor Group 683 @™® 6235605 0061593 275 a

The C167 also provides an excellent mechanism to identify and to process exceptions or error conditions that arise during run-time, so-called ‘Hardware Traps’. Hardware traps cause immediate non-maskable system reaction which is similar to a standard interrupt service (branching to a dedicated vector table location). The occurrence of a hardware trap is additionally signified by an individual bit in the trap flag register (TFR). Except when another higher prioritized trap service is in Progress, a hardware trap will interrupt any actual program execution. In turn, hardware trap services can normally not be interrupted by standard or PEC interrupts. The following table shows all of the possible exceptions or error conditions that can arise during run- time: Exception Condition Trap Trap Vector Trap - Trap Flag Vector Location Number Priority Reset Functions: | Hardware Reset RESET | 00'0000, | 004 mM Software Reset RESET | 00'0000, | 00, MW Watchdog Timer Overflow RESET |00'00004 | 004 a Class A Hardware Traps: | Non-Maskable Interrupt NMI NMITRAP | 00'0008,, 024 i] Stack Overflow STKOF STOTRAP | 00'0010,, 04, I Stack Underflow STKUF STUTRAP | 00°0018,, 064 IL Class B Hardware Traps: Undefined Opcode UNDOPC }BTRAP | 00'0028, | 0Ay 1 Protected Instruction PRTFLT | BTRAP 00'0028,, | OA, ! Fault Illegal Word Operand ILLOPA |BTRAP |00'00284 | OAy 1 Access | Illegal Instruction Access. |ILLINA | BTRAP |00'00284 | OAy i Illegal External Bus ILLBUS | BTRAP 00'0028,, OAy | Access _ a Reserved [2Cyy- 3Cy) | (0B, - OF] Software Traps Any Any Current TRAP Instruction [00'0000,,- | [00,,-7F,) | CPU 00°01 FC) Priority in steps of 44 ‘Semiconductor Group 684 M@® 46235605 0061594 101

Capture/Compare (CAPCOM) Units The CAPCOM units support generation and control of timing sequences on up to 32 channels with a maximum resolution of 400 ns (at 20-MHz system clock). The CAPCOM units are typically used to handle high speed I/O tasks such as pulse and waveform generation, pulse width modulation (PMW), Digital to Analog (D/A) conversion, software timing, or time recording relative to external events. Four 16-bit timers (TO/T1, T7/T8) with reload registers provide two independent time bases for the capture/compare register array. The input clock for the timers is programmable to several prescaled values of the internal system clock, or may be derived from an overflow/underflow of timer T6 in module GPT2. This provides a wide range of variation for the timer period and resolution and allows precise adjustments to the application specific requirements. In addition, external count inputs for CAPCOM timers TO and 77 allow event scheduling for the capture/compare registers relative to external events. Both of the two capture/compare register arrays contain 16 dual purpose capture/compare registers, each of which may be individually allocated to either CAPCOM timer TO or T1 (T7 or T8, respectively), and programmed for capture or compare function. Each register has one port pin associated with it which serves as an input pin for triggering the capture function, or as an output pin - (except for CC24...CC27) to indicate the occurrence of a compare event. When a capture/compare register has been selected for capture mode, the current contents of the allocated timer will be latched (‘capture'd) into the capture/compare register in response to an external event at the port pin which is associated with this register. in addition, a specific interrupt request for this capture/compare register is generated. Either a positive, a negative, or both a positive and a negative external signal transition at the pin can be selected as the triggering event. The contents of all registers which have been selected for one of the five compare modes are continuously compared with the contents of the allocated timers. When a match occurs between the timer value and the value in a capture/compare register, specific actions will be taken based on the selected compare mode. Compare Modes Function _ Z Mode 0 Interrupt-only compare mode; several compare interrupts per timer period are possible Mode 1 Pin toggles on each compare match; ‘several compare events per timer period are possible Mode 2 Interrupt-only compare mode; | only one compare interrupt per timer period is generated Mode 3 | Pin set ‘1’ on match; pin reset ‘0’ on compare time overflow; { only one compare event per timer period is generated Double | Two registers operate on one pin; pin toggles on each compare match; Register Mode several compare events per timer period are possible. Semiconductor Group 685 M@! =8235605 0061595 048 a

| SIEMENS ors Reload Reg. TxREL CPU Clock ut Interrupt Tx Request mn [J Input CAPCOM Timer Tx

5 Control

: Mode ===" Steen === :

16 Control Soo: 16-Bit -2o> 16

Capture Inputs (Capture =--- Capture/ ----} Copture/Compare Compare Outputs » or IZ! Compare °~""] Interrupt Requests a. ) Compare) IICl Registers 2222 ; CPU Clock—[2" n=3...10} if Interrupt ly Request emt CAPCOM Timer Ty GPT2 Timer T6 ontrol Over/Underflow a I a Reload Reg. TyREL ceontas *) 12 outputs on CAPCOM2 Figure 5 . CAPCOM Unit Block Diagram Semiconductor Group 686 M™@ 4235605 0061596 Tay mw

The Pulse Width Modulation Module can generate up to four PWM output signals using edge- aligned or center-aligned PWM. In addition the PWM module can generate PWM burst signals and single shot outputs. The frequency range of the PWM signals covers 4.8 Hz to 78.1 kHz (referred toa CPU clock of 20 MHz). The level of the output signals is selectable and the PWM module can generate interrupt requests. General Purpose Timer (GPT) Unit The GPT unit represents a very flexible multifunctional timer/counter structure which may be used for many different time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or pulse multiplication. The GPT unit incorporates five 16-bit timers which are organized in two separate modules, GPT1 and GPT2. Each timer in each module may operate independently in a number of different modes, or may be concatenated with another timer of the same module. Each of the three timers T2, T3, T4 of module GPT1 can be configured individually for one of three basic modes of operation, which are Timer, Gated Timer, and Counter Mode. In Timer Mode, the input clock for a timer is derived from the GPU clock, divided by a programmable prescaler, while Counter Mode allows a timer to be clocked in reference to external events. Pulse width or duty cycle measurement is supported in Gated Timer Mode, where the operation of a timer is controlled by the ‘gate’ level on an external input pin. For these purposes, each timer has ‘one associated port pin (TxIN) which serves as gate or clock input. The maximum resolution of the timers in module GPT1 is 400 ns (@ 20-MHz CPU clock). The count direction (up/down) for each timer is programmable by software or may additionally be altered dynamically by an external signal on a port pin (TxEUD) to facilitate e. g. position tracking. Timers T3 and T4 have output toggle latches (TxOTL) which change their state on each timer over- tlow/underflow. The state of these latches may be output on port pins (TxOUT) e. g. for time out monitoring of external hardware components, or may be used internally to clock timers T2 and T4 for measuring long time periods with high resolution. In addition to their basic operating modes, timers T2 and T4 may be configured as reload or capture registers for timer T3. When used as capture or reload registers, timers T2 and T4 are stopped. The contents of timer T3 is captured into T2 or T4 in response to a signal at their associated input pins (TxIN). Timer T3 is reloaded with the contents of T2 or T4 triggered either by an external signal or by a selectable state transition of its toggle latch T3OTL. When both T2 and T4 are configured to alternately reload T3 on opposite state transitions of TSOTL with the low and high times of a PWM. signal, this signal can be constantly generated without software intervention. With its maximum resolution of 200 ns (@ 20 MHz), the GPT2 module provides precise event control and time measurement. it includes two timers (TS, T6) and a capture/reload register (CAPREL). Both timers can be clocked with an input clock which is derived from the CPU clock via a programmable prescaler or with external signals. The count direction (up/down) for each timer is programmable by software or may additionally be altered dynamically by an external signal on a port pin (TxEUD). Concatenation of the timers is supported via the output toggle latch (T6EOTL) of timer T6, which changes its state on each timer overflow/underflow. Semiconductor Group 687 MH 4235605 0061597 410

The state of this latch may be used to clock timer T5, or it may be output on a port pin (T6OUT). The overflows/underflows of timer T6 can additionally be used to clock the CAPCOM timers TO or T1, and to cause a reload from the CAPREL register. The CAPREL register may capture the contents of timer T5 based on an external signal transition on the corresponding port pin (CAPIN), and timer T5 may optionally be cleared after the capture procedure. This allows absolute time differences to be measured or pulse multiplication to be performed without software overhead. rzevo [_ J u/o - interrupt CPU Clock ® bow © tan [}——+]_ Mode | Reload Conirol [cose | VAI 13IN Controt C}— u/o tseuo (J r Interrupt Sopture > Request ; u tain [} Mode PU Clock Control + oP0 Cle Interrupt Figure 6 Block Diagram of GPT1 Semiconductor Group 688 MB 8235605 0061598 85?

Mod PT2 Timer T: tsi [ F tose GPT2 Timer TS Request cot [7 | can CJ 4S erat Reload Interrupt Request CPU Clock Control - u/o to CAPCOM ree (J > Timers wctoaa2 Figure 7 Block Diagram of GPT2 Semiconductor Group 689 @™® =$235605 0061599 793 a

i I | SIEMENS 167 AID Converter For analog signal measurement, a 10-bit A/D converter with 16 multiplexed input channels and a sample and hold circuit has been integrated on-chip. It uses the method of successive approximation. The sample time (for loading the capacitors) and the conversion time is programmable and can so be adjusted to the external circuitry. Overrun error detection/protection is provided for the conversion result register (ADDAT): either an interrupt request will be generated when the result of a previous conversion has not been read from the result register at the time the next conversion is complete, or the next conversion is suspended in such a case until the previous result has been read. For applications which require less than 16 analog input channels, the remaining channel inputs can be used as digital input port pins. The A/D converter of the C167 supports four different conversion modes. In the standard Single Channel conversion mode, the analog level on a specified channel is sampled once and converted to a digital result. In the Single Channel Continuous mode, the analog level on a specified channel is repeatedly sampled and converted without software intervention. In the Auto Scan mode, the analog levels on a prespecified number of channels are sequentially sampled and converted. In the Auto Scan Continuous mode, the number of prespecified channels is repeatedly sampled and converted. In addition, the conversion of a specific channel can be inserted (injected) into a running sequence without disturbing this sequence. This is called Channel Injection Mode. The Peripheral Event Controller (PEC) may be used to automatically store the conversion results into a table in memory for later evaluation, without requiring the overhead of entering and exiting interrupt routines for each data transfer. Parallel Ports The C167 provides up to 111 V/O lines which are organized into eight input/output ports and one input port. All port lines are bit-addressable, and all input/output lines are individually (bit-wise) programmable as inputs or outputs via direction registers. The I/O ports are true bidirectional ports which are switched to high impedance state when configured as inputs. The output drivers of five VO ports can be configured (pin by pin) for push/pull operation or open-drain operation via control registers. During the internal reset, all port pins are configured as inputs. Allport lines have programmable alternate input or output functions associated with them. PORTO and PORT1 may be used as address and data lines when accessing external memory, while Port 4 outputs the additional segment address bits A23/19/17...A16 in systems where segmentation is enabled to access more than 64 KBytes of memory. Port 2, Port 8 and Port 7 are associated with the capture inputs or compare outputs of the CAPCOM units and/or with the outputs of the PWM module. Port 6 provides optional bus arbitration signals (BREQ, HLDA, HOLD) and chip select signals. Port 3 includes alternate functions of timers, serial interfaces, the optional bus control signal BHE and the system clock output (CLKOUT). Port 5 is used for the analog input channels to the A/ D converter or timer control signals. All port lines that are not used for these alternate functions may be used as general purpose I/O lines. Semiconductor Group 690 @® 4235605 0061600 235 mm

Serial communication with other microcontrollers, processors, terminals or external peripheral components is provided by two serial interfaces with different functionality, an Asynchronous/ Synchronous Serial Channel (ASCO) and a High-Speed Synchronous Serial Channel (SSC). They are upward compatible with the serial ports of the Siemens SAB 8051x microcontroller family and support full-duplex asynchronous communication up to 625 Kbaud and half-duplex synchronous communication up to 5 Mbaud (2.5 Mbaud on the ASCO) @ 20-MHz system clock. Two dedicated baud rate generators allow to set up all standard baud rates without oscillator tuning. For transmission, reception, and erroneous reception 3 separate interrupt vectors are provided for each serial channel. In asynchronous mode, 8- or 9-bit data frames are transmitted or received, preceded by a start bit and terminated by one or two stop bits. For multiprocessor communication, a mechanism to distinguish address from data bytes has been included (8-bit data + wake up bit mode). In synchronous mode, the ASCO transmits or receives bytes (8 bits) synchronously to a shift clock which is generated by the ASCO. The SSC transmits or receives characters of 2...16 bits length synchronously to a shift clock which can be generated by the SSC (master mode) or by an external master (slave mode). The SSC can start shifting with the LSB or with the MSB, while the ASCO always shifts the LSB first. A loop back option is available for testing purposes. A number of optional hardware error detection capabilities has been included to increase the reliability of data transfers. A parity bit can automatically be generated on transmission or be checked on reception. Framing error detection allows to recognize data frames with missing stop bits. An overrun error will be generated, if the last character received has not been read out of the receive buffer register at the time the reception of a new character is complete. Watchdog Timer The Watchdog Timer represents one of the fail-safe mechanisms which have been implemented to prevent the controller from malfunctioning for longer periods of time. The Watchdog Timer is always enabled after a reset of the chip, and can only be disabled in the time interval until the EINIT (end of initialization) instruction has been executed. Thus, the chip's start-up procedure is always monitored. The software has to be designed to service the Watchdog Timer before it overflows. If, due to hardware or software related failures, the software fails to do so, the Watchdog Timer overflows and generates an internal hardware reset and pulls the RSTOUT pin low in order to allow external hardware components to be reset. ‘The Watchdog Timer is a 16-bit timer, clocked with the system clock divided either by 2 or by 128. The high byte of the Watchdog Timer register can be set to a prespecified reload value (stored in WDTREL) in order to allow further variation of the monitored time interval. Each time it is serviced by the application software, the high byte of the Watchdog Timer is reloaded. Thus, time intervals between 25 us and 420 ms can be monitored (@ 20 MHz). The default Watchdog Timer interval after reset is 6.55 ms (@ 20 MHz). Semiconductor Group 691 MB 4235605 00b1b01 171

SIEMENS . C167 Instruction Set ‘Summary The table below lists the instructions of the C167 in a condensed way. The various addressing modes that can be used with a specific instruction, the operation of the instructions, parameters for conditional execution of instructions, and the opcodes for each instruction can be found in the “C16x Family Instruction Set Manual”. This document also provides a detailed description of each instruction. Instruction Set Summary Viemonie [Desception SSC ADDC(B) ‘Add word (byte) operands with Carry 2/4 SUB(B) Subtract word (byte) operands 2/4 ‘SUBC(B) Subtract word (byte) operands with Carry 2/4 MUL(U) (Un)Signed multiply direct GPR by direct GPR (16-16-bit) | 2 DIU) (Un)Signed divide register MDL by direct GPR (16-/16-bit) |2 DIVL(U) (Un)Signed long divide reg. MD by direct GPR (32-/16-bit) |2 CPU [Conplonentakectword (fe) GPR NES [Negsearectworgfye)GPR_————d OR(B) Bitwise OR, (word/byte operands) 2/4 XOR(B) Bitwise XOR, (word/byte operands) T2714 BCLR Cleardirectbit 2 BSET Set direct bit a - 2 BMOV(N) Move (negated) direct bit to direct bit 4 BAND, BOR, BXOR | ANDIORXOR det win arectok id direct word memory with immediate data ora) [Compare word(s) operands =i CMPD1/2 Compare word data to GPR and decrement GPR by 1/2 2/4 CMPI/2 ‘Compare word data to GPR and increment GPR by 1/2 [2/4 PRIOR Determine number of shift cycles to normalize direct 2 word GPR and store result in direct word GPR SHL/SHR Shift leftright direct word GPR 2 ROL / ROR Rotate left/right direct word GPR 2. ASH [Achmet gn Baron dre worsGPR [8 Semiconductor Group 692 M@™§ 46235605 0061602 008 mm

Instruction Set Summary (cont'd) Mnemonic Description Bytes MOV(B) Moveword(byte)data ss tS 214 MOVBS Move byte operand to word operand with sign extension 2/4 MOVBZ Move byte operand to word operand, with zero extension | 2/4 JMPA, JMPI, JMPR Jump absolute/indirect/relative if condition is met 4 JUMPS Jump absolute toa code segment 4. J(N)B Jump relative if direct bitis(not)set = t—<“<it=‘s«~CS*~*# JBC Jump relative and clear bit i direct bitis set. 4 JNBS Jump relative and set bit if direct bit is not set 4 CALLA, CALI, CALLA | Call absolute/indirectrelative subroutine if condition is met [4 CALLS - Call absolute subroutine in any code segment 4 PCALL Push direct word register onto system stack and call 4 absolute subroutine TRAP Call interrupt service routine via immediate trap number | 2 PUSH, POP Push/pop direct word register onto/from system stack [2 SCXT | Push direct word register onto system stack and update | 4 _ register with word operand RET Return from intra-segment subroutine 2 RETS Return from inter-segment subroutine 2 RETP Return from intra-segment subroutine and pop direct 2 word register from system stack RETI Return from interrupt service subroutine 2 SRST | Software Reset 4 IDLE Enter Idle Mode ~~ 4 PWRDN EnterPowerDown Mode 4 (supposes NMI-pin being low) SRYWOT Service Watchdog Timer 4 DISWDT Disable Watchdog Timer 4 EINIT Signify End-of-Initialization on RSTOUT-pin 4 ATOMIC Begin ATOMIC sequence «(2 EXTR | Begin EXTended Register sequence 2 EXTP(R) Begin EXTended Page (and Register) sequence 214 EXTS(R) "| Begin EXTended Segment (and Register) sequence 2/4 NOP” Null operation i Semiconductor Group 693 @™ 8235605 0061603 Tuy mm

Special Function Registers Overview The following table lists all SFRs which are implemented in the C167 in alphabetical order. Bit-addressable SFRs are marked with the letter “b” in column "Name". SFRs within the Extended ‘SFR-Space (ESFRs) are marked with the letter “E” in column "Physical Address”. An SFR can be specified via its individual mnemonic name. Depending on the selected addressing mode, an SFR can be accessed via its physical address (using the Data Page Pointers), or via its short 8-bit address (without using the Data Page Pointers). ‘Special Function Registers Overview Name Physical Description Reset | Address | Address Value en oo Control Register ABCON b FFRO, |i 0, ADDAT2 | FOA0, E|50, —_| A/D Converter 2 Result Register 0000, ADDRSEL1 |FE18, | 0Cy Address Select Register1 0000, ADDRSEL2 ee [0D | Address Select Register 2 0000,, ADEIC — b| FF9A, AD Converter Overrun Error Interrupt Control | 00004 Register BUSCONO b/FFOC, |86, | Bus Configuration Register 0 OXX0, BUSCON4 b Bus Contfiguration Register 4 0000, CAPREL GPT2 Capture/Reload Register 0000, cco [FE8O, [40 | CAPCOM Register 0 ~___ [00004 ccoc ob CAPCOM Register 0 Interrupt Control Register| 0000, cet | FEB2, CAPCOM Register 1 00004, CCIIC b|FF7A, |BDy | CAPCOM Register 1 Interrupt Control Register | 0000, cc2 FEG4, |42, | CAPCOM Register 2 ~ 0000, cezc ob CAPCOM Register 2 Interrupt Control Register | 0000, Semiconductor Group 604 @™ 8235605 O0b1b04 9480 a

Special Function Registers Overview (cont'd) Name Physical [8-Bit | Description Reset Address | Address Value ccs 43,4 [CAPCOM Register 3 Z 0000), CC3IC_b|FF7E, |8Fy | CAPCOM Register 3 Interrupt Control Register [0000 _ ccs 454 CAPCOM Register 5 0000, cer 004 cc7ic bb C34 CAPCOM Register 7 Interrupt Control Register | 00004 ccs CAPCOM Register 8 _ 000044 ccaic ib CAPCOM Register 8 Interrupt Control Register | 0000, ces _[FES%j[40y[CAPCOMRepsiro 00D, cc10 CAPCOM Register 10 0000}, ccioic ob C6, | CAPCOM Register 10 Interrupt Control Register | 0000, coi E96, | 4B, CAPCOM Register 11 ‘| 0000, C13 FESA, |4Dy | CAPCOM Register 13 0000} CCI3IC bb} FF92,, C8, CAPCOM Register 13 Interrupt Control Register | 0000, CCI5IC b/FF96, |CBy | CAPCOM Register 15 Interrupt Control Register | 0000, cc16 CAPCOM Register 16 0000, ccc ob BOy CAPCOM Register 16 Interrupt Control Register | 0000, Semiconductor Group 695 @™® 6235605 0061605 617

Special Function Registers Overview (cont'd) Name Physical |8-Bit | Description a Reset Address | Address Value cci7icb CAPCOM Register 17 Interrupt Control Register | 0000, cc1sic §b/ F164, E/B2, | CAPCOM Register 18 interrupt Control Register | 00004 ccs 334 CAPCOM Register 19 ~~ [00004 ccisic ob B3, CAPCOM Register 19 Interrupt Control Register | 0000, ocas 004 cc2sic | FI6E, E/B7, | CAPCOM Register 23 Interrupt Control Register | 0000, cc2sic bb BO, CAPCOM Register 25 Interrupt Control Register | 0000, cc26 FE74, |3Ay | CAPCOM Register 26 - (00004 cc26Ic bb BA, | CAPCOM Register 26 Interrupt Control Register | 00004, cc28 FE78, |3Cy | CAPCOM Register 28 0000, cca 2004 CC30IC b C6y CAPCOM Register 30 Interrupt Control Register | 00004 Ccatidp| Fie, [chy CAPCOM Rep 21 rat Gn at |=00, Semiconductor Group 696 @™@ 6235605 O0b1b0b 753 me

Special Function Registers Overview (cont'd) Name Physical |8-Bit | Description Reset Address | Address Value CCM3—_b/FF58, | ACy —_ | CAPCOM Mode Control Register 3 00004 coma b 814 __ | CAPCOM Mode Control Register 4 000044 ccMs —b 924 | CAPCOM Mode Control Register 5 000044 ccM7 bb 24, CAPCOM Mode Control Register 7 0000, cP CL FE10y | 08q CPU Context Pointer Register FCO, car |Fe0m |osy _|PUCom Segment Pat Rai esr) O00 DPOH sb | F102, E| 81,4 POH Direction Control Register 004 — DPIL _b/ F104, E 824 PAL Direction Control Register 00, DPIH | F1064 E 83, P1H Direction Control Register 004 DP4 -b/FFCAy (£5, —_| Port 4 Direction Control Register 004, DP6 b 00,5 Der FFDay |e, [Pon 7 mien Cont Rapier | DPPO [FEOO, | 00,4 CPU Data Page Pointer 0 Register (10 bits) 0000, DPP1 [FEO2, [Oty CPU Data Page Pointer 1 Register (10 bits) 00014 DPP2 FEO44 | 02, CPU Data Page Pointer 2 Register (10 bits) 0002}, DPP3 FE06, |03y | OPU Data Page Pointer 3 Register (10 bits) 0003, EXICON b | F1C04 E/ E04 External interrupt Control Register ! 0000, MDC b/FFOE, 87 | CPU Multiply Divide Control Register 0000, MDH FEOCy 08, | CPU Multiply Divide Register — High Word /0000, MDL CPU Multiply Divide Register - Low Word 0000, Semiconductor Group 697 @™ 8235605 0061607 b5T a

SIEMENS cre? Special Function Registers Overview (cont'd) Name Description —— Reset Address | Address Value OpP2.b Ely Port 2 Open Drain Control Register 0000), ODP3. ob Port 3 Open Drain Control Register 0000,, OpP8 | F1D6, E|EB, —_| Port 8 Open Drain Control Register 004 Pon »|FFO5, [ety [Par OHoh Rapier (Upern of ORTON oy P1H b/FFO6, [834 _| Port 1 High Register (Upper half of PORT) 004 P2 IFFCO, |E0, | Port 2 Register - 00004 P3 b/FFC4, |E2, |PonSRegister 0000, P6 b E64 Port 6 Register (8 bits) 00, P7 b/FFDO, |E8, |Port7 Register (bits) 004 PB bFFO4, |EA, | Ports Register (8 bits) 00, PECC2 —|FEC4, | 62 —_| PEC Channel 2 Control Register 0000, PECC3 | FEC6y PEC Channel 3 Control Register 0000, PECC4 ee PEC Channel 4 Control Register : 00004 PECC7 FECE, PEC Channel 7 Control Register 0000, PPO | F038, E PWM Module Period Register 0 — 0000, PPI FO3A, E| 1D, | PWM Module Period Register 1 0000, PP2 FO3Cy E PWM Module Period Register 2 0000, Pa 004 Semiconductor Group 698 @@! =6235605 OOb1b08 Sch

Special Function Registers Overview (cont'd) Name Physical |8-Bit _| Description Reset Address | Address Value PT2 F034, E) 1Ay | PWM Module Up/Down Counter 2 00004, PT3 | F036, E/1By | PWM Module Up/Down Counter 3 00004 Pwo 184 | PWM Module Pulse Width Register 0 0000), Pw2 FE34, |1Ay | PWM Module Pulse Width Register 2 0000, Pw3 PWM Module Pulse Width Register 3 0000, PWMCONOb|FF30, [984 | PWM Module Control Register 0 0000}, PWMCON1b | FF32,, | 994, PWM Module Control Register 1 00004 RPOH | F108, E|84, System Startup Configuration Register (Rd. only) | XX SOBG FEB4, 5A, | Serial Channel 0 Baud Rate Generator Reload | 0000, Register SOCON b Serial Channel 0 Control Register [0000 SOEIC b Serial Channel 0 Error Interrupt Control Register 0000, SORBUF [FeBe |5% | Serial Channel 0 Receive Buffer Register 1XXy (read only) Register i] Register SOTBUF Serial Channel 0 Transmit Buffer Register | 00,4 | (write only) S0TIC b/FF6Cy B64 | Serial Channel O Transmit Interrupt Control 00004, Register SP FE12y | 094 CPU System Stack Pointer Register "FC004 SSCBR FOB4, E|5A, | SSC Baudrate Register 0000, SSCCON b|FFB2, [D3, |SSCControlRegister 0000}, SSCEIC b ‘SSC Error Interrupt Control Register ) 0000, Semiconductor Group 699 M@™ 8235605 0061609 4bc

Special Function Registers Overview (cont'd) Name Physical |@-Bit |Description Reset Address | Address Value SSCRB SSC Receive Butfer (read only) XXXXq sscTic FF, |, 004 sIKOV FAO STKUN|FE%6, [064 |O°U Sask Undoow Ponte Rapr | FO, To [FESO, {281 | CAPCOM Timer 0 Register 0000}, TOIC b/FF9C, |CEy [CAPCOM Timer 0 Interrupt Control Register 0000, THC —bIFFOE, [CF | CAPCOM Timer interrupt Control Register| 00004 TIREL ‘2By | CAPCOM Timer 1 Reload Register 0000, 2 20, | GPT1 Timer 2 Register 0000,

73 FE42y GPTI Timer 3 Register 00004

Talc | FF64, | B24, | GPT1 Timer 4 Interrupt Control Register 0000, 16 |Fe48, |24, | GPT2 Timer 6 Register 0000, T6CON _b FF48, |[A4, | GPT2 Timer 6 Control Register 100004 TéIC b/FF68, [B44 | GPT2 Timer 6 Interrupt Control Register 0000, Semiconductor Group 700 M@™ 6235605 0061610 164

Special Function Registers Overview (cont'd) Name [Physical [@-Bit |Description | Reset | Address | Address Value

7 F050, E| 28, | CAPCOM Timer 7 Register 0000,

T78CON b/FF20, | 904 CAPCOM Timer 7 and 8 Control Register | 0000, T7ICb FI7Ay E BE, [CAPCOM Timer 7 Interrupt Control Register | 0000, T7REL F054, E 2Ay —_| CAPCOM Timer 7 Reload Register 0000,

18 F052, E294 CAPCOM Timer 8 Register ~~ | 000044

TaIc b FI7Cy E/BFy | CAPCOM Timer 8 Interrupt Control Register | 0000, TSREL F056, E 2B, | CAPCOM Timer 8 Reload Register 0000}, TFR b FFACy |D6y | Trap Flag Register _ 0000); woT |FEAE, 574 | Watchdog Timer Register (read only) 0000, WDTCON |FFAE, | D7} Watchdog Timer Control Register ~ 10000, XPOIC ob C34 X-Peripheral 0 Interrupt Control Register 00004 XPIICb | FI8Ey E X-Peripheral 1 Interrupt Control Register 100004 XP2IC_b|F196, E|CBy | X-Peripheral 2 Interrupt Control Register 0000, — XP3IC | FI9E, E|CFy __ | X-Peripheral 3 Interrupt Control Register ‘0000, ZEROS b/FFICy |8Ey | Constant Value 0's Register (read only) 0000, *) The system configuration is selected during reset. Note: The Interrupt Control Registers XPniC are prepared to control interrupt requests from integrated X-Bus peripherals. Nodes, where no X-Peripherals are connected, may be used to generate software controlled interrupt requests by setting the respective XPnIR bit. Semiconductor Group 701 WM =8235605 0061611 010

Ambient temperature under bias (7): SAB-C167-LM....ssssssssseserssseeccssecsssnsnnnnnunsesseeseeseesnennnusssanuseseeseessssssansnnnsesseseesssassessssessnneeeeO £0 +70 °C SAF-C167-LM..sssssssssssessssseeesssseensnnnssnnnnsseseesseeeennsannunssssnesesseeessatesssnsnsssseeesceessesssssssees “40 t0 +85 °C Storage temperature (T51)....ssecsssseesssssseeersessseessssnessssssseeessnseesssssneransseveccsssnnesssses recess = OD tO +150 C Voltage on Vec pins with respect to ground (Vgs) -assssesnsenseusintenseineinananeeneineen 05 10 46.5 V Voltage on any pin with respect to ground (Veg) .evctsnsntnesntntintntnenneinnnenneni0.5 10 Vog $0.5 V Input current on any pin during overload CONdILION ....sssssssnsusennsssesassnseseensenens 10 10410 MA Absolute sum of all input currents during overload CONItION -....ssctusssveeseteseesstaneeeeeene [100 MAJ Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During overload conditions (Viy>Voc or Viv<Vss) the voltage on pins with respect to ground (Vs) must not exceed the values defined by the Absolute Maximum Ratings. Parameter Interpretation The parameters listed in the following partly represent the characteristics of the C167 and partly its demands on the system. To aid in interpreting the parameters right, when evaluating them for a design, they are marked in column “Symbol”: CC (Controller Characteristics): The logic of the C167 will provide signals with the respective timing characteristics. SR (System Requirement): The external system must provide signals with the respective timing characteristics to the C167. DC Characteristics Vog=5V10%; Ves=0V; —— fopy = 20 MHz T, = 0 to +70 'C for SAB-C167-LM Ty, = -4010 +85 °C for SAF-C167-LM Parameter Symbol Limit Values en Test Condition Input low voltage {y SR|-0.5 - i -04 Input high voltage Vu SR}02Voco [Voor 05 |V |= (all except ASTIN and XTAL1) +0.9 Input high voltage RSTIN Va SR 0.6 Veo = Semiconductor Group 702 MB 8235605 OOb1lb1e TS?

Parameter | Limit Values Unit | Test Condition Output low voltage _ = 0.45 Vo f=24mA (PORTO, PORT!, Port 4, ALE, RD, | WR, BHE, CLKOUT, RSTOUT) Output low voltage Vo, OC[- 0.45 [Vg = 1.6 mA {all other outputs) Output high voltage _ rey Veo |= [Vow S00 HA (PORTO, PORT!, Port4, ALE, RD, 2.4 dow =— 2.4 mA WR, BHE, CLKOUT, RSTOUT) Output high voltage - Vow =- 250 pA (all other outputs) 24 V [Tow == 1.6 mA Input leakage current (Port 5) 2) +200 [nA |OV< Vy < Veo Input leakage current (all other) 4500 nA [OV < Fin < Voo ASTIN pullup resistor 150K. a Read/Write inactive current ®) 450 WA | Voy =2.4V ~ ReadWrite active current © Vout = Veumax ALE inactive current 9 Tu? [= [150 [A _| Your = Vounes ALE active current 5 [nen [2000 [= [HA | For =24V Port 6 inactive current 5) [ew [= [150 [WA | our = 2.4V Port 6 active current Tog. =~ -2000 BA | Pour = Voumax PORTO configuration current 9 | Iopy |= ” | BA | Viv =Vounn Im) [100 |= [WA | Fou= Vrms XTAL1 input current [hm ccj|- ——fs20 WA 0V< Pu Moo Pin capacitance ® Jee i | f= MHz (digital inputs/outputs) T= 25°C Power supply current [ee le | Reset active 8* fopu fopy in [MHz] Idle mode supply current ‘Io OC Re fopu in [MHz]? 3* fopu Power-down mode supply current | Ip CC ~ [100 [wa | Yop = 5.5V9 Semiconductor Group 703 M™ 6235605 0061613 193

*) This specification is not valid for outputs which are switched to open drain mode. In this case the respective output will float and the voltage results from the external circuitry. 2) This specification does not apply to the analog input (Port 5.x) which 1s currently converted. 9) The maximum current may be drawn while the respective signal line remains inactive. 4) The minimum current must be drawn in order to drive the respective signal line active. 5) This specification is only valid during Reset, or during Hold- or Adapt-mode. Port 6 pins are only affected, if they are used for CS output and the open drain function is not enabled. ®) Not 100% tested, guaranteed by design characterization. 7) The supply current is a function of the operating frequency. This dependency is illustrated in the figure below. These parameters are tested at 20 MHz CPU clock with all outputs open, ®) All inputs (including pins configured as inputs) at 0 V to 0.1 V or at Veg - 0.1 V to Voc, Vag = 0 V, all outputs (including pins configured as outputs) disconnected. x | 200- | ' lecmax i 150- ' 100- ' | ' | pT TTT et ‘omax } 50 1 10 ' } 5 10 15 20 fopy [MHz] Figure 8 Supply/idle Current as a Function of Operating Frequency Semiconductor Group 704 WM 4235605 O0b1b14 627 a

AVD Converter Characteristics Voo=5V10%; Vss=0V T= 0to+70°C for SAB-C167-LM T, = -40 to +85 °C for SAF-C167-LM 4.0 VS Vance $ Voct0.1 V; Ve5-0.1 VS Vaguo $ Vagt0.2 V Parameter Symbol | Limit Values Test Condition [min. | max. Analog input voltage range Van SR | Vacwo Vener v Sample time ts CC - | 2 tee [| 2)4) Conversion time te CC\\- 10 too + a4 tg+ 4TCL Total unadjusted error TUE CC|- 5 Internal resistance of reference | Rener CC tec/ 250 | kQQ | fec in (ns] 9” voltage source - 0.25 Internal resistance of analog RasacCC 15/500 |kGQ2 |tsin (ns] 2)” source - 0.25 ADC input capacitance [Cm CCl- [50 pF |? Notes ~ 1 Vg may exceed Vagnp OF Vaner up to the absolute maximum ratings. However, the conversion result in these cases will be X000, or X3FFy, respectively. ?) During the sample time the input capacitance C can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitors to reach their final voltage level within 1s. After the end of the sample time #s, changes of the analog input voltage have no effect on the conversion result. Values for the sample clock gc depend on programming and can be taken from the table below. 3) This parameter includes the sample time ss, the time for determining the digital result and the time to load the result register with the conversion result Values for the conversion clock icc depend on programming and can be taken from the table below. 4) This parameter depends on the ADC control logic. It is not a real maximum value, but rather a fixum. 5) TUE is tested at Vaner=5.0V, Vagno=0V, Voc=4.8V. It is guaranteed by design characterization for all other voltages within the defined voltage range. ® During the conversion the ADC's capacitance must be repeatedly charged or discharged. The internal resistance of the reference voltage source must allow the capacitors to reach their respective voltage level within tgg. The maximum internal resistance results from the programmed conversion timing. 7) Not 100% tested, guaranteed by design charactenzation. ADCON.15|14 ADCON.13/12 | Sample clock fs-

00 TOL *32 | too

a Reserved, do not use fog *2

10 TOL" 128 [10 tect

" ToL" 64 ix [tet Semiconductor Group 705 @@ 8235605 OObLb1S 7bb

External Clock Drive XTAL1 Vog=5V+10%; Vag=0V T,=0 to +70 °C for SAB-C167-LM T,=-40to+85°C for SAF-C167-LM Parameter Max.CPUClock | Variable CPU Clock Unit = 20 MHz 1/2TCL = 1 to 20 MHz Oscillator period To. sr[25 [25 25 ns High time = - 6 ns Low time b SR - 6 ns Rise time SR 5 - Is Ins Falline le sRl= sd 4 ~et ls 4 Vie My h Teh wToo76s Figure 11 External Clock Drive XTAL1 Memory Cycle Variables The timing tables below use three variables which are derived from the BUSCONx registers and represent the special characteristics of the programmed memory cycle. The following table describes, how these variables are to be computed. Description [ Symbol | Values ALE Extension [m | TCL* <ALECTL> Memory Cycle Time Waitstates te 2TCL* (15 - <MCTC>) | Memory Tristate Time de 2TCL* (1 - <MTTC>) _ Semiconductor Group 707 M™ 8235605 O0b1b17 539

| AC Characteristics (cont'd) Multiplexed Bus Veo=5V210%; Ves=0V T,=0t0+70°C for SAB-C167-LM T,=-40104+85°C forSAF-C167-1M C, (for PORTO, PORT1, Port 4, ALE, RD, WA, BHE, CLKOUT) = 100 pF C, (for Port 6, CS) = 100 pF ALE cycle time = 6 TCL + 2ty + fg + ty (150 ns at 20-MHz CPU clock without waitstates) Parameter [Symbol | Max. CPU Clock Variable CPU Clock —_| Unit = 20 MHz 4/2TCL = 1 to 20 MHz _ min. —_| max. min. [max. | ALE high time 154% |- TCL-10+%|- [ns Aadioss souptoALE | co] 10+ | _(T0L-15+%|- [rw Adkess held ater ALE |i, 00/15+% [= _|TOL-10+m [= ALE fallingedgetoRD, |% CC\\15+% |~ TCL-10+% |- ns WR (with RW-delay) | ALE falling edge toRD, f CC -10+% 10+, j- ns WR (no RW-delay) | Address float after AD, [fp CC |— ns WR (with RW-delay) | Address float afterRD, | 4, CC|- TCL+5 ns WR (no RW-delay) RD, WR low time te CC|40 +t 2TCL - 10 ns (with RW-delay) +e RD, WR low time ty CC165 +t 3TCL- 10 ns {no RW-delay) +b RD to valid data in ta SR|- Bri |- leTCL-25 [ns (with RW-delay) | [tte RD to valid data in its SR/- 50+f |= STCL-25 ns (no RW-delay) | +l ALE low to valid datain [te SR 50 - (3TCL-25 [ns tty to thy tle Address to valid datain ty SR 65 4TCL-35 [ns + tht bo + 2th + te Data hold after RD ns rising edge Data float after RD 354% |- 2TCL-15 [ns __ _ + te Data valid to WR te CC|35+f |~ 2TCL-15 |= ns - . | ite Semiconductor Group 708 M™ 8235605 0061618 475

Parameter ==‘ |Symbol| Max.CPUClock | Variable CPUClock | Unit = 20 MHz _V2TCL = 1 to 20 MHz minimax mine. Data hold after WR. tog CC) 35 +t, aTCL-15 — ns +h . __ ALE rising edge after RD, | t5 CC 35 +t, 2TCL-15 |- ns WR _ th | Address hold after RD, |, CC|35 +t, 2TcL-15 |= ns WR _ - +p ALE fallngedgetoCS | typ CC /5-% |10-% —|-S-te 10- tm [ns CS low to Valid Data In tg SR 45 - 3TCL-30 ins tio + Qty + tot Qty | CS hold after RD, WR [ie cefere | 3TCL-15 |= ins +r | ALE fall. edge toRdcS, |%. CCl20+% | TCL-5 [= ns WrCS (with RW delay) - - es +t ALE fall. edgetoRdcs, | CC|-5+% |- 5 = ns wrcs (no RW delay) : es ee a _ Address float after RdCS, | t44 CC}— 0 1) ns WrCS (with RW delay) jf Address float after RACS, | tj, CC TCL ns WrCS (no RW delay) RdCS to Valid Data In tye SR|- (20 +t 2TCL-30 ns (with RW delay) | +e RdCS to Valid Data In fq SRI- 454i, |= 3TCL-30 |ns RdCS,WrCS LowTime tig CC|40+t, |- 2TCL - 10 - ns (with RW delay) i tho __ RdCS, WrCS Low Time tig CC} 65 + fe - 3TCL-10 - ns (no RW delay) tte __ Data valid to WrCS te CC|35+te |= aTCL-15 |- ns | +f Data float after RACS - 304% |- 2TCL-20 |ns the Address hold after ts, CC) 30 +t, - 2TCL-200 - ns RdCS, WrCS ite Data hold after WrCS tes CC) 30+t; - 2TCL-20 |- ns tle M! 6235605 0061619 30] Semiconductor Group 709

sete tle 4 sts | i TT | A23-A16 ty) Bt, — | BHE — — : | prlee =< —-h — bg RdCSx : NG f _ | : : : : poole tt | | wR “NY — \\WRL, WRH : =; it | ; oe | fete hol too ey | | WroSx \\ Y \\<——tte +} Figure 12-1 External Memory Cycle: Multiplexed Bus, With Read/Write Delay, Normal ALE @™§ 46235405 OOb1be0 023 Semiconductor Group 710

AE A \\ in J te ti ro eS lo BHE ; + —* f ht pt : : j {hs —+ RD i i NE TY tot RdCSx H H NO Kf to i << ___ _WA, i No Y WAL, WRH H = ot : rhe — | WicSx \\ 4 ta Figure 12-2 External Memory Cycle: Multiplexed Bus, With Read/Write Delay, Extended ALE MB 8235605 O0b1b21 TLT mt Semiconductor Group 711

se typ ty ——~ (9) yee BHE — — f Bett y ‘ ww \\ pois i RACSx : ™ j fT ty alte | _ WN EY, WAL, WRH Poa Top ot bys rls feels a tn es | WrCSx \\ x Figure 12-3 External Memory Cycle: Multiplexed Bus, No Read/Write Delay, Normal ALE MB 46235605 OOblbe2 Tb Semiconductor Group 712

te {3 roy S's on ——, A23-A16 ——— oh) oe a EE BHE } — — f SSS ReadCyele i : behest ; q \\ ww RD H : \\ HH eA fot — i hs eels bo bp —! RdCSx : ' XN : _ —h ohh _ sk eal : WR, : \\ i / AL, WAH : } Ty ut : ha | tig rites i ho | Wrcsx \\ fo te + Figure 12-4 External Memory Cycle: Multiplexed Bus, No Read/Write Delay, Extended ALE M@™§ 8235605 O0blb2e3 632 Semiconductor Group 713

AC Characteristics (cont'd) Demultiplexed Bus Voo=5V410%; Veg=0V T,=0t0+70°C for SAB-C167-LM T,=-40t0+85 °C forSAF-C167-LM C, (for PORTO, PORT1, Port 4, ALE, RD, WA, BHE, CLKOUT) = 100 pF | CC, (for Port 6, CS) = 100 pF ALE cycle time = 4 TCL + 2t, + te + ff (100 ns at 20-MHz CPU clock without waitstates) Parameter Symbol! Max. CPU Clock Variable CPU Clock Unit = 20 MHz 1/2TCL = 1 to 20 MHz ALE high time th CC/15+t TOL-10+u|- [ns Address setup to ALE te CC)10+h TCL - 15 +t, ns ALE falling edge toRD, jf CC|15+% TCL-10 ns WR (with RW-delay) +h ALE fallingedgetoRD, |t CC]-10+% “10 ns WR (no RW-delay) thy RD, WR low time te CC/40 +t 2TCL-10 ns (with RW-delay) +t RD, WR low time hs CC|65+ te STCL-10 = ns (no RW-delay) +h | RD to valid data in lq, SRI B+to |= [2TCL-25 [ns (with RW-delay) | +l RD to valid data in |‘ SR|- 50+ |= |3TCL-25 [ns (no RW-delay) | +e ALE low to validdatain {t%~ SR/- 50 STCL - 25 ns +tytle title Address to validdatain [1 SR 65 4TCL-35 | ns + 2th + he +2, 4 bo Data hold after RD ty SR ns rising edge Data float after RD rising B5+t |= 2TCL-15 |ns edge (with RW-delay) +h Data float atter RD rising |t, SR 1Stte |= TCL-10 [ns edge (no RW-delay) ltt ALE rising edge after AD, | a5 CC|-10 +t, “10 j- ns WR +h MP 4235605 ooblbe4 275 Semiconductor Group 4

Parameter, ~~ | Symbol | Max. CPU Clock Variable CPU Clock | Unit | =20MHz | _‘1/2TCL = 1 to 20 MHz Address holdafter RD, |i CC|0+% |- ‘0 ns WR Ltt ALETaling ofge1008 [iq 00'S [1-m [Sm _(1-m __In CS low to Valid Data In 45 - 3TCL-30 [ns +o 2ty | +t +2ty CS hold after RD, WR - TTCL- 15 ro ns ALE falling edge to RCS, [tf CC|20+% |- TTCL-5 ns WICS (with RW-delay) \\4t ALE falling edge to RCS, | tg CC]-5+t% 5 = ns WrCS (no RW-delay) tty RACS to Valid Data In - 20 + te 2TCL-30 [ns (with RW-delay) ft +t RaCS to Valid Data In - 45 + tc 3TCL-30 [ns (no RW-delay) __ +o RACS, WrCS LowTime |ty CC] 40 +% 2TCL - 10 ns (with RWedelay) +l RaCs, WiCS Low Time |i CCl65+i |- 3TCL- 10 ns (no RW-delay) th Data valid to WicS = laTcL-15 ns [th Data hold after RACS of fo ns Data float after RICS = 30 +t - aTcL-20 |ns (with RW-delay) |. +h Data float after RdCS teg SR|- Sth i= TCL - 20 ns (no RW-delay) ft foe Address hold atter tes CCl-15+f |- 15 - ns RCS, WrCS 7 the Data hold afterWrCS [ty CC | 10 +t TCL-15 ns _. +h M! =8235b05 OOblbeS bOS Semiconductor Group 715

hk =e ——) be >! ale AN Lio AN A23-A16 tt, ——_ et BHE — — f reba! bets ! {bth — Read Cycle ! bite 07-00 ' i to RD PON A Pot ole beg Write Cycle : ety BUS : : ‘ 07-D0 ; : A : : ot sl | WR, re te | ‘WAL, WRH oN H fo | fete} ho | Wresx \\ 4 | tye Figure 13-1 External Memory Cycle: Demuttiplexed Bus, With Read/Write Delay, Normal ALE @™ 6235605 O0blb2b S4L Semiconductor Group 716

Sos ee : A23-A16 oe ts : BHE ? + — ‘ : ke to teks ot Read Cycle 3 a | BUS : i ~~ | (D15-D8) i { Gatain >> ' 07-00 : fot Lod — : hu i RD ! \\ wea i — ts i | RACE : \\ 4 ' Write Cycle : ety BUS - : WR, pb nt be el AL, WRH : NO as tp ht : WiCSx NX f hg Figure 13-2 External Memory Cycle: Demultiplexed Bus, With Read/Write Delay, Extended ALE M™ 8235605 00b1b27 438 Semiconductor Group 17

A23-A16 oo te ' BHE — — f : iti | fo feots : bo bey j Fiend Cycle : tiki ! (015-08) 07-Do : it tt : is Dot if _ fama tee Po RD iN wea io eat ee ‘te a ee — bow mee RaCSx ™ wy BUS : ! ; a a D7-Do : : : : fh i by WA, m ihe ei | AL, WRH ™ : as WrCSx NX if Figure 13-3 External Memory Cycle: Demultiplexed Bus, No Read/Write Delay, Normal ALE Semiconductor Group 718 @® 8235605 O0blbed 314

tb ts, rt i te ft . : i A23-A16 oo tt ln BHE } 4 — ‘ ' ste to fobs | BUS \\' : (015-08) i {_ tatain > 07-00 a! — ——— en bets tg ot 1 RaCSx ee en 7 Write Cycle : bent «i BUS : : D7-Do : : arent : : fate i -—tb—~ pte: WR, i : AL, WRH ! ; ee} WOON } moe Figure 13-4 External Memory Cycle: Demultiplexed Bus, No Read/Write Delay, Extended ALE Semiconductor Group 719 @™® 8235605 00b1b2e9 250

AC Characteristics (cont'd) CLKOUT and READY Vec=5Vt10% Vag=0V T,=0t0+70°C for SAB-C167-LM T,=-40t0+85°C for SAF-C167LM_ , (for PORTO, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF , (for Port 6, CS) = 100 pF Parameter Max. CPU Clock | Variable CPU Clock | Unit = 20 MHz 1/2TCL = 1 to 20 MHz min. [max. | min. max. CLKOUT cycle time It CCi50 [50 ——*([2TCL 2TCL ns CLKOUT high time [> CC/20 |- Ta-5 |- ns akouTialime CLKOUT risingedgeto [tx CC]O+m [10+m [Orn 104% ns ALE falling edge Synchronous READY |r, SR| 15 ns setup time to CLKOUT Synchronous READY |i SRS. ns hold time after CLKOUT | Asynchronous READY —f_-—« SR. 65 - [2TCL +15 ns low time | | Asynchronous READY fy © SR| 15 ns setup time ") Asynchronous READY |i, SR - ns hold time Async. READY hold time |t% SRO 0 0 TCL-25 [ns after RD, WR high | +2, + fe + 2th + tp (Demuttiplexed Bus)? | | 2 a _ Notes: 1) These tunings are given for test purposes only, in order to assure recognition at a specific clock edge 2) Demultiplexed bus is the worst case. For multiplexed bus 2TCL are to be added to the maximum values This adds even more time for deactivating READY ‘The 2t, refer to the next following bus cycle Semiconductor Group 720 M@™ 6235605 00b1b30 T?e

~ : READY) a Running cycle *) wail MUX/Tristate Ss 1 ' ta iit: : ' euKouT \\ BNO NINN tt ot fat ' ii it bt ‘ 1 ALE Join A 3 t Vi i it it y ' tt tt tt t ' RD, WR it t Tt u t ii bef ihe hs tite OU ' Syne Tt Toe WD Hy READY. ii an tt Ht Ny 4) tig the be bs 1 bo ' Asyne IIS ig) n READY. : BN: d . My hr —_— 3 see 6) Figure 14 CLKOUT and READY Notes ” Cycle as programmed, including MCTC wartstates (Example shows 0 MCTC WS).

2 The leading edge of the respective command depends on RW-delay

READY sampied HIGH at this sampling pont generates a READY controlied waitstate, READY sampled LOW at this sampling pomt terminates the currently running bus cycle READY may be deactivated in response to the trailing (sing) edge of the corresponding command (RD or WA) 9) Ifthe Asynchronous READY signal does not fulfill the indicated setup and hold times with respect to CLKOUT (e.g. because CLKOUT 1s not enabled), it must fultill f;7 in order to be safely synchronized This is guaranteed, if READY ts removed in response to the command (see Note “!) ® Multiplexed bus modes have a MUX waitstate added after a bus cycle, and an additional MTTC waitstate may be inserted here. For a multiplexed bus with MTTC waitstate this delay is 2 CLKOUT cycles, for a demultiplexed bus without MTTC waitstate this delay 1s zero

7 The next extemal bus cycle may start here

M@® = 8235605 0061631 109

AC Characteristics (cont'd) External Bus Arbitration Vec=5V#10% Ves = OV T,=010+70°C for SAB-C167-LM T,=-4010+85°C for SAF-C167LM_ , (for PORTO, PORT1, Port 4, ALE, AD, WR, BHE, CLKOUT) = 100 pF C, (for Port 6, CS) = 100 pF Parameter ~~ Symbol | Max.CPUClock | VariableCPU Clock | Unit _ =20MHz W2TCL =1 to 20 MHz min. [max | max. HOLD input setup time |r, SR - ns CLKOUT toHLDA high fre. CC ns or BREQ low delay CLKOUT toHLDA tow —|i—) CC ns or BREG high delay CSxrelease fu CCl= ns Other signats release | tm CC|— [20s [ns Other signals drive te ccs | [25 [ns Semiconductor Group 722 M@™ 8235605 00b1b32 445 ml

HOLD ‘ i : ALDA : TN BREG ; NE) x4 poccccrca senna (On P6.x) Other ‘ ceseeeeeeeeeeeee Figure 15 External Bus Arbitration, Releasing the Bus Notes 1) The C167 will complete the currently running bus cycle before granting bus access 2) This is the first possibility for BREO to get active 3) The CS outputs will be resistive high (pullup) after ty Semiconductor Group 723 M@® 8235605 0061633 78)

: ; i 2) | ouwot “NON NAN IY YY ; sh + : : HOLD iso: j : ! : : ite HLDA : : LA: | jt ile fhe : bbs CBx i (On P6.x) H : itr Other elec eeeeceeccecseeeeecceceeecceee. C Signals s Figure 16 External Bus Arbitration, (Regaining the Bus) Notes ’) This is the last chance for BREQ to tngger the indicated regain-sequence Even if BREQ is activated earlier, the regan-sequence is initiated by HOLD going high Please note that HOLD may also be deactivated without the C167 requesting the bus 2) The next C167 driven bus cycle may start here Semiconductor Group 724 Mi 4235605 0061634 616