SAFC163-L

C163-L SIEMENS | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 68

Technical content

0LFURFRPSXWHU&RPSRQHQWV %LW&0266LQJOH&KLS0LFURFRQWUROOHU Data Sheet 1998-08 Preliminary http://www.siemens.de/ semiconductor/

Revision History: 1998-08 Preliminary Previous Releases: 12.95 Advance Information Page Subjects --- 3 V specification introduced. 2 Ordering codes removed. 3 Pin description corrected (pin 16, 17, 21, 40). 24 SSCBR removed. 26, 27 Revised description of Absolute Maximum Ratings and Operating Conditions. 36 PLL description reworked. 39, 47 t 22 updated. 55 t 35, t36, t59 updated. 61 t 200, t203, t204, t209 updated. Edition 1998-08 Published by Siemens AG, Bereich Halbleiter, Marketing-Kommunikation Balanstraße 73, D-81541 München © Siemens AG 1998. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components per se, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide. Due to technical requirements components may contain dangerous substances. For information on the type in question please contact your nearest Siemens Office, Semiconductor Group. Siemens AG is an approved CECC manufacturer. Packing Please use the recycling operators known to you. We can also help you - get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components 1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express written approval of the Semiconductor Group of Siemens AG. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If the y fail, it is reasonable to assume that the health of the user may be endangered.

• High Performance 16-bit CPU with 4-Stage Pipeline – 80 ns Instruction Cycle Time at 25 MHz CPU Clock – 400 ns Multiplication (16 × 16 bit), 800 ns Division (32 / 16 bit) – Enhanced Boolean Bit Manipulation Facilities – Additional Instructions to Support HLL and Operating Systems – Register-Based Design with Multiple Variable Register Banks – Single-Cycle Context Switching Support – 16 MBytes Total Linear Address Space for Code and Data – 1024 Bytes On-Chip Special Function Register Area
• 16-Priority-Level Interrupt System with 20 Sources, Sample-Rate down to 40 ns
• 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via Peripheral Event Controller (PEC)
• Clock Generation via on-chip PLL (1:1.5/2/2.5/3/4/5), via prescaler or via direct clock input
• On-Chip Memory Modules – 1 KBytes On-Chip Internal RAM (IRAM)
• On-Chip Peripheral Modules – Two Multi-Functional General Purpose Timer Units with 5 Timers – Two Serial Channels (Synchronous/Asynchronous and High-Speed-Synchronous)
• Up to 16 MBytes External Address Space for Code and Data – Programmable External Bus Characteristics for Different Address Ranges – Multiplexed or Demultiplexed External Address/Data Buses with 8-Bit or 16-Bit Data Bus Width – Five Programmable Chip-Select Signals – Hold- and Hold-Acknowledge Bus Arbitration Support
• Idle and Power Down Modes
• Programmable Watchdog Timer and Oscillator Watchdog
• Up to 77 General Purpose I/O Lines
• High Speed Operation with 5 V Supply up to 25 MHz
• Low Power Operation with 3 V Supply up to 12 MHz
• Supported by a Large Range of Development Tools like C-Compilers, Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers, Simulators, Logic Analyzer Disassemblers, Programming Boards
• 100-Pin TQFP Package (Thin QFP) This document describes the SAB-C163-LF , the SAB-C163-L25F and the SAF-C163-L25F . For simplicity all versions are referred to by the term C163-L throughout this document. C166-Family of High-Performance CMOS 16-Bit Microcontrollers Preliminary C163-L 16-Bit Microcontroller C163-L 1 1998-08

11Aug98@14:48h Intermediate Version Semiconductor Group 2 1998-08 C163-L Introduction The C163-L is a derivative of the Siemens C166 family of 16-bit single-chip CMOS microcontrollers. It combines high CPU performance (up to 12.5 million instructions per second) with high peripheral functionality and enhanced IO-capabilities. Figure 1 Logic Symbol The C163-L can be operated from a 5 V power supply as well as from a 3 V power supply (25 MHz versions C163-L25F only). Within the standard supply voltage range of VDD = 4.5 - 5.5 V it delivers its maximum performance at CPU clock frequencies of up to 25 MHz. Within the reduced supply voltage range of VDD = 2.7 - 3.6 V it provides low power operation for energy sensitive applications at CPU clock frequencies of up to 12 MHz (PLL operation is not supported in this case).

Ordering Information

The ordering code for Siemens microcontrollers provides an exact reference to the required product. This ordering code identifies:

• the derivative itself, ie. its function set
• the specified temperature range
• the package
• the type of delivery. For the available ordering codes for the C163-L please refer to the „Product Information Microcontrollers“, which summarizes all available microcontroller variants. C163-L

11Aug98@14:48h Intermediate Version Semiconductor Group 3 1998-08 C163-L Note: The ordering codes for Mask-ROM versions are defined for each product after verification of the respective ROM code. Pin Configuration TQFP Package (top view) Figure 2 P5.12/T6IN P5.11/T5EUD P5.10/T6EUD P2.15/EX7IN P2.14/EX6IN P2.13/EX5IN P2.12/EX4IN P2.11/EX3IN P2.10/EX2IN P2.9/EX1IN P2.8/EX0IN P6.7/BREQ P6.6/HLDA P6.5/HOLD P6.4/CS4 P6.3/CS3 P6.2/CS2 P6.1/CS1 P6.0/CS0 NMI RSTOUT RSTIN VDD VSS P1H.7/A15 100 C163-L P1H.6/A14 P1H.5/A13 P1H.4/A12 P1H.3/A11 P1H.2/A10 V SS VDD P1H.1/A9 P1H.0/A8 P1L.7/A7 P1L.6/A6 P1L.5/A5 P1L.4/A4 P1L.3/A3 P1L.2/A2 P1L.1/A1 P1L.0/A0 P0H.7/AD15 P0H.6/AD14 P0H.5/AD13 P0H.4/AD12 P0H.3/AD11 P0H.2/AD10 P0H.1/AD9 P0H.0/AD8 P5.13/T5IN P5.14/T4EUD P5.15/T2EUD V SS XTAL1 XTAL2 VDD P3.0 P3.1/T6OUT P3.2/CAPIN P3.3/T3OUT P3.4/T3EUD P3.5/T4IN P3.6/T3IN P3.7/T2IN P3.8 P3.9 P3.10/TxD0 P3.11/RxD0 P3.12/BHE /WRH P3.13 P3.15/CLKOUT P4.0/A16 P4.1/A17 P4.2/A18 P4.3/A19 VSS VDD P4.4/A20/SSPCE1 P4.5/A21/SSPCE0 P4.6/A22/SSPDAT P4.7/A23/SSPCLK RD WR /WRL READY ALE EA VDD VSS OWE P0L.0/AD0 P0L.1/AD1 P0L.2/AD2 P0L.3/AD3 P0L.4/AD4 P0L.5/AD5 P0L.6/AD6 P0L.7/AD7 V DD VSS

11Aug98@14:48h Intermediate Version Semiconductor Group 4 1998-08 C163-L Pin Definitions and Functions Symbol Pin Numb. TQFP Input Out- put Function P5.10 P5.11 P5.12 P5.13 P5.14 P5.15 100 I I I I I I I Port 5 is a 6-bit input-only port with Schmitt-Trigger characteristics. The pins of Port 5 also serve as timer inputs: T6EUD GPT2 Timer T6 External Up/Down Control Input T5EUD GPT2 Timer T5 External Up/Down Control Input T6IN GPT2 Timer T6 Count Input T5IN GPT2 Timer T5 Count Input T4EUD GPT1 Timer T4 External Up/Down Control Input T2EUD GPT1 Timer T2 External Up/Down Control Input XTAL1 XTAL2 I O Input to the oscillator amplifier and input to the internal clock generator. Output of the oscillator amplifier circuit. To clock the device from an external source, drive XTAL1, while leaving XTAL2 unconnected. Minimum and maximum high/low and rise/fall times specified in the AC Characteristics must be observed. P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 P3.8 P3.9 P3.10 P3.11 P3.12 P3.13 P3.15 IO O I O I I I I O IO O O O Port 3 is a 15-bit (P3.14 is missing) bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. Port 3 outputs can be configured as push/pull or open drain drivers. Some Port 3 pins also serve for alternate functions: T6OUT GPT2 Timer T6 Toggle Latch Output CAPIN GPT2 Register CAPREL Capture Input T3OUT GPT1 Timer T3 Toggle Latch Output T3EUD GPT1 Timer T3 Ext.Up/Down Ctrl.Input T4IN GPT1 Timer T4 Input for Count/Gate/Reload/Capture T3IN GPT1 Timer T3 Count/Gate Input T2IN GPT1 Timer T2 Input for Count/Gate/Reload/Capture T×D0 ASC0 Clock/Data Output (Asyn./Syn.) R ×D0 ASC0 Data Input (Asyn.) or I/O (Syn.) BHE Ext. Memory High Byte Enable Signal, WRH Ext. Memory High Byte Write Strobe CLKOUT System Clock Output (=CPU Clock)

11Aug98@14:48h Intermediate Version Semiconductor Group 5 1998-08 C163-L P4.0 P4.1 P4.2 P4.3 P4.4 P4.5 P4.6 P4.7 IO O O O O O O O O O IO O O Port 4 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. In case of an external bus configuration, Port 4 can be used to output the segment address lines and it provides the SSP interface lines: A16 Least Significant Segment Address Line A17 Segment Address Line A18 Segment Address Line A19 Segment Address Line A20 Segment Address Line, SSPCE1 SSP Chip Enable Line 1 A21 Segment Address Line, SSPCE0 SSP Chip Enable Line 0 A22 Segment Address Line, SSPDAT SSP Data Input/Output Line A23 Most Significant Segment Addr. Line SSPCLK SSP Clock Output Line RD 33 O External Memory Read Strobe. RD is activated for every external instruction or data read access. WR / WRL 34 O External Memory Write Strobe. In WR -mode this pin is activated for every external data write access. In WRL-mode this pin is activated for low byte data write accesses on a 16-bit bus, and for every data write access on an 8-bit bus. See bit WRCFG in register SYSCON for mode selection. READY 35 I Ready Input. When the Ready function is enabled, a high level at this pin during an external memory access will force the insertion of memory cycle time waitstates until the pin returns to a low level. ALE 36 O Address Latch Enable Output. Can be used for latching the address into external memory or an address latch in the multiplexed bus modes. EA 37 I External Access Enable pin. A low level at this pin during and after Reset forces the C163-L to begin instruction execution out of external memory. A high level forces execution out of the internal ROM. The C163-L must have this pin tied to ‘0’. Pin Definitions and Functions (cont’d) Symbol Pin Numb. TQFP Input Out- put Function

11Aug98@14:48h Intermediate Version Semiconductor Group 6 1998-08 C163-L PORT0 P0L.0-7 P0H.0-7 41 - 48 51 - 58 IO PORT0 consists of the two 8-bit bidirectional I/O ports P0L and P0H. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. In case of an external bus configuration, PORT0 serves as the address (A) and address/data (AD) bus in multiplexed bus modes and as the data (D) bus in demultiplexed bus modes. Demultiplexed bus modes: Data Path Width: 8-bit 16-bit P0L.0 – P0L.7: D0 – D7 D0 - D7 P0H.0 – P0H.7: I/O D8 - D15 Multiplexed bus modes: Data Path Width: 8-bit 16-bit P0L.0 – P0L.7: AD0 – AD7 AD0 - AD7 P0H.0 – P0H.7: A8 - A15 AD8 - AD15 PORT1 P1L.0-7 P1H.0-7 59 - 66 67, 68, 71 - 76 IO PORT1 consists of the two 8-bit bidirectional I/O ports P1L and P1H. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. PORT1 is used as the 16-bit address bus (A) in demultiplexed bus modes and also after switching from a demultiplexed bus mode to a multiplexed bus mode. RSTIN 79 I Reset Input with Schmitt-Trigger characteristics. A low level at this pin for a minimum of 2 CPU clock cycles while the oscillator is running resets the C163-L. An internal pullup resistor permits power-on reset using only a capacitor connected to VSS . Note: To let the reset configuration of PORT0 settle and to let the PLL lock a reset duration of ca. 1 ms is recommended. RST OUT 80 O Internal Reset Indication Output. This pin is set to a low level when the part is executing either a hardware-, a software- or a watchdog timer reset. RSTOUT remains low until the EINIT (end of initialization) instruction is executed. NMI 81 I Non-Maskable Interrupt Input. A high to low transition at this pin causes the CPU to vector to the NMI trap routine. When the PWRDN (power down) instruction is executed, the NMI pin must be low in order to force the C163-L to go into power down mode. If NMI is high, when PWRDN is executed, the part will continue to run in normal mode. If not used, pin NMI should be pulled high externally. Pin Definitions and Functions (cont’d) Symbol Pin Numb. TQFP Input Out- put Function

11Aug98@14:48h Intermediate Version Semiconductor Group 7 1998-08 C163-L P6.0 P6.1 P6.2 P6.3 P6.4 P6.5 P6.6 P6.7 IO O O O O O I I/O O Port 6 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. Port 6 outputs can be configured as push/pull or open drain drivers. The Port 6 pins also serve as bus interface signals: CS0 Chip Select 0 Output CS1 Chip Select 1 Output CS2 Chip Select 2 Output CS3 Chip Select 3 Output CS4 Chip Select 4 Output HOLD External Master Hold Request Input HLDA Hold Acknowledge Output or Input (Master mode: O, Slave mode: I) BREQ Bus Request Output P2.8 P2.9 P2.10 P2.11 P2.12 P2.13 P2.14 P2.15 IO I I I I I I I I Port 2 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. Port 2 outputs can be configured as push/pull or open drain drivers. The Port 2 pins also serve as fast external interrupt inputs: EX0IN Fast External Interrupt 0 Input EX1IN Fast External Interrupt 1 Input EX2IN Fast External Interrupt 2 Input EX3IN Fast External Interrupt 3 Input EX4IN Fast External Interrupt 4 Input EX5IN Fast External Interrupt 5 Input EX6IN Fast External Interrupt 6 Input EX7IN Fast External Interrupt 7 Input OWE 40 I Oscillator Watchdog Enable. This pin enables the PLL when high or disables it when low (e.g. to disable the OWD for testing purposes. An internal pullup device holds this input high if nothing is driving it. Note: The input voltage at pin OWE must not exceed 12.6 V. For 3 V operation pin OWE must be driven low. VDD 7, 28, 38, 49, 69, 78 - Digital Supply Voltage: + 5 V or +3 V during normal operation and idle mode. ≥ 2.5 V during power down mode VSS 4, 27, 39, 50, 70, 77 - Digital Ground. Pin Definitions and Functions (cont’d) Symbol Pin Numb. TQFP Input Out- put Function

11Aug98@14:48h Intermediate Version Semiconductor Group 8 1998-08 C163-L Functional Description The architecture of the C163-L combines advantages of both RISC and CISC processors and of advanced peripheral subsystems in a very well-balanced way. The following block diagram gives an overview of the different on-chip components and of the advanced, high bandwidth internal bus structure of the C163-L. Note: All time specifications refer to a CPU clock of 25/12 MHz for 5/3 V operation (see definition in the AC Characteristics section). Figure 3 Block Diagram PLL

11Aug98@14:48h Intermediate Version Semiconductor Group 9 1998-08 C163-L Memory Organization The memory space of the C163-L is configured in a Von Neumann architecture which means that code memory, data memory, registers and I/O ports are organized within the same linear address space which includes 16 MBytes. The entire memory space can be accessed bytewise or wordwise. Particular portions of the on-chip memory have additionally been made directly bit addressable. The C163-L is prepared to incorporate on-chip mask-programmable ROM, OTP or Flash memory for code or constant data. Currently no program memory is integrated.

1 KByte of on-chip RAM is provided as a storage for user defined variables, for the system stack,

general purpose register banks and even for code. A register bank can consist of up to 16 wordwide (R0 to R15) and/or bytewide (RL0, RH0, …, RL7, RH7) so-called General Purpose Registers (GPRs). 1024 bytes (2 * 512 bytes) of the address space are reserved for the Special Function Register areas (SFR space and ESFR space). SFRs are wordwide registers which are used for controlling and monitoring functions of the different on-chip units. Unused SFR addresses are reserved for other/future members of the C166 family. In order to meet the needs of designs where more memory is required than is provided on chip, up to 16 MBytes of external RAM and/or ROM can be connected to the microcontroller.

11Aug98@14:48h Intermediate Version Semiconductor Group 10 1998-08 C163-L External Bus Controller All of the external memory accesses are performed by a particular on-chip External Bus Controller (EBC). It can be programmed either to Single Chip Mode when no external memory is required, or to one of four different external memory access modes, which are as follows: – 16-/18-/20-/24-bit Addresses, 16-bit Data, Demultiplexed – 16-/18-/20-/24-bit Addresses, 16-bit Data, Multiplexed – 16-/18-/20-/24-bit Addresses, 8-bit Data, Multiplexed – 16-/18-/20-/24-bit Addresses, 8-bit Data, Demultiplexed In the demultiplexed bus modes, addresses are output on PORT1 and data is input/output on PORT0 or P0L, respectively. In the multiplexed bus modes both addresses and data use PORT0 for input/output. Important timing characteristics of the external bus interface (Memory Cycle Time, Memory Tri- State Time, Length of ALE and Read Write Delay) have been made programmable to allow the user the adaption of a wide range of different types of memories and external peripherals. In addition, up to 4 independent address windows may be defined (via register pairs ADDRSELx / BUSCONx) which allow to access different resources with different bus characteristics. These address windows are arranged hierarchically where BUSCON4 overrides BUSCON3 and BUSCON2 overrides BUSCON1. All accesses to locations not covered by these 4 address windows are controlled by BUSCON0. Up to 5 external CS signals (4 windows plus default) can be generated in order to save external glue logic. Access to very slow memories is supported via a particular ‘Ready’ function. A HOLD /HLDA protocol is available for bus arbitration and allows to share external resources with other bus masters. The bus arbitration is enabled by setting bit HLDEN in register SYSCON. After EBC. In Master Mode (default after reset) the HLDA pin is an output. By setting bit DP6.7 to ’1’ the Slave Mode is selected where pin HLDA is switched to input. This allows to directly connect the slave controller to another master controller without glue logic. For applications which require less than 16 MBytes of external memory space, this address space can be restricted to 1 MByte, 256 KByte or to 64 KByte. In this case Port 4 outputs four, two or no address lines at all. It outputs all 8 address lines, if an address space of 16 MBytes is used. Note: When the on-chip SSP Module is to be used the segment address output on Port 4 must be limited to 4 bits (ie. A19...A16) in order to enable the alternate function of the SSP interface pins.

11Aug98@14:48h Intermediate Version Semiconductor Group 11 1998-08 C163-L Central Processing Unit (CPU) The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit (ALU) and dedicated SFRs. Additional hardware has been spent for a separate multiply and divide unit, a bit-mask generator and a barrel shifter. Based on these hardware provisions, most of the C163-L’s instructions can be executed in just one machine cycle which requires 80 ns at 25-MHz CPU clock. For example, shift and rotate instructions are always processed during one machine cycle independent of the number of bits to be shifted. All multiple-cycle instructions have been optimized so that they can be executed very fast as well: branches in 2 cycles, a 16 × 16 bit multiplication in 5 cycles and a 32-/16 bit division in 10 cycles. Another pipeline optimization, the so-called ‘Jump Cache’, allows reducing the execution time of repeatedly performed jumps in a loop from 2 cycles to 1 cycle. Figure 4 CPU Block Diagram

11Aug98@14:48h Intermediate Version Semiconductor Group 12 1998-08 C163-L The CPU disposes of an actual register context consisting of up to 16 wordwide GPRs which are physically allocated within the on-chip RAM area. A Context Pointer (CP) register determines the base address of the active register bank to be accessed by the CPU at a time. The number of register banks is only restricted by the available internal RAM space. For easy parameter passing, a register bank may overlap others. A system stack of up to 512 words is provided as a storage for temporary data. The system stack is allocated in the on-chip RAM area, and it is accessed by the CPU via the stack pointer (SP) register. Two separate SFRs, STKOV and STKUN, are implicitly compared against the stack pointer value upon each stack access for the detection of a stack overflow or underflow. The high performance offered by the hardware implementation of the CPU can efficiently be utilized by a programmer via the highly efficient C163-L instruction set which includes the following instruction classes: – Arithmetic Instructions – Logical Instructions – Boolean Bit Manipulation Instructions – Compare and Loop Control Instructions – Shift and Rotate Instructions – Prioritize Instruction – Data Movement Instructions – System Stack Instructions – Jump and Call Instructions – Return Instructions – System Control Instructions – Miscellaneous Instructions The basic instruction length is either 2 or 4 bytes. Possible operand types are bits, bytes and words. A variety of direct, indirect or immediate addressing modes are provided to specify the required operands.

11Aug98@14:48h Intermediate Version Semiconductor Group 13 1998-08 C163-L Interrupt System With an interrupt response time within a range from just 200 ns to 480 ns (in case of internal program execution), the C163-L is capable of reacting very fast to the occurence of non- deterministic events. The architecture of the C163-L supports several mechanisms for fast and flexible response to service requests that can be generated from various sources internal or external to the microcontroller. Any of these interrupt requests can be programmed to being serviced by the Interrupt Controller or by the Peripheral Event Controller (PEC). In contrast to a standard interrupt service where the current program execution is suspended and a branch to the interrupt vector table is performed, just one cycle is ‘stolen’ from the current CPU activity to perform a PEC service. A PEC service implies a single byte or word data transfer between any two memory locations with an additional increment of either the PEC source or the destination pointer. An individual PEC transfer counter is implicity decremented for each PEC service except when performing in the continuous transfer mode. When this counter reaches zero, a standard interrupt is performed to the corresponding source related vector location. PEC services are very well suited, for example, for supporting the transmission or reception of blocks of data. The C163- L has 8 PEC channels each of which offers such fast interrupt-driven data transfer capabilities. A separate control register which contains an interrupt request flag, an interrupt enable flag and an interrupt priority bitfield exists for each of the possible interrupt sources. Via its related register, each source can be programmed to one of sixteen interrupt priority levels. Once having been accepted by the CPU, an interrupt service can only be interrupted by a higher prioritized service request. For the standard interrupt processing, each of the possible interrupt sources has a dedicated vector location. Fast external interrupt inputs are provided to service external interrupts with high precision requirements. These fast interrupt inputs feature programmable edge detection (rising edge, falling edge or both edges). Software interrupts are supported by means of the ‘TRAP’ instruction in combination with an individual trap (interrupt) number.

11Aug98@14:48h Intermediate Version Semiconductor Group 14 1998-08 C163-L The following table shows all of the possible C163-L interrupt sources and the corresponding hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers: Source of Interrupt or PEC Service Request Request Flag Enable Flag Interrupt Vector Vector Location Trap Number External Interrupt 0 CC8IR CC8IE CC8INT 00’0060H 18H External Interrupt 1 CC9IR CC9IE CC9INT 00’0064 H 19H External Interrupt 2 CC10IR CC10IE CC10INT 00’0068 H 1AH External Interrupt 3 CC11IR CC11IE CC11INT 00’006C H 1BH External Interrupt 4 CC12IR CC12IE CC12INT 00’0070 H 1C H External Interrupt 5 CC13IR CC13IE CC13INT 00’0074 H 1D H External Interrupt 6 CC14IR CC14IE CC14INT 00’0078 H 1EH External Interrupt 7 CC15IR CC15IE CC15INT 00’007C H 1FH GPT1 Timer 2 T2IR T2IE T2INT 00’0088 H 22H GPT1 Timer 3 T3IR T3IE T3INT 00’008C H 23H GPT1 Timer 4 T4IR T4IE T4INT 00’0090 H 24H GPT2 Timer 5 T5IR T5IE T5INT 00’0094 H 25H GPT2 Timer 6 T6IR T6IE T6INT 00’0098 H 26H GPT2 CAPREL Register CRIR CRIE CRINT 00’009C H 27H ASC0 Transmit S0TIR S0TIE S0TINT 00’00A8 H 2AH ASC0 Transmit Buffer S0TBIR S0TBIE S0TBINT 00’011C H 47H ASC0 Receive S0RIR S0RIE S0RINT 00’00AC H 2BH ASC0 Error S0EIR S0EIE S0EINT 00’00B0 H 2C H SSP Interrupt XP1IR XP1IE XP1INT 00’0104 H 41H PLL Unlock / OWD XP3IR XP3IE XP3INT 00’010C H 43H

11Aug98@14:48h Intermediate Version Semiconductor Group 15 1998-08 C163-L The C163-L also provides an excellent mechanism to identify and to process exceptions or error conditions that arise during run-time, so-called ‘Hardware Traps’. Hardware traps cause immediate non-maskable system reaction which is similar to a standard interrupt service (branching to a dedicated vector table location). The occurence of a hardware trap is additionally signified by an individual bit in the trap flag register (TFR). Except when another higher prioritized trap service is in progress, a hardware trap will interrupt any actual program execution. In turn, hardware trap services can normally not be interrupted by standard or PEC interrupts. The following table shows all of the possible exceptions or error conditions that can arise during run- time: Exception Condition Trap Flag Trap Vector Vector Location Trap Number Trap Priority Reset Functions: Hardware Reset Software Reset Watchdog Timer Overflow RESET RESET RESET 00’0000 H 00’0000H 00’0000H 00H 00H 00H III III III Class A Hardware Traps: Non-Maskable Interrupt Stack Overflow Stack Underflow NMI STKOF STKUF NMITRAP STOTRAP STUTRAP 00’0008 H 00’0010H 00’0018H 02H 04H 06H II II II Class B Hardware Traps: Undefined Opcode Protected Instruction Fault Illegal Word Operand Access Illegal Instruction Access Illegal External Bus Access UNDOPC PRTFLT ILLOPA ILLINA ILLBUS BTRAP BTRAP BTRAP BTRAP BTRAP 00’0028 H 00’0028H 00’0028H 00’0028H 00’0028H 0AH 0AH 0AH 0AH 0AH I I I I I Reserved [2C H – 3CH ][ 0 BH – 0FH ] Software Traps TRAP Instruction Any [00’0000H – 00’01FCH ] in steps of 4 H Any [00 H – 7FH ] Current CPU Priority

11Aug98@14:48h Intermediate Version Semiconductor Group 16 1998-08 C163-L General Purpose Timer (GPT) Unit The GPT unit represents a very flexible multifunctional timer/counter structure which may be used for many different time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or pulse multiplication. The GPT unit incorporates five 16-bit timers which are organized in two separate modules, GPT1 and GPT2. Each timer in each module may operate independently in a number of different modes, or may be concatenated with another timer of the same module. Each of the three timers T2, T3, T4 of module GPT1 can be configured individually for one of three basic modes of operation, which are Timer, Gated Timer, and Counter Mode. In Timer Mode, the input clock for a timer is derived from the CPU clock, divided by a programmable prescaler, while Counter Mode allows a timer to be clocked in reference to external events. Pulse width or duty cycle measurement is supported in Gated Timer Mode, where the operation of a timer is controlled by the ‘gate’ level on an external input pin. For these purposes, each timer has one associated port pin (TxIN) which serves as gate or clock input. The maximum resolution of the timers in module GPT1 is 320 ns (@ 25 MHz CPU clock). The count direction (up/down) for each timer is programmable by software or may additionally be altered dynamically by an external signal on a port pin (TxEUD) to facilitate e. g. position tracking. Figure 5 Block Diagram of GPT1 Timer T3 has an output toggle latch (T3OTL) which changes its state on each timer over-flow/ underflow. The state of this latch may be output on port a pin (T3OUT) e.g. for time out monitoring of external hardware components, or may be used internally to clock timers T2 and T4 for measuring long time periods with high resolution.

11Aug98@14:48h Intermediate Version Semiconductor Group 17 1998-08 C163-L In addition to their basic operating modes, timers T2 and T4 may be configured as reload or capture registers for timer T3. When used as capture or reload registers, timers T2 and T4 are stopped. The contents of timer T3 is captured into T2 or T4 in response to a signal at their associated input pins (TxIN). Timer T3 is reloaded with the contents of T2 or T4 triggered either by an external signal or by a selectable state transition of its toggle latch T3OTL. When both T2 and T4 are configured to alternately reload T3 on opposite state transitions of T3OTL with the low and high times of a PWM signal, this signal can be constantly generated without software intervention. Figure 6 Block Diagram of GPT2 With its maximum resolution of 160 ns (@ 25 MHz), the GPT2 module provides precise event control and time measurement. It includes two timers (T5, T6) and a capture/reload register (CAPREL). Both timers can be clocked with an input clock which is derived from the CPU clock via a programmable prescaler or with external signals. The count direction (up/down) for each timer is programmable by software or may additionally be altered dynamically by an external signal on a port pin (TxEUD). Timer T6 has an output toggle latch (T6OTL) which changes its state on each timer overflow/underflow. Concatenation of the timers is supported via T6OTL. The state of this latch may be used to clock timer T5, or it may be output on a port pin (T6OUT). The overflows/underflows of timer T6 can additionally be used to cause a reload from the CAPREL register. The CAPREL register may capture the contents of timer T5 based on an external signal transition on the corresponding port pin (CAPIN), and timer T5 may optionally be cleared after the capture procedure. This allows absolute time differences to be measured or pulse multiplication to be performed without software overhead.

11Aug98@14:48h Intermediate Version Semiconductor Group 18 1998-08 C163-L Parallel Ports The C163-L provides up to 77 I/O lines which are organized into six input/output ports and one input port. All port lines are bit-addressable, and all input/output lines are individually (bit-wise) programmable as inputs or outputs via direction registers. The I/O ports are true bidirectional ports which are switched to high impedance state when configured as inputs. The output drivers of three I/O ports can be configured (pin by pin) for push/pull operation or open-drain operation via control registers. During the internal reset, all port pins are configured as inputs. All port lines have programmable alternate input or output functions associated with them. PORT0 and PORT1 may be used as address and data lines when accessing external memory, while Port 4 outputs the additional segment address bits A23/19/17...A16 in systems where segmentation is enabled to access more than 64 KBytes of memory. Port 6 provides optional bus arbitration signals (BREQ , HLDA, HOLD) and chip select signals. Port 3 includes alternate functions of timers, serial interfaces, the optional bus control signal BHE and the system clock output (CLKOUT). Port 5 is used for timer control signals. All port lines that are not used for these alternate functions may be used as general purpose I/O lines. Serial Channels Serial communication with other microcontrollers, processors, terminals or external peripheral components is provided by two serial interfaces with different functionality, an Asynchronous/ Synchronous Serial Channel (ASC0) and a Synchronous Serial Port (SSP). The ASC0 is upward compatible with the serial ports of the Siemens 8-bit microcontroller families and supports full-duplex asynchronous communication at up to 781 KBaud and half-duplex synchronous communication at up to 3.125 MBaud @ 25 MHz CPU clock. A dedicated baud rate generator allows to set up all standard baud rates without oscillator tuning. For transmission, reception and error handling 4 separate interrupt vectors are provided. In asynchronous mode, 8- or 9-bit data frames are transmitted or received, preceded by a start bit and terminated by one or two stop bits. For multiprocessor communication, a mechanism to distinguish address from data bytes has been included (8-bit data plus wake up bit mode). In synchronous mode, the ASC0 transmits or receives bytes (8 bits) synchronously to a shift clock which is generated by the ASC0. The ASC0 always shifts the LSB first. A loop back option is available for testing purposes. A number of optional hardware error detection capabilities has been included to increase the reliability of data transfers. A parity bit can automatically be generated on transmission or be checked on reception. Framing error detection allows to recognize data frames with missing stop bits. An overrun error will be generated, if the last character received has not been read out of the receive buffer register at the time the reception of a new character is complete. clock which is generated by the SSP. The SSP can start shifting with the LSB or with the MSB and allows to select shifting and latching clock edges as well as the clock polarity. Up to two chip select lines may be activated in order to direct data transfers to one or both of two peripheral devices. One general interrupt vector is provided for the SSP.

11Aug98@14:48h Intermediate Version Semiconductor Group 19 1998-08 C163-L Watchdog Timer The Watchdog Timer represents one of the fail-safe mechanisms which have been implemented to prevent the controller from malfunctioning for longer periods of time. The Watchdog Timer is always enabled after a reset of the chip, and can only be disabled in the time interval until the EINIT (end of initialization) instruction has been executed. Thus, the chip’s start-up procedure is always monitored. The software has to be designed to service the Watchdog Timer before it overflows. If, due to hardware or software related failures, the software fails to do so, the Watchdog Timer overflows and generates an internal hardware reset and pulls the RSTOUT pin low in order to allow external hardware components to be reset. The Watchdog Timer is a 16-bit timer, clocked with the system clock divided either by 2 or by 128. The high byte of the Watchdog Timer register can be set to a prespecified reload value (stored in WDTREL) in order to allow further variation of the monitored time interval. Each time it is serviced by the application software, the high byte of the Watchdog Timer is reloaded. Thus, time intervals between 20 µs and 336 ms can be monitored (@ 25 MHz). The default Watchdog Timer interval after reset is 5.24 ms (@ 25 MHz). Oscillator Watchdog During direct drive or prescaler operation the Oscillator Watchdog (OWD) monitors the clock signal generated by the on-chip oscillator (either with a crystal or via external clock drive). For this operation the PLL provides a clock signal which is used to supervise transitions on the oscillator clock. This PLL clock is independent from the XTAL1 clock. When the expected oscillator clock transitions are missing the OWD activates the PLL Unlock / OWD interrupt node and supplies the CPU with the PLL clock signal. Under these circumstances the PLL will oscillate with its basic frequency. A low level on pin OWE disables the PLL and the OWD’s interrupt output so the clock signal is derived from the oscillator clock in any case. Note: The CPU clock source is only switched back to the oscillator clock after a hardware reset. For 3 V operation pin OWE must always be low (OWD disabled) as the PLL cannot deliver an appropriate clock signal in this case. For 5 V operation pin OWE should only be pulled low (PLL disabled) if direct drive or prescaler operation is configured. All other configurations (PLL factors) result in direct drive operation.

11Aug98@14:48h Intermediate Version Semiconductor Group 20 1998-08 C163-L Instruction Set Summary The table below lists the instructions of the C163-L in a condensed way. The various addressing modes that can be used with a specific instruction, the operation of the instructions, parameters for conditional execution of instructions, and the opcodes for each instruction can be found in the “C16x Family Instruction Set Manual”. This document also provides a detailled description of each instruction. Instruction Set Summary Mnemonic Description Bytes ADD(B) Add word (byte) operands 2 / 4 ADDC(B) Add word (byte) operands with Carry 2 / 4 SUB(B) Subtract word (byte) operands 2 / 4 SUBC(B) Subtract word (byte) operands with Carry 2 / 4 MUL(U) (Un)Signed multiply direct GPR by direct GPR (16-16-bit) 2 DIV(U) (Un)Signed divide register MDL by direct GPR (16-/16-bit) 2 DIVL(U) (Un)Signed long divide reg. MD by direct GPR (32-/16-bit) 2 CPL(B) Complement direct word (byte) GPR 2 NEG(B) Negate direct word (byte) GPR 2 AND(B) Bitwise AND, (word/byte operands) 2 / 4 OR(B) Bitwise OR, (word/byte operands) 2 / 4 XOR(B) Bitwise XOR, (word/byte operands) 2 / 4 BCLR Clear direct bit 2 BSET Set direct bit 2 BMOV(N) Move (negated) direct bit to direct bit 4 BAND, BOR, BXOR AND/OR/XOR direct bit with direct bit 4 BCMP Compare direct bit to direct bit 4 BFLDH/L Bitwise modify masked high/low byte of bit-addressable direct word memory with immediate data CMP(B) Compare word (byte) operands 2 / 4 CMPD1/2 Compare word data to GPR and decrement GPR by 1/2 2 / 4 CMPI1/2 Compare word data to GPR and increment GPR by 1/2 2 / 4 PRIOR Determine number of shift cycles to normalize direct word GPR and store result in direct word GPR SHL / SHR Shift left/right direct word GPR 2 ROL / ROR Rotate left/right direct word GPR 2 ASHR Arithmetic (sign bit) shift right direct word GPR 2

11Aug98@14:48h Intermediate Version Semiconductor Group 21 1998-08 C163-L MOV(B) Move word (byte) data 2 / 4 MOVBS Move byte operand to word operand with sign extension 2 / 4 MOVBZ Move byte operand to word operand. with zero extension 2 / 4 JMPA, JMPI, JMPR Jump absolute/indirect/relative if condition is met 4 JMPS Jump absolute to a code segment 4 J(N)B Jump relative if direct bit is (not) set 4 JBC Jump relative and clear bit if direct bit is set 4 JNBS Jump relative and set bit if direct bit is not set 4 CALLA, CALLI, CALLR Call absolute/indirect/relative subroutine if condition is met 4 CALLS Call absolute subroutine in any code segment 4 PCALL Push direct word register onto system stack and call absolute subroutine TRAP Call interrupt service routine via immediate trap number 2 PUSH, POP Push/pop direct word register onto/from system stack 2 SCXT Push direct word register onto system stack und update register with word operand RET Return from intra-segment subroutine 2 RETS Return from inter-segment subroutine 2 RETP Return from intra-segment subroutine and pop direct word register from system stack RETI Return from interrupt service subroutine 2 SRST Software Reset 4 IDLE Enter Idle Mode 4 PWRDN Enter Power Down Mode (supposes NMI -pin being low) SRVWDT Service Watchdog Timer 4 DISWDT Disable Watchdog Timer 4 EINIT Signify End-of-Initialization on RSTOUT-pin 4 ATOMIC Begin ATOMIC sequence 2 EXTR Begin EXTended Register sequence 2 EXTP(R) Begin EXTended Page (and Register) sequence 2 / 4 EXTS(R) Begin EXTended Segment (and Register) sequence 2 / 4 NOP Null operation 2 Instruction Set Summary (cont’d) Mnemonic Description Bytes

11Aug98@14:48h Intermediate Version Semiconductor Group 22 1998-08 C163-L Special Function Registers Overview The following table lists all SFRs which are implemented in the C163-L in alphabetical order. Bit-addressable SFRs are marked with the letter “b” in column “Name”. SFRs within the Extended SFR-Space (ESFRs) are marked with the letter “E” in column “Physical Address”. Registers within on-chip X-Peripherals (SSP) are marked with the letter “X” in column “Physical Address”. An SFR can be specified via its individual mnemonic name. Depending on the selected addressing mode, an SFR can be accessed via its physical address (using the Data Page Pointers), or via its short 8-bit address (without using the Data Page Pointers). Special Function Registers Overview Name Physical Address 8-Bit Address Description Reset Value ADDRSEL1 FE18 H 0C H Address Select Register 1 0000 H ADDRSEL2 FE1A H 0D H Address Select Register 2 0000 H ADDRSEL3 FE1C H 0EH Address Select Register 3 0000 H ADDRSEL4 FE1E H 0FH Address Select Register 4 0000 H BUSCON0 b FF0C H 86H Bus Configuration Register 0 0XX0 H BUSCON1 b FF14H 8AH Bus Configuration Register 1 0000 H BUSCON2 b FF16H 8BH Bus Configuration Register 2 0000 H BUSCON3 b FF18H 8C H Bus Configuration Register 3 0000 H BUSCON4 b FF1A H 8D H Bus Configuration Register 4 0000 H CAPREL FE4A H 25H GPT2 Capture/Reload Register 0000 H CC8IC b FF88H C4 H EX0IN Interrupt Control Register 0000 H CC9IC b FF8A H C5 H EX1IN Interrupt Control Register 0000 H CC10IC b FF8C H C6 H EX2IN Interrupt Control Register 0000 H CC11IC b FF8E H C7 H EX3IN Interrupt Control Register 0000 H CC12IC b FF90H C8 H EX4IN Interrupt Control Register 0000 H CC13IC b FF92H C9 H EX5IN Interrupt Control Register 0000 H CC14IC b FF94H CA H EX6IN Interrupt Control Register 0000 H CC15IC b FF96H CB H EX7IN Interrupt Control Register 0000 H CP FE10 H 08H CPU Context Pointer Register FC00 H CRIC b FF6A H B5H GPT2 CAPREL Interrupt Control Register 0000 H CSP FE08 H 04H CPU Code Segment Pointer Register (read only) 0000H

11Aug98@14:48h Intermediate Version Semiconductor Group 23 1998-08 C163-L DP0L b F100H E 80H P0L Direction Control Register 00 H DP0H b F102H E 81H P0H Direction Control Register 00 H DP1L b F104H E 82H P1L Direction Control Register 00 H DP1H b F106H E 83H P1H Direction Control Register 00 H DP2 b FFC2 H E1H Port 2 Direction Control Register 0000 H DP3 b FFC6 H E3H Port 3 Direction Control Register 0000 H DP4 b FFCA H E5H Port 4 Direction Control Register 00 H DP6 b FFCE H E7H Port 6 Direction Control Register 00 H DPP0 FE00 H 00H CPU Data Page Pointer 0 Register (10 bits) 0000H DPP1 FE02 H 01H CPU Data Page Pointer 1 Register (10 bits) 0001H DPP2 FE04 H 02H CPU Data Page Pointer 2 Register (10 bits) 0002H DPP3 FE06 H 03H CPU Data Page Pointer 3 Register (10 bits) 0003H EXICON b F1C0 H E E0H External Interrupt Control Register 0000 H MDC b FF0E H 87H CPU Multiply Divide Control Register 0000 H MDH FE0C H 06H CPU Multiply Divide Register – High Word 0000H MDL FE0E H 07H CPU Multiply Divide Register – Low Word 0000 H ODP2 b F1C2 H E E1H Port 2 Open Drain Control Register 0000 H ODP3 b F1C6 H E E3H Port 3 Open Drain Control Register 0000 H ODP6 b F1CE H E E7H Port 6 Open Drain Control Register 00 H ONES FF1E H 8FH Constant Value 1’s Register (read only) FFFF H P0L b FF00H 80H Port 0 Low Register (Lower half of PORT0) 00H P0H b FF02H 81H Port 0 High Register (Upper half of PORT0) 00H P1L b FF04H 82H Port 1 Low Register (Lower half of PORT1) 00H P1H b FF06H 83H Port 1 High Register (Upper half of PORT1) 00H P2 b FFC0 H E0H Port 2 Register 0000 H P3 b FFC4 H E2H Port 3 Register 0000 H P4 b FFC8 H E4H Port 4 Register (8 bits) 00 H P5 b FFA2 H D1 H Port 5 Register (read only) XXXX H Special Function Registers Overview (cont’d) Name Physical Address 8-Bit Address Description Reset Value

11Aug98@14:48h Intermediate Version Semiconductor Group 24 1998-08 C163-L P6 b FFCC H E6H Port 6 Register (8 bits) 00 H PECC0 FEC0 H 60H PEC Channel 0 Control Register 0000 H PECC1 FEC2 H 61H PEC Channel 1 Control Register 0000 H PECC2 FEC4 H 62H PEC Channel 2 Control Register 0000 H PECC3 FEC6 H 63H PEC Channel 3 Control Register 0000 H PECC4 FEC8 H 64H PEC Channel 4 Control Register 0000 H PECC5 FECA H 65H PEC Channel 5 Control Register 0000 H PECC6 FECC H 66H PEC Channel 6 Control Register 0000 H PECC7 FECE H 67H PEC Channel 7 Control Register 0000 H PSW b FF10H 88H CPU Program Status Word 0000 H RP0H b F108H E 84H System Startup Configuration Register (Rd. only) XXH S0BG FEB4 H 5AH Serial Channel 0 Baud Rate Generator Reload Register 0000H S0CON b FFB0 H D8 H Serial Channel 0 Control Register 0000 H S0EIC b FF70H B8H Serial Channel 0 Error Interrupt Control Register 0000H S0RBUF FEB2 H 59H Serial Channel 0 Receive Buffer Register (read only) XX H S0RIC b FF6E H B7H Serial Channel 0 Receive Interrupt Control Register 0000H S0TBIC b F19C H E CE H Serial Channel 0 Transmit Buffer Interrupt Control Register 0000H S0TBUF FEB0 H 58H Serial Channel 0 Transmit Buffer Register (write only) 00H S0TIC b FF6C H B6H Serial Channel 0 Transmit Interrupt Control Register 0000H SP FE12 H 09H CPU System Stack Pointer Register FC00 H SSPCON0 EF00 H X --- SSP Control Register 0 0000 H SSPCON1 EF02 H X --- SSP Control Register 1 0000 H SSPRTB EF04 H X --- SSP Receive/Transmit Buffer XXXX H SSPTBH EF06 H X --- SSP Transmit Buffer High XXXX H STKOV FE14 H 0AH CPU Stack Overflow Pointer Register FA00 H Special Function Registers Overview (cont’d) Name Physical Address 8-Bit Address Description Reset Value

11Aug98@14:48h Intermediate Version Semiconductor Group 25 1998-08 C163-L 1) The system configuration is selected during reset. 2) Bit WDTR indicates a watchdog timer triggered reset. STKUN FE16 H 0BH CPU Stack Underflow Pointer Register FC00 H SYSCON b FF12H 89H CPU System Configuration Register 0XX0 H T2 FE40 H 20H GPT1 Timer 2 Register 0000 H T2CON b FF40H A0H GPT1 Timer 2 Control Register 0000 H T2IC b FF60H B0H GPT1 Timer 2 Interrupt Control Register 0000H T3 FE42 H 21H GPT1 Timer 3 Register 0000 H T3CON b FF42H A1H GPT1 Timer 3 Control Register 0000 H T3IC b FF62H B1H GPT1 Timer 3 Interrupt Control Register 0000 H T4 FE44 H 22H GPT1 Timer 4 Register 0000 H T4CON b FF44H A2H GPT1 Timer 4 Control Register 0000 H T4IC b FF64H B2H GPT1 Timer 4 Interrupt Control Register 0000 H T5 FE46 H 23H GPT2 Timer 5 Register 0000 H T5CON b FF46H A3H GPT2 Timer 5 Control Register 0000 H T5IC b FF66H B3H GPT2 Timer 5 Interrupt Control Register 0000 H T6 FE48 H 24H GPT2 Timer 6 Register 0000 H T6CON b FF48H A4H GPT2 Timer 6 Control Register 0000 H T6IC b FF68H B4H GPT2 Timer 6 Interrupt Control Register 0000 H TFR b FFAC H D6 H Trap Flag Register 0000 H WDT FEAE H 57H Watchdog Timer Register (read only) 0000 H WDTCON FFAE H D7 H Watchdog Timer Control Register 000X H XP1IC b F18E H E C7 H SSP Interrupt Control Register 0000 H XP3IC b F19E H E CF H PLL/OWD Interrupt Control Register 0000 H ZEROS b FF1C H 8EH Constant Value 0’s Register (read only) 0000 H Special Function Registers Overview (cont’d) Name Physical Address 8-Bit Address Description Reset Value

11Aug98@14:48h Intermediate Version Semiconductor Group 26 1998-08 C163-L Absolute Maximum Ratings Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During absolute maximum rating overload conditions ( VIN>VDD or VIN<VSS ) the voltage on VDD pins with respect to ground (VSS ) must not exceed the values defined by the absolute maximum ratings. Parameter Symbol Limit Values Unit Notes min. max. Storage temperature TST -65 150 °C Voltage on VDD pins with respect to ground (VSS ) VDD -0.5 6.5 V Voltage on any pin with respect to ground (VSS ) VIN -0.5 VDD +0.5 V Input current on any pin during overload condition -10 10 mA Absolute sum of all input currents during overload condition - |100| mA Power dissipation PDISS - 1.5 W

11Aug98@14:48h Intermediate Version Semiconductor Group 27 1998-08 C163-L Operating Conditions The following operating conditions must not be exceeded in order to ensure correct operation of the C163-L. All parameters specified in the following sections refer to these operating conditions, unless otherwise noticed. Note: Operation at reduced supply voltage is defined for the 25 MHz devices (SA*-C163L25F) only. Parameter Interpretation The parameters listed in the following partly represent the characteristics of the C163-L and partly its demands on the system. To aid in interpreting the parameters right, when evaluating them for a design, they are marked in column “Symbol”: CC (C ontroller C haracteristics): The logic of the C163-L will provide signals with the respective timing characteristics. SR (System R equirement): The external system must provide signals with the respective timing characteristics to the C163-L. 1) Overload conditions occur if the standard operatings conditions are exceeded, ie. the voltage on any pin exceeds the specified range (ie. VOV >V DD +0.5V, except pin OWE, or VOV <V SS -0.5V). The absolute sum of input overload currents on all port pins may not exceed 50 mA . The supply voltage must remain within the specified limits. 2) Not 100% tested, guaranteed by design characterization. Parameter Symbol Limit Values Unit Notes min. max. Digital supply voltage VDD 4.5 5.5 V Active mode, fCPUmax = 25 MHz 2.5 5.5 V PowerDown mode Reduced digital supply voltage VDD 2.7 3.6 V Active mode, fCPUmax = 12 MHz Digital ground voltage VSS 0 V Reference voltage Overload current IOV - ±5 mA Per pin 1) 2) Absolute sum of overload currents Σ|IOV |- 5 0 m A Ambient temperature TA 0 70 °C SAB-C163-L... -40 85 °C SAF-C163-L...

11Aug98@14:48h Intermediate Version Semiconductor Group 28 1998-08 C163-L DC Characteristics (Standard Supply Voltage Range) (Operating Conditions apply) Parameter Symbol Limit Values Unit Test Condition min. max. Input low voltage VIL SR – 0.5 0.2 VDD – 0.1 Input high voltage (all except RSTIN and XTAL1) VIH SR 0.2 VDD + 0.9 VDD + 0.5 V – Input high voltage RSTIN VIH1 SR 0.6 VDD VDD + 0.5 V – Input high voltage XTAL1 VIH2 SR 0.7 VDD VDD + 0.5 V – Output low voltage (PORT0, PORT1, Port 4, ALE, RD, WR , BHE, CLKOUT, RSTOUT ) VOL CC – 0.45 V IOL = 2.4 mA Output low voltage (all other outputs) VOL1 CC – 0.45 V IOL1 = 1.6 mA Output high voltage (PORT0, PORT1, Port 4, ALE, RD, WR , BHE, CLKOUT, RSTOUT ) VOH CC 0.9 VDD 2.4 V V IOH = – 500 µA IOH = – 2.4 mA Output high voltage 1) (all other outputs) VOH1 CC 0.9 VDD 2.4 V IOH = – 250 µA IOH = – 1.6 mA Input leakage current (Port 5)IOZ1 CC – ±200 nA 0.45 V < VIN < VDD Input leakage current (all other)IOZ2 CC – ±500 nA 0.45 V < VIN < VDD RSTIN pullup resistor RRST CC 50 250 k Ω – Read/Write inactive current 2) IRWH 3) –- 4 0 µA VOUT = 2.4 V Read/Write active current 2) IRWL 4) -500 – µA VOUT = VOLmax ALE inactive current 2) IALEL 3) –4 0 µA VOUT = VOLmax ALE active current 2) IALEH 4) 500 – µA VOUT = 2.4 V Port 6 inactive current 2) IP6H 3) –- 4 0 µA VOUT = 2.4 V Port 6 active current 2) IP6L 4) -500 – µA VOUT = VOL1max PORT0 configuration current 2) IP0H 3) –- 1 0 µA VIN = VIHmin IP0L 4) -100 – µA VIN = VILmax XTAL1 input current IIL CC – ±20 µA0 V < VIN < VDD Pin capacitance 5) (digital inputs/outputs) C IO CC – 10 pF f = 1 MHz TA = 25 °C Power supply current (at 5 V supply voltage) IDD5 – 10 + 3.5 * fCPU mA RSTIN = VIL2 fCPU in [MHz] 6)

11Aug98@14:48h Intermediate Version Semiconductor Group 29 1998-08 C163-L 1) This specification is not valid for outputs which are switched to open drain mode. In this case the respective output will float and the voltage results from the external circuitry. 2) This specification is only valid during Reset, or during Hold- or Adapt-mode. Port 6 pins are only affected, if they are used for CS output and the open drain function is not enabled. 3) The maximum current may be drawn while the respective signal line remains inactive. 4) The minimum current must be drawn in order to drive the respective signal line active. 5) Not 100% tested, guaranteed by design characterization. 6) The supply current is a function of the operating frequency. This dependency is illustrated in the figure below. These parameters are tested at VDDmax and maximum CPU clock with all outputs disconnected and all inputs at VIL or VIH. 7) This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0 V to 0.1 V or at VDD – 0.1 V to VDD , VREF = 0 V, all outputs (including pins configured as outputs) disconnected. Idle mode supply current (at 5 V supply voltage) IID5 –2 + 1.1 * fCPU mA RSTIN = VIH1 fCPU in [MHz] 6) Power-down mode supply current (at 5 V supply voltage) IPD5 –5 0 µA VDD = VDDmax Parameter Symbol Limit Values Unit Test Condition min. max.

11Aug98@14:48h Intermediate Version Semiconductor Group 30 1998-08 C163-L DC Characteristics (Reduced Supply Voltage Range) (Operating Conditions apply) Parameter Symbol Limit Values Unit Test Condition min. max. Input low voltage VIL SR – 0.5 0.8 V – Input high voltage (all except RSTIN and XTAL1) VIH SR 1.8 VDD + 0.5 V – Input high voltage RSTIN VIH1 SR 0.6 VDD VDD + 0.5 V – Input high voltage XTAL1 VIH2 SR 0.7 VDD VDD + 0.5 V – Output low voltage (PORT0, PORT1, Port 4, ALE, RD, WR , BHE, CLKOUT, RSTOUT ) VOL CC – 0.45 V IOL = 1.6 mA Output low voltage (all other outputs) VOL1 CC – 0.45 V IOL1 = 1.0 mA Output high voltage (PORT0, PORT1, Port 4, ALE, RD, WR , BHE, CLKOUT, RSTOUT ) VOH CC 0.9 VDD –V IOH = – 500 µA Output high voltage 1) (all other outputs) VOH1 CC 0.9 VDD –V IOH = – 250 µA Input leakage current (Port 5)IOZ1 CC – ±200 nA 0.45 V < VIN < VDD Input leakage current (all other)IOZ2 CC – ±500 nA 0.45 V < VIN < VDD RSTIN pullup resistor RRST CC 50 250 k Ω – Read/Write inactive current 2) IRWH 3) –- 1 0 µA VOUT = 2.4 V Read/Write active current 2) IRWL 4) -500 – µA VOUT = VOLmax ALE inactive current 2) IALEL 3) –2 0 µA VOUT = VOLmax ALE active current 2) IALEH 4) 500 – µA VOUT = 2.4 V Port 6 inactive current 2) IP6H 3) –- 1 0 µA VOUT = 2.4 V Port 6 active current 2) IP6L 4) -500 – µA VOUT = VOL1max PORT0 configuration current 2) IP0H 3) –- 5 µA VIN = VIHmin IP0L 4) -100 – µA VIN = VILmax XTAL1 input current IIL CC – ±20 µA0 V < VIN < VDD Pin capacitance 5) (digital inputs/outputs) C IO CC – 10 pF f = 1 MHz TA = 25 °C Power supply current (at 3 V supply voltage) IDD3 – 10 + 1.5 * fCPU mA RSTIN = VIL2 fCPU in [MHz] 6)

11Aug98@14:48h Intermediate Version Semiconductor Group 31 1998-08 C163-L 1) This specification is not valid for outputs which are switched to open drain mode. In this case the respective output will float and the voltage results from the external circuitry. 2) This specification is only valid during Reset, or during Hold- or Adapt-mode. Port 6 pins are only affected, if they are used for CS output and the open drain function is not enabled. 3) The maximum current may be drawn while the respective signal line remains inactive. 4) The minimum current must be drawn in order to drive the respective signal line active. 5) Not 100% tested, guaranteed by design characterization. 6) The supply current is a function of the operating frequency. This dependency is illustrated in the figure below. These parameters are tested at VDDmax and maximum CPU clock with all outputs disconnected and all inputs at VIL or VIH. 7) This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0 V to 0.1 V or at VDD – 0.1 V to VDD , VREF = 0 V, all outputs (including pins configured as outputs) disconnected. Idle mode supply current (at 3 V supply voltage) IID3 –2 + 0.7 * fCPU mA RSTIN = VIH1 fCPU in [MHz] 6) Power-down mode supply current (at 3 V supply voltage) IPD3 –3 0 µA VDD = VDDmax Parameter Symbol Limit Values Unit Test Condition min. max.

11Aug98@14:48h Intermediate Version Semiconductor Group 32 1998-08 C163-L Figure 7 Supply/Idle Current as a Function of Operating Frequency I [mA] fCPU [MHz]5 10 15 25 100 IDD5max IID5max IDD5typ IID5typ IDD3max IDD3typ IID3max IID3typ

11Aug98@14:48h Intermediate Version Semiconductor Group 34 1998-08 C163-L AC Characteristics Definition of Internal Timing The internal operation of the C163-L is controlled by the internal CPU clock fCPU . Both edges of the CPU clock can trigger internal (eg. pipeline) or external (eg. bus cycles) operations. The specification of the external timing (AC Characteristics) therefore depends on the time between two consecutive edges of the CPU clock, called “TCL” (see figure below). Figure 10 Generation Mechanisms for the CPU Clock The CPU clock signal can be generated via different mechanisms. The duration of TCLs and their variation (and also the derived external timing) depends on the used mechanism to generate fCPU . This influence must be regarded when calculating the timings for the C163-L. Note: The example for PLL operation shown in the figure above refers to a PLL factor of 4. The used mechanism to generate the CPU clock is selected during reset via the logic levels on pins The table below associates the combinations of these three bits with the respective clock generation mode. TCL TCL TCL TCL fCPU fOSC fCPU fOSC Phase Locked Loop Operation Direct Clock Drive TCL TCL fCPU fOSC Prescaler Operation

11Aug98@14:48h Intermediate Version Semiconductor Group 35 1998-08 C163-L Prescaler Operation When pins P0.15-13 (P0H.7-5) equal ’001’ during reset the CPU clock is derived from the internal oscillator (input clock signal) by a 2:1 prescaler. The frequency of f CPU is half the frequency of fOSC and the high and low time of fCPU (ie. the duration of an individual TCL) is defined by the period of the input clock fOSC . The timings listed in the AC Characteristics that refer to TCLs therefore can be calculated using the period of fOSC for any TCL. Direct Drive When pins P0.15-13 (P0H.7-5) equal ’011’ during reset the on-chip phase locked loop is disabled and the CPU clock is directly driven from the internal oscillator with the input clock signal. The frequency of f CPU directly follows the frequency of fOSC so the high and low time of fCPU (ie. the duration of an individual TCL) is defined by the duty cycle of the input clock fOSC . The timings listed below that refer to TCLs therefore must be calculated using the minimum TCL that is possible under the respective circumstances. This minimum value can be calculated via the following formula: TCL min = 1/fOSC * DCmin (DC = duty cycle) For two consecutive TCLs the deviation caused by the duty cycle of fOSC is compensated so the duration of 2TCL is always 1/fOSC . The minimum value TCLmin therefore has to be used only once for timings that require an odd number of TCLs (1,3,...). Timings that require an even number of TCLs (2,4,...) may use the formula 2TCL = 1/fOSC . Note: The address float timings in Multiplexed bus mode (t11 and t45) use the maximum duration of TCL (TCLmax = 1/fOSC * DCmax ) instead of TCLmin. 1) The external clock input range refers to a CPU clock range of 10...25 MHz. 2) The maximum frequency depends on the duty cycle of the external clock signal. Direct drive is also selected instead of PLL operation if pin OWE = ’0’ in such a case. C163-L Clock Generation Modes P0.15-13 (P0H.7-5) CPU Frequency fCPU = fOSC * F External Clock Input Range 1) Notes 111 fOSC * 4 2.5 to 6.25 MHz Default configuration 110 fOSC * 3 3.33 to 8.33 MHz 101 fOSC * 2 5 to 12.5 MHz 100 fOSC * 5 2 to 5 MHz 011 fOSC * 1 1 to 25 MHz Direct drive 2) 010 fOSC * 1.5 6.66 to 16.6 MHz 001 fOSC / 2 2 to 50 MHz CPU clock via prescaler 000 fOSC * 2.5 4 to 10 MHz

11Aug98@14:48h Intermediate Version Semiconductor Group 36 1998-08 C163-L Phase Locked Loop For all other combinations of pins P0.15-13 (P0H.7-5) during reset the on-chip phase locked loop is enabled and provides the CPU clock (see table above). The PLL multiplies the input frequency by the factor F which is selected via the combination of pins P0.15-13 (i.e. fCPU = fOSC * F). With every F’th transition of fOSC the PLL circuit synchronizes the CPU clock to the input clock. This synchronization is done smoothely, i.e. the CPU clock frequency does not change abruptly. Due to this adaptation to the input clock the frequency of fCPU is constantly adjusted so it is locked to fOSC . The slight variation causes a jitter of fCPU which also effects the duration of individual TCLs. The timings listed in the AC Characteristics that refer to TCLs therefore must be calculated using the minimum TCL that is possible under the respective circumstances. The actual minimum value for TCL depends on the jitter of the PLL. As the PLL is constantly adjusting its output frequency so it corresponds to the applied input frequency (crystal or oscillator) the relative deviation for periods of more than one TCL is lower than for one single TCL (see formula and figure below). For a period of N * TCL the minimum value is computed using the corresponding deviation DN : (N * TCL)min = N * TCLNOM - DN D N [ns] = ±(13.3 + N *6.3) / fCPU [MHz], where N = number of consecutive TCLs and 1 ≤ N ≤ 40. and (3TCL)min = 3TCLNOM - 1.288 ns = 58.7 ns (@ fCPU = 25 MHz). This is especially important for bus cycles using waitstates and e.g. for the operation of timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter is neglectible. Note: For all periods longer than 40 TCL the N=40 value can be used (see figure below). Figure 11 Approximated Maximum Accumulated PLL Jitter Note: The PLL only operates within the standard supply voltage range of VDD = 4.5 - 5.5 V. 40201051 ±10 ±20 N This approximated formula is valid for 1 ≤ N ≤ 40 and 10MHz ≤ fCPU ≤ 25MHz. ±26.5 Max.jitter DN [ns]

20 MHz

25 MHz

16 MHz

10 MHz

11Aug98@14:48h Intermediate Version Semiconductor Group 37 1998-08 C163-L AC Characteristics External Clock Drive XTAL1 (Standard Supply Voltage Range) (Operating Conditions apply) AC Characteristics External Clock Drive XTAL1 (Reduced Supply Voltage Range) (Operating Conditions apply) 1) The minimum and maximum oscillator periods for PLL operation depend on the selected CPU clock generation mode. Please see respective table above. 2) The clock input signal must reach the defined levels VIL and VIH2. 1) The clock input signal must reach the defined levels VIL and VIH2. Parameter Symbol Direct Drive 1:1 Prescaler 2:1 PLL 1:N Unit Oscillator period tOSC SR 40 1000 20 500 60 1) 500 1) ns High time t1 SR 18 2) –6 2) – 10 2) –n s Low time t2 SR 18 2) –6 2) – 10 2) –n s Rise time t3 SR – 10 2) –6 2) – 10 2) ns Fall time t4 SR – 10 2) –6 2) – 10 2) ns Parameter Symbol Direct Drive 1:1 Prescaler 2:1 PLL 1:N Unit Oscillator period tOSC SR 83 1000 42 500 – – ns High time t1 SR 36 1) – 10 1) –––n s Low time t2 SR 36 1) – 10 1) –––n s Rise time t3 SR – 10 1) –6 1) ––n s Fall time t4 SR – 10 1) –6 1) ––n s

11Aug98@14:48h Intermediate Version Semiconductor Group 38 1998-08 C163-L Figure 12 External Clock Drive XTAL1 Memory Cycle Variables The timing tables below use three variables which are derived from the BUSCONx registers and represent the special characteristics of the programmed memory cycle. The following table describes, how these variables are to be computed. Description Symbol Values ALE Extension tA TCL * <ALECTL> Memory Cycle Time Waitstates tC 2TCL * (15 - <MCTC>) Memory Tristate Time tF 2TCL * (1 - <MTTC>)

11Aug98@14:48h Intermediate Version Semiconductor Group 39 1998-08 C163-L AC Characteristics Multiplexed Bus (Standard Supply Voltage Range) (Operating Conditions apply, C L = 100 pF) ALE cycle time = 6 TCL + 2tA + tC + tF (120 ns at 25 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock = 25 MHz Variable CPU Clock 1 / 2TCL = 1 to 25 MHz Unit min. max. min. max. ALE high time t5 CC 10 + tA – TCL - 10 + tA –n s Address setup to ALE t6 CC 4 + tA – TCL - 16 + tA –n s Address hold after ALE t7 CC 10 + tA – TCL - 10 + tA –n s ALE falling edge to RD, WR (with RW-delay) t8 CC 10 + tA – TCL - 10 + tA –n s ALE falling edge to RD, WR (no RW-delay) t9 CC -10 + tA – -10 + tA –n s Address float after RD, WR (with RW-delay) t10 CC – 6 –6n s Address float after RD, WR (no RW-delay) t11 CC –2 6 – T C L + 6 n s RD , WR low time (with RW-delay) t12 CC 30 + tC – 2TCL - 10 + tC –n s RD , WR low time (no RW-delay) t13 CC 50 + tC – 3TCL - 10 + tC –n s RD to valid data in (with RW-delay) t14 SR – 20 + tC –2 T C L - 2 0 + tC ns RD to valid data in (no RW-delay) t15 SR – 40 + tC –3 T C L - 2 0 + tC ns ALE low to valid data int16 SR – 40 + tA + tC –3 T C L - 2 0 + tA + tC ns Address to valid data int17 SR – 50 + 2tA + tC –4 T C L - 3 0 + 2tA + tC ns Data hold after RD rising edge t18 S R 0 – 0–n s Data float after RD t19 SR – 26 + tF – 2TCL - 14 + tF ns Data valid to WR t22 CC 20 + tC – 2TCL - 20 + tC –n s Data hold after WR t23 CC 26 + tF – 2TCL - 14 + tF –n s ALE rising edge after RD, WR t25 CC 26 + tF – 2TCL - 14 + tF –n s

11Aug98@14:48h Intermediate Version Semiconductor Group 40 1998-08 C163-L Address hold after RD, WR t27 CC 26 + tF – 2TCL - 14 + tF –n s ALE falling edge to CS t38 CC -4 - tA 10 - tA -4 - tA 10 - tA ns CS low to Valid Data Int39 SR – 40 + tC + 2tA –3 T C L - 2 0 + tC + 2tA ns CS hold after RD, WR t40 CC 46 + tF – 3TCL - 14 + tF –n s ALE fall. edge to RdCS, WrCS (with RW delay) t42 CC 16 + tA – TCL - 4 + tA –n s ALE fall. edge to RdCS, WrCS (no RW delay) t43 CC -4 + tA –- 4 + tA –n s Address float after RdCS, WrCS (with RW delay) t44 C C – 0 –0n s Address float after RdCS, WrCS (no RW delay) t45 CC – 20 – TCL ns RdCS to Valid Data In (with RW delay) t46 SR – 16 + tC –2 T C L - 2 4 + tC ns RdCS to Valid Data In (no RW delay) t47 SR – 36 + tC –3 T C L - 2 4 + tC ns RdCS , WrCS Low Time (with RW delay) t48 CC 30 + tC – 2TCL - 10 + tC –n s RdCS , WrCS Low Time (no RW delay) t49 CC 50 + tC – 3TCL - 10 + tC –n s Data valid to WrCS t50 CC 26 + tC – 2TCL - 14 + tC –n s Data hold after RdCS t51 S R 0 – 0–n s Data float after RdCS t52 SR – 20 + tF – 2TCL - 20 + tF ns Address hold after RdCS , WrCS t54 CC 20 + tF – 2TCL - 20 + tF –n s Data hold after WrCS t56 CC 20 + tF – 2TCL - 20 + tF –n s Parameter Symbol Max. CPU Clock = 25 MHz Variable CPU Clock 1 / 2TCL = 1 to 25 MHz Unit min. max. min. max.

11Aug98@14:48h Intermediate Version Semiconductor Group 41 1998-08 C163-L AC Characteristics Multiplexed Bus (Reduced Supply Voltage Range) (Operating Conditions apply, C L = 100 pF) ALE cycle time = 6 TCL + 2tA + tC + tF (250 ns at 12 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock = 12 MHz Variable CPU Clock 1 / 2TCL = 1 to 12 MHz Unit min. max. min. max. ALE high time t5 CC 22 + tA – TCL - 20 + tA –n s Address setup to ALE t6 CC 12 + tA – TCL - 30 + tA –n s Address hold after ALE t7 CC 32 + tA – TCL - 10 + tA –n s ALE falling edge to RD, WR (with RW-delay) t8 CC 32 + tA – TCL - 10 + tA –n s ALE falling edge to RD, WR (no RW-delay) t9 CC -10 + tA – -10 + tA –n s Address float after RD, WR (with RW-delay) t10 CC – 6 –6n s Address float after RD, WR (no RW-delay) t11 CC –4 8 – T C L + 6 n s RD , WR low time (with RW-delay) t12 CC 63 + tC – 2TCL - 20 + tC –n s RD , WR low time (no RW-delay) t13 CC 105 + tC – 3TCL - 20 + tC –n s RD to valid data in (with RW-delay) t14 SR – 49 + tC –2 T C L - 3 4 + tC ns RD to valid data in (no RW-delay) t15 SR – 91 + tC –3 T C L - 3 4 + tC ns ALE low to valid data int16 SR – 93 + tA + tC –3 T C L - 3 2 + tA + tC ns Address to valid data int17 SR – 115 + 2tA + tC –4 T C L - 5 2 + 2tA + tC ns Data hold after RD rising edge t18 S R 0 – 0–n s Data float after RD t19 SR – 69 + tF – 2TCL - 14 + tF ns Data valid to WR t22 CC 47 + tC – 2TCL - 36 + tC –n s Data hold after WR t23 CC 69 + tF – 2TCL - 14 + tF –n s ALE rising edge after RD, WR t25 CC 69 + tF – 2TCL - 14 + tF –n s

11Aug98@14:48h Intermediate Version Semiconductor Group 42 1998-08 C163-L Address hold after RD, WR t27 CC 69 + tF – 2TCL - 14 + tF –n s ALE falling edge to CS t38 CC -10 - tA 10 - tA -10 - tA 10 - tA ns CS low to Valid Data Int39 SR – 89 + tC + 2tA –3 T C L - 3 6 + tC +2tA ns CS hold after RD, WR t40 CC 105 + tF – 3TCL - 20 + tF –n s ALE fall. edge to RdCS, WrCS (with RW delay) t42 CC 36 + tA – TCL - 6 + tA –n s ALE fall. edge to RdCS, WrCS (no RW delay) t43 CC -6 + tA –- 6 + tA –n s Address float after RdCS, WrCS (with RW delay) t44 C C – 0 –0n s Address float after RdCS, WrCS (no RW delay) t45 CC – 42 – TCL ns RdCS to Valid Data In (with RW delay) t46 SR – 45 + tC –2 T C L - 3 8 + tC ns RdCS to Valid Data In (no RW delay) t47 SR – 87 + tC –3 T C L - 3 8 + tC ns RdCS , WrCS Low Time (with RW delay) t48 CC 69 + tC – 2TCL - 14 + tC –n s RdCS , WrCS Low Time (no RW delay) t49 CC 111 + tC – 3TCL - 14 + tC –n s Data valid to WrCS t50 CC 53 + tC – 2TCL - 30 + tC –n s Data hold after RdCS t51 S R 0 – 0–n s Data float after RdCS t52 SR – 63 + tF – 2TCL - 20 + tF ns Address hold after RdCS , WrCS t54 CC 63 + tF – 2TCL - 20 + tF –n s Data hold after WrCS t56 CC 63 + tF – 2TCL - 20 + tF –n s Parameter Symbol Max. CPU Clock = 12 MHz Variable CPU Clock 1 / 2TCL = 1 to 12 MHz Unit min. max. min. max.

11Aug98@14:48h Intermediate Version Semiconductor Group 43 1998-08 C163-L Figure 13-1 External Memory Cycle: Multiplexed Bus, With Read/Write Delay, Normal ALE Data In Data OutAddress Address t38 t44 t10 Address ALE CSx A23-A16 (A15-A8) BHE BUS Read Cycle RD RdCSx BUS Write Cycle WR , WRL , WRH WrCSx t5 t16 t17 t6 t7 t39 t40 t25 t27 t18 t19 t14 t46 t12 t48 t10 t22 t23 t44 t12 t48 t42 t42 t50 t51 t54 t52 t56

11Aug98@14:48h Intermediate Version Semiconductor Group 44 1998-08 C163-L Figure 13-2 External Memory Cycle: Multiplexed Bus, With Read/Write Delay, Extended ALE Data OutAddress Data InAddress t38 t44 t10 Address ALE CSx A23-A16 (A15-A8) BHE BUS Read Cycle RD RdCSx BUS Write Cycle WR , WRL , WRH WrCSx t5 t16 t17 t6 t7 t39 t40 t25 t27 t18 t19 t14 t46 t12 t48 t10 t22 t23 t44 t12 t48 t42 t42 t50 t51 t54 t52 t56

11Aug98@14:48h Intermediate Version Semiconductor Group 45 1998-08 C163-L Figure 13-3 External Memory Cycle: Multiplexed Bus, No Read/Write Delay, Normal ALE Data OutAddress Address Data In t38 Address ALE CSx A23-A16 (A15-A8) BHE BUS Read Cycle RD RdCSx BUS Write Cycle WR , WRL , WRH WrCSx t5 t16 t17 t6 t7 t39 t40 t25 t27 t18 t19 t15 t47 t13 t49 t22 t23 t13 t49 t43 t43 t11 t45 t11 t45 t50 t51 t54 t52 t56

11Aug98@14:48h Intermediate Version Semiconductor Group 46 1998-08 C163-L Figure 13-4 External Memory Cycle: Multiplexed Bus, No Read/Write Delay, Extended ALE Data OutAddress Data InAddress t38 Address ALE CSx A23-A16 (A15-A8) BHE BUS Read Cycle RD RdCSx BUS Write Cycle WR , WRL , WRH WrCSx t5 t16 t17 t6 t7 t39 t40 t25 t27 t18 t19 t15 t47 t13 t49 t22 t23 t13 t49 t43 t43 t9 t11 t45 t11 t45 t50 t51 t54 t52 t56

11Aug98@14:48h Intermediate Version Semiconductor Group 47 1998-08 C163-L AC Characteristics Demultiplexed Bus (Standard Supply Voltage Range) (Operating Conditions apply, C L = 100 pF) ALE cycle time = 4 TCL + 2tA + tC + tF (80 ns at 25 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock = 25 MHz Variable CPU Clock 1 / 2TCL = 1 to 25 MHz Unit min. max. min. max. ALE high time t5 CC 10 + tA – TCL - 10 + tA –n s Address setup to ALE t6 CC 4 + tA – TCL - 16 + tA –n s ALE falling edge to RD, WR (with RW-delay) t8 CC 10 + tA –T C L - 1 0 + tA –n s ALE falling edge to RD, WR (no RW-delay) t9 CC -10 + tA –- 1 0 + tA –n s RD , WR low time (with RW-delay) t12 CC 30 + tC – 2TCL - 10 + tC –n s RD , WR low time (no RW-delay) t13 CC 50 + tC – 3TCL - 10 + tC –n s RD to valid data in (with RW-delay) t14 SR – 20 + tC –2 T C L - 2 0 + tC ns RD to valid data in (no RW-delay) t15 SR – 40 + tC –3 T C L - 2 0 + tC ns ALE low to valid data int16 SR – 40 + tA + tC –3 T C L - 2 0 + tA + tC ns Address to valid data int17 SR – 50 + 2tA + tC –4 T C L - 3 0 + 2tA + tC ns Data hold after RD rising edge t18 S R 0 – 0–n s Data float after RD rising edge (with RW-delay 1)) t20 SR – 26 + tF –2 T C L - 1 4 + 2tA + tF 1) ns Data float after RD rising edge (no RW-delay 1)) t21 SR – 10 + tF –T C L - 1 0 + 2tA + tF 1) ns Data valid to WR t22 CC 20 + tC – 2TCL - 20 + tC –n s Data hold after WR t24 CC 10 + tF –T C L - 1 0 + tF –n s ALE rising edge after RD, WR t26 CC -10 + tF –- 1 0 + tF –n s Address hold after WR 2) t28 CC 0 + tF –0 + tF –n s ALE falling edge to CS t38 CC -4 - tA 10 - tA -4 - tA 10 - tA ns

11Aug98@14:48h Intermediate Version Semiconductor Group 48 1998-08 C163-L 1) RW-delay and tA refer to the next following bus cycle. 2) Read data are latched with the same clock edge that triggers the address change and the rising RD edge. Therefore address changes before the end of RD have no impact on read cycles. CS low to Valid Data Int39 SR –4 0 + tC + 2tA –3 T C L - 2 0 + tC +2tA ns CS hold after RD, WR t41 CC 6 + tF –T C L - 1 4 + tF –n s ALE falling edge to RdCS, WrCS (with RW-delay) t42 CC 16 + tA – TCL - 4 + tA –n s ALE falling edge to RdCS, WrCS (no RW-delay) t43 CC -4 + tA –- 4 + tA –n s RdCS to Valid Data In (with RW-delay) t46 SR – 16 + tC –2 T C L - 2 4 + tC ns RdCS to Valid Data In (no RW-delay) t47 SR – 36 + tC –3 T C L - 24 + tC ns RdCS , WrCS Low Time (with RW-delay) t48 CC 30 + tC – 2TCL - 10 + tC –n s RdCS , WrCS Low Time (no RW-delay) t49 CC 50 + tC – 3TCL - 10 + tC –n s Data valid to WrCS t50 CC 26 + tC – 2TCL - 14 + tC –n s Data hold after RdCS t51 S R 0 – 0–n s Data float after RdCS (with RW-delay) t53 SR – 20 + tF –2 T C L - 2 0 + tF ns Data float after RdCS (no RW-delay) t68 SR – 0 + tF –T C L - 2 0 + tF ns Address hold after RdCS , WrCS t55 CC -6 + tF –- 6 + tF –n s Data hold after WrCS t57 CC 6 + tF – TCL - 14 + tF –n s Parameter Symbol Max. CPU Clock = 25 MHz Variable CPU Clock 1 / 2TCL = 1 to 25 MHz Unit min. max. min. max.

11Aug98@14:48h Intermediate Version Semiconductor Group 49 1998-08 C163-L AC Characteristics Demultiplexed Bus (Reduced Supply Voltage Range) (Operating Conditions apply, C L = 100 pF) ALE cycle time = 4 TCL + 2tA + tC + tF (166.7 ns at 12 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock = 12 MHz Variable CPU Clock 1 / 2TCL = 1 to 12 MHz Unit min. max. min. max. ALE high time t5 CC 22 + tA – TCL - 20 + tA –n s Address setup to ALE t6 CC 12 + tA – TCL - 30 + tA –n s ALE falling edge to RD, WR (with RW-delay) t8 CC 32 + tA –T C L - 1 0 + tA –n s ALE falling edge to RD, WR (no RW-delay) t9 CC -10 + tA –- 1 0 + tA –n s RD , WR low time (with RW-delay) t12 CC 63 + tC – 2TCL - 20 + tC –n s RD , WR low time (no RW-delay) t13 CC 105 + tC – 3TCL - 20 + tC –n s RD to valid data in (with RW-delay) t14 SR – 49 + tC –2 T C L - 3 4 + tC ns RD to valid data in (no RW-delay) t15 SR – 91 + tC –3 T C L - 3 4 + tC ns ALE low to valid data int16 SR – 93 + tA + tC –3 T C L - 3 2 + tA + tC ns Address to valid data int17 SR – 115 + 2tA + tC –4 T C L - 5 2 + 2tA + tC ns Data hold after RD rising edge t18 S R 0 – 0–n s Data float after RD rising edge (with RW-delay 1)) t20 SR – 69 + tF –2 T C L - 1 4 + 2tA + tF 1) ns Data float after RD rising edge (no RW-delay 1)) t21 SR – 32 + tF –T C L - 1 0 + 2tA + tF 1) ns Data valid to WR t22 CC 47 + tC – 2TCL - 36 + tC –n s Data hold after WR t24 CC 32 + tF –T C L - 1 0 + tF –n s ALE rising edge after RD, WR t26 CC -12 + tF –- 1 2 + tF –n s Address hold after WR 2) t28 CC 0 + tF –0 + tF –n s ALE falling edge to CS t38 CC -10 - tA 10 - tA *) -10 - tA 10 - tA *) ns

11Aug98@14:48h Intermediate Version Semiconductor Group 50 1998-08 C163-L 1) RW-delay and tA refer to the next following bus cycle. 2) Read data are latched with the same clock edge that triggers the address change and the rising RD edge. Therefore address changes before the end of RD have no impact on read cycles. CS low to Valid Data Int39 SR –8 9 + tC + 2tA –3 T C L - 3 6 + tC +2tA ns CS hold after RD, WR t41 CC 22 + tF –T C L - 2 0 + tF –n s ALE falling edge to RdCS, WrCS (with RW-delay) t42 CC 36 + tA – TCL - 6 + tA –n s ALE falling edge to RdCS, WrCS (no RW-delay) t43 CC -6 + tA –- 6 + tA –n s RdCS to Valid Data In (with RW-delay) t46 SR – 45 + tC –2 T C L - 3 8 + tC ns RdCS to Valid Data In (no RW-delay) t47 SR – 87 + tC –3 T C L - 38 + tC ns RdCS , WrCS Low Time (with RW-delay) t48 CC 69 + tC – 2TCL - 14 + tC –n s RdCS , WrCS Low Time (no RW-delay) t49 CC 111 + tC – 3TCL - 14 + tC –n s Data valid to WrCS t50 CC 53 + tC – 2TCL - 30 + tC –n s Data hold after RdCS t51 S R 0 – 0–n s Data float after RdCS (with RW-delay) t53 SR – 63 + tF –2 T C L - 2 0 + tF ns Data float after RdCS (no RW-delay) t68 SR – 22 + tF –T C L - 2 0 + tF ns Address hold after RdCS , WrCS t55 CC -20 + tF – -20 + tF –n s Data hold after WrCS t57 CC 26 + tF – TCL - 16 + tF –n s Parameter Symbol Max. CPU Clock = 12 MHz Variable CPU Clock 1 / 2TCL = 1 to 12 MHz Unit min. max. min. max.

11Aug98@14:48h Intermediate Version Semiconductor Group 51 1998-08 C163-L Figure 14-1 External Memory Cycle: Demultiplexed Bus, With Read/Write Delay, Normal ALE Data Out Data In t38 Address ALE CSx A23-A16 A15-A0 BHE BUS (D15-D8) D7-D0 Read Cycle RD RdCSx Write Cycle WrCSx t5 t16 t17 t39 t41 t26 t28 t18 t20 t14 t46 t12 t48 t22 t24 t12 t48 t42 t42 t50 t51 t55 t53 t57 BUS (D15-D8) D7-D0 WR , WRL , WRH

11Aug98@14:48h Intermediate Version Semiconductor Group 52 1998-08 C163-L Figure 14-2 External Memory Cycle: Demultiplexed Bus, With Read/Write Delay, Extended ALE Data Out Data In t38 Address ALE CSx A23-A16 A15-A0 BHE Read Cycle RD RdCSx Write Cycle WrCSx t5 t16 t17 t39 t41 t26 t28 t18 t20 t14 t46 t12 t48 t22 t24 t12 t48 t42 t42 t50 t51 t55 t53 t57 BUS (D15-D8) D7-D0 BUS (D15-D8) D7-D0 WR , WRL , WRH

11Aug98@14:48h Intermediate Version Semiconductor Group 53 1998-08 C163-L Figure 14-3 External Memory Cycle: Demultiplexed Bus, No Read/Write Delay, Normal ALE Data Out Data In t38 Address ALE CSx A23-A16 A15-A0 BHE Read Cycle RD RdCSx Write Cycle WrCSx t5 t16 t17 t39 t41 t26 t28 t18 t21 t15 t47 t13 t49 t22 t24 t13 t49 t43 t43 t50 t51 t55 t68 t57 BUS (D15-D8) D7-D0 BUS (D15-D8) D7-D0 WR , WRL , WRH

11Aug98@14:48h Intermediate Version Semiconductor Group 54 1998-08 C163-L Figure 14-4 External Memory Cycle: Demultiplexed Bus, No Read/Write Delay, Extended ALE Data Out Data In t38 Address ALE CSx A23-A16 A15-A0 BHE Read Cycle RD RdCSx Write Cycle WR , WRL , WRH WrCSx t5 t16 t17 t39 t41 t26 t28 t18 t21 t15 t47 t13 t49 t22 t24 t13 t49 t43 t43 t50 t51 t55 t68 t57 BUS (D15-D8) D7-D0 BUS (D15-D8) D7-D0

11Aug98@14:48h Intermediate Version Semiconductor Group 55 1998-08 C163-L AC Characteristics CLKOUT and READY (Standard Supply Voltage Range) (Operating Conditions apply, C L = 100 pF) 1) These timings are given for test purposes only, in order to assure recognition at a specific clock edge. 2) Demultiplexed bus is the worst case. For multiplexed bus 2TCL are to be added to the maximum values. This adds even more time for deactivating READY. The 2tA and tC refer to the next following bus cycle, tF refers to the current bus cycle. Parameter Symbol Max. CPU Clock = 25 MHz Variable CPU Clock 1 / 2TCL = 1 to 25 MHz Unit min. max. min. max. CLKOUT cycle time t29 CC 40 40 2TCL 2TCL ns CLKOUT high time t30 CC 14 – TCL – 6 – ns CLKOUT low time t31 CC 10 – TCL – 10 – ns CLKOUT rise time t32 C C – 4 –4n s CLKOUT fall time t33 C C – 4 –4n s CLKOUT rising edge to ALE falling edge t34 CC 0 + tA 10 + tA 0 + tA 10 + tA ns Synchronous READY setup time to CLKOUT t35 SR 14 – 14 – ns Synchronous READY hold time after CLKOUT t36 S R 4 – 4–n s Asynchronous READY low time t37 SR 54 – 2TCL + 14 – ns Asynchronous READY setup time 1) t58 SR 14 – 14 – ns Asynchronous READY hold time 1) t59 SR 4 – 4–n s Async. READY hold time after RD, WR high (Demultiplexed Bus) 2) t60 SR 00 + 2tA + tC + tF 0T C L - 2 0 + 2tA + tC + tF ns

11Aug98@14:48h Intermediate Version Semiconductor Group 56 1998-08 C163-L AC Characteristics CLKOUT and READY (Reduced Supply Voltage Range) (Operating Conditions apply, C L = 100 pF) 1) These timings are given for test purposes only, in order to assure recognition at a specific clock edge. 2) Demultiplexed bus is the worst case. For multiplexed bus 2TCL are to be added to the maximum values. This adds even more time for deactivating READY. The 2tA and tC refer to the next following bus cycle, tF refers to the current bus cycle. Parameter Symbol Max. CPU Clock = 12 MHz Variable CPU Clock 1 / 2TCL = 1 to 12 MHz Unit min. max. min. max. CLKOUT cycle time t29 CC 83 83 2TCL 2TCL ns CLKOUT high time t30 CC 22 – TCL – 20 – ns CLKOUT low time t31 CC 26 – TCL – 16 – ns CLKOUT rise time t32 CC – 16 – 16 ns CLKOUT fall time t33 CC – 10 – 10 ns CLKOUT rising edge to ALE falling edge t34 CC -6 + tA 6 + tA -6 + tA 6 + tA ns Synchronous READY setup time to CLKOUT t35 SR 20 – 20 – ns Synchronous READY hold time after CLKOUT t36 S R 0 – 0–n s Asynchronous READY low time t37 SR 103 – 2TCL + 20 – ns Asynchronous READY setup time 1) t58 SR 20 – 20 – ns Asynchronous READY hold time 1) t59 SR 0 – 0–n s Async. READY hold time after RD, WR high (Demultiplexed Bus) 2) t60 SR 01 6 + 2tA + tC + tF 0T C L - 2 6 + 2tA + tC + tF ns

11Aug98@14:48h Intermediate Version Semiconductor Group 57 1998-08 C163-L Figure 15 CLKOUT and READY Notes 1) Cycle as programmed, including MCTC waitstates (Example shows 0 MCTC WS). 2) The leading edge of the respective command depends on RW-delay. 3) READY sampled HIGH at this sampling point generates a READY controlled waitstate, READY sampled LOW at this sampling point terminates the currently running bus cycle. 4) READY may be deactivated in response to the trailing (rising) edge of the corresponding command (RD or WR ). 5) If the Asynchronous READY signal does not fulfill the indicated setup and hold times with respect to CLKOUT (eg. because CLKOUT is not enabled), it must fulfill t37 in order to be safely synchronized. This is guaranteed, if READY is removed in reponse to the command (see Note 4)). 6) Multiplexed bus modes have a MUX waitstate added after a bus cycle, and an additional MTTC waitstate may be inserted here. For a multiplexed bus with MTTC waitstate this delay is 2 CLKOUT cycles, for a demultiplexed bus without MTTC waitstate this delay is zero. 7) The next external bus cycle may start here. CLKOUT ALE t30 t34 Sync READY t35 t36 t35 t36 Async READY t58 t59 t58 t59 waitstate READY MUX/Tristate 6) t32 t33 t29 Running cycle 1) t31 t37 3) 3) Command RD , WR t60 see 6) 3) 3)

11Aug98@14:48h Intermediate Version Semiconductor Group 58 1998-08 C163-L AC Characteristics External Bus Arbitration (Standard Supply Voltage Range) (Operating Conditions apply, C L = 100 pF) AC Characteristics External Bus Arbitration (Reduced Supply Voltage Range) (Operating Conditions apply, C L = 100 pF) Parameter Symbol Max. CPU Clock = 25 MHz Variable CPU Clock 1 / 2TCL = 1 to 25 MHz Unit min. max. min. max. HOLD input setup time to CLKOUT t61 SR 20 –2 0 – n s CLKOUT to HLDA high or BREQ low delay t62 CC – 20 – 20 ns CLKOUT to HLDA low or BREQ high delay t63 CC – 20 – 20 ns CSx release t64 CC – 20 – 20 ns CSx drive t65 CC -4 24 -4 24 ns Other signals release t66 CC – 20 – 20 ns Other signals drive t67 CC -4 24 -4 24 ns Parameter Symbol Max. CPU Clock = 12 MHz Variable CPU Clock 1 / 2TCL = 1 to 12 MHz Unit min. max. min. max. HOLD input setup time to CLKOUT t61 SR 34 – 34 – ns CLKOUT to HLDA high or BREQ low delay t62 CC – 24 – 24 ns CLKOUT to HLDA low or BREQ high delay t63 CC – 24 – 24 ns CSx release t64 CC – 20 – 20 ns CSx drive t65 CC -6 30 -6 30 ns Other signals release t66 CC – 20 – 20 ns Other signals drive t67 CC -6 30 -6 30 ns

11Aug98@14:48h Intermediate Version Semiconductor Group 59 1998-08 C163-L Figure 16 External Bus Arbitration, Releasing the Bus Notes 1) The C163-L will complete the currently running bus cycle before granting bus access. 2) This is the first possibility for BREQ to get active. 3) The CS outputs will be resistive high (pullup) after t64. CLKOUT HOLD t61 HLDA t63 Other Signals t66 CSx (On P6.x) t64 2)BREQ t62

11Aug98@14:48h Intermediate Version Semiconductor Group 60 1998-08 C163-L Figure 17 External Bus Arbitration, (Regaining the Bus) Notes 1) This is the last chance for BREQ to trigger the indicated regain-sequence. Even if BREQ is activated earlier, the regain-sequence is initiated by HOLD going high. Please note that HOLD may also be deactivated without the C163-L requesting the bus. 2) The next C163-L driven bus cycle may start here. CLKOUT HOLD HLDA Other Signals t62 CSx (On P6.x) t67 t62 t65 t61 BREQ t63t62

11Aug98@14:48h Intermediate Version Semiconductor Group 61 1998-08 C163-L AC Characteristics Synchronous Serial Port Timing (Standard Supply Voltage Range) (Operating Conditions apply, C L = 100 pF) Parameter Symbol Max. Baudrate = 12.5 / 10 MBd Variable Baudrate = 0.5 to 12.5 MBd Unit min. max. min. max. SSP clock cycle time t200 CC 80 / 100 80 / 100 4 TCL 512 TCL ns SSP clock high time t201 CC 30 / 40 –/ – t200/2 - 10 – ns SSP clock low time t202 CC 30 / 40 – / – t200/2 - 10 – ns SSP clock rise time t203 CC – / – 6 / 6 – 6 ns SSP clock fall time t204 CC – / – 6 / 6 – 6 ns CE active before shift edge t205 CC 30 / 40 – / – t200/2 - 10 – ns CE inactive after latch edge t206 CC 70 / 90 90 / 110 t200 - 10 t200 + 10 ns Write data valid after shift edget207 CC – / – 10 / 10 – 10 ns Write data hold after shift edget208 CC 0 / 0 – / – 0 – ns Write data hold after latch edget209 CC 34 / 44 46 / 56 t200/2 - 6 t200/2 + 6 ns Read data active after latch edget210 SR 50 / 60 – / – t200/2 + 10 – ns Read data setup time before latch edge t211 SR 20 / 20 – / – 20 – ns Read data hold time after latch edge t212 SR 0 / 0 – / – 0 – ns

11Aug98@14:48h Intermediate Version Semiconductor Group 62 1998-08 C163-L AC Characteristics Synchronous Serial Port Timing (Reduced Supply Voltage Range) (Operating Conditions apply, C L = 100 pF) Parameter Symbol Max. Baudrate = 6 MBd Variable Baudrate = 0.5 to 6 MBd Unit min. max. min. max. SSP clock cycle time t200 CC 167 167 4 TCL 512 TCL ns SSP clock high time t201 CC 63 – t200/2 - 20 – ns SSP clock low time t202 CC 73 – t200/2 - 10 – ns SSP clock rise time t203 CC – 14 – 14 ns SSP clock fall time t204 CC – 10 – 10 ns CE active before shift edge t205 CC 73 – / – t200/2 - 10 – ns CE inactive after latch edge t206 CC 147 187 t200 - 20 t200 + 20 ns Write data valid after shift edget207 CC – / – 20 – 20 ns Write data hold after shift edget208 CC -6 – -6 – ns Write data hold after latch edget209 CC 63 103 t200/2 - 20t200/2 + 20 ns Read data active after latch edget210 SR 93 – t200/2 + 10 – ns Read data setup time before latch edge t211 SR 30 – 30 – ns Read data hold time after latch edge t212 SR 0–0–n s

11Aug98@14:48h Intermediate Version Semiconductor Group 64 1998-08 C163-L Package Outlines Figure 20 Sorts of Packing Package outlines for tubes, trays, etc. are contained in our Data Book “Package Information” SMD = Surface Mounted Device Dimensions in mm Plastic Package, P-TQFP-100-3 (SMD) (Plastic Thin Metric Quad Flat Package)

11Aug98@14:48h Intermediate Version Semiconductor Group 65 1998-08 C163-L

11Aug98@14:48h Intermediate Version Semiconductor Group 66 1998-08 C163-L Siemens Aktiengesellschaft Published by