SAF-C503-1RN

SAB-C503 SIEMENS | Alldatasheet

Document overview

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Technical content

8-Bit CMOS Microcontroller SAB-C503 Preliminary @ Fully compatible to standard 8051 microcontroller @ Versions for 12 / 20 MHz operating frequency @ 8K x8 ROM (SAB-C503-1R only) @ 256 x 8 RAM @ Four 8-bit ports, (including one input port for digital or analog input) @ Three 16-bit Timers / Counters (Timer 2 with Up/Down Counter feature) @ USART @ Genuine 10-bit A/D Converter with 8 multiplexed inputs @ Seven interrupt sources, two priority levels @ Programmable 15-bit Watchdog Timer @ Oscillator Watchdog @ Fast Power On Reset @ Power Saving Modes @ P-LCC-44 package @ Temperature ranges: SAB-C503 Tx: 0 'C to 70 C SAF-C503 T,:— 40 C to 85 'C SAB-C503 Oscillator RAM 5 Ee eo Analog/ n | 8-bil Digit. Input ed SE ROM 8k x 8 weedy tier | aahott ik won Pot o> CAO TG4

The SAB-C503-L/C503-1R described in this document is compatible (not pin-compatible) with the SAB 80C32/C52 and can be used for all present SAB 80C52 applications. The SAB-C503-1R contains a non-volatile 8 K x 8 read-only program memory, a volatile 256 x 8 read/write data memory, four ports, three 16-bit timers/counters, a seven source, two priority level Interrupt structure, a serial port, versatile fail save mechanisms and a genuine 10-bit A/D Converter. The SAB-C503-L is identical, except that it lacks the program memory on chip. Therefore the term SAB-C503 refers to both versions within this specification unless otherwise noted.

Ordering Information

Code (8-Bit CMOS microcontroller) SAB-C503-LN Q67120-C835 | P-LCC-44 | for external memory

12 MHz

SAB-C503-1RN P-LCC-44 | with mask-programmable ROM, SAB-C503-L20N Q67120-C877 | P-LCC-44 | for external memory

20 MHz

SAB-C503-1R20N P-LCC-44 | with mask-programmable ROM, 20 MHz . SAF-C503-LN Q67120-C879 |P-4CC-44 | for external ROM, 12 MHz, ext. temp. - 40 °C to 85 °C SAF-C503-1RN Q67120-C880 | P-LCC-44 | with mask-programmable ROM, 12 MHz, ext. temp. — 40 'C to 85 'C ~ SAF-C503-L20N Q67120-C881 | P-LCC-44 | for external memory, 20 MHz, ext. temp. - 40 'C to 85 °C SAF-C503-1R20N Q67120-C882 | P-LCC-44 | with mask-programmable ROM, 20 MHz, ext. temp. — 40 'C to 85 °C Note: Extended temperature range — 40 °C to 110 C (SAH-C503) on request.

{top view) (P-LCC-44) cm ae 88 85388 zz | 2258 =f 4g be 2.9592 tases seeee oop oooooe P1.2/ane2 ( 7 O 3910 P0.4/AD4 P1.3/a0c3 O 8 3810 PO.5/ADS Pi.4/apcs C9 370 P0.6/A06 P1.5/a0C5 (10 36D PO.7/AD7 Pt.6/ance C14 35 A P1.7/anc7 (12 SAB-C503 341 ALE reset C13 331) PSEN P3.0/RxD C14 321 P2.7/a15 P3.1/Txd 015 31D P2.6/a14 P3.2/iNTO C116 300 P2.5/a13 P3.3/INTI C17 2910 P2.4/a12 18 19 20 21 22 23 24 25 26 27 28 aS bore] er SECRET SEES som 5 > a 7 = . eared agg

Yser <> abit oigit. 1/0 Ycwo Port t RESET <I petit Analog/Digit. Input FA SAB-C503 : Port porn <—> soit Digit. [/0 Port 3 XTALI K—> aon ne ae 8-bit Digit, [/0 WOU 765 Logic Symbol

Pin Definitions and Functions Symbol _| Pin Number | Function a — P1.7-P1.0 |12-5 jl | Port 1 is an 8-bit unidirectional input port. Port pins can be used for digital input, if voltage levels meet the specified input high low voltages, and for the multiplexed analog inputs of the A/D- Converter, simultaneously. Port 1 also contains the timer 2 pins as secondary function. The secondary functions are assigned to the pins of port 1, as follows: 5 P1.0 ANO/T2 Analog input channel 0 Input to counter 2 16 P1.1. AN1/T2EX Analog input channel 1 Capture - Reload | | trigger of timer 2 / Up-Down count

7 P12 AN2 Analog input channel 2

‘8 | P1.3 ANS Analog input channel 3

9 P14 ANA Analog input channel 4

|10 P1.5 ANS Analog input channel 5 1" P16 ANG Analog input channel 6 12 P1.7 AN7 Analog input channel 7 *) 1 Input © = Output M@™® 8235605 0061320 350 Semiconductor Group 406

Pin Definitions and Functions (cont'd) Symbol | Pin Number [1/0 | Function P.ice-44_ |") P3.0-P3.7 |14-21 VO | Port3 is a bidirectional /O port with internal pull-up resistors. Port 3 pins that have 1s written to them are pulled high by the internal pull-up resistors, and in that state they can be used as inputs. As inputs, port 3 pins being externally pulled low will source current (/,, in the DC characteristics) because of the internal | pull-up resistors. Port 3 also contains the interrupt, timer, serial | |port 0 and external memory strobe pins which are used by | various options. The output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate. | | The secondary functions are assigned to the pins of port 3, as | | follows: i 14 | |=RxD — (P3.0): receiver data input (asynchronous) or data j inpuvoutput (synchronous) of serial interface 15 | -TxD — (P3.1): transmitter data output (asynchronous) or | clock output (synchronous) of serial interface | |=iNTO (P3.2): interrupt 0 inputtimer 0 gate control 16 | |-INTT (P3.3): interrupt T input/timer 1 gate control 17 | |=T0 —(P3.4): counter 0 input 18 -T1_— (P3.5): counter 1 input 19 -WA — (P3.6): the write controt signal latches the data byte 20 __ from port 0 into the external data memory -RD — (P3.7): the read control signal enables the external 24 } data memory to port 0 *) = Input O = Output MM 6235605 006132) 217 Semiconductor Group 407

Pin Definitions and Functions (cont'd) Symbol [Pin Number |/O [Function = OO Pcc-44 |”) XTAL2 XTAL2 Output of the inverting oscillator amplifier. XTAL1 23 — | XTAL1 Input to the inverting oscillator amplifier and input to the internal clock generator circuits. To drive the device from an external clock source, XTAL1 should be driven, while XTAL2 is left unconnected. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is divided down by a divide-by-two flip-flop, Minimum and maximum high and low times a well as rise/fall times specified in the AC _ characteristics must be observed. P2.0-P2.7 | 25-32 VO | Port 2 is a bidirectional /O port with internal pull-up resistors, Port 2 pins that have 1s written to them are pulled high by the internal pull-up resistors, and in that state they can be used as inputs. { As inputs, port 2 pins being externally pulled low will source | current (7, in the DC characteristics) because of the internal i pull-up resistors. Port 2 emits the high-order address byte | | during fetches from external program memory and during accesses to external data memory that use 16-bit addresses | | (MOVX @DPTR). In this application it uses strong internal ' pull-up resistors when issuing 1s. During accesses to external ; } data memory that use 8-bit addresses (MOVX @Ri), port 2 i issues the contents of the P2 special function register. PSEN 133 O |The Program Store Enable output is a control signal that enables the external program memory to the bus during external fetch operations. It is | | activated every six oscillator periods except during external data memory accesses. Remains high during internal program | execution. RESET 13 RESET A high level on this pin for two machine cycles while the oscillator is running resets the device. An internal diffused | resistor to V5 permits power-on reset using only an external | capacitor to Voc. _ __ *) = Input O = Output M™ 8235605 0061322 153 mm Semiconductor Group 408

Pin Definitions and Functions (cont'd) ‘Symbol Pin Number Function P-LCC-44 ALE The Address Latch Enable output is used for latching the low-byte of the address into external memory during normal operation. It is activated every six oscillator periods except during an external data memory access. EA External Access Enable When held at high level, instructions are fetched from the internal ROM (SAB-C503-1R only) when the PC is less than 2000}. When held at low level, the SAB-C503 fetches all instructions from external program memory. For the SAB-C503-L this pin must be tied low. PO.0-P0.7 | 43-36 VO | Porto is an 8-bit open-drain bidirectional /O port. Port 0 pins that have 1s written to them float, and in that state can be used as high-impedance inputs. Port 0 is also the multiplexed low- order address and data bus during accesses to external Program or data memory. In this application it uses strong internal pull-up resistors when issuing 1s. Port 0 also outputs the code bytes during program verification in the SAB-C503-1R. External pull-up resistors are required during program verification. . Viner 2 Reference voltage for the A/D converter. Vacno [3 __| __| Reference ground for the A/D converter, Veg [4,24 |- _| Circuit ground potential Veo [44 __|— _| Supply terminal for all operating modes N.C [1 __|=_[ No connection *) Le Input = Output MH 6235605 0061323 O97 Semiconductor Group 409

The SAB-C503 is fully compatible to the standard 8051 microcontroller family. It is compatible with the SAB 80C52 but not pin-compatible. While maintaining all architectural and operational characteristics of the SAB 80C52 the SAB-C503 incorporates a genuine 10-bit A/D Converter as well as some enhancements in the Timer2 and Fail Save Mechanism Unit. Figure 1 shows a block diagram of the SAB-C503. poor a ' 1 oscillator ' | | Watchdog ROM i 1 RAM x8 |! | | 256 x 8 C503-1R XTALI '} 0S¢ & Timing only ' xTAL2 «<— \\ RESET —o LL cru - ALE «—| PSEN <—— [ Programmable \\ TA —»! | Watchdog Timer i

1 Port 0

| ' \\ | i ° T Analog Input \\ [ rer? => 8-bit Digit. 1/0

1 Port 5

' | Port 3 > B-bit Digi. 1/0 Ga er 1 1 \\ 1 Varer ——-]| A/D Converter ! 1 Vacvo ——H| 10-bit ! | 1 ica | LIT W toa wceoi7e7 Figure 1 oe —_ : Block Diagram of the SAB-C503 M™ 8235605 0061324 T2b mm Semiconductor Group 410

The SAB-C503 is efficient both as a controller and as an arithmetic processor. It has extensive facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results from an instruction set consisting of 44% one-byte, 41 % two-byte, and 15 % three-byte instructions. With a 12 MHz crystal, 58 % of the instructions executed in 1.0 us (20 MHz : 600 ns). ‘Special Function Register PSW MsB ise Bit No. 7 6 5 4 3 2 1 0 neet.0oy [OY | a [Fo [Asi | Aso | ov] A | P_jesw Bit [Function _ cy Carry Flag AC Auxiliary Carry Flag (for BCD operations) FO General Purpose Flag RS1 RSO Register Bank select control bits 0 0 Bank 0 selected, data address 00} - 07} 0 1 Bank 1 selected, data address 08} - OF}, 1 0 Bank 2 selected, data address 10}4 - 174 1 a Bank 3 selected, data address 18-1Fy ov __| Overflow Flag FA General Purpose Flag P Parity Flag. Set/cleared by hardware each instruction cycle to indicate an odd/ even number of “one” bits in the accumulator, i.e. even parity. Reset value of PSW is OOH. M™@ 6235605 0061325 She a Semiconductor Group 4it

Special Function Registers All registers, except the program counter and the four general purpose register banks, reside in the special function register area. The 33 special function registers (SFRs) include pointers and registers that provide an interface between the CPU and the other on-chip peripherals. There are also 128 directly addressable bits within the SFR area. All SFRs are listed in table 1, table 2 and table 3. In table 1 they are organized in numeric order of their addresses. In table 2 they are organized in groups which refer to the functional blocks of the SAB-C503. Table 3 illustrates the contents of the SFRs. Table 1 Special Function Registers in Numeric Order of their Addresses “Address | Register Contents | Address Contents _ after Reset after Reset

804 Pov FFH 984 SCON” 00H,

81H SP 074 9944 ‘SBUF XXpy? 82 DPL 00, =| = 9A reserved XX? 83y, DPH 004 | 9By reserved XXy? 84y (WDTL)® 04 | 9Cy reserved XX}?! 854 (WOTH)® 004 9Dq reserved XXH?) 86H WDTREL 004 9Ey reserved XXy?) __ 87H PCON 000X0000p” OF reserved | XXy? 88y TCON ? 004 A0y P20 FFy 894 TMOD 004 Aly reserved XXy?! BAH TLO 004 A2y reserved XX?! 8By Tut 004 A8H reserved XX? 8Cy THO 00H A4y, reserved XX? 8Dy THI 004 ASH reserved XXy2 8Ey reserved XXy?) AG reserved XXy2 8Fy _reserved XX? | AH “reserved XXy2 90H PI FFH A8y IE” 00H 914 reserved 004, AS reserved XX? 9244 reserved KH? | AAW reserved XXy?) 934 reserved XXy? ABY reserved XXy? 944 reserved xxy? | ACY reserved XX? 954, reserved XXy?— | AD reserved XXy?) 9644 reserved XXy? | AE reserved XXy? 97H reserved XX? AFH reserved _ XH? 0: Bit-addressable Special Function Register 2); X means that the value is indeterminate and the location is reserved ®; () ... SFR not user accessable M@™@ 8235605 O0b13cb 679 a Semiconductor Group 412

Special Function Register in Numeric Order of thelr Addresses (cont'd) Address Contents. Address Register Contents after Reset after Reset BOy P3”) FFH D8y ‘ADCONO” 004, Biy reserved | — XXy? Dey ADDATH 004, Bay reserved | XX}? DAY ADDATL 004 B3y reserved | XXy? DBy reserved XX}? Bay reserved XXy? DCy ADCON1 OXXX0000B? Boy reserved | XX?) DDY reserved XXy? N6Y reserved | = XX} DEY reserved XXpy? B7y reserved XXy7 DF reserved XX? BBy PD XX000000g E0y ACC! 004 Boy, reserved XXy 2) Ey reserved XX?) BAY reserved XXpy? E2y reserved XXy? BBY reserved XXy? E3y reserved | XXq? BCy reserved XXy? E4y reserved | XXy? BDy reserved | XXq® 5uy reserved XXy? BEY reserved | XXy E6y reserved XXy? BFH reserved | _XXy” E7H reserved XXq? COy | WDCON” | XXXX00008 ? E6y reserved XXpy# Ciy reserved XXy? Ey reserved XXy? Cay reserved XXy? EAW reserved XXy2 C3y reserved XXy? EB reserved XXy2 C4y reserved XXy2 ECy reserved XXpy? C5y reserved XXy? EDy reserved XX? C6y reserved XXy7 EEY reserved XXpy?) C7H reserved XXy? EF reserved XX?) C8y T2CON® 004, FO BD 00H C94 |) T2MOD | XXXXXXX0g” Fiy reserved XXy? CAW | RC2L | 00H Fay, reserved XX?) CBy | RC2H | ooy F3y reserved XXp? ccy | TL2 00H Fay reserved XXy CDy TH2 004 F5H reserved XX CEY reserved XX? Fb reserved XXH? CFy reserved XXpy? F7H reserved XXH? DOy Psw? 00H Fey reserved XXq? Diy reserved XX? Foy reserved XXp?! Dey | reserved XXy? FAY, reserved XXp?) D3y | reserved XXy? FBY reserved XXy? D4y reserved XXH? Foy reserved XXy? D5q, reserved XXy? FOY reserved XXy? 064 reserved XXH? FEY reserved XXy? D7H reserved XXH? FFY reserved XXH? »: Bittaddressable Special Function Register 2: X means that the value is indeterminate and the location is reserved @™® 6235605 0061327 735 Semiconductor Group 413

Special Function Registers - Functional Blocks Block Symbol | Name ~ ‘Address | _ Contents after Reset cPU ACC | Accumulator E04” 004 B B-Register FOy? 0044 DPH _| Data Pointer, High Byte 834 0044 DPL Data Pointer, Low Byte 82 0044 PSW Program Status Word Register Do” 004, SP Stack Pointer 81H 07H Interrupt Interrupt Enable Register ABY” 0044 System Interrupt Priority Register B8y” | X000 0000p Ports PO Port 0 80,4” OFF Pt Port 1, Analog/Digital Input 9044” XXq? P2 Port 2 Ady” OFFy P3 Port 3 BOY” OFFy A/D-Converter | ADCONO | A/D Converter Control Register 0 DsH® 004 ADCONI | A/D Converter Control Register 1 ocy OXXX 0000p” ADDATH | A/D Converter Data Register High Byte | D9y 00H ADDATL | A/D Converter Data Register Low Byte | DAY 004, Serial PCON® | Power Control Register 874 00q Channels SBUF _| Serial Channel Buffer Reg. 9944 OXXy SCON | Serial Channel 0 Control Reg. 9844” 004 Timer 0/ TCON Timer 0/1 Control Register 88H" 00H Timer 1 THO Timer 0, High Byte H 0044 THt Timer 1, High Byte 8Dy 0044 TLO Timer 0, Low Byte 8A 0044 Tu Timer 1, Low Byte 8By 0044 TMOD _| Timer Mode Register 89H 00H, Timer 2 T2CON | Timer 2 Control Register C8y” 004 T2MOD | Timer 2 Mode Register Coy XXXX XXX0g” RC2H Timer 2 Reload Capture Reg., High Byte | CA}, OO, RC2L | Timer 2 Reload Capture Reg., Low Byte | CBY 00} TH2 Timer 2, High Byte CDy 0044 TL2 Timer 2, Low Byte __|eCu 00H, Watchdog | WDCON | Watchdog Timer Control Register Coy? — | XXXX 00005” WDTREL | Watchdog Timer Reload Reg. 86} 0044 Pow.Sav. PCON | Power Control Register 874 000X 00005” Modes . ") Bit-addressable special function registers ® This special function register is listed repeatedly since some bits of it also belong to other functional blocks 3) X means that the value is indeterminate and the location is reserved @® =4235605 0061328 67] Semiconductor Group 414

Contents of SFRs, SFRs in Numeric Order Address | Register) Bit7 6 5 4 3 2 1 C) A | SO |_ 864 | woTREL PCON |[ SMOD | PDS | IDLS | - | GFI | GFO | PDE | IDLE TCON |[_tFi_[ tat | tro | tro | ie: | m1 | ico | 10 89, | TMOD |[ GATE | CT | Mi, MO, GATE, CT | Mi | MO BAY | TO 8By | TL —_ 984 | SCON |[{ smo | smi [ sw2 | REN | Tes | Res | Tl | Al 4 | spur [[ Aoy [pe | Agu | te |[ ea [evo | ere | es | err | ext [eto | 2x0 | | bey |e |[ = [acy pre [ps jer | px | pro | x0 | coy | wocon |[" | ==] =| owns | wors | wor | swor | | C84 | Tecon || tre | exre | RCLK | TCLK | EXENO| The | Off@ | OPALD Temop |{ ~~ = = = = = Tce) CT TT 1 TTT] srr bit and byte addressable I Lt SFR not bit addressable C) must not be used —: = bit location is reserved @™! 86235605 0061329 SOs Semiconductor Group 415

Contents of SFRs, SFRs in Numeric Order (cont'd) [Address | Register] sit7 6 5 4 3 2 1 0 [omy | Road [Cd [roo [owe | [doy | psw [oy [| ac | ro [rsi [ws [Tov [A [P| 084 | ADcono [= | - | aoc [| psy | ADM | Mxe | Mxr | Mx | [DAY | ADDATL a = -t- if. = DC} ADCON' Eq) acc | Foy | oe TT CET TT {TJ ] serit and byte addressable tot SFR not bit addressable C] must not be used —1= bit location is reserved M™@ 6235605 0061330 22T a Semiconductor Group 416

Timer/Counter 0 and 1 can be used in four operating modes as listed in table 4: Table 4 Timert/Counter 0 and 1 Operating Modes Mode |Description ~TMOD Input Clock cr external (max) 0 8-bit timer/counter with a x x Soschexse Soso/rax32 divide-by-32 prescaler 1 16-bit timer/counter [x |x | 0 | 1 | feels | fosclse 2 8-bit timer/counter with x [x Sosche Soscles | B-bit auto-reload . 3 Timer/counter 0 used as one x x Soso! 2 Soscles 8-bit timer/counter and one | 8-bit timer {Timer 1 stops oe . In the “timer” function (C/T = ‘0’) the register is incremented every machine cycle. Therefore the count rate is foso/12. In the “counter” function the register is incremented in response to a 1-to-0 transition at its ‘corresponding external input pin (P3.4/TO, P3.5/T1). Since it takes two machine cycles to detect a falling edge the max. count rate is foso/24. External inputs INTO and INTT (P3.2, P3.3) can be programmed to function as a gate to facilitate pulse width measurements. Figure 2 illustrates the input clock logic. oy °3.4/T0 Timer 0/1 max fose/24 1 TR 0/1 | contro! TCON ‘| __ 24 P3.2/iNTO P3.3/INTI wesor768 Figure 2 Timer/Counter 0 and 1 Input Clock Logic M™@ 6235605 0061331 1lbb a Semiconductor Group 417

Timer 2 is a 16-bit Timer/Counter with an up/down count feature. It can operate either as timer or as an event counter which is selected by bit C/T2 (T2CON.1). It has three operating modes as shown in table 5. Table 5 Timer/Counter 2 Operating Modes — T2CON __| T2MOD] T2CON Input Clock PXCLK | PL - Mode or | om | tre T2EX Remarks \\ external txeik | PL2 DCEN | EXEN | (P1.0/T2) . 16-bit 0 ic) 1 o | Oo X | reload upon Auto- | overtiow reload 0 o}4 0 1 4 | reload trigger max (faling edge) |"? | feosoa 0 ) 1 1 x 0 | Down counting 0 0 1 1 x 1 | Up counting 16-bit 1 x Cy) X | 16 bit Timer/ Cap- Counter (only ture up-counting) max 1 x | 4 J feapture TH2, | 80/12 | p04 | TL2 > RC2H, RC2L _ Baud 1 x x | 0 X | no overflow Rate interrupt Gene- Tequest (TF2) Soadl2 max rator 1 x x 1 4 extra external | 7° Sosol24 interrupt (‘Timer 2") a# {x px fey x) x |X [tinezso | =| Note: |= ~\\_ falling edge M™@ 4235605 0061332 OT2 a Semiconductor Group 418

Serial Interface (USART) The serial port is full duplex and can operate in four modes (one synchronous mode, three asynchronous modes) as illustrated in table 6. The possible baudrates can be calculated using the formulas given in table 7. Table 6 USART Operating Modes Mode =o | “__ 0 Sosc/12 Serial data enters and exits through RxD. TxD outputs the shift clock. 8-bits are transmitted/received (LSB first) 1 1 Timer 1/2 overtlow rate | 8-bit UART 10 bits are transmitted (through TxD) or received (RxD) _ 2 1 0 Foso/32 0F fosc/64 9-bit UART 11 bits are transmitted (TxD) or received (RxD) . 3 1 1 | Timer 1/2 overflow rate_| 9-bit UART Like mode 2 except the variable baud rate Table 7 Formulas for Calculating Baudrates Baud Rate Interface Mode —-Baudrate derived from Oscillator 0 Sfosc/12 2 (280° x fosc) / 64 Timer 1 (16-bit timer) 13 (28"©° x timer 1 overflow rate) /32 (8-bit timer with 1,3 (25M02 x fog) / (32 x 12 x (256-TH1)) 8-bit autoreload) Timer 2 13 osc ! (32 x (65536-(RC2H, RC2L)) @™ 4235605 0061333 735 Semiconductor Group 419

In the SAB-C503 a high performance/high speed 8-channel 10-bit A/D-Converter (ADC) using the successive approximation technique is implemented. internal Bus P 1 (90}) | =e ese [ee] | . ADCONI (OCH) emZ 44 is - | UMM TET | ae WLAZ eSY WD] WT WK 0 Li Ll ADDATH ADDATL Single/ (094) (OAH) Continous Mod ott ‘antinous Mode 757] = wx L+ i wo = | 3 Va) | Converter [4 Va] fose ZY five Ls 37] \\ [6 [6 ise oo Vaowo - Start of | = Conversion ——— Write to ADDATL - internal Bus Shaded bit locations are not used in ADC~functions wcaot769 Ai Bit x3 in SFR ADCONI must not be set Figure 3 Block Diagram A/D-Converter Note that bit ADCL in SFR ADCONO has to be set when fosc is higher than 16 MHz. Furthermore bit MX3 in SFR ADCON1 must not be set otherwise a not connected channel would be selected. The formula for the conversion time is given by: fg = 14 x (8 x 24°°) / fose @@ =6235605 0061334 975 Semiconductor Group 420

The SAB-C503 provides 7 interrupt sources with two priority levels. Figure 4 gives a general overview of the interrupt sources and illustrates the request and contro! flags. Timer 0 Overtlow —s f Low Priority TCONS — IEA Timer 1 Overflow (FJ as TCON.0 TCON.7 — IES Timer 2 Overflow oH T2CON.7 | ~ ye a || a/——\\b T2CON.E IES T2CON.3 {Ri} | 21 < “, USART SCONO |” “- an i} Gs STON. 14 Pa P3.2/ [>] , é TCOND 1.0 1P.0 wR eR He | TCONZ 2 2 | ra A/D Converter — maa ADCONO.S < 6 7 P6 wes01770 Figure 4 Interrupt Request Sources M@™@ 4235605 0061335 401 a Semiconductor Group 421

Interrupt Sources and their Corresponding Interrupt Vectors Source (Request Flags) Vector ~~ T Vector Address - =) External interrupt 0 00034 TFO Timer 0 interrupt 000By

161 External interrupt 1 00134

TFA Timer 1 interrupt 001B, Rl+Tl Serial port interrupt 0023} TF2 + EXF2 ‘Timer 2 interrupt 002By IADC AID converter interrupt 00434) A low-priority interrupt can itself be interrupted by a high-priority interrupt, but not by another low- priority interrupt. A high-priority interrupt cannot be interrupted by any other interrupt source. If two requests of different priority level are received simultaneously, the request of higher priority is serviced. If requests of the same priority are received simultaneously, an internal polling sequence determines which request is serviced. Thus within each priority level there is a second priority structure determined by the polling sequence as shown in table 9. Table 9 Interrupt Priority-within-Level Interrupt Source Priority External Interrupt 0, 1EO High AID Converter, 1ADC Timer 0 Interrupt, TFO External Interrupt 1, 1E1 4 Timer 1 Interrupt, FI Serial Channel, RlorTl Timer 2 Interrupt, ‘TF2 or EXF2 Low MH 4235605 0061336 748 Semiconductor Group 422

— Starting and refreshing the WOT Table 10 gives an overview how to start and refresh the WOT. The mentioned bits are located in SFR WOCON. Table 10 Starting and Refreshing the WOT Function [Example __| Remarks Starting WOT SETB — SWDT | Cannot be stopped during active mode of the device. W0DT is halted during idle mode, power down mode or the oscillator watchdog reset is active. Refreshing WOT | SETB WOT | Double instruction sequence SETB — SWDT | (setting bit WOT and SWDT consecutively) to increase system security. — Watchdog reset and watchdog status flag (WDTS) If the software fails to clear the watchdog in time, an internally generated watchdog reset is entered at the counter state 7FFC}y. The duration of the reset signal then depends on the prescaler selection (either 8 or 128 cycles). This internal reset differs from an external one in so far as the Watchdog Timer is not disabled and bit WOTS (SFR WDCON) is set. The WDTS is a flip-flop, which is set by a Watchdog Timer reset and can be cleared by an external hardware reset. Bit WDTS allows the software to examine from which source the reset was activated. The bit WDTS can also be cleared by software. M™§ 8235605 0061338 510 mm Semiconductor Group aza

Fast Internal Reset after Power-On The SAB-C503 can use the oscillator watchdog unit for a fast internal reset procedure after power- on. Normally members of the 8051 family enter their default reset state not before the on-chip oscillator starts. The reason is that the external reset signal must be internally synchronized and processed in order to bring the device into the correct reset state. Especially if a crystal is used the start up timed of the oscillator is relatively long (typ. 1 ms). During this time period the pins have an undefined state which could have severe effects e.g. to actuators connected to port pins. In the SAB-C503 the oscillator watchdog unit avoids this situation. After power-on the oscillator watchdog’s RC oscillator starts working within a very short start-up time (typ. less than 2 1s), In the following the watchdog circultry detects a failure condition for the on-chip oscillator this has not yet started (a failure is always recognized if the watchdog's RC oscillator runs faster than the on-chip oscillator). As long as this condition is valid the watchdog uses the RC oscillator output as a clock source for the chip rather than the on-chip oscillator's output. This allows correct resetting of the part and brings also ail ports to the defined state. Delay between power-on and correct reset state: Typ: 18ys Max: 34 us M@™ 6235605 0061340 1795 Semiconductor Group 426

Two power down modes are available, the Idle Mode and Power Down Mode. The bits PDE, PDS and IDLE, IDLS select the Power Down mode or the idle mode, respectively. If the Power Down mode and the idle mode are set at the same time, Power Down takes precedence. Table 10 gives a general overview of the power saving modes. Table 10 Power Saving Modes Overview se _|etome_(eety_(reene Idle mode ORL PCON, #01H |-enabled interrupt | CPU is gated off ORL PCON, #20H | — Hardware Reset | CPU status registers maintain their data. Peripherals are active Double _ instruction sequence Power-Down | ORL PCON, #02H | Hardware Reset Oscillator are stopped. Mode ORL PCON, #40H Contents of on-chip RAM and | SFR's are maintained (leaving { Power Down Mode means redefinition of SFR's contents).

7 Double instruction sequence

In the Power Down mode of operation, Vo, can be reduced to minimize power consumption. It must be ensured, however, that Vcc is not reduced before the Power Down mode is invoked, and that Voo is restored to its normal operating level, before the Power Down mode is terminated. The reset signal that terminates the Power Down mode also restarts the oscillator. The reset should not be activated before Voc is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize (simulator to power-on reset). M@™@ 6235605 0061341 00S mm Semiconductor Group 427

Ambient temperature under bias (7) ....ss-socesseeesseceseseenesusssassesnsennsneeeeeeeres = 40 tO + 85°C Storage temperature (Ti:)..-seieneteieisiesentisnstinnennssnesnnnannnan = 6510+ 150°C Voltage on Vgc pins with respect to ground (Vg) svwevnwrveeeeeererecrenenase = 0.5 V 10 6.5 V Note: Stresses above those listed under “Absolute Maximum Ratings" may cause permanent damage of the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for longer periods may affect device reliability. During overload conditions (Vj > Voc OF Vy < Ves) the Voltage on Vcc pins with respect fo ground (Vss) must not exceed the values defined by the absolute maximum ratings. MB 6235605 0061342 TH) ‘Semiconductor Group 428

Vog=5V+10%,- 15%: Veg=0V; Ta=0°Ct0 70°C _for the SAB-C503 T,=~40°C to. 85°C for the SAF-C503 Parameter Symbol Limit Values Test Condition min, max. Input low voltage a -05 0.2Vee-0.11V |= (except EA, RESET) 7 Input low voltage (EA) _ Faus -0.5 0.2%oc-0.3 V |= Inputlow voltage (RESET) [Vir |-05 — |02Vec+01|V |- Input high voltage (except | Vay 02 Veg +09! Voo+05 VV |= RESET, XTAL1, EA) — input igh volage to XTALI EA Output low voltage Vo. 0.45 V [i=t.6ma” (ports 2, 3) Output low voltage Vo: |= 0.45 Vo [Iq =3.2mA0 (port 0, ALE, PSEN) Output high voltage Vou 24 - V | Jon =—- 80 pA, (ports 2, 3) 09 Vee = Jou==10WA Output high voltage Vou [24 = V | Zou =~ 800 WA, (port 0 in external bus mode, 0.9 Veo - Toy = — 80 pA? ALE, PSEN) __ Logie 0 input current I =10 -50 TWA | Vy = 0.45 V (ports 1, 2, 3) — Logical 1-t0-0 transition Ih vA |Vy=2V current (ports 2, 3) input leakage current ly #1 WA [0.45 <Vy< Voc (port 0, EA, P1) Pin capacitance Co fc = 1 MHz, T, = 25°C Power supply current: Active mode, 12 MHz”) | Joc 25.8 mA | Vec= 5V,° Idle mode, 12MHz7— Tog, 8 mA | Voc= 5V,° Active mode, 20 MHz”) | Too 35.5 mA | Voc=5V,9 Idle mode, 20 MHz? | og 10.1 mA | Voc=5V,® Power Down Mode Teo 50 BA |Voc=2...5.5V,9_ M™ 4235605 0061343 988 Semiconductor Group 429

Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the Vo. of ALE and port 3. The noise 1s due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operation. In the worst case (capacitive loading > 100 pF), the noise pulse on ALE line may exceed 0.8 V. In such cases it may be desirable to quality ALE with a schmitttrigger, ‘or use an address latch with a schmitt-rigger strobe input. 2. Capacitive loading on ports 0 and 2 may cause the Voy on ALE and PSEN to momentarily fall below the 0.9 Veg specification when the address lines are stabilizing,

2 Jpn (Power Down Mode) is measured under following conditions:

EA = Port 0 = Port 1 = Voc: RESET = Vg; XTAL2 = N.C.; XTAL1 = Visi Vaono = Vssi all other pins are disconnected. ® Igg (active mode) is measured with: _ XTALI driven with foros forci = 58, Vi, = Vos + 0.5 V, Vn, = Voo— 0.5 V, XTAL2 = N.C.; EA = Port 0 = Port 1 = RESET = Vo; all other pins are disconnected. Ic would be slightly higher if a crystal oscillator is used (appr. 1 mA). ® Iog (Idle mode) is measured with all output pins disconnected and with all peripherals disabled; _ Port 0 = Port 1 = Moc; all other pins are disconnected; 7 ec max other frequencies is given by: active mode: Tocmax = 1.21 X fose + 11.28 idle mode: Iecmax = 0.27 X fose + 4.73 where foss is the oscillator frequency in MHz. foc values are given in mA and measured at Voc = 5 V. M@™@ 6235605 0061344 614 mm ‘Semiconductor Group 430

A/D Converter Characteristics Vog = 5 V + 10 %,— 15 %; Veg = OV Vaser = Voc + 5%: Vagao = Veg + 0.2 V; T,=0C to 70°C for the SAB-C503. T,=— 40°C to 85°C for the SAF-C503 Parameter Symbol] Limit Values _| Test Condition [min. [typ [max. | Raoainpaeapasionce [Gas [70 oF Sample tine (neloadtine) [72 || ta as 2 Conversion time Te 14 toy ® a (inc. sample time) Total unadjusted error *: TUE +2 LSB | VAREF = Veo, VAGND = Veg © toy = (BX 2°) / fose (toy = 11! faoei fave = Foss / (B x 240°) 2 This parameter specifies the time during the input capacitance C, can be charged/discharged by the external source. It must be guaranteed, that the input capacitance C,, is fully loaded within this time. 4 TCY 1s 2 us at the fogo = 16 MHz. After the end of the sample time 7s, changes of the analog input voltage have no effect on the conversion result. ® This parameter includes the sample time Ts. 14 TCY is 7 us at fosc = 16 MHz. * This parameter includes also the DNLE. MB 6235605 0061345 750 Semiconductor Group 431

AC Characteristics for SAB-C503-LN / C503-1RN Voo = 5 V + 10%, — 15%; Veg = OV Ty = 0 to 70°C for the SAB-C503 T,=-40°C to 85°C for the SAF-C503 (C, for port 0, ALE and PSEN outputs = 100 pF; C, for all other outputs = 80 pF) Program Memory Characteristics Parameter | Symbol Limit Values Unit | | 12MHz Varlable Clock | | Clock | 1iteuc, = 3.5 MHz to 12 MHz [in max. | min. max. ALE pulse width Tie (127 |= tan 40 [= ns ‘Address setup to ALE ta 43 = - Tas ALE low to valid instr in lt |- 283 |- | Aten —100 [ns SEN ule wih Ps Input instruction hold after PSEN | tpxx - ns Input instruction float after PSEN fee | ns Address valid after PSEN tou? [75 |- |tua-8 [- ins Address to valid instr in lism [- (902 |- [Stam —115 | ns Address float to PSEN [om [0 |- [o |= sins *) Interfacing the SAB-C503 to devices with float times up to 75 ns is permissible. This limited bus contention will not cause any damage to port 0 Drivers. WM 8235605 00b134b 617? Semiconductor Group 432

AC Characteristics for SAB-C503-LN / C503-1RN External Data Memory Characteristics Parameter Symbol Limit Values Unit “42 MHz Variable Clock Clock | 1/teu. = 3.5 MHz to 12 MHz min. [min. [max RD pulse width Traum | 400 Gtac.- 100 |= ns Address hold after ALE 30 taa-53[- ins Data hs ter RD line [0 [= 0 ALE to valid data in [tov [= [517 |= [ta —150 [ns ‘Address to valid data in ltvov [= 1585 |- [Stan 165 ns ALE to WR or RD fam Bt +50 [ns Address valid to WR or RD fave = |4taa-130 [= |ns WR or RD high to ALE high tan 123 \\tua-40 |taa+40 |ns_ Data valid to WR transition = Jfaa-50 [- [ns Dataseup btreWA Yann |e88 [=| Plaw 150 [= 1 M@® 6235605 0061347 Ses Semiconductor Group 433

Parameter : Limit Values ; Unit Varlable Clock Freq. = 3.5 MHz to 12 MHz max. Oscillator period 285.7 ns High time [toner | ns M™ 4235605 0061348 4bT a Semiconductor Group 434

AC Characteristics for SAB-C503-L20N / C503-1R20N Voc = 5V + 10%, — 15 %; Vos = OV T,=0°Cto70'C for the SAB-C503 T,=-40°C to 85°C for the SAF-C503 (C, for port 0, ALE and PSEN outputs = 100 pF; C, for all other outputs = 80 pF) Program Memory Characteristics Parameter Symbol Limit Values Unit

20 MHz ‘Variable Clock

Clock | titac. = 3.5 MHz to 20 MHz ALEpulsewidth ———~—~S tims —*(6O Bt -40 |- ins Address setup to ALE tay [20 | ear -+— ns Address hold after ALE tux [20 [= [taa-30 [- ins ALE low to valid instr in law - |100 [- fra —100 [ns ALE to PSEN tw (25 = ta -25 [= is PSEN pulse width ltr 115 |= | Biaqa-35 |= ns PSEN to valid instr in try |= (78 | Stan -75 [ns Input instruction hold after PSEN foxx |0 - - ns Input instruction float after PSEN | frxz? [- [40 foc - 10 ns Address valid after PSEN tow 147 [= ltaa-3 [- ins ‘Address to valid instr in [tw | 1190 |= [Sta -60 [ns *) Interfacing the SAB-C503 to devices with float times up to 45 ns is permissible. This limited bus contention will not cause any damage to port 0 Drivers. M™@ 4235605 0061349 3Tb Semiconductor Group 435

AC Characteristics for SAB-C501-L20N / C503-1R20N External Data Memory Characteristics Parameter ‘Symbol Limit Values Unit | Clock | titeucy = 9.5 MHz to 20 MHz min. [max min [max FB pus wd Tam 00 [= ya=100 = +(e WR pulse width Gi. -100 |- | ns ‘Address hold after ALE. fue | 20 taa-30 ns RD to valid data in - Slag -95 [ns Data hold after RD [tmox [0 |- [oO | ns Address to valid data in [two [- [285 [- [Sta 165 [ns ALE to WR or BD [tum [100 [200 [Saq-50 |Sian+S0 [ns Address valid to WR or RD Ttwm (70 |- = ns WR or RD high to ALE high fmm [20 [80 | f—30 faa +30 [ns Data valid to WA transition tow [5 |- faa-45 |- (ns Data hold after WA wwe [10 [= fa -40 [= Address float after FG a a M™ 6235605 0061350 018 Semiconductor Group 436

Parameter ~~ T symbol “Limit Values jest Variable Clock | | Freq, = 3.5 MHz to 20 MHz | min. max. Oscillator Period fouce 50 285.7 ns High time tonex 12 teror — foucx ins Low time Toxcx fexcu — foncx Ins Rise time ns T fou ALE rc fav | Cy, fopy —~| | I fury mQ tuw =) | tow PEN } | | bm fae. —) fpay ake fur |e) tong tone fa a weroo096 Figure 7 Program Memory Read Cycle @™ 6235605 006135) T54 Semiconductor Group 437

| Ann ALE RD tev fo Fasor Ltrs | i eur fran HO-AT from YYY AN AO-AT Instr vert Hero” XXXL soe i from. 4yypy ———— weT00097 Figure 8 Data Memory Read Cycle M@™ 8235605 0061352 990 a Semiconductor Group 438

func} Pew wR 1 fav =m | ~ fun hi a RO-AT from WV A0-A7 l-— faye wero00e8 Figure 9 Data Memory Write Cycle M™ 4235605 0061353 62? Semiconductor Group 439

ROM Verification Characteristics tor SAB-C503-1A ROM Verification Mode 1 Parameter ——— Address to valid data tayov Bloc ns ENABLE to valid data [Feow Bloc. ns Data float after ENABLE evar ns Oscillator frequency tere le Ss«S Mz puoeeda {vies ) _| favav tow. ae, | fome P27 ENABLE a wor009e Address: P1.0-P1.7=A0-A7 Inputs: P2.5-P2.6, PSEN=K P2.0-P2.4=A8~A12 ALE, FA= Vy Data; P0.0-P0.7=00-07 RESET = Viq1 Figure 10 7 i ROM Verification Mode 1 MM 6235605 0061354 7b3 ‘Semiconductor Group 440

3.5-20 MHz C9 XTALI 7 XTALI

23 External Oscillator 23}

C = 30pF +10pF weso17es (incl. stray capacitance) Crystal Oscillator Mode Driving from External Source Figure 14 Recommended Oscillator Circults MB 8235605 0061356 53b Semiconductor Group 442