SAE81C52 SIEMENS | Alldatasheet

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Technical content

The SAE 81C52 is a CMOS-silicon gate, static random access memory (RAM), organized as 256 words by 8 bits. The multiplexed address and data bus interfaces directly to 8-bit microprocessors/microcontrollers without any timing or level problems, e.g. the families SAB 8086, SAB 8051. All inputs and outputs are fully compatible with NMOS circuits, except CS1. Data retention is ensured up to VDD ≥ 1.0 V. The SAE 81C52 has three different inputs for two chip select modes which allow to inhibit either the address/data lines (AD 0 … AD 7) and the control lines ( WR, RD, ALE, CS2,CS3), or only the control linesRD, WR. The power consumption is max. 5.5µW in standby mode and max. 16.5 mW in operation. In standby mode, the power consumption will not increase if the control inputs are on undefined potential. Type Ordering Code Package SAE 81C52 P Q67100-H9017 P-DIP-16-1 SAE 81C52 G Q67100-H9015 P-DSO-20-1 (SMD) 256 x 8-Bit Static CMOS RAM NMOS-Compatible Preliminary DataCMOS IC SAE 81C52 P-DIP-16-1 P-DSO-20-1 PFeatures

  • 256 x 8-bit organization
  • Standby mode
  • Compatible with the NMOS and CMOS versions of the microprocessor/microcontroller families SAB 8086, SAB 8051
  • Very low power dissipation
  • Data retention up toVDD ≥ 1 V
  • Three different chip select inputs for two chip select modes
  • No increasing power consumption in standby mode if the control inputs are on undefined potential
  • Temperature range – 40 to 110°C Semiconductor Group 1 09.94

(top view) SAE 81C52 P SAE 81C52 G

Pin Definitions and Functions SAE 81C52 G SAE 81C52 P Symbol Function Pin No. Pin No. 1, 2, 4, 5, 6 7, 12, 14 1 … 6 10, 11 AD0 … 7 Address/data lines 15 12 CS1 Chip select 1 (standby) active low; inhibits all lines including control lines 16 13 ALE Address latch enable WR RD Write enable Read enable 20 16 VDD Power supply

97 VSS GND (0 V)

Chip select 2; inhibits control inputsRD, WR Counterpart to CS2

*: Level =VSS … VDD X: Level = low or high CS1 CS2 CS3 ALE RD WR AD0 … AD7 Function L H H H H H X H H L X X L L X H H L L L L H L H X X H H L X X Floating (tristate) Addresses to memory Data from memory Data to memory Floating (tristate) Floating (tristate) Standby Store addresses Read Write None None

TA = – 40 to 110 °C Parameter Symbol Limit Values Unit Supply voltage referred to GND (VSS ) All input and output voltages VDD VIM 0 to 6 VSS – 0.3 VDD + 0.3 V V V Total power dissipation Power dissipation for each output Ptot PQ 250 mW mW Junction temperature Storage temperature Tj Tstg 125 – 55 to 125 Thermal resistance system - air P-DIP-16-1 P-DSO-20-1 Rth SA Rth SA K/W K/W Operating Range Supply voltage VDD 4.5 to 5.5 V Ambient temperature TA – 40 to 110 °C

TA = – 40 to 110 °C; VDD = 4.25 V to 5.5 V;VSS = 0 V Parameter Symbol Limit Values Unit Test Condition min. max. Standby supply current Supply current IDD IDD µA mA VDD = 5.5 V; TA = 25°C; VCS1 = 0 V Δtcyc = 1µs;VDD = 5.5 V; C L = 100 pF Standby voltage for data retention VDD 1.0 V L-input current (for each input) Output leakage current IIL IQLK µA µA VI = 0 toVDD VQ = 0 toVDD tristate L-input voltage H-input voltage VIL VIH VSS 2.2 0.8 VDD V V L-output voltage H-output voltage VQL VQH 2.6 0.4 V V IQL = 1 mA IQL = 1 mA L-input voltage CS1 H-input voltage CS1 VIL VIH VSS VDD – 1 VDD V V

TA = – 40 to 110°C; VDD = 4.5 to 5.5 V;VSS = 0 V Parameter Symbol Limit Values Unit min. max. ALE pulse width ALE low beforeRD low RD high before ALE high ALE low before WR low WR high before ALE high tLHLL tLLRL tRHLH tLLWL tWHLH 100 ns ns ns ns ns Address setup before ALE Address hold after ALE WR or RD pulse width tAVLL tLLAX tWLWH 250 ns ns ns Data setup before WR Data hold afterWR Data hold afterRD tQVWH tWHQX tRHDX ns ns ns Chip select (2, 3) before RD, WR Chip select (2, 3) afterRD, WR Chip select 1 before ALE Chip select 1 after RD, WR tCS tSC tCSLH tCSWH ns ns ns ns Output delay time tRLDV 200 ns Input capacitance toVSS (for each input)C I 10 pF

SAE 81C52 with theµC SAB 8051