SAB80C166 SIEMENS | Alldatasheet
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Data Sheet 09.94 Microcomputer Components SAB 80C166/83C166 16-Bit CMOS Single-Chip Microcontroller
Semiconductor Group 1 09.94 l High Performance 16-bit CPU with 4-Stage Pipeline l 100 ns Instruction Cycle Time at 20 MHz CPU Clock l 500 ns Multiplication (16 · 16 bit), 1 ms Division (32 / 16 bit) l Enhanced Boolean Bit Manipulation Facilities l Register-Based Design with Multiple Variable Register Banks l Single-Cycle Context Switching Support l Up to 256 KBytes Linear Address Space for Code and Data l 1 KByte On-Chip RAM l 32 KBytes On-Chip ROM (SAB 83C166 only) l Programmable External Bus Characteristics for Different Address Ranges l 8-Bit or 16-Bit External Data Bus l Multiplexed or Demultiplexed External Address/Data Buses l Hold and Hold-Acknowledge Bus Arbitration Support l 512 Bytes On-Chip Special Function Register Area l Idle and Power Down Modes l 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via Peripheral Event Controller (PEC) l 16-Priority-Level Interrupt System l 10-Channel 10-bit A/D Converter with 9.7 ms Conversion Time l 16-Channel Capture/Compare Unit l Two Multi-Functional General Purpose Timer Units with 5 Timers l Two Serial Channels (USARTs) l Programmable Watchdog Timer l Up to 76 General Purpose I/O Lines l Supported by a Wealth of Development Tools like C-Compilers, Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers, Simulators, Logic Analyzer Disassemblers, Programming Boards l On-Chip Bootstrap Loader l 100-Pin Plastic MQFP Package (EIAJ) C16x-Family of High-Performance CMOS 16-Bit Microcontrollers Preliminary SAB 80C166/83C166 16-Bit Microcontroller SAB 80C166/83C166
The SAB 80C166 is the first representative of the Siemens SAB 80C166 family of full featured single-chip CMOS microcontrollers. It combines high CPU performance (up to 10 million instructions per second) with high peripheral functionality and enhanced IO-capabilities. Figure 1 Logic Symbol
Ordering Information
Note: The ordering codes (Q67120-D...) for the Mask-ROM versions are defined for each product after verification of the respective ROM code. Type Ordering Code Package Function SAB 83C166-5M Q67121-D... P-MQFP-100-2 16-bit microcontroller, 0 ˚C to +70 ˚C,
1 KByte RAM and 32 KByte ROM
SAB 83C166-5M-T3 Q67121-D... P-MQFP-100-2 16-bit microcontroller, -40 ˚C to +85 ˚C, SAB 80C166-M Q67121-C848 P-MQFP-100-2 16-bit microcontroller, 0 ˚C to +70 ˚C
1 KByte RAM
SAB 80C166-M-T3 Q67121-C900 P-MQFP-100-2 16-bit microcontroller, -40 ˚C to +85 ˚C
Pin Configuration Rectangular P-MQFP-100-2 (top view) Figure 2 SAB 80C166
Pin Definitions and Functions Symbol Pin Number Input Output Function P4.0 – P4.1 16-17 I/O O O Port 4 is a 2-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. In case of an external bus configuration, Port 4 can be used to output the segment address lines: P4.0 A16 Least Significant Segment Addr. Line P4.1 A17 Most Significant Segment Addr. Line XTAL1 XTAL2 I O XTAL1: Input to the oscillator amplifier and input to the internal clock generator XTAL2: Output of the oscillator amplifier circuit. To clock the device from an external source, drive XTAL1, while leaving XTAL2 unconnected. Minimum and maximum high/low and rise/fall times specified in the AC Characteristics must be observed. BUSACT EBC1, EBC0 I I I External Bus Configuration selection inputs. These pins are sampled during reset and select either the single chip mode or one of the four external bus configurations: BUSACT EBC1 EBC0 Mode/Bus Configuration 0 0 0 8-bit demultiplexed bus 0 0 1 8-bit multiplexed bus 0 1 0 16-bit multiplexed bus 0 1 1 16-bit demultiplexed bus 1 0 0 Single chip mode 1 0 1 Reserved. 1 1 0 Reserved. 1 1 1 Reserved. ROMless versions must have pin BUSACT tied to ‘0’. RSTIN 27 I Reset Input with Schmitt-Trigger characteristics. A low level at this pin for a specified duration while the oscillator is running resets the SAB 80C166. An internal pullup resistor permits power-on reset using only a capacitor connected to VSS . RSTOUT 28 O Internal Reset Indication Output. This pin is set to a low level when the part is executing either a hardware-, a software- or a watchdog timer reset. RSTOUT remains low until the EINIT (end of initialization) instruction is executed.
NMI 29 I Non-Maskable Interrupt Input. A high to low transition at this pin causes the CPU to vector to the NMI trap routine. When the PWRDN (power down) instruction is executed, pin NMI must be low in order to force the SAB 80C166 to go into power down mode. If NMI is high, when PWRDN is executed, the part will continue to run in normal mode. If not used, pull NMI high externally. ALE 25 O Address Latch Enable Output. Can be used for latching the address into external memory or an address latch in the multiplexed bus modes. RD 26 O External Memory Read Strobe. RD is activated for every external instruction or data read access. P1.0 – P1.15 30-37 40-47 I/O Port 1 is a 16-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. Port 1 is used as the 16-bit address bus (A) in demultiplexed bus modes and also after switching from a demultiplexed bus mode to a multiplexed bus mode. P5.0 – P5.9 48-53 56-59 I I Port 5 is a 10-bit input-only port with Schmitt-Trigger characteristics. The pins of Port 5 also serve as the (up to 10) analog input channels for the A/D converter, where P5.x equals ANx (Analog input channel x). P2.0 – P2.15 62-77 I/O I/O I/O O I/O O I/O I Port 2 is a 16-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. The following Port 2 pins also serve for alternate functions: P2.0 CC0IO CAPCOM: CC0 Cap.-In/Comp.Out P2.13 CC13IO CAPCOM: CC13 Cap.-In/Comp.Out, BREQ External Bus Request Output P2.14 CC14IO CAPCOM: CC14 Cap.-In/Comp.Out, HLDA External Bus Hold Acknowl. Output P2.15 CC15IO CAPCOM: CC15 Cap.-In/Comp.Out, HOLD External Bus Hold Request Input Pin Definitions and Functions (cont’d) Symbol Pin Number Input Output Function
P3.0 – P3.15 80-92, 95-97 I/O I/O I O I O I I I I O I/O O I/O O O I O Port 3 is a 16-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. The following Port 3 pins also serve for alternate functions: P3.0 T0IN CAPCOM Timer T0 Count Input P3.1 T6OUT GPT2 Timer T6 Toggle Latch Output P3.2 CAPIN GPT2 Register CAPREL Capture Input P3.3 T3OUT GPT1 Timer T3 Toggle Latch Output P3.4 T3EUD GPT1 Timer T3 Ext.Up/Down Ctrl.Input P3.5 T4IN GPT1 Timer T4 Input for Count/Gate/Reload/Capture P3.6 T3IN GPT1 Timer T3 Count/Gate Input P3.7 T2IN GPT1 Timer T2 Input for Count/Gate/Reload/Capture P3.8 TxD1 ASC1 Clock/Data Output (Asyn./Syn.) P3.9 RxD1 ASC1 Data Input (Asyn.) or I/O (Syn.) P3.10 T ·D0 ASC0 Clock/Data Output (Asyn./Syn.) P3.11 R ·D0 ASC0 Data Input (Asyn.) or I/O (Syn.) P3.12 BHE Ext. Memory High Byte Enable Signal P3.13 WR External Memory Write Strobe P3.14 READY Ready Signal Input P3.15 CLKOUT System Clock Output (=CPU Clock) P0.0 – P0.15 98 – 5 8 – 15 I/O Port 0 is a 16-bit bidirectional IO port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. In case of an external bus configuration, Port 0 serves as the address (A) and address/data (AD) bus in multiplexed bus modes and as the data (D) bus in demultiplexed bus modes. Demultiplexed bus modes: Data Path Width: 8-bit 16-bit P0.0 – P0.7: D0 – D7 D0 - D7 P0.8 – P0.15: output! D8 - D15 Multiplexed bus modes: Data Path Width: 8-bit 16-bit P0.0 – P0.7: AD0 – AD7 AD0 - AD7 P0.8 – P0.15: A8 - A15 AD8 - AD15 VAREF 54 - Reference voltage for the A/D converter. VAGND 55 - Reference ground for the A/D converter. Pin Definitions and Functions (cont’d) Symbol Pin Number Input Output Function
VCC 7, 18, 38, 61, 79, 93 - Digital Supply Voltage: + 5 V during normal operation and idle mode. ‡ 2.5 V during power down mode VSS 6, 21, 39, 60, 78, 94 - Digital Ground. Pin Definitions and Functions (cont’d) Symbol Pin Number Input Output Function
The architecture of the SAB 80C166 combines advantages of both RISC and CISC processors and of advanced peripheral subsystems in a very well-balanced way. The following block diagram gives an overview of the different on-chip components and of the advanced, high bandwidth internal bus structure of the SAB 80C166. Note: All time specifications refer to a CPU clock of 20 MHz (see definition in the AC Characteristics section). Figure 3 Block Diagram
The memory space of the SAB 80C166 is configured in a Von Neumann architecture which means that code memory, data memory, registers and I/O ports are organized within the same linear address space which includes 256 KBytes. Address space expansion to 16 MBytes is provided for future versions. The entire memory space can be accessed bytewise or wordwise. Particular portions of the on-chip memory have additionally been made directly bit addressable. The SAB 83C166 contains 32 KBytes of on-chip mask-programmable ROM for code or constant data. The ROM can be mapped to either segment 0 or segment 1.
1 KByte of on-chip RAM is provided as a storage for user defined variables, for the system stack,
general purpose register banks and even for code. A register bank can consist of up to 16 wordwide (R0 to R15) and/or bytewide (RL0, RH0, …, RL7, RH7) so-called General Purpose Registers (GPRs). 512 bytes of the address space are reserved for the Special Function Register area. SFRs are wordwide registers which are used for controlling and monitoring functions of the different on-chip units. 98 SFRs are currently implemented. Unused SFR addresses are reserved for future members of the SAB 80C166 family. In order to meet the needs of designs where more memory is required than is provided on chip, up to 256 KBytes of external RAM and/or ROM can be connected to the microcontroller. External Bus Controller All of the external memory accesses are performed by a particular on-chip External Bus Controller (EBC). It can be programmed either to Single Chip Mode when no external memory is required, or to one of four different external memory access modes, which are as follows: – 16-/18-bit Addresses, 16-bit Data, Demultiplexed – 16-/18-bit Addresses, 16-bit Data, Multiplexed – 16-/18-bit Addresses, 8-bit Data, Multiplexed – 16-/18-bit Addresses, 8-bit Data, Demultiplexed In the demultiplexed bus modes, addresses are output on Port 1 and data is input/output on Port 0. In the multiplexed bus modes both addresses and data use Port 0 for input/output. Important timing characteristics of the external bus interface (Memory Cycle Time, Memory Tri- State Time, Read/Write Delay and Length of ALE, i.e. address setup/hold time with respect to ALE) have been made programmable to allow the user the adaption of a wide range of different types of memories. In addition, different address ranges may be accessed with different bus characteristics. Access to very slow memories is supported via a particular ‘Ready’ function. A HOLD /HLDA protocol is available for bus arbitration. For applications which require less than 64 KBytes of external memory space, a non-segmented memory model can be selected. In this case all memory locations can be addressed by 16 bits and Port 4 is not required to output the additional segment address lines.
Central Processing Unit (CPU) The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit (ALU) and dedicated SFRs. Additional hardware has been spent for a separate multiply and divide unit, a bit-mask generator and a barrel shifter. Based on these hardware provisions, most of the SAB 80C166’s instructions can be executed in just one machine cycle which requires 100 ns at 20-MHz CPU clock. For example, shift and rotate instructions are always processed during one machine cycle independent of the number of bits to be shifted. All multiple-cycle instructions have been optimized so that they can be executed very fast as well: branches in 2 cycles, a 16 · 16 bit multiplication in 5 cycles and a 32-/16 bit division in 10 cycles. Another pipeline optimization, the so-called ‘Jump Cache’, allows reducing the execution time of repeatedly performed jumps in a loop from 2 cycles to 1 cycle. The CPU disposes of an actual register context consisting of up to 16 wordwide GPRs which are physically allocated within the on-chip RAM area. A Context Pointer (CP) register determines the base address of the active register bank to be accessed by the CPU at a time. The number of register banks is only restricted by the available internal RAM space. For easy parameter passing, a register bank may overlap others. Figure 4 CPU Block Diagram
32 KByte in the
A system stack of up to 512 bytes is provided as a storage for temporary data. The system stack is allocated in the on-chip RAM area, and it is accessed by the CPU via the stack pointer (SP) register. Two separate SFRs, STKOV and STKUN, are implicitly compared against the stack pointer value upon each stack access for the detection of a stack overflow or underflow. The high performance offered by the hardware implementation of the CPU can efficiently be utilized by a programmer via the highly efficient SAB 80C166 instruction set which includes the following instruction classes: – Arithmetic Instructions – Logical Instructions – Boolean Bit Manipulation Instructions – Compare and Loop Control Instructions – Shift and Rotate Instructions – Prioritize Instruction – Data Movement Instructions – System Stack Instructions – Jump and Call Instructions – Return Instructions – System Control Instructions – Miscellaneous Instructions The basic instruction length is either 2 or 4 bytes. Possible operand types are bits, bytes and words. A variety of direct, indirect or immediate addressing modes are provided to specify the required operands.
With an interrupt response time within a range from just 250 ns to 600 ns (in case of internal program execution), the SAB 80C166 is capable of reacting very fast to the occurrence of non- deterministic events. The architecture of the SAB 80C166 supports several mechanisms for fast and flexible response to service requests that can be generated from various sources internal or external to the microcontroller. Any of these interrupt requests can be programmed to being serviced by the Interrupt Controller or by the Peripheral Event Controller (PEC). In contrast to a standard interrupt service where the current program execution is suspended and a branch to the interrupt vector table is performed, just one cycle is ‘stolen’ from the current CPU activity to perform a PEC service. A PEC service implies a single byte or word data transfer between any two memory locations with an additional increment of either the PEC source or the destination pointer. An individual PEC transfer counter is implicity decremented for each PEC service except when performing in the continuous transfer mode. When this counter reaches zero, a standard interrupt is performed to the corresponding source related vector location. PEC services are very well suited, for example, for supporting the transmission or reception of blocks of data, or for transferring A/D converted results to a memory table. The SAB 80C166 has 8 PEC channels each of which offers such fast interrupt-driven data transfer capabilities. A separate control register which contains an interrupt request flag, an interrupt enable flag and an interrupt priority bitfield exists for each of the possible interrupt sources. Via its related register, each source can be programmed to one of sixteen interrupt priority levels. Once having been accepted by the CPU, an interrupt service can only be interrupted by a higher prioritized service request. For the standard interrupt processing, each of the possible interrupt sources has a dedicated vector location. Software interrupts are supported by means of the ‘TRAP’ instruction in combination with an individual trap (interrupt) number. The following table shows all of the possible SAB 80C166 interrupt sources and the corresponding hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers:
CAPCOM Register 0 CC0IR CC0IE CC0INT 40 H 10H CAPCOM Register 1 CC1IR CC1IE CC1INT 44 H 11H CAPCOM Register 2 CC2IR CC2IE CC2INT 48 H 12H CAPCOM Register 3 CC3IR CC3IE CC3INT 4C H 13H CAPCOM Register 4 CC4IR CC4IE CC4INT 50 H 14H CAPCOM Register 5 CC5IR CC5IE CC5INT 54 H 15H CAPCOM Register 6 CC6IR CC6IE CC6INT 58 H 16H CAPCOM Register 7 CC7IR CC7IE CC7INT 5C H 17H CAPCOM Register 8 CC8IR CC8IE CC8INT 60 H 18H CAPCOM Register 9 CC9IR CC9IE CC9INT 64 H 19H CAPCOM Register 10 CC10IR CC10IE CC10INT 68 H 1AH CAPCOM Register 11 CC11IR CC11IE CC11INT 6C H 1BH CAPCOM Register 12 CC12IR CC12IE CC12INT 70 H 1C H CAPCOM Register 13 CC13IR CC13IE CC13INT 74 H 1D H CAPCOM Register 14 CC14IR CC14IE CC14INT 78 H 1EH CAPCOM Register 15 CC15IR CC15IE CC15INT 7C H 1FH CAPCOM Timer 0 T0IR T0IE T0INT 80 H 20H CAPCOM Timer 1 T1IR T1IE T1INT 84 H 21H GPT1 Timer 2 T2IR T2IE T2INT 88 H 22H GPT1 Timer 3 T3IR T3IE T3INT 8C H 23H GPT1 Timer 4 T4IR T4IE T4INT 90 H 24H GPT2 Timer 5 T5IR T5IE T5INT 94 H 25H GPT2 Timer 6 T6IR T6IE T6INT 98 H 26H GPT2 CAPREL Register CRIR CRIE CRINT 9C H 27H A/D Conversion Complete ADCIR ADCIE ADCINT A0 H 28H A/D Overrun Error ADEIR ADEIE ADEINT A4 H 29H ASC0 Transmit S0TIR S0TIE S0TINT A8 H 2AH ASC0 Receive S0RIR S0RIE S0RINT AC H 2BH ASC0 Error S0EIR S0EIE S0EINT B0 H 2C H ASC1 Transmit S1TIR S1TIE S1TINT B4 H 2D H ASC1 Receive S1RIR S1RIE S1RINT B8 H 2EH ASC1 Error S1EIR S1EIE S1EINT BC H 2FH
The SAB 80C166 also provides an excellent mechanism to identify and to process exceptions or error conditions that arise during run-time, so-called ‘Hardware Traps’. Hardware traps cause immediate non-maskable system reaction which is similar to a standard interrupt service (branching to a dedicated vector table location). The occurrence of a hardware trap is additionally signified by an individual bit in the trap flag register (TFR). Except when another higher prioritized trap service is in progress, a hardware trap will interrupt any actual program execution. In turn, hardware trap services can normally not be interrupted by standard or PEC interrupts. The following table shows all of the possible exceptions or error conditions that can arise during run- time: Exception Condition Trap Flag Trap Vector Vector Location Trap Number Trap Priority Reset Functions: Hardware Reset Software Reset Watchdog Timer Overflow RESET RESET RESET 0000 H 0000H 0000H 00H 00H 00H III III III Class A Hardware Traps: Non-Maskable Interrupt Stack Overflow Stack Underflow NMI STKOF STKUF NMITRAP STOTRAP STUTRAP 0008 H 0010H 0018H 02H 04H 06H II II II Class B Hardware Traps: Undefined Opcode Protected Instruction Fault Illegal Word Operand Access Illegal Instruction Access Illegal External Bus Access UNDOPC PRTFLT ILLOPA ILLINA ILLBUS BTRAP BTRAP BTRAP BTRAP BTRAP 0028 H 0028H 0028H 0028H 0028H 0AH 0AH 0AH 0AH 0AH I I I I I Reserved [002C H – 003C H ] [0BH – 0FH ] Software Traps TRAP Instruction Any [0000H – 01FC H ] in steps of 04 H Any [00 H – 7FH ] Current CPU Priority
Capture/Compare (CAPCOM) Unit The CAPCOM unit supports generation and control of timing sequences on up to 16 channels with a maximum resolution of 400 ns (@ 20 MHz CPU clock). The CAPCOM unit is typically used to handle high speed I/O tasks such as pulse and waveform generation, pulse width modulation (PMW), Digital to Analog (D/A) conversion, software timing, or time recording relative to external events. Two 16-bit timers (T0/T1) with reload registers provide two independent time bases for the capture/ compare register array. The input clock for the timers is programmable to several prescaled values of the CPU clock, or may be derived from an overflow/underflow of timer T6 in module GPT2. This provides a wide range of variation for the timer period and resolution and allows precise adjustments to the application specific requirements. In addition, an external count input for CAPCOM timer T0 allows event scheduling for the capture/compare registers relative to external events. The capture/compare register array contains 16 dual purpose capture/compare registers, each of which may be individually allocated to either CAPCOM timer T0 or T1, and programmed for capture or compare function. Each register has one port pin associated with it which serves as an input pin for triggering the capture function, or as an output pin to indicate the occurrence of a compare event. When a capture/compare register has been selected for capture mode, the current contents of the allocated timer will be latched (captured) into the capture/compare register in response to an external event at the port pin which is associated with this register. In addition, a specific interrupt request for this capture/compare register is generated. Either a positive, a negative, or both a positive and a negative external signal transition at the pin can be selected as the triggering event. The contents of all registers which have been selected for one of the five compare modes are continuously compared with the contents of the allocated timers. When a match occurs between the timer value and the value in a capture/compare register, specific actions will be taken based on the selected compare mode. Compare Modes Function Mode 0 Interrupt-only compare mode; several compare interrupts per timer period are possible Mode 1 Pin toggles on each compare match; several compare events per timer period are possible Mode 2 Interrupt-only compare mode; only one compare interrupt per timer period is generated Mode 3 Pin set ‘1’ on match; pin reset ‘0’ on compare time overflow; only one compare event per timer period is generated Double Register Mode Two registers operate on one pin; pin toggles on each compare match; several compare events per timer period are possible.
x = 0 y = 1
General Purpose Timer (GPT) Unit The GPT unit represents a very flexible multifunctional timer/counter structure which may be used for many different time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or pulse multiplication. The GPT unit incorporates five 16-bit timers which are organized in two separate modules, GPT1 and GPT2. Each timer in each module may operate independently in a number of different modes, or may be concatenated with another timer of the same module. Each of the three timers T2, T3, T4 of module GPT1 can be configured individually for one of three basic modes of operation, which are Timer, Gated Timer, and Counter Mode. In Timer Mode, the input clock for a timer is derived from the CPU clock, divided by a programmable prescaler, while Counter Mode allows a timer to be clocked in reference to external events. Pulse width or duty cycle measurement is supported in Gated Timer Mode, where the operation of a timer is controlled by the ‘gate’ level on an external input pin. For these purposes, each timer has one associated port pin (TxIN) which serves as gate or clock input. The maximum resolution of the timers in module GPT1 is 400 ns (@ 20 MHz CPU clock). Figure 6 Block Diagram of GPT1
The count direction (up/down) for each timer is programmable by software. For timer T3 the count direction may additionally be altered dynamically by an external signal on a port pin (T3EUD) to facilitate e. g. position tracking. Timer T3 has an output toggle latch (T3OTL) which changes its state on each timer over-flow/ underflow. The state of this latch may be output on a port pin (T3OUT) e. g. for timeout monitoring of external hardware components, or may be used internally to clock timers T2 and T4 for measuring long time periods with high resolution. In addition to their basic operating modes, timers T2 and T4 may be configured as reload or capture registers for timer T3. When used as capture or reload registers, timers T2 and T4 are stopped. The contents of timer T3 is captured into T2 or T4 in response to a signal at their associated input pins (TxIN). Timer T3 is reloaded with the contents of T2 or T4 triggered either by an external signal or by a selectable state transition of its toggle latch T3OTL. When both T2 and T4 are configured to alternately reload T3 on opposite state transitions of T3OTL with the low and high times of a PWM signal, this signal can be constantly generated without software intervention. Figure 7 Block Diagram of GPT2
With its maximum resolution of 200 ns (@ 20 MHz), the GPT2 module provides precise event control and time measurement. It includes two timers (T5, T6) and a capture/reload register (CAPREL). Both timers can be clocked with an input clock which is derived from the CPU clock via a programmable prescaler. The count direction (up/down) for each timer is programmable by software. Concatenation of the timers is supported via the output toggle latch (T6OTL) of timer T6, which changes its state on each timer overflow/underflow. The state of this latch may be used to clock timer T5, or it may be output on a port pin (T6OUT). The overflows/underflows of timer T6 can additionally be used to clock the CAPCOM timers T0 or T1, and to cause a reload from the CAPREL register. The CAPREL register may capture the contents of timer T5 based on an external signal transition on the corresponding port pin (CAPIN), and timer T5 may optionally be cleared after the capture procedure. This allows absolute time differences to be measured or pulse multiplication to be performed without software overhead. A/D Converter For analog signal measurement, a 10-bit A/D converter with 10 multiplexed input channels and a sample and hold circuit has been integrated on-chip. It uses the method of successive approximation. The sample time (for loading the capacitors) and the conversion time adds up to 9.7 us @ 20 MHz CPU clock. Overrun error detection/protection is provided for the conversion result register (ADDAT): an interrupt request will be generated when the result of a previous conversion has not been read from the result register at the time the next conversion is complete. For applications which require less than 10 analog input channels, the remaining channel inputs can be used as digital input port pins. The A/D converter of the SAB 80C166 supports four different conversion modes. In the standard Single Channel conversion mode, the analog level on a specified channel is sampled once and converted to a digital result. In the Single Channel Continuous mode, the analog level on a specified channel is repeatedly sampled and converted without software intervention. In the Auto Scan mode, the analog levels on a prespecified number of channels are sequentially sampled and converted. In the Auto Scan Continuous mode, the number of prespecified channels is repeatedly sampled and converted. The Peripheral Event Controller (PEC) may be used to automatically store the conversion results into a table in memory for later evaluation, without requiring the overhead of entering and exiting interrupt routines for each data transfer.
The SAB 80C166 provides up to 76 I/O lines which are organized into five input/output ports and one input port. All port lines are bit-addressable, and all input/output lines are individually (bit-wise) programmable as inputs or outputs via direction registers. The I/O ports are true bidirectional ports which are switched to high impedance state when configured as inputs. During the internal reset, all port pins are configured as inputs. All port lines have programmable alternate input or output functions associated with them. Port 0 and Port 1 may be used as address and data lines when accessing external memory, while Port 4 outputs the additional segment address bits A17/A16 in systems where segmentation is enabled to access more than 64 KBytes of memory. Port 2 is associated with the capture inputs or compare outputs of the CAPCOM unit and/or with optional bus arbitration signals (BREQ , HLDA, HOLD). Port 3 includes alternate functions of timers, serial interfaces, optional bus control signals (WR, BHE , READY) and the system clock output (CLKOUT). Port 5 is used for the analog input channels to the A/D converter. All port lines that are not used for these alternate functions may be used as general purpose I/O lines. Serial Channels Serial communication with other microcontrollers, processors, terminals or external peripheral components is provided by two serial interfaces with identical functionality, Asynchronous/ Synchronous Serial Channels ASC0 and ASC1. They are upward compatible with the serial ports of the Siemens SAB 8051x microcontroller family and support full-duplex asynchronous communication up to 625 Kbaud and half-duplex synchronous communication up to 2.5 Mbaud @ 20 MHz CPU clock. Two dedicated baud rate generators allow to set up all standard baud rates without oscillator tuning. For transmission, reception, and erroneous reception 3 separate interrupt vectors are provided for each serial channel. In asynchronous mode, 8- or 9-bit data frames are transmitted or received, preceded by a start bit and terminated by one or two stop bits. For multiprocessor communication, a mechanism to distinguish address from data bytes has been included (8-bit data + wake up bit mode). In synchronous mode one data byte is transmitted or received synchronously to a shift clock which is generated by the SAB 80C166. A loop back option is available for testing purposes. A number of optional hardware error detection capabilities has been included to increase the reliability of data transfers. A parity bit can automatically be generated on transmission or be checked on reception. Framing error detection allows to recognize data frames with missing stop bits. An overrun error will be generated, if the last character received has not been read out of the receive buffer register at the time the reception of a new character is complete.
The Watchdog Timer represents one of the fail-safe mechanisms which have been implemented to prevent the controller from malfunctioning for longer periods of time. The Watchdog Timer is always enabled after a reset of the chip, and can only be disabled in the time interval until the EINIT (end of initialization) instruction has been executed. Thus, the chip’s start-up procedure is always monitored. The software has to be designed to service the Watchdog Timer before it overflows. If, due to hardware or software related failures, the software fails to do so, the Watchdog Timer overflows and generates an internal hardware reset and pulls the RSTOUT pin low in order to allow external hardware components to be reset. The Watchdog Timer is a 16-bit timer, clocked with the CPU clock divided either by 2 or by 128. The high byte of the Watchdog Timer register can be set to a prespecified reload value (stored in WDTREL) in order to allow further variation of the monitored time interval. Each time it is serviced by the application software, the high byte of the Watchdog Timer is reloaded. Thus, time intervals between 25 ms and 420 ms can be monitored (@ 20 MHz CPU clock). The default Watchdog Timer interval after reset is 6.55 ms (@ 20 MHz CPU clock). Bootstrap Loader The SAB 80C166 provides a built-in bootstrap loader (BSL), which allows to start program execution out of the SAB 80C166’s internal RAM. The program to be started is loaded via the serial interface ASC0 and does not require external memory or an internal ROM. The SAB 80C166 enters BSL mode, when ALE is sampled high at the end of a hardware reset and if NMI becomes active directly after the end of the internal reset sequence. BSL mode is entered independent of the bus mode selected via EBC0, EBC1 and BUSACT. After entering BSL mode the SAB 80C166 scans the RXD0 line to receive a zero byte, i.e. one start bit, eight ‘0’ data bits and one stop bit. From the duration of this zero byte it calculates the corresponding baudrate factor with respect to the current CPU clock and initializes ASC0 accordingly. Using this baudrate, an acknowledge byte is returned to the host that provides the loaded data. The SAB 80C166 returns the value <55 H >. The next 32 bytes received via ASC0 are stored sequentially into locations 0FA40H through 0FA5FH of the internal RAM. To execute the loaded code the BSL then jumps to location 0FA40H . The loaded program may load additional code / data, change modes, etc. The SAB 80C166 exits BSL mode upon a software reset (ignores the ALE level) or a hardware reset (remove conditions for entering BSL mode before).
The table below lists the instructions of the SAB 80C166 in a condensed way. The various addressing modes that can be used with a specific instruction, the operation of the instructions, parameters for conditional execution of instructions, and the opcodes for each instruction can be found in the “C16x Family Instruction Set Manual”. This document also provides a detailed description of each instruction. Instruction Set Summary Mnemonic Description Bytes ADD(B) Add word (byte) operands 2 / 4 ADDC(B) Add word (byte) operands with Carry 2 / 4 SUB(B) Subtract word (byte) operands 2 / 4 SUBC(B) Subtract word (byte) operands with Carry 2 / 4 MUL(U) (Un)Signed multiply direct GPR by direct GPR (16-16-bit) 2 DIV(U) (Un)Signed divide register MDL by direct GPR (16-/16-bit) 2 DIVL(U) (Un)Signed long divide reg. MD by direct GPR (32-/16-bit) 2 CPL(B) Complement direct word (byte) GPR 2 NEG(B) Negate direct word (byte) GPR 2 AND(B) Bitwise AND, (word/byte operands) 2 / 4 OR(B) Bitwise OR, (word/byte operands) 2 / 4 XOR(B) Bitwise XOR, (word/byte operands) 2 / 4 BCLR Clear direct bit 2 BSET Set direct bit 2 BMOV(N) Move (negated) direct bit to direct bit 4 BAND, BOR, BXOR AND/OR/XOR direct bit with direct bit 4 BCMP Compare direct bit to direct bit 4 BFLDH/L Bitwise modify masked high/low byte of bit-addressable direct word memory with immediate data CMP(B) Compare word (byte) operands 2 / 4 CMPD1/2 Compare word data to GPR and decrement GPR by 1/2 2 / 4 CMPI1/2 Compare word data to GPR and increment GPR by 1/2 2 / 4 PRIOR Determine number of shift cycles to normalize direct word GPR and store result in direct word GPR SHL / SHR Shift left/right direct word GPR 2 ROL / ROR Rotate left/right direct word GPR 2 ASHR Arithmetic (sign bit) shift right direct word GPR 2
MOV(B) Move word (byte) data 2 / 4 MOVBS Move byte operand to word operand with sign extension 2 / 4 MOVBZ Move byte operand to word operand. with zero extension 2 / 4 JMPA, JMPI, JMPR Jump absolute/indirect/relative if condition is met 4 JMPS Jump absolute to a code segment 4 J(N)B Jump relative if direct bit is (not) set 4 JBC Jump relative and clear bit if direct bit is set 4 JNBS Jump relative and set bit if direct bit is not set 4 CALLA, CALLI, CALLR Call absolute/indirect/relative subroutine if condition is met 4 CALLS Call absolute subroutine in any code segment 4 PCALL Push direct word register onto system stack and call absolute subroutine TRAP Call interrupt service routine via immediate trap number 2 PUSH, POP Push/pop direct word register onto/from system stack 2 SCXT Push direct word register onto system stack and update register with word operand RET Return from intra-segment subroutine 2 RETS Return from inter-segment subroutine 2 RETP Return from intra-segment subroutine and pop direct word register from system stack RETI Return from interrupt service subroutine 2 SRST Software Reset 4 IDLE Enter Idle Mode 4 PWRDN Enter Power Down Mode (supposes NMI -pin being low) SRVWDT Service Watchdog Timer 4 DISWDT Disable Watchdog Timer 4 EINIT Signify End-of-Initialization on RSTOUT-pin 4 NOP Null operation 2 Instruction Set Summary (cont’d) Mnemonic Description Bytes
Special Function Registers Overview The following table lists all SFRs which are implemented in the SAB 80C166 in alphabetical order. Bit-addressable SFRs are marked with the letter “b” in column “Name”. An SFR can be specified via its individual mnemonic name. Depending on the selected addressing mode, an SFR can be accessed via its physical address (using the Data Page Pointers), or via its short 8-bit address (without using the Data Page Pointers). Special Function Registers Overview Name Physical Address 8-Bit Address Description Reset Value ADCIC b FF98 H CC H A/D Converter End of Conversion Interrupt Control Register 0000H ADCON b FFA0 H D0 H A/D Converter Control Register 0000 H ADDAT FEA0 H 50H A/D Converter Result Register 0000 H ADDRSEL1 FE18 H 0C H Address Select Register 1 0000 H ADEIC b FF9A H CD H A/D Converter Overrun Error Interrupt Control Register 0000H BUSCON1 b FF14H 8AH Bus Configuration Register 1 0000 H CAPREL FE4A H 25H GPT2 Capture/Reload Register 0000 H CC0 FE80 H 40H CAPCOM Register 0 0000 H CC0IC b FF78H BC H CAPCOM Register 0 Interrupt Control Register 0000H CC1 FE82 H 41H CAPCOM Register 1 0000 H CC1IC b FF7A H BD H CAPCOM Register 1 Interrupt Control Register 0000H CC2 FE84 H 42H CAPCOM Register 2 0000 H CC2IC b FF7C H BE H CAPCOM Register 2 Interrupt Control Register 0000H CC3 FE86 H 43H CAPCOM Register 3 0000 H CC3IC b FF7E H BF H CAPCOM Register 3 Interrupt Control Register 0000H CC4 FE88 H 44H CAPCOM Register 4 0000 H CC4IC b FF80H C0 H CAPCOM Register 4 Interrupt Control Register 0000H CC5 FE8A H 45H CAPCOM Register 5 0000 H CC5IC b FF82H C1 H CAPCOM Register 5 Interrupt Control Register 0000H CC6 FE8C H 46H CAPCOM Register 6 0000 H CC6IC b FF84H C2 H CAPCOM Register 6 Interrupt Control Register 0000H CC7 FE8E H 47H CAPCOM Register 7 0000 H
CC7IC b FF86H C3 H CAPCOM Register 7 Interrupt Control Register 0000H CC8 FE90 H 48H CAPCOM Register 8 0000 H CC8IC b FF88H C4 H CAPCOM Register 8 Interrupt Control Register 0000H CC9 FE92 H 49H CAPCOM Register 9 0000 H CC9IC b FF8A H C5 H CAPCOM Register 9 Interrupt Control Register 0000H CC10 FE94 H 4AH CAPCOM Register 10 0000 H CC10IC b FF8C H C6 H CAPCOM Register 10 Interrupt Control Register 0000H CC11 FE96 H 4BH CAPCOM Register 11 0000 H CC11IC b FF8E H C7 H CAPCOM Register 11 Interrupt Control Register 0000H CC12 FE98 H 4C H CAPCOM Register 12 0000 H CC12IC b FF90H C8 H CAPCOM Register 12 Interrupt Control Register 0000H CC13 FE9A H 4D H CAPCOM Register 13 0000 H CC13IC b FF92H C9 H CAPCOM Register 13 Interrupt Control Register 0000H CC14 FE9C H 4EH CAPCOM Register 14 0000 H CC14IC b FF94H CA H CAPCOM Register 14 Interrupt Control Register 0000H CC15 FE9E H 4FH CAPCOM Register 15 0000 H CC15IC b FF96H CB H CAPCOM Register 15 Interrupt Control Register 0000H CCM0 b FF52H A9H CAPCOM Mode Control Register 0 0000 H CCM1 b FF54H AA H CAPCOM Mode Control Register 1 0000 H CCM2 b FF56H AB H CAPCOM Mode Control Register 2 0000 H CCM3 b FF58H AC H CAPCOM Mode Control Register 3 0000 H CP FE10 H 08H CPU Context Pointer Register FC00 H CRIC b FF6A H B5H GPT2 CAPREL Interrupt Control Register 0000 H CSP FE08 H 04H CPU Code Segment Pointer Register (2 bits, read only) 0000H DP0 b FF02H 81H Port 0 Direction Control Register 0000 H DP1 b FF06H 83H Port 1 Direction Control Register 0000 H DP2 b FFC2 H E1H Port 2 Direction Control Register 0000 H DP3 b FFC6 H E3H Port 3 Direction Control Register 0000 H DP4 b FF0A H 85H Port 4 Direction Control Register (2 bits) 00H Special Function Registers Overview (cont’d) Name Physical Address 8-Bit Address Description Reset Value
DPP0 FE00 H 00H CPU Data Page Pointer 0 Register (4 bits) 0000H DPP1 FE02 H 01H CPU Data Page Pointer 1 Register (4 bits) 0001H DPP2 FE04 H 02H CPU Data Page Pointer 2 Register (4 bits) 0002H DPP3 FE06 H 03H CPU Data Page Pointer 3 Register (4 bits) 0003H MDC b FF0E H 87H CPU Multiply / Divide Control Register 0000 H MDH FE0C H 06H CPU Multiply / Divide Register – High Word 0000H MDL FE0E H 07H CPU Multiply / Divide Register – Low Word 0000H ONES FF1E H 8FH Constant Value 1’s Register (read only) FFFF H P0 b FF00H 80H Port 0 Register 0000 H P1 b FF04H 82H Port 1 Register 0000 H P2 b FFC0 H E0H Port 2 Register 0000 H P3 b FFC4 H E2H Port 3 Register 0000 H P4 b FFC8 H E4H Port 4 Register (2 bits) 00 H P5 b FFA2 H D1 H Port 5 Register (read only) XXXX H PECC0 FEC0 H 60H PEC Channel 0 Control Register 0000 H PECC1 FEC2 H 61H PEC Channel 1 Control Register 0000 H PECC2 FEC4 H 62H PEC Channel 2 Control Register 0000 H PECC3 FEC6 H 63H PEC Channel 3 Control Register 0000 H PECC4 FEC8 H 64H PEC Channel 4 Control Register 0000 H PECC5 FECA H 65H PEC Channel 5 Control Register 0000 H PECC6 FECC H 66H PEC Channel 6 Control Register 0000 H PECC7 FECE H 67H PEC Channel 7 Control Register 0000 H PSW b FF10H 88H CPU Program Status Word 0000 H S0BG FEB4 H 5AH Serial Channel 0 Baud Rate Generator Reload Register 0000H S0CON b FFB0 H D8 H Serial Channel 0 Control Register 0000 H S0EIC b FF70H B8H Serial Channel 0 Error Interrupt Control Register 0000H S0RBUF FEB2 H 59H Serial Channel 0 Receive Buffer Register (read only) XX H Special Function Registers Overview (cont’d) Name Physical Address 8-Bit Address Description Reset Value
S0RIC b FF6E H B7H Serial Channel 0 Receive Interrupt Control Register 0000H S0TBUF FEB0 H 58H Serial Channel 0 Transmit Buffer Register (write only) 00H S0TIC b FF6C H B6H Serial Channel 0 Transmit Interrupt Control Register 0000H S1BG FEBC H 5EH Serial Channel 1 Baud Rate Generator Reload Register 0000H S1CON b FFB8 H DC H Serial Channel 1 Control Register 0000 H S1EIC b FF76H BB H Serial Channel 1 Error Interrupt Control Register 0000H S1RBUF FEBA H 5D H Serial Channel 1 Receive Buffer Register (read only) XX H S1RIC b FF74H BA H Serial Channel 1 Receive Interrupt Control Register 0000H S1TBUF FEB8 H 5C H Serial Channel 1 Transmit Buffer Register (write only) 00H S1TIC b FF72H B9H Serial Channel 1 Transmit Interrupt Control Register 0000H SP FE12 H 09H CPU System Stack Pointer Register FC00 H STKOV FE14 H 0AH CPU Stack Overflow Pointer Register FA00 H STKUN FE16 H 0BH CPU Stack Underflow Pointer Register FC00 H SYSCON b FF0C H 86H CPU System Configuration Register 0xx0 H *) T0 FE50 H 28H CAPCOM Timer 0 Register 0000 H T01CON b FF50H A8H CAPCOM Timer 0 and Timer 1 Control Register 0000H T0IC b FF9C H CE H CAPCOM Timer 0 Interrupt Control Register 0000H T0REL FE54 H 2AH CAPCOM Timer 0 Reload Register 0000 H T1 FE52 H 29H CAPCOM Timer 1 Register 0000 H T1IC b FF9E H CF H CAPCOM Timer 1 Interrupt Control Register 0000H T1REL FE56 H 2BH CAPCOM Timer 1 Reload Register 0000 H T2 FE40 H 20H GPT1 Timer 2 Register 0000 H T2CON b FF40H A0H GPT1 Timer 2 Control Register 0000 H T2IC b FF60H B0H GPT1 Timer 2 Interrupt Control Register 0000 H Special Function Registers Overview (cont’d) Name Physical Address 8-Bit Address Description Reset Value
*) The system configuration is selected during reset. T3 FE42 H 21H GPT1 Timer 3 Register 0000 H T3CON b FF42H A1H GPT1 Timer 3 Control Register 0000 H T3IC b FF62H B1H GPT1 Timer 3 Interrupt Control Register 0000 H T4 FE44 H 22H GPT1 Timer 4 Register 0000 H T4CON b FF44H A2H GPT1 Timer 4 Control Register 0000 H T4IC b FF64H B2H GPT1 Timer 4 Interrupt Control Register 0000 H T5 FE46 H 23H GPT2 Timer 5 Register 0000 H T5CON b FF46H A3H GPT2 Timer 5 Control Register 0000 H T5IC b FF66H B3H GPT2 Timer 5 Interrupt Control Register 0000 H T6 FE48 H 24H GPT2 Timer 6 Register 0000 H T6CON b FF48H A4H GPT2 Timer 6 Control Register 0000 H T6IC b FF68H B4H GPT2 Timer 6 Interrupt Control Register 0000 H TFR b FFAC H D6 H Trap Flag Register 0000 H WDT FEAE H 57H Watchdog Timer Register (read only) 0000 H WDTCON FFAE H D7 H Watchdog Timer Control Register 0000 H ZEROS b FF1C H 8EH Constant Value 0’s Register (read only) 0000 H Special Function Registers Overview (cont’d) Name Physical Address 8-Bit Address Description Reset Value
Ambient temperature under bias (TA): Storage temperature ( Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During overload conditions ( VIN > VCC or VIN < VSS ) the voltage on pins with respect to ground (VSS ) must not exceed the values defined by the Absolute Maximum Ratings. Parameter Interpretation The parameters listed in the following partly represent the characteristics of the SAB 80C166 and partly its demands on the system. To aid in interpreting the parameters right, when evaluating them for a design, they are marked in column “Symbol”: CC (C ontroller C haracteristics): The logic of the SAB 80C166 will provide signals with the respective timing characteristics. SR (System R equirement): The external system must provide signals with the respective timing characteristics to the SAB 80C166.
VCC = 5 V – 10 %; VSS = 0 V TA = 0 to +70 ˚C for SAB 83C166-5M, SAB 80C166-M TA = -40 to +85 ˚C for SAB 83C166-5M-T3, SAB 80C166-M-T3 Parameter Symbol Limit Values Unit Test Condition min. max. Input low voltage VIL SR – 0.5 0.2 VCC – 0.1 Input high voltage (all except RSTIN and XTAL1) VIH SR 0.2 VCC + 0.9 VCC + 0.5 V – Input high voltage RSTIN VIH1 SR 0.6 VCC VCC + 0.5 V – Input high voltage XTAL1 VIH2 SR 0.7 VCC VCC + 0.5 V – Output low voltage (Port 0, Port 1, Port 4, ALE, RD, WR , BHE, CLKOUT, RSTOUT ) VOL CC – 0.45 V IOL = 2.4 mA Output low voltage (all other outputs) VOL1 CC – 0.45 V IOL1 = 1.6 mA Output high voltage (Port 0, Port 1, Port 4, ALE, RD, WR , BHE, CLKOUT, RSTOUT ) VOH CC 0.9 VCC 2.4 –V IOH = – 500 mA IOH = – 2.4 mA Output high voltage (all other outputs) VOH1 CC 0.9 VCC 2.4 V IOH = – 250 mA IOH = – 1.6 mA Input leakage current (Port 5) 1) IOZ1 CC – –200 nA 0 V < VIN < VCC Input leakage current (all other)IOZ2 CC – –500 nA 0 V < VIN < VCC RSTIN pullup resistor RRST CC 50 150 k W – Read inactive current 4) IRH 2) – -40 mA VOUT = VOHmin Read active current 4) IRL 3) -500 – mA VOUT = VOLmax ALE inactive current 4) IALEL 2) – 150 mA VOUT = VOLmax ALE active current 4) IALEH 3) 2100 – mA VOUT = VOHmin XTAL1 input current IIL CC – –20 mA 0 V < VIN < VCC Pin capacitance 5) (digital inputs/outputs) C IO CC – 10 pF f = 1 MHz TA = 25 ˚C Power supply current ICC – 50 + 5 * fCPU mA Reset active fCPU in [MHz] 6) Idle mode supply current IID – 30 + 1.5 * fCPU mA f CPU in [MHz] 6) Power-down mode supply currentIPD –5 0 mA VCC = 5.5 V 7)
1) This specification does not apply to the analog input (Port 5.x) which is currently converted. 2) The maximum current may be drawn while the respective signal line remains inactive. 3) The minimum current must be drawn in order to drive the respective signal line active. 4) This specification is only valid during Reset, or during Hold-mode. 5) Not 100% tested, guaranteed by design characterization. 6) The supply current is a function of the operating frequency. This dependency is illustrated in the figure below. These parameters are tested at VCCmax and 20 MHz CPU clock with all outputs open. 7) All inputs (including pins configured as inputs) at 0 V to 0.1 V or at VCC – 0.1 V to VCC , VREF = 0 V, all outputs (including pins configured as outputs) disconnected. A voltage of V CC ‡ 2.5 V is sufficient to retain the content of the internal RAM during power down mode. Figure 8 Supply/Idle Current as a Function of Operating Frequency
A/D Converter Characteristics VCC = 5 V – 10 %; VSS = 0 V TA = 0 to +70 ˚C for SAB 83C166-5M, SAB 80C166-M TA = -40 to +85 ˚C for SAB 83C166-5M-T3, SAB 80C166-M-T3 4.0 V £ VAREF £ VCC +0.1 V; VSS -0.1 V £ VAGND £ VSS +0.2 V Notes 1) VAIN may exceed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result in these cases will be X000H or X3FFH , respectively. 2) During the sample time the input capacitance C I can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitors to reach their final voltage level within tS. After the end of the sample time tS, changes of the analog input voltage have no effect on the conversion result. The value for the sample clock is tSC = TCL * 32. 3) This parameter includes the sample time tS, the time for determining the digital result and the time to load the result register with the conversion result. The value for the conversion clock is t CC = TCL * 32. 4) This parameter depends on the ADC control logic. It is not a real maximum value, but rather a fixum. 5) TUE is tested at VAREF = 5.0V, VAGND = 0 V, VCC = 4.8 V. It is guaranteed by design characterization for all other voltages within the defined voltage range. 6) During the conversion the ADC’s capacitance must be repeatedly charged or discharged. The internal resistance of the reference voltage source must allow the capacitors to reach their respective voltage level within t CC . The maximum internal resistance results from the CPU clock period. 7) Not 100% tested, guaranteed by design characterization. Parameter Symbol Limit Values Unit Test Condition min. max. Analog input voltage range VAIN SR VAGND VAREF V 1) Sample time tS CC – 2 tSC 2) 4) Conversion time tC CC – 10 tCC + tS + 4TCL 3) 4) Total unadjusted error TUE CC – – 2 LSB 5) Internal resistance of reference voltage source RAREF SR – tCC / 250 - 0.25 kW tCC in [ns] 6) 7) Internal resistance of analog source RASRC SR – tS / 500 - 0.25 kW tS in [ns] 2) 7) ADC input capacitance C AIN CC – 50 pF 7)
External Clock Drive XTAL1 VCC = 5 V – 10 %; VSS = 0 V TA = 0 to +70 ˚C for SAB 83C166-5M, SAB 80C166-M TA = -40 to +85 ˚C for SAB 83C166-5M-T3, SAB 80C166-M-T3 Figure 11 External Clock Drive XTAL1 Memory Cycle Variables The timing tables below use three variables which are derived from registers SYSCON and BUSCON1 and represent the special characteristics of the programmed memory cycle. The following table describes, how these variables are to be computed. Parameter Symbol Max. CPU Clock = 20 MHz Variable CPU Clock 1/2TCL = 1 to 20 MHz Unit min. max. min. max. Oscillator period TCL SR 25 25 25 500 ns High time t1 S R 6 – 6–n s Low time t2 S R 6 – 6–n s Rise time t3 S R – 5 –5n s Fall time t4 S R – 5 –5n s Description Symbol Values ALE Extension tA TCL * <ALECTL> Memory Cycle Time Waitstates tC 2TCL * (15 - <MCTC>) Memory Tristate Time tF 2TCL * (1 - <MTTC>)
AC Characteristics (cont’d) Multiplexed Bus VCC = 5 V – 10 %; VSS = 0 V TA = 0 to +70 ˚C for SAB 83C166-5M, SAB 80C166-M TA = -40 to +85 ˚C for SAB 83C166-5M-T3, SAB 80C166-M-T3 C L (for Port 0, Port 1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF ALE cycle time = 6 TCL + 2tA + tC + tF (150 ns at 20-MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock = 20 MHz Variable CPU Clock 1/2TCL = 1 to 20 MHz Unit min. max. min. max. ALE high time t5 CC 15 + tA – TCL - 10 + tA –n s Address setup to ALE t6 CC 10 + tA – TCL - 15 + tA –n s Address hold after ALE t7 CC 15 + tA – TCL - 10 + tA –n s ALE falling edge to RD, WR (with RW-delay) t8 CC 15 + tA – TCL - 10 + tA –n s ALE falling edge to RD, WR (no RW-delay) t9 CC -10 + tA – -10 + tA –n s Address float after RD, WR (with RW-delay) t10 C C – 5 –5n s Address float after RD, WR (no RW-delay) t11 CC – 30 – TCL + 5 ns RD , WR low time (with RW-delay) t12 CC 40 + tC – 2TCL - 10 + tC –n s RD WR low time (no RW-delay) t13 CC 65 + tC – 3TCL - 10 + tC –n s RD to valid data in (with RW-delay) t14 SR – 30 + tC – 2TCL - 20 + tC ns RD to valid data in (no RW-delay) t15 SR – 55 + tC – 3TCL - 20 + tC ns ALE low to valid data int16 SR – 55 + tA + tC – 3TCL - 20 + tA + tC ns Address to valid data int17 SR – 75 + 2tA + tC – 4TCL - 25 + 2tA + tC ns Data hold after RD rising edge t18 S R 0 – 0–n s Data float after RD t19 SR – 35 + tF – 2TCL - 15 + tF ns Data valid to WR t22 CC 35 + tC – 2TCL - 15 + tC –n s
Data hold after WR t23 CC 35 + tF – 2TCL - 15 + tF –n s ALE rising edge after RD, WR t25 CC 35 + tF – 2TCL - 15 + tF –n s Address hold after RD, WR t27 CC 35 + tF – 2TCL - 15 + tF –n s Parameter Symbol Max. CPU Clock = 20 MHz Variable CPU Clock 1/2TCL = 1 to 20 MHz Unit min. max. min. max.
External Memory Cycle: Multiplexed Bus, With Read/Write Delay, Normal ALE BUS Read Cycle RD Data In Data OutAddress Address t10 Address ALE A17-A16 (A15-A8) BHE BUS Write Cycle WR t5 t16 t17 t6 t7 t25 t27 t18 t19 t14 t12 t10 t22 t23 t12
External Memory Cycle: Multiplexed Bus, With Read/Write Delay, Extended ALE Data OutAddress Data InAddress t10 Address ALE A17-A16 (A15-A8) BHE BUS Read Cycle RD BUS Write Cycle WR t5 t16 t17 t6 t7 t25 t27 t18 t19 t14 t12 t10 t22 t23 t12
External Memory Cycle: Multiplexed Bus, No Read/Write Delay, Normal ALE Data OutAddress Address Data In Address ALE A17-A16 (A15-A8) BHE BUS Read Cycle RD BUS Write Cycle WR t5 t16 t17 t6 t7 t25 t27 t18 t19 t15 t13 t22 t23 t13 t11 t11
External Memory Cycle: Multiplexed Bus, No Read/Write Delay, Extended ALE Data OutAddress Data InAddress Address ALE A17-A16 (A15-A8) BHE BUS Read Cycle RD BUS Write Cycle WR t5 t16 t17 t6 t7 t25 t27 t18 t19 t15 t13 t22 t23 t13 t9 t11 t11
AC Characteristics (cont’d) Demultiplexed Bus VCC = 5 V – 10 %; VSS = 0 V TA = 0 to +70 ˚C for SAB 83C166-5M, SAB 80C166-M TA = -40 to +85 ˚C for SAB 83C166-5M-T3, SAB 80C166-M-T3 C L (for Port 0, Port 1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF ALE cycle time = 4 TCL + 2tA + tC + tF (100 ns at 20-MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock = 20 MHz Variable CPU Clock 1/2TCL = 1 to 20 MHz Unit min. max. min. max. ALE high time t5 CC 15 + tA – TCL - 10 + tA –n s Address setup to ALE t6 CC 10 + tA – TCL - 15 + tA –n s ALE falling edge to RD, WR (with RW-delay) t8 CC 15 + tA – TCL - 10 + tA –n s ALE falling edge to RD, WR (no RW-delay) t9 CC -10 + tA – -10 + tA –n s RD , WR low time (with RW-delay) t12 CC 40 + tC – 2TCL - 10 + tC –n s RD , WR low time (no RW-delay) t13 CC 65 + tC – 3TCL - 10 + tC –n s RD to valid data in (with RW-delay) t14 SR – 30 + tC – 2TCL - 20 + tC ns RD to valid data in (no RW-delay) t15 SR – 55 + tC – 3TCL - 20 + tC ns ALE low to valid data int16 SR – 55 + tA + tC – 3TCL - 20 + tA + tC ns Address to valid data int17 SR – 75 + 2tA + tC – 4TCL - 25 + 2tA + tC ns Data hold after RD rising edge t18 S R 0 – 0–n s Data float after RD rising edge (with RW-delay) t20 SR – 35 + tF – 2TCL - 15 + tF ns Data float after RD rising edge (no RW-delay) t21 SR – 15 + tF – TCL - 10 + tF ns Data valid to WR t22 CC 35 + tC – 2TCL - 15 + tC –n s Data hold after WR t24 CC 15 + tF – TCL - 10 + tF –n s
ALE rising edge after RD, WR t26 CC -10 + tF – -10 + tF –n s Address hold after RD, WR t28 CC 0 + tF –0 + tF –n s Parameter Symbol Max. CPU Clock = 20 MHz Variable CPU Clock 1/2TCL = 1 to 20 MHz Unit min. max. min. max.
External Memory Cycle: Demultiplexed Bus, With Read/Write Delay, Normal ALE Data Out Data In Address ALE A17-A16 A15-A0 BHE BUS (D15-D8) D7-D0 Read Cycle RD Write Cycle t5 t16 t17 t26 t28 t18 t20 t14 t12 t22 t24 t12 BUS (D15-D8) D7-D0 WR
External Memory Cycle: Demultiplexed Bus, With Read/Write Delay, Extended ALE Data Out Data In Address ALE A17-A16 A15-A0 BHE Read Cycle RD Write Cycle t5 t16 t17 t26 t28 t18 t20 t14 t12 t22 t24 t12 BUS (D15-D8) D7-D0 BUS (D15-D8) D7-D0 WR
External Memory Cycle: Demultiplexed Bus, No Read/Write Delay, Normal ALE Data Out Data In Address ALE A17-A16 A15-A0 BHE Read Cycle RD Write Cycle t5 t16 t17 t26 t28 t18 t21 t15 t13 t22 t24 t13 BUS (D15-D8) D7-D0 BUS (D15-D8) D7-D0 WR
External Memory Cycle: Demultiplexed Bus, No Read/Write Delay, Extended ALE Data Out Data In Address ALE A17-A16 A15-A0 BHE Read Cycle RD Write Cycle WR t5 t16 t17 t26 t28 t18 t21 t15 t13 t22 t24 t13 BUS (D15-D8) D7-D0 BUS (D15-D8) D7-D0
AC Characteristics (cont’d) CLKOUT and READY VCC = 5 V – 10 %; VSS = 0 V TA = 0 to +70 ˚C for SAB 83C166-5M, SAB 80C166-M TA = -40 to +85 ˚C for SAB 83C166-5M-T3, SAB 80C166-M-T3 C L (for Port 0, Port 1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF Notes 1) These timings are given for test purposes only, in order to assure recognition at a specific clock edge. 2) Demultiplexed bus is the worst case. For multiplexed bus 2TCL are to be added to the maximum values. This adds even more time for deactivating READY. Parameter Symbol Max. CPU Clock = 20 MHz Variable CPU Clock 1/2TCL = 1 to 20 MHz Unit min. max. min. max. CLKOUT cycle time t29 CC 50 50 2TCL 2TCL ns CLKOUT high time t30 CC 20 – TCL – 5 – ns CLKOUT low time t31 CC 15 – TCL – 10 – ns CLKOUT rise time t32 C C – 5 –5n s CLKOUT fall time t33 C C – 5 –5n s CLKOUT rising edge to ALE falling edge t34 CC 0 + tA 10 + tA 0 + tA 10 + tA ns Synchronous READY setup time to CLKOUT t35 SR 10 – 10 – ns Synchronous READY hold time after CLKOUT t36 SR 10 – 10 – ns Asynchronous READY low time t37 SR 65 – 2TCL + 15 – ns Asynchronous READY setup time 1) t58 SR 20 – 20 – ns Asynchronous READY hold time 1) t59 S R 0 – 0–n s Async. READY hold time after RD, WR high (Demultiplexed Bus) 2) t60 SR 0 0 + 2tA + tF 2)
0 TCL - 25
+ 2tA + tF 2) ns
1) Cycle as programmed, including MCTC waitstates (Example shows 0 MCTC WS). 2) The leading edge of the respective command depends on RW-delay. 3) READY sampled HIGH at this sampling point generates a READY controlled waitstate, READY sampled LOW at this sampling point terminates the currently running bus cycle. 4) READY may be deactivated in response to the trailing (rising) edge of the corresponding command (RD or WR ). 5) If the Asynchronous READY signal does not fulfill the indicated setup and hold times with respect to CLKOUT (e.g. because CLKOUT is not enabled), it must fulfill t37 in order to be safely synchronized. This is guaranteed, if READY is removed in response to the command (see Note 4)). 6) Multiplexed bus modes have a MUX waitstate added after a bus cycle, and an additional MTTC waitstate may be inserted here. For a multiplexed bus with MTTC waitstate this delay is 2 CLKOUT cycles, for a demultiplexed bus without MTTC waitstate this delay is zero. 7) The next external bus cycle may start here. CLKOUT ALE t30 t34 Sync READY t35 t36 t35 t36 Async READY t58 t59 t58 t59 waitstate READY MUX/Tristate 6) t32 t33 t29 Running cycle 1) t31 t37 3) 3) Command RD, WR t60 see 6) 3) 3)
AC Characteristics (cont’d) External Bus Arbitration VCC = 5 V – 10 %; VSS = 0 V TA = 0 to +70 ˚C for SAB 83C166-5M, SAB 80C166-M TA = -40 to +85 ˚C for SAB 83C166-5M-T3, SAB 80C166-M-T3 C L (for Port 0, Port 1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF Parameter Symbol Max. CPU Clock = 20 MHz Variable CPU Clock 1/2TCL = 1 to 20 MHz Unit min. max. min. max. HOLD input setup time to CLKOUT t61 SR 20 – 20 – ns CLKOUT to HLDA high or BREQ low delay t62 CC – 50 – 50 ns CLKOUT to HLDA low or BREQ high delay t63 CC – 50 – 50 ns Other signals release t66 CC – 25 – 25 ns Other signals drive t67 CC -5 35 -5 35 ns
External Bus Arbitration, Releasing the Bus Notes 1) The SAB 80C166 will complete the currently running bus cycle before granting bus access. 2) This is the first possibility for BREQ to get active. CLKOUT HOLD t61 HLDA t63 Other Signals t66 2)BREQ t62
External Bus Arbitration, (Regaining the Bus) Notes 1) This is the last chance for BREQ to trigger the indicated regain-sequence. Even if BREQ is activated earlier, the regain-sequence is initiated by HOLD going high. Please note that HOLD may also be deactivated without the SAB 80C166 requesting the bus. 2) The next SAB 80C166 driven bus cycle may start here CLKOUT HOLD HLDA Other Signals t62 t67 t62 t61 BREQ t63t62