SAB82C215-16-N

SAB82C215 SIEMENS | Alldatasheet

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Data / Address Buffer SAB 82C215 . ™ . of Siemens PC-AT'™ Chipset Advance Information e Address buffer and latch for local CPU- @ += Parity generation / detection logic for and X-address bus interface memory data bus @ Data buffer and latch for local CPU @ CMOS implementation for high speed data bus / memory data bus interface and low power requirements © Bus conversion logic for 16-bit to 8-bit @ 84-pin plastic leaded chip carrier transfers package (PL-CC-84) Siemens PC-AT Chipset a oo. D0-15 MO0-15 245 [_S20-15 ra paeeeueER Eee ape 4 | es | no-23 fT Memory Bus I : | 4 | MA sti . | | A0-23 f 0-9 BIOS E | Vay) i i e 287 | CT, a i | a ex SA1-16 B I HT I} {573 1 [ xeo s l LE LH} | 2x | e042) | Local 4 A0-9 : a j Py ISA LA17-23 Slot Address Busses | #88 Data Busses | 1 2.90

As a member of the Siemens PC-AT Chipset the SAB 82C215 provides address buffer / latch, data bus buffer / latch, data bus path conversion logic and parity logic. The SAB 82C215 data / address buffer, the SAB 82C211 system controller, the SAB 82C212 memory controller and the SAB 82C206 integrated peripheral controller provide a highly integrated high performance system solution for PC-AT compatible systems. The SAB 82C215 is fabricated in Siemens ACMOS technology and packaged in a 84-pin plastic leaded chip carrier package (PL-CC-84).

Ordering Information

Type Ordering code Package Description SAB 82C215-12-N_ | Q67120-P297 PL-CC-84 (SMD) | Data / Address Buffer of Siemens PC-AT Chipset (12 MHz) SAB 82C215-16-N | Q67120-P298 PL-CC-84 (SMD) | Data / Address Buffer of Siemens PC-AT Chipset (16 MHz) Siemens Aktiengesellschaft 2

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Pin Definitions and Functions Symbol Pin input (I) Function Output (O) Address Latch / Buffers IALE Address Latch Enable JALE is the strobe input line of the address latch. It is used to latch the CPU addresses onto the X-address lines. A1 -A16 25-31 vO CPU Address Lines 1 - 16 33 - 411) During CPU cycles (HLDA1 =0) Ai - A16 are the inputs to the internal address latch of the SAB 82C215. During DMA cycles (HLDA1 = 1) A1 — A16 are outputs. The address latch is controlled by IALE. XA1 - XA16_ | 60 - 54 vo XBUS Address Lines 1 - 16 52:- 441) During CPU cycles (HLDA1 =0) XA1 - 16 are the outputs of the address latch. During DMA cycles (HLDA1 = 1) XA1 - 16 are inputs. HLDA1 53 Hold Acknowledge HLDA1 indicates the type of cycle currently executing. CPU cycles are executed with HLDA1 =0. During DMA cycles HLDA1 = 1. HLDA1 controls the direction of the address and data bus transfers. Data Buffers / Latch DO - D15 24, 23 vo CPU Data Bus Lines 0 - 15 . 21-16 DO - D15 represent the local CPU data bus lines. 9-21) The data bus buffers are controlled by HLDA1 and DRD#. i ACO,1 13, 12 ! Action Code Line 0, 1 | The two action code lines control the data path H during CPU and DMA cycles. ACO,1 are qualified i (enabled) by the ACEN# signal. At the Siemens | PC-AT chipset ACO,1 are generated by the SAB i 82C211. | 1) For detailed pin numbers see also pin configuration (figure 2). | Siemens Aktiengesellschaft 4

Pin Definitions and Functions (cont'd) Symbol Pin Input (I) Function Output (0) Data Buffers / Latch ACEN# 14 Action Code Enable# ACEN# =0 validates the action code signals ACO,1. MDO - MD15 | 61 - 63 vO Memory Data Bus 0 - 15 65 - 73 MDO - MD15 are the memory data bus lines. 79 - 821) They are controlled by HLDA1, DRD#, AC1,0 and ACEN#. DRD# 74 Data Read# DRD¢# controls the direction of the data bus buffer ‘ path. DRD#=1 sets the data path from local CPU i bus to memory bus. DRD#=0 sets the data path | from memory to local CPU bus. | DLE 76 ! Data Latch Enable | DLE controls the data bus latch. Memory bus data is stored in the latch with the high-to-low i transition of DLE. : Parity Generator / Checker AO Address Line 0 : AO is used to enable the low byte parity checking. BHE# 1 Byte High Enable# BHE# is used to enable the high byte parity checking. | MP1, MPO 78, 77 fe) Memory Parity Bit 1,0 | MP1 and MPO are the parity bits for the high and | low order bytes of the system DRAM’s. These ; lines are inputs during memory read operations for parity error detection and are outputs during i memory write operations for parity generation. ' PARERR# 83 ° Parity Error# PARERR# =0 indicates that a parity error has been detected during a system memory read operation. At the Siemens PC-AT chipset PARERR# is checked by the SAB 82C211 system controller. 1) For detailed pin numbers see also pin configuration (figure 2). : Siemens Aktiengeselischaft 5

Pin Definitions and Functions (cont'd) Symbol Input (I) Function Output (O Power Supply Voc 32, 42, Power Supply (+5 V) GND 1, 22, Ground (0 V) 43, 64, Figure 3 Block Diagram A1-16 eae XA1 - 16 Latch HLDA1 > DO - 15 PP | Swap MDO - 15 Latch D aK ! Parity anes Co Logic MPout } — PARERR# i ot Control H DRD# Logic | DLE Siemens Aktiengesellschaft 6

The SAB 82C215 data / address buffer for the SIEMENS PC-AT chipset provides the following functional units: e@ Address buffer and latch e Data buffer and latch @ Data bus conversion logic @ Parity generation / detection logic Address Buffer and Latch For local CPU cycles (HLDA1 =0) the SAB 82C215 provides the address buffering and latching between the CPU address lines A1 - A16 and the peripheral bus address lines XA1 - XA16. A1 - A16 can be latched by the address latch enable signal !ALE. The latch is transparent with IALE = high. During DMA cycles (HLDA1 = 1) the peripheral address bus XA1 - XA16 is routed to the A1 - A16 address bus lines. The address latch is not available during DMA cycles. Data Buffer and Latch The SAB 82C215 provides the buffering between the CPU data bus DO - D15 and the memory data bus MDO - MD15 for local cycles (on-board memory read / write cycles) or AT-bus cycles (on-board peripherals or AT-slot read / write cycles). DRD# is the direction control signal for the data buffer. For local write cycles DRD¢# is at high level and sets the data path from the CPU data bus to the memory data bus. For local read cycles DRD#=0 sets the data path from MD-bus to D-bus. DLE controls the data latch. DLE = 1 makes the latch transparent. During local cycles the action code enable signal is inactive (ACEN# = 1). During AT-bus cycles DLE is inactive (low), and instead of DLE the ACEN# signal is used to strobe the data into the data latch. With ACEN#=0 the data latch is transparent and data is stored with the low-to-high transition of ACEN#. During DMA cycles the D-bus of the SAB 82C215 is switched off. During DMA memory write operations (AC1,0 =0,0 and 1,0), the MD-bus lines are connected to the parity generator. If data bus conversion is required during DMA cycles (AC1,0 = 1,0 and 1,1), the corresponding data path is set between MDO - 7 and MD8 - 15. Data Bus Conversion Logic : The SAB 82C215 provides data bus conversion when the 16-bit CPU reads from or writes : to 8-bit devices. It also provides data bus conversion for DMA cycles. Table 1 lists the H possible cases of the data paths for CPU and DMA cycles. The action code signals | AC1, 0, which are qualified by ACEN#, control the different data path configurations. : Siemens Aktiengesellschaft 7

Table 1: Action Code Functions ACI ACO HLDA1 | Operation Data path 1) 0 16-bit Write A-B-D-E and F-G-J-K F-Gu-K ie) 1 16-bit Read E-D-B-A and K-J-G-F 8-bit Low Read K-J-G-F 1 [| 0 | 0 _| &bit High Write to MD-bus low A-B-C-H-J-K 1 [| 1 | 0 | 8-bit Read MD-bus Low to D-bus high | K-J-H-C-B-A

0 MD-bus tristated: -

16-bit/8-bit (low byte) DMA read / write at MD-bus of + Tt fresewes 1 1 High memory Write to MD8 - 15 from K-J-H-C-D-E MDO -7 1 1 1 High memory Read from MD8 - 15 to E-D-C-H-J-K MDO -7 1) see figure 4 Figure 4 Data Bus Conversion Paths Local SAB 82C215 : Memory : cPu Data : Bus Bus i be - 015 “RED KE woe - m0 18 Do - 07 ee MDo - MD7 i : Siemens Aktiengesellschaft 8

Parity Generation / Detection Logic For local memory write cycles the SAB 82C215 generates an even parity bit (MP0, MP1) for each of the two data bytes MDO - 7 and MD8 - 15. The parity bit is set if the corres- ponding data byte has an even number of 1's. During local memory read cycles the SAB 82C215 checks the data bytes for even parity. If a parity error is detected, the PARERR# output becomes active (low). PARERR# is activated by the falling edge of DLE and deactivated by the rising edge of DRD#. For DMA cycles (HLDA1 = 1) the parity checker is disabled. During parity checking AO and BHE# select the data bytes to be checked. SAB 82C215 control lines interface The SAB 82C215 has several control lines. In a PC-AT design using the Siemens PC-AT chipset the interface of the SAB 82C215 control lines is shown in the next figure. Figure 5 Interface of the SAB 82C215 control lines in the Siemens PC-AT Chipset active, if HLDA1 =0 x BHE# SAB cpu Y active, if sas sas i ACO 82021 sc25 | System ["ACEN# Controle SAB DRD# | 820212 | Memory | Controller Siemens Aktiengesellschaft 9

Ambient temperature under bias... 26-26. e ees OF0 70°C Storage temperature 2... cece eee = 6510 +150 °C Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to absolute maximum ratings for extended periods may affect device reliability. DC Characteristics Ta = Oto 70 °C; Voc = +5 V45 %; GND=O0V Parameter Test Input high voltage Vin 2.0 Voc Vv - +0.5 Output low voltage Vo Vv MDO - 15: Io. =8MA other outputs: lo. =4 mA Output high voltage Vou 24 Vv MDO ~ 15: Ion =- 8MA other outputs: Ton =- 4 MA Input leakage current [m |- [+10 |u| 0V<Vin<Voc Output tristate loz +10 pA 0.45 V < Vout < Voc leakage current Standby power supply current | fcose _[- [1.0 [ma_|- Siemens Aktiengesellschaft 10

Ta = 0 to 70 °C; Voc = +5V45 %; GND=0V Parameter [Semeot [ unit wewes [unt Test condition MD-bus tristated after DRD# active [fs | 75 | 24 [ns | - MD-bus valid to D-bus valid [2 | 8 | 185 [ns [- MD-bus being driven after DRD# inactive [ts. | 75 | 28 [ns | - MPO, MP1 being driven after DRD# a ee - inactive D-bus invalid after DRD# inactive le | 4 | 13 [ns | - D-bus tristated after DRD# inactive ls | 6 | 15 [ns | - D-bus valid to MD-bus valid lt | 11 | 19 [ns [- D-bus valid to MP1, MPO valid fe | 11 | 20 [ns |- ACEN# active to D-bus valid [| 16 | 27 [ns | - Action code valid to MO-bus valid ls _| 10 | 19 [ns | - i Action code invalid to MD-bus invalid [to | 11 | 20 [ns | = "DLE inactive to, PARERR# enabled [t, | 17 | 30 [ns [- DRD# inactive to PARERR# disabled [tz | _17 | 28 [ns_|- | TALE active to XA-bus valid lis | 11 | 19 [ns [- | XA-bus valid to A-bus validSAB 82C215-12 fT tp ete - SAB 82C215-15 7 16 - MD, MP setup time to DLE trailingedge [ts | 0 | - [ns_|- MD, MP hold time from DLE trailing edge [te | 6 | - [ns |- : DRD¢# setup time to DLE trailing edge [ir | 12 { - [ns | - | MD-bus hold time from ACEN# fe P78 fe | - | trailing edge | MD-bus valid to MP valid during DMA a ee - | memory write cycle | MD-bus high byte valid to MD low byte fe Pe] ei | - | valid during DMA high memory read cycle | Action code valid to MD high byte valid ef ef ei - i during DMA high memory write cycle j Action code valid to MP valid during DMA fe pr] i | - | high memory write cycle Siemens Aktiengesellschaft 11

DRD# tae tap mea oust ! a H Output For this timing: DLE =1 a CPU Write Timing +} fe tr >| Siemens Aktiengesellschaft 12

' Data Latch Timing (CPU Read) i OLE DRD# MDO - 15 | \\ MPO,1 tis Pt ths | DMA Timing (HLDA1 = 1) i Memory Write Cycle HLDA1 too >] | Siemens Aktiengesellschaft 13

DMA Timing (HLDA1 = 1) Memory Read High Byte / 1/O Write Low Byte HLDA1 / < t, >| DMA Timing (HLDA1 = 1) VO Read Low Byte / Memory Write High Byte | HLDA1 / : — >| tee r ! tag Siemens Aktiengesellschaft 14

ACEN# Timing <— ty ACEN# hg : DRD#=DLE=0 i Action Code Timing i i ACEN#=0 | Siemens Aktiengeselischaft 15

PARERR# Timing DLE DRD# PARERR# j<— ty Adress Latch Timing ALE ms th XA1 - 16 Output <— fia i Siemens Aktiengesellschaft 16

Load Circuit and AC Characteristics Measurement Waveform fhe t TTT TIN FF We TTT Input pV 13v) 2 2 Ton four You Output (Delay) 1.3V 13V, fra fu 13V : tput 1 (Enable/Disable) ‘ron fap Vou i OsV : 13V : Vin=3V, Y= OV, s10ns, f= 5ns Ye do. j R i R ‘ q : , sw2 i i i ' Siemens Aktiengesellschaft 17

Load Circuit Measurement Conditions Parameter Output Type | symbot_| C. (pF) [Riko | Ry (kQ) [sw, | sw, Propagation Totem Pole Delay Time Tristate teu OFF | ON Bidirectional tPHL OFF | ON Propagation Open Drain or tPLH 50 05 OFF Delay Time Open Collector | teu. 50 0.5 OFF Disable Time Tristate teiz 0.5 ON Bidirectional teuz 0.5 OFF | ON Enable Time Tristate tpze 50 0.5 1.0 ON ON Bidirectional tpzH 50 0.5 1.0 OFF ON i i ; Siemens Aktiengeselischaft 18

Plastic Package, PL-CC-84 (SMD) (Plastic leaded chip-carrier) 30.203 29.31.02 Index Marking ; 4 a a | —_ zi. - Fa 8, B _-| [3.27 (0.81 max osnal 4420.3] 35 : Dimensions in mm i i i Siemens Aktiengeselischaft 19

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