Microcontroller

SAB80C32-20-P

Siemens Semiconductor G...

High-Performance 8-Bit Single Chip Microcontroller

Manufacturer: Siemens Semiconductor G...

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SAB80C52 SIEMENS | Alldatasheet

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8-Bit CMOS Microcontroller SAB 80C52/80C32 Preliminary SAB 80C52 CMOS microcontroller with factory-maskprogrammable ROM SAB 80032 CMOS microcontroller for external ROM @ Versions for 12 MHz /16MHz /20 MHz operating frequency @ 8K x 8 ROM (SAB 80C82 only) @ 256 x 8 RAM @ Four 8-bit ports, 32 /O lines @ Three 16-bit timer/event counters @ High-performance full-duplex serial channel with flexible transmit/receive baud rate capability @ External memory expandable up to 128 Kbytes @ Boolean processor @ Most instructions execute in 1 us /750 ns /666 ns @ Multiply and divide in 4 us /3 us /2.7 us © Six interrupt sources, two priority levels @ Idle and power-down operation @ Fully functionally compatible with SAB 8052A/8032A @ Three temperature ranges available: Oto 70°C, — 40 to +85°C, = 40 to +110°C @ P-DIP-40 and P-LCC-44 package Semiconductor Group 351 8.92

SAB_80C51/80C31 RAM RAM =P Pere Bit Timer 2 {sa 80CSt- | ART Timer 1 ‘orel Port 2 Ki > v0 ROM ROM — LB [eek ceotare The SAB 80C52/80C32 is a standalone, high-performance CMOS single-chip microcontroller, designed in Siemens ACMOS technology. It is functionally compatible with the SAB 8052A/ 8032A devices in MYMOS technology. Furthermore, it is backwardly compatible with the SAB 80C51/80C31. The low-power proper- ties of ACMOS technology allow applications where power consumption and dissipation are critical. In addition, the SAB 80C52/80C32 has two software-selectable modes of reduced ac- tivity for further power reduction ~ idle and power-down The SAB 80C52 contains a non-volatile 8 K x 8 read-only program memory, a volatile

256 K x 8 read/write data memory, 32 I/O lines, three 16-bit timer/counters, a six-source, two-

priority-level interrupt structure, a serial I/O port, an on-chip oscillator, and clock circuits. The SAB 80C32 is identical, except that it lacks the program memory on the chip. Semiconductor Group 352

Ordering Information

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Ba 85838 | anaes S885 | psd7 ‘3910 P0.4/aD4 prea Oo 3870 PO.S/ADS e709 3770 P0.6/aD6 rst Gio 361 F0.7/a07 | euo/eso 11 spa Z SAB 80032 a we Gra SAB socse upc 1x0/P3.1 G13, 33) ale | inioyes.2 Gra sz) FSen | inti/e3.3 C15 aif P2.7/a15 ro/e3.4 16 30f) P2.6/a14 T1/P3.5 G17 290 P2.s/ar3 | 18 19 20 21.22 23 24 25 26 27 28 ie B2e2g Pin Configuration (P-LCC-44) Semiconductor Group 355

ol [2 5 e Efes(t RST | 2 } n + ay Rk in — mH SAB - iE “ 80052 5 80032 * Ro — _ + — m— ls wm — J” sl +[% w—+)é Ef s/t : ind |e : i — | a + | wa Logic Symbol Semiconductor Group 356

Pin Definitions and Functions Symbol Pin Number }VO" |Function P-DIP-40 P-LCC-44 P1o-P17 |1-8 29 vo |Port1 is an 8-bit bidirectional I/O port with in- ternal pullup resistors. Port 1 pins that have 1s written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As in- puts, port 1 pins being externally pulled low will source current (Ju, on the DC characteristics) because of the internal pullup resistors. Port 1 also receives the low-order address bytes during program verification. Port 1 also contains the timer 2 pins as a se- condary function. The output latch cor- responding to a secondary function must be programmed to a one (1) for that function to operate. The secondary functions are assigned to the pins of port 1, as follows: — T2(P1.0): Input to counter 2. — T2EX (P1.1): Capture/Reload trigger of timer 2. RST o. 10 |_| Ahigh ievel on this pin for two machine cycles while the oscillator is running re- sets the device. An internal diffused re- sistor to vss permits power-on reset using only an external capacitor to vec. “1 Input 0 = Output Semiconductor Group 357

Pin Definitions and Functions (cont'd) Symbol Pin Number vo” |Function P-DIP-40 P-LCC-44 P3.0-P3.7 10-17 11, «(VO [Port's 13-49 | is an 8-bit bidirectional /O port with in- | |ternal pullup resistors. Port 3 pins that | | |have 1s written to them are pulled high | iby the internal pullup resistors, and in that state can be used as inputs. As in- j puts, port 3 pins being externally pulled | low will source current (J x, on the DC | characteristics) because of the internal pullup resistors. Port 3 also contains the interrupt, timer, serial port and RD and WR pins that are used by various op- | tions. The output latch corresponding to | a secondary function must be program- | med to a one (1) for that function to | operate. The secondary functions are assigned to the pins of port 3, as follows: |= R x Didata (P3.0): Serial port's | | receiver data input (asynchronous) or data input/output (synchronous). | | |~ Tx Diclock (P3.1): Serial port's i | transmitter data output (asynchron- | | ous) or clock output (synchronous). |— INTO (P3.2): Interrupt 0 input or gate control input for counter 0. — INT (P3.3): Interrupt 1 input or gate | control input for counter 1. — TO (P3.4): Input to counter 0. | — T1 (P3.5): Input to counter 1 | | — WR (P3.6): The write control signal | latches the data byte from port 0 into. } the external data memory. — (P3.7): The read control signal | enables external | data memory to port 0 “|= Input O = Output Semiconductor Group 358

Pin Definitions and Functions (cont'd) Symbol Pin Number VO" Function P-DIP-40 P-LCC-44 XTAL1 19 21 VO |XTAL1 XTAL2 18 20 Input to the inverting oscillator amplifier and input to the internal clock generator circuits. XTAL 2 | Output of the inverting oscillator | amplifier. To drive the device from an external | clock source, XTAL1 | should be driven, while XTAL 2 is left | unconnected. There are no require- | ments on the duty cycle of the external clock signal, since the input to the inter- nal clocking circuitry is through a divide- by-two flip-flop. Minimum and maximum high and low times specified in the AC characteristics must be observed. P2.0-P2.7 |21-28 24-31 VO |Port2 is an 8-bit bidirectional /O port with in- ternal pullup resistors. Port 2 pins that | have 1s written to them are pulled high | by the internal pullup resistors, and in that state can be used as inputs. As in- puts, port 2 pins being externally pulled low will source current (/1.. on the DC. | characteristics) because of the internal | pullup resist. | Port 2 emits the high-order address byte during fetches from external program memory and during accesses to exter- nal data memory that use 16-bit ad- dresses (MOVX @DPTR). In this appli- cation it uses strong internal pullup re- sistors when issuing 1s. During accesses to external data memory that use 8-bit addresses (MOVX@Ri), port 2 issues the contents of the P2 special function register. “1 = Input O = Output Semiconductor Group 359

Pin Definitions and Functions (cont'd) Symbol | Pin Number VO" Function |P-DIP-40 | P-LCC-44 { {a PSEN 29 \\32 fe} Program Store Enable This output issues a control signal that enables the external program memory | to access the bus during external fetch | operations. It is activated every six os- | cillator periods, except during external { data memory accesses. Remains high | during internal program execution. ALE 30 33 ° Address Latch Enable | Provides signal used for latching the ad- | |dress into external memory during nor- | mal operation. It is activated every six oscillator periods except during an ex- ‘ternal data memory access. EA 31 35 | | External Access When held at a high level, the SAB | 80C52 executes instructions from the internal ROM when the PC is less than | | 8192. When held at a low level, the SAB. | 80CS2 fetches all instructions from the external program memory. For the SAB 80C32 this pin must be tied low. “Le Input = Output Semiconductor Group 360

Pin Definitions and Functions (cont'd) Symbot [____PinNumber [0 JFunction P-DIP-40 P-LCC-44 PortO is an 8-bit open drain bidirectional I/O port. Port 0 pins that have 1s written to them float, and in that state can be used as high-impedance inputs. Port 0 is also the multiplexed iow-order address and data bus during accesses to external program and data memory. In this application it uses strong internal pullup resistors when issuing 1s. Port 0 also outputs the code bytes during pro- gram verification in the SAB 80C52. Ex- ternal pullup resistors are required dur- ing program verification. Vec 40 44 Supply voltage during normal, idle, and power-down operations. Vss 20 22 Circuit ground potential. NC - 1,12, - No connection | 23, 24 _ i ee — “|= Input O = Output Semiconductor Group 361

a a ea ale eae | \\ i | | 1] oscitator | | program emory aseayte Timervévent | | L] 90d Timing (SAB 80C5 only) Data Memory Counters | 1 ! if 1 | + { | | sae eocsz | i cpu i ! ! 1 { 1 ' | Programmable] | H 64K byte Bus Serial Port | { Expander [4 Programmable 1/0 +Full Duplex UART | { t Controt +Synchronous | | I Shifter 1 H Interrupts | Interrupts Controt Parallel Ports Serial IN Serial OUT Address Data Bus and 1/0 Pins wco00es Figure 1 Block Diagram Semiconductor Group 362

The SAB 80C52/80C32 is functionally compatible with the SAB 8052A/8032A products that are designed in Siemens MYMOS technology. Furthermore, the SAB 80C52/80C32 is backwardly compatible with the SAB 80C51/80C31 devices. In addition, instead of the RAM backup power supply of the SAB 8052A/8032A, the SAB 80C52/ 80C32 offers two additional power contro! modes, the idle mode and the power- down mode. The control bits for the reduced power modes are in the special function register PCON. Idle mode In the idle mode, the CPU puts itself to sleep while all the on-chip peripherals stay active. The instruction that invokes the idle mode is the last instruction executed in the normal operating mode before the idle mode is activated. The contents of the CPU, the on-chip RAM, and all the special function registers remain intact during this mode. The idle mode can be terminated ei- ther by any enabled interrupt, at which time the process is picked up at the interrupt service routine and continued, or by a hardwarere set which starts the processor in the same way as a power-on reset. Power-down mode In the power-down mode the oscillator is stopped, and the instruction that invoke power-down is the last instruction executed, Only the contents of the on-chip RAMis preserved. A hardware reset is the only way to terminate power-down. During power-down and idle mode the external pins will have the following status (see table 1): Semiconductor Group 363

Status of the External Pins during Idle and Power-Down Modes Mode Program Port2 |Port3 Memory | Idle Internal Data/ Data Data/ Alternate Alternate Outputs Outputs Idle External Float Data/ Address Data/ Alternate {Alternate Outputs Outputs Power-Down | Internal Data Data/ Data | Data/ Last Out- ‘Last Out- put of ‘put of Alternate /Alternate Function Function Power-Down | External bY) 0 Float Data/ Data Data/ | Last Out- Last Out- | put of |put of Alternate {Alternate Function Function Instruction Set The SAB 80C52/80C32 has the same instruction set as the industry standard 8051 microcontroller. A pocket guide is available which contains the complete instruction set in functional and hexadecimal order. Furtheron it provides helpful information about Special Function Register, Interrupt Vectors and Assembler Directives. Literature Information Title Ordering No. 7 Microcontroller Family SAB 8051 Pocket Guide B158-B6229-X-X-7600 Semiconductor Group 364

40 to 85 °C (SAB 80C52/80C32-T40/85) —40to 110°C (SAB 80C52/80C32-T40/1 10) Power dissipation ..cccscccssssseseesssnnssenssensesnisensnsesenesinsienseneens 1 W Note Stresses above those listed under "Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Characteristics Vcc =5V+10%; Vss=OV; Ta=0 to 70 °C (SAB 80C52/80C32) Ta =— 40 to 85 "C (SAB 80C52/80C32-T40/85) Ta=-40to 110°C (SAB 80C52/80C32-T40/110) Parameter Symbol | Limit Values Unit Test condition min. | max. Input low voltage Vi ” T v - (except EA) for SAB 80C52/80C32, -05 0.2Voco 80C52/80C32-T40/85 -01 for SAB 80C52/80C32, -05 |0.2Voo- T40/110 j |0.3 Input low voltage (EA) Vin -05 |0.2Veg- |V - 1 0.3 Input high voltage Vin 02Vog 02Veg V I- (except XTAL1, RST) +0.9 +05 | Input high voltage Vinw 0.7 Veo |Veo +05 |v |= (XTAL1, RST) | Output low voltage Vou |- 0.45 Vv fop=1.6mA» (ports 1, 2, 3) | Output low voltage Vou - 0.45 Vo fo, =3.2mA» (port 0, ALE, PSEN) | Output high voltage Vou 2.4Vcc |= V |ron=- 80pA (ports 1, 2, 3) 0.9 lon =- 10pA Notes see page 367 Semiconductor Group 365

DC Characteristics (cont'd) Parameter iSymbol | Limit Values Unit | Test condition Output high voltage Vout 24 Vcc |- VIg.=- 800 pA (port 0 in external bus 09 - IV |Iop=- 80 pA2 mode, ALE, PSEN | Logical 0 input current Te ~50 lv Viy = 0.45 V (ports 1, 2, 3) | Logical 1-to-0 transition I -650 Vo \\Vin=2V current (ports 1, 2, 3) v Input leakage current Tu £10 Ha 10.45 <Vin<Voo (port 0, EA) Reset pulldown resistor Rast 150 KQ |= Pin capacitance Cio — 10 | f<= 1 MHz, Ta= 25°C Power supply current: Active mode, 12 MHz 6 Toc - 20 mA |Voc=5V# Active mode, 16 MHz ©) loo - \\26 mA |Voo=5V" Idle mode,12 MHz ® loc - les mA |Vcco=5V% Idle mode,16 MHz ©) Toc - \\8.4 jmA Voco=5V9 Power Down Mode Teo - 50 WA Veg =2...5.5 V9 Notes see page 367 Semiconductor Group 366

Notes for pages 365 and 366 1) Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed ‘on the Vo, of ALE and ports 1 and 3. The noise is due to external bus capacitance discharg- ing into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus oper- ation. In the worst case (capacitive loading > 100 pF), the noise pulse on ALE line may ex- ceed 0.8 V. In such cases it may be desirable to qualify ALE with a Schmitt-trigger, or use an address latch with a Schmitt-trigger strobe input. 2) Capacitive loading on ports 0 and 2 may cause the Voy on ALE and PSEN to momentarily fall below the 0.9 V cc specification when the address lines are stabilizing. 3) Power-down / gc is measured with: EA = Port 0 = V ¢¢; XTAL1 = V gg; XTAL2 = N.C.; 4) I ¢¢ (active mode) is measured with: XTAL1 driven with clock signal according to the figure below; XTAL2 = N.C.; EA = Port 0 = Vcc; RST = V cc; all other pins are disconnected. To might be slightly higher if a crystal oscillator is used. 5) 1 cc (idle mode) is measured with: XTAL1 driven with clock signal according to the figure below; XTAL2 = N.C.; EA = V gg; Port 0 = Vcc; RST = V gg; alll other pins are disconnected. 6) cc Maxat other frequencies is given by: activemode: Ico Max = 1.5 -fosc: 2.0 idle mode: I6¢ max = 0.4 « fosc 2.0 where fogcis the oscillator frequency im MHz. / cc values are given in mA and measured at Voc = 5 V (see also notes 5 and 6) Semiconductor Group 367

Vec-05 ---—— ‘ 7c tewcx: ousv 02 Yer -04 Fence Pt fae t fon a ae mT 90033 Clock Signal Waveform for / cc Tests in Active and Idle Mode Semiconductor Group. 368

V oo = 5 V 210%; V gg = 0 V; Ta= 0 to 70°C; (SAB 80C52/80C32) Ta=—40to 85°C; (SAB 80C52/80C32 — T40/85) Ta=-40to 110°C; (SAB 80C52/80C32 — T40/110) (C; for port 0, ALE and PSEN outputs = 100 pF; C, for all other outputs = 80 pF) Parameter Symbol Limit values unit

12 MHz clock | Variable clock |

Alt cucy = 0.5 MHzto 12 MHz Program Memory Characteristics ALE pulse width - Ztcac.-40 |- ns Address setuptoALE iayp (43 |- terc.-40 = [ns Address hold after ALE | tax 60 - _{forct -23 |- ns Address to valid tuv - 233 | larocox =100 jns instruction in = ALE to PSEN Ino (58 | = leven -25 |= ns PSEN pulse width IPLPH = Bicic.-35 |- jns PSEN to valid instruction | tpyy - 150 - \\3teic, — 100 [ns Input instruction hold —tpxix «| - jo ns after PSEN | | i Input instruction float jipxiz*) |= 6 tor. 20 ns after PSEN a { Address valid after trxav’) [75 |= tc.c.-8 - ns PSEN | Address to valid taviv 302 0 Sicic.- 115 ns instruction in | Address floattoPSEN |ipaz |- —_—|0 - ° ns *) Interfacing the SAB 80C515A to devices with float times up to 45 ns is permissible. This limited bus contention will not cause any damage to port 0 drivers. Semiconductor Group 369

AC Characteristics (cont'd) _ ~

12 MHz clock Variable clock

1t cucy = 0.5 MHz to 12 MHz External Data Memory Characteristics WR pulse width twuwH | 400 6 tcc, — 100 ns Address hold after ALE [taxa (132 feat ns RDtovaliddatain —lipipy —- 252 = [Steucy ~ 165 |ns Data float after RD tRHoz |- 97 2tcucL.- 70 |ns Address to valid data in |aypy - a5 [|e - 165 | ns high | Address valid to WR or - 4 tcc. - 130 ns RD Data valid to WR tovwx [33 = Ieve. — 50 ns transition | Data setup before WR - 7 teuet — 150 ns Address float atterAD [maz | 0 nis Semiconductor Group 370

AC Characteristics (cont'd) Parameter Symbol Limit values Unit ; Variable clock i } Frequ. = 0.5 MHz to 12 MHz min max. External Clock Drive XTAL1 Oscillator period toi. «(183.3 2000 Ins High time ICHCX 20 ICLOL-ICHOX ns Low time Ioucx. 20 TCLOL-ICHOX Ins Fall time touon = 20 ns Semiconductor Group 371

AC Characteristics (cont'd) V co =5 V 210%; V gg=0V; Ta= 0 to 70°C; (SAB 80C52-16/80C32-16) Ta=—-40to 85°C; (SAB 80C52-16/80C32-16 — T40/85) Ta=—40to 110°C; (SAB 80C52-16/80C32-16 — T40/110) (C for port 0, ALE and PSEN outputs = 100 pF; C, for all other outputs = 80 pF) Parameter Symbol Limit values Unit Variable clock 4t cLey = 0.5 MHz to 16 MHz min [max | min. | max. _—| Program Memory Characteristics ALE pulse width TLHUL 85 2toucL— 40 ns Address setup to ALE ray, 23 tore, - 40 ns Address to valid tlw [- 233 4tcicL- 100 |ns instruction in PSEN pulse width tpipy [153 |= 3icc.-35 |- ns Oo — a — PSEN to valid instruction | rpijy - 150 |- 3icuc. - 100 | ns in Input instruction hold |ipyix 10 - oO ns after PSEN | Input instruction float ipyiz | 63 tou. 15 |ns after PSEN Address valid after tpxay") 60 toc. -3 ns PSEN Address to valid ta’) [= SiccL-90 ns instruction in *) Interfacing the SAB 80C52-16/80C32-16 to devices with float times up to 45 ns permissible. This limited bus contention will not cause any damage to port 0 drivers Semiconductor Group 372

AC Characteristics (cont'd) Parameter Symbol Limit values unit "Variable clock Frequ. = 0.5 MHz to 16 MHz min max. External Clock Drive XTAL1 Oscillator period tcc. «—«(O25 ~~ [2000 ns High time ICHCX ICLCLICHCX ns Low time TeLcx IcLoL-ICHCX ns Fall time toner |= 15 ns Semiconductor Group 374

AC Characteristics (cont'd) V co = 5 V 210%; V gg = OV; Ta= 0 to 70°C; (SAB 80C52-20/80C32-20) Ta=- 40 to 85°C; (SAB 80C52-20/80C32-20 ~ T40/85) Ta=- 40 to 110°C; (SAB 80C52-20/80C32-20 - T40/110) (C for port 0, ALE and PSEN outputs = 100 pF; C, for all other outputs = 80 pF) Parameter Limit values Unit Variable clock 4 cic = 0.5 MHz to 20 MHz Program Memory Characteristics : ALE pulse width THUL [- [tere = 40 ns Address setup to ALE TAVLL - | toe. — 30 ns ‘Address to valid tu - 4icic.— 100 /ns instruction in PSEN pulse width tpipy = (1S 3icic.-35 = ns PSEN to valid instruction |pyy [- 175 3icucp -75 ins in Input instruction hold | tpxix ns after PSEN Input instruction float | tpxiz 40 |= teic.-10 [ns after PSEN Address valid after tpxav') [47 [= tere. - 3 - ns PSEN | Address to valid taviv’) 190 [0 Sicic. 60 |ns instruction in { Address floattoPSEN lipaz |- —|10 |= 0 ns *) Intertacing the SAB 80C52-20/80C32-20 to devices with float times up to 45 ns permissible. This limited bus contention will not cause any damage to port 0 drivers Semiconductor Group 378

AC Characteristics (cont'd) _ - .

20 MHz clock Variable clock

4t uct = 0.5 MHz to 20 MHz External Data Memory Characteristics WR pulse width twuwH 20000 = 6 tect - 100 ns Address hold after ALE |1Laxo ot ns AD to valid datain——taipv 88 Step = 165 |ns Data hold after AD taux 0 - 0 = ns Data float after RD URHpz it 140 2tcic.— 60 |ns Address to valid data in taypy 205 |= Btcucy - 1685 | ns Adress valid to WR or |iaywt Pf ferme | ns { | WR or RD high to ALE lw terc.-30—licuch +30 [ns ig! | | Data valid to WR ltawwx 5 \\- tovc. - 45 - Ins transition | Data setup before — Trac-150 |- ns Data hold after WR twaox [10 |= [ic -40 Fs Semiconductor Group 376

‘AC Characteristics (cont'd) Parameter Limit values Unit ~ ~ Variable clock : Frequ. = 0.5 MHz to 20 MHz min max. External Clock Drive XTAL1 Oscillator period toro. [50 2000 7 " | ns High time tcHex | 12 ICLCLICHCX ns Low time Iecx. 112 TeLCLICHOX ins Rise time - 12 ns Fall time tcuce | 12 ns Semiconductor Group 377

ROM Verification Characteristics Ta= 25°C 25°C; Vog = 5 V + 10%; Veg = OV Parameter Symbol | Limit values Unit ae min a _ max. ROM Verification Address to validdataliayqy [- 48 fovcL ns ENABLE to validdata’ |teqy — |- 48 IcLoL Ins Data float after ENABLE ieyoz (0 48 toLcL Ins two Porto tee “ey 27 [— ENABLE wcpons4s Address: P1.0-P1.7 =A0-A7 Inputs: P2,5-P2.6,PSEN = 1g P2.0-P2.4 = AB-A12 ALE, EA =Vu Data: Porto = DO-D7 RST = Vn ROM Verification Semiconductor Group 378

ay fae trom — fan tow fw PSEN q oxav tome = fox - hs09 — weT00808 Program Memory Read Cycle ALE aa RD ay ton Taow Powe = cs , =f ron 0 48 oy SRR KP —$ff vie nC Tin bcs >< teow favo Data Memory Read Cycle Semiconductor Group 379

ita 7] PSEN we ey fave l fee | hance tuna RO-AT_tram SOL AOAT inate Pero Cer ope” tote oor KX Ee >< a Data Memory Write Cycle i 1923) External 19/24) —. XTALt Oscittator XTALY | Signal S05-12MH2 OS-1oMHe i 1920 (20) B20 TAL 2 wc 0201 rate C=30pF 10pF vcsoupm Crystal Oscillator Mode Driving from External Source Pin numbers in (. ..) are for PL-CC-44 package Recommended Oscillator Circuits Semiconductor Group 380

Yec-5 ~~~ == re Foncx | ausy 02 Ver -04 tone tox feuck fou nero0033 External Clock Cycle Vee-05 0.2V; +09 _—=> Test Points 0. 2Ve 5 - 01 o4sy at | Mc700037 AC Inputs during testing are driven at Voc - 0.5 V for a logic 1" and 0.45 V for a logic ‘0. Timing measure- ments are made at Vipjmin f0r a logic "1" aNd Vi max for a logic 0" AC Testing: Input, Output Waveforms i | Vioan #01V Voy -O1V > ~._ Timing Reference Yoon -_" Ponts Vioag -01V Vo, +01 mcro0038 For timing purposes a port pin is no longer floating when a 100. mV change from load voltage occurs and begins to float when a 100 mV change from the loaded V o}/Vq level occurs. Jou!ion > +20 mA AC Testing: Float Waveforms Semiconductor Group 381

Product Information

SAB80C32-20-P specifications and overview.

Summary

High-Performance 8-Bit Single Chip Microcontroller

Description

High-Performance 8-Bit Single Chip Microcontroller

Source title SAB80C32-20-P Datasheet(PDF) - Siemens Semiconductor Group

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