SAB8088-1-P

SAB8088 SIEMENS | Alldatasheet

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SAB 8088 5 MHz SAB 8088-1 10 MHz SAB 8088-2 8 MHz ® 8-bit data bus interface @ 8-bit and 16-bit signed and unsigned arithmeticin @ 16-bit internal architecture binary or decimal, including multiply and divide © Direct addressing capability to © Clock rates:

1 Mbyte of memory 5 MHz for SAB 8088

© Software compatible with SAB 8086 8 MHz for SAB 8088-2 . ps . 10 MHz for SAB 8088-1 @ 14-word by 16-bit register set with ible with i symetrical operations bd compape iD industry standard ape8 e lock ti @ Available in a 40-pin plastic dual-in-line e Byte. word and block operations package (P-DIP-40) or in a plastic leaded chip pera 9 carrier package (PL-CC-44) Pin Configuration HIN fray P-DIP-40 MODE ‘(MODE PL-CC-44 cno1 407] vec au(]2 39[ J ats, a 2 Fa aBly3 36 [7] Ateis3 ERLE Rz vl Zee an(]s 36, ] A1B/SS: Ai d7 O 39D Ats/S6 ans 38 [J awiss aoe 3611550 __ as(]7 361 a0 (HIGH) wn ie b o aeCfa 33 MN Ave Gt SAB 35[THOLD ao7L]9 3210 ADs (12 8088 34 PP HLOA aosC]o gay EHOW OST ane 43 8088-2 3p me 8088-2 Rae ans — 32p1101 aosC]n 5008.) Pinto are) ap2 15 por Ape] 12 pm dor ADI He sof nc A033 zeiom (52) 400017 290) DEN p20] ao si) 18 19 20 21 22 23 % 25 apy (415 » 2 ]DEN (50) SEESZ SR SEES ano C6 Ae (aso) eee 8 ek noi (C]17 2 PNTA (ast) INTRO] 8 23 test cak(]9 22 [READY Guo] 20 21 Reset SAB 8088 is a high-performance 8-bit microprocessor implemented in +5V advanced Siemens MYMOS technology, packaged in a 40-pin plastic dual-in-line package (P-DIP-40) or in a 44-pin plastic leaded chip carrier package (PL-CC-44). It is 100 percent compatible with the industry standard 8088. With features like string handling, 16-bit arithmetic with multiply and divide it significantly increases system performance. It is highly suited for multi-processor applications in various configurations. Siemens Aktiengesellschaft 101 8.88

Pin Definitions and Functions The following pin definitions are for SAB 8088 systems in either minimum or maximum mode. The “local bus” in these descriptions is the direct multiplexed bus interface connection to the SAB 8088 (without regard to additional bus buffers). AD7—ADO 9-16 VO ADDRESS DATA BUS These lines constitute the time multiplexed memory I/O address (T1} and data (T2, T3, Tw, and T4) bus. These lines are active high and float to tristate off during interrupt acknowledge and local bus “hold acknowledge”. A15—A8 39, 2-8 ADDRESS BUS These lines provide address bits 8 through 15 for the entire bus cycle (T1—T4). These lines do not have to be latched by ALE to remain valid. A15—A8 are active high and float to tristate off during interrupt acknowledge and local bus “hold acknowledge”. A19/S6, A18/S5, | 34-38 ADDRESS/STATUS A17/S4, A16/S3 During T1, these are the four most significant address lines for memory operations. During I/O operations, these lines are low. During memory and I/O operations, status information is available on these lines during T2, T3, TW and T4. S6 is always low. The status of the interrupt enable flag bit (S5) is updated at the beginning of each clack cycle. S4 and S3 are encoded as shown, 0 0 Alternate Data Oo 1 Stack 1 0 Code or None 1 1 Data This information indicates which segment register is presently being used for data accessing. These lines float to tristate off during local bus “hold acknowledge”. RD READ Read strobe indicates that the processor is performinga _ memory or I/O read cycle, depending on the state of the 10/M pin or $2. This signal is used to read devices which reside on the SAB 8088 local bus. RD is active low during T2, T3 and TW of any read cycle, and is guaranteed to remain high in T2 until the SAB 8088 local bus has floated. This signal floats to tristate off in “hold acknowledge”. READY 22 READY This is the acknowledgement from the addressed memory or I/O device that it will complete the data transfer. The RDY signal from memory or I/O is synchronized by the SAB 8284A/ 8284B clock generator to form READY. This signal is active high. The SAB 8088 READY input is not synchronized. Correct operation is not guaranteed if the setup and hold times are not met. Siemens Aktiengesellschaft 102

a Pin Definitions and Functions (cont'd) Symbol en Beet oy [Function INTR INTERRUPT REQUEST This is a level triggered input which is sampled during the last clock cycle of each instruction to determine if the processor should enter into an interrupt acknowledge operation. Asubroutine is vectored to via an interrupt vector lookup table located in system memory. It can be internally masked by software resetting the interrupt enable bit. INTR is internally synchronized. This signal is active high. TES TEST This input is examined by the “wait for test” instruction. If the TEST input is low, execution continues, otherwise the processor waits in an “idle” state. This input is synchronized internally during each clock cycle on the leading edge of CLK. NMI 7 NON-MASKABLE INTERRUPT This is an edge triggered input which causes a type 2 interrupt. A subroutine is vectored to via interrupt vector lookup table located in system memory. NMI is not maskable internally by software. A transition from low to high initiates the interrupt at the end of the current instruction. This input is internally synchronized. RESET 21 RESET Causes the processor to immediately terminate its present activity. The signal must be active high for at least four clock cycles. It restarts execution, as described in the instruction set description, when RESET returns low. RESET is internally synchronized. CLK CLOCK Provides the basic timing for the processor and bus controller. itis asymmetric with a 33% duty cycle to provide optimized internal timing. Ve Io [= rower surety trav MN/MX MINIMUM/MAXIMUM Indicates what mode the processor is to operate in. The two modes are discussed in the following sections. Siemens Aktiengesellschaft 103

Pin Definitions and Functions (cont'd) The following pin descriptions are for the SAB 8088 minimum mode (i.e. MN/MX = Vcc). Only the pin functions which are unique to minimum mode are described; all other pin functions are as already described. Symbol fem | Oe oy | Function 10/M 28 STATUS LINE __ Is an inverted maximum mode S2. It is used to distinguish a memory access from an I/O access. IO/M becomes valid in the T4 preceding a bus cycle and remains valid until the final T4 of the cycle (I/O = high, M = low). |O/M floats to tristate off in local bus “‘hold acknowledge”. wR WRITE The write strobe indicates that the processor is performing awrite memoryor write I/O cycle depending on the state of the 10/M signal. WR is active for T2, T3, and TW of any write cycle. Itis active low, and ftoats to tristate off in local bus “hold acknowledge”. INTA INTERRUPT ACKNOWLEDGE Is used as a read strobe for interrupt acknowledge cycles. It is active low during T2, T3, and TW of each interrupt acknowledge cycle. ALE ADDRESS LATCH ENABLE Is provided by the processor to latch the address into the SAB 8282 /8282A/8283/8283A address latch. It is a high pulse active during clock low of T1 of any bus cycle. Note that ALE is never floated. DT/R 27 DATA TRANSMIT/RECEIVE ls needed in a minimum system that desires to use an SAB 8286/8286A/8287/8287A data bus transceiver. It is used to control the direction of data flow through the transceiver. Logically, DT/R is equivalent to $1 in the maximum mode, and its timing is the same as for 1O/M (T = high, R = low). This signal floats to tristate off in local “hold acknowledge”. DEN 26 DATA ENABLE \\s provided as an output enable for the SAB 8286/8286A/ 8287/8287A in a minimum system which uses the transceiver. DEN is active low during each memory and I/O access, and for INTA cycles. For a read or INTA cycle, it is active from the middle of T2 until the middle of T4, while for a write cycle, it is active from the beginning of T2 until the middle of T4. DEN floats to tristate off during local bus “hold acknowledge”. HOLD, HLDA Ze) HOLD Indicates that another master is requesting a local bus “hold”. To be acknowledged, HOLD must be active high. The processor receiving the “hold” request will issue HLDA (high) as an acknowledgement, in the middle of a T4 or T1 clock cycle. Simultaneous with the issuance of HLDA the processor will float the local bus and control lines. After HOLD is detected as being low, the processor lowers HLDA, and when the processor needs to run another cycle, it will again drive the local bus and control lines. HOLD is not an asynchronous input. External synchronization should be provided if the system cannot otherwise guarantee the setup time. Siemens Aktiengesellschaft 104

Pin Definitions and Functions (cont'd) $s0 34 STATUS LINE _ It is logically equivalent to SO in the maximum mode. The combination of SSO, 1O/M and DT/R allows the system to completely decode the current bus cycle status. 1o/M_| DT/R [sso | Characteristics 1 0 it) Interrupt Acknowledge 1 oO 1 Read I/O Port 1 1 i?) Write I/O Port 1 1 1 Halt 0 oO i) Code Access VY) 0 1 Read Memory (o) 1 i) Write Memory i} 1 1 Passive Siemens Aktiengesellschaft 105

a Pin Definitions and Functions (cont'd) The following pin descriptions are for the SAB 8088/8288 system in maximum mode (i.e. MN/MX = GND). Only the pin functions which are unique to maximum mode are described. All other pin functions are as already described. symbol fem | Beto) | Function $2, 51,50 28-26 STATUS Is active during clock high of T4, T1, and T2, and is returned to the passive state (1,1,1) during T3 or during TW when READY is high. This status is used by the SAB 8288/8288A bus controller to generate all memory and I/O access control signals. Any change by S2, $1, or SO during T4 is used to indicate the beginning of a bus cycle, and the return to the passive state in T3 or TW is used to indicate the end of a bus cycle. These signals float to tristate off during “hold acknowledge”. During the first clock cycle after RESET becomes active, these signals are active high. After this first clock, they float . to tristate off. 82 [x |x | Characteristics Oo 0 0 Interrupt Acknowledge 0 0 1 Read I/O Port 0 1 0 Write 1/0 Port i) 1 1 Halt 1 0 0 Code Access

1 Q 1 Read Memory

RQ/GT1 Vo Pins are used by other local bus masters to force the processor to release the local bus at the end of the processor's current bus cycle. Each pin is bidirectional with RO/GTO having higher priority than RO/GT1. RO/GT has an internal pullup resistor so may be left unconnected. The request/grant sequence is as follows (see page 38): 1. A pulse of one CLK wide from another local bus master indicates a local bus request (“hold”) to the SAB 8088 (pulse 1). 2. During a T4 or T1 clock cycle, a pulse one clock wide from the SAB 8088 to the requesting master (pulse 2), indicates that the SAB 8088 has allowed the local bus to float and that it will enter the “hold acknowledge” state at the next CLK. The CPU’s bus interface unit is disconnected logically from the local bus during “hold acknowledge”. The same rules as for HOLD/HOLDA apply as for when the bus is released. 3. A pulse one CLK wide from the requesting master indicates to the SAB 8088 (pulse 3) that the “hold” request is about to end and that the SAB 8088 can reclaim the local bus at the next CLK. The CPU then enters T4. Each master-master exchange of the local bus is a sequence of three pulses. There must be one idle CLK cycle after each bus exchange. Pulses are active low. Siemens Aktiengesellschaft 106

Pin Definitions and Functions (cont'd) Symbol Seo) Function If the request is made while the CPU is performing a memory cycle, it will release the local bus during T4 of the cycle when all the following conditions are met: 1. Request occurs on or before T2. 2. Current cycle is not the low byte of a word. 3. Current cycle is not the first acknowledge of an interrupt acknowledge sequence. 4. A locked instruction is not currently executing. If the local bus is idle when the request is made the two possible events will follow: 1, Local bus will be released during the next clock. 2. Amemory cycle will start within 3 clocks. Now the four rules for a currently active memory cycle apply with condition number 1 already satisfied. LOCK LOCK Indicates that other system bus masters are not to gain control of the system bus while LOCK is active (low). The LOCK signal is activated by the “LOCK” prefix instruction and remains active until the completion of the next instruction. This signal is active low, and floats to tristate off in “hold acknowledge”. Qs1, QSO 24,25 QUEUE STATUS Provide status to allow external tracking of the internal SAB 8088 instruction queue. The queue status is valid during the CLK cycle after which the queue operation is performed. ast [aso [characteristics 0 0 No Operation 0 1 First Byte of Op Code from Queue 1 0 Empty the Queue 1 1 Subsequent Byte from Queue = [ajo Pin 34 is always high in the maximum mode. Siemens Aktiengesellschaft 107

a Block Diagram as | | \\ | / | | LAX | | | [+] Instruction | | B-Bus Stream | | ore | | ore | | | | oe ! | | | | | | \\ | | System | I | | A-Bus | | ] | | | | | tage Unt | | | Logic Unit I | | : co | | | | | | | ~* | | S a | Loe HI Siemens Aktiengesellschaft 108

The processor provides a 20-bit address to memory which locates the byte being referenced. The memory is organized as a linear array of up to 1 million bytes, addressed as 00000(H) to FFFFF(H). The memory is logically divided into code, data, extra data, and stack segments of up to 64 Kbytes each, with each segment falling on 16-byte boundaries. All memory references are made relative to base addresses contained in high-speed segment registers. The segment types were chosen based on the addressing needs of programs. The segment register to be selected is automatically chosen according to the rules of the following table. Allinformation in one segment type shares the same logical attributes (e.g. code or data). By structuring memory into relocatable areas of similar characteristics and by automatically selecting segment registers, programs are shorter, faster, and more structured. Word (16-bit) operands can be located on even or odd address boundaries. For address and data operands, the least significant byte of the word is stored in the lower valued address loca- tion and the most significant byte in the next higher address location. The BIU will automati- cally execute two fetch or write cycles for 16-bit operands. Certain locations in memory are reserved for specific CPU operations. Locations from addres- ses FFFFOH trough FFFFFH are reserved for operations including a jump to the initial system initialization routine. Following RESET, the CPU will always begin execution at location FFFFOH where the jump must be located. Locations O0000H through 003FFH are reserved for interrupt operations. Four-byte pointers consisting of a 16-bit segment address and a 16-bit offset ad- dress direct program flow to one of the 256 possible interrupt service routines. The pointer elements are assumed to have been stored at their respective places in reserved memory prior to the occurrence of interrupts. Memory Organization FFFFFH t 4 ) 2 || po" Segment [ L XXXXOH [FF _ pStack Segment ot | | Se Re Fil jegment soe ile » | bata Segment ee a a | un Data Segment LT wooo Siemens Aktiengesellschaft 109

a Minimum and Maximum Modes The requirements for supporting minimum and maximum mode in SAB 8088 systems are sufficiently different that they cannot be met efficiently with 40 uniquely defined pins. Conse- quently, the SAB 8088 is equipped with a strap pin (MN/MX) which defines the system confi- guration. The definition of a certain subset of the pins changes, dependent on the condition of the strap pin. When the MN/MX pin is strapped to GND, the SAB 8088 defines pins 24 through 31 and 34 in maximum mode. When the MN/MxX pin is strapped to VCC, the SAB 8088 gene- rates bus control signals itself on pins 24 through 31 and 34. The minimum mode SAB 8088 can be used with either a multiplexed or demultiplexed bus. The multiplexed bus configuration is compatible with the SAB 8085A multiplexed bus peripherals (e.g. SAB 8155) and provides the user with a minimum chip count system. This architecture provides the SAB 8088 processing power in a highly integrated form. The demultiplexed mode requires one latch (for 64K addressability) or two latches (for a full megabyte of addressing). A third latch can be used for buffering if the address bus loading Tequires it. An SAB 8286/8286A or SAB 8287/8287A transceiver can also be used if data bus buffering is required. The SAB 8088 provides DEN and DT/Rto control the transceiver, and ALE to latch the addresses. This configuration of the minimum mode provides the standard demultiplexed bus structure with heavy bus buffering and relaxed bus timing requirements. The maximum mode employs the SAB 8288/8288A bus controller. The SAB 8288/8288A decodes status lines SO, $1, and $2, and provides the system with all bus control signals. Moving the bus control to the SAB 8288/8288A provides better source and sink current capability to the control lines, and frees the SAB 8088 pins for extended large system features. Hardware lock, queue status, and two request/grant interfaces are provided by the SAB 8088 in maximum mode. These features allow coprocessors in local bus and remote bus configurations. Bus Operation The SAB 8088 address/data bus is broken into three parts — the lower eight address/data bits (ADO-AD7), the midle eight address bits (A8-A15), and the upper four address bits (A16-A19). The address/data bits and the highest four address bits are time multiplexed. This technique provides the most efficient use of pins on the processor, permitting the use of a standard 40 lead package. The middle eight address bits are not multiplexed, i.e. they remain valid throughout each bus cycle. In addition, the bus can be demultiplexed at the processor with a single address latch if a standard, non-multiplexed bus is desired for the system. Each processor bus cycle consists of at least four CLK cycles. These are referredto as 11,12, T3 and T4. The address is emitted from the processor during T1 and data transfer occurs on the bus during T3 and T4. T2 is used primarily for changing the direction of the bus during read operations. In the event that a “NOT READY” indication is given by the addressed device, wait states (TW) are inserted between T3 and T4. Each inserted wait state is of the same duration as a CLK cycle. Periods can occur between SAB 8088 driven bus cycles. These are referred to as “idle” states (Ti), or inactive CLK cycles. The processor uses these cycles for internal house- keeping. During T1 of any bus cycle, the ALE (address latch enable) signal is emitted (by either the processor or the SAB 8288/8288A bus controller, depending on the MN/MxX strap). At the trailing edge of this pulse, a valid address and certain status information for the cycle may be latched. Siemens Aktiengesellschaft 110

(4+N WAT) fy (4+N WAIT) =f, m1 | 12] 13 | wm] m1 | 12 | 13 | tw 1 CLK Goes Inactive in the State ALE just Prior to 4 82-50 ADOR AIS-A8 AIS-AB ADDR, Bus Reservedlf 07-00) owe __ Xtra {estar tap--~-47-AY ate Outor-00))-—-{ RD.INTA \\ rd READY ey | KK NN WAIT DI/R DEN | f-Memory Access Time: WR \\ / Siemens Aktiengesellschaft 114

a Status bits 50, $1, and $2 are used, in maxi- _ Status bits $3 through S6 are multiplexed mum mode, by the bus controller to identify with highorder address bits and are therefore the type of bus transaction according to the valid during T2 through T4. S3 and S4 following table: indicate which segment register was used for this bus cycle in forming the address accord- ing to the following table: $2 [si [50 | Characteristics o(Low) 0 {0 | Interrupt Acknowledge s4 [sx | Characteristics ° : 4 feed yo 0 (Low) 0 Alternate Data 0 1 3/1) |ealt (extra segment) 1(High) [0 0 | Instruction Fetch oT. 1 Stack 1 0 |1. |Read Data from Memory _‘! (High) ° Code or None 1 1 |0 |Write Data to Memory 1 Data 1 1 1 Passive (no bus cycle) $5 is a reflection of the PSW interrupt enable bit. S6 is always equal to 0. I/O Addressing In the SAB 8088, I/O operations can address up to a maximum of 64K I/O registers. The 1/0 address appears in the same format as the memory address on bus lines A15 to AO. The address lines A19 to A16 are zero in I/O operations. The variable I/O instructions, which use register DX as a pointer have full address capability, while the direct I/O instructions directly address one ortwo ofthe 256 I/O byte locations in page 0 of the I/O address space. I/O ports are addressed in the same manner as memory locations. Design engineers familiar with the SAB 8085 or upgrading an SAB 8085 design should observe that the SAB 8085 addresses I/O with an 8-bit address on both halves of the 16-bit address bus. The SAB 8088 uses a full 16-bit address on its lower 16 address lines. System Components Support Circuits SAB 8282/8282A Octal Latch SAB 8283/8283A Octal Latch (inverting) SAB 8284A/8284B Clock Generator and Driver SAB 8286/8286A Octal Bus Transceiver SAB 8287/8287A Octal Bus Transceiver (inverting) SAB 8288/8288A Bus Controller SAB 8289 Bus Arbiter SAB 82594 Programmable Interrupt Controller Typical Applications The SAB 8088 is a general-purpose 8-bit micro processor which can be used for applications ranging from process control to data processing. The next page shows typical system configu- rations for SAB 8088 familiy components. Siemens Aktiengesellschaft 112

Minimum Mode SAB 8088 Typical System Configuration e cenetie | —~]ots HWA] ol [eee ca) - — SApEaIGA Reset RO - - 7 wal - 4 a

1 Wot 1 SAB

1 State | Ed

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1 Woit ve 2A

ioe} —— . TT | saa +t a0-a07] Bea KACBRIOATE >) eae Tears wr it T iain UM [2 EN WE CSO TEC] [TS RO we axe8 SAB 76 wo sae ste RAM EPROM Peripherals 50h Interrupt Centre i__ nr KC RoR? Siemens Aktiengesellschaft 113

a Instruction Set Summary Data Transfer MOV = Move: 76543210 76543210 76543210 76543210 Immediate to register/memory Register/memory to segment register PUSH = Push: Register/memory POP = Pop: Segment register XCHG = Exchange: Register with accumulator IN = Input from: Variable port ' Siemens Aktiengesellschaft 114

a OUT = Output to: 76543210 76543210 76543210 76543210 Variable port XLAT = Translate byte to AL LDS = Load pointer to DS LES = Load pointer to ES LAHF = Load AH with flags SAHF = Store AH into flags PUSHF = Push flags Arithmetic ADD = Add: Immediate to register/memory [Fooc00sw|moaooar/m| date [devaitsw=0] . ADC = Add with carry: immediate register memory Immediate to accumulator INC = Increment: Aegitar merry AAA = ASCII adjust for add DAA = Decimal adjust for add Siemens Aktiengesellschaft 415

SUB = Subtract: 76543210 76543210 76543210 76543210 agen and reise othe Immediate from register/memory Immediate from accumulator SBB = Subtract with borrow: Reg./memory and register to either Immediate from register/memory Inmates DEC = Decrement: 76543210 76543210 76543210 76543210 Register NEG = Change sign CMP = Compare: Register/memory and register immediate with register/memory Inmate ts sce AAS = ASCII adjust for subtract DAS = Decimal adjust for subtract MUL = Multiply (unsigned) IMUL = Integer multiply (signed) AAM = ASCII adjust for multiply DIV = Divide (unsigned) IDIV = Integer divide (signed) AAD = ASCII adjust for divide CBW = Convert byte to word ‘CWD = Convert word to double word Siemens Aktiengesellschaft 116

Logic 76543210 76543210 76543210 76543210 SHL/SAL = Shift logical/arithmetic left SHR = Shift logical right * SAR = Shift arithmetic right ROL = Rotate left ROR = Rotate right ACL = Rotate through carry flag left RCR = Rotate through carry flag right AND = And: Reg./memory and register to either Immediate to register/memory Immediate to accumulator TEST = And function to flags, no result: Register/memory and register Immediate dat and cegister/memory [1111014w| mod000e/m| data | Gataitwot | Immediate data and accumulator ‘OR = Or: tmanedite to rgitar/marnory XOR = Exclusive Or: Reg./memory and register to either Immediate to register/memary Siemens Aktiengesellschaft 117

String Manipulation 76543210 76543210 76543210 REP = Repeat MOVS = Move byte/word MPS = Compare byte/word . LODS = Load byte/word to AL/AX STOS = Store byte/word from AL/A Control Transfer CALL = Calt: Indirect within segment JMP = Unconditional jump: Indirect intersegment Siemens Aktiengesellschaft 118

RET = Return from CALL: 76543210 76543210 76543210 Within seg. adding immediate to SP Intersegment JL/INGE = dump on less/not greater JLE/JNG = Jump on less or equal/not greater JB/JNAE = jump. on below/not above JBE/JNA = Jump on below or equal/ not above JNE/JNZ = Jump on not equal/not zero JNL/JGE = dump on not less/greater JNLE/JG = dump on not less or equal/ JNB/JAE = dump on not below/above JNBE/JA = dump on not below or JNP/JPO = Jump on not parity/parity JNS = Jump on not sign LOOP = Loop CX times LOOPZ/LOOPE = Loop while zero/equal LOOPNZ/LOOPNE = Loop awhile not JCXZ = Jump on CX zero Siemens Aktiengesellschaft 119

a INT = Interrupt 76543210 76543210 Processor Control CLC = Clear carry CMC = Complement carry CLD = Clear direction STD = Set direction STI = Set interrupt WAIT = Wait LOCK = Bus lock prefix Siemens Aktiengesellschaft 120

a Notes: AL = 8-bit accumulator if mod = 11 then r/m is treated as a REG field AX = 16-bit accumulator if mod = 00 then DISP = 0*, disp-low and disp-high CX = Count register ; are absent ; | DS = Data segment if mod = 01 then DISP = disp-low sign-extended to ES = Extra segment ; 16-bits, disp high is absent Above/below refers to unsigned value. if mod = 10 then DISP = disp-high: disp low Greater = more positive; if r/m = 000 then EA = (BX) + (SI) + DISP Less = less positive (more negative) signed values if r/m = 001 then EA = (BX) + (DI) + DISP if d = 1 then “to” reg; if d = 0 then “from” reg if r/m = 010 then EA = (BP) + (SI) + DISP ifw= 1then word instruction; ifw = 0 then byte if r/m = 011 then EA = (BP) + (DI) +DISP instruction - . if r/m = 100 then EA = (SI) + DISP if s:w = 01 then 16-bits of immediate data from ifr/m = 101 then EA = (DI) + DISP me operand diate data byte is si if r/m = 110 then EA = (BP) + DISP* its:w = 11 then an immediate data byte is sign if r/m = 111 then EA = (BX) + DISP . extended to form the 16-bit operand DISP follows 2nd byte of instruction (before data if if v= 0 then “count” = 1; if v = 1 then “count” in ired) (CL) require x = don’t care ; I for stri imiti force arsion with * except if mod = 00 and r/m = 110 then EA = zis used for string primitives for comparsir disp-high:disp-low. REG is assigned according to the following table Segment Override Prefix 16-bit (w=1) 8-bit (w=0) Segment 001reg 110 000 AX 000 AL 00 ES

001 CX 001 CL 01 CS

010 DX 010 DL 10 SS

011 BX 011 BL 11: DS

100 SP 100 AH

101 BP 101 CH

110 SI 110 DH

111 DI 111 BH

Instruction which reference the flag register file as a 16-bit object use the symbol FLAGS to represent the file: FLAGS = X:X:X:X:(OF):(DF):(IF):(TF):(SF):(ZF): X:(AF):X:(PF):X:(CF) Siemens Aktiengesellschaft 121

Ambient temperature under bias Oto 70°C Storage temperature —65to+150°C Voltage on any pin with respect to ground —1.0to +7V Power dissipation 2.5W Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Characteristics SAB 8088: T, = 0 to 70°C, Voc = 5V 10% SAB 8088-2: T, = 0 to 70°C, Veg = 5V + 5% SAB 8088-1: T, = 0 to 70°C, Voc = 5V + 5% Parameter Symbol |min. | max. _| Unit Test conditions Inputiow votage mw f-os[+oe |v | Inputhigh votage vu 20 |vetos |v |r? Output low voltage vo | fos [vig = 20mA Output high votage [vow 2a |v row = 4005 Power supply current Tec mA | All outputs open Ty = 25°C Input leakage current fu [= sifu ove tn = Yer Clock input low voltage va [-o5_|+oe |v |- Clock input high voltage - Capacitance of input buffer Cw 15 f, = 1MHz (all inputs except___ ADO to AD7, RO/GT) Capacitance of |/O buffer Co 15 f, = 1MHz (ADO to AD7, ROQ/GT) 1) Vu tested with MN/MX in = OV Vi tested with MN/MX in = 5V MN/MX pin is a strap pin. 2) Not applicable to RG/GTO and RG/GT1 pins (pins 30 and 31) Siemens Aktiengesellschaft 122

a AC Characteristics for SAB 8088/8088-2 SAB 8088: Ta = Oto 70°C, Voc = 5V + 10% SAB 8088-2: T, = Oto 70°C, Voc = 5V + 5% Minimum Complexity System Timing Requirements . Test Parameter Symbol | SAB 8088 SAB 8088-2 Unit | conditions Cikeysleperiod aa |200 [5005 [soo [ns_{- CLK tow time a eC CLK high time Po Ce CLK rise time limon [- fro |= fro ns tromtoro sv CLL fal time fico [= fro |= [tons tomastorov Datainsewptime [iowa [30 |= 20 |= ns | - Datainnolstime ——fiaxe fo [fo |= ns RDY setup time into, tae 35 - SAB 8284A/8284B")”) RDY hold time into. tourix - SAB 8284A/8284B ')?) READY setup time into tryricH - SAB 8088 READY holdtime into —_| tcunyx - SAB 8088 reapyinestveto Gtk) [ima [-@ |= |e [= ns | - Horosewptime [tines 138 | 20 | sf INTR, NMI, TEST fiver 30 - setup time”) Input rise time tum from 0.8 to 2.0V (except CLK) Input fall time tan. 12 from 2.0 to 0.8V (except CLK) ) Signal at SAB 8284A/8284B shown for reference only. 2) Setup requirement for asynchronous signal only to guarantee recognition at next CLK. 3) Applies only to T2 state (8 ns into T3). Siemens Aktiengesellschaft 123

Parameter Symbo! Unit Cettitions rin [roe [rin [no Addressvaliddelay |tsw [10 [to [ons |” Addresshoidtime ia 10 tons | Addressfioatdetey [tee [sax [80_[tam 50 ns | ALE wiath Jims ftewr20_ [= esavnto_f-|ns | ALcactivedelay fia [- fan | ds ns Ateinactvedelay tow |e [5 [ns | ALE inactive Datavaliddeley [tw [toro [0 foo ns | Dataholdtime ater WR [imo |teor-30 [-[rv-30_ [ns | Control active delay 1 [tower [toto fro 20s [ns " Control active delay 2 ftcwr [10 [tro fro eons | " Gontolinactivedelay fteven [10 jt ro 70 ns | a READ active - RDinectivedelay fam [ro f60_ fro dao ns | address active RD with [inm [ata [-fatannso [= [ns | WR with [ims [2taan6o[-[2taanao | [ns |” Address valid to ALEtow [twa [feox-60[-taen-40—[- [ns | : Ourputrisetime mon [> [zo | f20 [ns | romastozov Outputfantime we | te ens firom ato 08v 1) ©, = 20-100 pF for all SAB 8088 outputs in addition to the internal loads Siemens Aktiengeselischaft 124

Maximum Mode System (using SAB 8288/8288A bus controller) Timing Requirements Parameter symbol | SAB 8088 SAB 8088-2 Unit | 78S ng [rin [rox [ron [re | CLK fal time fica [- fro [ftom | roma ston0v RDY setup time into taivet - SAB 8284A/8284B ')*) RDY hold time into tounrx - SAB 8284A/8284B ')*) READY setup time into tayHcH - SAB 8088 READY hold time into touryx - SAB 8088 Setup time for tinven - recognition (INTR, NMI, TEST) *) RO hold time into tonex - SAB 8088 Input rise time thon from 0.8 to 2.0V (except CLK) Input fall time teu 12 from 2.0 to 0.8V (except CLK) 1) Signal at SAB 8284A/8284B or SAB 8288/8288A shown for reference only. 2) Setup requirement for asynchronous signal only to guarantee recognition at next CLK. 3) Applies only to T2 state (8 ns into T3). Siemens Aktiengesellschaft 125

Parameter Symbol Unit eeNitions [min [max [min [max | Command Active Delay") [tam [10 [as fio fa [ns | Command Inactive Delay ') [tom [ro [as [ro [a5 [ns | > erceen = [PT status passive *) Stausactivedelay [tow [1010 [to feo ne |? Status inactive delay ltasn fo frg0 fro 70 [ns | * Address vaidetey [tam [toto [ro fons |? Address hold time fiaxe [tos [-_ fro [- [ns | * Addressfioatdetey [tax [tum [80 [tax 0 [ns |? Statusvalidto ALE high") [tenn [- [20 [= f20 [ns |? mr [=~ PPP MCE high ') CLK low to ALE valid ') iam [- [ao f= [a0 [ns | > cixiowtomcenian’) [toner [- ao [- 20 ns |? ALE inactive delay ') fio fa sts fats [ns > Data valid delay law [10 {tro [to [60 [ns | > Data hols time toe fro [fons PO Controtactvedetay") [tom [5 [4s fs fas ns | Control inactive delay ') liom fro fas fo fas [ns | * ') Signal at SAB 8284A/8284B or SAB 8288/8288A shown for reference only. 2) Applies only to T2 state (8 ns into T3). 5) C, = 20-100 pF for all SAB 8088 outputs in addition to the internal loads. Siemens Aktiengesellschaft 126

Timing Responses (cont'd) . | Test Parameter Symbol | SAB 8088 SAB 8088-2 Unit | conditions Address float to taza 2) READ active RDinectivedsley [tam [1060 [10 foo [ns |? RD inactive to next tanav | taxc.—45 ter 40 ? address active Direction control tenor. 2 active delay ') Direction control fonoTH bu inactive delay ') GT active delay fico [fos ss GTinactve dsiey tam | fas [foo ns | 1) Signal at SAB 8284A/8284B or SAB 8288/8288A shown for reference only. 2) , = 20-100 pF for all SAB 8088 outputs in addition to the internal loads. Siemens Aktiengesellschaft 127

AC Characteristics for SAB 8088-1 SAB 8088-1: T, = 0 to 70°C, Voc = 5V + 5% Minimum Complexity System Timing Requirements i CLK cyete period fia |100 500 [ns Data in hold time ae Se RDY setup time into trivee 35 - SAB 8284A/8284B ')?) RDY hold time into teumx - SAB 8284A/8284B ')*) READY setup time into trvich | 53 - SAB 8088 READY hold time into tounvx | 20 - SAB 8088 INTR, NMI, TEST twven - setup time *) Input rise time tun 20 from 0.8 to 2.0V (except CLK) Input fall time ti, ns from 2.0 to 0.8V (except CLK) ") Signal at SAB 8284A/82848 shown for reference only. 2) Setup requirement for asynchronous signal only to guarantee recognition at next CLK. 2) Applies only to T2 state (8 ns into T3). Siemens Aktiengesellschaft 128

Timing Responses SAB 8088-1 [ae [rome —_—| Address valid delay CS | . Aaldress hold time en Ec EC Address float delay [iar [to fans | » ALE width fim facto ns_P ALE active delay fio [aos | ALE inactive delay CE Se Address hold time to Co ee ee ee ” ALE inactive Date vali delay a ee Data hold time SC eC Data hold time after WR ee ee , Control active delay 2 a Cc " Control inactive delay [ixce [0 sons » READ active RD inactive delay Jim [ro feos, | moran f= FT address active HILDA valid lay ea CC 0 RD width lino [2taaao |-fns_ | Address valid to ALE low [tom taer35 [= ns | " Output rise time finn [- toss from 0.8 to 2.0V Output fall time fiw [- «2s [fromzotoo.av 1) C, = 20-100 pF for all SAB 8088 outputs in addition to the internal loads. Siemens Aktiengesellschaft 129

Maximum Mode System (using SAB 8288/8288A bus controller) Timing Requirements SAB 8088-1 Parameter Symbol Unit Test ons a CLK eyele period [tac [100 [500 ns CLK low time LE CLKhigh time ftom [x9 fn CK rise time tone [- fons romt.oro gv RDY setup time into teaver. - SAB 8284A/8284B ')*) RDY hold time into teunix - SAB 8284A/8284B ')?) READY setup time into tavucn — | 53 - SAB 8088 READY hold time into tounvx | 20 - SAB 8088 READY inactive to CLK®) lima [10 fF ns Setup time for ten ~ recognition (INTR, NMI, TEST) *} RO/GT setup time iow fre vs RO hold time into touax 20 - SAB 8088 Input rise time tun from 0.8 to 2.0V (except CLK) Input fall time te from 2.0 to 0.8V (except CLK) ) Signal at SAB 8284A/8284B or SAB 8288/8288A shown for reference only. 2) Setup requirement for asynchronous signal only to guarantee recognition at next CLK. 3) Applies only to T2 state (8 ns into T3}. Siemens Aktiengesellschaft 130

Timing Responses SAB 8088-1 Parameter Test ions a Command active delay ') liam [to fas, [ns ® rt a d status passive *) Status inactive delay fiase [to [55 [ns a Address valid delay a CC CC Address hola time jim fro ns J Adres float delay fine fro fons Status valid to ALE high ') ce a a MCE high *) CLK low to ALE valid") en Se Ce ° i CLK low to MCE high Ee CC ALE inactive delay fous fe ts ns Data valid delay [icv [ro sons Data hold time fio fro fms Control inactive delay ') [iemx [to fas [ns ° 1) Signal at SAB 8284A/8284B or SAB 8288/8288A shown for reference only. ?) Applies only to T2 state (8 ns into T3). 3} G, = 20-100 pF for all SAB 8088 outputs in addition to the internal loads. Siemens Aktiengesellschaft 131

a Timing Responses SAB 8088-1 (cont'd) Parameter Symbol Unit | conditions [am [ne —_| Address float to tone 2 READ active RD inactive to next truav tercr—35 ns 4 address active Direction control towom ® active delay ') Direction control tonptn 2 inactive delay ') ST active delay fixe fo fae ns T® ST inactive delay icon fo fas nsf? 1) Signal at SAB 8284A/8284B or SAB 8288/8288A shown for reference only. 2) C, = 20-100 pF for all SAB 8088 outputs in addition to the internal loads. Input/Output Waveforms for AC Tests 1.SV-—-— Test Points —=1.5V 045V AC Testing: Inputs are driven at 2.4V for a logic 1" and 0.45V for a logic “Q". The clock is driven at 4.3V and 0.25V. Timing measurements are made at 1.5V for both a logic "4" and “0”, Siemens Aktiengesellschaft 132

a Load Circuit for AC Tests Device under Test + C,=100 pF C, includes Jig Capacitance Asynchronous Signal Recognition CLK \\ | \\ NMI favor” INTR >Signal TEST 1) Setup requirements for asynchronous signals only to guarantee recognition at next CLK Bus Lock Signal Timing (Maximum Mode only) ‘Any CLK Cycle ‘Any CLK Cycle CLK a euay foav TOCK Siemens Aktiengesellschaft 133

Bus Timing — Minimum Mode System 1 12 B th CLK Mow (SAB 82844182868, Outputs) ome T TXT Tt TT) i Oa wm | XL seem |? else | re Vea te _ ALE f fava. | RDY . = tr {SAB 0088 Input) hun frrrwce : feusz fover feo "eg iB ‘| Vz aE teres fm Cr |, fenery ge LRH 7 “B oR | fever Notes see next page Siemens Aktiengeselischaft 134

Bus Timing — Minimum Mode System (cont'd) 1 72 13 Th [= fees 7 fone} haa f ; ck Vou ( | (SAB 8284 A,8284B, Outputs) Me foes fav tone _ Sanox Z foverx FS DEN ke foo -—— frown wa feverx tox fewery | < fonctv = _ \\ \\ 25 oT | i 32 : wee gee =e = AD7-ADO Invalid Address Software HALT Bas see tow tes SBS 1) All signals switch between Vou and Vo, unless otherwise specified. 2) RDY is sampled near the end of T2, 73, TW to determine if TW machine states are to be inserted. 4) Two INTA cycles run back to back. The SAB 8088 local ADDR/DATA bus is floating during both INTA cycles. Control signals shown for second INTA cycle. 4) Signals at SAB 8284A/8284B are shown for reference only. 5) all timing measurements are made at 1.5V unless otherwise noted. Siemens Aktiengesellschaft 135

Bus Timing - Maximum Mode System (using SAB 8288/8288A) nh ara aE} Tw, Th fee A fecn fam f You cLK ones [TTX TTX | XT TX aoa > ae ALE | ro {SAB 8288/8288, i A sh Outputs) 7 Cine | — ROY | = wets | SCHEIN READY = 2 foun (SAB 8088 Input) | Fares H Read Cycle fu ae 7 feo] fam c | er YS tr \\ | = loa Foca . \\ “ : wer OUR ‘SAB B288/828BA ¢ Or } ' Outputs. iort ani y mn } tow r tynx v DEN Notes see next page. Siemens Aktiengesellschaft 136

Bus Timing — Maximum Mode System (using SAB 8288/8288A) Write Cycle " 2 | 3 ow % Mea cu Ea 325150 \\ V; LC cern = XK | | | A ae it vn DEN i sag J AMY | i 8288/8288 Towe i j Outputs i | a shun or ! 1Owe i | \\ | INTA Cycle 38) Float || (Roane Fat | Float as a fanz MCE/ / | fo | | f—- PORN jf X L \\ fi fac toon J i Tear ~ 1 oy 5g) | OVR / \\ ‘SAB < t 8288/8288A fount i feo ma fan DEN x \\ a te ‘Software HALT — ny oo X Invalid Address tu! aS a a A Y---— ') All signals switch between Voy and Vo, unless otherwise specified. 2) RDY is sampled near the end of T2, T3, TW to determine if TW machine states are to be inserted. 3) Cascade address is valid between first and second INTA cycle. 4) Two INTA cycles run back-to-back. The SAB 8088 local ADDR/DATA bus is floating during both INTA cycles. Control for pointer address is shown for second INTA cycle. 5) Signals at SAB 8284A/8284B or SAB 8288/8288A are shown for reference only. °) ‘The issuance of the SAB 8288/8288A command and control signals (MRDC, MWTC, AMWC, IORC, TOWC, AIOWC, INTA and DEN) lags the active high SAB 8288/8288 DEN. 7) All timing measurements are made at 1.5 V unless otherwise noted. °) Status inactive in state just prior to T4. Siemens Aktiengesellschaft 137

a Request/Grant Sequence Timing (Maximum Mode only) Any CLK Cycle 20 CLK Cycle CLK Phin fave Phu mats fee foo his Pulse 3 Pulse1 Pulse 2 ine Pe RH Ce SAB B088 RO/GT PRG A Cr AD7 -ADO Previous Grant faz AN9/S6-A16/$3 @&-_ AIS AB SAB 8088 Coprocessor 1 oe aa — $2,$1,S0 RD. LOCK 1) The coprocessor may not drive the buses outside the region shown without risking contention Hold/Hold Acknowledge Timing (Minimum Mode only) PICLK Cycle tor 2 Cycles, CLK \\ | favcr taven HOLD

1 Femay Fonav 7

A15- AB 3) A19/S6-A16/S3 SAB 8088 Coprocessor 8088 RD10/M, = $s DT/R, WR, DEN Siemens Aktiengesel\\schaft 138 i

Ordering Information

Type Ordering code Function SAB 8088-P Q67120-C106 8-bit microprocessor — 5 MHz (P-DIP-40) SAB 8088-2-P Q67120-C213 8-bit microprocessor — 8 MHz (P-DIP-40) SAB 8088-1-P Q67120-C249 8-bit microprocessor — 10 MHz (P-DIP-40) SAB 8088-N Q67120-C301 8-bit microprocessor — 5 MHz (PL-CC-44) SAB 8088-2-N Q67120-C302 8-bit microprocessor — 8 MHz (PL-CC-44) SAB 8088-1-N Q67120-C321 8-bit microprocessor — 10 MHz (PL-CC-44) Siemens Aktiengesellschaft 139