Microcontroller

SAB80515-N

Siemens Semiconductor G...

High-Performance 8-Bit Single Chip Microcontroller

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SAB80535 SIEMENS | Alldatasheet

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8-Bit Single Chip Microcontroller SAB 80515/80535 Preliminary SAB 80515 Microcontroller with factory mask-programmable ROM SAB 80535 Microcontroller for external ROM @ 8K x 8 ROM (SAB 80C515 only) @ 256 x8 RAM © Six 8-bit /O ports, one 8-bit input port for analog signals @ Three 16-bit timer/counters @ Highly flexible reload, capture, compare capabilities @ Full-duplex serial channel @ Twelve interrupt vectors, four priority levels @ 8-bit A/D converter with 8 multiplexed inputs and programmable internal reference voltages @ 16-bit watchdog timer @ pp provides standby current for 40 bytes of RAM @ Boolean processo @ 256-bit-addressable locations @ Most instructions execute in 1 ys (750 ns) © 4.us (3 ns) multiply and divide @ External memory expandable up to 128 Kbytes @ Backwardly compatible with SAB 8051 @ Two temperature ranges available: Oto 70°C —401085°C (140/85) The SAB 80515/80535 is a powerful member of the Siemens SAB 8051 family of 8-bit micro- controllers. It is fabricated in + 5 V N-channel, silicon-gate Siemens MYMOS technology. The SAB 80515/80535 is a stand-alone, high-performance single-chip microcontroller based on the SAB 8051 architecture. While maintaining all the SAB 8051 operating characteristics, the SAB 80515/80535 incorporates several enhancements which significantly increase design flexibility and overall system performance. The SAB 80535 is identical with the SAB 80515 except that it lacks the on-chip program me- mory. The SAB 80515/80535 is supplied in a 68-pin plastic leaded chip carrier package (P-LCC-68). Dal 8.95 M@@ 4235605 0082077 201

Ordering Information

SIEMENS Device Specifications Veg Mes AK, Port 0 xray —— R= Poet XTALZ ~— ~ 8-8 oe vy = Vy aeBit Ye — As, Port 2 “ Mi 8-Bit SAB Mad _ goss = > 85° “no 80835 fs V—, fea 4 rots. J > ear sah ‘ N, Port 5 K—> ear * > ALE RESET —> PSEN wees Logic Symbol RSET Gio 60 P57 Yee e) B 90.7 You G Dp P06 qd B ioe ane Bs ans G Bi 70.3 ana Be me SAB 80515/20595 Bees ant BF ano q B aus m0 /F3.0 G 5 SSEN 130/°3.1 B ent invo/es.2 q Bea? inti7e3.3 Bes 10/3. Bera 11/735 G26 as P23 27 43 eecceaceee eeaes 3) Bane Pin Configuration (P-LCC-68) Semiconductor Group 303 M@! 8235605 0082079 084

SIEMENS Device Specifications Pin Definitions and Functions Symbol Pin Input (I) Function Output (0) | is an 8-bit quasi-bidirectional /O port . | Port 4 can sink/source 4 LS-TTL loads. Yep 4 Power down supply. If Vpp is held within its specs while Voc drops below specs, Vpp will provide standby power to 40 byte of the internal RAM. WhenVpp is low, the RAM's current is drawn from Voc. RESET A low level on this pin for the duration of two machine cycles while the oscillator is running resets the SAB 80C515. A small internal pullup resistor permits power-on reset using only a capacitor connected to ¥ss Veper a Reference voltage for the A/D converter Vaond Reference ground for the A/D converter AN7-ANO | 13-20 ii Multiplexed analog inputs Semiconductor Group 304 @ 8235605 0082080 &Tb

SIEMENS Device Specifications Pin Definitions and Functions (cont'd) Symbol Pin Input (I) Function Output (0) P3.0-P3.7 |21-28 vO Port 3 is an 8-bit bidirectional I/O, It also contains the in- terrupt, timer, serial port and external memory strobe loins that are used by various options. The output latch corresponding to a secondary function must be pro- grammed to a one (1) for that function to operate. Port 3 can sink/source 4 LS-TTL loads.The secondary func- tions are assigned to the pins of port 3, as follows: — RxD (P3.0): serial port's receiver data input (asynchronous) or data input/output (synchronous) - TxD (P3.1): serial port's transmitter data output (asynchronous) or clock output (synchronous) — INTO(P3.2): interrupt 0 input/timer 0 gate control input — INT7(P3.3): interrupt 1 inputitimer 1 gate control input — TO (P3.4): counter 0 input — T1 (P3.5): counter 1 input — WR(P3.6): the write control signal latches the data byte from port 0 into the external data memory — RD (P3.7): the read control signal enables the external data memory to port 0 Semiconductor Group 305 ms 8235605 0082081 732 a

SIEMENS Device Specifications Pin Definitions and Functions (cont'd) Symbol Pin ‘Input (I) | Function | Output (0) P1.7-P1.0 29-36 (VO Port 1 is an 8-bit bidirectional I/O port .It is used for the | low-order address byte during program verification. It also contains the interrupt, timer, clock, capture and compare pins that are used by various options. The out- put latch must be programmed to a one (1) for that func- tion to operate (except when used for the compare func- tions). The secondary functions are assigned to the port 1 pins as follows: | | — INT3/CCO (P1.0): interrupt 3 input / i compare 0 output / | capture 0 input — INT4/CC1 (P1.1): interrupt 4 input / | compare 1 output / / | capture 1 input | — INTS/CC2 (P1.2): interrupt 5 input / | | compare 2 output / | | capture 2 input | |— INT6/CC3 (P1.3): interrupt 6 input / compare 3 output / capture 3 input — INT2(P1.4): interrupt 2 input — T2EX (P1.5): timer 2 external reload trigger input — CLKOUT (P1.6): system clock output — T2(P1.7): counter 2 input Ves 37 Substrate pin. Must be connected to Vgg through a capacitor (47 to 100 nF) for proper operation of the A/D ‘converter. XTAL2 - XTAL2 is the output from the oscillator's amplifier.input to the internal timing circuitry. A crystal, ceramic resona- |tor, or external source can be used. XTAL1 - XTAL1 is the input to the oscillator's high gain amplifier. | Required when a crystal or ceramic resonator is used. ‘Connect to Vgg when external source is used on (XTAL2. Semiconductor Group 306 @® 4235605 0042082 679

SIEMENS Device Specifications Pin Definitions and Functions (cont'd) Symbol Pin Input (1) | Function i Output (O) P2.0-P2.7 41-48 vo Port 2 is an 8-bit quasi-bidirectiona! I/O port. It also emits the high-order address byte when accessing ex- | ternal memory. It is used for the high-order address and | the control signals during program verification. Port 2 | can sink/source 4 LS-TTL loads. PSEN 49 The program store enable output is a control signal that enables the external program memory to the bus during external fetch operations. It is activated every six oscil- lator periods except during external data memory ac- cesses. Remains high during internal program executi- on. ALE 50 Provides address latch enable output used for latching the address into external memory during normal opera- tion. It is activated every six oscillator periods except du- ring an external data memory access. EA 51 LF When held at a TTL high level, the SAB 80515 executes i instructions from the internal ROM when the PC is less H than 8192. When held at a TTL low level, the SAB j 80515 fetches all instructions from external program | memory. For the SAB 80535 this pin must be tied low. P0.0-P0.7 | 52-59 vO Port 0 is an 8-bit open-drain bidirectional I/O port. It is ialso the multiplexed low-order address and data bus when using external memory. It is used for data output during program verification. Port 0 can sink/source | 8LS-TTL loads. P5.7-P5.0 | 60-67 vo Port 5 is an 8-bit quasi-bidirectional /O port. Port 5 can sink/source 4 LS-TTL loads. Yoo POWER SUPPLY (+5 V power supply during normal operation and program verification) ¥sg GROUND (0 V) Semiconductor Group 307 mm 8235605 0082083 SOS a

SIEMENS Device Specifications Functional Description The architecture of the SAB 80515 is based on the SAB 8051 microcontrolier family. The fol- lowing features of the SAB 80515 are fully compatible with the SAB 8051 features: — Instruction set - External memory expansion interface (port 0 and port 2) - Full-dupiex serial port — Timer/counter 0 and 1 — Alternate functions on port 3 — The lower 128 bytes of internal RAM and the lower 4 Kbytes of internal ROM The SAB 80515 additionally contains 128 bytes of internal RAM and 4 Kbytes of internal ROM, which results in a total of 256 bytes of RAM and 8 Kbytes of ROM on chip. The SAB 80515 has a new 16-bit timer/counter with a 2:1 prescaler, reload mode, compare and capture capability. It also contains a 16-bit watchdog timer, an 8-bit A/D converter with pro- grammable reference voltages, two additional quasi-bidirectional 8-bit ports, one 8-bit input port for analog signals, and a programmable clock output (/osc/12). Furthermore, the SAB 80515 has a powerful interrupt structure with 12 vectors and 4 program- mable priority levels. Figure 1 shows a block diagram of the SAB 80515. CPU The SAB 80515 is efficient both as a controller and as an arithmetic processor. It has extensive facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results from an instruction set consisting of 44% one-byte, 41% two-byte, and 15% three-byte instructions. With a 12 MHz crystal, 58% of the instructions execute in 1.0 us. Memory Organization The SAB 80515 manipulates operands in the four memory address spaces described in the fol- lowing. (Figure 2 illustrates the memory address spaces of the SAB 80515). Semiconductor Group 309 M@™§ 6235605 0082085 345 a

SIEMENS Device Specifications Shared Address Location | fl | is re | | } Upper Special | 128-Bytes Function | Regist | External Internal eaters | —— | | 80. sof External Data 000! Memory| ITT TTT : iT ' Corre] | ! Lower | i 128-Byles i il Internat i Internal External cane | ni (fA=1) (FA=0) HHH o o oof Ti TTT} 9000) Program Memory Dota Memery Direct Byte pegister Addressing Addressing wcsooa7s Figure 2 Memory Address Spaces Semiconductor Group 310 M™ 6235605 0082046 214

SIEMENS Device Specifications Program memory The SAB 80515 has 8 Kbyte of on-chip ROM, while the SAB 80535 has no internal ROM. The program memory can be externally expanded up to 64 Kbytes. If the EA pin is held high, the ‘SAB 80515 executes out of internal ROM unless the address exceeds 1FFF},. Locations 2000, through OFFFF,, are then fetched from the external program memory. If the EA pin is held low, the SAB 80515 fetches alll instructions from the external program memory. Since the SAB 80535 has no internal ROM, pin EA must be tied low when using this component. Data Memory The data memory address space consists of an internal and an external memory space. The internal data memory is divided into three physically separate and distinct blocks: the lower 128 bytes of RAM, the upper 128 bytes of RAM, and the 128-byte special function register (SFR) area. While the upper 128 bytes of data memory and the SFR area share the same address locations, they are accessed through different addressing modes. The lower 128 bytes of data memory can be accessed through direct or register indirect addressing; the upper 128 bytes of RAM can be accessed through register indirect addressing; the special function registers are accessible through direct addressing. Four 8-register banks, each bank consisting of eight 8-bit multi-purpose registers, occupy loca- tions 0 through 1Fy in the lower RAM area. The next 16 bytes, locations 20, through 2Fy, con- tain 128 directly addressable bit locations. The stack can be located anywhere in the internal data memory address space, and the stack depth can be expanded up to 256 bytes. The external data memory can be expanded up to 64 Kbytes and can be accessed by instruc- tions that use a 16-bit or an 8-bit address. ‘Semiconductor Group 311 @™ 8235605 0082087 150

SIEMENS Device Specifications Special Function Registers All registers, except the program counter and the four 8-register banks, reside in the special function register area. The 41 special function registers (SFR’s) include arithmetic registers, pointers, and registers that provide an interface between the CPU and the on-chip peripheral functions. There are also 128 directly addressable bits within the SFR area. The special function registers are listed in the following table: In table 1 they are organized in numeric order of their addresses. In table 2 they are organized in groups which refer to the functional blocks of the SAB 80515/80535. Table 1 Special Function Register Address Register Contents Contents after Reset after Reset 804, PO") OFFy 98, SCON? [004

814 SP 07H 994, ‘SBUF XXXX XXXXp_

824 DPL 004, Ay reserved = |XX}

83,4 DPH 004, 9By, reserved XXy?) 84, reserved XXy 2) 9Cy reserved XXy 854, reserved XXy? 9Dy reserved XXq? 86, reserved XXy?? 9Ey reserved XX?

874 PCON 000X 000032 |9Fy reserved = |XXy2)

88, TCON 00), A0y P20 OFFy 89, TMOD 00, Aly reserved XXy 2 BAY TLO 004 AQ, reserved XXy? 8B, TL 004, ASH reserved XXy? 8Cy THO 004 Ady reserved |XX? 8Dy THI 004 A5y reserved — |XX? 8Ey reserved XXy 2 AG reserved = | XX?) 8Fy reserved XX, 2 ATK reserved XXpy 2

904 PID OFF, AB, 1ENO » 004

914 reserved XX?) AQy IPO X000 0000, ? 924 reserved XX? AAy reserved |XX 93, reserved XX? ABy reserved XXy?? 9444 reserved XXy?) ACY reserved = |XX42 954 reserved XXy2) ADy reserved | XX42 964 reserved XX?) AE reserved = |XX42 974 reserved XX? AFy reserved |XX )) Bit-addressable Special Function Register 2) X means that the value is indeterminate and the location is reserved Semiconductor Group 312 MM 4235605 0082088 097 a

SIEMENS Device Specifications Table 1 Special Function Register (cont'd) Address Register Contents Address Contents after Reset | after Reset BO, P3!) OFFy DOy Psw?) 004, Biy reserved — |XX’) Diy reserved — |XX}42) B2, reserved | XX,) D2y reserved — |XX?) B3y reserved XX?) D3y, reserved XXq?) Ba, reserved XX?) D4, reserved XXy?) BSy reserved XX?) D5y reserved XXy?) Bey \\reserved XX?) | D6, reserved XXp2) B74 reserved | XX}?) D74 reserved = |XX} BS, 1EN1 00H, D8 ADCON _|00X0 00003”) Bo, IP1 XX00 000032 |D9, ADDAT 00, BAY reserved XXH?) DAW DAPR 004, BB, reserved — |XX}2) DB, P6 BCy reserved |XX?) DCy reserved = |XXy2) BDy reserved = |XX) DDy reserved — |XXy42) BE, reserved XXy?) DEW reserved XXy?) BFy reserved Xp? DFy reserved XXp2) CO, IRCON®) [00,4 E0y ACC ») 004 Cty CCEN 004, Ely reserved — |XXy2) Cay CCL 004, E2y reserved |XX?) C3, CCHt 004, 3, reserved — |XX}42) C44 ccLe 004 E4y reserved — |XX?) C54 CCH2 004 ESy reserved — |XXy42) C6, ccLs 00, E6, reserved — |XX) C74 CCHS 004 E7y reserved — |XX42 C8, T2CON» |00, E8y, P4?) OFFy C84 reserved XXy?) E94 reserved XXy?) CA CRCL 004 EAy reserved |XX?) CBy CRCH 00, EB, reserved — |XX42 CCy TL2 004 ECy reserved = |XX) CD, TH2 00, ED, reserved — |XXy2) CEy reserved XXy?) EE, reserved XXq?2) CFy reserved XXy?) EFy reserved XXy?) 1) Bit-addressable Special Function Register 2) X means that the value is indeterminate and the location is reserved Semiconductor Group 313 @® 46235605 0082089 T23

Sl EM ENS Device Specifications Table 1 Special Function Register (cont'd) Address Contents Contents after Reset after Reset FOy BY 00, FB, P51) OFF, Fiy reserved — |XX) Foy reserved — |XX) Fy reserved =| XX2) FAy reserved — |XX42) F3y reserved XX?) FBY reserved XXq?) Fay reserved |XX) FCy reserved —|XX42) F5y reserved XX?) FDY reserved XXy?) Fey reserved = |XX) FEY reserved = |XX) F7y reserved XX") FFy reserved XXy?) *) Bit-addressable Special Function Register 2) X means that the value Is indeterminate and the location is reserved Semiconductor Group 314 @® 4235605 0082090 745 me

SIEMENS Device Specifications Table 2 Special Function Registers - Functional Blocks Block Symbol Address Contents after Reset CPU ACC Accumululator OEO, ” 004, B B-Register OFO, ? 00}, DPH Data Pointer, High Byte 0834, 00, DPL Data Pointer, Low Byte 0824 00H, PSWw Program Status Word Register 0D0,, » 004, SP Stack Pointer 0814, O74 AID- ADCON2?) |A/D Converter Control Register 0D8)," 00X0 0000,” Converter |ADDAT A/D Converter Data Register 09D, 00,4 DAPR _|A/D Converter Program Register. |ODAy 004) Interrupt ENO Interrupt Enable Register 0 OA8,” 004 System IEN1? Interrupt Enable Register 1 0B8,” 004 IPO? Interrupt Priority Register 0 OAS, X000 0000,” 1P1 Interrupt Priority Register 1 0B9,, XX00 000059) IRCON Interrupt Request Control Register |0CO,” 004 TCON2! Timer Control Register 88," 00, T2CON ® |Timer 2 Control Register OCB,” 004, Compare/ |CCEN ‘Comp./Capture Enable Reg. 0C1y, 0044 Capture- CCH1 Comp./Capture Reg. 1, High Byte [0C3,, 004, Unit CCH2 Comp./Capture Reg. 2, High Byte |OC5, 004 Compare). |CCH3 —_|Comp./Capture Reg. 3, High Byte |OC7, 004 Capture- CCLi Comp./Capture Reg. 1, Low Byte |0C2y 004 Unit CccL2 Comp./Capture Reg. 2. Low Byte |0C4, 00,4, (ccu) CCL3 Comp./Capture Reg. 3, Low Byte |0C6y 004 (cont'd) CRCH —|Com//Rel./Capt. Reg. High Byte. |OCBy 0044 (ccu) RCL Com,/Rel./Capt. Reg. Low Byte — |OCAy 004, TH2 Timer 2, High Byte OCD, 004, TL2 Timer 2, Low Byte OCC, 004, T2CON” | Timer 2 Control Register 0c8,” 004, 1) Bit-addressable special function registers 2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks 3) X means that the value is indeterminate Semiconductor Group 315 M™ 8235605 0082091 66) a

A) | EM ENS Device Specifications Table 2 Special Function Registers- Functional Blocks (cont'd) Block Address | Contents after Reset Ports PO Porto 80,” OFFy Pi Port 1 904 OFF, P2 Port2 OAD,» OFFy, P3 Port 3 OBO, *) OFFy P4 Port 4 OE8,, *) OFFy, PS Port 5 FB, *) OFF y P6 Port 6, Analog/Digital Input ODBy, Pow. Sav. |PCON2) |Power Control Register 087); 000X 0000 B 2) Modes Serial ADCON 7” |A/D Converter Control Reg. 0D8,, ") /00X0 0000p * Channels PCON?) {Power Control Register 0874, }000X 0000. 9 SBUF Serial Channel Buffer Reg. 099, XXXX XXXXg 9) SCON | Serial Channel Control Reg. 098,” 004; Timer 0/ TCON® Timer Control Register 088,,") 00}; Timer 1 THO Timer 0. High Byte 08C,, 004; THT Timer 1, High Byte O8Dy 004 TLO Timer 0, Low Byte O8A, 004, TL Timer 1, Low Byte 8B, 004 TMOD | Timer Mode Register 089} 004 Watchdog {ENO ®) Interrupt Enable Register 0 OA8,") 004, IEN1?) —_|Interrupt Enable Register 1 0B8,” 00,4 IPO?) Interrupt Priority Register 0 OAS, X000 0000, ?) .) Bit-addressable special function registers 2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks. 3) X means that the value is indeterminate and the location is reserved Semiconductor Group 316 MM 6235605 0082092 518 me

SIEMENS Device Specifications Serial Port The serial port of the SAB 80515 enables full duplex communication between microcontrollers or between microcontroller and peripheral devices. The serial port can operate in 4 modes: Mode 0: Shift register mode. Serial data enters and exits through RxD. TxD outputs the shift clock. 8 bits are transmitted/received: 8 data bits (LSB first). The baud rate is fixed at 1/12 of the oscillator frequency. Mode 1: 10 bits are transmitted (through RxD) or received (through TxD): a start bit (0), 8 data bits (LSB first), and a stop bit (1). The baud rate is variable. Mode 2: 11 bits are transmitted (through RxD) or received (through TxD): a start bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1). The baud rate is programmable to either 1/32 or 1/64 of the oscillator frequency. Mode 3: 11 bits are transmitted (through TxD) or received (through RxD): a start bit (0), 8 data bits (LSB first), a programmable Sth data bit, and a stop bit (1). Mode 3 is identical to mode 2 except for the baud rate. The baud rate in mode 3 is variable. The variable baud rates in modes 1 and 3 can be generated by timer 1 or an internal baud rate generator. A/D Converter The 8-bit A/D converter of the SAB 80515 has eight multipiexed analog inputs (Port 6) and uses the successive approximation method. It takes 5 machine cycles to sampie an analog signal (during this sample time the input signal should be held constant); the total conversion time (including sample time) is 15 machine cyc- les (15 us at 12 MHz oscillator frequency). Conversion can be programmed to be single or con- tinuous; at the end of a conversion an interrupt can be generated. A unique feature is the capability of internal reference voltage programming. The internal refe- rence voltages Vintaner aNd Vintaqnp for the A/D converter both are programmable to one of 16 steps with respect to the external reference voltages. This feature permits a conversion with a smaller internal reference voltage range to gain a higher resolution. In addition, the internal reference voltages can easily be adapted by software to the desired analog input voltage range. Figure 3 shows a block diagram of the A/D converter. Semiconductor Group 317 MM 4235605 0082093 454

SIEMENS Device Specifications Baud System Busy Conver- AN-Input Rate Clock Flag sion Select Enable Enable Mode... Udets ted ste] fe ADCON (0D8y) ADDAT (0094) - ‘ANO-AN7 . s G Tigt aon] | ns ger 3 i % z j i noo | | DAPR (ODA) Ute ts tede ded Pe f= Programming Programming Tin ner Thos nono wepoo0e0 |_. Figure 3 Block Diagram of the A/D Converter Semiconductor Group 318 mm 8235605 0082094 390 =

SIEMENS Device Specifications Timer/Counters The SAB 80515 contains three 16-bit timer/counters which are useful in many applications for timing and counting. The input clock for each timer/counter is 1/12 of the oscillator frequency in the timer operation or can be taken from an external clock source for the counter operation (maximum count rate is 1/24 of the oscillator frequency). - Timer/counter 0 and 1 These timer/counters can operate in four modes: Mode 0: 8-bit timer/counter with 32:1 prescaler Mode 1: 16-bit timer/counter Mode 2: 8-bit timer/counter with 8-bit auto-reload Mode 3: Timer/counter 0 is configured as one 8-bit timer/counter and one 8-bit timer; timer/counter 1 in this mode holds its count. External inputs INTO and INT1 can be programmed to function as a gate for timer/counters 0 and 1 to facilitate pulse width measurements. — Timer/counter 2 Timer/counter 2 of the SAB 80515 is a 16-bit timer/counter with several additional features. It offers a 2:1 prescaler, a selectable gate function, and compare, capture and reload functions. Corresponding to the 16-bit timer register there are four 16-bit capture/compare registers, one of them can be used to perform a 16-bit reload on a timer overflow or external event. Each of these registers corresponds to a pin of port 1 for capture input/compare output. Figure 4 shows a block diagram of the timer/counter 2 Reload A 16-bit reload can be performed with the 16-bit CRC register, which is a concatenation of the 8-bit registers CRCL and CRCH. There are two modes from which to select: Mode 0: Reload is caused by a timer 2 overflow (auto-reload). Mode 1: Reload is caused in response to a negative transition at pin T2EX (P1.5), which can also request an interrupt. Capture This feature permits saving the actual timer/counter contents into a selected register upon an external event or a software write operation. Two modes are provided to latch the current 16- bit value in timer 2 registers into a dedicated capture register: Mode 0: Capture is performed in response to a transition at the corresponding port 1 pins CCO to CC3. Mode 1: Write operation into the low-order byte of the dedicated capture register causes the timer 2 contents to be latched into this register. Semiconductor Group 319 M@™ 8235605 0082095 227 a

SIEMENS Device Specifications Compare In the compare mode, the 16-bit values stored in the dedicated compare registers are compa- red to the contents of the timer 2 registers. If the count value in the timer 2 registers matches one of the stored values, an appropriate output signal is generated and an interrupt is requ- ested. Two compare modes are provided: Mode 0: Upon a match the output signal changes from low to high. It goes back to a low level when timer 2 overflows. Mode 1: The transition of the output signal can be determined by software. A timer 2 overflow causes no output change. Semiconductor Group 320 M™® 6235405 0082096 1b3 a

SIEMENS Device Specifications i 1210 ‘EXEN2 i} T2I1 | pry < H | Request Fosc/12 “ é | imi : i —— vy} [-——] |e i — Fh | a i i j [Lt — i rt = | i S = P1.0/iNTS | / 16-6 16-8 16-8! 16-8 8 B ptennraces : | 4 S fam P1.2/ints/ccr t | | | s | > P1.3/INT6/CCS | ws vie cam Copture | | (oe pe —i | | | i {4 i | : | : weeseors i Figure 4 Block Diagram of Timer/Counter 2 Semiconductor Group 321 M@™ 4235605 0082097 OTT

SIEMENS Device Specifications Interrupt Structure The SAB 80515 has 12 interrupt vectors with the following vector addresses and request flags: Table 3 Interrupt Sources and Vectors Source (Request Flags) Vector Address Vector 1Eo 10003, External interrupt 0 TFO }000By Timer 0 interrupt 11 0013, External interrupt 1 TF 001By, Timer 1 interrupt Al+TI 00234, Serial port interrupt TF2 + EXF2 002By, Timer 2 interrupt 1ADC 0043, A/D converter interrupt IEX2 0048, External interrupt 2 1EX3 0053, External interrupt 3 IEX4 005B,, External interrupt 4 1EX5, 0063.4 External interrupt 5 IEX6 O06By, External interrupt 6 Each interrupt vector can be individually enabled/disabled. The minimum response time to an interrupt request is more than 3 machine cycles and less than 9 machine cycles. Figure 5 shows the interrupt request sources, External interrupts 0 and 1 can be activated by a low-level or a negative transition (selectable) at their corresponding input pin, external interrupts 2 and 3 can be programmed for triggering on a negative or a positive transition. The external interrupts 3 to 6 are combined with the cor- responding alternate functions compare (output) and capture (input) on port 1. For programming of the priority levels the interrupt vectors are combined to pairs. Each pair can be programmed individually to one of four priority levels by setting or clearing one bit in the ‘special function register IPO and one in IP1. Figure 6 shows the priority level structure. Semiconductor Group 322 @® =6235b05 0042098 T3b

SIEMENS Device Specifications | ma oh / P3.2/INTO {:e0} | TCON.O ofA] TIMER 0 Srertow {iro} P3.3/iNTT TCON.2 UA} | TIMER 1 5 Overflow Receiver ———[# + - Le] SERIAL PORT Tronsmitter a] - TIMER 2 Interrupt Control PLS/T2EX “Al ao ef EXEN2 pia/int2 — a | T2CONS oA] Compare 0 ye T2CON.6 2} Compare 1 a | } Compare 2 | P1.2/INTS/CC2 + |7]| [09] Compare 3 | P1.3/INT6/0c3 ——t— +7} fice] | wcpoNe8t | Figure 5 Interrupt Request Sources Semiconductor Group 323 W@™ 8235605 0082099 172

1 Nt =

| x2 f Interrupt Request/ |. Vector | IENO.2 Priority-Control_ F—” Locations Cet oe Pi2 P02 | ENED = 1X3 0

1 ENS H

SIEMENS Device Specifications VO Ports The SAB 80515 has six 8-bit /O ports and one 8-bit input port. Port 0 is an open-drain bidi- rectional I/O port, while ports 1 to 5 are quasi-bidirectional /O ports with internal pull-up resi- stors. That means, when configured as inputs, ports 1 to 5 will be pulled high and will source current when externally pulled low. Port 0 will float when configured as input. Port 0 and port 2 can be used to expand the program and data memory externally. During an access to external memory, port 0 emits the low-order address byte and reads/writes the data byte, while port 2 emits the high-order address byte. In this function, port 0 is not an open-drain port, but uses a strong internal pullup FET. Ports 1 and 3 are provided for several alternate functions, as listed below: Por [Symbol [Function - OO P1.0 /INT3/CCo | External interrupt 3 input, compare 0 output, capture 0 input P1.1 |INT4/CC1 | External interrupt 4 input, compare 1 output, capture 1 input P1.2 |INT5/CC2 | External interrupt 5 input, compare 2 output, capture 2 input P1.3. |INT6/CC3 | External interrupt 6 input, compare 3 output, capture 3 input P14 INT2 External interrupt 2 input P15 |T2EX ‘Timer 2 external reload trigger input P1.6 |CLKOUT |System clock output PL7 |T2 Timer 2 external counter input P3.0 |RXD Serial port's receiver data input (asynchronous) or data input/output (synchronous) P3.1 | TXD Serial port's transmitter data output (asynchronous) or clock output (synchronous) P3.2 |INTO External interrupt 0 input, timer 0 gate control P3.3 |INTT External interrupt 1 input, timer 1 gate control P3.4 |TO Timer 0 external counter input P3.5 |T1_ Timer 1 external counter input P3.6 WR External data memory write strobe P3.7 |RD External data memory read strobe The input port ANO-AN7 is used for analog input signals to the A/D converter. Semiconductor Group 325 M@™§ 6235605 0082101 350

SIEMENS Device Specifications Watchdog Timer This feature is provided as a means of graceful recovery from a software upset. After an exter- nal reset, the watchdog timer is cleared and stopped. It can be started and cleared by software, but it cannot be stopped. If the software fails to clear the watchdog timer at least every 65532 machine cycles (about 65 ms if a 12 MHz oscillator frequency is used), an internal hardware reset will be initiated. The reset cause (external reset or reset caused by the watchdog) can be examined by soft- ware. To clear the watchdog, two bits in two different special function registers must be set by two consecutive instructions (bits IENO.6 and IEN1.6). This is done to prevent the watchdog from being cleared by unexpected opcodes. Instruction Set Summary The SAB 80515/80535 has the same instruction set as the industry standard 8051 microcontroller. A pocket guide is available which contains the complete instruction set in functional and hexadecimal order. Furtheron it provides helpful information about Special Function Registers, interrupt Vectors and Assembler Directives. Literature Information Title Ordering No. Microcontroller Family SAB 8051 Pocket Guide B158-B6599 - X - X - 7600 Semiconductor Group 326 WA 82355605 9082102 297 mm

SIEMENS Device Specifications Absolute Maximum Ratings Ambient temperature under bias Voltage on any pins with respect to ground (Vg)... 70.5 VtO7V Note Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Characteristics Voc = 5 V +10 %; Veg = 0V Ta= 0to70 °C for the SAB 80515/80535 Ta =— 40 to 85 °C for the SAB 80515/80535-T40/85 Tx =—-40to110 °C for the SAB 80515/80535-T40/110 Parameter Symbol Limit values Test condition min. max. Input high voltage ) Min 2.0 Yoo- IV - (except RESET, XTAL2 05 Input high voltage to XTAL2 er Pe Voo+ \\V_ |XTAL1 10 Veg 0.5 Input high voltage toRESET [Vio [30 [= vo ~ Power down voltage Veo iss fv Voo=0V Output low voltage Vor Vv Jo, = 1.6 mA ports 1, 2,3, 4,5 Output low voltage You Vig = 3.2 mA” port 0, ALE, PSEN Output high voltage Vou Vv JoH=— 80 nA ports 1, 2,3,4,5 | Output high voltage You 24 - V Hon=—400 A port 0, ALE, PSEN. *) Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the Vo, of ALE and ports 1,3,4,5. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-0 transitions during bus operation. Semiconductor Group 327 M@™® 6235605 0082103 123

SIEMENS Device Specifications DC Characteristics (cont'd) Parameter oe ‘Test condition Logic 0 input current Tie — -800 pA |My, =0.45V ports 1, 2,3, 4,5 } Logic 0 input current Tu - F 2.5 |mA |XTAL1= Veg XTAL2 | Vy = 0.45V Input low current to RESET Ns {- pA |My = 0.45 V for reset Input leakage current to du +10 WA |0V<Vin<Voco port 0, EA ANO - AN7 Power supply current: SAB 80515/80535 leo le10 | mA |all outputs SAB 80515/80535-T40/85 Tec — [280 |mA_ jdisconnected SAB 80515/80535-T40/110 Toc = |230 mA ”) Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the Voy of ALE and ports 1,3,4,5. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins. when these pins make 1-0 transitions during bus operation. Semiconductor Group 328 MB 8235605 0082204 ObT mm

SIEM ENS Device Specifications AID Converter Characteristics Voc = 5 V 410 %; Veg = 0 V; Varner = Voc + 5%: Vacnn = Vsg + 0.2 V: Vinarer —VinaGnn 2>1V; Ta =0to + 70°C for SAB 80515/80535 Tp = — 40 to + 85 °C for SAB 80515/80535 - T40/85 Parameter Symbol Limit values Unit | Test condition min. typ. max. Analog input voltage Vaineut Vagno ~ | Varer+ |V - 0.2 o2 | Analog input capacitance - pF i) Load time 2tcy |us - Sample time ts - 5 toy ys - (incl. load time) Conversion time Io - — 13 toy |ps |= (including sample time) | Differential non-linearity |DNLE |= +12 [41 LSB [Vinaner = Integral non-linearity INLE 41/2 |44 LSB | Vaper = Foo Offset error £12 [+4 LSB VintAGND = Gain error +12 |+1 LSB | //MAGND v, Total unadjusted error | TUE +1 (42 iLSB ne = USS Vaner supply current Tree - \\- 5 mA 2) Internal reference error |Vintreren +30 mv | ‘) The internal resistance of the analog source must be low enough to assure full loading of the sample capaci- tance (C;)during load time (r,). After charging of the internal capacitance (C\\ ) in the load time (r) the analog input must be held constant for the rest of the sample time (‘g) 2) The differential impedance rp of the analog reference voltage source must be less than 1 k&2 at reference supply voltage. Semiconductor Group 329 M™ §8235605 0062105 TTh a

SIEMENS Device Specifications AC Characteristics Vog = 5 V #10 %; Vgg= 0 V; (C for port 0, ALE and PSEN outputs = 100 pF; CC for all other outputs = 80 pF) 7’, = 0 to + 70 °C; for SAB 80515/80535 Tx = — 40 to + 85 °C; for SAB 80515/80535 - 40/85 Variable clock it cig. = 1-2MHz to 12 MHz Program Memory Characteristics ALE to valid tv 4tcic.—100 |ns instruction in PSEN to valid tpuv 3terc.—100 |ns instruction in Input instruction hold ltpxix ns after PSEN Input instruction float tote. — 20 ns after PSEN Address valid after tpxay? {75 terc.-8 ns PSEN Address to valid tavw Stouc.- 115 (ns instruction in ) Interfacing the SAB 805156 to devices with float times up to 75 ns is permissible. This limited bus contention will not cause any damage to port 0 drivers. Semiconductor Group 330 M@™ 6235605 0082106 932 mm

SIEMENS Device Specifications Parameter ‘Symbol Limit values Unit Variable clock Wt creL = 1.2 MHz to 12 MHz [ max. | min. max. | External Data Memory Characteristics Address hold after ALE |, axo Zicuc-35 |= ns RD to valid data in IRLDV - Stoic 165 ns Address to valid data in [voy [- [588 fF 9 trcuc. - 165 |ns WR or RD high to twa {43 123 Jig. 40 foc. +40 ins ALE high | Data valid to WR towwx — {33 tore. — 50 - ins transition | Data setup before WR lian [433 |- [Fcc - 150 |- ns Semiconductor Group 331 Mi 4235605 008210? 675

SIEMENS Device Specifications Waveforms Scie | Fes = fu — \\ fon ne | 1 | beta lm | Fa Some | ry Program Memory Read Cycle nie a) ' ae | { arlene he lin | ra non |

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SIEMENS Device Specifications | ry | ' as | i i] | = uw = 4 i we | ‘| = — joe | = | ‘wereenes | Data Memory Read Cycle oo ——— _ 7 i | c rT 40} xTaLt +5V x XTALL 12-12 wie we | c | 7404 | 74LS04 C = 30pF + 10pF esoooss | | Crystal Oscillator Mode. Driving from External Source — _ . a Recommended Oscillator Circuits Semiconductor Group 333 @® 8235605 0082105 64]

SIEM ENS Device Specifications AC Characteristics (cont'd) Variable clock Frequ. = 1.2 MHz to 12 MHz External Clock Drive XTAL2 eC Lorine ee | es fac fewes | 25 25° 25 | 08 0.8. ta wens or fevce External Clock Cycle Semiconductor Group 334 y MB 4235605 0082110 363

SIEMENS Device Specifications a — ——— i | aay Tov Tov 2av | Test Points | ousv sv 0.8v ausy | | i | | re — Float 24V 2AV | 2.00 2.0 0.45 0.6 oey 0.45V | wenano2e | Timing measurements are made at 2.0 V for a logic "1" and at 0.8 V for a logic "0". For timing purposes, the float state is defined as the point at which a PO pin sinks 3.2 mA or sources 400 uA at the voltage test levels. A.C. Testing Input, Output, Float Waveforms Semiconductor Group 335 M@™ 8235605 0082111 eTT

SIEMENS Device Specifications AC Characteristics (cont'd) Variable clock Wt cue, = 1.2 MHz to 12 MHz ‘System Clock Timing GxoTewine ase (7 man high j foun ae | fuse fous. [>— fuse ux our I ,.,, ———-| ns en — PSEN | | / | ROLWR | Prom Manor dees De Money feess es | | | | System Clock Timing Semiconductor Group 336 @™® 6235605 0082112 136

SIEMENS Device Specifications ROM Verification Characteristics Ty= 25°C 15°C: og =5 V+ 10%; Veg =0V Parameter Symbol Limit values Unit min max. ROM Verification Address to valid data tavav |= 48 tcLoLt ins —_ H a a ENABLE tovaliddata lieugy |- 48 trout ins Data float after ENABLE |teoz —(/0 48 crow ns Oscillator frequency 4 6 “MHz cat ied fae tear 227 enna \\ } come adress: P1.0-91,7=A0-47 puts: P25-P2.6, 2SEV=Kg 72.0-P2.4=KB~AI? ale, The Vy Dele: Pork © =00-07 aesET = H Address: P1.0-P1.7 = A0-A7 P2.0-P2.4 = A8-A12 Data: Porto = 00-07 Inputs: P2.5-P2.6, PSEN = V'gg ALE.EA = iy RESET = ¥,. ROM Verification Semiconductor Group 337 W@® 8235605 0082113 O72 a

SI EMENS Device Specifications Package Outlines if | Plastic Package, P-LCC-68- SMD | (Plastic Leaded Chip-Carrier) oom ag oe 338) SHEN, 1 ae SOMORED 2.43290] l 2B --l 22——=! wl : In 3 ors) Se Maing sus, ses, aaron

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Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. ‘SMD = Surface Mounted Device: Dimensions in mm Semiconductor Group 338 M@™ 4235605 0062114 TOS a

Product Information

SAB80515-N specifications and overview.

Summary

High-Performance 8-Bit Single Chip Microcontroller

Description

High-Performance 8-Bit Single Chip Microcontroller

Source title SAB80515-N Datasheet(PDF) - Siemens Semiconductor Group

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