SAB8032A

SAB8032A SIEMENS | Alldatasheet

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4?E D MM 6235605 0029793 0 MBSIEG SIEMENS SIEMENS AKTIENGESELLSCHAF T= 49-1%- OS 8-Bit Single Chip Microcontroller SAB 8052A/8032A Preliminary SAB 8052A-P(N) Microcontroller with factory-maskprogrammabel ROM SAB 8032A-P(N) Microcontroller for external ROM @ 8K x 8 ROM (SAB 8052A only) @ 256 x8 RAM @ Four 8-bit ports, 32 /O lines @ Three 16-bit timer/event counters @ High-performance full-duptex serial channel with flexible transmit/receive baud rate capability © External memory expandable up to 128 Kbytes @ Boolean processor @ Most instructions execute in 1 1s @ Multiply and divide in 4 us @ Six interrupt vectors, two priority levels @ RAM power-down supply @ P-DIP-40 and PL-CC-44 package @ Full backward compatibility with SAB 8051/8031 Pin Configuration P-DIP-40 PL-CC-44 newts ols: Ze 3288 neceu 2 ssflrao a0 gicgiivecsize pote ee ate LES EERE ES mu pa3 a vustfr Tepleoe ace rife pe ov rode © vfs math x [ros aos rode Pires 106 pute saProe 06 510 xefe 107 sites afleor 101 sorts SAB afew sorretn spe romain 832A sohace nee ef ourowiesrtiz 8052A ashosenw wore Os ‘SAB 8032A/ 80524 oDae werverenagja eer as onroevena fhe nPlstue rea fhe flee an arenas ase as uns nflns a iat ofr a0 sozien gn xen an teste apis a wnuthe alee a os sean nien 19 PRige2S5ERe The SAB 8052A/8032A is a standalone, high-performance single-chip microcontroller fabricated in + 5 V advanced N-channel, silicon gate Siemens MYMOS technology, packaged in a 40-pin DIP or 44-pin plastic leaded chip carrier (PL-CC-44) package. It is backwardly compatible with the SAB 8051A/8031A. It provides the hardware features, 329 2.88

47E D MM 8235605 0029794 2 MBSIEG SIEMENS AKTIENGESELLSCHAF SAB 6052A/8032A T-49- 19-055 architectural enhancements, and instructions that are necessary to make it a powerful and cost-effective controller for applications requiring up to 64 Kbytes of program memory and/or up to 64 Kbytes of data memory. The SAB 8052A contains a non-volatile 8 K x 8 read-only program memory; a volatile 256 x 8 read/write data memory; 32 I/O lines; three 16-bit timer/ counters; a six-source, two-priority-level, nested interrupt structure; a serial I/O port for either multiprocessor communications, I/O expansion, or full-duplex UART; as well as on-chip oscillator and clock circuits. The SAB 8032A is identical with the SAB 8052A, except that it lacks the program memory. For systems that require extra capability, the SAB 8052A can be expanded using standard TTL compatible memories and the byte-oriented SAB 8080 and SAB 8085 peripherals. Logic Symbol Ms Me XTALI 13 <+(2 XTAL2 13 she \\3 RST/Vo El esle ede \\ 8 cat ++) yon PSEN# +—T2Ex Aue SAB - 80324 3 8052 RxD > — ro =| ae INTO# —> —ls INT # >, { 2 gi [8 to e|—[é Tt — 2 wR -| | RO# «— —) : weveones Siemens Aktiengeselischaft 330

47E D MM 8235605 0029795 4 MMSIEG SIEMENS AKTIENGESELLSCHAF SAB 80524/8032A THY 9-19-05 Pin Definitions and Functions ‘Symbol Pin Input (1) | Function DIP-49 | PL-CC-44 | Output (0) P1O-PL.7 29 vo Port 1 is an 8-bit quasi-bidirectional /O por. Its used for the low-order address byte during program verification. Port 1 can sink/source four LS TTL loads. Port 1 also contains the timer 2 pins as a secondary function. The output latch corresponding to a secondary function must be programmed to a one (1) {or that function to operate, The secondary functions ara assigned to the pins of port 1, as follows: ~ T2(P1.0). Input to counter 2 ~ T2 EX (P1.1). Capture/Reload trigger of timer 2. RST/Veo 10 Ahiigh level on this pin resets the SAB 8052A. A small internal pulldown resistor permits power-on reset using only a capacitor connected to VCC. If VPD is held within its spec while voc drops below spec, VPO will provide standby power to the RAM, When VPD is low, the RAMs current is drawn from vec. P3.0-P37 | 10-17 | 11, Port 3 is an 8-bit quasi-bidirectional VO port. Italso 13-19 contains the interrupt, timer, serial port and RD and WR pins that are used by various options. The output latch | ‘corresponding to a secondary function must be programmed to a one (1) for that function to operate. Port 3 can sink/source four LS TTL loads. The secondary functions are assigned to the pins of Port 3, as follows: — RxDidata (P3.0). Serial ports receiver data input (asynchronous) or data inpuvoutput (synchronous). — TxD/clock (P3.1). Serial port's transmitter data output | (asynchronous) or clock output (synchronous). — INTO (P3.2). Interrupt 0 input or gate control input for counter 0. — INT1 (P3.3), Interrupt 1 Input or gate control input for counter 1. = TO(P3.4). Input to counter 0. T1(P3.5). input to counter 1. — WA (P3.6). The write control signal latches the data byte from port 0 into the extemal data memory. ~ RD (P3.7). The read contro! signal enables external data memory to port 0. XTAL1 XTAL 1 input to the oscillator’s high gain amplifier. XTAL 2 Required when a crystal is used. Connect to Vss when external source is used on XTAL 2. XTAL 2 output from the oscillator’s ampiifier. Input to the internal timing circuitry. A crystal or external source can be used. P2.0-P2.7 24-31 Port 2 is an 8-bit quasi-bidirectional VO port. It also emits the high-order address byte when accessing external memory. It is used for the high-order address and the control signals during program veritication. Port 2 can sink/source four LS TTL loads. Siemens Aktiengeselischaft 331

4?7E D MM 4235605 0029796 & MSIEG SAB 8052A/8032A SIEMENS AKTIENGESELLSCHAF Pin Definitions and Functions (cont'd) ‘Symbol Pin Input () | Function DIP-40__| PL-CC-44 | Output (0) a PSEN The programm store enable output is a control signal that enables the external program memory to the bus during extemal fetch operations. itis activated every six oscillator periods, except during external data memory accesses. Remains high during internal program execution. ALE Provides address latch enable output used for latching the address into external memory during normal operation. It is activated every six oscillator periods, except during an external data memory access. EA ‘When held at a TTL high level, the SAB 8052A executes instructions from the internal ROM when the PC is less than 8192. When held at a TTL low level, the SAB 8052A fetches all instructions from external program memory. For the SAB 8032A this pin must be tied low. P0.0-P0.7 | 39-32 Port 0 is an 8-bit open drain bidirectional VO port. It is also the multiplexed low-order address and data bus when using external memory. It is used for data output during program verification. Port 0 can sink/source eight LS TTL loads, Voo 44 +5, power supply during operation and program verification. . Pies | ‘sone Siemens Aktiengeselischaft 332

4?E D MM 8235605 0029797 & MBSIEG SIEMENS AKTIENGESELLSCHAF SAB 6052A/8032A T-49-19-05- Block Diagram Frequency Reference Counters ea Inne Suneenenneeeeeeeea Ws a | 1 ; at92Bytes ! Oscillator y' Three t6-Bit | | \\ Program 256 Bytes Timerevent | 1) timing Memory Data Memory Counters 1 1 (SAB 8052A only) | i | ‘SABBOS2A | i} ceu I | | | | \\ i | Programmable | | 1 64Kbyte Bus Serial Port { | Expansion Programmable 1/0 «Full Duplex UART | | t Controt * Synchronous i ij Shifter H H [Interrupts 1 Lope fe Interrupts Control Parallel Ports Serial Serial Address Data Bus Input Output and 1/0 Pins wcB00047 Siemens Aktiengesellschaft 333

4?E D MM 8235605 0029798 T MBSIEG SIEMENS AKTIENGESELLSCHAF SAB 8052A/8032A Th 99-19-05 Instruction Set Summary Arithmetic operations =) Aa [Add register to accumulator ft AOD Ades [at ret tw scamutor fe 0D _A@R__[adendvea RAMs surat ADD Atdata | Addimmeciate data to acoumulator 2 | A005 Af [aot acura win cay tag 11 ‘DDC Adirect Add direct byte to A with carry flag le a ADDC Aftdata ‘Add immediate data to A with carry flag [2 a SUBB ARn Subtract register from A with borrow 1 [a SUBS Adect_| ube creator A win boron [2a SUBB A@Ri ‘Subtract indirect RAM from A with borrow 1 SUBB Addidata Subtract immediate data from A with borrow ES 1 DEC Rn Decrement register 1 ic PTR [rene poner ne we A Sipy ard Div AB Divide A by B [1 [4 Siemens Aktiengesellschaft 334

47E D M@@ 8235605 0029799 1 MBSIEG SIEMENS AKTIENGESELLSCHAF SAB 8052A/6032A T-49-19-05 Instruction Set Summary (cont'd) Mnemonic | Description [eye | Cycle Logical operations ANL Adirect AND direct byte to accumulator let NL AGRI [ANDindvact RAMoacoumuiator tft ANL Grecia [AND accumulatortodrectoye et ANL direct,#data__| AND immediate data to direct byte [se ORL ARn OR register to accumulator — [1a ORL Adirect_ __[ORairect byte to acoumulator 2 XRL ARn __| Exclusive OR register to accumulator [1 [a xAL Grecia | Exclusive OR accumulatortodrectbyte 2 XRL direct,#data | Exclusive OR immediate data to direct byte js 2 RR A Rotate accumulator right 1 RRC A [Rotate Arightthrough cary fag }— 1 SWAP A ‘Swap nibbles within the accumulator [tt Siemens Aktiengeselischaft 335

4?E D MM 8235605 0029800 4 MMSIEG SIEMENS AKTIENGESELLSCHAF SAB 8052A/8032A J-49-17-8 Ss Instruction Set Summary (cont'd) Data transfer MoV ARn | Move register to accumulator [1 [a Mov Adirect’) __| Move direct byte to accumulator [2s Mov A@Ri Move indirect RAM to accumulator 1 Mov Aitdata Move immediate data to accumulator [2s Mov Ana [Move acounuistoriorepiter nt Mov Findirect _[Movedrectbytetoregiser 2 Mov Rndata | Move immediate datatoregister 21 Mov direct. A [Move accumulatortodrectbye [2 MOV direct,An Move register to direct byte le [2 MOV directirect _| Move direct byte to direct byte [3 [2 MOV __direc@R_| Move indirect RAM to direct byte [2 [2 Mov @Ri#data__| Move immediate data to indirect RAM 1 MOVE A@ADPTA | ov cle by role to DFTA macau [1 [2 move A@A+PC 2 MOVX A@DPTR __| Move external RAM (16-bit addr.) to accumulator 2 MOVX @oPTRA [Move AtoextoralRAM(te-titacér) | [2 Pus eved__[Pushdrecionw ows suck de XCH A@RI 1 *) MOV A,AAC is not a valid instruction Siemens Aktiengesellschaft 336

4?7E D MM 8235605 0029801 & MBSIEG r SAB 8052A/8032A SIEMENS AKTIENGESELLSCHAF 803 BS TY FH 1920S Instruction Set Summary (cont'd) Boolean variable manipulation CLR c Clear carry flag 1 CLR bit Clear direct bit 1 CPL bit Complement direct bit je ft ANL Cit AND direct bit to carry flag [2 2 ANL Coit AND complement of direct bit to cary 2 ORL Coit OR direct bit to carry flag 2 ORL Cybit OR complement of direct bit to carry 2 2 Siemens Aktiengeselischaft 337

u7E D mm 8235605 O027802 6 me SAB 8052A/8032A SIEMENS AKTIENGESELLSCHAF T-99-19-05° Instruction Set Summary (cont'd) neon [bwcinion (i J Program and machine control ACALL addr 11 ‘Absolute subroutine call [2 fe LCALL addr 16 Long subroutine call Is f2 RETI Return from interrupt 1 [2 AIMP, addr 11 Absolute jump [2 |e LMP addr 16 Long jump [3 |2 SJMP rel Short jump (relative addr.) 2 [2 MP @A+DPTR _| Jump indirect relative to the DPTR [1 2 wz rel ‘Jump if accumulator is zero 2 [2 NZ rel ‘Jump if accumulator is not zero 2 [2 JC rel Jump if carry flag is set j2_ [2 INC rel Jump i cary flag is not set le [2 JB bitrrel Jump if direct bit is set [32 JNB bityrel Jump if direct bit is not set [s__ [2 JBC bitrel Jump if direct bit is set and clear bit 2 CINE Adirect,rel__| Compare direct byte to A and jump if not equal [3 |2 CJNE A,fdata,rel ‘Comp. immed. to A and jump if not equal [a [2 CJNE Rn,#data,rel__ | Comp. immed. to reg. and jump if not equal [32 CJNE @Ri,#data,rel_| Comp. immed. to ind. and jump if not equal [s__ [2 DUNZ Rn,ret Decrement register and jump if not zero [2 [2 DUNZ direct,ret Decrement direct and jump if not zero isa NOP | No operation [1 ft Notes on data addressing modes: Rn Working register RO— R7 direct — 128 intemal RAM locations, any VO port, control or status register @Ri = Indirect internal or external RAM location addressed by register RO or R1 data = 8-it constant included in instruction data 16 — 16-bit constant included as bytes 2 and 3 of instruction bit ~ 128 software flags, any /O pin, control or status bit A = Accumulator Notes on program addressing modes addr 16 —Destination address for LCALL and LUMP may be anywhere within the 64 Kbyte program memory address space. addr11 __— Destination address for ACALL and AJMP will be within the same 2 Kbyte page of program memory as the first byte of the following instruction. rel SUMP and all conditional jumps include an 8-bit offset byte. Range is + 127/- 128 bytes relative to first byte of the following instruction. All mnemonics copyrighted © Intel Corporation 1980 Siemens Aktiengeselischaft 338

4?E D MM 8235605 0029803 T MMBSTEG SIEMENS AKTIENGESELLSCHAF SAB 8052A/8032A ~Y9-/G-05° Instruction Op Codes in Hexadecimal Order T ¥ Hex Number | Mnemonic | Operands Hex ‘Number | Mnemonic | Operands code | of bytes code | of bytes 00 1 NOP 33 4 RLC A o1 2 AJMP code addr 34 2 ADDC Aftdata 02 3 LJMP code addr 35 2 ADDC A,data addr 03 1 AR A 36 1 ADDC A@RO 04 1 INC A 37 it ADDC A@RI 05 2 INC data addr 38 1 ADDC ARO 06 1 ING @RO 39 1 ADDC ARI 07 1 INC @R1 3A 1 ADDC AR2 08 1 INC RO 3B 1 ADDC AR3 og 1 INC R1 3c 1 ADDC ARS OA 1 INC R2 3D 1 ADDC ARS 0B 1 INC R3 3E 1 ADDC A,R7 oc 1 INC R4 3F 1 ADDC A.R7 oD 1 INC R5 40 2 Jc code addr OE 1 INC R6 4 2 AJMP_ code addr OF 1 INC R7 42 2 ORL data addr,A 10 3 JBC bit addr,code addr 43 3 ORL data addr,#data W 2 ACALL code addr 44 2 ORL A#data 12 3 LCALL code addr 45 2 ORL A,data addr 13 1 RAC A 46 1 ORL A@RO 14 1 DEC A 47 1 ORL A@R1 15 2 DEC data addr 48 1 ORL ARO 16 1 DEC @RO 49 1 ORL ARI 17 1 DEC @Ri 4A 1 ORL AR2 18 1 DEC RO 4B 1 ORL ARB 19 1 DEC Rt 4c 1 ORL AR4 1A 1 DEC R2 4D 1 ORL ARS 1B 1 DEC R3 4E 1 ORL ARE 1c 1 DEC R4 4aF 1 ORL A,R7 1D 1 DEC RS 50 2 JNC code addr 1E 1 DEC RE 51 2 ACALL code addr 1F 1 DEC R7 52 2 ANL data addr,A 20 3 JB bit addr,code addr 53 3 ANL data addr,#tdata 21 2 AJMP code addr ‘54 2 ANL Aftdata 22 1 RET 55 2 ANL A.data addr 23 1 RL A 56 1 ANL A,@RO 24 2 ADD Ajtdata 57 1 ANL A@R1 25 2 ADD A.data addr 58 1 ANL ARO 26 1 ADD A,@RO 59 1 ANL ARI 27 1 ADD A@R1 SA 1 ANL AR2 28 1 ADD ARO 5B 1 ANL A.R3 23 1 ADD ARI 5c 1 ANL AWR4 2A 1 ADD AR2 5D 1 ANL ARS 2B 1 ADD AR 5E 1 ANL ARE 2c 1 ADD AR4 5F 1 ANL AR7 2D 1 ADD ARS 60 2 JZ code addr 2E 1 ADD ARE 61 2 AJMP- code addr OF 1 ADD AR7 62 2 XRL data addr,A 30 3 JNB bit addr,code addr 63 3 XRL data addr,#data 31 2 ACALL code addr 64 2 XRL Afdata 32 1 RETI 65 2 XRL A.data addr Siemens Aktiengeselischaft 339

47E D MM 8235605 0029804 1 MBSIEG 8052A/8032A SIEMENS AKTIENGESELLSCHAF SAB S03 T-¥9-19-05- Instruction Op Codes in Hexadecimal Order (cont'd) Hex [Number | Mnemonic | Operands Hex | Number | Mnemonic | Operands code | of bytes code | of bytes | 6s it XRL A.@RO 9 it ‘SUBB ARI 67 it XRL A@R1 oA it SUBB AR2 6s it XRL ARO 9B 1 SUBB ARS 69 ft XRL ARI gc [1 SUBB AWR4 6A |t XRL AR2 90 |1 SUBB ARS 6B it XRL AR3 9 {1 SUBB A\\RG ec it XRL ARS oF 4 ‘SUBB A\\R7 6D |1 XRL ARS Ao |2 ORL C,/bit addr 6E it XRL AR6 At |2 AJMP code addr er it XRL AR7 a2 [2 Mov ,bit addr 7 2 NZ code addr a3 it INC OPTR m (2 ACALL | code addr aa {4 MUL AB 7 2 ORL C,bit addr AS reserved 73 (4 JMP @A+DPTR AB 2 Mov @RO,data addr 7m 2 Mov Aitdata av {2 Mov @R1 data addr 7% |3 Mov data addr,#data aa 2 MoV RO,data addr 7% |2 Mov @RO,tdata ag 2 MOV Ri.data addr 7m |2 Mov @RI,#data AA |2 MoV Re,data addr 7 |2 Mov RO,#data AaB i2 mov R3,data addr 79 |2 Mov Ri.tdata ac |2 Mov Ré,data addr 7A 2 MOV R2#data AD |2 Mov R5,data addr 7B 2 Mov R3,ttdata AE |2 Mov R6,data addr 7o 2 mov R4,tdata ar 2 Mov R7,data addr 7 |2 Mov R5.stdata Bo |2 | ANL Cit addr 7E |2 Mov Ré,tdata Bi |2 ACALL | code addr TF 2 MoV R7.#tdata Be |2 PL bit addr Bo 2 SJMP code addr Bait CPL c at 2 AJMP code addr B4 |3 CJNE A,tdata,code addr ee |2 ANL C,bit addr BS {3 CJNE ‘A.data addr,code addr ast MOVC =| A.@AsPC Be |3 CINE @RO,#data,code addr 84 itl ov AB 87 {3 CJNE @AI ,#data,code addr a5 |3 Mov data addrdata addr «BBS 3 CJNE RO,#data,code addr a6 2 Mov data addr,@RO Bo |3 UNE Rit ,#data,code addr 87 2 MOV data addr@R1 BA |3 CJNE R2,#data,code addr ag 2 MOV data addr,RO BB 3 CJNE 3 ,##data,code addr eo 2 MOV data addr,R1 BC j3 CJNE Ra, #data,code addr BA 2 Mov data addr,R2 Bo |3 CINE RS ,#tdata,code addr eB 2 Mov data addr,R3 BE |3 CJNE R6,#data,code addr ec 2 Mov data addr,R4 BF |3 CJNE R7,#data,code addr ap |2 Mov data addr,A5 co j2 PUSH data addr BE 2 MoV data addr,R6 cr |2 AJMP code addr ar 2 mov data addr,R7 ce |2 CLR bit addr 90 [3 Mov DPTR,#data ca |4 cLR Cc a1 |2 ACALL | code addr ca |4 SWAP A 92 |2 Mov bit addr,C cs |2 XCH A.data addr 93 it MOovc =| A@A+DPTR ce it XCH A@RO 94 [2 SUBB Afdata c7 |1 XCH A@RI 95 j2 SUBB ‘A,data addr cat XCH A\\RO 96 it ‘SUBB A.@RO co it XCH ARI o7 it SUBB A@Rt cA 4 XCH AWR2 98 it ‘SUBB A,RO ce |i XCH A\\R3 Siemens Aktiengeselischaft 340

47E D MM 8235605 0029805 3 MBSIEG SAB 8052A/8032A SIEMENS AKTIENGESELLSCHAF T~49-! G-0F Instruction Op Codes in Hexadecimal Order (cont'd) Hex Mnemonic | Operands Hex | Number | Mnemonic | Operands code code | of bytes co |1 XCH ARS FD} 4 MoV RS,A cD | XCH ARS Fe | 1 MoV REA ce {4 XCH ARG Fe id Mov R7,A cr | 4 XCH ART — Do 2 POP data addr D1 2 ACALL code addr be 2 SETB bit adar p34 SETB c Dafa DA A DS 3 DJNZ data addr,code addr oe | 1 XCHD A@RO o7 1 XCHD A@RI Ds j2 DJNZ R0,code addr oo |2 DJNZ Ri, code addr DA |2 DUNZ R2,code addr OB 2 DJNZ R3,code addr De j2 DJNZ Ré4,code addr Dp 2 DUNZ R5,code addr DE |2 DUNZ Ré,code addr DF |2 DJNZ R7,code addr co |1 MOVX | A@DPTR. E1 |2 AJMP. code addr eo |4 MOVX | A@RO es | 4 MOVX | A@RI es {4 CLR A —5 |2 mov A.data addr) Ee |i MoV A.@RO ey 4 MOV A@RI Ee j1 Mov A\\RO Eo jt Mov ARI EA |1 Mov AR2 EB ft MOV ARS Ec | 1 Mov AR4 ED }1 Mov A.RS ce |i MOV ARS er |4 MOV ART Fo {4 MOvx — | @DPTRA Fi 2 ACALL — | code addr Fo | 4 Movx — | @RO,A F301 Movx =| @R1,A Fa | cPL A FS 2 MOV data addr,A Fé 1 MOV @RO,A e7 4 MOV @RIA Fei MoV ROA Fo jt MOV RLA FA | 4 Mov R2,A FBO} mov R3,A FO} 4 Mov R4,A *) MOV A,ACC is not a valid instruction Siemens Aktiengesellschaft 341

4?E D MM 6235605 0029406 5 MMSIEG SIEMENS AKTIENGESELLSCHAF SAB 8052A/8032A Tr¥G-19- os Absolute Maximum Ratings Ambient temperature under bias Oto 70°C Storage temperature —65 to + 150°C Voltage on any pin with respect to ground (Vss) -05to +7V Power dissipation 2w Note: Stresses above those listed under "Absolute Maximum Ratings" may cause perma- nent damage to the device. Exposure to absolute maximum rating conditions for exten- ded periods may affect device reliability. DC Characteristics Ta=0 to 70 °C; Vec = 5 V+ 10%;Vss = OV vu Input high voltage vec+05 |v |- (except RST/Veo and XTAL 2) Vo Input high voltage to voc+0.5 |V | XTAL1tovss RST/Vpo for reset, XTAL 2 veo Power-down voltage Vv | vec=0V to RST/VPo Vou Output low voltage, Vo | t= 1.6 mA Ports 1, 2,3 Vous Output low voltage _ Vo | tv =3.2mA Port 0, ALE, PSEN Ports 1, 2,3 Vout Output high voltage 24 Vi | fon == 400 uA i Port 0, ALE, PSEN ft ae Logical 0 input current - - 500 vA | Yu =0.45V Ports 1, 2,3 me Logical 0 input current ~20 mA | XTAL1 = vss XTAL2 vu =0.45V tis Input high current to vA | vin = Voo-1.5V RST/vPo for reset te Input leakage current vA | OV<viN< veo to port 0, EA tec Power supply current 175 mA | All outputs disconnected Siemens Aktiengesellschaft 342

/47E D- MM 8235605 0029807 7 MMSIEG SAB 8052A/8032A SIEMENS AKTIENGESELLSCHAF T- y 9-19-95 AC Characteristics Ta=0 °C to 70 °C; Voo= 5 V+ 10%; Vss=0V (Cc for port 0, ALE and PSEN outputs = 100 pF; C. for all other outputs = 80 pF) Program Memory Characteristics Syma | Prater ee Fema [oe Aitevce = 1.2 MHz to 12 MHz fee ‘fn __| ALE pulse width 2iac~a0|- ns inn [aAderess sowproate fsa |= teucgo [= ns tua _[AddresshoiateraLe fae |= reweena5 [=n tuw [ate tovatdinstuctonin [-f2g3 [= aterinto0 [ns true | PSEN pulse with fais | faves [= ns ae tox | Inputinstuction hold ater PSEN [o [- [a __ | - ns fone’) | inpwtinstucton foatatePsen |- [ea | eueica__ ns tome [Addess vaidaterPSEN [75 [= fue | - _{ns__ taza_| Address float to PSEN 0 [-. et +) Interfacing the SAB 8052A to devices with float times up to 75 ns is permissible. This limited bus contention will not cause any damage to port 0 drivers. Siemens Aktiengesellschaft 343

47E D MM 8235605 0029808 9 MMSIEG SAB 8052A/8032A SIEMENS AKTIENGESELLSCHAF T-49-19-05- External Data Memory Characteristics Variable clock 12 Miz clock ANCLCE 1.2 MHz to 12 funn | RD pulse wiath [40g [= feructoo [ns wwe [Wipuisewidn 400 omucn-too[- ns tune | Address hold aftr ALE jrse_[-famenas | ns wmuov [AD tovaiadatain [= fase | as fox | Data hod atter RO Ce ee ( wor | Data toa ater RO j= fer f= atece-70 Ins tuo [AE wvaldcaain i= st) =‘ ase 150s ior [Adesso valddaain [= [as [= [ota 168 [nw tum [ateowRorad [200 [200 [amia-so [amicus (ns trom | Address to WA or RO: [= [aevct90 [= ns fan | WR or RD high to ALE high [r29 [mena [mado [ns tom | Datasetup beforewWA 4a [| ucint50_ [ns tor [DataraganerWR (so |= [aes] ids Siemens Aktiengesellschatt 344

47E D MM 8235605 0029809 O M@BSIEG SAB 8052A/8032A SIEMENS AKTIENGESELLSCHAF T= 49-17-05 External Clock Drive XTAL 2 Variable clock Freq = 1.2 MHz to 12 MHz Bex a vet [Fautime feos Waveforms: External Clock Cycle t fox — sy Bt ae ee 25 25 25 f 08 08 tex A.C. Testing Input, Output, Float Waveforms ah 20 70 Test Points 0.65 08 08 ae 20 2.0 24 0.45 o8 98 0.45 Mcaago2s ‘AC. testing inputs are driven at 2.4 V for a logic “1” and 0.45 V for a logic "0". Timing measurements are made at 2.0 V for a logic "1" and 0.8 V for a logic "0". For timing purposes, the float state is defined as the point at which a PO pin sinks 3.2 mA or sources 400 yA at the voltage test levels. Siemens Aktiengeselischaft 345

42E D m™@ 8235605 0029810 7 WBSIEG ; SAB 8052A/8032A SIEMENS AKTIENGESELLSCHAF THY 9G O05 Program Memory Read Cycle ty tLe fiw -ofisee | ALE J PSEN#® h few eye! feel afte nm | tel <j Terao Data Memory Read Cycle 4py— | a) ALE | | PSEN# an ROH fue | tw “LL fay hel favo: ee VV WS ve (ae KY} {nw OY |teuz port? Adresse Address A15-A8 or SFR-P2 = Siemens Aktiengeselischaft 346

4Y7E D MM. 8235605 0029811 9 MBSIEG SAB 8052A/8032A SIEMENS AKTIENGESELLSCHAF THYI-N9-OS Data Memory Write Cycle fn ALE PSEN# btw y+ wre ana Nanex fuse foo an ve (me Mer mote wet adress A'S-AG oF SFRP2 Haro Recommended Oscillator Circuits ; f 19124 a TAL S20 tact +5V fr) .242MH 7k f 18120) 18(20) XTAL 2 XTAL2 7404 ToLS04 wesoooue €=30 pF 10pF Crystal Oscillator Mode Driving from External Source Pin numbers in (. ..) are specified for PL-CC-44 package Siemens Aktiengesellschatt 347

47E D MM 8235605 0029812 0 MBSIEG ; AB 8052A/8032A SIEMENS AKTIENGESELLSCHAF SAB 805: THY 9-]9-05- ROM Verification Characteristics Ta= 25 C+5 C; Voc=5 V+ 10%; Vss=O0V ve ne ™ Address to valid data [ovov [= fa feu ns ENABLE to val ata a oT Oscillator frequency Se ( ROM Verification P1.0-P17 p28. Pru tavay Feav, tenoz poe | vcoo00%e Address: P1.0-P1,7. = A0-A7 P2.0-P24 =AB-AI2 Data: Porto == D0-D7 Inputs: P2.5-P2.6, PSEN = vss ALE, EA | = TTLhigh level RSTiveo = Vi Siemens Aktiengeselischaft 348

“Y7E D Ml 8235605 0029813 2 MMSIEG oo SAB 8052A/8032A SIEMENS AKTIENGESELLSCHAF TAg-19-0S

Ordering Information

8-bit single-chip microcontroller ‘SAB 8052A-P Q67120-C195 with mask-programmable ROM (P-DIP40) ‘SAB 6032A-P for external memory (P-DIP40) SAB 8052A-N with mask-programmable ROM (PL-CC-44) SAB 8032A-N for extemal memory (PL-CC-44) Siemens Aktiengesellschaft 349