SAA-XC886C-8FFA5V

SAA-XC886CLM INFINEON | Alldatasheet

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V1.1 2010-08 Microcontrollers 8-Bit SAA-XC886CLM 8-Bit Single Chip Microcontroller

81726 Munich, Germany

© 2010 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

V1.1 2010-08 Microcontrollers 8-Bit SAA-XC886CLM 8-Bit Single Chip Microcontroller

Data Sheet V1.1, 2010-08 SAA-XC886 Data Sheet Revision History: V1.1 2010-08 Previous Versions: V1.0 2009-09 Page Subjects (major chan ges since last revision) 126 New parameter on weighted average temperature is added. 126 Maximum value of parameter VCDM is increased from 500 V to 750 V. 126 Parameter VCDM is no longer differentiated between VDDC and all other pins. We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: mcdocu.comments@infineon.com

Data Sheet I-1 V1.1, 2010-08 Table of Contents

Data Sheet I-2 V1.1, 2010-08

Data Sheet I-3 V1.1, 2010-08

Data Sheet 1 V1.1, 2010-08 SAA-XC886CLM8-Bit Single Chip Microcontroller

1 Summary of Features

The SAA-XC886 has the following features:

• High-performance XC800 Core – compatible with sta ndard 8051 processor – two clocks per machine cycle architecture (for memory access without wait state) – two data pointers
• On-chip memory – 12 Kbytes of Boot ROM – 256 bytes of RAM – 1.5 Kbytes of XRAM – 24/32 Kbytes of Flash (includes memory protection strategy)
• I/O port supply at 5.0 V and core logic supply at 2.5 V (generated by embedded voltage regulator) (more features on next page) Figure 1 SAA-XC886 Functional Units Port 0 Port 1 Port 2 Port 3 XC800 Core UART ADC 10-bit 8-channel Boot ROM 12K x 8 XRAM 1.5K x 8 RAM 256 x 8 On-Chip Debug Support Timer 0 16-bit Timer 1 16-bit Timer 2 16-bit UART 1 SSCFlash 24K/32K x 8 Capture/Compare Unit 16-bit Compare Unit 16-bit 7-bit Digital I/O 8-bit Digital I/O 8-bit Digital I/O 8-bit Digital/ Analog Input Port 4MDU CORDIC MultiCAN Timer 21 16-bit Watchdog Timer 3-bit Digital I/O

Data Sheet 2 V1.1, 2010-08 Features: (continued)

• Power-on reset generation
• Brownout detection fo r core logic supply
• On-chip OSC and PLL for clock generation – PLL loss-of-lock detection
• Power saving modes – slow-down mode – idle mode – power-down mode with wake-up ca pability via RXD or EXINT0 – clock gating contro l to each peripheral
• Programmable 16-bit Watchdog Timer (WDT)
• S i x p o r t s – Up to 48 pins as digital I/O – 8 pins as digital/analog input
• 8-channel, 10-bit ADC
• Four 16-bit timers – Timer 0 and Time r 1 (T0 and T1) – Timer 2 and Ti mer 21 (T2 and T21)
• Multiplication/Division Unit fo r arithmetic operations (MDU)
• Software libraries to support fl oating point and MDU calculations
• CORDIC Coprocessor for computation of trigonometric, hy perbolic and linear functions
• MultiCAN with 2 nodes , 32 message objects
• Capture/compare unit for PW M signal generation (CCU6)
• Two full-duplex serial in terfaces (UART and UART1)
• Synchronous serial channel (SSC)
• On-chip debug support – 1 Kbyte of monitor ROM (part of the 12-Kbyte Boot ROM) – 64 bytes of monitor RAM
• Package: – PG-TQFP-48
• Temperature range TA: – SAA (-40 to 140 °C)

Data Sheet 3 V1.1, 2010-08 SAA-XC886 Variant Devices The SAA-XC886 product family features devices with di fferent confi gurations and program memory sizes, to offer cost-eff ective solutions for different application requirements. The list of SAA-XC886 device configurations are summarized in Table 1. Note: For variants with LIN BSL support, only LIN BSL is available regardless of the availability of the CAN module. As this document refers to all the derivatives, some de scription may not apply to a specific product. For simpli city, all versions are refe rred to by the term SAA-XC886 throughout this document.

Ordering Information

The ordering code for Infineo n Technologies microcontrol lers provides an exact reference to the required product. This ordering code identifies:

• The derivative itself, i.e. its function set, the temper ature range, and the supply voltage
• The package and the type of delivery For the available ordering codes for the SAA- XC886, please refer to your responsible sales representative or your local distributor. Table 1 Device Profile Device Type Sales Type Program Memory (Kbytes) CAN Module LIN BSL Support MDU Module Flash SAA-XC886-8FFA 5V 32 No No No SAA-XC886C-8FFA 5V 32 Yes No No SAA-XC886CM-8FFA 5V 32 Yes No Yes SAA-XC886LM-8FFA 5V 32 No Yes Yes SAA-XC886CLM-8FFA 5V 32 Yes Yes Yes SAA-XC886-6FFA 5V 24 No No No SAA-XC886C-6FFA 5V 24 Yes No No SAA-XC886CM-6FFA 5V 24 Yes No Yes SAA-XC886LM-6FFA 5V 24 No Yes Yes SAA-XC886CLM-6FFA 5V 24 Yes Yes Yes

General Device Information Data Sheet 4 V1.1, 2010-08

2 General Device Information

Chapter 2 contains the block diagram, pin configurations, definitions and functions of the SAA-XC886.

2.1 Block Diagram

The block diagram of the SAA-XC886 is shown in Figure 2. Figure 2 SAA-XC886 Block Diagram ADC Port 0Port 1Port 2Port 3 UART1CORDIC SSCMDU Timer 2 12-Kbyte Boot ROM1) 256-byte RAM 64-byte monitor RAM 1.5-Kbyte XRAM 24/32-Kbyte Flash XC800 Core T0 & T1 UART 1) Includes 1-Kbyte monitor ROM P0.0 - P0.5, P0.7 P1.0 - P1.7 P3.0 - P3.7 P2.0 - P2.7 VAREF VAGNDClock Generator

9.6 MHz

P4.0 - P4.1, P4.3 WDT OCDS

General Device Information Data Sheet 5 V1.1, 2010-08

2.2 Logic Symbol

The logic symbols of the SAA-XC886 are shown in Figure 3. Figure 3 SAA-XC886 Logic Symbol XC886 VDDP VSSP VDDC VSSC VAREF VAGND XTAL1 XTAL2 TMS RESET MBC Port 0 7-Bit Port 1 8-Bit Port 3 8-Bit Port 2 8-Bit Port 4 3-Bit

General Device Information Data Sheet 6 V1.1, 2010-08

2.3 Pin Configuration

The pin configuration of th e XC886, which is based on the PG-TQFP-48 package, is shown in Figure 4. Figure 4 XC886 Pin Configurat ion, PG-TQFP-48 Package (top view) XC886 123 4 56789 1 0 1 1 1 2 36 35 34 33 32 31 30 29 28 27 26 25 RESET P3.5 P3.4 P4.1 P4.0 P0.3 P0.4 MBC P3.2 P3.3 P0.7 VDDP VSSP P0.0 P0.5 P1.6 P1.7 VSSC VDDC XTAL2 XTAL1 TMS P2.2 VDDP VSSP P2.0 P2.1 P2.4 P2.3 P2.5 P2.6 VAREF VAGND P0.2 P0.1 P1.3 P1.4 P1.2 P1.0 P1.1 P1.5 P2.7 P3.0 P3.1 P3.6 P3.7 P4.3 VDDP

General Device Information Data Sheet 7 V1.1, 2010-08

2.4 Pin Definitions and Functions

The functions and default st ates of the SAA-XC886 exte rnal pins are provided in Table 2. Table 2 Pin Definiti ons and Functions Symbol Pin Number Type Reset State Function P0 I/O Port 0 Port 0 is an 8-bit bidirectional general purpose I/O port. It can be used as alternate functions for the JTAG, CCU6, UART, UART1, Timer 2, Timer 21, MultiCAN and SSC. P0.0 11 Hi-Z TCK_0 T12HR_1 CC61_1 CLKOUT_0 RXDO_1 JTAG Clock Input CCU6 Timer 12 Hardware Run Input Input/Output of Capture/Compare channel 1 Clock Output UART Transmit Data Output P0.1 13 Hi-Z TDI_0 T13HR_1 RXD_1 RXDC1_0 COUT61_1 EXF2_1 JTAG Serial Data Input CCU6 Timer 13 Hardware Run Input UART Receive Data Input MultiCAN Node 1 Receiver Input Output of Capture/Compare channel 1 Timer 2 External Flag Output P0.2 12 PU CTRAP_2 TDO_0 TXD_1 TXDC1_0 CCU6 Trap Input JTAG Serial Data Output UART Transmit Data Output/Clock Output MultiCAN Node 1 Transmitter Output P0.3 48 Hi-Z SCK_1 COUT63_1 RXDO1_0 SSC Clock Input/Output Output of Capture/Compare channel 3 UART1 Transmit Data Output

General Device Information Data Sheet 8 V1.1, 2010-08 P0.4 1 Hi-Z MTSR_1 CC62_1 TXD1_0 SSC Master Transmit Output/ Slave Receive Input Input/Output of Capture/Compare channel 2 UART1 Transmit Data Output/Clock Output P0.5 2 Hi-Z MRST_1 EXINT0_0 T2EX1_1 RXD1_0 COUT62_1 SSC Master Receive Input/Slave Transmit Output External Interrupt Input 0 Timer 21 External Trigger Input UART1 Receive Data Input Output of Capture/Compare channel 2 P0.7 47 PU CLKOUT_1 Clock Output Table 2 Pin Definiti ons and Functions (cont’d) Symbol Pin Number Type Reset State Function

General Device Information Data Sheet 9 V1.1, 2010-08 P1 I/O Port 1 Port 1 is an 8-bit bidirectional general purpose I/O port. It can be used as alternate functions for the JTAG, CCU6, UART, Timer 0, Timer 1, Timer 2, Timer 21, MultiCAN and SSC. P1.0 26 PU RXD_0 T2EX RXDC0_0 UART Receive Data Input Timer 2 External Trigger Input MultiCAN Node 0 Receiver Input P1.1 27 PU EXINT3 T0_1 TDO_1 TXD_0 TXDC0_0 External Interrupt Input 3 Timer 0 Input JTAG Serial Data Output UART Transmit Data Output/Clock Output MultiCAN Node 0 Transmitter Output P1.2 28 PU SCK_0 SSC Clock Input/Output P1.3 29 PU MTSR_0 TXDC1_3 SSC Master Transmit Output/Slave Receive Input MultiCAN Node 1 Transmitter Output P1.4 30 PU MRST_0 EXINT0_1 RXDC1_3 SSC Master Receive Input/ Slave Transmit Output External Interrupt Input 0 MultiCAN Node 1 Receiver Input P1.5 31 PU CCPOS0_1 EXINT5 T1_1 EXF2_0 RXDO_0 CCU6 Hall Input 0 External Interrupt Input 5 Timer 1 Input Timer 2 External Flag Output UART Transmit Data Output Table 2 Pin Definiti ons and Functions (cont’d) Symbol Pin Number Type Reset State Function

General Device Information Data Sheet 10 V1.1, 2010-08 P1.6 8 PU CCPOS1_1 T12HR_0 EXINT6_0 RXDC0_2 T21_1 CCU6 Hall Input 1 CCU6 Timer 12 Hardware Run Input External Interrupt Input 6 MultiCAN Node 0 Receiver Input Timer 21 Input P1.7 9 PU CCPOS2_1 T13HR_0 T2_1 TXDC0_2 CCU6 Hall Input 2 CCU6 Timer 13 Hardware Run Input Timer 2 Input MultiCAN Node 0 Transmitter Output P1.5 and P1.6 can be used as a software chip select output for the SSC. Table 2 Pin Definiti ons and Functions (cont’d) Symbol Pin Number Type Reset State Function

General Device Information Data Sheet 11 V1.1, 2010-08 P2 I Port 2 Port 2 is an 8-bit general purpose input-only port. It can be used as alternate functions for the digital inputs of the JTAG and CCU6. It is also used as the analog inputs for the ADC. P2.0 14 Hi-Z CCPOS0_0 EXINT1_0 T12HR_2 TCK_1 CC61_3 AN0 CCU6 Hall Input 0 External Interrupt Input 1 CCU6 Timer 12 Hardware Run Input JTAG Clock Input Input of Capture/Compare channel 1 Analog Input 0 P2.1 15 Hi-Z CCPOS1_0 EXINT2_0 T13HR_2 TDI_1 CC62_3 AN1 CCU6 Hall Input 1 External Interrupt Input 2 CCU6 Timer 13 Hardware Run Input JTAG Serial Data Input Input of Capture/Compare channel 2 Analog Input 1 P2.2 16 Hi-Z CCPOS2_0 CTRAP_1 CC60_3 AN2 CCU6 Hall Input 2 CCU6 Trap Input Input of Capture/Compare channel 0 Analog Input 2 P2.3 19 Hi-Z AN3 Analog Input 3 P2.4 20 Hi-Z AN4 Analog Input 4 P2.5 21 Hi-Z AN5 Analog Input 5 P2.6 22 Hi-Z AN6 Analog Input 6 P2.7 25 Hi-Z AN7 Analog Input 7 Table 2 Pin Definiti ons and Functions (cont’d) Symbol Pin Number Type Reset State Function

General Device Information Data Sheet 12 V1.1, 2010-08 P3 I/O Port 3 Port 3 is an 8-bit bidirectional general purpose I/O port. It can be used as alternate functions for CCU6, UART1, Timer 21 and MultiCAN. P3.0 35 Hi-Z CCPOS1_2 CC60_0 RXDO1_1 CCU6 Hall Input 1 Input/Output of Capture/Compare channel 0 UART1 Transmit Data Output P3.1 36 Hi-Z CCPOS0_2 CC61_2 COUT60_0 TXD1_1 CCU6 Hall Input 0 Input/Output of Capture/Compare channel 1 Output of Capture/Compare channel 0 UART1 Transmit Data Output/Clock Output P3.2 37 Hi-Z CCPOS2_2 RXDC1_1 RXD1_1 CC61_0 CCU6 Hall Input 2 MultiCAN Node 1 Receiver Input UART1 Receive Data Input Input/Output of Capture/Compare channel 1 P3.3 38 Hi-Z COUT61_0 TXDC1_1 Output of Capture/Compare channel 1 MultiCAN Node 1 Transmitter Output P3.4 39 Hi-Z CC62_0 RXDC0_1 T2EX1_0 Input/Output of Capture/Compare channel 2 MultiCAN Node 0 Receiver Input Timer 21 External Trigger Input P3.5 40 Hi-Z COUT62_0 EXF21_0 TXDC0_1 Output of Capture/Compare channel 2 Timer 21 External Flag Output MultiCAN Node 0 Transmitter Output P3.6 33 PD CTRAP_0 CCU6 Trap Input Table 2 Pin Definiti ons and Functions (cont’d) Symbol Pin Number Type Reset State Function

General Device Information Data Sheet 13 V1.1, 2010-08 P3.7 34 Hi-Z EXINT4 COUT63_0 External Interrupt Input 4 Output of Capture/Compare channel 3 Table 2 Pin Definiti ons and Functions (cont’d) Symbol Pin Number Type Reset State Function

General Device Information Data Sheet 14 V1.1, 2010-08 P4 I/O Port 4 Port 4 is an 8-bit bidirectional general purpose I/O port. It can be used as alternate functions for CCU6, Timer 0, Timer 1, Timer 21 and MultiCAN. P4.0 45 Hi-Z RXDC0_3 CC60_1 MultiCAN Node 0 Receiver Input Output of Capture/Compare channel 0 P4.1 46 Hi-Z TXDC0_3 COUT60_1 MultiCAN Node 0 Transmitter Output Output of Capture/Compare channel 0 P4.3 32 Hi-Z EXF21_1 COUT63_2 Timer 21 External Flag Output Output of Capture/Compare channel 3 Table 2 Pin Definiti ons and Functions (cont’d) Symbol Pin Number Type Reset State Function

General Device Information Data Sheet 15 V1.1, 2010-08 VDDP 7, 17, 43 – – I/O Port Supply (5.0 V) Also used by EVR and analog modules. All pins must be connected. VSSP 18, 42 – – I/O Port Ground All pins must be connected. VDDC 6 – – Core Supply Monitor (2.5 V) VSSC 5 – – Core Supply Ground VAREF 24 – – ADC Reference Voltage VAGND 23 – – ADC Reference Ground XTAL1 4 I Hi-Z External Oscillator Input (backup for on-chip OSC, normally NC) XTAL2 3 O Hi-Z External Oscillator Output (backup for on-chip OSC, normally NC) TMS 10 I PD Test Mode Select RESET 41 I PU Reset Input MBC1) 44 I PU Monitor & BootStrap Loader Control 1) An external pull-up device in the range of 4.7 k Ω to 100 kΩ. is required to enter user mode. Alternatively MBC can be tied to high if alternate functions (for debugging) of the pin are not utilized. Table 2 Pin Definiti ons and Functions (cont’d) Symbol Pin Number Type Reset State Function

Data Sheet 16 V1.1, 2010-08

3 Functional Description

Chapter 3 provides an overview of the SAA-XC886 functional description.

3.1 Processor Architecture

The SAA-XC886 is based on a high-performance 8-bit Central Processing Unit (CPU) that is compatible with the standard 8051 processor. While the standard 8051 processor is designed around a 12-clock machine cycl e, the SAA-XC886 CPU uses a 2-clock machine cycle. This allows fast access to ROM or RAM me mories without wait state. Access to the Flash memory, however, requ ires an additional wait state (one machine cycle). The instruction set consists of 45% one-byte, 41% two-byte and 14% three-byte instructions. The SAA-XC886 CPU provides a range of debugging features, including basic stop/start, single-step execution, break point support and r ead/write access to the data memory, program memory and Special Function Registers (SFRs). Figure 5 shows the CPU functional blocks. Figure 5 CPU Block Diagram Register Interface ALU UART Core SFRs 16-bit Registers & Memory Interface Opcode Decoder State Machine & Power Saving Interrupt Controller Multiplier / Divider Opcode & Immediate Registers Timer 0 / Timer 1 Internal Data Memory External SFRs External Data Memory Program Memory fCCLK Memory Wait Reset Legacy External Interrupts (IEN0, IEN1) External Interrupts Non-Maskable Interrupt

Data Sheet 17 V1.1, 2010-08

3.2 Memory Organization

The SAA-XC886 CPU operates in the following five address spaces:

• 12 Kbytes of Boot ROM program memory
• 256 bytes of intern al RAM data memory
• 1.5 Kbytes of XRAM memory (XRAM can be read/written as program memory or external data memory)
• A 128-byte Special Function Register area
• 24/32 Kbytes of Flash program memory Figure 6 illustrates the memory address spaces of the 32-Kbyte Flash devices. For the 24-Kbyte Flash devices, the shaded banks are not available. Figure 6 Memory Map of SAA-XC886 Flash Device 0000H 2000H 4000H 6000H F000H C000H F600H FFFFH 7000H 8000H P-Flash Banks 2 and 3 2 x 4 Kbytes Boot ROM

12 Kbytes

1.5 Kbytes

Program Space External Data Space Internal Data Space Internal RAM XRAM

4 Kbytes

2 x 4 Kbytes1) In 24-Kbyte Flash devices, the upper 2- Kbyte of Banks 4 and 5 are not available.

Data Sheet 18 V1.1, 2010-08

3.2.1 Memory Protection Strategy

The SAA-XC886 memory protection strategy includes:

• Read-out protection: The user is able to protect the contents in the Flash memory from being read – Flash protection is enabled by progr amming a valid password (8-bit non-zero value) via BSL mode 6.
• Flash program and erase protection.

3.2.1.1 Flash Memory Protection

As long as a valid password is available, all external access to the device, including the Flash, will be blocked. For additional security, the Flash hardware protection can be enabled to implement a second layer of read-out protection, as well as to enable program and erase protection. Flash hardware protection is available only for Flash devices and comes in two modes:

• Mode 0: Only the P-Flash is prot ected; the D-Flash is unprotected
• Mode 1: Both the P-Flash and D-Flash are protected The selection of each protection mode and the restrictions imposed are summarized in Table 3. Table 3 Flash Protection Modes Flash Protection Without hardware protection With hardware protection Hardware Protection Mode -0 1 Activation Program a valid password via BSL mode 6 Selection Bit 4 of password = 0 B it 4 of password = 1 MSB of password = 0 Bit 4 of password = 1 MSB of password = 1 P-Flash contents can be read by Read instructions in any program memory Read instructions in the P-Flash Read instructions in the P-Flash or D- Flash External access to P-Flash Not possible Not possible Not possible P-Flash program and erase Possible Not possible Not possible D-Flash contents can be read by Read instructions in any program memory Read instructions in any program memory Read instructions in the P-Flash or D- Flash

Data Sheet 19 V1.1, 2010-08 BSL mode 6, which is used for enabling Flash protection, can also be used for disabling Flash protection. Here, the programmed pa ssword must be provided by the user. A password match triggers an automatic er ase of the protected P-Flash and D-Flash contents, including the prog rammed password. The Flash protection is then disabled upon the next reset. Although no protection scheme can be considered infallible, the SAA-XC886 memory protection strategy provides a very high level of prot ection for a general purpose microcontroller. External access to D-Flash Not possible Not possible Not possible D-Flash program Possible Possible Not possible D-Flash erase Possible Possible, on condition that bit DFLASHEN in register MISC_CON is set to 1 prior to each erase operation Not possible Table 3 Flash Protection Modes (cont’d) Flash Protection Without hardware protection With hardware protection

Data Sheet 20 V1.1, 2010-08

3.2.2 Special Function Register

The Special Function Registers (SFRs) occupy direct internal data memory space in the range 80H to FFH. All registers, except the program counter, reside in the SFR area. The SFRs include pointers and registers that provide an interface between the CPU and the on-chip peripherals. As the 128-SFR range is less than th e total number of registers required, address extension mechanisms ar e required to increa se the number of addressable SFRs. The address extension mechanisms include:

• Mapping
• P a g i n g

3.2.2.1 Address Extension by Mapping

Address extension is performed at the syst em level by mapping. The SFR area is extended into two portions: the standard (non-mapped) SFR area and the mapped SFR area. Each portion supports the same address range 80H to FFH, bringing the number of addressable SFRs to 256. The extended address range is not directly controlled by the CPU instruction itself, but is derived from bi t RMAP in the system control register SYSCON0 at address 8F H. T o a c c e s s S F R s i n t h e mapped area, bit RMAP in SFR SYSCON0 must be set. Alternatively, the SFRs in the standard area can be accessed by clearing bit RMAP. The SFR area can be selected as shown in Figure 7. As long as bit RMAP is set, the mapped SFR area can be accessed. This bit is not cleared automatically by hardware. Thus , before standard/ma pped registers are accessed, bit RMAP must be cleared/set, respectively, by software.

Data Sheet 21 V1.1, 2010-08 Figure 7 Address Extension by Mapping Module 1 SFRs …... SYSCON0.RMAP SFR Data (to/from CPU) rw Standard Area (RMAP = 0) …... 80H FF H 80H FF H Direct Internal Data Memory Address Mapped Area (RMAP = 1) Module 2 SFRs Module n SFRs Module (n+1) SFRs Module (n+2) SFRs Module m SFRs

Data Sheet 22 V1.1, 2010-08 Note: The RMAP bit should be cleared/set by ANL or ORL instructions.

3.2.2.2 Address Extension by Paging

Address extension is further performed at the module level by paging. With the address extension by mapping, the SAA-XC886 has a 256-SFR address range. However, this is still less than the total number of SFRs needed by the on-chip peripherals. To meet this requirement, some peripherals have a built-i n local address extens ion mechanism for increasing the number of addressable SFRs. The extended address range is not directly controlled by the CPU instruction itself, but is derived from bit field PAGE in the module page register MOD_PAGE. Hence, the bi t field PAGE must be programmed before accessing the SFR of the target module. Each module may contain a different number of pages and a different number of SF Rs per page, dependi ng on the specific requirement. Besides setting the correct RMAP bit value to select the SFR area, the user must also ensure that a valid PAGE is selected to target the desired SFR. A page inside the extended address range can be selected as shown in Figure 8. SYSCON0 System Control Register 0 Reset Value: 04 H 76543210

0 IMODE 0 1 0 RMAP

Field Bits Type Description RMAP 0r w Interrupt Node XINTR0 Enable

0 The access to the st andard SFR area is

1 The access to the m apped SFR area is

Returns 1 if read; should be written with 1. 0 [7:5], 3,1 r Reserved Returns 0 if read; should be written with 0.

Data Sheet 23 V1.1, 2010-08 Figure 8 Address Exte nsion by Paging In order to access a register located in a page different from the actual one, the current page must be exited. This is done by reprog ramming the bit fi eld PAGE in the page register. Only then can the desired access be performed. If an interrupt routine is initiated be tween the page register access and the module register access, and the interrupt needs to access a register located in another page, the current page setting can be saved, the new one programmed and the old page setting restored. This is possible with the storage fields STx (x = 0 - 3) for the save and restore action of the current page setting. By indicating which storage bit field should be used in parallel with the new page value, a single write operation can:

• Save the contents of PAGE in STx be fore overwriting with the new value (this is done in the beginning of the interrupt routine to save the current page setting and program the new page number); or SFR0 SFR1 SFRx …... PAGE 0 SFR0 SFR1 SFRy …... PAGE 1 …... SFR0 SFR1 SFRz …... PAGE q MOD_PAGE.PAGE SFR Address (from CPU) SFR Data (to/from CPU) rw Module

Data Sheet 24 V1.1, 2010-08

• Overwrite the contents of PAGE with the co ntents of STx, ignoring the value written to the bit positions of PAGE (this is done at the end of the interrupt ro utine to restore the previous page setting before the interrupt occurred) Figure 9 Storage El ements for Paging With this mechanism, a certain number of interrupt routines (or other routines) can perform page changes without reading and storing the previously used page information. The use of only write oper ations makes the system simp ler and faster. Consequently, this mechanism significantly improves the performance of short interrupt routines. The SAA-XC886 supports local address extension for:
• Parallel Ports
• Analog-to-Digital Converter (ADC)
• Capture/Compare Unit 6 (CCU6)
• System Control Registers PAGE ST0 ST1 ST2 ST3 value update from CPU STNR

Data Sheet 25 V1.1, 2010-08 The page register has the following definition: MOD_PAGE Page Register for module MOD Reset Value: 00 H 76543210 OP STNR 0 PAGE ww rr w Field Bits Type Description PAGE [2:0] rw Page Bits When written, the value indicates the new page. When read, the value indicates the currently active page. STNR [5:4] w Storage Number This number indicates which storage bit field is the target of the operation defined by bit field OP. If OP = 10B, the contents of PAGE are saved in STx before being overwritten with the new value. If OP = 11 the contents of PAGE are overwritten by the contents of STx. The value written to the bit positions of PAGE is ignored. 00 ST0 is selected. 01 ST1 is selected. 10 ST2 is selected. 11 ST3 is selected.

Data Sheet 26 V1.1, 2010-08

3.2.3 Bit Protection Scheme

The bit protection scheme prevents direct software writing of selected bits (i.e., protected bits) using the PASSWD register. When the bit field MODE is 11B, writing 10011B to the bit field PASS opens access to writing of all protected bits, and writing 10101B to the bit field PASS closes access to writing of all prot ected bits. In both cases, the value of the bit field MODE is not changed even if PASSWD register is written with 98H or A8H. It can only be changed when bit field PASS is written with 11000B, for example, writing D0H to PASSWD register disables the bit protection scheme. Note that access is opened for maximum 32 CCLKs if the “close access” password is not written. If “open access” password is written again before the end of 32 CCLK cycles, there will be a recount of 32 CCLK cycles. The protecte d bits include the N- and K- Divider bits, NDIV and KDIV; the Watchdog Timer enable bit, WDTEN; and the power- down and slow-down enable bits, PD and SD. OP [7:6] w Operation 0X Manual page mode. Th e value of STNR is ignored and PAGE is directly written.

10 New page programming with automatic page

saving. The value written to the bit positions of PAGE is stored. In parallel, the previous contents of PAGE are saved in the storage bit field STx indicated by STNR. 11 Automatic restore page action. The value written to the bit positions PAGE is ignored and instead, PAGE is overwritten by the contents of the storage bit field STx indicated by STNR. 0 3r Reserved Returns 0 if read; should be written with 0. Field Bits Type Description

Data Sheet 27 V1.1, 2010-08

3.2.3.1 Password Register

Password Register Reset Value: 07 H 76543210 PASS PROTECT _S MODE wh rh rw Field Bits Type Description MODE [1:0] rw Bit Protection Scheme Control Bits

00 Scheme disabled - di rect access to the

protected bits is allowed.

11 Scheme enabled - the bi t field PASS has to be

written with the passwords to open and close the access to protected bits. (default) Others:Scheme Enabled. These two bits cannot be written directly. To change the value between 11B and 00B, the bit field PASS must be written with 11000B; only then, will the MODE[1:0] be registered. PROTECT_S 2r h Bit Protection Signal Status Bit This bit shows the status of the protection. 0 Software is able to writ e to all protected bits.

1 Software is unable to write to any protected

bits. PASS [7:3] wh Password Bits The Bit Protection Scheme only recognizes three patterns. 11000B Enables writing of the bit field MODE. 10011B Opens access to writing of all protected bits. 10101B Closes access to writing of all protected bits

Data Sheet 28 V1.1, 2010-08

3.2.4 SAA-XC886 Register Overview

The SFRs of the SAA-XC886 are organized into groups a ccording to their functional units. The contents (bits) of the SFRs are summarized in Chapter 3.2.4.1 to Chapter 3.2.4.14. Note: The addresses of the bitaddressable SFRs appear in bold typeface.

3.2.4.1 CPU Registers

The CPU SFRs can be accessed in both the standard and ma pped memory areas (RMAP = 0 or 1). Table 4 CPU Register Overview A d d r R e g i s t e r N a m e B i t 76543210 RMAP = 0 or 1 81H SP Reset: 07 HStack Pointer Register Bit Field SP Type rw 82H DPL Reset: 00 HData Pointer Register Low Bit Field DPL7 DPL6 DPL5 DPL4 DPL3 DPL2 DPL1 DPL0 Type rw rw rw rw rw rw rw rw 83H DPH Reset: 00 HData Pointer Register High Bit Field DPH7 DPH6 DPH5 DPH4 DPH3 DPH2 DPH1 DPH0 Type rw rw rw rw rw rw rw rw 87H PCON Reset: 00 HPower Control Register Bit Field SMOD 0 GF1 GF0 0 IDLE Type rw r rw rw r rw 88H TCON Reset: 00 HTimer Control Register Bit Field TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 Type rwh rw rwh rw rwh rw rwh rw 89H TMOD Reset: 00 HTimer Mode Register Bit Field GATE T1S T1M GATE T0S T0M Type rw rw rw rw rw rw 8AH TL0 Reset: 00 HTimer 0 Register Low Bit Field VAL Type rwh 8BH TL1 Reset: 00 HTimer 1 Register Low Bit Field VAL Type rwh 8CH TH0 Reset: 00 HTimer 0 Register High Bit Field VAL Type rwh 8DH TH1 Reset: 00 HTimer 1 Register High Bit Field VAL Type rwh 98H SCON Reset: 00 HSerial Channel Control Register Bit Field SM0 SM1 SM2 REN TB8 RB8 TI RI Type rw rw rw rw rw rwh rwh rwh 99H SBUF Reset: 00 HSerial Data Buffer Register Bit Field VAL Type rwh

Data Sheet 29 V1.1, 2010-08

3.2.4.2 MDU Registers

The MDU SFRs can be accessed in the mapped memory area (RMAP = 1). A2H EO Reset: 00 HExtended Operation Register Bit Field 0 TRAP_ EN

0 DPSE

A8H IEN0 Reset: 00 HInterrupt Enable Register 0 Bit Field EA 0 ET2 ES ET1 EX1 ET0 EX0 T y p e r w r r wr wr wr wr wr w B8H IP Reset: 00 HInterrupt Priority Register Bit Field 0 PT2 PS PT1 PX1 PT0 PX0 T y p e r r wr wr wr wr wr w B9H IPH Reset: 00 HInterrupt Priority High Register Bit Field 0 PT2H PSH PT1H PX1H PT0H PX0H T y p e r r wr wr wr wr wr w D0H PSW Reset: 00 HProgram Status Word Register Bit Field CY AC F0 RS1 RS0 OV F1 P Type rwh rwh rw rw rw rwh rw rh E0H ACC Reset: 00 HAccumulator Register Bit Field ACC7 ACC6 ACC5 ACC4 ACC3 ACC2 ACC1 ACC0 Type rw rw rw rw rw rw rw rw E8H IEN1 Reset: 00 HInterrupt Enable Register 1 Bit Field ECCIP ECCIP ECCIP ECCIP EXM EX2 ESSC EADC Type rw rw rw rw rw rw rw rw F0H B Reset: 00 HB Register Bit Field B7 B6 B5 B4 B3 B2 B1 B0 Type rw rw rw rw rw rw rw rw F8H IP1 Reset: 00 HInterrupt Priority 1 Register Bit Field PCCIP PCCIP PCCIP PCCIP PXM PX2 PSSC PADC Type rw rw rw rw rw rw rw rw F9H IPH1 Reset: 00 HInterrupt Priority 1 High Register Bit Field PCCIP PCCIP PCCIP PCCIP PXMH PX2H PSSC H PADC H Type rw rw rw rw rw rw rw rw Table 5 MDU Register Overview A d d r R e g i s t e r N a m e B i t 76543210 RMAP = 1 H MDUSTAT Reset: 00 HMDU Status Register Bit Field 0 BSY IERR IRDY Type r rh rwh rwh B1H MDUCON Reset: 00 HMDU Control Register Bit Field IE IR RSEL STAR T OPCODE Type rw rw rw rwh rw B2H MD0 Reset: 00 HMDU Operand Register 0 Bit Field DATA Type rw B2H MR0 Reset: 00 HMDU Result Register 0 Bit Field DATA Type rh Table 4 CPU Register Overview (cont’d) A d d r R e g i s t e r N a m e B i t 76543210

Data Sheet 30 V1.1, 2010-08

3.2.4.3 CORDIC Registers

The CORDIC SFRs can be accessed in the mapped memory area (RMAP = 1). B3H MD1 Reset: 00 HMDU Operand Register 1 Bit Field DATA Type rw B3H MR1 Reset: 00 HMDU Result Register 1 Bit Field DATA Type rh B4H MD2 Reset: 00 HMDU Operand Register 2 Bit Field DATA Type rw B4H MR2 Reset: 00 HMDU Result Register 2 Bit Field DATA Type rh B5H MD3 Reset: 00 HMDU Operand Register 3 Bit Field DATA Type rw B5H MR3 Reset: 00 HMDU Result Register 3 Bit Field DATA Type rh B6H MD4 Reset: 00 HMDU Operand Register 4 Bit Field DATA Type rw B6H MR4 Reset: 00 HMDU Result Register 4 Bit Field DATA Type rh B7H MD5 Reset: 00 HMDU Operand Register 5 Bit Field DATA Type rw B7H MR5 Reset: 00 HMDU Result Register 5 Bit Field DATA Type rh Table 6 CORDIC Register Overview A d d r R e g i s t e r N a m e B i t 76543210 RMAP = 1 9AH CD_CORDXL Reset: 00 HCORDIC X Data Low Byte Bit Field DATAL Type rw 9BH CD_CORDXH Reset: 00 HCORDIC X Data High Byte Bit Field DATAH Type rw 9CH CD_CORDYL Reset: 00 HCORDIC Y Data Low Byte Bit Field DATAL Type rw 9DH CD_CORDYH Reset: 00 HCORDIC Y Data High Byte Bit Field DATAH Type rw 9EH CD_CORDZL Reset: 00 HCORDIC Z Data Low Byte Bit Field DATAL Type rw Table 5 MDU Register Overview (cont’d) A d d r R e g i s t e r N a m e B i t 76543210

Data Sheet 31 V1.1, 2010-08

3.2.4.4 System Control Registers

The system control SFRs can be accessed in the mapped memory area (RMAP = 0). 9FH CD_CORDZH Reset: 00 HCORDIC Z Data High Byte Bit Field DATAH Type rw A0H CD_STATC Reset: 00 HCORDIC Status and Data Control Register Bit Field KEEP Z KEEP Y KEEP X DMAP INT_E N EOC ERRO R BSY Type rw rw rw rw rw rwh rh rh A1H CD_CON Reset: 00 HCORDIC Control Register Bit Field MPS X_USI GN ST_M ODE ROTV EC MODE ST Type rw rw rw rw rw rwh Table 7 SCU Register Overview A d d r R e g i s t e r N a m e B i t 76543210 RMAP = 0 or 1 8FH SYSCON0 Reset: 04 HSystem Control Register 0 Bit Field 0 IMOD E 0 1 0 RMAP Type r rw r r r rw RMAP = 0 BFH SCU_PAGE Reset: 00 HPage Register Bit Field OP STNR 0 PAGE Type w w r rw RMAP = 0, PAGE 0 B3H MODPISEL Reset: 00 HPeripheral Input Select Register Bit Field 0 URRIS H JTAGT DIS JTAGT CKS EXINT 2IS EXINT 1IS EXINT 0IS URRIS T y p e r r wr wr wr wr wr wr w B4H IRCON0 Reset: 00 HInterrupt Request Register 0 Bit Field 0 EXINT EXINT EXINT EXINT EXINT EXINT EXINT Type r rwh rwh rwh rwh rwh rwh rwh B5H IRCON1 Reset: 00 HInterrupt Request Register 1 Bit Field 0 CANS RC2 CANS RC1 ADCS ADCS RIR TIR EIR Type r rwh rwh rwh rwh rwh rwh rwh B6H IRCON2 Reset: 00 HInterrupt Request Register 2 Bit Field 0 CANS RC3

0 CANS

B7H EXICON0 Reset: F0 HExternal Interrupt Control Register 0 Bit Field EXINT3 EXINT2 EXINT1 EXINT0 Type rw rw rw rw BAH EXICON1 Reset: 3F HExternal Interrupt Control Register 1 Bit Field 0 EXINT6 EXINT5 EXINT4 Type r rw rw rw BBH NMICON Reset: 00 HNMI Control Register Bit Field 0 NMI ECC NMI VDDP NMI VDD NMI OCDS NMI FLASH NMI PLL NMI WDT T y p e r r wr wr wr wr wr wr w Table 6 CORDIC Register Overview (cont’d) A d d r R e g i s t e r N a m e B i t 76543210

Data Sheet 32 V1.1, 2010-08 BCH NMISR Reset: 00 HNMI Status Register Bit Field 0 FNMI ECC FNMI VDDP FNMI VDD FNMI OCDS FNMI FLASH FNMI PLL FNMI WDT Type r rwh rwh rwh rwh rwh rwh rwh BDH BCON Reset: 00 HBaud Rate Control Register Bit Field BGSEL 0 BRDIS BRPRE R Type rw r rw rw rw BEH BG Reset: 00 HBaud Rate Timer/Reload Register Bit Field BR_VALUE Type rwh E9H FDCON Reset: 00 HFractional Divider Control Register Bit Field BGS SYNE N ERRS YN EOFS YN BRK NDOV FDM FDEN Type rw rw rwh rwh rwh rwh rw rw EAH FDSTEP Reset: 00 HFractional Divider Reload Register Bit Field STEP Type rw EBH FDRES Reset: 00 HFractional Divider Result Register Bit Field RESULT Type rh RMAP = 0, PAGE 1 B3H ID Reset: UU HIdentity Register Bit Field PRODID VERID Type r r B4H PMCON0 Reset: 00 HPower Mode Control Register 0 Bit Field 0 WDT RST WKRS WK SEL SD PD WS Type r rwh rwh rw rw rwh rw B5H PMCON1 Reset: 00 HPower Mode Control Register 1 Bit Field 0 CDC_ DIS CAN_ DIS MDU_ DIS T2_ DIS CCU_ DIS SSC_ DIS ADC_ DIS T y p e r r wr wr wr wr wr wr w B6H OSC_CON Reset: 08 HOSC Control Register Bit Field 0 OSC PD XPD OSC SS ORD RES OSCR T y p e r r wr wr w r w h r h B7H PLL_CON Reset: 90 HPLL Control Register Bit Field NDIV VCO BYP OSC DISC RESL D LOCK Type rw rw rw rwh rh BAH CMCON Reset: 10 HClock Control Register Bit Field VCO SEL KDIV 0 FCCF G CLKREL Type rw rw r rw rw BBH PASSWD Reset: 07 HPassword Register Bit Field PASS PROT ECT_S MODE Type wh rh rw BCH FEAL Reset: 00 HFlash Error Address Register Low Bit Field ECCERRADDR Type rh BDH FEAH Reset: 00 HFlash Error Address Register High Bit Field ECCERRADDR Type rh Table 7 SCU Register Overview (cont’d) A d d r R e g i s t e r N a m e B i t 76543210

Data Sheet 33 V1.1, 2010-08

3.2.4.5 WDT Registers

The WDT SFRs can be accessed in the mapped memory area (RMAP = 1). BEH COCON Reset: 00 HClock Output Control Register Bit Field 0 TLEN COUT S COREL Type r rw rw rw E9H MISC_CON Reset: 00 HMiscellaneous Control Register Bit Field 0 DFLAS HEN Type r rwh RMAP = 0, PAGE 3 B3H XADDRH Reset: F0 HOn-chip XRAM Address Higher Order Bit Field ADDRH Type rw B4H IRCON3 Reset: 00 HInterrupt Request Register 3 Bit Field 0 CANS RC5 CCU6 SR1 B5H IRCON4 Reset: 00 HInterrupt Request Register 4 Bit Field 0 CANS RC7 CCU6 SR3 B7H MODPISEL1 Reset: 00 HPeripheral Input Select Register Bit Field EXINT 6IS

0 UR1RIS T21EX

BAH MODPISEL2 Reset: 00 HPeripheral Input Select Register Bit Field 0 T21IS T2IS T1IS T0IS T y p e r r wr wr wr w BBH PMCON2 Reset: 00 HPower Mode Control Register 2 Bit Field 0 UART 1_DIS T21_D IS Type r rw rw BDH MODSUSP Reset: 01 HModule Suspend Control Register Bit Field 0 T21SU SP T2SUS P T13SU SP T12SU SP WDTS USP T y p e r r wr wr wr wr w Table 8 WDT Register Overview A d d r R e g i s t e r N a m e B i t 76543210 RMAP = 1 BBH WDTCON Reset: 00 HWatchdog Timer Control Register Bit Field 0 WINB EN WDTP R

0 WDTE

N WDTR S WDTI N Type r rw rh r rw rwh rw BCH WDTREL Reset: 00 HWatchdog Timer Reload Register Bit Field WDTREL Type rw BDH WDTWINB Reset: 00 HWatchdog Window-Boundary Count Register Bit Field WDTWINB Type rw Table 7 SCU Register Overview (cont’d) A d d r R e g i s t e r N a m e B i t 76543210

Data Sheet 34 V1.1, 2010-08

3.2.4.6 Port Registers

The Port SFRs can be accessed in the standard memory area (RMAP = 0). BEH WDTL Reset: 00 HWatchdog Timer Register Low Bit Field WDT Type rh BFH WDTH Reset: 00 HWatchdog Timer Register High Bit Field WDT Type rh Table 9 Port Register Overview A d d r R e g i s t e r N a m e B i t 76543210 RMAP = 0 H PORT_PAGE Reset: 00 HPage Register Bit Field OP STNR 0 PAGE Type w w r rw RMAP = 0, PAGE 0 80H P0_DATA Reset: 00 HP0 Data Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw 86H P0_DIR Reset: 00 HP0 Direction Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw 90H P1_DATA Reset: 00 HP1 Data Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw 91H P1_DIR Reset: 00 HP1 Direction Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw 92H P5_DATA Reset: 00 HP5 Data Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw 93H P5_DIR Reset: 00 HP5 Direction Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw A0H P2_DATA Reset: 00 HP2 Data Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw A1H P2_DIR Reset: 00 HP2 Direction Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw B0H P3_DATA Reset: 00 HP3 Data Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw B1H P3_DIR Reset: 00 HP3 Direction Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw C8H P4_DATA Reset: 00 HP4 Data Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw C9H P4_DIR Reset: 00 HP4 Direction Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw Table 8 WDT Register Overview (cont’d) A d d r R e g i s t e r N a m e B i t 76543210

Data Sheet 35 V1.1, 2010-08 RMAP = 0, PAGE 1 80H P0_PUDSEL Reset: FF HP0 Pull-Up/Pull-Down Select Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw 86H P0_PUDEN Reset: C4 HP0 Pull-Up/Pull-Down Enable Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw 90H P1_PUDSEL Reset: FF HP1 Pull-Up/Pull-Down Select Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw 91H P1_PUDEN Reset: FF HP1 Pull-Up/Pull-Down Enable Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw 92H P5_PUDSEL Reset: FF HP5 Pull-Up/Pull-Down Select Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw 93H P5_PUDEN Reset: FF HP5 Pull-Up/Pull-Down Enable Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw A0H P2_PUDSEL Reset: FF HP2 Pull-Up/Pull-Down Select Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw A1H P2_PUDEN Reset: 00 HP2 Pull-Up/Pull-Down Enable Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw B0H P3_PUDSEL Reset: BF HP3 Pull-Up/Pull-Down Select Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw B1H P3_PUDEN Reset: 40 HP3 Pull-Up/Pull-Down Enable Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw C8H P4_PUDSEL Reset: FF HP4 Pull-Up/Pull-Down Select Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw C9H P4_PUDEN Reset: 04 HP4 Pull-Up/Pull-Down Enable Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw RMAP = 0, PAGE 2 80H P0_ALTSEL0 Reset: 00 HP0 Alternate Select 0 Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw 86H P0_ALTSEL1 Reset: 00 HP0 Alternate Select 1 Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw 90H P1_ALTSEL0 Reset: 00 HP1 Alternate Select 0 Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw 91H P1_ALTSEL1 Reset: 00 HP1 Alternate Select 1 Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw 92H P5_ALTSEL0 Reset: 00 HP5 Alternate Select 0 Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw Table 9 Port Register Overview (cont’d) A d d r R e g i s t e r N a m e B i t 76543210

Data Sheet 36 V1.1, 2010-08

3.2.4.7 ADC Registers

The ADC SFRs can be accessed in the standard memory area (RMAP = 0). 93H P5_ALTSEL1 Reset: 00 HP5 Alternate Select 1 Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw B0H P3_ALTSEL0 Reset: 00 HP3 Alternate Select 0 Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw B1H P3_ALTSEL1 Reset: 00 HP3 Alternate Select 1 Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw C8H P4_ALTSEL0 Reset: 00 HP4 Alternate Select 0 Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw C9H P4_ALTSEL1 Reset: 00 HP4 Alternate Select 1 Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw RMAP = 0, PAGE 3 80H P0_OD Reset: 00 HP0 Open Drain Control Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw 90H P1_OD Reset: 00 HP1 Open Drain Control Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw 92H P5_OD Reset: 00 HP5 Open Drain Control Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw B0H P3_OD Reset: 00 HP3 Open Drain Control Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw C8H P4_OD Reset: 00 HP4 Open Drain Control Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw Table 10 ADC Register Overview Addr Register Name Bit 7 6 5 4 3 2 1 0 RMAP = 0 H ADC_PAGE Reset: 00 HPage Register Bit Field OP STNR 0 PAGE Type w w r rw RMAP = 0, PAGE 0 CA H ADC_GLOBCTR Reset: 30 HGlobal Control Register Bit Field ANON DW CTC 0 Type rw rw rw r CBH ADC_GLOBSTR Reset: 00 HGlobal Status Register Bit Field 0 CHNR 0 SAMP LE BUSY Type r rh r rh rh CCH ADC_PRAR Reset: 00 HPriority and Arbitration Register Bit Field ASEN ASEN

0 ARBM CSM1 PRIO1 CSM0 PRIO0

Type rw rw r rw rw rw rw rw Table 9 Port Register Overview (cont’d) A d d r R e g i s t e r N a m e B i t 76543210

Data Sheet 37 V1.1, 2010-08 CDH ADC_LCBR Reset: B7 HLimit Check Boundary Register Bit Field BOUND1 BOUND0 Type rw rw CEH ADC_INPCR0 Reset: 00 HInput Class 0 Register Bit Field STC Type rw CFH ADC_ETRCR Reset: 00 HExternal Trigger Control Register Bit Field SYNE SYNE ETRSEL1 ETRSEL0 Type rw rw rw rw RMAP = 0, PAGE 1 CAH ADC_CHCTR0 Reset: 00 HChannel Control Register 0 Bit Field 0 LCC 0 RESRSEL Type r rw r rw CBH ADC_CHCTR1 Reset: 00 HChannel Control Register 1 Bit Field 0 LCC 0 RESRSEL Type r rw r rw CCH ADC_CHCTR2 Reset: 00 HChannel Control Register 2 Bit Field 0 LCC 0 RESRSEL Type r rw r rw CDH ADC_CHCTR3 Reset: 00 HChannel Control Register 3 Bit Field 0 LCC 0 RESRSEL Type r rw r rw CEH ADC_CHCTR4 Reset: 00 HChannel Control Register 4 Bit Field 0 LCC 0 RESRSEL Type r rw r rw CFH ADC_CHCTR5 Reset: 00 HChannel Control Register 5 Bit Field 0 LCC 0 RESRSEL Type r rw r rw D2H ADC_CHCTR6 Reset: 00 HChannel Control Register 6 Bit Field 0 LCC 0 RESRSEL Type r rw r rw D3H ADC_CHCTR7 Reset: 00 HChannel Control Register 7 Bit Field 0 LCC 0 RESRSEL Type r rw r rw RMAP = 0, PAGE 2 CA H ADC_RESR0L Reset: 00 HResult Register 0 Low Bit Field RESULT 0 VF DRC CHNR Type rh r rh rh rh CBH ADC_RESR0H Reset: 00 HResult Register 0 High Bit Field RESULT Type rh CCH ADC_RESR1L Reset: 00 HResult Register 1 Low Bit Field RESULT 0 VF DRC CHNR Type rh r rh rh rh CDH ADC_RESR1H Reset: 00 HResult Register 1 High Bit Field RESULT Type rh CEH ADC_RESR2L Reset: 00 HResult Register 2 Low Bit Field RESULT 0 VF DRC CHNR Type rh r rh rh rh CFH ADC_RESR2H Reset: 00 HResult Register 2 High Bit Field RESULT Type rh D2H ADC_RESR3L Reset: 00 HResult Register 3 Low Bit Field RESULT 0 VF DRC CHNR Type rh r rh rh rh Table 10 ADC Register Overview (cont’d) Addr Register Name Bit 7 6 5 4 3 2 1 0

Data Sheet 38 V1.1, 2010-08 D3H ADC_RESR3H Reset: 00 HResult Register 3 High Bit Field RESULT Type rh RMAP = 0, PAGE 3 CA H ADC_RESRA0L Reset: 00 HResult Register 0, View A Low Bit Field RESULT VF DRC CHNR Type rh rh rh rh CBH ADC_RESRA0H Reset: 00 HResult Register 0, View A High Bit Field RESULT Type rh CCH ADC_RESRA1L Reset: 00 HResult Register 1, View A Low Bit Field RESULT VF DRC CHNR Type rh rh rh rh CDH ADC_RESRA1H Reset: 00 HResult Register 1, View A High Bit Field RESULT Type rh CEH ADC_RESRA2L Reset: 00 HResult Register 2, View A Low Bit Field RESULT VF DRC CHNR Type rh rh rh rh CFH ADC_RESRA2H Reset: 00 HResult Register 2, View A High Bit Field RESULT Type rh D2H ADC_RESRA3L Reset: 00 HResult Register 3, View A Low Bit Field RESULT VF DRC CHNR Type rh rh rh rh D3H ADC_RESRA3H Reset: 00 HResult Register 3, View A High Bit Field RESULT Type rh RMAP = 0, PAGE 4 CAH ADC_RCR0 Reset: 00 HResult Control Register 0 Bit Field VFCT R WFR 0 IEN 0 DRCT R Type rw rw r rw r rw CBH ADC_RCR1 Reset: 00 HResult Control Register 1 Bit Field VFCT R WFR 0 IEN 0 DRCT R Type rw rw r rw r rw CCH ADC_RCR2 Reset: 00 HResult Control Register 2 Bit Field VFCT R WFR 0 IEN 0 DRCT R Type rw rw r rw r rw CDH ADC_RCR3 Reset: 00 HResult Control Register 3 Bit Field VFCT R WFR 0 IEN 0 DRCT R Type rw rw r rw r rw CEH ADC_VFCR Reset: 00 HValid Flag Clear Register Bit Field 0 VFC3 VFC2 VFC1 VFC0 T y p e r wwww RMAP = 0, PAGE 5 CAH ADC_CHINFR Reset: 00 HChannel Interrupt Flag Register Bit Field CHINF CHINF CHINF CHINF CHINF CHINF CHINF CHINF Type rh rh rh rh rh rh rh rh CBH ADC_CHINCR Reset: 00 HChannel Interrupt Clear Register Bit Field CHINC CHINC CHINC CHINC CHINC CHINC CHINC CHINC T y p ewwwwwwww Table 10 ADC Register Overview (cont’d) Addr Register Name Bit 7 6 5 4 3 2 1 0

Data Sheet 39 V1.1, 2010-08 CCH ADC_CHINSR Reset: 00 HChannel Interrupt Set Register Bit Field CHINS CHINS CHINS CHINS CHINS CHINS CHINS CHINS T y p ewwwwwwww CDH ADC_CHINPR Reset: 00 HChannel Interrupt Node Pointer Register Bit Field CHINP CHINP CHINP CHINP CHINP CHINP CHINP CHINP Type rw rw rw rw rw rw rw rw CEH ADC_EVINFR Reset: 00 HEvent Interrupt Flag Register Bit Field EVINF EVINF EVINF EVINF

0 EVINF

CFH ADC_EVINCR Reset: 00 HEvent Interrupt Clear Flag Register Bit Field EVINC EVINC EVINC EVINC

0 EVINC

D2H ADC_EVINSR Reset: 00 HEvent Interrupt Set Flag Register Bit Field EVINS EVINS EVINS EVINS

0 EVINS

D3H ADC_EVINPR Reset: 00 HEvent Interrupt Node Pointer Register Bit Field EVINP EVINP EVINP EVINP

0 EVINP

RMAP = 0, PAGE 6 CAH ADC_CRCR1 Reset: 00 HConversion Request Control Register 1 Bit Field CH7 CH6 CH5 CH4 0 Type rwh rwh rwh rwh r CBH ADC_CRPR1 Reset: 00 HConversion Request Pending Register 1 Bit Field CHP7 CHP6 CHP5 CHP4 0 Type rwh rwh rwh rwh r CCH ADC_CRMR1 Reset: 00 HConversion Request Mode Register 1 Bit Field Rsv LDEV CLRP ND SCAN ENSI ENTR 0 ENGT T y p e r w w r wr wr w r r w CDH ADC_QMR0 Reset: 00 HQueue Mode Register 0 Bit Field CEV TREV FLUS H CLRV 0 ENTR 0 ENGT T y p ewwww rr wrr w CEH ADC_QSR0 Reset: 20 HQueue Status Register 0 Bit Field Rsv 0 EMPT Y EV 0 FILL Type r r rh rh r rh CFH ADC_Q0R0 Reset: 00 HQueue 0 Register 0 Bit Field EXTR ENSI RF V 0 REQCHNR Type rh rh rh rh r rh D2H ADC_QBUR0 Reset: 00 HQueue Backup Register 0 Bit Field EXTR ENSI RF V 0 REQCHNR Type rh rh rh rh r rh D2H ADC_QINR0 Reset: 00 HQueue Input Register 0 Bit Field EXTR ENSI RF 0 REQCHNR Type w w w r w Table 10 ADC Register Overview (cont’d) Addr Register Name Bit 7 6 5 4 3 2 1 0

Data Sheet 40 V1.1, 2010-08

3.2.4.8 Timer 2 Registers

The Timer 2 SFRs can be accessed in the standard memory area (RMAP = 0).

3.2.4.9 Timer 21 Registers

The Timer 21 SFRs can be accessed in the mapped memory area (RMAP = 1). Table 11 T2 Register Overview A d d r R e g i s t e r N a m e B i t 76543210 RMAP = 0 C0H T2_T2CON Reset: 00 HTimer 2 Control Register Bit Field TF2 EXF2 0 EXEN TR2 C/T2 CP/ RL2 Type rwh rwh r rw rwh rw rw C1H T2_T2MOD Reset: 00 HTimer 2 Mode Register Bit Field T2RE GS T2RH EN EDGE SEL PREN T2PRE DCEN Type rw rw rw rw rw rw rw rw C2H T2_RC2L Reset: 00 HTimer 2 Reload/Capture Register Low Bit Field RC2 Type rwh C3H T2_RC2H Reset: 00 HTimer 2 Reload/Capture Register High Bit Field RC2 Type rwh C4H T2_T2L Reset: 00 HTimer 2 Register Low Bit Field THL2 Type rwh C5H T2_T2H Reset: 00 HTimer 2 Register High Bit Field THL2 Type rwh Table 12 T21 Register Overview A d d r R e g i s t e r N a m e B i t 76543210 RMAP = 1 C0H T21_T2CON Reset: 00 HTimer 2 Control Register Bit Field TF2 EXF2 0 EXEN TR2 C/T2 CP/ RL2 Type rwh rwh r rw rwh rw rw C1H T21_T2MOD Reset: 00 HTimer 2 Mode Register Bit Field T2RE GS T2RH EN EDGE SEL PREN T2PRE DCEN Type rw rw rw rw rw rw rw rw C2H T21_RC2L Reset: 00 HTimer 2 Reload/Capture Register Low Bit Field RC2 Type rwh C3H T21_RC2H Reset: 00 HTimer 2 Reload/Capture Register High Bit Field RC2 Type rwh C4H T21_T2L Reset: 00 HTimer 2 Register Low Bit Field THL2 Type rwh

Data Sheet 41 V1.1, 2010-08

3.2.4.10 CCU6 Registers

The CCU6 SFRs can be accessed in the standard memory area (RMAP = 0). C5H T21_T2H Reset: 00 HTimer 2 Register High Bit Field THL2 Type rwh Table 13 CCU6 Register Overview A d d r R e g i s t e r N a m e B i t 76543210 RMAP = 0 A3H CCU6_PAGE Reset: 00 HPage Register Bit Field OP STNR 0 PAGE Type w w r rw RMAP = 0, PAGE 0 H CCU6_CC63SRL Reset: 00 HCapture/Compare Shadow Register for Channel CC63 Low Bit Field CC63SL Type rw 9BH CCU6_CC63SRH Reset: 00 HCapture/Compare Shadow Register for Channel CC63 High Bit Field CC63SH Type rw 9CH CCU6_TCTR4L Reset: 00 HTimer Control Register 4 Low Bit Field T12 STD T12 STR 0 DT RES T12 RES T12R S T12R R T y p e ww r wwww 9DH CCU6_TCTR4H Reset: 00 HTimer Control Register 4 High Bit Field T13 STD T13 STR

0 T13

S T13R R T y p e ww r www 9EH CCU6_MCMOUTSL Reset: 00 HMulti-Channel Mode Output Shadow Register Low Bit Field STRM CM

0 MCMPS

9FH CCU6_MCMOUTSH Reset: 00 HMulti-Channel Mode Output Shadow Register High Bit Field STRH P

0 CURHS EXPHS

A4H CCU6_ISRL Reset: 00 HCapture/Compare Interrupt Status Reset Register Low Bit Field RT12 PM RT12 OM RCC6 RCC6 RCC6 RCC6 RCC6 RCC6 T y p e wwwwwwww A5H CCU6_ISRH Reset: 00 HCapture/Compare Interrupt Status Reset Register High Bit Field RSTR RIDLE RWH E RCHE 0 RTRP F RT13 PM RT13 CM T y p e wwww r www A6H CCU6_CMPMODIFL Reset: 00 HCompare State Modification Register Low Bit Field 0 MCC6

0 MCC6

A7H CCU6_CMPMODIFH Reset: 00 HCompare State Modification Register High Bit Field 0 MCC6 Table 12 T21 Register Overview (cont’d) A d d r R e g i s t e r N a m e B i t 76543210

Data Sheet 42 V1.1, 2010-08 FAH CCU6_CC60SRL Reset: 00 HCapture/Compare Shadow Register for Channel CC60 Low Bit Field CC60SL Type rwh FBH CCU6_CC60SRH Reset: 00 HCapture/Compare Shadow Register for Channel CC60 High Bit Field CC60SH Type rwh FCH CCU6_CC61SRL Reset: 00 HCapture/Compare Shadow Register for Channel CC61 Low Bit Field CC61SL Type rwh FDH CCU6_CC61SRH Reset: 00 HCapture/Compare Shadow Register for Channel CC61 High Bit Field CC61SH Type rwh FEH CCU6_CC62SRL Reset: 00 HCapture/Compare Shadow Register for Channel CC62 Low Bit Field CC62SL Type rwh FFH CCU6_CC62SRH Reset: 00 HCapture/Compare Shadow Register for Channel CC62 High Bit Field CC62SH Type rwh RMAP = 0, PAGE 1 9AH CCU6_CC63RL Reset: 00 HCapture/Compare Register for Channel CC63 Low Bit Field CC63VL Type rh 9BH CCU6_CC63RH Reset: 00 HCapture/Compare Register for Channel CC63 High Bit Field CC63VH Type rh 9CH CCU6_T12PRL Reset: 00 HTimer T12 Period Register Low Bit Field T12PVL Type rwh 9DH CCU6_T12PRH Reset: 00 HTimer T12 Period Register High Bit Field T12PVH Type rwh 9EH CCU6_T13PRL Reset: 00 HTimer T13 Period Register Low Bit Field T13PVL Type rwh 9FH CCU6_T13PRH Reset: 00 HTimer T13 Period Register High Bit Field T13PVH Type rwh A4H CCU6_T12DTCL Reset: 00 HDead-Time Control Register for Timer T12 Low Bit Field DTM Type rw A5H CCU6_T12DTCH Reset: 00 HDead-Time Control Register for Timer T12 High Bit Field 0 DTR2 DTR1 DTR0 0 DTE2 DTE1 DTE0 T y p e r r hr hr h r r w r w r w A6H CCU6_TCTR0L Reset: 00 HTimer Control Register 0 Low Bit Field CTM CDIR STE1 T12R T12 PRE T12CLK Type rw rh rh rh rw rw A7H CCU6_TCTR0H Reset: 00 HTimer Control Register 0 High Bit Field 0 STE1 T13R T13 PRE T13CLK Type r rh rh rw rw FAH CCU6_CC60RL Reset: 00 HCapture/Compare Register for Channel CC60 Low Bit Field CC60VL Type rh Table 13 CCU6 Register Overview (cont’d) A d d r R e g i s t e r N a m e B i t 76543210

Data Sheet 43 V1.1, 2010-08 FBH CCU6_CC60RH Reset: 00 HCapture/Compare Register for Channel CC60 High Bit Field CC60VH Type rh FCH CCU6_CC61RL Reset: 00 HCapture/Compare Register for Channel CC61 Low Bit Field CC61VL Type rh FDH CCU6_CC61RH Reset: 00 HCapture/Compare Register for Channel CC61 High Bit Field CC61VH Type rh FEH CCU6_CC62RL Reset: 00 HCapture/Compare Register for Channel CC62 Low Bit Field CC62VL Type rh FFH CCU6_CC62RH Reset: 00 HCapture/Compare Register for Channel CC62 High Bit Field CC62VH Type rh RMAP = 0, PAGE 2 9AH CCU6_T12MSELL Reset: 00 HT12 Capture/Compare Mode Select Register Low Bit Field MSEL61 MSEL60 Type rw rw 9BH CCU6_T12MSELH Reset: 00 HT12 Capture/Compare Mode Select Register High Bit Field DBYP HSYNC MSEL62 Type rw rw rw 9CH CCU6_IENL Reset: 00 HCapture/Compare Interrupt Enable Register Low Bit Field ENT1 PM ENT1 OM ENCC 62F ENCC 62R ENCC 61F ENCC 61R ENCC 60F ENCC 60R Type rw rw rw rw rw rw rw rw 9DH CCU6_IENH Reset: 00 HCapture/Compare Interrupt Enable Register High Bit Field EN STR EN IDLE EN WHE EN CHE 0 EN TRPF ENT1 3PM ENT1 3CM Type rw rw rw rw r rw rw rw 9EH CCU6_INPL Reset: 40 HCapture/Compare Interrupt Node Pointer Register Low Bit Field INPCHE INPCC62 INPCC61 INPCC60 Type rw rw rw rw 9FH CCU6_INPH Reset: 39 HCapture/Compare Interrupt Node Pointer Register High Bit Field 0 INPT13 INPT12 INPERR T y p e r r wr wr w A4H CCU6_ISSL Reset: 00 HCapture/Compare Interrupt Status Set Register Low Bit Field ST12 PM ST12 OM SCC6 SCC6 SCC6 SCC6 SCC6 SCC6 T y p e wwwwwwww A5H CCU6_ISSH Reset: 00 HCapture/Compare Interrupt Status Set Register High Bit Field SSTR SIDLE SWHE SCHE SWH C STRP F ST13 PM ST13 CM T y p e wwwwwwww A6H CCU6_PSLR Reset: 00 HPassive State Level Register Bit Field PSL63 0 PSL Type rwh r rwh A7H CCU6_MCMCTR Reset: 00 HMulti-Channel Mode Control Register Bit Field 0 SWSYN 0 SWSEL Type r rw r rw FAH CCU6_TCTR2L Reset: 00 HTimer Control Register 2 Low Bit Field 0 T13TED T13TEC T13 SSC T12 SSC Type r rw rw rw rw Table 13 CCU6 Register Overview (cont’d) A d d r R e g i s t e r N a m e B i t 76543210

Data Sheet 44 V1.1, 2010-08 FBH CCU6_TCTR2H Reset: 00 HTimer Control Register 2 High Bit Field 0 T13RSEL T12RSEL Type r rw rw FCH CCU6_MODCTRL Reset: 00 HModulation Control Register Low Bit Field MCM EN

0 T12MODEN

FDH CCU6_MODCTRH Reset: 00 HModulation Control Register High Bit Field ECT1

0 T13MODEN

FEH CCU6_TRPCTRL Reset: 00 HTrap Control Register Low Bit Field 0 TRPM TRPM TRPM Type r rw rw rw FFH CCU6_TRPCTRH Reset: 00 HTrap Control Register High Bit Field TRPP EN TRPE N13 TRPEN Type rw rw rw RMAP = 0, PAGE 3 H CCU6_MCMOUTL Reset: 00 HMulti-Channel Mode Output Register Low Bit Field 0 R MCMP Type r rh rh 9BH CCU6_MCMOUTH Reset: 00 HMulti-Channel Mode Output Register High Bit Field 0 CURH EXPH Type r rh rh 9CH CCU6_ISL Reset: 00 HCapture/Compare Interrupt Status Register Low Bit Field T12 PM T12 OM ICC62 F ICC62 R ICC61 F ICC61 R ICC60 F ICC60 R Type rh rh rh rh rh rh rh rh 9DH CCU6_ISH Reset: 00 HCapture/Compare Interrupt Status Register High Bit Field STR IDLE WHE CHE TRPS TRPF T13 PM T13 CM Type rh rh rh rh rh rh rh rh 9EH CCU6_PISEL0L Reset: 00 HPort Input Select Register 0 Low Bit Field ISTRP ISCC62 ISCC61 ISCC60 Type rw rw rw rw 9FH CCU6_PISEL0H Reset: 00 HPort Input Select Register 0 High Bit Field IST12HR ISPOS2 ISPOS1 ISPOS0 Type rw rw rw rw A4H CCU6_PISEL2 Reset: 00 HPort Input Select Register 2 Bit Field 0 IST13HR Type r rw FAH CCU6_T12L Reset: 00 HTimer T12 Counter Register Low Bit Field T12CVL Type rwh FBH CCU6_T12H Reset: 00 HTimer T12 Counter Register High Bit Field T12CVH Type rwh FCH CCU6_T13L Reset: 00 HTimer T13 Counter Register Low Bit Field T13CVL Type rwh FDH CCU6_T13H Reset: 00 HTimer T13 Counter Register High Bit Field T13CVH Type rwh Table 13 CCU6 Register Overview (cont’d) A d d r R e g i s t e r N a m e B i t 76543210

Data Sheet 45 V1.1, 2010-08

3.2.4.11 UART1 Registers

The UART1 SFRs can be accessed in the mapped memory area (RMAP = 1). FEH CCU6_CMPSTATL Reset: 00 HCompare State Register Low Bit Field 0 CC63 ST CC POS2 CC POS1 CC POS0 CC62 ST CC61 ST CC60 ST T y p e r r hr hr hr hr hr hr h FFH CCU6_CMPSTATH Reset: 00 HCompare State Register High Bit Field T13IM COUT 63PS COUT 62PS CC62 PS COUT 61PS CC61 PS COUT 60PS CC60 PS Type rwh rwh rwh rwh rwh rwh rwh rwh Table 14 UART1 Register Overview A d d r R e g i s t e r N a m e B i t 76543210 RMAP = 1 C8H SCON Reset: 00 HSerial Channel Control Register Bit Field SM0 SM1 SM2 REN TB8 RB8 TI RI Type rw rw rw rw rw rwh rwh rwh C9H SBUF Reset: 00 HSerial Data Buffer Register Bit Field VAL Type rwh CAH BCON Reset: 00 HBaud Rate Control Register Bit Field 0 BRPRE R Type r rw rw CBH BG Reset: 00 HBaud Rate Timer/Reload Register Bit Field BR_VALUE Type rwh CCH FDCON Reset: 00 HFractional Divider Control Register Bit Field 0 NDOV FDM FDEN Type r rwh rw rw CDH FDSTEP Reset: 00 HFractional Divider Reload Register Bit Field STEP Type rw CEH FDRES Reset: 00 HFractional Divider Result Register Bit Field RESULT Type rh Table 13 CCU6 Register Overview (cont’d) A d d r R e g i s t e r N a m e B i t 76543210

Data Sheet 46 V1.1, 2010-08

3.2.4.12 SSC Registers

The SSC SFRs can be accessed in the standard memory area (RMAP = 0).

3.2.4.13 MultiCAN Registers

The MultiCAN SFRs can be accessed in the standard memory area (RMAP = 0). Table 15 SSC Register Overview A d d r R e g i s t e r N a m e B i t 76543210 RMAP = 0 A9H SSC_PISEL Reset: 00 HPort Input Select Register Bit Field 0 CIS SIS MIS Type r rw rw rw AAH SSC_CONL Reset: 00 HControl Register Low Programming Mode Bit Field LB PO PH HB BM Type rw rw rw rw rw AAH SSC_CONL Reset: 00 HControl Register Low Operating Mode Bit Field 0 BC Type r rh ABH SSC_CONH Reset: 00 HControl Register High Programming Mode Bit Field EN MS 0 AREN BEN PEN REN TEN T y p e r wr w r r wr wr wr wr w ABH SSC_CONH Reset: 00 HControl Register High Operating Mode Bit Field EN MS 0 BSY BE PE RE TE Type rw rw r rh rwh rwh rwh rwh ACH SSC_TBL Reset: 00 HTransmitter Buffer Register Low Bit Field TB_VALUE Type rw ADH SSC_RBL Reset: 00 HReceiver Buffer Register Low Bit Field RB_VALUE Type rh AEH SSC_BRL Reset: 00 HBaud Rate Timer Reload Register Low Bit Field BR_VALUE Type rw AFH SSC_BRH Reset: 00 HBaud Rate Timer Reload Register High Bit Field BR_VALUE Type rw Table 16 CAN Register Overview A d d r R e g i s t e r N a m e B i t 76543210 RMAP = 0 H ADCON Reset: 00 HCAN Address/Data Control Register Bit Field V3 V2 V1 V0 AUAD BSY RWEN Type rw rw rw rw rw rh rw D9H ADL Reset: 00 HCAN Address Register Low Bit Field CA9 CA8 CA7 CA6 CA5 CA4 CA3 CA2 Type rwh rwh rwh rwh rwh rwh rwh rwh DAH ADH Reset: 00 HCAN Address Register High Bit Field 0 CA13 CA12 CA11 CA10 Type r rwh rwh rwh rwh

Data Sheet 47 V1.1, 2010-08

3.2.4.14 OCDS Registers

The OCDS SFRs can be accessed in the mapped memory area (RMAP = 1). DBH DATA0 Reset: 00 HCAN Data Register 0 Bit Field CD Type rwh DCH DATA1 Reset: 00 HCAN Data Register 1 Bit Field CD Type rwh DDH DATA2 Reset: 00 HCAN Data Register 2 Bit Field CD Type rwh DEH DATA3 Reset: 00 HCAN Data Register 3 Bit Field CD Type rwh Table 17 OCDS Register Overview A d d r R e g i s t e r N a m e B i t 76543210 RMAP = 1 E9H MMCR2 Reset: 1U HMonitor Mode Control 2 Register Bit Field STMO DE EXBC DSUS P MBCO N ALTDI MMEP MMOD E JENA Type rw rw rw rwh rw rwh rh rh F1H MMCR Reset: 00 HMonitor Mode Control Register Bit Field MEXIT MEXIT 0 MSTE P MRAM S_P MRAM S TRF RRF Type w rwh r rw w rwh rh rh F2H MMSR Reset: 00 HMonitor Mode Status Register Bit Field MBCA M MBCIN EXBF SWBF HWB3 F HWB2 F HWB1 F HWB0 F Type rw rwh rwh rwh rwh rwh rwh rwh F3H MMBPCR Reset: 00 HBreakpoints Control Register Bit Field SWBC HWB3C HWB2C HWB1 C HWB0C Type rw rw rw rw rw F4H MMICR Reset: 00 HMonitor Mode Interrupt Control Register Bit Field DVEC T DRET R COMR ST MSTS EL MMUI E_P MMUI E RRIE_ P RRIE Type rwh rwh rwh rh w rw w rw F5H MMDR Reset: 00 HMonitor Mode Data Transfer Register Receive Bit Field MMRR Type rh F6H HWBPSR Reset: 00 HHardware Breakpoints Select Register Bit Field 0 BPSEL BPSEL Type r w rw F7H HWBPDR Reset: 00 HHardware Breakpoints Data Register Bit Field HWBPxx Type rw EBH MMWR1 Reset: 00 HMonitor Work Register 1 Bit Field MMWR1 Type rw Table 16 CAN Register Overview (cont’d) A d d r R e g i s t e r N a m e B i t 76543210

Data Sheet 48 V1.1, 2010-08 ECH MMWR2 Reset: 00 HMonitor Work Register 2 Bit Field MMWR2 Type rw Table 17 OCDS Register Overview (cont’d) A d d r R e g i s t e r N a m e B i t 76543210

Data Sheet 49 V1.1, 2010-08

3.3 Flash Memory

The Flash memory provides an embedded user-programm able non-volatile memory, allowing fast and reliable storage of user code and data. It is operated from a single 2.5 V supply from the Embedded Voltage Regu lator (EVR) and does not require additional programming or erasing volta ge. The sectorization of t he Flash memory allows each sector to be erased independently.

Features

• In-System Programming (ISP) via UART
• In-Application Programming (IAP)
• Error Correction Code (ECC) for dynamic correction of single-bit errors
• Background program a nd erase operations for CPU load minimization
• Support for aborti ng erase operation
• Minimum program width 1) of 32-byte for D-Flash and 64-byte for P-Flash
• 1-sector minimum erase width
• 1-byte read access
• Flash is deliver ed in erased state (read all zeros)
• Operating supply vo ltage: 2.5 V ± 7.5 %
• Read access time: 3 × tCCLK = 125 ns2)
• Program time: 248256 / fSYS = 2.6 ms3)
• Erase time: 9807360 / fSYS = 102 ms3) 1) P-Flash: 64-byte wordline can only be programmed once, i.e., one gate disturb allowed. D-Flash: 32-byte wordline can be programmed twice, i.e., two gate disturbs allowed. 2) Values shown here are typical values. fsys =9 6M H z±7 . 5 % (fCCLK = 24 MHz ± 7.5 %) is the maximum frequency range for Flash read access. 3) Values shown here are typical values. fsys = 96 MHz ± 7.5% is the only frequency range for Flash programming and erasing. fsysmin is used for obtaining the worst case timing.

Data Sheet 50 V1.1, 2010-08 Table 18 shows the Flash data retention and endurance targets.

3.3.1 Flash Bank Sectorization

The SAA-XC886 product family offers Flash devices with either 24 Kbytes or 32 Kbytes of embedded Flash me mory. Each Flash device consis ts of Program Flash (P-Flash) and Data Flash (D-Flash) bank(s) with different sectorization shown in Figure 10. Both types can be used for code and data storage. The label “Data” neither implies that the D-Flash is mapped to the data memory regi on, nor that it can only be used for data storage. It is used to distinguish the different Flash bank sectorizations. The 32-Kbyte Flash device cons ists of 6 P-Flash and 2 D- Flash banks, while the 24- Kbyte Flash device consists of also of 6 P-Flash banks but with the upper 2 banks only 2 Kbytes each, and only 1 D-Flash bank. The P-Flash banks are always grouped in pairs. As such, the P-Flash banks are also sometimes referred to as P-Flash bank pair. Each sect or in a P-Flash bank is grouped with the corresponding sector from the other bank within a bank pair to form a P-Flash bank pair sector. Table 18 Flash Data Retention and Endur ance (Operating Conditions apply) Retention Endurance 1) 1) One cycle refers to the programming of all wordlines in a sector and erasing of sector. The Flash endurance data specified in Table 18 is valid only if the following conditions are fulfilled: - the maximum number of erase cycles per Flash sector must not exceed 100,000 cycles. - the maximum number of erase cycles per Flash bank must not exceed 300,000 cycles. - the maximum number of program cycles per Flash bank must not exceed 2,500,000 cycles. Size Remarks TA = -40 to 125 °C TA = 125 to 140 °C Program Flash 20 years 1,000 cycles up to 32 Kbytes 2) If no Flash is used for data, the Program Flash size can be up to the maximum Flash size available in the device variant. Having more Data Flash will mean less Flash is available for Program Flash. for 32-Kbyte Variant 20 years 1,000 c ycles up to 24 Kbytes 2) for 24-Kbyte Variant Data Flash 20 years 1,000 cycles 3) For TA = 125 to 140°C, refers to programming of second 8 bytes (bytes 8 to 15) per WL.

4 Kbytes 1 Kbyte

5 years 10,000 cycles 3) 1 Kbyte 256 bytes 2 years 70,000 cycles 3) 512 bytes 128 bytes 2 years 100,000 cycles 3) 128 bytes 32 bytes

Data Sheet 51 V1.1, 2010-08 Figure 10 Flash Bank Sectorization The internal structure of each Flash bank represents a sect or architecture for flexible erase capability. The minimum erase width is always a complete sector, and sectors can be erased separately or in parallel. Contrary to st andard EPROMs, erased Flash memory cells contain 0s. The D-Flash bank is divided into more physical sectors fo r extended erasing and reprogramming capability; even numbers for each sector size are provided to allow greater flexibility and the ability to adapt to a wide range of application requirements.

3.3.2 Parallel Read Access of P-Flash

To enhance system performance, the P-Flash banks are configured for parallel read to allow two bytes of linear c ode to be read in 4 x CCLK cycles, compared to 6 x CCLK cycles if serial read is performed. This is achieved by reading two bytes in parallel from a P-Flash bank pair within the 3 x CCLK cycles access time and storing them in a cache. Subsequent read from the cache by the CPU does not require a wait state and can be completed within 1 x CCLK cycle. The result is the average instruction fetch time from the P-Flash banks is reduced and thus, the MIPS (Mega Instruction Per Second) of the system is increased. However, if the parallel read feature is not desired due to certain timing constraints, it can be disabled by calling the parallel read disable subroutine. Sector 9: 128-byte Sector 5: 256-byte Sector 3: 512-byte Sector 1: 1-Kbyte Sector 0: 1-Kbyte Sector 7: 128-byte Sector 8: 128-byte Sector 6: 128-byte Sector 4: 256-byte Sector 2: 512-byte Sector 0: 3.75-Kbyte P-Flash D-Flash Sector 2: 128-byte Sector 1: 128-byte

Data Sheet 52 V1.1, 2010-08

3.3.3 Flash Programming Width

For the P-Flash banks, a programmed wordlin e (WL) must be erased before it can be reprogrammed as the Flash cells can only withstand one gate disturb. This means that the entire sector cont aining the WL must be erased sinc e it is impossible to erase a single WL. For the D-Flash bank, the same WL can be programmed twice before erasing is required as the Flash cells are able to withstand two gate disturbs. This means if the number of data bytes that needs to be written is sm aller than the 32-byt e minimum programming width, the user can opt to program this nu mber of data bytes (x ; where x can be any integer from 1 to 31) first a nd program the remain ing bytes (32 - x) la ter. Hence, it is possible to program the same WL, for example, with 16 bytes of data two times (see Figure 11) Figure 11 D-Flash Programming Note: When programming a D-Fl ash WL the second time, the previously programmed Flash memory cells (whether 0s or 1s) should be reprogrammed with 0s to retain its original contents and to prevent “over-programming”. 0000 ….. 0000 H 0000 ….. 0000 H 32 bytes (1 WL) 1111 ….. 1111 H0000 ….. 0000 H 16 bytes 16 bytes 0000 ….. 0000 H 1111 ….. 1111 H Flash memory cells 32-byte write buffers 1111 ….. 0000 H 1111 ….. 1111 H 0000 ….. 0000 H1111 ….. 0000 H Program 1 Program 2 Note: A Flash memory cell can be programmed from 0 to 1, but not from 1 to 0.

Data Sheet 53 V1.1, 2010-08

3.4 Interrupt System

The XC800 Core supports one non-maskable interrupt (NMI) and 14 maskable interrupt requests. In addition to the standard interr upt functions supporte d by the core, e.g., configurable interrupt priori ty and interrupt masking, the SAA-XC886 interrupt system provides extended interrupt support capabilities such as the mapping of each interrupt vector to several interrupt sources to increase the number of interrupt sources supported, and additional stat us registers for detecting and determining the interrupt source.

3.4.1 Interrupt Source

Figure 12 to Figure 16 give a general overview of the interrupt sources and nodes, and their corresponding control and status flags. Figure 12 Non-Maskable In terrupt Request Sources 0073 H NMIWDT NMICON.0 WDT Overflow >=1 Non Maskable Interrupt NMIPLL NMICON.1 PLL Loss of Lock NMIFLASH Flash Operation Complete NMIVDD NMICON.4 VDD Pre-Warning FNMIWDT NMIISR.0 FNMIPLL NMIISR.1 FNMIFLASH NMIISR.2 FNMIVDD NMIISR.4 NMIVDDP NMICON.5 VDDP Pre-Warning FNMIVDDP NMIISR.5 NMIECC NMICON.6 Flash ECC Error FNMIECC NMIISR.6

Data Sheet 54 V1.1, 2010-08 Figure 13 Interrupt Request Sources (Part 1) Highest Lowest Priority Level Bit-addressable Request flag is cleared by hardware 000B HET0 IEN0.1 TF0 TCON.5 Timer 0 Overflow 001B HET1 IEN0.3 TF1 TCON.7 Timer 1 Overflow IP.1/ IPH.1 IP.3/ IPH.3

0023 HES

IEN0.4 IP.4/ IPH.4 >=1 RI SCON.0 TI SCON.1 UART Transmit

0003 HEX0

IEN0.0 IE0 TCON.1 IP.0/ IPH.0 0013 H IP.2/ IPH.2 IT0 TCON.0 EX1 IEN0.2 IE1 TCON.3 IT1 TCON.2 IEN0.7 EA P o l l i n g S e q u e n c e UART Receive EXINT0 EXICON0.0/1 EINT0 EXINT1 EXICON0.2/3 EINT1

Data Sheet 55 V1.1, 2010-08 Figure 14 Interrupt Request Sources (Part 2) Highest Lowest Priority Level Bit-addressable Request flag is cleared by hardware 002B H IP.5/ IPH.5 P o l l i n g S e q u e n c e

0033 HEADC

IEN1.0 IP1.0/ IPH1.0 >=1 ADCSR0 IRCON1.3 ADC_0 ADC_1 ADCSR1 IRCON1.4 CANSRC1 IRCON1.5 MultiCAN_1 ET2 IEN0.5 >=1 TF2 T2_T2CON.7 EXF2 T2_T2CON.6 Timer 2 Overflow EXEN2 T2_T2CON.3 CANSRC0 IRCON2.0 MultiCAN_0 NDOV FDCON.2 Normal Divider Overflow IEN0.7 EA CANSRC2 IRCON1.6 MultiCAN_2 T2EX EDGES EL T2_T2MOD.5 >=1 EOFSYN FDCON.4 End of Synch Byte ERRSYN FDCON.5 Synch Byte Error >=1 SYNEN

Data Sheet 56 V1.1, 2010-08 Figure 15 Interrupt Request Sources (Part 3) Highest Lowest Priority Level Bit-addressable Request flag is cleared by hardware P o l l i n g S e q u e n c e 003B HESSC IEN1.1 IP1.1/ IPH1.1 >=1TIR IRCON1.1 RIR IRCON1.2 EIR IRCON1.0 SSC_EIR SSC_TIR SSC_RIR IEN0.7 EA 0043 H IP1.2/ IPH1.2 EXINT2 EXICON0.4/5 EXINT2 IRCON0.2 EINT2 EX2 IEN1.2 IRDY MDUSTAT.0 MDU_0 MDU_1 IERR MDUSTAT.1 EOC CDSTATC.2 Cordic >=1 >=1 RI UART1_SCON.0 TI UART1_SCON.1 UART1 NDOV Normal Divider Overflow UART1_FDCON.2 TF2 T21_T2CON.7 EXF2 T21_T2CON.6 Timer 21 Overflow EXEN2 T21_T2CON.3 T21EX EDGES EL T21_T2MOD.5 >=1

Data Sheet 57 V1.1, 2010-08 Figure 16 Interrupt Request Sources (Part 4) IEN0.7 Highest Lowest Priority Level Bit-addressable Request flag is cleared by hardware P o l l i n g S e q u e n c e EA 004B HEXM IEN1.3 IP1.3/ IPH1.3 >=1 EXINT5 EXICON1.2/3 EXINT5 IRCON0.5 EINT5 EXINT3 EXICON1.0/1 EXINT4 IRCON0.4 EINT4 EXINT3 EXICON0.6/7 EXINT3 IRCON0.3 EINT3 EXINT6 EXICON1.4/5 EXINT6 IRCON0.6 EINT6 CANSRC3 IRCON2.4 MultiCAN_3

Data Sheet 58 V1.1, 2010-08 Figure 17 Interrupt Request Sources (Part 5) Highest Lowest Priority Level P o l l i n g S e q u e n c e IEN0.7 Bit-addressable Request flag is cleared by hardware EA 0053 H CCU6 interrupt node 0 IP1.4/ IPH1.4 005B H IP1.5/ IPH1.5 0063 H IP1.6/ IPH1.6 006B H IP1.7/ IPH1.7 ECCIP0 IEN1.4 ECCIP1 IEN1.5 ECCIP2 IEN1.6 ECCIP3 IEN1.7 CANSRC4 IRCON3.1 MultiCAN_4 >=1 CCU6 interrupt node 1 CANSRC5 IRCON3.5 MultiCAN_5 >=1 CCU6 interrupt node 2 CANSRC6 IRCON4.1 MutliCAN_6 >=1 CCU6 interrupt node 3 CANSRC7 IRCON4.5 MultiCAN_7 >=1 CCU6SR0 IRCON3.0 CCU6SR1 IRCON3.4 CCU6SR2 IRCON4.0 CCU6SRC3 IRCON4.4

Data Sheet 59 V1.1, 2010-08

3.4.2 Interrupt Source and Vector

Each interrupt event source has an associated interrupt vector address for the interrupt node it belongs to. This vector is accessed to service the corresponding interrupt node request. The interrupt service of each inte rrupt source can be in dividually enabled or disabled via an enable bit. The assignment of the SAA- XC886 interrupt sources to the interrupt vector a ddress and the corresponding inte rrupt node enable bits are summarized in Table 19. Table 19 Interrupt Vector Addresses Interrupt Source Vector Address Assignment for SAA- XC886 Enable Bit SFR NMI 0073 H Watchdog Timer NMI NMIWDT NMICON PLL NMI NMIPLL Flash NMI NMIFLASH VDDC Prewarning NMI NMIVDD VDDP Prewarning NMI NMIVDDP Flash ECC NMI NMIECC XINTR0 0003 H External Interrupt 0 EX0 IEN0 XINTR1 000B H Timer 0 ET0 XINTR2 0013 H External Interrupt 1 EX1 XINTR3 001B H Timer 1 ET1 XINTR4 0023 H UART ES XINTR5 002B H T2 ET2 UART Fractional Divider (Normal Divider Overflow) MultiCAN Node 0 LIN

Data Sheet 60 V1.1, 2010-08 XINTR6 0033 H MultiCAN Nodes 1 and 2 EADC IEN1 ADC[1:0] XINTR7 003B H SSC ESSC XINTR8 0043 H External Interrupt 2 EX2 T21 CORDIC UART1 UART1 Fractional Divider (Normal Divider Overflow) MDU[1:0] XINTR9 004B H External Interrupt 3 EXM External Interrupt 4 External Interrupt 5 External Interrupt 6 MultiCAN Node 3 XINTR10 0053 H CCU6 INP0 ECCIP0 MultiCAN Node 4 XINTR11 005B H CCU6 INP1 ECCIP1 MultiCAN Node 5 XINTR12 0063 H CCU6 INP2 ECCIP2 MultiCAN Node 6 XINTR13 006B H CCU6 INP3 ECCIP3 MultiCAN Node 7 Table 19 Interrupt Vector Addresses (cont’d) Interrupt Source Vector Address Assignment for SAA- XC886 Enable Bit SFR

Data Sheet 61 V1.1, 2010-08

3.4.3 Interrupt Priority

An interrupt that is currentl y being serviced can only be in terrupted by a higher-priority interrupt, but not by another interrupt of the same or lower priority. Hence, an interrupt of the highest priority cannot be interrupted by any other interrupt request. If two or more requests of different priority levels ar e received simultaneously, the request of the highest priority is serviced first. If requests of th e same prio rity are received simultaneously, then an internal polling sequence determines which request is serviced first. Thus, within ea ch priority level, there is a second priority structure determined by the polling sequence shown in Table 20. Table 20 Priority Structur e within Interrupt Level Source Level Non-Maskable Interrupt (NMI) (highest) External Interrupt 0 1 Timer 0 Interrupt 2 External Interrupt 1 3 Timer 1 Interrupt 4 UART Interrupt 5 Timer 2,UART Normal Divider Overflow, MultiCAN, LIN Interrupt ADC, MultiCAN Interrupt 7 SSC Interrupt 8 External Interrupt 2, Timer 21, UART1, UART1 Normal Divider Overflow, MDU, CORDIC Interrupt External Interrupt [6:3], MultiCAN Interrupt 10 CCU6 Interrupt Node Pointer 0, MultiCAN interrupt 11 CCU6 Interrupt Node Pointer 1, MultiCAN Interrupt 12 CCU6 Interrupt Node Pointer 2, MultiCAN Interrupt 13 CCU6 Interrupt Node Pointer 3, MultiCAN Interrupt 14

Data Sheet 62 V1.1, 2010-08

3.5 Parallel Ports

The SAA-XC886 has 34 port pins organized into five parallel ports, Port 0 (P0) to Port 4 (P4). Each pin has a pair of internal pull-up and pull-down devices that can be individually enabled or disabled. Ports P0, P1, P3 and P4 are bidirectional and can be used as general purpose input/output (GPIO) or to perform alternate input/output functions for the on-chip peripherals. When configured as an output, the op en drain mode can be selected. Port P2 is an inpu t-only port, providing gener al purpose i nput functions, alternate input fu nctions for the on-chip peripherals, and also analog inputs for the Analog-to-Digital Converter (ADC). Bidirectional Port Features

• Configurable pin direction
• Configurable pull-up /pull-down devices
• Configurable open drain mode
• Transfer of data through digital inpu ts and outputs (general purpose I/O)
• Alternate input/output for on-chip peripherals Input Port Features
• Configurable input driver
• Configurable pull-up /pull-down devices
• Receive of data through digita l input (general purpose input)
• Alternate input for on-chip peripherals
• Analog input for ADC module

Data Sheet 65 V1.1, 2010-08

3.6 Power Supply System with Embedded Voltage Regulator

The SAA-XC886 microcontroller requires two different levels of power supply:

• 5.0 V for the Embedded Voltag e Regulator (EVR) and Ports
• 2.5 V for the core, memory, on-ch ip oscillator, and peripherals Figure 20 shows the SAA-XC886 power supply syste m. A power supply of 5.0 V must be provided from the external power supply pin. The 2.5 V power supply for the logic is generated by the EVR. The EVR helps to reduce the pow er consumption of the whole chip and the complexity of the application board design. The EVR consists of a main voltage regula tor and a low power voltage regulator. In active mode, both voltage regulators are enabled. In power-down mode, the main voltage regulator is switched off, while the low power voltage re gulator continues to function and provide power supply to the system with low power consumption. Figure 20 SAA-XC886 Power Supply System EVR Features
• Input voltage ( VDDP): 5.0 V
• Output voltage ( VDDC): 2.5 V ± 7.5%
• Low power voltage regulator provided in power-down mode
• VDDC and VDDP prewarning detection
• VDDC brownout detection On-chip OSC CPU & Memory VDDC (2.5V) VDDP (5.0V) VSSP GPIO Ports (P0-P5) EVR Peripheral logic FLASH ADC PLL XTAL1& XTAL2

Data Sheet 66 V1.1, 2010-08

3.7 Reset Control

The SAA-XC886 has five types of reset: power-on reset, hardware reset, watchdog timer reset, power-down wake-up reset, and brownout reset. When the SAA-XC886 is first powered up, the status of certain pins (see Table 22) must be defined to ensure proper start operation of the device. At the end of a reset sequence, the sampled values are latched to select the desired b oot option, which cannot be modified until the next power-on reset or hardware reset. Th is guarantees stable conditions during the normal operation of the device. In order to power up the system properly, the external reset pin RESET must be asserted until VDDC reaches 0.9*VDDC. The delay of external reset can be realized by an external capacitor at RESET pin. This capacitor value must be selected so that VRESET reaches 0.4 V, but not before VDDC reaches 0.9* VDDC. A typical application example is shown in Figure 21. The VDDP capacitor value is 100 nF while the VDDC capacitor value is 220 nF. T he capacitor connected to RESET pin is 100 nF. Typically, the time taken for VDDC to reach 0.9*VDDC is less than 50μs once VDDP reaches 2.3V. Hence, based on the condition that 10% to 90% VDDP (slew rate) is less than 500 μs, the RESET pin should be held low for 500 μs typically. See Figure 22. Figure 21 Reset Circuitry VSSP VDDP VDDC VSSC RESET EVR VR VIN 100nF 220nF typ. 100nF XC886 30k

Data Sheet 67 V1.1, 2010-08 Figure 22 VDDP, VDDC and VRESET during Power-on Reset The second type of reset in SAA- XC886 is the hardware reset. This reset function can be used during normal operation or when the chip is in power-down mode. A reset input pin RESET is provided for the hardware reset. The Watchdog Timer (WDT) module is also capable of resetting the device if it detects a malfunction in the system. Another type of reset that needs to be detected is a re set while the device is in power-down mode (wake-up reset). While the contents of the static RAM are undefined after a power-on reset, they are well defin ed after a wake-up reset from power-down mode. VDDP RESET wit h capacitor 2.3V VDDC < 0.4V 0.9*VDDC 2.5V Voltage Voltage Time Time typ. < 50 μs

Data Sheet 68 V1.1, 2010-08

3.7.1 Module Reset Behavior

Table 21 lists the functions of t he SAA-XC886 and the variou s reset types that affect these functions. The symbol “■” signifies that the particular function is reset to its default state.

3.7.2 Booting Scheme

When the SAA-XC886 is reset, it must ident ify the type of configuration with which to start the different modes once the reset sequence is complete. Thus, boot configuration information that is required for activation of special modes and conditions needs to be applied by the external world through input pins. After power-on reset or hardware reset, the pins MBC, TMS and P0 .0 collectively select t he different boot options. Table 22 shows the available boot options in the SAA-XC886. Table 21 Effect of Reset on Device Functions Module/ Function Wake-Up Reset Watchdog Reset Hardware Reset Power-On Reset Brownout Reset On-Chip Static RAM Not affected, Reliable Not affected, Reliable Not affected, Reliable Affected, un- reliable Affected, un- reliable Oscillator, PLL ■ Not affected ■■■ EVR The voltage regulator is switched on Not affected ■■■ NMI Disabled Disabled ■■■ Table 22 SAA-XC886 Boot Selection MBC TMS P0.0 Type of Mode PC Start Value 1 0 X User Mode 1); on-chip OSC/PLL non-bypassed 0000 H 0 0 X BSL Mode; on-chip OSC/PLL non-bypassed 2) 0000H 0 1 0 OCDS Mode; on-chip OSC/PLL non- bypassed 0000H 1 1 0 User (JTAG) Mode 3); on-chip OSC/PLL non- bypassed (normal) 0000H

Data Sheet 69 V1.1, 2010-08 Note: The boot options are valid only with the default set of UART and JTAG pins.

3.8 Clock Generation Unit

The Clock Generation Unit (CGU) allows great flexibility in the clock generation for the SAA-XC886. The power consumpt ion is indirectly prop ortional to the frequency, whereas the performance of the microcontroller is directly proportional to the frequency. During user program execution, the frequency can be programmed for an optimal ratio between performance and power consumption. Therefore the power consumption can be adapted to the actual application state.

• Phase-Locked Loop (PLL) for multiplyin g clock source by different factors
• P L L B a s e M o d e
• Prescaler Mode
• P L L M o d e
• Power-down mode support The CGU consists of an oscillator circuit and a PLL. In the SAA-XC886, the oscillator can be from either of these tw o sources: the on-chip oscilla tor (9.6 MHz) or the external oscillator (4 MHz to 12 MHz). The term “osc illator” is used to re fer to both on-chip oscillator and external osci llator, unless otherwise stated . After the reset, the on-chip oscillator will be used by default.The external oscillator can be selected via software. In addition, the PLL prov ides a fail-safe logic to perform oscillator run and loss-of-lock detection. This allows emer gency routines to be executed for system recovery or to perform system shut down. 1) BSL mode is automatically entered if no valid password is installed and data at memory address 0000H equals zero. 2) OSC is bypassed in MultiCAN BSL mode 3) Normal user mode with standard JTAG (T CK,TDI,TDO) pins for hot-attach purpose.

Data Sheet 70 V1.1, 2010-08 Figure 23 CGU Block Diagram PLL Base Mode When the oscillator is disconnected from the PLL, the system clock is derived from the VCO base (free running) frequency clock (Table 24) divided by the K factor. (3.1) Prescaler Mode (VCO Bypass Operation) In VCO bypass operation, the system clock is derived from the oscillator clock, divided by the P and K factors. (3.2) PLL core lock detect N:1 P:1 fvco fn fp osc fail detect OSC fosc K:1 fsys NDIVOSCDISC OSCR LOCK VCOBYP PLLBYP fSYS fVCObase K----×= fSYS fOSC

Data Sheet 71 V1.1, 2010-08 PLL Mode The system clock is derived from the oscill ator clock, multipli ed by the N factor, and divided by the P and K factors. Both VCO bypass and PLL bypass must be inactive for this PLL mode. The PLL mode is used during normal system operation. (3.3) System Frequency Selection For the SAA-XC886, the value of P is fixed to 1. In order to obtain the required fsys, the value of N and K can be sele cted by bits NDIV and KDIV respectively for different oscillator inputs. The output frequency must always be configured for 96 MHz. Table 23 provides examples on how fsys = 96 MHz can be obtained fo r the different oscillator sources. Table 23 System frequency ( fsys =9 6M H z ) Oscillator Fosc N P K Fsys On-chip 9.6 MHz 20 1 2 96 MHz External 8 MHz 24 1 2 96 MHz

6 MHz 32 1 2 96 MHz

4 MHz 48 1 2 96 MHz

N

Data Sheet 72 V1.1, 2010-08 Table 24 shows the VCO range for the SAA-XC886.

3.8.1 Recommended External Oscillator Circuits

The oscillator circuit, a Pierce oscillator, is designed to work with both, an external crystal oscillator or an external stable clock source. It basically consists of an inverting amplifier and a feedback element with XTAL1 as input, and XTAL2 as output. When using a crystal, a proper external oscillator circuitr y must be con nected to both pins, XTAL1 and XTAL2. Th e crystal frequency can be within the range of 4 MHz to 12 MHz. Additionally, it is necessary to have two load capacitances CX1 and CX2, and depending on the crystal type, a series resistor RX2, to limit the current. A test resistor RQ may be temporarily inserted to measure the oscillation allowance (negative resistance) of the oscillator circuitry. RQ values are typically specified by the crystal vendor. The CX1 and CX2 values shown in Figure 24 can be used as starti ng points for the negative resistance evaluation and for non-producti ve systems. The exact values and related operating range are dependent on the crystal frequency and have to be determined and optimized together wit h the crystal vendor using the negative resistance method. Oscillation measurement with the final target system is strongly recommended to verify the input amplitude at XTAL1 and to determine the actual oscillation allowance (margin negative resistance) for the oscillator-crystal system. When using an external clock signal, the signal must be connected to XTAL1. XTAL2 is left open (unconnected). The oscillator can also be us ed in combination with a ceramic re sonator. The final circuitry must also be verifi ed by the res onator vendor. Figure 24 shows the recommended external oscillator circuitries fo r both operating mode s, external crystal mode and external input clock mode. Table 24 VCO Range fVCOmin fVCOmax fVCOFREEmin fVCOFREEmax Unit 150 200 20 80 MHz 100 150 10 80 MHz

Data Sheet 73 V1.1, 2010-08 Figure 24 External Os cillator Circuitry Note: For crystal operation, it is st rongly recommended to measure the negative resistance in the final target system (layout) to determine the optimum parameters for the oscillator operation. Please refer to the minimum and maximum values of the negative resistance specified by the crystal supplier. Clock_EXOSC XC886 Oscillator VSS CX1 4 - 12 MHz CX2 XTAL 1 XTAL 2 XC886 Oscillator XTAL 1 XTAL 2 External Clock Signal fOSC fOSC Fundamental Mode Crystal Crystal Frequency C X1, CX2

4 MHz

8 MHz

10 MHz

12 MHz 12 pF

1) Note that these are evaluation start values ! RX2 RX2 RQ VSS

Data Sheet 74 V1.1, 2010-08

3.8.2 Clock Management

The CGU generates all clock signals required within the mi crocontroller from a single clock, fsys. During normal syst em operation, the typical fr equencies of the different modules are as follow:

• CPU clock: CCLK, SCLK = 24 MHz
• Fast clock (used by MultiCA N): FCLK = 24 or 48 MHz
• Peripheral clock: PCLK = 24 MHz
• Flash Interface clock: CCLK2 = 48 MHz and CCLK = 24 MHz In addition, different clock frequencies can be output to pin CLKOUT (P0.0 or P0.7). The clock output frequency, which is derived from the clock output divider (bit COREL), can further be divided by 2 using toggle latch (bit TL EN is set to 1). Th e resulting output frequency has a 50% duty cycle. Figure 25 shows the clock di stribution of the SAA- XC886. Figure 25 Clock Generation from fsys PLL N,P,K fsys= 96MHz CLKREL CCLK SCLK PCLK CCLK2 CORE Peripherals FLASH Interface OSC CLKOUT fosc COREL COUTS Toggle Latch TLEN MultiCAN FCLK FCCFG SD

Data Sheet 75 V1.1, 2010-08 For power saving purposes, the clocks may be disabled or slowed down according to Table 25. Table 25 System frequency ( fsys =9 6M H z ) Power Saving Mode Action Idle Clock to the CPU is disabled. Slow-down Clocks to the CPU and all th e peripherals are divided by a common programmable factor defined by bit field CMCON.CLKREL. Power-down Oscillator an d PLL are switched off.

Data Sheet 76 V1.1, 2010-08

3.9 Power Saving Modes

The power saving modes of the SAA-XC886 provide flexible power consumption through a combination of techniques, including:

• Stopping the CPU clock
• Stopping the clocks of i ndividual system components
• Reducing clock speed of some peripheral components
• Power-down of the entire system with fast restart capability After a reset, the ac tive mode (normal operating m ode) is selected by default (see Figure 26) and the system runs in the main system clock frequency. From active mode, different power saving modes can be selected by software. They are:
• Idle mode
• Slow-down mode
• Power-down mode Figure 26 Transition betw een Power Saving Modes POWER-DOWN IDLE ACTIVE SLOW-DOWN set PD bit set PD bit set IDLE bit set IDLE bit set SD bit clear SD bit any interrupt & SD=0 EXINT0/RXD pin & SD=0 EXINT0/RXD pin & SD=1 any interrupt & SD=1

Data Sheet 77 V1.1, 2010-08

3.10 Watchdog Timer

The Watchdog Timer (WDT) provides a high ly reliable and secure way to detect and recover from software or hardware failures. The WDT is reset at a regular interval that is predefined by the user. The CPU must service the WDT within this interval to prevent the WDT from causing an SAA-XC886 system reset. Hence, r outine service of the WDT confirms that the system is functioning properly. This ensure s that an accidental malfunction of the SAA-XC886 will be aborted in a user-specified time period. In debug mode, the WDT is def ault suspended and stops counting. Therefore, there is no need to refresh the WDT during debugging.

• 16-bit Watchdog Timer
• Programmable reload value fo r upper 8 bits of timer
• Programmable window boundary
• Selectable input frequency of fPCLK/2 or fPCLK/128
• Time-out detection wit h NMI generation and reset prewarning activation (after which a system reset will be performed) The WDT is a 16-bit timer incremented by a count rate of fPCLK/2 or fPCLK/128. This 16-bit timer is realized as two concatenated 8-bit timers. The upper 8 bits of the WDT can be preset to a user-programmable value via a watchdog service access in order to modify the watchdog expire time per iod. The lower 8 bits are reset on each service access. Figure 27 shows the block diagram of the WDT unit. Figure 27 WDT Block Diagram WDTREL MUX WDT Low Byte 1:2 Clear WDT Control 1:128 WDT High Byte FNMIWDT WDTIN fPCLK Logic ENWDT ENWDT_P WDTRST Overflow/Time-out Control & Window-boundary control WDTWINB

Data Sheet 78 V1.1, 2010-08 If the WDT is not serviced before the timer overflow, a system malfunction is assumed. As a result, the WDT NMI is triggered (asse rt FNMIWDT) and the reset prewarning is entered. The prewarni ng period lasts for 30 H count, after which the system is reset (assert WDTRST). The WDT has a “programmable window boundary” which disallows any refresh during the WDT’s count-up. A refr esh during this win dow boundary constitutes an invalid access to the WDT, causing the reset prewarning to be entered but without triggering the WDT NMI. The system will still be reset after the prewarning period is over. The window boundary is from 0000H to the value obtained from the concatenation of WDTWINB and 00H. After being serviced, the WDT continues counting up from the value (<WDTREL> * 28). The time period for an overflow of the WDT is programmable in two ways:

• The input frequency to the WDT can be selected to be either fPCLK/2 or fPCLK/128
• The reload value WDTREL for the high by te of WDT can be programmed in register WDTREL The period, PWDT, between servicing the WDT and the next overflow can be determined by the following formula: (3.4) If the Window-Boundary Refresh featur e of the WDT is enabled, the period PWDT between servicing the WDT and the next overflow is shortened if WDTWINB is greater than WDTREL, see Figure 28. This period can be calculated using the same formula by replacing WDTREL with WDTWINB. For this feature to be useful, WDTWINB cannot be smaller than WDTREL. PWDT 2 1W D T I N+6 ×() 216 WDTREL–2 8×()× fPCLK

Data Sheet 79 V1.1, 2010-08 Figure 28 WDT Timing Diagram Table 26 lists the possible watchdog time ranges that can be achieved using a certain module clock. Some numbers are rounded to 3 significant digits. Table 26 Watchdog Time Ranges Reload value In WDTREL Prescaler for fPCLK 2 (WDTIN = 0) 128 (WDTIN = 1)

24 MHz 24 MHz

FFH 21.3 μs1 . 3 7 m s 7FH 2.75 ms 176 ms 00H 5.46 ms 350 ms WDTREL WDTWINB time Count FFFFH No refresh allowed Refresh allowed

Data Sheet 80 V1.1, 2010-08

3.11 Multiplication/Division Unit

The Multiplication/Divis ion Unit (MDU) provides fast 16-bit multiplication, 16-bit and 32-bit division as well as shift and normalize features. It has been integrated to support the SAA-XC886 Core in real-time control applications, which require fast mathematical computations.

• Fast signed/unsigned 16-bit multiplication
• Fast signed/unsigned 32-bit di vide by 16-bit and 16-bit divide by 16-bit operations
• 32-bit unsigned no rmalize operation
• 32-bit arithmetic/logi cal shift operations Table 27 specifies the number of clock cycles used for calculation in various operations. Table 27 MDU Operation Characteristics Operation Result Remainder N o. of Clock Cycles used for calculation Signed 32-bit/16-bit 32-bit 16-bit 33 Signed 16-bit/16bit 16-bit 16-bit 17 Signed 16-bit x 16-bit 32-bit - 16 Unsigned 32-bit/16-bit 32-bit 16-bit 32 Unsigned 16-bit/16-bit 16-bit 16-bit 16 Unsigned 16-bit x 16-bit 32-bit - 16 32-bit normalize - - No. of shifts + 1 (Max. 32) 32-bit shift L/R - - No. of shifts + 1 (Max. 32)

Data Sheet 81 V1.1, 2010-08

3.12 CORDIC Coprocessor

The CORDIC Coprocessor provides CPU wit h hardware support for the solving of circular (trigonometric), linear (multiply-add, divide-add) and hyperbolic functions.

• Modes of operation – Supports all CORDIC operatin g modes for solving circul ar (trigonometric), linear (multiply-add, divide-add) and hyperbolic functions – Integrated look-up tables (L UTs) for all operating modes
• Circular vectoring mode: Ext ended support for values of initial X and Y data up to full range of [-215,(215-1)] for solving angle and magnitude
• Circular rotation mode: Extended support for values of initial Z data up to full range of [-2 15,(215-1)], representing angles in the range [- π,((215-1)/215)π] for solving trigonometry
• Implementation-depen dent operational frequency of up to 80 MHz
• Gated clock input to s upport disabling of module
• 16-bit accessible data width – 24-bit kernel data width plus 2 overflow bits for X and Y each – 20-bit kernel data width plus 1 overflow bit for Z – With KEEP bit to retain the la st value in the kernel register for a new calculation
• 16 iterations per calculation: Approximately 41 clock-cycles or less, from set of start (ST) bit to set of end-of-calculation flag, excludi ng time taken for write and read access of data bytes.
• Twos complement data processing – Only exception: X result data with us er selectable option for unsigned result
• X and Y data generally acce pted as integer or rational number; X and Y must be of the same data form
• Entries of LUTs are 20-bit signed integers – Entries of atan and atanh LUTs are inte ger representations (S19) of angles with the scaling such that [-215,(215-1)] represents the range [-π,((215-1)/215)π] – Accessible Z result data for circular and hyperbolic functions is integer in data form of S15
• Emulated LUT fo r linear function – Data form is 1 integer bit and 15-bit fractional part (1.15) – Accessible Z result data fo r linear function is rational number with fixed data form of S4.11 (signed 4Q16)
• Truncation Error – The result of a CORDIC calculation may return an approximation due to truncation of LSBs – Good accuracy of the CORDIC calculated result data, especially in circular mode
• Interrupt – On completion of a calculation

Data Sheet 82 V1.1, 2010-08 – Interrupt enabling a nd corresponding flag

3.13 UART and UART1

The SAA-XC886 provides two Universal Asyn chronous Receiver/Transmitter (UART and UART1) modules for full- duplex asynchronous recept ion/transmission. Both are also receive-buffered, i.e., they can commence recepti on of a second byte before a previously received byte has been read from the receive register. However, if the first byte still has not been read by the time reception of the second byte is complete, one of the bytes will be lost.

• Full-duplex asynchronous modes – 8-bit or 9-bit data frames, LSB first – Fixed or vari able baud rate
• Receive buffered
• Multiprocessor communication
• Interrupt generation on the completion of a data transmission or reception The UART modules can operate in the four modes shown in Table 28. There are several ways to generate the baud rate clock for the serial port, depending on the mode in which it is operating. In mode 0, the baud rate for the transfer is fixed at fPCLK/2. In mode 2, the baud rate is generated internally based on the UART input clock and can be configured to eitherfPCLK/32 or fPCLK/64. For UART1 module, only fPCLK/64 is available. The variable baud rate is set by the underflow rate on the dedicated baud-rate generator. For UART module, t he variable baud rate alter natively can be set by the overflow rate on Timer 1.

3.13.1 Baud-Rate Generator

Both UART modules have their own dedicat ed baud-rate generator, which is based on a programmable 8-bit reload value, and in cludes divider stages (i.e., prescaler and Table 28 UART Modes Operating Mode Baud Rate Mode 0: 8-bit shift register fPCLK/2 Mode 1: 8-bit shift UART Variable Mode 2: 9-bit shift UART fPCLK/32 or fPCLK/641) 1) For UART1 module, the baud rate is fixed at f PCLK/64. Mode 3: 9-bit shift UART Variable

Data Sheet 83 V1.1, 2010-08 fractional divider) for generating a wide range of baud rates based on its input clock fPCLK, see Figure 29. Figure 29 Baud-rate Generator Circuitry The baud rate timer is a count-down timer a nd is clocked by eith er the output of the fractional divider ( fMOD) if the fractional divider is enabled (FDCON.FDEN = 1), or the output of the prescaler (fDIV) if the fractional divider is disabled (FDEN = 0). For baud rate generation, the fractional di vider must be configured to fractional divider mode (FDCON.FDM = 0). This allows the baud rate control run bit BCON.R to be used to start or stop the baud rate timer. At each timer underflow, the timer is reloaded with the 8-bit reload value in register BG and one clock pulse is generated for the serial channel. Enabling the fractional divider in normal divider mode (FDEN = 1 and FDM = 1) stops the baud rate timer and nullifies the effect of bit BCON.R. See Section 3.14. The baud rate (fBR) value is dependent on the following parameters:

• Input clock fPCLK
• Prescaling factor (2 BRPRE) defined by bit field BRPRE in register BCON
• Fractional divider (STEP/256 ) defined by register FDSTEP (to be considered only if fractional divider is enab led and operatin g in fractional divider mode)
• 8-bit reload value (BR_VAL UE) for the baud rate timer defined by register BG FDSTEP FDM Adder FDRES FDEN&FDM clk Fractional Divider Prescaler NDOV ‘0’ FDEN (overflow) fBR 8-Bit Baud Rate Timer 8-Bit Reload Value R fDIV fDIVfPCLK fMOD

Data Sheet 84 V1.1, 2010-08 The following formulas calculate the final baud rate without and with the fractional divider respectively: (3.5) (3.6) The maximum baud rate that can be generated is limited to fPCLK/32. Hence, for a module clock of 24 MHz, the maximum achievable baud rate is 0.75 MBaud. Standard LIN protocol can support a maximum baud rate of 20 kH z, the baud rate accuracy is not critical and the fractional divider can be disabled. Only the prescaler is used for auto baud rate calculation. For LIN fast mode, which supports the baud rate of 20 kHz to 115.2 kHz, the higher baud rates require the use of the frac tional divider for greater accuracy. Table 29 lists the various commonly used baud rates with their corresponding parameter settings and deviation errors. The fractiona l divider is disabled and a module clock of 24 MHz is used. The fractional divider allows baud rates of higher accuracy (lower deviation error) to be generated. Table 30 lists the resulting de viation errors from ge nerating a baud rate of 115.2 kHz, using different modu le clock frequencies. The fr actional divider is enabled (fractional divider mode) and the corresponding parameter settings are shown. Table 29 Typical Baud rates for UART with Fractional Divider disabled Baud rate Prescaling Factor (2BRPRE) Reload Value (BR_VALUE + 1) Deviation Error 19.2 kBaud 1 (BRPRE=000 B) 7 8 ( 4 E H)0 . 1 7 % 9600 Baud 1 (BRPRE=000 B) 156 (9C H)0 . 1 7 % 4800 Baud 2 (BRPRE=001 B) 156 (9C H)0 . 1 7 % 2400 Baud 4 (BRPRE=010 B) 156 (9C H)0 . 1 7 % baud rate fPCLK 16 2 BRPRE BR_VALUE 1+()×× baud rate fPCLK 16 2 BRPRE BR_VALUE 1+()××

Data Sheet 85 V1.1, 2010-08

3.13.2 Baud Rate Generation using Timer 1

In UART modes 1 and 3 of UART module, Timer 1 can be used for generating the variable baud rates. In theo ry, this timer could be used in any of its modes. But in practice, it should be set into auto-reload mode (Timer 1 mode 2), with its high byte set to the appropriate value for the required b aud rate. The baud rate is determined by the Timer 1 overflow rate and the value of SMOD as follows: (3.7)

3.14 Normal Divider Mode (8-bit Auto-reload Timer)

Setting bit FDM in register FDCON to 1 configures the fractional divider to normal divider mode, while at the same time disables baud rate generation (see Figure 29). Once the fractional divider is enabled (FDEN = 1), it f unctions as an 8-bit auto-reload timer (with no relation to baud rate generation) and counts up from the reload value with each input clock pulse. Bit field RESULT in register FDRES represents the timer value, while bit field STEP in register FDSTEP defines the reload value. At eac h timer overflow, an overflow flag (FDCON.NDOV) will be set and an interrupt request generated. This gives an output clock fMOD that is 1/n of the input clock fDIV, where n is defined by 256 - STEP. The output frequency in normal divider mode is derived as follows: (3.8) Table 30 Deviation Error for UART wi th Fractional Divider enabled fPCLK Prescaling Factor (2BRPRE) Reload Value (BR_VALUE + 1) STEP Deviation Error 24 MHz 1 10 (A H) 197 (C5 H) +0.20 % 12 MHz 1 6 (6 H) 236 (EC H) +0.03 % 8M H z 1 4 ( 4 H) 236 (EC H) +0.03 % 6M H z 1 3 ( 3 H) 236 (EC H) +0.03 % Mode 1, 3 baud rate 2SMOD fPCLK× fMOD fDIV

Data Sheet 86 V1.1, 2010-08

3.15 LIN Protocol

The UART module can be used to support the Local Interconnect Network (LIN) protocol for both master and slave operations. The LIN baud rate detect ion feature, which consists of the hardware logic for Break and Synch Byte detection, provides the capability to detect the baud rate within LIN protocol using Timer 2. This allows the UART to be synchronized to the LIN baud rate for data transmission and reception. Note: The LIN baud rate dete ction feature is available fo r use only with UART. To use UART1 for LIN communication, software has to be implemented to detect the Break and Synch Byte. LIN is a holistic comm unication concept for local inte rconnected networks in vehicles. The communication is based on the SCI (UART) data format, a single-master/multiple- slave concept, a clock synchronization fo r nodes without stab ilized time base. An attractive feature of LIN is self-synchronization of the sl ave nodes without a crystal or ceramic resonator, which significantly reduces the cost of hardware platform. Hence, the baud rate must be calculated and returned with every message frame. The structure of a LIN frame is shown in Figure 30. The frame consists of the:

• Header, which comprises a Break ( 13-bit time low), Synch Byte (55H), and ID field
• Response time
• Data bytes (according to UART protocol)
• Checksum Figure 30 Structure of LIN Frame Frame slot Frame Response Response spaceHeader Synch Protected identifier Data 1 Data 2 Data N Checksum

Data Sheet 87 V1.1, 2010-08

3.15.1 LIN Header Transmission

LIN header transmission is only applicable in master mode. In the LIN communication, a master task decides when and which fram e is to be transferred on the bus. It also identifies a slave task to pr ovide the data trans ported by each frame. The information needed for the handshaking betw een the master and slave ta sks is provided by the master task through the header portion of the frame. The header consists of a break and synch pattern followed by an identifier. Among these three fields, only the break pattern cannot be transmitted as a normal 8-bit UART data. The break must contain a dominant value of 13 bits or more to ensure proper synchronization of slave nodes. In the LIN communication, a slave task is r equired to be synchronized at the beginning of the protected identifier fi eld of frame. For this purpos e, every frame starts with a sequence consisting of a brea k field followed by a synch by te field. This sequence is unique and provides enough information for any slave task to detect the beginning of a new frame and be synchronized at the start of the identifier field. Upon entering LIN communication, a connection is establ ished and the transfer speed (baud rate) of the serial communication part ner (host) is automatically synchronized in the following steps: STEP 1: Initialize interface for reception and timer for baud rate measurement STEP 2: Wait for an incoming LIN frame from host STEP 3: Synchronize the baud rate to the host STEP 4: Enter for Master Request Frame or for Slave Response Frame Note: Re-synchronization and setup of baud rate are always done for every Master Request Header or Slave Response Header LIN frame.

Data Sheet 88 V1.1, 2010-08

3.16 High-Speed Synchronous Serial Interface

The High-Speed Synchronou s Serial Interface (SSC ) supports full-duplex and half-duplex synchronous communication. The serial clock signal can be generated by the SSC internally (master m ode), using its own 16-bit bau d-rate generator, or can be received from an external master (slave mode). Data width, shift direction, clock polarity and phase are programmable. This allows communication with SPI-compatible devices or devices using other synchronous serial interfaces.

• Master and slave mode operation – Full-duplex or ha lf-duplex operation
• Transmit and receive buffered
• Flexible data format – Programmable number of data bits: 2 to 8 bits – Programmable shift directi on: LSB or MSB shift first – Programmable clock polarity: idle lo w or high state for the shift clock – Programmable clock/data phase: data shift with leading or trailing edge of the shift clock
• Variable baud rate
• Compatible with Serial Pe ripheral Interface (SPI)
• Interrupt generation – On a transmitter empty condition – On a receiver full condition – On an error condition (receive, p hase, baud rate, transmit error) Data is transmitted or received on lines TXD and RXD, which are normally connected to the pins MTSR (Master Transmit/Slave Re ceive) and MRST (Ma ster Receive/Slave Transmit). The clock signal is output via line MS_CLK (Master Serial Shift Clock) or input via line SS_CLK (Slave Serial Shift Clock). Both lines are normally connected to the pin SCLK. Transmission and reception of data are double-buffered. Figure 31 shows the block diagram of the SSC.

Data Sheet 89 V1.1, 2010-08 Figure 31 SSC Block Diagram PCLK SS_CLK RIR TIR EIR Receive Int. Request Transmit Int. Request Error Int. Request ControlStatus TXD(Master) RXD(Slave) Shift Clock MS_CLK RXD(Master) TXD(Slave) Internal Bus Baud-rate Generator Clock Control SSC Control Block Register CON Pin Control16-Bit Shift Register Transmit Buffer Register TB Receive Buffer Register RB

Data Sheet 90 V1.1, 2010-08

3.17 Timer 0 and Timer 1

Timer 0 and Timer 1 can func tion as both timers or count ers. When functioning as a timer, Timer 0 and Timer 1 are incremented every machine cycle, i.e. every 2 input clocks (or 2 PCLKs). When functioning as a counter, Timer 0 and Timer 1 are incremented in response to a 1-to-0 transition (falling edge) at their respective external input pins, T0 or T1. Timer 0 and 1 are fully compat ible and can be configured in four different operating modes for use in a vari ety of applications, see Table 31. In modes 0, 1 and 2, the two timers operate independently, but in mode 3, their functions are specialized. Table 31 Timer 0 and Timer 1 Modes Mode Operation 0 13-bit timer The timer is essentially an 8-bit counter with a divide-by-32 prescaler. This mode is included solely for compatibility with Intel 8048 devices. 1 16-bit timer The timer registers, TLx and THx, are concatenated to form a 16-bit counter. 2 8-bit timer with auto-reload The timer register TLx is reloaded with a user-defined 8-bit value in THx upon overflow.

3 Timer 0 operates as two 8-bit timers

The timer registers, TL0 and TH0, operate as two separate 8-bit counters. Timer 1 is halted and retains its count even if enabled.

Data Sheet 91 V1.1, 2010-08

3.18 Timer 2 and Timer 21

Timer 2 and Timer 21 are 16-bit general purpose timers (THL2) that are fully compatible and have two modes of operation, a 16-bit auto-reload mode and a 16-bit one channel capture mode, see Table 32. As a timer, the timers count with an input clock of PCLK/12 (if prescaler is disabled). As a counter, they count 1-to-0 transitions on pin T2. In the counter mode, the maximum resolution for the count is PCLK/24 (if prescaler is disabled). Table 32 Timer 2 Modes Mode Description Auto-reload Up/Down Count Disabled

• Count up only
• Start counting from 16-bit reload value, overflow at FFFFH
• Reload event confi gurable for trigger by overflow condition only, or by negative/positive edge at input pin T2EX as well
• Programmble reload value in register RC2
• Interrupt is generate d with reload event Up/Down Count Enabled
• Count up or down, direction dete rmined by level at input pin T2EX
• No interrupt is generated
• Count up – Start counting from 16-bit re load value, overflow at FFFF H – Reload event triggered by overflow condition – Programmble reload value in register RC2
• Count down – Start counting from FFFF H, underflow at value defined in register RC2 – Reload event trigger ed by underflow condition – Reload value fixed at FFFF H Channel capture
• Count up only
• Start counting from 0000 H, overflow at FFFFH
• Reload event triggered by overflow condition
• Reload value fixed at 0000 H
• Capture event triggered by falling/rising edge at pin T2EX
• Captured timer value st ored in register RC2
• Interrupt is gene rated with reload or capture event

Data Sheet 92 V1.1, 2010-08

3.19 Capture/Compare Unit 6

The Capture/Compare Unit 6 (CCU6) provides two independent timers (T12, T13), which can be used for Pulse Width Modulation (P WM) generation, especially for AC-motor control. The CCU6 also supports specia l control modes for block commutation and multi-phase machines. The timer T12 can function in capture and/or compare mode for its three channels. The timer T13 can work in compare mode only. The multi-channel control unit generates output patterns, whic h can be modulated by T12 and/or T13. The modulation sources can be select ed and combined for the signal modulation. Timer T12 Features

• Three capture/compare channels, each ch annel can be used either as a capture or as a compare channel
• Supports generation of a three-phase PWM (six outputs, indi vidual signals for highside and lowside switches)
• 16-bit resolution, maximum count fr equency = peripheral clock frequency
• Dead-time control for each channel to av oid short-circuits in the power stage
• Concurrent update of the required T12/13 registers
• Generation of cente r-aligned and edge-aligned PWM
• Supports single-shot mode
• Supports many interr upt request sources
• Hysteresis-like control mode Timer T13 Features
• One independent compar e channel with one output
• 16-bit resolution, maximum count fr equency = peripheral clock frequency
• Can be synchronized to T12
• Interrupt generation at per iod-match and compare-match
• Supports single-shot mode Additional Features
• Implements block commutati on for Brushless DC-drives
• Position detection vi a Hall-sensor pattern
• Automatic rotational speed meas urement for block commutation
• Integrated error handling
• Fast emergency stop without CPU load via external signal (CTRAP)
• Control modes for multi-channel AC-drives
• Output levels can be selected and adapted to the power stage The block diagram of the CCU6 module is shown in Figure 32.

Data Sheet 93 V1.1, 2010-08 Figure 32 CCU6 Block Diagram channel 0 channel 1 channel 2 T12 dead- time control input / output control CC62 COUT62 CC61 COUT61 CC60 COUT60 COUT63 CTRAP channel 3T13 CCPOS0 2221 start compare captu re multi- channel control address decoder clock control interrupt control trap control compare compar e compar e compar e trap input port control CCPOS1 CCPOS2 outpu t select outpu t select Ha ll input module kernel CCU6_block_diagram T13HR T12HR

Data Sheet 94 V1.1, 2010-08

3.20 Controller Area Network (MultiCAN)

The MultiCAN module contains two Fu ll-CAN nodes operat ing independently or exchanging data and remote frames via a gateway function. Transmission and reception of CAN frames is handled in accordance to CAN specification V2.0 B active. Each CAN node can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. Both CAN nodes share a common set of message objects, where each message object may be individually allocated to one of the CAN nodes. Besides serving as a storage container for incoming and outgoing frames, message objects may be combined to build gateways between the CAN nodes or to setup a FIFO buffer. The message objects are organized in double chained lists, where each CAN node has it’s own list of message objects. A CAN node stores frames only into message objects that are allocated to the list of the CAN node. It only transmits messages from objects of this list. A powerful, command driven list controller performs all list operations. The bit timings for the CAN nodes are derived from the peripheral clock ( fCAN) and are programmable up to a data rate of 1 MBaud. A pair of receive and transmit pins connects each CAN node to a bus transceiver. Figure 33 Overview of the MultiCAN

• Compliant to ISO 11898. MultiCAN Module Kernel Mult iCAN_XC8_overview Port ControlCAN Node 0 CAN Control Message Object Buffer Objects CAN Node 1 TXDC0 RXDC0 TXDC1 RXDC1Linked List Control fCANClock Control Address Decoder & Data control Access Mediator Interrupt Controller CANSRC[7:0] A[13: 2] D[31:0]

Data Sheet 95 V1.1, 2010-08

• CAN functionality according to CAN specification V2.0 B active.
• Dedicated control registers ar e provided for each CAN node.
• A data transfer rate up to 1 MBaud is supported.
• Flexible and powerful message transfer c ontrol and error hand ling capabilities are implemented.
• Advanced CAN bus bit timing analysis and baud rate detection can be performed for each CAN node via the frame counter.
• Full-CAN functionality: A set of 32 message objects can be individually – allocated (assigned ) to any CAN node – configured as transmit or receive object – setup to handle frames with 11-bit or 29-bit identifier – counted or assigned a time stamp via a frame counter – configured to remote monitoring mode
• Advanced Accept ance Filtering: – Each message object provid es an individual acceptan ce mask to filter incoming frames. – A message object can be configured to accept only standard or only extended frames or to accept both standard and extended frames. – Message objects can be grouped into 4 priority classes. – The selection of the message to be transmitted first can be performed on the basis of frame identifier, IDE bit and RTR bit according to CAN arbitration rules.
• Advanced Message Ob ject Functionality: – Message Objects can be combined to build FIFO message buffers of arbitrary size, which is only limited by the total number of message objects. – Message objects can be linked to form a gateway to automatically transfer frames between 2 different CAN buses. A single gateway can link any two CAN nodes. An arbitrary number of gateways may be defined.
• Advanced Data Management: – The Message objects are org anized in double chained lists. – List reorganizations may be performed an y time, even during full operation of the CAN nodes. – A powerful, command driven list contro ller manages the organ ization of the list structure and ensures consistency of the list. – Message FIFOs are based on the list structure and can easily be scaled in size during CAN operation. – Static Allocation Commands offer compatibility with TwinCAN applications, which are not list based.
• Advanced Interrupt Handling: – Up to 8 interrupt output lines are available. Most interrupt requests can be individually routed to one of the 8 interrupt output lines. – Message postprocessing notifications c an be flexibly aggregated into a dedicated register field of 64 notification bits.

Data Sheet 96 V1.1, 2010-08

3.21 Analog-to-Digital Converter

The SAA-XC886 includes a high-performance 10-bit Analog-to-Digital Converter (ADC) with eight multiplexed analog input channels. The ADC uses a successive approximation technique to convert t he analog voltage levels from up to eight different sources. The analog input channels of the ADC are available at Port 2.

• Successive approximation
• 8-bit or 10-bit resolution (TUE of ± 1 LSB and ± 2 LSB, respectively)
• Eight analog channels
• Four independent result registers
• Result data protection for slow CPU access (wait-for-read mode)
• Single conversion mode
• Autoscan functionality
• Limit checking for conversion results
• Data reduction filter (accumulation of up to 2 conversion results)
• Two independent conversion request sources with programmable priority
• Selectable conversion request trigger
• Flexible interrupt generation wi th configurable service nodes
• Programmable sample time
• Programmable clock divider
• Cancel/restart feature for running conversions
• Integrated sample and hold circuitry
• Compensation of offset errors
• Low power modes

3.21.1 ADC Clocking Scheme

A common module clock fADC generates the various clock signals used by the analog and digital parts of the ADC module:

• fADCA is input clock for the analog part.
• fADCI is internal clock for the analog part (defines the time base for conversion length and the sample time). This clock is generated internally in the analog part, based on the input clock fADCA to generate a correct duty cycle for the analog components.
• fADCD is input clock for the digital part. The internal clock for the analog part fADCI is limited to a maximum frequency of 10 MHz. Therefore, the ADC clock prescaler must be programmed to a value that ensures fADCI does not exceed 10 MHz. The prescaler rati o is selected by bit field CTC in register

Data Sheet 97 V1.1, 2010-08 GLOBCTR. A prescaling ratio of 32 can be selected when the maximum performance of the ADC is not required. Figure 34 ADC Clocking Scheme For module clock fADC = 24 MHz, the analog clock fADCI frequency can be selected as shown in Table 33. As fADCI cannot exceed 10 MHz, bit field CTC should not be set to 00 B when fADC is 24 MHz. During slow-down mode where fADC may be reduced to 12 MHz, 6 MHz etc., CTC can be set to 00B as long as the divided analog clock fADCI does not exceed 10 MHz. Table 33 fADCI Frequency Selection Module Clock fADC CTC Prescaling Ratio Analog Clock fADCI 24 MHz 00 B ÷ 2 12 MHz (N.A) 01B ÷3 8M H z 10B ÷4 6M H z 11B (default) ÷ 32 750 kHz analog components fADCI fADC= fPCLK MUX arbiter registers interrupts analog part digital part fADCD fADCA 32÷ clock prescaler CTC ≤Condition: fADCI 10 MHz, where tADCI = fADCI

Data Sheet 98 V1.1, 2010-08 However, it is important to note that the conversion error could increase due to loss of charges on the capacitors, if fADC becomes too low during slow-down mode.

3.21.2 ADC Conversion Sequence

The analog-to-digital conversion procedure consists of the following phases:

• Synchronization phase ( tSYN)
• Sample phase ( tS)
• Conversion phase
• Write result phase ( tWR) Figure 35 ADC Conversion Timing tS tCONV tWR SAMPLE Bit BUSY Bit Conversion PhaseSample Phase Write Result Phase conversion start trigger Source interrupt Result interrupt tSYN Channel interrupt fADCI

Data Sheet 99 V1.1, 2010-08

3.22 On-Chip Debug Support

The On-Chip Debug Support (OCDS ) provides the basic functionality required for the software development and debugging of XC800-based systems. The OCDS design is based on these principles:

• Use the built-in debug func tionality of the XC800 Core
• Add a minimum of hardware overhead
• Provide support for mo st of the operations by a Monitor Program
• Use standard interfaces to communicate with the Host (a Debugger)
• Set breakpoints on instruction addre ss and on address ra nge within the Program Memory
• Set breakpoints on internal RAM address range
• Support unlimited software brea kpoints in Flash/RAM code region
• Process external breaks via JTAG and upon activating a dedicated pin
• Step through the program code The OCDS functional blocks are shown in Figure 36. The Monitor Mode Control (MMC) block at the center of OCDS system brings together control sign als and supports the overall functionality. The MMC communicates with the XC800 Core, primarily via the Debug Interface, and also receives reset and clock signals. After processing memory address and control signals from the core, the MMC provides proper access to the dedicated extra-memories: a Monitor ROM (holding the code) and a Monitor RAM (for work-data and Monitor-stack). The OCDS system is a ccessed through the JTAG 1), which is an interface dedicated exclusively for testing a nd debugging activities and is not normally used in an application. The dedica ted MBC pin is used for exter nal configuration and debugging control. Note: All the debug func tionality described here can normally be used only after SAA- XC886 has been started in OCDS mode. 1) The pins of the JTAG port can be assigned to either t he primary port (Port 0) or either of the secondary ports (Ports 1 and 2/Port 5). User must set the JTAG pins (TCK and TDI) as input during connection with the OCDS system.

Data Sheet 100 V1.1, 2010-08 Figure 36 OCDS Block Diagram

3.22.1 JTAG ID Register

This is a read-only register located inside the JTAG module, and is used to recognize the device(s) connected to the JTAG interface. Its content is shifted out when INSTRUCTION register contains the IDCODE command (opcode 04H), and the same is also true immediately after reset. The JTAG ID register contents for the SAA-XC886 Flash devices are given in Table 34. Note: The asterisk (*) above denotes all possible device configurations. Table 34 JTAG ID Summary Device Type Device Name JTAG ID Flash SAA-XC886*-8FF 1012 0083 H SAA-XC886*-6FF 1012 5083 H JTAG Module Monitor & Bootstrap loader Control line JTAG Memory Control Unit User Program Memory XC800 Core PROG & IRAM Addresses Debug Interface Reset Clock TMS TCK TDI TDO TCK TDI TDO Control Memory Control Debug Interface System Control Unit Boot/ Monitor ROM Monitor RAM User Internal RAM Reset Reset Clock PROG Data Monitor Mode Control MBC - parts of OCDS SuspendControl OCDS_XC886C-Block_Diagram-UM-v0.2

Data Sheet 101 V1.1, 2010-08

3.23 Chip Identification Number

The SAA-XC886 identity (ID) register is located at Page 1 of address B3H. The value of ID register is 09 H. However, for easy id entification of produc t variants, the Chip Identification Number, which is an unique number assigned to each product variant, is available. The differentiati on is based on the product, variant type and device step information. Two methods are provided to read a device’s chip identification number:

• In-application subroutine, GET_CHIP_INFO
• Bootstrap loader (BSL) mode A Table 35 lists the chip identification numbers of available SAA-XC886 device variants. Table 35 Chip Identification Number Product Variant Chip Identification Number AB-Step AB-Step AC-Step XC886CLM-8FFA 5V - 09900102 H 0B900102H XC886LM-8FFA 5V - 09900122 H 0B900122H XC886CLM-6FFA 5V - 09951502 H 0B951502H XC886LM-6FFA 5V - 09951522 H 0B951522H XC886CM-8FFA 5V - 09980102 H 0B980102H XC886C-8FFA 5V - 09980142 H 0B980142H XC886-8FFA 5V - 09980162 H 0B980162H XC886CM-6FFA 5V - 099D1502 H 0B9D1502H XC886C-6FFA 5V - 099D1542 H 0B9D1542H XC886-6FFA 5V - 099D1562 H 0B9D1562H

Data Sheet 102 V1.1, 2010-08

4 Electrical Parameters

Chapter 4 provides the characteristics of the electrical par ameters which are implementation-specific for the SAA-XC886.

4.1 General Parameters

The general parameters are described here to aid the us ers in interpreting the parameters mainly in Section 4.2 and Section 4.3.

4.1.1 Parameter Interpretation

The parameters listed in this section represent partly t he characteristics of the SAA- XC886 and partly its requireme nts on the system. To aid in terpreting the parameters easily when evaluating them for a design, they are indicated by the abbreviations in the “Symbol” column:

• CC These parameters indicate Controller Characteristics, which are distinctive features of the SAA-XC886 and must be regarded for a system design.
• SR These parameters indicate System Requirements, which must be provided by the microcontroller system in which the SAA-XC886 is designed in.

Data Sheet 103 V1.1, 2010-08

4.1.2 Absolute Maximum Rating

Maximum ratings are the ex treme limits to which the SAA-XC886 can be subjected to without permanent damage. Note: Stresses above thos e listed under “Absolute Ma ximum Ratings” may cause permanent damage to the device. This is a stre ss rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for exten ded periods may affect device reliability. During absolute maximum rating overload conditions (VIN > VDDP or VIN < VSS) the voltage on VDDP pin with respect to ground ( VSS) must not exceed the values defined by the absolute maximum ratings. Table 36 Absolute Maximu m Rating Parameters Parameter Symbol Limit Values Unit Notes min. max. Ambient temperature TA -40 140 °C under bias Storage temperature TST -65 150 °C 1) 1) Not subjected to production test, verified by design/characterization. Junction temperature TJ -40 150 °C under bias 1) Voltage on power supply pin with respect to VSS VDDP -0.5 6 V 1) Voltage on any pin with respect to VSS VIN -0.5 VDDP + 0.5 or max. 6 V whichever is lower Input current on any pin during overload condition IIN -10 10 mA 1) Absolute sum of all input currents during overload condition IIN|– 5 0 m A 1)

Data Sheet 104 V1.1, 2010-08

4.1.3 Operating Conditions

The following operating conditi ons must not be exceeded in order to ensure correct operation of the SAA-XC886. All parameters mentioned in the following table refer to these operating conditions, unless otherwise noted. Table 37 Operating Condition Parameters Parameter Symbol Limit Values Unit Notes/ Conditionsmin. max. Digital power supply voltage VDDP 4.5 5.5 V 5V Device Digital ground voltage VSS 0V Digital core supply voltage VDDC 2.3 2.7 V System Clock Frequency1) 1) fSYS is the PLL output clock. During normal operating mode, CPU clock is fSYS / 4. Please refer to Figure 25 for detailed description. fSYS 88.8 103.2 MHz Ambient temperature TA -40 140 °C SAA-XC886...

Data Sheet 105 V1.1, 2010-08

4.2 DC Parameters

The electrical characteristics of the DC Parameters are detailed in this section.

4.2.1 Input/Output Characteristics

Table 38 provides the characteristics of the input/output pins of the SAA-XC886. Table 38 Input/Output Characteristi cs (Operating Conditions apply) Parameter Symbol Limit Values Unit Test Conditions min. max. VDDP = 5 V Range Output low voltage VOL CC – 1.0 V IOL =1 5m A –1 . 0 V IOL = 5 mA, current into all pins > 60 mA –0 . 4 V IOL = 5 mA, current into all pins ≤ 60 mA Output high voltage VOH CC VDDP - 1.0 –V IOH =- 1 5m A VDDP - 1.0 –V IOH = -5 mA, current from all pins > 60 mA VDDP - 0.4 –V IOH = -5 mA, current from all pins ≤ 60 mA Input low voltage on port pins (all except P0.0 & P0.1) VILP SR – 0.3 × VDDP V CMOS Mode Input low voltage on P0.0 & P0.1 VILP0 SR -0.2 0.3 × VDDP V CMOS Mode Input low voltage on RESET pin VILR SR – 0.3 × VDDP V CMOS Mode Input low voltage on TMS pin VILT SR – 0.3 × VDDP V CMOS Mode Input high voltage on port pins (all except P0.0 & P0.1) VIHP SR 0.7 × VDDP – V CMOS Mode Input high voltage on P0.0 & P0.1 VIHP0 SR 0.7 × VDDP VDDP V CMOS Mode

Data Sheet 106 V1.1, 2010-08 Input high voltage on RESET pin VIHR SR 0.7 × VDDP – V CMOS Mode Input high voltage on TMS pin VIHT SR 0.75 × VDDP – V CMOS Mode Input Hysteresis on port pins HYSP CC 0.07 × VDDP – V CMOS Mode 1) Input Hysteresis on XTAL1 HYSX CC 0.07 × VDDC –V 1) Input low voltage at XTAL1 VILX SR VSS - 0.5 0.3 × VDDC V Input high voltage at XTAL1 VIHX SR 0.7 × VDDC VDDC + 0.5 V Pull-up current IPU SR – -10 μA VIHP,min -150 – μA VILP,max Pull-down current IPD SR – 10 μA VILP,max 150 – μA VIHP,min Input leakage current IOZ1 CC -2 2 μA0 < VIN < VDDP, TA ≤ 140°C2) Input current at XTAL1 IILX CC -10 10 μA Overload current on any pin IOV SR -5 5 mA 3) Absolute sum of overload currents IOV|S R – 2 5 m A 3) Voltage on any pin during VDDP power off VPO SR – 0.3 V 4) Maximum current per pin (excluding VDDP and VSS) IM SR SR – 15 mA Maximum current for all pins (excluding VDDP and VSS) Σ|IM|S R – 9 0 m A Table 38 Input/Output Characteristi cs (Operating Conditions apply) (cont’d) Parameter Symbol Limit Values Unit Test Conditions min. max.

Data Sheet 107 V1.1, 2010-08 Maximum current into VDDP IMVDDP SR – 120 mA 3) Maximum current out of VSS IMVSS SR – 120 mA 3) 1) Not subjected to production test, verified by design/characterization. Hysteresis is implemented to avoid meta stable states and switching due to internal ground bounce. It cannot be guaranteed that it suppresses switching due to external system noise. 2) An additional error current ( IINJ) will flow if an overload current fl ows through an adjacent pin. TMS pin and RESET pin have internal pull devices and are not included in the input leakage current characteristic. 3) Not subjected to production test, verified by design/characterization. 4) Not subjected to production test, verified by design/characterization. However, for applications with strict low power-down current requirements, it is mandatory that no active voltage source is supplied at any GPIO pin when VDDP is powered off. Table 38 Input/Output Characteristi cs (Operating Conditions apply) (cont’d) Parameter Symbol Limit Values Unit Test Conditions min. max.

Data Sheet 108 V1.1, 2010-08

4.2.2 Supply Threshold Characteristics

Table 39 provides the characteristics of the supply threshold in the SAA-XC886. Figure 37 Supply Th reshold Parameters Table 39 Supply Threshold Parameters (Operating Conditions apply) Parameters Symbol Limit Values Unit min. typ. max. VDDC prewarning voltage1) 1) Detection is disabled in power-down mode. VDDCPW CC 2.2 2.3 2.4 V VDDC brownout voltage in active mode1) VDDCBO CC 2.0 2.1 2.2 V RAM data retention voltage VDDCRDR CC 0.9 1.0 1.1 V VDDC brownout voltage in power-down mode2) 2) Detection is enabled in both active and power-down mode. VDDCBOPD CC 1.3 1.5 1.7 V VDDP prewarning voltage3) 3) Detection is enabled for external power supply of 5.0V. VDDPPW CC 3.4 4.0 4.6 V Power-on reset voltage2)4) 4) The reset of EVR is extended by 300 μs typically after the VDDC reaches the power-on reset voltage. VDDCPOR CC 1.3 1.5 1.7 V VDDP VDDC VDDPPW VDDCPOR VDDCPW VDDCBO VDDCBOPD 5.0V 2.5V VDDCRDR

Data Sheet 109 V1.1, 2010-08

4.2.3 ADC Characteristics

The values in the table be low are given for an analog power supply between 4.5 V to 5.5 V. All ground pins (VSS) must be externally connected to one single star point in the system. The voltage difference between the ground pins must not exceed 200mV. Table 40 ADC Characteristics (O perating Conditions apply; VDDP = 5V Range) Parameter Symbol Limit Values Unit Test Conditions/ Remarksmin. typ . max. Analog reference voltage VAREF SR VAGND + 1 VDDP VDDP + 0.05 V 1) Analog reference ground VAGND SR VSS - 0.05 VSS VAREF - 1 V 1) Analog input voltage range VAIN SR VAGND – VAREF V ADC clocks fADC – 24 25.8 MHz module clock 1) fADCI – – 10 MHz internal analog clock 1) See Figure 34 Sample time tS CC (2 + INPCR0.STC) × tADCI μs 1) Conversion time tC CC See Section 4.2.3.1 μs 1) Total unadjusted error |TUE| CC – – 1 LSB 8-bit conversion 2) – – 2 LSB 10-bit conversion 2) Differential Nonlinearity |EADNL| CC – 1 – LSB 10-bit conversion 1) Integral Nonlinearity |EAINL| CC – 1 – LSB 10-bit conversion 1) Offset |EAOFF| CC – 1 – LSB 10-bit conversion 1) Gain |EAGAIN| CC – 1 – LSB 10-bit conversion 1) Overload current coupling factor for analog inputs KOVA CC – – 1.0 x 10-4 – IOV >0 1)3) –– 1 . 5 x 10-3 – IOV <0 1)3) Overload current coupling factor for digital I/O pins KOVD CC – – 5.0 x 10-3 – IOV >0 1)3) –– 1 . 0 x 10-2 – IOV <0 1)3)

Data Sheet 110 V1.1, 2010-08 Switched capacitance at the reference voltage input CAREFSW CC – 10 20 pF 1)4) Switched capacitance at the analog voltage inputs CAINSW CC – 5 7 pF 1)5) Input resistance of the reference input RAREF CC – 1 2 k Ω 1) Input resistance of the selected analog channel RAIN CC – 1 1.5 k Ω 1) 1) Not subjected to production test, verified by design/characterization 2) TUE is tested at VAREF =5 . 0V , VAGND =0V , VDDP =5 . 0V . 3) An overload current ( IOV) through a pin injects a certain error current ( IINJ) into the adjacent pins. This error current adds to the respective pin’s leakage current (IOZ). The amount of error current depends on the overload current and is defined by the overload coupling factor KOV. The polarity of the injected error current is inverse compared to the polarity of the overload current that produces it. The total current through a pin is |ITOT| = |IOZ1| + (|IOV| × KOV). The additional error current may distort the input voltage on analog inputs. 4) This represents an equivalent switched capacitance. This capacitance is not switched to the reference voltage at once. Instead of this, smaller capacitances are successively switched to the reference voltage. 5) The sampling capacity of the conversion C-Network is pre-charged to VAREF/2 before connecting the input to the C-Network. Because of the parasitic elements, the voltage measured at ANx is lower than VAREF/2. Table 40 ADC Characteristics (O perating Conditions apply; VDDP = 5V Range) Parameter Symbol Limit Values Unit Test Conditions/ Remarksmin. typ . max.

Data Sheet 111 V1.1, 2010-08 Figure 38 ADC Input Circuits VAGNDx REXT Analog Input Circuitry VAIN CEXT ANx CAINSW RAIN, On VAGNDx Reference Voltage Input Circuitry CAREFSW RAREF, OnVAREFx VAREF

Data Sheet 112 V1.1, 2010-08

4.2.3.1 ADC Conversion Timing

Conversion time, tC = tADC × ( 1 + r × ( 3+n+S T C ) ) , w h e r e r=C T C+2 f o r C T C=0 0B, 01B or 10B, r = 32 for CTC = 11B, CTC = Conversion Time Control (GLOBCTR.CTC), STC = Sample Time Control (INPCR0.STC), n = 8 or 10 (for 8-bit and 10-bit conversion respectively), tADC =1/ fADC

Data Sheet 113 V1.1, 2010-08

4.2.4 Power Supply Current

Table 41 and Table 42 provide the characteristics of the power supply current in the SAA-XC886. Table 41 Power Supply Curre nt Parameters (Operating Conditions apply; VDDP = 5V range) Parameter Symbol Limit Va lues Unit Test Condition typ.1) 1) The typical IDDP values are periodically measured at TA =+2 5 °C and VDDP =5 . 0V . max.2) 2)The maximum IDDP values are measured under worst case conditions (TA = + 140 °C and VDDP =5 . 5V ) . VDDP = 5V Range Active Mode IDDP 26.9 31.9 mA 3) 3) IDDP (active mode) is measured with: CPU clock and inpu t clock to all peripherals running at 24 MHz(set by on-chip oscillator of 9.6 MHz and NDIV in PLL_CON to 1001B), RESET = VDDP, no load on ports. Idle Mode IDDP 20.3 24.4 mA 4) 4) IDDP (idle mode) is measured with: CPU clock disabled, watchdog timer disabled, input clock to all peripherals enabled and running at 24 MHz, RESET = VDDP, no load on ports. Active Mode with slow-down enabled IDDP 13.7 17.0 mA 5) 5) IDDP (active mode with slow-down mode) is measured with: CPU clock and input clock to all peripherals running at 8 MHz by setting CLKREL in CMCON to 0110B, RESET = VDDP, no load on ports. Idle Mode with slow-down enabled IDDP 11.4 14.2 mA 6) 6) IDDP (idle mode with slow-down mode) is measured with: CPU clock disabled, watchdog timer disabled, input clock to all peripherals enabled and running at 8 MHz by setting CLKREL in CMCON to 0110B, RESET = VDDP, no load on ports.

Data Sheet 114 V1.1, 2010-08 Table 42 Power Down Current (O perating Conditions apply; VDDP = 5V range) Parameter Symbol Limit Va lues Unit Test Condition typ.1) 1) The typical IPDP values are measured at VDDP =5 . 0V . max.2) 2) The maximum IPDP values are measured at VDDP =5 . 5V . VDDP = 5V Range Power-Down Mode IPDP 11 0 μA TA =+2 5 °C3)4) 3)IPDP has a maximum value of 400 μA at TA = + 140 °C. 4) IPDP is measured with: RESET = VDDP, VAGND= VSS, RXD/INT0 = VDDP; rest of the ports are programmed to be input with either internal pull devices enabled or driven externally to ensure no floating inputs. 5) Not subjected to production test, verified by design/characterization.

Data Sheet 115 V1.1, 2010-08

4.3 AC Parameters

The electrical characteristics of the AC Parameters are detailed in this section.

4.3.1 Testing Waveforms

The testing waveforms for rise /fall time, output delay an d output high impedance are shown in Figure 39, Figure 40 and Figure 41. Figure 39 Rise/Fall Time Parameters Figure 40 Testing Waveform, Output Delay Figure 41 Testing Waveform, Output High Impedance 10% 90% 10% 90% VSS VDDP tR tF VDDE / 2 Test Points VDDE / 2 VSS VDDP VLoad + 0.1 V VOH - 0.1 VTiming Reference PointsVLoad - 0.1 V VOL - 0.1 V

Data Sheet 116 V1.1, 2010-08

4.3.2 Output Rise/Fall Times

Table 43 provides the characteristics of the output rise/fall times in the SAA-XC886. Figure 42 Rise/Fall Times Parameters Table 43 Output Rise/Fall Times Parame ters (Operating Conditions apply) Parameter Symbol Limit Values Unit Test Conditions min. max. VDDP = 5V Range Rise/fall times t R, tF –1 0 n s 2 0 p F . 1)2)3) 1) Rise/Fall time measurements are taken with 10% - 90% of pad supply. 2) Not all parameters are 100% tested, but are verified by design/characterization and test correlation. 3) Additional rise/fall time valid for CL = 20pF - 100pF @ 0.125 ns/pF. tR 10% 90% 10% 90% tF VSS VDDP

Data Sheet 117 V1.1, 2010-08

4.3.3 Power-on Reset and PLL Timing

Table 47 provides the characteristics of the power-on reset and PLL timing in the SAA- XC886. Table 44 Power-On Reset and PLL Timi ng (Operating Conditions apply) Parameter Symbol Limit Values Unit Test Conditions min. typ. max. Pad operating voltage VPAD CC 2.3 – – V 1) 1) Not all parameters are 100% tested, but are verified by design/characterization and test correlation. On-Chip Oscillator start-up time tOSCST CC – – 500 ns 1) Flash initialization time tFINIT CC – 160 – μs 1) RESET hold time tRST SR – 500 – μs VDDP rise time (10% – 90%) ≤ 500μs1)2) 2) RESET signal has to be active (low) until VDDC has reached 90% of its maximum value (typ. 2.5 V). PLL lock-in in time tLOCK CC – – 200 μs 1) PLL accumulated jitter DP ––0 . 7 n s 1)3) 3) PLL lock at 96 MHz using a 4 MHz external oscillator. The PLL Divider settings are K = 2, N = 48 and P = 1.

Data Sheet 118 V1.1, 2010-08 Figure 43 Power-on Reset Timing VDDP Pads VDDC VPAD OSC tOSCST PLL Reset Initialization Ready to ReadFlash State PLL unlock PLL lock 2) 3) tLOCK tFINIT 1)Pad state undefined 2)ENPS control 3)As Programmed I)until EVR is stable II)until PLL is locked III) until Flash go to Ready-to-Read IV) CPU reset is released; Boot ROM software begin execution RESET tRST

Data Sheet 119 V1.1, 2010-08

4.3.4 On-Chip Oscillator Characteristics

Table 45 provides the characteristics of the on-chip oscillator in the SAA-XC886. Table 45 On-chip Oscillator Characteri stics (Operating Conditions apply) Parameter Symbol Limit Values Unit Test Conditions min. typ. max. Nominal frequency fNOM CC 9.36 9.6 9.84 MHz under nominal conditions1) 1) Nominal condition: VDDC =2 . 5V , TA =+2 5 °C. Long term frequency deviation ΔfLT CC 0 – 6.0 % with respect to fNOM, over lifetime and temperature (125°C to 140°C), for one given device after trimming -5.0 – 5.0 % with respect to fNOM, over lifetime and temperature (-10°C to 125°C), for one given device after trimming -6.0 – 0 % with respect to fNOM, over lifetime and temperature (-40°C to -10°C), for one given device after trimming Short term frequency deviation ΔfST CC -1.0 – 1.0 % within one LIN message

Data Sheet 120 V1.1, 2010-08

4.3.5 External Clock Drive XTAL1

Table 46 shows the parameters th at define the external clock supply for SAA-XC886. These timing parameters are bas ed on the direct XTAL1 dr ive of clock input signals. They are not applicable if an external crystal or ceramic resonator is considered. Figure 44 External Clock Drive XTAL1 Table 46 External Clock Drive Character istics (Operating Conditions apply) Parameter Symbol Limit Values Unit Test Conditions Min. Max. Oscillator period tosc SR 83.3 250 ns 1)2) 1) The clock input signals with 45-55% duty cycle are used. 2) Not all parameters are 100% tested, but are verified by design/characterization and test correlation. High time t1 SR 25 - ns 2)3) 3) The clock input signal must reach the defined levels VILX and VIHX. Low time t2 SR 25 - ns 2)3) Rise time t3 SR - 20 ns 2)3) Fall time t4 SR - 20 ns 2)3) t3 t4 tOSC

0.5 VDDC

Data Sheet 121 V1.1, 2010-08

4.3.6 JTAG Timing

Table 47 provides the characteristics of the JTAG timing in the SAA-XC886. Figure 45 TCK Clock Timing Table 47 TCK Clock Timing (Operating Conditions apply; CL = 50 pF) Parameter Symbol Limits Unit Test Conditions min max TCK clock period tTCK SR 50 - ns 1) 1) Not all parameters are 100% tested, but are verified by design/characterization and test correlation. TCK high time t1 SR 20 − ns 1) TCK low time t2 SR 20 - ns 1) TCK clock rise time t3 SR - 4 ns 1) TCK clock fall time t4 SR - 4 ns 1) Table 48 JTAG Timing (Operating Conditions apply; CL = 50 pF) Parameter Symbol Limits Unit Test Conditionsmin max TMS setup to TCK t1 SR 8 - ns 1) TMS hold to TCK t2 SR 24 - ns 1) TDI setup to TCK t1 SR 11 - ns 1) TDI hold to TCK t2 SR 24 - ns 1) TDO valid output from TCK t3 CC - 27 ns 1) TCK

0.9 VDDP

0.1 VDDP

0.5 VDDP

Data Sheet 122 V1.1, 2010-08 Figure 46 JTAG Timing TDO high impedance to valid output from TCK t4 CC - 35 ns 1) TDO valid output to high impedance from TCK t5 CC - 27 ns 1) 1) Not all parameters are 100% tested, but are verified by design/characterization and test correlation. Table 48 JTAG Timing (Operating Conditions apply; CL = 50 pF) (cont’d) Parameter Symbol Limits Unit Test Conditionsmin max TMS TDI TCK TDO t4 t3 t5

Data Sheet 123 V1.1, 2010-08

4.3.7 SSC Master Mode Timing

Table 49 provides the characteristics of the SSC timing in the SAA-XC886. Figure 47 SSC Master Mode Timing Table 49 SSC Master Mode Timing (Ope rating Conditions apply; CL = 50 pF) Parameter Symbol Limit Values Unit Test Conditionsmin. max. SCLK clock period t0 CC 2*T SSC –n s 1)2) 1) T SSCmin =T CPU =1 / fCPU. When fCPU = 24 MHz, t0 = 83.3ns. TCPU is the CPU clock period. 2) Not all parameters are 100% tested, but are verified by design/characterization and test correlation. MTSR delay from SCLK t1 CC 0 8 ns 2) MRST setup to SCLK t2 SR 24 – ns 2) MRST hold from SCLK t3 SR 0 – ns 2) SSC_Tmg1 SCLK1) MTSR1) t1 t1 MRST1) Data valid 1) This timing is based on the following setup: CON.PH = CON.PO = 0.

Package and Quality Declaration Data Sheet 124 V1.1, 2010-08

5 Package and Quality Declaration

Chapter 5 provides the information of the SAA-XC886 package and reliability section.

5.1 Package Parameters

Table 50 provides the thermal characteristics of the package used in SAA-XC886. Table 50 Thermal Characteristics of the Packages Parameter Symbol Limit Values Unit Notes Min. Max. PG-TQFP-48 Thermal resistance junction case RTJC CC - 11.6 K/W 1)2) 1) The thermal resistances between the case and the ambient ( RTCA) , the lead and the ambient (RTLA) are to be combined with the thermal resistances between the junction and the case ( RTJC), the junction and the lead (RTJL) given above, in order to calculate the total thermal resistance between the junction and the ambient (RTJA). The thermal resistances between the case and the ambient ( RTCA), the lead and the ambient ( RTLA) depend on the external system (PCB, case) characteristics, and are under user responsibility. The junction temperature can be calculated using the following equation: TJ=TA+RTJA ×PD, where the RTJA is the total thermal resistance between the junction and the ambient. This total junction ambient resistance RTJA can be obtained from the upper four partial thermal resistances, by a) simply adding only the two thermal resistances (junction lead and lead ambient), or b) by taking all four resistances into account, depending on the precision needed. 2) Not all parameters are 100% tested, but are verified by design/characterization and test correlation. Thermal resistance junction lead RTJL CC - 33.2 K/W 1)2)

Package and Quality Declaration Data Sheet 125 V1.1, 2010-08

5.2 Package Outline

Figure 48 shows the package outlines of the SAA-XC886. Figure 48 PG-TQFP-48 Package Outline Index Marking 0.22 71) 0.2 0.2 A-BM0.08 A D B ±0.05 GPP09237 0.5 5.5 0.1 C ±0.05 D 48xC 48x H A-B A-B D D 1.2 MAX. 0.08 1±0.05 H 0.125 +0.075 ±0.150.6 MAX.7˚ -0.035 1) Does not include plastic or metal protrusion of 0.25 max. per side 2) Does not include dambar protrusion of 0.08 max. per side

Package and Quality Declaration Data Sheet 126 V1.1, 2010-08

5.3 Quality Declaration

Table 51 shows the characteristics of the quality parameters in the SAA-XC886. Table 51 Quality Parameters Parameter Symbol Limit Values Unit Notes Min. Typ. Max. Operation Lifetime when the device is used at the four stated TA 1) 1) This lifetime refers only to the time when the device is powered-on. tOP - - 1500 hours TA = 140°C2) 2) Not all parameters are 100% tested, but are verified by design/characterization and test correlation. - - 2000 hours TA = 125°C2) - - 10000 hours TA = 85°C2) - - 1500 hours TA = -40°C2) Operation Lifetime when the device is used at the two stated TA tOP2 - - 18000 hours TA = 108°C2) - - 130000 hours TA = 27°C2) Weighted Average Temperature3) 3) This parameter is derived based on the Arrhenius model. TWA - 106 - °C For 15000 hours 2) ESD susceptibility according to Human Body Model (HBM) for all pins VHBM - - 2000 V Conforming to EIA/JESD22- A114-B2) ESD susceptibility according to Charged Device Model (CDM) pins VCDM - - 750 V Conforming to JESD22-C101-C2)

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