S9408

S9408S SUMMIT | Alldatasheet

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© SUMMIT MICROELECTRONICS, Inc. 2000 • 300 Orchard City Drive, Suite 131  Campbell, CA 95008  Phone 408-378-6461  Fax 408-378-6586  www.summitmicro.com 2015 2.2 8/2/00Characteristics subject to change without notice SUMMIT MICROELECTRONICS, Inc.

FEATURES

• Four 8-Bit DACS – Differential Non-linearity - ±0.5LSB max – Integral Non-Linearity - ±1LSB max  Each DAC has Independent Reference Inputs – Output Buffer Amplifiers Swing Rail-to-Rail – Ground to VDD Reference Input Range  Each DAC’s Digital Input Data Maintained in Nonvolatile EEPROM  Power-On Reset Reloads Registers with Nonvolatile Data  Simple Serial Interface for Reading and Writing DAC values, SPI™ and QSPI™ compatible.  Fully operational from 2.7V to 5.5V  Low Power: <1mW @ 2.7V Serial Input, Quad 8-Bit Nonvolatile DACPOT™ S9408 OVERVIEW The S9408 DACPOT™ is a serial input, voltage output, quad 8-bit digital to analog converter. The S9408 oper- ates from a single +2.7V to +5.5V supply. Internal preci- sion buffers swing rail-to-rail and the reference input range includes both ground and the positive supply. The S9408 integrates four 8-bit DACs and their associ- ated circuits which include an enhanced unity-gain opera- tional amplifier output, an 8-bit data latch, an 8-bit non- volatile register, and an industry-standard serial interface for reading and writing data to the DACs’ data latches and registers. The DACs are independently programmable and each has its own electrically isolated Vreference inputs. FUNCTIONAL BLOCK DIAGRAM VREFH0 VOUT018 8-Bit E2PROM 8-Bit Data Register Serial Data In Serial Data Out 8-Bit DAC AMPVDD 3 RDY/BSY# 4 VREFL0 CS# DI 7 00/REG# CLK 5 VREFH1 VOUT117 VREFL112 VREFH2 VOUT216 VREFL213 VREFH3 VOUT315 VREFL314 DAC SECTION 0 DAC SECTION 1 DAC SECTION 2 DAC SECTION 3 DO8 Memory Control Programming Memory Controller Control Logic GND 10 2015 T BD 2.0

2015 2.2 8/2/00 SUMMIT MICROELECTRONICS, Inc. The analog outputs of the S9408 can be programmed to any one of 256 individual voltage steps. Each step value is 1/256 th of the voltage differential between VREFH and VREFL of the respective DAC. Once programmed these settings can be retained in nonvolatile memory during all power conditions and will be automatically recalled upon a power-up sequence. Each DAC can be independently read without affecting the output voltage during the read cycle. In addition, each output can be adjusted an unlim- ited number of times without altering the value stored in the nonvolatile memory. DEVICE OPERATION Analog Section The S9804 is an 8-bit, voltage output digital-to-analog converter (DAC). The DAC consists of a resistor network that converts 8-bit digital inputs into equivalent analog output voltages in proportion to the applied reference voltage. Reference inputs The voltage differential between the V REFL and VREFH inputs sets the full-scale output voltage for its respective DAC. V REFL must be equal to or greater than ground (positive voltage). VREFH must be greater (more positive) than VREFL and less than or equal to VDD . PINOUT and SIGNAL DEFINITION Pin Name Function 1, 2 V REFH Vreference High: 20, 19 V REFL < VREFH - VDD 3V DD Power Supply Voltage

4 RDY/BSY# Ready/Busy: open drain output

indicating status of nonvolatile write operations

5 CLK Clock Input Pin: used for serial

6 CS# Chip Select: When high deselects

the device and places it in a low power mode

7 DI Data Input: serial data input pin

8 DO Data Output: serial data output pin

9 00/REG# Power On Recall Option Input

10 GND Power Supply Ground

11, 12 VREFL Vreference Low: 13, 14 V REFH > VREFL  GND 15, 16 VOUT DAC Output: buffered D to A 17, 18 converter output Output Buffer Amplifiers The voltage outputs are precision unity-gain followers that slew up to 1V/µs. The outputs can swing from V REFL to VREFH . With a 0V to 5V output transition the amplifier outputs typically settle to 1LSB in 40µs. DIGITAL INTERFACE The S9408 employs a common 4-wire serial interface. It is comprised of a Clock (CLK), Chip Select (CS#), Data In (DI) and Data Out (DO). Data is clocked into the device on the clock’s rising edge and out of the device on the clock’s falling edge. Data is shifted in and out MSB first. DO only becomes active after the device has been selected and after a valid read command and address has been re- ceived. All data transfers are initiated after CS# goes low and a logic ‘1’ is clocked into the device. This first data transfer is the start bit and must precede all operations. Following the start bit are two command bits used to specify which of four commands to execute. The next two bits are the address bits used to select one of the four DACs. The action of the next eight clock cycles will be dependent upon the command issued. VREFH1 VREFH0 VDD RDY/BSY# CLK CS# DI DO 00/REG# GND VREFH2 VREFH3 VOUT0 VOUT1 VOUT2 VOUT3 VREFL3 VREFL2 VREFL1 VREFL0 2015 T PCon 2.0 20-Pin PDIP or 20-Pin SOIC

3SUMMIT MICROELECTRONICS, Inc. up or by executing the Recall command. can be used to make situational adjustments. conditions for a write operation. FIGURE 1. READ SEQUENCE TABLE 1. COMMAND FORMAT

110 A A t uOataD—daeR

111 A A l laceR

5SUMMIT MICROELECTRONICS, Inc. FIGURE 4. RECALL COMMAND SEQUENCE bus conditions for a Recall operation.

2015 2.2 8/2/00 SUMMIT MICROELECTRONICS, Inc. ABSOLUTE MAXIMUM RATINGS Stresses listed under Absolute Maximum Ratings may cause perma- nent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. RECOMMENDED OPERATING CONDITIONS Condition Min Max Temperature -40 °C +85 °C VDD +2.7V +5.5V 2015 PGM T2 1.2 lobmySr etemaraPn iMx aMt inU V PAZ ytilibitpecsuSDSE0 002V I HTL pu-hctaL0 01A m T RD noitneteRataD0 01s raeY N DNE ecnarudnE0 00,000,1s elcyCegarotS RELIABILITY CHARACTERISTICS (O ver recommended operating conditions unless otherwise specified) DC ELECTRICAL CHARACTERISTICS (O ver recommended operating conditions unless otherwise specified) lobmySr etemaraPs noitidnoCn iMp yTx aMt inU IDD erotsgnirudtnerrucylppuS )1eton( V=SC LI 8.15 .2A m IBS tnerrucylppusybdnatSV =SC HI 0620 05A µ IHI tnerrucegakaeltupnIV NI V= DD 1<0 1A µ ILI tnerrucegakaeltupnIV NI V0=1 <0 1– Aµ V HI egatlovtupnilevelhgiH2 V DD V V LI egatlovtupnilevelwoL0 8 .0V V HO egatlovtuptuolevelhgiHA µ004–=HOIV DD 3.0– V V LO egatlovtuptuolevelwoL ,Am1=LOIV DD ;V5= ,Am4.0=LOIV DD V7.2= 4.0V Note 1: IDD is the supply current drawn while the EEPROM is being updated. 3.0

7SUMMIT MICROELECTRONICS, Inc. FIGURE 5. AC TIMING DIAGRAM Notes: 1. All timing measurements are defined at the point of signal crossing VDD /2.

2015 2.2 8/2/00 SUMMIT MICROELECTRONICS, Inc. DAC DC ELECTRICAL CHARACTERISTICS VDD = 2.7V to 5.5V, VREFH = VDD , VREFL = 0V, TA = -40°C to +85°C, unless otherwise specified ytreporPl obmySr etemaraPs noitidnoCn iMp yTx aMt inU ycaruccA LNIy tiraenil-nonlargetnII DAOL Aµ001=5 .01 ±B SL LNDy tiraenil-nonlaitnereffiDI DAOL )1eton(Aµ001=1 .05 .0±B SL secnerefeR V HFER egatlovtupnIV LFER V DD V V LFER egatlovtupnID NGV hFER V R NI V HFER Vot LFER ecnatsiserk 04 Ω RCT NI Rfotneiciffeoc.pmeT NI 0030 06C º/mpp ∆R NI hctamecnatsisertupnI5 .0±1 ±% golanA tuptuO G SFE rorreniagelacs-lluFF F=D XEH 1±B SL V TUO SZe gatlovtesffotuptuO0 0=D XEH 05 .25 V m VCT TUO V TUO tneiceiffeoc.pmet V DD I,V5= DAOL Aµ05= )1eton( 05C º/Vµ IL tnerrucdaoltuptuopmA0 02– 0001A µ R TUO ecnatsisertuptuopmA I DAOL Aµ001=V 5 Ω Ω RRSPn oitcejerylppusrewoPI DAOL Aµ01=1 V /BSL tS BSL1otemitgnilttesCAD Fp01V 5 V3Fp01 sµ sµ eN esiontuptuopmAV ,zHk1=f DD V5=0 9V n √ zH DHTn oitrotsidcinomrahlatoT V HFER V,V5.2= DD ,V5= V,zHk1=f NI V1= SMR 80.0% WBB d3–htdiwdnaB V HFER V,V5.2= DD ,V5= V NI Vm001= SMR 003z Hk Note 1: Guaranteed but not tested

9SUMMIT MICROELECTRONICS, Inc. FIGURE 6. VL to VH END-TO-END RESISTANCE

39.0 RESISTANCE (k Ω )

2015 2.2 8/2/00 SUMMIT MICROELECTRONICS, Inc.

ORDERING INFORMATION

SUMMIT Microelectronics, Inc. reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. SUMMIT Microelectronics, Inc. assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained herein reflect representative operating parameters, and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked, SUMMIT Microelectronics, Inc. shall not be liable for any damages arising as a result of any error or omission. SUMMIT Microelectronics, Inc. does not recommend the use of any of its products in life support or aviation applications where the failure or malfunction of the product can reasonably be expected to cause any failure of either system or to significantly affect their safety or effectiveness. Products are not authorized for use in such applications unless SUMMIT Microelectronics, Inc. receives written assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and (c) potential liability of SUMMIT Microelectronics, Inc. is adequately protected under the circumstances. © Copyright 2000 SUMMIT Microelectronics, Inc. Package P = 20 Pin PDIP S = 20 Pin SOIC S9408 P Base Part Number 2015 Tree 2.0 *Special order